diff options
Diffstat (limited to 'arch/mips/pci/pci-ocelot-g.c')
| -rw-r--r-- | arch/mips/pci/pci-ocelot-g.c | 97 |
1 files changed, 0 insertions, 97 deletions
diff --git a/arch/mips/pci/pci-ocelot-g.c b/arch/mips/pci/pci-ocelot-g.c deleted file mode 100644 index 1e3430154fa..00000000000 --- a/arch/mips/pci/pci-ocelot-g.c +++ /dev/null | |||
| @@ -1,97 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) | ||
| 7 | * | ||
| 8 | * This doesn't really fly - but I don't have a GT64240 system for testing. | ||
| 9 | */ | ||
| 10 | #include <linux/init.h> | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/types.h> | ||
| 13 | #include <linux/pci.h> | ||
| 14 | #include <asm/gt64240.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * We assume these address ranges have been programmed into the GT-64240 by | ||
| 18 | * the firmware. PMON in case of the Ocelot G does that. Note the size of | ||
| 19 | * the I/O range is completly stupid; I/O mappings are limited to at most | ||
| 20 | * 256 bytes by the PCI spec and deprecated; and just to make things worse | ||
| 21 | * apparently many devices don't decode more than 64k of I/O space. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #define gt_io_size 0x20000000UL | ||
| 25 | #define gt_io_base 0xe0000000UL | ||
| 26 | |||
| 27 | static struct resource gt_pci_mem0_resource = { | ||
| 28 | .name = "MV64240 PCI0 MEM", | ||
| 29 | .start = 0xc0000000UL, | ||
| 30 | .end = 0xcfffffffUL, | ||
| 31 | .flags = IORESOURCE_MEM | ||
| 32 | }; | ||
| 33 | |||
| 34 | static struct resource gt_pci_io_mem0_resource = { | ||
| 35 | .name = "MV64240 PCI0 IO MEM", | ||
| 36 | .start = 0xe0000000UL, | ||
| 37 | .end = 0xefffffffUL, | ||
| 38 | .flags = IORESOURCE_IO | ||
| 39 | }; | ||
| 40 | |||
| 41 | static struct mv_pci_controller gt_bus0_controller = { | ||
| 42 | .pcic = { | ||
| 43 | .pci_ops = &mv_pci_ops, | ||
| 44 | .mem_resource = >_pci_mem0_resource, | ||
| 45 | .mem_offset = 0xc0000000UL, | ||
| 46 | .io_resource = >_pci_io_mem0_resource, | ||
| 47 | .io_offset = 0x00000000UL | ||
| 48 | }, | ||
| 49 | .config_addr = PCI_0CONFIGURATION_ADDRESS, | ||
| 50 | .config_vreg = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER, | ||
| 51 | }; | ||
| 52 | |||
| 53 | static struct resource gt_pci_mem1_resource = { | ||
| 54 | .name = "MV64240 PCI1 MEM", | ||
| 55 | .start = 0xd0000000UL, | ||
| 56 | .end = 0xdfffffffUL, | ||
| 57 | .flags = IORESOURCE_MEM | ||
| 58 | }; | ||
| 59 | |||
| 60 | static struct resource gt_pci_io_mem1_resource = { | ||
| 61 | .name = "MV64240 PCI1 IO MEM", | ||
| 62 | .start = 0xf0000000UL, | ||
| 63 | .end = 0xffffffffUL, | ||
| 64 | .flags = IORESOURCE_IO | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct mv_pci_controller gt_bus1_controller = { | ||
| 68 | .pcic = { | ||
| 69 | .pci_ops = &mv_pci_ops, | ||
| 70 | .mem_resource = >_pci_mem1_resource, | ||
| 71 | .mem_offset = 0xd0000000UL, | ||
| 72 | .io_resource = >_pci_io_mem1_resource, | ||
| 73 | .io_offset = 0x10000000UL | ||
| 74 | }, | ||
| 75 | .config_addr = PCI_1CONFIGURATION_ADDRESS, | ||
| 76 | .config_vreg = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER, | ||
| 77 | }; | ||
| 78 | |||
| 79 | static __init int __init ocelot_g_pci_init(void) | ||
| 80 | { | ||
| 81 | unsigned long io_v_base; | ||
| 82 | |||
| 83 | if (gt_io_size) { | ||
| 84 | io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size); | ||
| 85 | if (!io_v_base) | ||
| 86 | panic("Could not ioremap I/O port range"); | ||
| 87 | |||
| 88 | set_io_port_base(io_v_base); | ||
| 89 | } | ||
| 90 | |||
| 91 | register_pci_controller(>_bus0_controller.pcic); | ||
| 92 | register_pci_controller(>_bus1_controller.pcic); | ||
| 93 | |||
| 94 | return 0; | ||
| 95 | } | ||
| 96 | |||
| 97 | arch_initcall(ocelot_g_pci_init); | ||