Merge branch 'linux-2.6' into for-linus

7 files changed, 25 insertions, 43 deletions

diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index be624b8c3b0..43dba6ce660 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -62,16 +62,6 @@ void enable_atlas_irq(unsigned int irq_nr)
         iob();
 }
 
-static unsigned int startup_atlas_irq(unsigned int irq)
-{
-        enable_atlas_irq(irq);
-        return 0; /* never anything pending */
-}
-
-#define shutdown_atlas_irq      disable_atlas_irq
-
-#define mask_and_ack_atlas_irq disable_atlas_irq
-
 static void end_atlas_irq(unsigned int irq)
 {
         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -80,11 +70,11 @@ static void end_atlas_irq(unsigned int irq)
 
 static struct irq_chip atlas_irq_type = {
         .typename = "Atlas",
-        .startup = startup_atlas_irq,
-        .shutdown = shutdown_atlas_irq,
-        .enable = enable_atlas_irq,
-        .disable = disable_atlas_irq,
-        .ack = mask_and_ack_atlas_irq,
+        .ack = disable_atlas_irq,
+        .mask = disable_atlas_irq,
+        .mask_ack = disable_atlas_irq,
+        .unmask = enable_atlas_irq,
+        .eoi = enable_atlas_irq,
         .end = end_atlas_irq,
 };
 
@@ -217,13 +207,8 @@ static inline void init_atlas_irqs (int base)
          */
         atlas_hw0_icregs->intrsten = 0xffffffff;
 
-        for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) {
-                irq_desc[i].status      = IRQ_DISABLED;
-                irq_desc[i].action      = 0;
-                irq_desc[i].depth       = 1;
-                irq_desc[i].chip        = &atlas_irq_type;
-                spin_lock_init(&irq_desc[i].lock);
-        }
+        for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++)
+                set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq);
 }
 
 static struct irqaction atlasirq = {
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
index be80c5dd4a0..eeed944e0f8 100644
--- a/arch/mips/mips-boards/generic/memory.c
+++ b/arch/mips/mips-boards/generic/memory.c
@@ -176,7 +176,7 @@ unsigned long __init prom_free_prom_memory(void)
                 if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
                         continue;
 
-                addr = boot_mem_map.map[i].addr;
+                addr = PAGE_ALIGN(boot_mem_map.map[i].addr);
                 while (addr < boot_mem_map.map[i].addr
                               + boot_mem_map.map[i].size) {
                         ClearPageReserved(virt_to_page(__va(addr)));
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index 9337f6c8873..3192a14698c 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -90,7 +90,7 @@ static struct pci_controller msc_controller = {
 void __init mips_pcibios_init(void)
 {
         struct pci_controller *controller;
-        unsigned long start, end, map, start1, end1, map1, map2, map3, mask;
+        resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;
 
         switch (mips_revision_corid) {
         case MIPS_REVISION_CORID_QED_RM5261:
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 6f8a9fe7c1e..e4604c73f02 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -187,7 +187,7 @@ out:
 }
 
 /*
- * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
+ * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
  */
 static unsigned int __init estimate_cpu_frequency(void)
 {
@@ -208,7 +208,8 @@ static unsigned int __init estimate_cpu_frequency(void)
                 count = 6000000;
 #endif
 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
-        unsigned int flags;
+        unsigned long flags;
+        unsigned int start;
 
         local_irq_save(flags);
 
@@ -217,13 +218,13 @@ static unsigned int __init estimate_cpu_frequency(void)
         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 
         /* Start r4k counter. */
-        write_c0_count(0);
+        start = read_c0_count();
 
         /* Read counter exactly on falling edge of update flag */
         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 
-        count = read_c0_count();
+        count = read_c0_count() - start;
 
         /* restore interrupts */
         local_irq_restore(flags);
@@ -287,6 +288,7 @@ void __init plat_timer_setup(struct irqaction *irq)
            The effect is that the int remains disabled on the second cpu.
            Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
         irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
+        set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
 #endif
 
         /* to generate the first timer interrupt */
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 6244d0e2c7d..90ad5bf3e2f 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -32,6 +32,7 @@
 #include <asm/i8259.h>
 #include <asm/irq_cpu.h>
 #include <asm/io.h>
+#include <asm/irq_regs.h>
 #include <asm/mips-boards/malta.h>
 #include <asm/mips-boards/maltaint.h>
 #include <asm/mips-boards/piix4.h>
@@ -131,7 +132,7 @@ static void corehi_irqdispatch(void)
         unsigned int intedge, intsteer, pcicmd, pcibadaddr;
         unsigned int pcimstat, intisr, inten, intpol;
         unsigned int intrcause,datalo,datahi;
-        struct pt_regs *regs;
+        struct pt_regs *regs = get_irq_regs();
 
         printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
         printk("epc   : %08lx\nStatus: %08lx\n"
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index ab460f805be..282f3e52eea 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -159,7 +159,7 @@ void __init plat_mem_setup(void)
                                 BONITO_PCIMEMBASECFG |=
                                         (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
                                          BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
-                                printk("Disabled Bonito IOBC coherency\n");
+                                printk("Enabled Bonito IOBC coherency\n");
                         }
                 }
                 else
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c
index c566b9bd042..30711d016fe 100644
--- a/arch/mips/mips-boards/sim/sim_time.c
+++ b/arch/mips/mips-boards/sim/sim_time.c
@@ -3,31 +3,24 @@
 #include <linux/kernel_stat.h>
 #include <linux/sched.h>
 #include <linux/spinlock.h>
-
-#include <asm/mipsregs.h>
-#include <asm/ptrace.h>
-#include <asm/hardirq.h>
-#include <asm/div64.h>
-#include <asm/cpu.h>
-#include <asm/time.h>
-
 #include <linux/interrupt.h>
 #include <linux/mc146818rtc.h>
 #include <linux/timex.h>
+
 #include <asm/mipsregs.h>
+#include <asm/ptrace.h>
 #include <asm/hardirq.h>
-#include <asm/irq.h>
 #include <asm/div64.h>
 #include <asm/cpu.h>
 #include <asm/time.h>
+#include <asm/irq.h>
 #include <asm/mc146818-time.h>
 #include <asm/msc01_ic.h>
+#include <asm/smp.h>
 
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/prom.h>
 #include <asm/mips-boards/simint.h>
-#include <asm/mc146818-time.h>
-#include <asm/smp.h>
 
 
 unsigned long cpu_khz;
@@ -102,7 +95,7 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
 
 
 /*
- * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
+ * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
  */
 static unsigned int __init estimate_cpu_frequency(void)
 {
@@ -203,7 +196,8 @@ void __init plat_timer_setup(struct irqaction *irq)
            on seperate cpu's the first one tries to handle the second interrupt.
            The effect is that the int remains disabled on the second cpu.
            Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
-        irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
+        irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;
+        set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
 #endif
 
         /* to generate the first timer interrupt */