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-rw-r--r--arch/mips/mips-boards/generic/time.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 6f8a9fe7c1e..e4604c73f02 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -187,7 +187,7 @@ out:
187} 187}
188 188
189/* 189/*
190 * Estimate CPU frequency. Sets mips_counter_frequency as a side-effect 190 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
191 */ 191 */
192static unsigned int __init estimate_cpu_frequency(void) 192static unsigned int __init estimate_cpu_frequency(void)
193{ 193{
@@ -208,7 +208,8 @@ static unsigned int __init estimate_cpu_frequency(void)
208 count = 6000000; 208 count = 6000000;
209#endif 209#endif
210#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA) 210#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
211 unsigned int flags; 211 unsigned long flags;
212 unsigned int start;
212 213
213 local_irq_save(flags); 214 local_irq_save(flags);
214 215
@@ -217,13 +218,13 @@ static unsigned int __init estimate_cpu_frequency(void)
217 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 218 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
218 219
219 /* Start r4k counter. */ 220 /* Start r4k counter. */
220 write_c0_count(0); 221 start = read_c0_count();
221 222
222 /* Read counter exactly on falling edge of update flag */ 223 /* Read counter exactly on falling edge of update flag */
223 while (CMOS_READ(RTC_REG_A) & RTC_UIP); 224 while (CMOS_READ(RTC_REG_A) & RTC_UIP);
224 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP)); 225 while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
225 226
226 count = read_c0_count(); 227 count = read_c0_count() - start;
227 228
228 /* restore interrupts */ 229 /* restore interrupts */
229 local_irq_restore(flags); 230 local_irq_restore(flags);
@@ -287,6 +288,7 @@ void __init plat_timer_setup(struct irqaction *irq)
287 The effect is that the int remains disabled on the second cpu. 288 The effect is that the int remains disabled on the second cpu.
288 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ 289 Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
289 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; 290 irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
291 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
290#endif 292#endif
291 293
292 /* to generate the first timer interrupt */ 294 /* to generate the first timer interrupt */