Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable

22 files changed, 1664 insertions, 303 deletions

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index de4fa992fc3..83ee08847d4 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,5 +1,6 @@
 if ARCH_MX5
-# ARCH_MX51 and ARCH_MX50 are left for compatibility
+# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single
+# image. So for most time, SOC_IMX50/51/53 should be used.
 
 config ARCH_MX50
         bool
@@ -50,6 +51,7 @@ config MACH_MX51_BABBAGE
 config MACH_MX51_3DS
         bool "Support MX51PDK (3DS)"
         select SOC_IMX51
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -112,19 +114,32 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
 
 endchoice
 
-config MACH_MX51_EFIKAMX
-        bool "Support MX51 Genesi Efika MX nettop"
+config MX51_EFIKA_COMMON
+        bool
         select SOC_IMX51
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_SPI_IMX
+        select MXC_ULPI if USB_ULPI
+
+config MACH_MX51_EFIKAMX
+        bool "Support MX51 Genesi Efika MX nettop"
+        select MX51_EFIKA_COMMON
         help
           Include support for Genesi Efika MX nettop. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_MX51_EFIKASB
+        bool "Support MX51 Genesi Efika Smartbook"
+        select MX51_EFIKA_COMMON
+        help
+          Include support for Genesi Efika Smartbook. This includes specific
+          configurations for the board and its peripherals.
+
 config MACH_MX53_EVK
         bool "Support MX53 EVK platforms"
         select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -136,6 +151,8 @@ config MACH_MX53_EVK
 config MACH_MX53_SMD
         bool "Support MX53 SMD platforms"
         select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for MX53 SMD platform. This includes specific
@@ -144,7 +161,10 @@ config MACH_MX53_SMD
 config MACH_MX53_LOCO
         bool "Support MX53 LOCO platforms"
         select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         help
           Include support for MX53 LOCO platform. This includes specific
           configurations for the board and its peripherals.
@@ -157,6 +177,7 @@ config MACH_MX50_RDP
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_SPI_IMX
+        select IMX_HAVE_PLATFORM_FEC
         help
           Include support for MX50 reference design platform (RDP) board. This
           includes specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0d43be98e51..4f63048be3c 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Object file lists.
-obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o
+obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o
 obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
 
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
@@ -16,5 +16,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
+obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
 obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
+obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
 obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index f8652ef25f8..d0296a94c47 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -60,7 +60,6 @@
 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
 #define MX51_USB_PLL_DIV_24_MHZ         0x02
 
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
 static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
@@ -105,12 +104,9 @@ static struct platform_device serial_device = {
                 .platform_data = serial_platform_data,
         },
 };
-#endif
 
 static struct platform_device *devices[] __initdata = {
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
         &serial_device,
-#endif
 };
 
 static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
@@ -188,7 +184,10 @@ static int initialize_otg_port(struct platform_device *pdev)
         v |= MX51_USB_PLL_DIV_19_2_MHZ;
         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 }
 
 static int initialize_usbh1_port(struct platform_device *pdev)
@@ -206,13 +205,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
 static struct mxc_usbh_platform_data dr_utmi_config = {
         .init           = initialize_otg_port,
         .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 
 static struct fsl_usb2_platform_data usb_pdata = {
@@ -223,7 +225,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
 static struct mxc_usbh_platform_data usbh1_config = {
         .init           = initialize_usbh1_port,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 };
 
 static int otg_mode_host;
@@ -298,7 +299,8 @@ MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
         /* Maintainer: Eric Bénard <eric@eukrea.com> */
         .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
-        .init_machine = eukrea_cpuimx51_init,
         .timer = &mxc_timer,
+        .init_machine = eukrea_cpuimx51_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index ad931895d8b..29b180823bf 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -42,6 +42,7 @@
 
 #include "devices-imx51.h"
 #include "devices.h"
+#include "cpu_op-mx51.h"
 
 #define USBH1_RST               IMX_GPIO_NR(2, 28)
 #define ETH_RST                 IMX_GPIO_NR(2, 31)
@@ -109,7 +110,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
 
         /* Touchscreen */
         /* IRQ */
-        _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+        _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 };
@@ -118,15 +119,9 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static int ts_get_pendown_state(void)
-{
-        return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
-}
-
 static struct tsc2007_platform_data tsc2007_info = {
         .model                  = 2007,
         .x_plate_ohms           = 180,
-        .get_pendown_state      = ts_get_pendown_state,
 };
 
 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
@@ -167,7 +162,10 @@ static int initialize_otg_port(struct platform_device *pdev)
         v |= MX51_USB_PLL_DIV_19_2_MHZ;
         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 }
 
 static int initialize_usbh1_port(struct platform_device *pdev)
@@ -186,13 +184,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
                         usbother_base + MX51_USB_CTRL_1_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
 static struct mxc_usbh_platform_data dr_utmi_config = {
         .init           = initialize_otg_port,
         .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 
 static struct fsl_usb2_platform_data usb_pdata = {
@@ -203,7 +204,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
 static struct mxc_usbh_platform_data usbh1_config = {
         .init           = initialize_usbh1_port,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 };
 
 static int otg_mode_host;
@@ -242,7 +242,7 @@ static struct mcp251x_platform_data mcp251x_info = {
 static struct spi_board_info cpuimx51sd_spi_device[] = {
         {
                 .modalias        = "mcp2515",
-                .max_speed_hz    = 6500000,
+                .max_speed_hz    = 10000000,
                 .bus_num         = 0,
                 .mode           = SPI_MODE_0,
                 .chip_select     = 0,
@@ -269,6 +269,10 @@ static void __init eukrea_cpuimx51sd_init(void)
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 
+#if defined(CONFIG_CPU_FREQ_IMX)
+        get_cpu_op = mx51_get_cpu_op;
+#endif
+
         imx51_add_imx_uart(0, &uart_pdata);
         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
 
@@ -329,7 +333,8 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
         /* Maintainer: Eric Bénard <eric@eukrea.com> */
         .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
-        .init_machine = eukrea_cpuimx51sd_init,
         .timer = &mxc_timer,
+        .init_machine = eukrea_cpuimx51sd_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index fd32e4c450e..dedf7f2d6d0 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -35,7 +35,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
-#include "devices-mx50.h"
+#include "devices-imx50.h"
+
+#define FEC_EN          IMX_GPIO_NR(6, 23)
+#define FEC_RESET_B     IMX_GPIO_NR(4, 12)
 
 static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
         /* SD1 */
@@ -102,7 +105,7 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
         MX50_PAD_I2C3_SCL__USBOTG_OC,
 
         MX50_PAD_SSI_RXC__FEC_MDIO,
-        MX50_PAD_SSI_RXC__FEC_MDIO,
+        MX50_PAD_SSI_RXFS__FEC_MDC,
         MX50_PAD_DISP_D0__FEC_TXCLK,
         MX50_PAD_DISP_D1__FEC_RX_ER,
         MX50_PAD_DISP_D2__FEC_RX_DV,
@@ -111,7 +114,6 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
         MX50_PAD_DISP_D5__FEC_TX_EN,
         MX50_PAD_DISP_D6__FEC_TXD1,
         MX50_PAD_DISP_D7__FEC_TXD0,
-        MX50_PAD_SSI_RXFS__FEC_MDC,
         MX50_PAD_I2C3_SDA__GPIO_6_23,
         MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
 
@@ -168,6 +170,24 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
+static const struct fec_platform_data fec_data __initconst = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static inline void mx50_rdp_fec_reset(void)
+{
+        gpio_request(FEC_EN, "fec-en");
+        gpio_direction_output(FEC_EN, 0);
+        gpio_request(FEC_RESET_B, "fec-reset_b");
+        gpio_direction_output(FEC_RESET_B, 0);
+        msleep(1);
+        gpio_set_value(FEC_RESET_B, 1);
+}
+
+static const struct imxi2c_platform_data i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
 /*
  * Board specific initialization.
  */
@@ -178,6 +198,11 @@ static void __init mx50_rdp_board_init(void)
 
         imx50_add_imx_uart(0, &uart_pdata);
         imx50_add_imx_uart(1, &uart_pdata);
+        mx50_rdp_fec_reset();
+        imx50_add_fec(&fec_data);
+        imx50_add_imx_i2c(0, &i2c_data);
+        imx50_add_imx_i2c(1, &i2c_data);
+        imx50_add_imx_i2c(2, &i2c_data);
 }
 
 static void __init mx50_rdp_timer_init(void)
@@ -191,7 +216,8 @@ static struct sys_timer mx50_rdp_timer = {
 
 MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
         .map_io = mx50_map_io,
+        .init_early = imx50_init_early,
         .init_irq = mx50_init_irq,
-        .init_machine = mx50_rdp_board_init,
         .timer = &mx50_rdp_timer,
+        .init_machine = mx50_rdp_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 49d64484237..63dfbeafbc1 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -71,24 +71,10 @@ static iomux_v3_cfg_t mx51_3ds_pads[] = {
 };
 
 /* Serial ports */
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static inline void mxc_init_imx_uart(void)
-{
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-}
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* SERIAL_IMX */
-
-#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
 static int mx51_3ds_board_keymap[] = {
         KEY(0, 0, KEY_1),
         KEY(0, 1, KEY_2),
@@ -124,16 +110,6 @@ static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
         .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
 };
 
-static void mxc_init_keypad(void)
-{
-        imx51_add_imx_keypad(&mx51_3ds_map_data);
-}
-#else
-static inline void mxc_init_keypad(void)
-{
-}
-#endif
-
 static int mx51_3ds_spi2_cs[] = {
         MXC_SPI_CS(0),
         MX51_3DS_ECSPI2_CS,
@@ -157,11 +133,14 @@ static struct spi_board_info mx51_3ds_spi_nor_device[] = {
 /*
  * Board specific initialization.
  */
-static void __init mxc_board_init(void)
+static void __init mx51_3ds_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
                                         ARRAY_SIZE(mx51_3ds_pads));
-        mxc_init_imx_uart();
+
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
 
         imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
         spi_register_board_info(mx51_3ds_spi_nor_device,
@@ -172,7 +151,8 @@ static void __init mxc_board_init(void)
                                     "devices on the board are unusable.\n");
 
         imx51_add_sdhci_esdhc_imx(0, NULL);
-        mxc_init_keypad();
+        imx51_add_imx_keypad(&mx51_3ds_map_data);
+        imx51_add_imx2_wdt(0, NULL);
 }
 
 static void __init mx51_3ds_timer_init(void)
@@ -180,15 +160,16 @@ static void __init mx51_3ds_timer_init(void)
         mx51_clocks_init(32768, 24000000, 22579200, 0);
 }
 
-static struct sys_timer mxc_timer = {
-        .init   = mx51_3ds_timer_init,
+static struct sys_timer mx51_3ds_timer = {
+        .init = mx51_3ds_timer_init,
 };
 
 MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
         /* Maintainer: Freescale Semiconductor, Inc. */
         .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
-        .init_machine = mxc_board_init,
-        .timer = &mxc_timer,
+        .timer = &mx51_3ds_timer,
+        .init_machine = mx51_3ds_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 1d231e84107..b2ecd194e76 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -161,23 +161,10 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
 };
 
 /* Serial ports */
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static inline void mxc_init_imx_uart(void)
-{
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-}
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* SERIAL_IMX */
-
 static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
         .bitrate = 100000,
 };
@@ -272,7 +259,10 @@ static int initialize_otg_port(struct platform_device *pdev)
         v |= MX51_USB_PLL_DIV_19_2_MHZ;
         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 }
 
 static int initialize_usbh1_port(struct platform_device *pdev)
@@ -290,13 +280,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
         iounmap(usb_base);
-        return 0;
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
+                        MXC_EHCI_ITC_NO_THRESHOLD);
 }
 
 static struct mxc_usbh_platform_data dr_utmi_config = {
         .init           = initialize_otg_port,
         .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 
 static struct fsl_usb2_platform_data usb_pdata = {
@@ -307,7 +300,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
 static struct mxc_usbh_platform_data usbh1_config = {
         .init           = initialize_usbh1_port,
         .portsc = MXC_EHCI_MODE_ULPI,
-        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
 };
 
 static int otg_mode_host;
@@ -349,7 +341,7 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
 /*
  * Board specific initialization.
  */
-static void __init mxc_board_init(void)
+static void __init mx51_babbage_init(void)
 {
         iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
         iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
@@ -360,7 +352,11 @@ static void __init mxc_board_init(void)
 #endif
         mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
                                         ARRAY_SIZE(mx51babbage_pads));
-        mxc_init_imx_uart();
+
+        imx51_add_imx_uart(0, &uart_pdata);
+        imx51_add_imx_uart(1, &uart_pdata);
+        imx51_add_imx_uart(2, &uart_pdata);
+
         babbage_fec_reset();
         imx51_add_fec(NULL);
 
@@ -399,15 +395,16 @@ static void __init mx51_babbage_timer_init(void)
         mx51_clocks_init(32768, 24000000, 22579200, 0);
 }
 
-static struct sys_timer mxc_timer = {
-        .init   = mx51_babbage_timer_init,
+static struct sys_timer mx51_babbage_timer = {
+        .init = mx51_babbage_timer_init,
 };
 
 MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
         /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
         .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
-        .init_machine = mxc_board_init,
-        .timer = &mxc_timer,
+        .timer = &mx51_babbage_timer,
+        .init_machine = mx51_babbage_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index b7946f8e8d4..acab1911cb3 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -25,6 +25,9 @@
 #include <linux/fsl_devices.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
@@ -40,8 +43,7 @@
 
 #include "devices-imx51.h"
 #include "devices.h"
-
-#define MX51_USB_PLL_DIV_24_MHZ 0x01
+#include "efika.h"
 
 #define EFIKAMX_PCBID0          IMX_GPIO_NR(3, 16)
 #define EFIKAMX_PCBID1          IMX_GPIO_NR(3, 17)
@@ -53,13 +55,14 @@
 
 #define EFIKAMX_POWER_KEY       IMX_GPIO_NR(2, 31)
 
-#define EFIKAMX_SPI_CS0         IMX_GPIO_NR(4, 24)
-#define EFIKAMX_SPI_CS1         IMX_GPIO_NR(4, 25)
-
 /* board 1.1 doesn't have same reset gpio */
 #define EFIKAMX_RESET1_1        IMX_GPIO_NR(3, 2)
 #define EFIKAMX_RESET           IMX_GPIO_NR(1, 4)
 
+#define EFIKAMX_POWEROFF        IMX_GPIO_NR(4, 13)
+
+#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
+
 /* the pci ids pin have pull up. they're driven low according to board id */
 #define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
 #define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
@@ -67,38 +70,11 @@
 #define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
 
 static iomux_v3_cfg_t mx51efikamx_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
         /* board id */
         MX51_PAD_PCBID0,
         MX51_PAD_PCBID1,
         MX51_PAD_PCBID2,
 
-        /* SD 1 */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-
-        /* SD 2 */
-        MX51_PAD_SD2_CMD__SD2_CMD,
-        MX51_PAD_SD2_CLK__SD2_CLK,
-        MX51_PAD_SD2_DATA0__SD2_DATA0,
-        MX51_PAD_SD2_DATA1__SD2_DATA1,
-        MX51_PAD_SD2_DATA2__SD2_DATA2,
-        MX51_PAD_SD2_DATA3__SD2_DATA3,
-
-        /* SD/MMC WP/CD */
-        MX51_PAD_GPIO1_0__SD1_CD,
-        MX51_PAD_GPIO1_1__SD1_WP,
-        MX51_PAD_GPIO1_7__SD2_WP,
-        MX51_PAD_GPIO1_8__SD2_CD,
-
         /* leds */
         MX51_PAD_CSI1_D9__GPIO3_13,
         MX51_PAD_CSI1_VSYNC__GPIO3_14,
@@ -107,64 +83,12 @@ static iomux_v3_cfg_t mx51efikamx_pads[] = {
         /* power key */
         MX51_PAD_PWRKEY,
 
-        /* spi */
-        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-        MX51_PAD_CSPI1_SS0__GPIO4_24,
-        MX51_PAD_CSPI1_SS1__GPIO4_25,
-        MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
-        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-
         /* reset */
         MX51_PAD_DI1_PIN13__GPIO3_2,
         MX51_PAD_GPIO1_4__GPIO1_4,
-};
 
-/* Serial ports */
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static const struct imxuart_platform_data uart_pdata = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static inline void mxc_init_imx_uart(void)
-{
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, &uart_pdata);
-        imx51_add_imx_uart(2, &uart_pdata);
-}
-#else /* !SERIAL_IMX */
-static inline void mxc_init_imx_uart(void)
-{
-}
-#endif /* SERIAL_IMX */
-
-/* This function is board specific as the bit mask for the plldiv will also
- * be different for other Freescale SoCs, thus a common bitmask is not
- * possible and cannot get place in /plat-mxc/ehci.c.
- */
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_24_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-        return 0;
-}
-
-static struct mxc_usbh_platform_data dr_utmi_config = {
-        .init   = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-        .flags  = MXC_EHCI_INTERNAL_PHY,
+        /* power off */
+        MX51_PAD_CSI2_VSYNC__GPIO4_13,
 };
 
 /*   PCBID2  PCBID1 PCBID0  STATE
@@ -265,47 +189,6 @@ static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initcon
         .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
 };
 
-static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = {
-        {
-         .name = "u-boot",
-         .offset = 0,
-         .size = SZ_256K,
-        },
-        {
-          .name = "config",
-          .offset = MTDPART_OFS_APPEND,
-          .size = SZ_64K,
-        },
-};
-
-static struct flash_platform_data mx51_efikamx_spi_flash_data = {
-        .name           = "spi_flash",
-        .parts          = mx51_efikamx_spi_nor_partitions,
-        .nr_parts       = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions),
-        .type           = "sst25vf032b",
-};
-
-static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = {
-        {
-                .modalias = "m25p80",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .platform_data = &mx51_efikamx_spi_flash_data,
-                .irq = -1,
-        },
-};
-
-static int mx51_efikamx_spi_cs[] = {
-        EFIKAMX_SPI_CS0,
-        EFIKAMX_SPI_CS1,
-};
-
-static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = {
-        .chipselect     = mx51_efikamx_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs),
-};
-
 void mx51_efikamx_reset(void)
 {
         if (system_rev == 0x11)
@@ -314,14 +197,53 @@ void mx51_efikamx_reset(void)
                 gpio_direction_output(EFIKAMX_RESET, 0);
 }
 
-static void __init mxc_board_init(void)
+static struct regulator *pwgt1, *pwgt2, *coincell;
+
+static void mx51_efikamx_power_off(void)
+{
+        if (!IS_ERR(coincell))
+                regulator_disable(coincell);
+
+        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                regulator_disable(pwgt2);
+                regulator_disable(pwgt1);
+        }
+        gpio_direction_output(EFIKAMX_POWEROFF, 1);
+}
+
+static int __init mx51_efikamx_power_init(void)
+{
+        if (machine_is_mx51_efikamx()) {
+                pwgt1 = regulator_get(NULL, "pwgt1");
+                pwgt2 = regulator_get(NULL, "pwgt2");
+                if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                        regulator_enable(pwgt1);
+                        regulator_enable(pwgt2);
+                }
+                gpio_request(EFIKAMX_POWEROFF, "poweroff");
+                pm_power_off = mx51_efikamx_power_off;
+
+                /* enable coincell charger. maybe need a small power driver ? */
+                coincell = regulator_get(NULL, "coincell");
+                if (!IS_ERR(coincell)) {
+                        regulator_set_voltage(coincell, 3000000, 3000000);
+                        regulator_enable(coincell);
+                }
+
+                regulator_has_full_constraints();
+        }
+
+        return 0;
+}
+late_initcall(mx51_efikamx_power_init);
+
+static void __init mx51_efikamx_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
                                         ARRAY_SIZE(mx51efikamx_pads));
+        efika_board_common_init();
+
         mx51_efikamx_board_id();
-        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
-        mxc_init_imx_uart();
-        imx51_add_sdhci_esdhc_imx(0, NULL);
 
         /* on < 1.2 boards both SD controllers are used */
         if (system_rev < 0x12) {
@@ -332,10 +254,6 @@ static void __init mxc_board_init(void)
         platform_device_register(&mx51_efikamx_leds_device);
         imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
 
-        spi_register_board_info(mx51_efikamx_spi_board_info,
-                ARRAY_SIZE(mx51_efikamx_spi_board_info));
-        imx51_add_ecspi(0, &mx51_efikamx_spi_pdata);
-
         if (system_rev == 0x11) {
                 gpio_request(EFIKAMX_RESET1_1, "reset");
                 gpio_direction_output(EFIKAMX_RESET1_1, 1);
@@ -343,6 +261,20 @@ static void __init mxc_board_init(void)
                 gpio_request(EFIKAMX_RESET, "reset");
                 gpio_direction_output(EFIKAMX_RESET, 1);
         }
+
+        /*
+         * enable wifi by default only on mx
+         * sb and mx have same wlan pin but the value to enable it are
+         * different :/
+         */
+        gpio_request(EFIKA_WLAN_EN, "wlan_en");
+        gpio_direction_output(EFIKA_WLAN_EN, 0);
+        msleep(10);
+
+        gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
+        gpio_direction_output(EFIKA_WLAN_RESET, 0);
+        msleep(10);
+        gpio_set_value(EFIKA_WLAN_RESET, 1);
 }
 
 static void __init mx51_efikamx_timer_init(void)
@@ -350,15 +282,16 @@ static void __init mx51_efikamx_timer_init(void)
         mx51_clocks_init(32768, 24000000, 22579200, 24576000);
 }
 
-static struct sys_timer mxc_timer = {
-        .init   = mx51_efikamx_timer_init,
+static struct sys_timer mx51_efikamx_timer = {
+        .init = mx51_efikamx_timer_init,
 };
 
 MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
         /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
         .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
         .init_irq = mx51_init_irq,
-        .init_machine =  mxc_board_init,
-        .timer = &mxc_timer,
+        .timer = &mx51_efikamx_timer,
+        .init_machine = mx51_efikamx_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
new file mode 100644
index 00000000000..db04ce8462d
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -0,0 +1,283 @@
+/*
+ * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
+ *
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <mach/ulpi.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-imx51.h"
+#include "devices.h"
+#include "efika.h"
+
+#define EFIKASB_USBH2_STP       IMX_GPIO_NR(2, 20)
+#define EFIKASB_GREEN_LED       IMX_GPIO_NR(1, 3)
+#define EFIKASB_WHITE_LED       IMX_GPIO_NR(2, 25)
+#define EFIKASB_PCBID0          IMX_GPIO_NR(2, 28)
+#define EFIKASB_PCBID1          IMX_GPIO_NR(2, 29)
+#define EFIKASB_PWRKEY          IMX_GPIO_NR(2, 31)
+#define EFIKASB_LID             IMX_GPIO_NR(3, 14)
+#define EFIKASB_POWEROFF        IMX_GPIO_NR(4, 13)
+#define EFIKASB_RFKILL          IMX_GPIO_NR(3, 1)
+
+#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
+
+static iomux_v3_cfg_t mx51efikasb_pads[] = {
+        /* USB HOST2 */
+        MX51_PAD_EIM_D16__USBH2_DATA0,
+        MX51_PAD_EIM_D17__USBH2_DATA1,
+        MX51_PAD_EIM_D18__USBH2_DATA2,
+        MX51_PAD_EIM_D19__USBH2_DATA3,
+        MX51_PAD_EIM_D20__USBH2_DATA4,
+        MX51_PAD_EIM_D21__USBH2_DATA5,
+        MX51_PAD_EIM_D22__USBH2_DATA6,
+        MX51_PAD_EIM_D23__USBH2_DATA7,
+        MX51_PAD_EIM_A24__USBH2_CLK,
+        MX51_PAD_EIM_A25__USBH2_DIR,
+        MX51_PAD_EIM_A26__USBH2_STP,
+        MX51_PAD_EIM_A27__USBH2_NXT,
+
+        /* leds */
+        MX51_PAD_EIM_CS0__GPIO2_25,
+        MX51_PAD_GPIO1_3__GPIO1_3,
+
+        /* pcb id */
+        MX51_PAD_EIM_CS3__GPIO2_28,
+        MX51_PAD_EIM_CS4__GPIO2_29,
+
+        /* lid */
+        MX51_PAD_CSI1_VSYNC__GPIO3_14,
+
+        /* power key*/
+        MX51_PAD_PWRKEY,
+
+        /* wifi/bt button */
+        MX51_PAD_DI1_PIN12__GPIO3_1,
+
+        /* power off */
+        MX51_PAD_CSI2_VSYNC__GPIO4_13,
+
+        /* wdog reset */
+        MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
+
+        /* BT */
+        MX51_PAD_EIM_A17__GPIO2_11,
+};
+
+static int initialize_usbh2_port(struct platform_device *pdev)
+{
+        iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
+        iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
+
+        mxc_iomux_v3_setup_pad(usbh2gpio);
+        gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
+        gpio_direction_output(EFIKASB_USBH2_STP, 0);
+        msleep(1);
+        gpio_set_value(EFIKASB_USBH2_STP, 1);
+        msleep(1);
+
+        gpio_free(EFIKASB_USBH2_STP);
+        mxc_iomux_v3_setup_pad(usbh2stp);
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
+}
+
+static struct mxc_usbh_platform_data usbh2_config = {
+        .init   = initialize_usbh2_port,
+        .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static void __init mx51_efikasb_usb(void)
+{
+        usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
+        if (usbh2_config.otg)
+                mxc_register_device(&mxc_usbh2_device, &usbh2_config);
+}
+
+static struct gpio_led mx51_efikasb_leds[] = {
+        {
+                .name = "efikasb:green",
+                .default_trigger = "default-on",
+                .gpio = EFIKASB_GREEN_LED,
+                .active_low = 1,
+        },
+        {
+                .name = "efikasb:white",
+                .default_trigger = "caps",
+                .gpio = EFIKASB_WHITE_LED,
+        },
+};
+
+static struct gpio_led_platform_data mx51_efikasb_leds_data = {
+        .leds = mx51_efikasb_leds,
+        .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
+};
+
+static struct platform_device mx51_efikasb_leds_device = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev = {
+                .platform_data = &mx51_efikasb_leds_data,
+        },
+};
+
+static struct gpio_keys_button mx51_efikasb_keys[] = {
+        {
+                .code = KEY_POWER,
+                .gpio = EFIKASB_PWRKEY,
+                .type = EV_PWR,
+                .desc = "Power Button",
+                .wakeup = 1,
+                .debounce_interval = 10, /* ms */
+        },
+        {
+                .code = SW_LID,
+                .gpio = EFIKASB_LID,
+                .type = EV_SW,
+                .desc = "Lid Switch",
+        },
+        {
+                /* SW_RFKILLALL vs KEY_RFKILL ? */
+                .code = SW_RFKILL_ALL,
+                .gpio = EFIKASB_RFKILL,
+                .type = EV_SW,
+                .desc = "rfkill",
+        },
+};
+
+static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
+        .buttons = mx51_efikasb_keys,
+        .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
+};
+
+static struct regulator *pwgt1, *pwgt2;
+
+static void mx51_efikasb_power_off(void)
+{
+        gpio_set_value(EFIKA_USB_PHY_RESET, 0);
+
+        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                regulator_disable(pwgt2);
+                regulator_disable(pwgt1);
+        }
+        gpio_direction_output(EFIKASB_POWEROFF, 1);
+}
+
+static int __init mx51_efikasb_power_init(void)
+{
+        if (machine_is_mx51_efikasb()) {
+                pwgt1 = regulator_get(NULL, "pwgt1");
+                pwgt2 = regulator_get(NULL, "pwgt2");
+                if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
+                        regulator_enable(pwgt1);
+                        regulator_enable(pwgt2);
+                }
+                gpio_request(EFIKASB_POWEROFF, "poweroff");
+                pm_power_off = mx51_efikasb_power_off;
+
+                regulator_has_full_constraints();
+        }
+
+        return 0;
+}
+late_initcall(mx51_efikasb_power_init);
+
+/* 01     R1.3 board
+   10     R2.0 board */
+static void __init mx51_efikasb_board_id(void)
+{
+        int id;
+
+        gpio_request(EFIKASB_PCBID0, "pcb id0");
+        gpio_direction_input(EFIKASB_PCBID0);
+        gpio_request(EFIKASB_PCBID1, "pcb id1");
+        gpio_direction_input(EFIKASB_PCBID1);
+
+        id = gpio_get_value(EFIKASB_PCBID0);
+        id |= gpio_get_value(EFIKASB_PCBID1) << 1;
+
+        switch (id) {
+        default:
+                break;
+        case 1:
+                system_rev = 0x13;
+                break;
+        case 2:
+                system_rev = 0x20;
+                break;
+        }
+}
+
+static void __init efikasb_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
+                                        ARRAY_SIZE(mx51efikasb_pads));
+        efika_board_common_init();
+
+        mx51_efikasb_board_id();
+        mx51_efikasb_usb();
+        imx51_add_sdhci_esdhc_imx(1, NULL);
+
+        platform_device_register(&mx51_efikasb_leds_device);
+        imx51_add_gpio_keys(&mx51_efikasb_keys_data);
+
+}
+
+static void __init mx51_efikasb_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+}
+
+static struct sys_timer mx51_efikasb_timer = {
+        .init   = mx51_efikasb_timer_init,
+};
+
+MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_early = imx51_init_early,
+        .init_irq = mx51_init_irq,
+        .init_machine =  efikasb_board_init,
+        .timer = &mx51_efikasb_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index caee04c0823..7b5735c5ea5 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
  */
 
@@ -42,28 +42,24 @@
 #include "devices-imx53.h"
 
 static iomux_v3_cfg_t mx53_evk_pads[] = {
-        MX53_PAD_CSI0_D10__UART1_TXD,
-        MX53_PAD_CSI0_D11__UART1_RXD,
-        MX53_PAD_ATA_DIOW__UART1_TXD,
-        MX53_PAD_ATA_DMACK__UART1_RXD,
+        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
 
-        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
-        MX53_PAD_ATA_DMARQ__UART2_TXD,
-        MX53_PAD_ATA_DIOR__UART2_RTS,
-        MX53_PAD_ATA_INTRQ__UART2_CTS,
+        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+        MX53_PAD_PATA_DIOR__UART2_RTS,
+        MX53_PAD_PATA_INTRQ__UART2_CTS,
 
-        MX53_PAD_ATA_CS_0__UART3_TXD,
-        MX53_PAD_ATA_CS_1__UART3_RXD,
-        MX53_PAD_ATA_DA_1__UART3_CTS,
-        MX53_PAD_ATA_DA_2__UART3_RTS,
+        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
+        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
 
-        MX53_PAD_EIM_D16__CSPI1_SCLK,
-        MX53_PAD_EIM_D17__CSPI1_MISO,
-        MX53_PAD_EIM_D18__CSPI1_MOSI,
+        MX53_PAD_EIM_D16__ECSPI1_SCLK,
+        MX53_PAD_EIM_D17__ECSPI1_MISO,
+        MX53_PAD_EIM_D18__ECSPI1_MOSI,
 
         /* ecspi chip select lines */
-        MX53_PAD_EIM_EB2__GPIO_2_30,
-        MX53_PAD_EIM_D19__GPIO_3_19,
+        MX53_PAD_EIM_EB2__GPIO2_30,
+        MX53_PAD_EIM_D19__GPIO3_19,
 };
 
 static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
@@ -72,9 +68,9 @@ static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
 
 static inline void mx53_evk_init_uart(void)
 {
-        imx53_add_imx_uart(0, &mx53_evk_uart_pdata);
+        imx53_add_imx_uart(0, NULL);
         imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
-        imx53_add_imx_uart(2, &mx53_evk_uart_pdata);
+        imx53_add_imx_uart(2, NULL);
 }
 
 static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
@@ -139,6 +135,7 @@ static void __init mx53_evk_board_init(void)
         spi_register_board_info(mx53_evk_spi_board_info,
                 ARRAY_SIZE(mx53_evk_spi_board_info));
         imx53_add_ecspi(0, &mx53_evk_spi_data);
+        imx53_add_imx2_wdt(0, NULL);
 }
 
 static void __init mx53_evk_timer_init(void)
@@ -152,7 +149,8 @@ static struct sys_timer mx53_evk_timer = {
 
 MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
         .map_io = mx53_map_io,
+        .init_early = imx53_init_early,
         .init_irq = mx53_init_irq,
-        .init_machine = mx53_evk_board_init,
         .timer = &mx53_evk_timer,
+        .init_machine = mx53_evk_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index d1348e04ace..0a18f8d23eb 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -39,33 +39,147 @@
 #define LOCO_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
 
 static iomux_v3_cfg_t mx53_loco_pads[] = {
-        MX53_PAD_CSI0_D10__UART1_TXD,
-        MX53_PAD_CSI0_D11__UART1_RXD,
-        MX53_PAD_ATA_DIOW__UART1_TXD,
-        MX53_PAD_ATA_DMACK__UART1_RXD,
-
-        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
-        MX53_PAD_ATA_DMARQ__UART2_TXD,
-        MX53_PAD_ATA_DIOR__UART2_RTS,
-        MX53_PAD_ATA_INTRQ__UART2_CTS,
-
-        MX53_PAD_ATA_CS_0__UART3_TXD,
-        MX53_PAD_ATA_CS_1__UART3_RXD,
-        MX53_PAD_ATA_DA_1__UART3_CTS,
-        MX53_PAD_ATA_DA_2__UART3_RTS,
+        /* FEC */
+        MX53_PAD_FEC_MDC__FEC_MDC,
+        MX53_PAD_FEC_MDIO__FEC_MDIO,
+        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
+        MX53_PAD_FEC_RX_ER__FEC_RX_ER,
+        MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
+        MX53_PAD_FEC_RXD1__FEC_RDATA_1,
+        MX53_PAD_FEC_RXD0__FEC_RDATA_0,
+        MX53_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX53_PAD_FEC_TXD1__FEC_TDATA_1,
+        MX53_PAD_FEC_TXD0__FEC_TDATA_0,
+        /* FEC_nRST */
+        MX53_PAD_PATA_DA_0__GPIO7_6,
+        /* FEC_nINT */
+        MX53_PAD_PATA_DATA4__GPIO2_4,
+        /* AUDMUX5 */
+        MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
+        MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
+        MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
+        MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
+        /* I2C2 */
+        MX53_PAD_KEY_COL3__I2C2_SCL,
+        MX53_PAD_KEY_ROW3__I2C2_SDA,
+        /* SD1 */
+        MX53_PAD_SD1_CMD__ESDHC1_CMD,
+        MX53_PAD_SD1_CLK__ESDHC1_CLK,
+        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+        /* SD3 */
+        MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
+        MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
+        MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
+        MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
+        MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
+        MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
+        MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
+        MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
+        MX53_PAD_PATA_IORDY__ESDHC3_CLK,
+        MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
+        /* SD3_CD */
+        MX53_PAD_EIM_DA11__GPIO3_11,
+        /* SD3_WP */
+        MX53_PAD_EIM_DA12__GPIO3_12,
+        /* VGA */
+        MX53_PAD_EIM_OE__IPU_DI1_PIN7,
+        MX53_PAD_EIM_RW__IPU_DI1_PIN8,
+        /* DISPLB */
+        MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
+        MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
+        MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
+        MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
+        /* DISP0_POWER_EN */
+        MX53_PAD_EIM_D24__GPIO3_24,
+        /* DISP0 DET INT */
+        MX53_PAD_EIM_D31__GPIO3_31,
+        /* LVDS */
+        MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
+        MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
+        MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
+        MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
+        MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
+        MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
+        MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
+        MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
+        MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
+        MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
+        /* I2C1 */
+        MX53_PAD_CSI0_DAT8__I2C1_SDA,
+        MX53_PAD_CSI0_DAT9__I2C1_SCL,
+        /* UART1 */
+        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+        /* CSI0 */
+        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
+        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
+        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
+        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
+        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
+        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
+        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
+        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
+        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
+        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
+        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
+        /* DISPLAY */
+        MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
+        MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
+        MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
+        MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
+        MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
+        MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
+        MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
+        MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
+        MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
+        MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
+        MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
+        MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
+        MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
+        MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
+        MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
+        MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
+        MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
+        MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
+        MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
+        MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
+        MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
+        MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
+        MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
+        MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
+        MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
+        MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
+        MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
+        MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
+        /* Audio CLK*/
+        MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
+        /* PWM */
+        MX53_PAD_GPIO_1__PWM2_PWMO,
+        /* SPDIF */
+        MX53_PAD_GPIO_7__SPDIF_PLOCK,
+        MX53_PAD_GPIO_17__SPDIF_OUT1,
+        /* GPIO */
+        MX53_PAD_PATA_DA_1__GPIO7_7,
+        MX53_PAD_PATA_DA_2__GPIO7_8,
+        MX53_PAD_PATA_DATA5__GPIO2_5,
+        MX53_PAD_PATA_DATA6__GPIO2_6,
+        MX53_PAD_PATA_DATA14__GPIO2_14,
+        MX53_PAD_PATA_DATA15__GPIO2_15,
+        MX53_PAD_PATA_INTRQ__GPIO7_2,
+        MX53_PAD_EIM_WAIT__GPIO5_0,
+        MX53_PAD_NANDF_WP_B__GPIO6_9,
+        MX53_PAD_NANDF_RB0__GPIO6_10,
+        MX53_PAD_NANDF_CS1__GPIO6_14,
+        MX53_PAD_NANDF_CS2__GPIO6_15,
+        MX53_PAD_NANDF_CS3__GPIO6_16,
+        MX53_PAD_GPIO_5__GPIO1_5,
+        MX53_PAD_GPIO_16__GPIO7_11,
+        MX53_PAD_GPIO_8__GPIO1_8,
 };
 
-static const struct imxuart_platform_data mx53_loco_uart_data __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static inline void mx53_loco_init_uart(void)
-{
-        imx53_add_imx_uart(0, &mx53_loco_uart_data);
-        imx53_add_imx_uart(1, &mx53_loco_uart_data);
-        imx53_add_imx_uart(2, &mx53_loco_uart_data);
-}
-
 static inline void mx53_loco_fec_reset(void)
 {
         int ret;
@@ -85,13 +199,22 @@ static struct fec_platform_data mx53_loco_fec_data = {
         .phy = PHY_INTERFACE_MODE_RMII,
 };
 
+static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
 static void __init mx53_loco_board_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
                                         ARRAY_SIZE(mx53_loco_pads));
-        mx53_loco_init_uart();
+        imx53_add_imx_uart(0, NULL);
         mx53_loco_fec_reset();
         imx53_add_fec(&mx53_loco_fec_data);
+        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
+        imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
+        imx53_add_sdhci_esdhc_imx(0, NULL);
+        imx53_add_sdhci_esdhc_imx(2, NULL);
 }
 
 static void __init mx53_loco_timer_init(void)
@@ -105,7 +228,8 @@ static struct sys_timer mx53_loco_timer = {
 
 MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
         .map_io = mx53_map_io,
+        .init_early = imx53_init_early,
         .init_irq = mx53_init_irq,
-        .init_machine = mx53_loco_board_init,
         .timer = &mx53_loco_timer,
+        .init_machine = mx53_loco_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index 7970f7a4858..31e173267ed 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -39,20 +39,19 @@
 #define SMD_FEC_PHY_RST         IMX_GPIO_NR(7, 6)
 
 static iomux_v3_cfg_t mx53_smd_pads[] = {
-        MX53_PAD_CSI0_D10__UART1_TXD,
-        MX53_PAD_CSI0_D11__UART1_RXD,
-        MX53_PAD_ATA_DIOW__UART1_TXD,
-        MX53_PAD_ATA_DMACK__UART1_RXD,
-
-        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
-        MX53_PAD_ATA_DMARQ__UART2_TXD,
-        MX53_PAD_ATA_DIOR__UART2_RTS,
-        MX53_PAD_ATA_INTRQ__UART2_CTS,
-
-        MX53_PAD_ATA_CS_0__UART3_TXD,
-        MX53_PAD_ATA_CS_1__UART3_RXD,
-        MX53_PAD_ATA_DA_1__UART3_CTS,
-        MX53_PAD_ATA_DA_2__UART3_RTS,
+        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
+        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
+
+        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
+        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
+
+        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
+        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
+        MX53_PAD_PATA_DA_1__UART3_CTS,
+        MX53_PAD_PATA_DA_2__UART3_RTS,
+        /* I2C1 */
+        MX53_PAD_CSI0_DAT8__I2C1_SDA,
+        MX53_PAD_CSI0_DAT9__I2C1_SCL,
 };
 
 static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
@@ -61,8 +60,8 @@ static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
 
 static inline void mx53_smd_init_uart(void)
 {
-        imx53_add_imx_uart(0, &mx53_smd_uart_data);
-        imx53_add_imx_uart(1, &mx53_smd_uart_data);
+        imx53_add_imx_uart(0, NULL);
+        imx53_add_imx_uart(1, NULL);
         imx53_add_imx_uart(2, &mx53_smd_uart_data);
 }
 
@@ -85,6 +84,10 @@ static struct fec_platform_data mx53_smd_fec_data = {
         .phy = PHY_INTERFACE_MODE_RMII,
 };
 
+static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
+        .bitrate = 100000,
+};
+
 static void __init mx53_smd_board_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
@@ -92,6 +95,8 @@ static void __init mx53_smd_board_init(void)
         mx53_smd_init_uart();
         mx53_smd_fec_reset();
         imx53_add_fec(&mx53_smd_fec_data);
+        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
 }
 
 static void __init mx53_smd_timer_init(void)
@@ -105,7 +110,8 @@ static struct sys_timer mx53_smd_timer = {
 
 MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
         .map_io = mx53_map_io,
+        .init_early = imx53_init_early,
         .init_irq = mx53_init_irq,
-        .init_machine = mx53_smd_board_init,
         .timer = &mx53_smd_timer,
+        .init_machine = mx53_smd_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 0a19e7567c0..652ace41382 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -42,6 +42,9 @@ static struct clk usboh3_clk;
 static struct clk emi_fast_clk;
 static struct clk ipu_clk;
 static struct clk mipi_hsc1_clk;
+static struct clk esdhc1_clk;
+static struct clk esdhc2_clk;
+static struct clk esdhc3_mx53_clk;
 
 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
 
@@ -867,10 +870,6 @@ static struct clk gpt_32k_clk = {
         .parent = &ckil_clk,
 };
 
-static struct clk kpp_clk = {
-        .id = 0,
-};
-
 static struct clk dummy_clk = {
         .id = 0,
 };
@@ -1147,10 +1146,80 @@ CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
 CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
 CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
 
+/* mx51 specific */
 CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
 CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
 CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
 
+static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+        else if (parent == &esdhc2_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
+static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else if (parent == &esdhc2_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
+/* mx53 specific */
+static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+        else if (parent == &esdhc3_mx53_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
+CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
+CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
+
+static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CSCMR1);
+        if (parent == &esdhc1_clk)
+                reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else if (parent == &esdhc3_mx53_clk)
+                reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
+        else
+                return -EINVAL;
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)          \
         static struct clk name = {                                      \
                 .id             = i,                                    \
@@ -1255,9 +1324,62 @@ DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
         clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
 DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
+        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
+        NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
+
+/* mx51 specific */
 DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
         clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
 
+static struct clk esdhc3_clk = {
+        .id = 2,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc3_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc3_ipg_clk,
+};
+static struct clk esdhc4_clk = {
+        .id = 3,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc4_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc4_ipg_clk,
+};
+
+/* mx53 specific */
+static struct clk esdhc2_mx53_clk = {
+        .id = 2,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc2_mx53_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc3_ipg_clk,
+};
+
+DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
+        clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
+
+static struct clk esdhc4_mx53_clk = {
+        .id = 3,
+        .parent = &esdhc1_clk,
+        .set_parent = clk_esdhc4_mx53_set_parent,
+        .enable_reg = MXC_CCM_CCGR3,
+        .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
+        .enable  = _clk_max_enable,
+        .disable = _clk_max_disable,
+        .secondary = &esdhc4_ipg_clk,
+};
+
 DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
 DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
 DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1302,7 +1424,7 @@ static struct clk_lookup mx51_lookups[] = {
         _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
-        _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
         _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
@@ -1316,6 +1438,8 @@ static struct clk_lookup mx51_lookups[] = {
         _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk)
         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
@@ -1336,10 +1460,14 @@ static struct clk_lookup mx53_lookups[] = {
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
-        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
+        _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
         _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
         _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
         _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
+        _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
 };
 
 static void clk_tree_init(void)
@@ -1427,6 +1555,14 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
         mx53_revision();
         clk_disable(&iim_clk);
 
+        /* Set SDHC parents to be PLL2 */
+        clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
+        clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
+
+        /* set SDHC root clock as 200MHZ*/
+        clk_set_rate(&esdhc1_clk, 200000000);
+        clk_set_rate(&esdhc3_mx53_clk, 200000000);
+
         /* System timer */
         mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
                 MX53_INT_GPT);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index d40671da437..df46b5e6085 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -78,11 +78,16 @@ static int get_mx53_srev(void)
         void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
         u32 rev = readl(iim_base + IIM_SREV) & 0xff;
 
-        if (rev == 0x0)
+        switch (rev) {
+        case 0x0:
                 return IMX_CHIP_REVISION_1_0;
-        else if (rev == 0x10)
+        case 0x2:
                 return IMX_CHIP_REVISION_2_0;
-        return 0;
+        case 0x3:
+                return IMX_CHIP_REVISION_2_1;
+        default:
+                return IMX_CHIP_REVISION_UNKNOWN;
+        }
 }
 
 /*
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index b462c22f53d..87c0c58f27a 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -217,9 +217,12 @@
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET      (20)
 #define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK        (0x3 << 20)
 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL                   (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL        (0x1 << 19)
 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL                   (0x1 << 18)
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET      (16)
 #define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK        (0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET       (16)
+#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK         (0x3 << 16)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET              (14)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK                (0x3 << 14)
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET              (12)
@@ -271,6 +274,10 @@
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK       (0x7 << 22)
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET     (19)
 #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK       (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET      (22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK        (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET      (19)
+#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK        (0x7 << 19)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET     (16)
 #define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK       (0x7 << 16)
 #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET              (14)
diff --git a/arch/arm/mach-mx5/devices-mx50.h b/arch/arm/mach-mx5/devices-imx50.h
index 98ab07468a0..c9e42823c7e 100644
--- a/arch/arm/mach-mx5/devices-mx50.h
+++ b/arch/arm/mach-mx5/devices-imx50.h
@@ -24,3 +24,11 @@
 extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
 #define imx50_add_imx_uart(id, pdata)   \
         imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
+
+extern const struct imx_fec_data imx50_fec_data __initconst;
+#define imx50_add_fec(pdata)    \
+        imx_add_fec(&imx50_fec_data, pdata)
+
+extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst;
+#define imx50_add_imx_i2c(id, pdata)    \
+        imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 8639735a117..9251008dad1 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -29,3 +29,7 @@ imx53_sdhci_esdhc_imx_data[] __initconst;
 extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
 #define imx53_add_ecspi(id, pdata)      \
         imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
+
+extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
+#define imx53_add_imx2_wdt(id, pdata)   \
+        imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-mx5/efika.h
new file mode 100644
index 00000000000..014aa985faa
--- /dev/null
+++ b/arch/arm/mach-mx5/efika.h
@@ -0,0 +1,10 @@
+#ifndef _EFIKA_H
+#define _EFIKA_H
+
+#define EFIKA_WLAN_EN           IMX_GPIO_NR(2, 16)
+#define EFIKA_WLAN_RESET        IMX_GPIO_NR(2, 10)
+#define EFIKA_USB_PHY_RESET     IMX_GPIO_NR(2, 9)
+
+void __init efika_board_common_init(void);
+
+#endif
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
new file mode 100644
index 00000000000..7ce12c804a3
--- /dev/null
+++ b/arch/arm/mach-mx5/ehci.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+
+#define MXC_OTG_OFFSET                  0
+#define MXC_H1_OFFSET                   0x200
+#define MXC_H2_OFFSET                   0x400
+
+/* USB_CTRL */
+#define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
+#define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
+#define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
+#define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
+#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)               /* HOST1 power mask */
+
+/* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_DIS_BIT               (1 << 5)        /* UH1 Disable Overcurrent Event */
+
+/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT          (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT           (1 << 4)
+
+#define MXC_USBCMD_OFFSET               0x140
+
+/* USBCMD */
+#define MXC_UCMD_ITC_NO_THRESHOLD_MASK  (~(0xff << 16)) /* Interrupt Threshold Control */
+
+int mx51_initialize_usb_hw(int port, unsigned int flags)
+{
+        unsigned int v;
+        void __iomem *usb_base;
+        void __iomem *usbotg_base;
+        void __iomem *usbother_base;
+        int ret = 0;
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base) {
+                printk(KERN_ERR "%s(): ioremap failed\n", __func__);
+                return -ENOMEM;
+        }
+
+        switch (port) {
+        case 0: /* OTG port */
+                usbotg_base = usb_base + MXC_OTG_OFFSET;
+                break;
+        case 1: /* Host 1 port */
+                usbotg_base = usb_base + MXC_H1_OFFSET;
+                break;
+        case 2: /* Host 2 port */
+                usbotg_base = usb_base + MXC_H2_OFFSET;
+                break;
+        default:
+                printk(KERN_ERR"%s no such port %d\n", __func__, port);
+                ret = -ENOENT;
+                goto error;
+        }
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+        switch (port) {
+        case 0: /*OTG port */
+                if (flags & MXC_EHCI_INTERNAL_PHY) {
+                        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
+                                /* OC/USBPWR is not used */
+                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                        } else {
+                                /* OC/USBPWR is used */
+                                v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                        }
+                        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+                        if (flags & MXC_EHCI_WAKEUP_ENABLED)
+                                v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
+                        else
+                                v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                v |= MXC_OTG_UCTRL_OPM_BIT;
+                        else
+                                v &= ~MXC_OTG_UCTRL_OPM_BIT;
+                        __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+                }
+                break;
+        case 1: /* Host 1 */
+                /*Host ULPI */
+                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
+                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                        /* HOST1 wakeup/ULPI intr enable */
+                        v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+                } else {
+                        /* HOST1 wakeup/ULPI intr disable */
+                        v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+                }
+
+                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+                else
+                        v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+                __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
+
+                v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                        v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
+                else
+                        v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
+                __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+
+                v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
+                if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
+                        /* Interrupt Threshold Control:Immediate (no threshold) */
+                        v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
+                __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
+                break;
+        case 2: /* Host 2 ULPI */
+                v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+                if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                        /* HOST1 wakeup/ULPI intr enable */
+                        v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+                } else {
+                        /* HOST1 wakeup/ULPI intr disable */
+                        v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+                }
+
+                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                else
+                        v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
+                break;
+        }
+
+error:
+        iounmap(usb_base);
+        return ret;
+}
+
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
index 8c6540e5839..b9c363b514a 100644
--- a/arch/arm/mach-mx5/mm-mx50.c
+++ b/arch/arm/mach-mx5/mm-mx50.c
@@ -26,6 +26,8 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
 
 /*
  * Define the MX50 memory map.
@@ -44,16 +46,27 @@ static struct map_desc mx50_io_desc[] __initdata = {
  */
 void __init mx50_map_io(void)
 {
+        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
+}
+
+void __init imx50_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX50);
         mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
-        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
 }
 
-int imx50_register_gpios(void);
+static struct mxc_gpio_port imx50_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+};
 
 void __init mx50_init_irq(void)
 {
         tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
-        imx50_register_gpios();
+        mxc_gpio_init(imx50_gpio_ports, ARRAY_SIZE(imx50_gpio_ports));
 }
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 457f9f95204..ff557301b42 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -47,18 +47,26 @@ static struct map_desc mx53_io_desc[] __initdata = {
  */
 void __init mx51_map_io(void)
 {
+        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
+}
+
+void __init imx51_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
 }
 
 void __init mx53_map_io(void)
 {
+        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
+}
+
+void __init imx53_init_early(void)
+{
         mxc_set_cpu_type(MXC_CPU_MX53);
         mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR));
-        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
+        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
 }
 
 int imx51_register_gpios(void);
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
new file mode 100644
index 00000000000..51a67fc7f0e
--- /dev/null
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -0,0 +1,636 @@
+/*
+ * based on code from the following
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
+ * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <mach/ulpi.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach-types.h>
+
+#include "devices-imx51.h"
+#include "devices.h"
+#include "efika.h"
+#include "cpu_op-mx51.h"
+
+#define MX51_USB_CTRL_1_OFFSET          0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
+#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
+
+#define EFIKAMX_USB_HUB_RESET   IMX_GPIO_NR(1, 5)
+#define EFIKAMX_USBH1_STP       IMX_GPIO_NR(1, 27)
+
+#define EFIKAMX_SPI_CS0         IMX_GPIO_NR(4, 24)
+#define EFIKAMX_SPI_CS1         IMX_GPIO_NR(4, 25)
+
+#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
+
+static iomux_v3_cfg_t mx51efika_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+
+        /* SD 1 */
+        MX51_PAD_SD1_CMD__SD1_CMD,
+        MX51_PAD_SD1_CLK__SD1_CLK,
+        MX51_PAD_SD1_DATA0__SD1_DATA0,
+        MX51_PAD_SD1_DATA1__SD1_DATA1,
+        MX51_PAD_SD1_DATA2__SD1_DATA2,
+        MX51_PAD_SD1_DATA3__SD1_DATA3,
+
+        /* SD 2 */
+        MX51_PAD_SD2_CMD__SD2_CMD,
+        MX51_PAD_SD2_CLK__SD2_CLK,
+        MX51_PAD_SD2_DATA0__SD2_DATA0,
+        MX51_PAD_SD2_DATA1__SD2_DATA1,
+        MX51_PAD_SD2_DATA2__SD2_DATA2,
+        MX51_PAD_SD2_DATA3__SD2_DATA3,
+
+        /* SD/MMC WP/CD */
+        MX51_PAD_GPIO1_0__SD1_CD,
+        MX51_PAD_GPIO1_1__SD1_WP,
+        MX51_PAD_GPIO1_7__SD2_WP,
+        MX51_PAD_GPIO1_8__SD2_CD,
+
+        /* spi */
+        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+        MX51_PAD_CSPI1_SS0__GPIO4_24,
+        MX51_PAD_CSPI1_SS1__GPIO4_25,
+        MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
+        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+        MX51_PAD_GPIO1_6__GPIO1_6,
+
+        /* USB HOST1 */
+        MX51_PAD_USBH1_CLK__USBH1_CLK,
+        MX51_PAD_USBH1_DIR__USBH1_DIR,
+        MX51_PAD_USBH1_NXT__USBH1_NXT,
+        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+
+        /* USB HUB RESET */
+        MX51_PAD_GPIO1_5__GPIO1_5,
+
+        /* WLAN */
+        MX51_PAD_EIM_A22__GPIO2_16,
+        MX51_PAD_EIM_A16__GPIO2_10,
+
+        /* USB PHY RESET */
+        MX51_PAD_EIM_D27__GPIO2_9,
+};
+
+/* Serial ports */
+static const struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+/* This function is board specific as the bit mask for the plldiv will also
+ * be different for other Freescale SoCs, thus a common bitmask is not
+ * possible and cannot get place in /plat-mxc/ehci.c.
+ */
+static int initialize_otg_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base)
+                return -ENOMEM;
+        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+
+        /* Set the PHY clock to 19.2MHz */
+        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+        v |= MX51_USB_PLL_DIV_19_2_MHZ;
+        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        iounmap(usb_base);
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
+}
+
+static struct mxc_usbh_platform_data dr_utmi_config = {
+        .init   = initialize_otg_port,
+        .portsc = MXC_EHCI_UTMI_16BIT,
+};
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
+        iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *socregs_base;
+
+        mxc_iomux_v3_setup_pad(usbh1gpio);
+        gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
+        gpio_direction_output(EFIKAMX_USBH1_STP, 0);
+        msleep(1);
+        gpio_set_value(EFIKAMX_USBH1_STP, 1);
+        msleep(1);
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
+
+        /* The clock for the USBH1 ULPI port will come externally */
+        /* from the PHY. */
+        v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
+        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
+                        socregs_base + MX51_USB_CTRL_1_OFFSET);
+
+        iounmap(usb_base);
+
+        gpio_free(EFIKAMX_USBH1_STP);
+        mxc_iomux_v3_setup_pad(usbh1stp);
+
+        mdelay(10);
+
+        return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD);
+}
+
+static struct mxc_usbh_platform_data usbh1_config = {
+        .init   = initialize_usbh1_port,
+        .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static void mx51_efika_hubreset(void)
+{
+        gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
+        gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
+        msleep(1);
+        gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
+        msleep(1);
+        gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
+}
+
+static void __init mx51_efika_usb(void)
+{
+        mx51_efika_hubreset();
+
+        /* pulling it low, means no USB at all... */
+        gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
+        gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
+        msleep(1);
+        gpio_set_value(EFIKA_USB_PHY_RESET, 1);
+
+        usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
+
+        mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        if (usbh1_config.otg)
+                mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+}
+
+static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
+        {
+         .name = "u-boot",
+         .offset = 0,
+         .size = SZ_256K,
+        },
+        {
+          .name = "config",
+          .offset = MTDPART_OFS_APPEND,
+          .size = SZ_64K,
+        },
+};
+
+static struct flash_platform_data mx51_efika_spi_flash_data = {
+        .name           = "spi_flash",
+        .parts          = mx51_efika_spi_nor_partitions,
+        .nr_parts       = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
+        .type           = "sst25vf032b",
+};
+
+static struct regulator_consumer_supply sw1_consumers[] = {
+        {
+                .supply = "cpu_vcc",
+        }
+};
+
+static struct regulator_consumer_supply vdig_consumers[] = {
+        /* sgtl5000 */
+        REGULATOR_SUPPLY("VDDA", "1-000a"),
+        REGULATOR_SUPPLY("VDDD", "1-000a"),
+};
+
+static struct regulator_consumer_supply vvideo_consumers[] = {
+        /* sgtl5000 */
+        REGULATOR_SUPPLY("VDDIO", "1-000a"),
+};
+
+static struct regulator_consumer_supply vsd_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
+        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
+};
+
+static struct regulator_consumer_supply pwgt1_consumer[] = {
+        {
+                .supply = "pwgt1",
+        }
+};
+
+static struct regulator_consumer_supply pwgt2_consumer[] = {
+        {
+                .supply = "pwgt2",
+        }
+};
+
+static struct regulator_consumer_supply coincell_consumer[] = {
+        {
+                .supply = "coincell",
+        }
+};
+
+static struct regulator_init_data sw1_init = {
+        .constraints = {
+                .name = "SW1",
+                .min_uV = 600000,
+                .max_uV = 1375000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .valid_modes_mask = 0,
+                .always_on = 1,
+                .boot_on = 1,
+                .state_mem = {
+                        .uV = 850000,
+                        .mode = REGULATOR_MODE_NORMAL,
+                        .enabled = 1,
+                },
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+        .consumer_supplies = sw1_consumers,
+};
+
+static struct regulator_init_data sw2_init = {
+        .constraints = {
+                .name = "SW2",
+                .min_uV = 900000,
+                .max_uV = 1850000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on = 1,
+                .boot_on = 1,
+                .state_mem = {
+                        .uV = 950000,
+                        .mode = REGULATOR_MODE_NORMAL,
+                        .enabled = 1,
+                },
+        }
+};
+
+static struct regulator_init_data sw3_init = {
+        .constraints = {
+                .name = "SW3",
+                .min_uV = 1100000,
+                .max_uV = 1850000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on = 1,
+                .boot_on = 1,
+        }
+};
+
+static struct regulator_init_data sw4_init = {
+        .constraints = {
+                .name = "SW4",
+                .min_uV = 1100000,
+                .max_uV = 1850000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .always_on = 1,
+                .boot_on = 1,
+        }
+};
+
+static struct regulator_init_data viohi_init = {
+        .constraints = {
+                .name = "VIOHI",
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data vusb_init = {
+        .constraints = {
+                .name = "VUSB",
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data swbst_init = {
+        .constraints = {
+                .name = "SWBST",
+        }
+};
+
+static struct regulator_init_data vdig_init = {
+        .constraints = {
+                .name = "VDIG",
+                .min_uV = 1050000,
+                .max_uV = 1800000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
+        .consumer_supplies = vdig_consumers,
+};
+
+static struct regulator_init_data vpll_init = {
+        .constraints = {
+                .name = "VPLL",
+                .min_uV = 1050000,
+                .max_uV = 1800000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data vusb2_init = {
+        .constraints = {
+                .name = "VUSB2",
+                .min_uV = 2400000,
+                .max_uV = 2775000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data vvideo_init = {
+        .constraints = {
+                .name = "VVIDEO",
+                .min_uV = 2775000,
+                .max_uV = 2775000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .apply_uV = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
+        .consumer_supplies = vvideo_consumers,
+};
+
+static struct regulator_init_data vaudio_init = {
+        .constraints = {
+                .name = "VAUDIO",
+                .min_uV = 2300000,
+                .max_uV = 3000000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+        }
+};
+
+static struct regulator_init_data vsd_init = {
+        .constraints = {
+                .name = "VSD",
+                .min_uV = 1800000,
+                .max_uV = 3150000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE,
+                .boot_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
+        .consumer_supplies = vsd_consumers,
+};
+
+static struct regulator_init_data vcam_init = {
+        .constraints = {
+                .name = "VCAM",
+                .min_uV = 2500000,
+                .max_uV = 3000000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE |
+                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+                .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
+                .boot_on = 1,
+        }
+};
+
+static struct regulator_init_data vgen1_init = {
+        .constraints = {
+                .name = "VGEN1",
+                .min_uV = 1200000,
+                .max_uV = 3150000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data vgen2_init = {
+        .constraints = {
+                .name = "VGEN2",
+                .min_uV = 1200000,
+                .max_uV = 3150000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data vgen3_init = {
+        .constraints = {
+                .name = "VGEN3",
+                .min_uV = 1800000,
+                .max_uV = 2900000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
+static struct regulator_init_data gpo1_init = {
+        .constraints = {
+                .name = "GPO1",
+        }
+};
+
+static struct regulator_init_data gpo2_init = {
+        .constraints = {
+                .name = "GPO2",
+        }
+};
+
+static struct regulator_init_data gpo3_init = {
+        .constraints = {
+                .name = "GPO3",
+        }
+};
+
+static struct regulator_init_data gpo4_init = {
+        .constraints = {
+                .name = "GPO4",
+        }
+};
+
+static struct regulator_init_data pwgt1_init = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .boot_on        = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
+        .consumer_supplies = pwgt1_consumer,
+};
+
+static struct regulator_init_data pwgt2_init = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .boot_on        = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
+        .consumer_supplies = pwgt2_consumer,
+};
+
+static struct regulator_init_data vcoincell_init = {
+        .constraints = {
+                .name = "COINCELL",
+                .min_uV = 3000000,
+                .max_uV = 3000000,
+                .valid_ops_mask =
+                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
+        .consumer_supplies = coincell_consumer,
+};
+
+static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
+        { .id = MC13892_SW1,            .init_data =  &sw1_init },
+        { .id = MC13892_SW2,            .init_data =  &sw2_init },
+        { .id = MC13892_SW3,            .init_data =  &sw3_init },
+        { .id = MC13892_SW4,            .init_data =  &sw4_init },
+        { .id = MC13892_SWBST,          .init_data =  &swbst_init },
+        { .id = MC13892_VIOHI,          .init_data =  &viohi_init },
+        { .id = MC13892_VPLL,           .init_data =  &vpll_init },
+        { .id = MC13892_VDIG,           .init_data =  &vdig_init },
+        { .id = MC13892_VSD,            .init_data =  &vsd_init },
+        { .id = MC13892_VUSB2,          .init_data =  &vusb2_init },
+        { .id = MC13892_VVIDEO,         .init_data =  &vvideo_init },
+        { .id = MC13892_VAUDIO,         .init_data =  &vaudio_init },
+        { .id = MC13892_VCAM,           .init_data =  &vcam_init },
+        { .id = MC13892_VGEN1,          .init_data =  &vgen1_init },
+        { .id = MC13892_VGEN2,          .init_data =  &vgen2_init },
+        { .id = MC13892_VGEN3,          .init_data =  &vgen3_init },
+        { .id = MC13892_VUSB,           .init_data =  &vusb_init },
+        { .id = MC13892_GPO1,           .init_data =  &gpo1_init },
+        { .id = MC13892_GPO2,           .init_data =  &gpo2_init },
+        { .id = MC13892_GPO3,           .init_data =  &gpo3_init },
+        { .id = MC13892_GPO4,           .init_data =  &gpo4_init },
+        { .id = MC13892_PWGT1SPI,       .init_data = &pwgt1_init },
+        { .id = MC13892_PWGT2SPI,       .init_data = &pwgt2_init },
+        { .id = MC13892_VCOINCELL,      .init_data = &vcoincell_init },
+};
+
+static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
+        .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
+        .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
+        .regulators = mx51_efika_regulators,
+};
+
+static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
+        {
+                .modalias = "m25p80",
+                .max_speed_hz = 25000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .platform_data = &mx51_efika_spi_flash_data,
+                .irq = -1,
+        },
+        {
+                .modalias = "mc13892",
+                .max_speed_hz = 1000000,
+                .bus_num = 0,
+                .chip_select = 0,
+                .platform_data = &mx51_efika_mc13892_data,
+                .irq = gpio_to_irq(EFIKAMX_PMIC),
+        },
+};
+
+static int mx51_efika_spi_cs[] = {
+        EFIKAMX_SPI_CS0,
+        EFIKAMX_SPI_CS1,
+};
+
+static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
+        .chipselect     = mx51_efika_spi_cs,
+        .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
+};
+
+void __init efika_board_common_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
+                                        ARRAY_SIZE(mx51efika_pads));
+        imx51_add_imx_uart(0, &uart_pdata);
+        mx51_efika_usb();
+        imx51_add_sdhci_esdhc_imx(0, NULL);
+
+        /* FIXME: comes from original code. check this. */
+        if (mx51_revision() < IMX_CHIP_REVISION_2_0)
+                sw2_init.constraints.state_mem.uV = 1100000;
+        else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
+                sw2_init.constraints.state_mem.uV = 1250000;
+                sw1_init.constraints.state_mem.uV = 1000000;
+        }
+        if (machine_is_mx51_efikasb())
+                vgen1_init.constraints.max_uV = 1200000;
+
+        gpio_request(EFIKAMX_PMIC, "pmic irq");
+        gpio_direction_input(EFIKAMX_PMIC);
+        spi_register_board_info(mx51_efika_spi_board_info,
+                ARRAY_SIZE(mx51_efika_spi_board_info));
+        imx51_add_ecspi(0, &mx51_efika_spi_pdata);
+
+#if defined(CONFIG_CPU_FREQ_IMX)
+        get_cpu_op = mx51_get_cpu_op;
+#endif
+}
+