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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-03-10 08:53:29 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-03-10 08:53:29 -0500
commit3afdb0f3528991de0833224f2dba60dc061e01fa (patch)
tree0d9c7529c6cc2b41f0df778cc396edd74699721a /arch
parent71d8c5b11e3b5936ae6c2e0b1dd6f5c78b305b65 (diff)
parentf7fdaca910e6bc13659ecdffc28c97938b752e01 (diff)
Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/configs/mx51_defconfig2
-rw-r--r--arch/arm/mach-imx/Kconfig12
-rw-r--r--arch/arm/mach-imx/Makefile5
-rw-r--r--arch/arm/mach-imx/clock-imx1.c1
-rw-r--r--arch/arm/mach-imx/clock-imx25.c3
-rw-r--r--arch/arm/mach-imx/devices-imx1.h11
-rw-r--r--arch/arm/mach-imx/devices-imx25.h6
-rw-r--r--arch/arm/mach-imx/dma-v1.c2
-rw-r--r--arch/arm/mach-imx/ehci-imx25.c80
-rw-r--r--arch/arm/mach-imx/ehci-imx27.c82
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c7
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c49
-rw-r--r--arch/arm/mach-imx/mach-eukrea_cpuimx25.c27
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c32
-rw-r--r--arch/arm/mach-imx/mach-imx27ipcam.c78
-rw-r--r--arch/arm/mach-imx/mach-imx27lite.c11
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c22
-rw-r--r--arch/arm/mach-imx/mach-mx21ads.c11
-rw-r--r--arch/arm/mach-imx/mach-mx25_3ds.c32
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c43
-rw-r--r--arch/arm/mach-imx/mach-mx27ads.c11
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c12
-rw-r--r--arch/arm/mach-imx/mach-pca100.c49
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c27
-rw-r--r--arch/arm/mach-imx/mach-scb9328.c13
-rw-r--r--arch/arm/mach-imx/mm-imx1.c21
-rw-r--r--arch/arm/mach-imx/mm-imx21.c23
-rw-r--r--arch/arm/mach-imx/mm-imx25.c18
-rw-r--r--arch/arm/mach-imx/mm-imx27.c23
-rw-r--r--arch/arm/mach-mx3/Kconfig25
-rw-r--r--arch/arm/mach-mx3/Makefile6
-rw-r--r--arch/arm/mach-mx3/devices-imx35.h2
-rw-r--r--arch/arm/mach-mx3/ehci-imx31.c83
-rw-r--r--arch/arm/mach-mx3/ehci-imx35.c80
-rw-r--r--arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c4
-rw-r--r--arch/arm/mach-mx3/iomux-imx31.c12
-rw-r--r--arch/arm/mach-mx3/mach-armadillo5x0.c41
-rw-r--r--arch/arm/mach-mx3/mach-bug.c66
-rw-r--r--arch/arm/mach-mx3/mach-cpuimx35.c31
-rw-r--r--arch/arm/mach-mx3/mach-kzm_arm11_01.c17
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c462
-rw-r--r--arch/arm/mach-mx3/mach-mx31ads.c57
-rw-r--r--arch/arm/mach-mx3/mach-mx31lilly.c95
-rw-r--r--arch/arm/mach-mx3/mach-mx31lite.c37
-rw-r--r--arch/arm/mach-mx3/mach-mx31moboard.c39
-rw-r--r--arch/arm/mach-mx3/mach-mx35_3ds.c42
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c46
-rw-r--r--arch/arm/mach-mx3/mach-pcm037_eet.c2
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c54
-rw-r--r--arch/arm/mach-mx3/mach-qong.c22
-rw-r--r--arch/arm/mach-mx3/mach-vpr200.c328
-rw-r--r--arch/arm/mach-mx3/mm.c43
-rw-r--r--arch/arm/mach-mx3/mx31moboard-devboard.c7
-rw-r--r--arch/arm/mach-mx3/mx31moboard-marxbot.c6
-rw-r--r--arch/arm/mach-mx3/mx31moboard-smartbot.c13
-rw-r--r--arch/arm/mach-mx5/Kconfig27
-rw-r--r--arch/arm/mach-mx5/Makefile4
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c20
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51sd.c31
-rw-r--r--arch/arm/mach-mx5/board-mx50_rdp.c34
-rw-r--r--arch/arm/mach-mx5/board-mx51_3ds.c43
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c43
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikamx.c211
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikasb.c283
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c40
-rw-r--r--arch/arm/mach-mx5/board-mx53_loco.c178
-rw-r--r--arch/arm/mach-mx5/board-mx53_smd.c40
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c148
-rw-r--r--arch/arm/mach-mx5/cpu.c11
-rw-r--r--arch/arm/mach-mx5/crm_regs.h7
-rw-r--r--arch/arm/mach-mx5/devices-imx50.h (renamed from arch/arm/mach-mx5/devices-mx50.h)8
-rw-r--r--arch/arm/mach-mx5/devices-imx53.h4
-rw-r--r--arch/arm/mach-mx5/efika.h10
-rw-r--r--arch/arm/mach-mx5/ehci.c156
-rw-r--r--arch/arm/mach-mx5/mm-mx50.c19
-rw-r--r--arch/arm/mach-mx5/mm.c14
-rw-r--r--arch/arm/mach-mx5/mx51_efika.c636
-rw-r--r--arch/arm/mach-mxc91231/iomux.c14
-rw-r--r--arch/arm/mach-mxc91231/magx-zn5.c11
-rw-r--r--arch/arm/mach-mxc91231/mm.c7
-rw-r--r--arch/arm/mach-mxs/Kconfig24
-rw-r--r--arch/arm/mach-mxs/Makefile5
-rw-r--r--arch/arm/mach-mxs/clock-mx23.c11
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c25
-rw-r--r--arch/arm/mach-mxs/devices-mx23.h11
-rw-r--r--arch/arm/mach-mxs/devices-mx28.h23
-rw-r--r--arch/arm/mach-mxs/devices.c2
-rw-r--r--arch/arm/mach-mxs/devices/Kconfig16
-rw-r--r--arch/arm/mach-mxs/devices/Makefile6
-rw-r--r--arch/arm/mach-mxs/devices/platform-auart.c64
-rw-r--r--arch/arm/mach-mxs/devices/platform-dma.c49
-rw-r--r--arch/arm/mach-mxs/devices/platform-fec.c5
-rw-r--r--arch/arm/mach-mxs/devices/platform-flexcan.c51
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxs-i2c.c51
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxs-pwm.c22
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxsfb.c46
-rw-r--r--arch/arm/mach-mxs/gpio.c46
-rw-r--r--arch/arm/mach-mxs/include/mach/common.h1
-rw-r--r--arch/arm/mach-mxs/include/mach/devices-common.h35
-rw-r--r--arch/arm/mach-mxs/include/mach/iomux-mx23.h190
-rw-r--r--arch/arm/mach-mxs/include/mach/iomux.h3
-rw-r--r--arch/arm/mach-mxs/include/mach/mx23.h38
-rw-r--r--arch/arm/mach-mxs/include/mach/mx28.h45
-rw-r--r--arch/arm/mach-mxs/include/mach/mxs.h9
-rw-r--r--arch/arm/mach-mxs/include/mach/mxsfb.h49
-rw-r--r--arch/arm/mach-mxs/include/mach/uncompress.h1
-rw-r--r--arch/arm/mach-mxs/mach-mx23evk.c90
-rw-r--r--arch/arm/mach-mxs/mach-mx28evk.c237
-rw-r--r--arch/arm/mach-mxs/mach-tx28.c183
-rw-r--r--arch/arm/mach-mxs/module-tx28.c131
-rw-r--r--arch/arm/mach-mxs/module-tx28.h9
-rw-r--r--arch/arm/mach-mxs/ocotp.c90
-rw-r--r--arch/arm/mach-mxs/pm.c43
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx23.h124
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx28.h177
-rw-r--r--arch/arm/mach-mxs/system.c2
-rw-r--r--arch/arm/mm/Kconfig2
-rw-r--r--arch/arm/plat-mxc/Kconfig1
-rw-r--r--arch/arm/plat-mxc/Makefile1
-rw-r--r--arch/arm/plat-mxc/devices.c2
-rw-r--r--arch/arm/plat-mxc/devices/platform-fec.c9
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-dma.c6
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-fb.c5
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-i2c.c10
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx2-wdt.c9
-rw-r--r--arch/arm/plat-mxc/devices/platform-spi_imx.c9
-rw-r--r--arch/arm/plat-mxc/ehci.c369
-rw-r--r--arch/arm/plat-mxc/gpio.c111
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/gpio.h15
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx35.h14
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx50.h44
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h44
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx53.h2639
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mxc91231.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v1.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/mx53.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/ulpi.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h7
-rw-r--r--arch/arm/plat-mxc/iomux-v1.c24
-rw-r--r--arch/arm/plat-mxc/ulpi.c5
146 files changed, 7469 insertions, 2174 deletions
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index 9cba68cfa51..e3c903281f7 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -110,7 +110,7 @@ CONFIG_MMC=y
110CONFIG_MMC_BLOCK=m 110CONFIG_MMC_BLOCK=m
111CONFIG_MMC_SDHCI=m 111CONFIG_MMC_SDHCI=m
112CONFIG_NEW_LEDS=y 112CONFIG_NEW_LEDS=y
113CONFIG_LEDS_CLASS=m 113CONFIG_LEDS_CLASS=y
114CONFIG_RTC_CLASS=y 114CONFIG_RTC_CLASS=y
115CONFIG_RTC_INTF_DEV_UIE_EMUL=y 115CONFIG_RTC_INTF_DEV_UIE_EMUL=y
116CONFIG_EXT2_FS=y 116CONFIG_EXT2_FS=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 56684b51707..5eec099e0c7 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -100,6 +100,7 @@ config MACH_MX25_3DS
100 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 100 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
101 select IMX_HAVE_PLATFORM_IMX2_WDT 101 select IMX_HAVE_PLATFORM_IMX2_WDT
102 select IMX_HAVE_PLATFORM_IMXDI_RTC 102 select IMX_HAVE_PLATFORM_IMXDI_RTC
103 select IMX_HAVE_PLATFORM_IMX_I2C
103 select IMX_HAVE_PLATFORM_IMX_FB 104 select IMX_HAVE_PLATFORM_IMX_FB
104 select IMX_HAVE_PLATFORM_IMX_KEYPAD 105 select IMX_HAVE_PLATFORM_IMX_KEYPAD
105 select IMX_HAVE_PLATFORM_IMX_UART 106 select IMX_HAVE_PLATFORM_IMX_UART
@@ -238,6 +239,7 @@ config MACH_MX27_3DS
238 select SOC_IMX27 239 select SOC_IMX27
239 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 240 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
240 select IMX_HAVE_PLATFORM_IMX2_WDT 241 select IMX_HAVE_PLATFORM_IMX2_WDT
242 select IMX_HAVE_PLATFORM_IMX_I2C
241 select IMX_HAVE_PLATFORM_IMX_KEYPAD 243 select IMX_HAVE_PLATFORM_IMX_KEYPAD
242 select IMX_HAVE_PLATFORM_IMX_UART 244 select IMX_HAVE_PLATFORM_IMX_UART
243 select IMX_HAVE_PLATFORM_MXC_EHCI 245 select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -265,6 +267,7 @@ config MACH_IMX27LITE
265 bool "LogicPD MX27 LITEKIT platform" 267 bool "LogicPD MX27 LITEKIT platform"
266 select SOC_IMX27 268 select SOC_IMX27
267 select IMX_HAVE_PLATFORM_IMX_UART 269 select IMX_HAVE_PLATFORM_IMX_UART
270 select IMX_HAVE_PLATFORM_IMX_SSI
268 help 271 help
269 Include support for MX27 LITEKIT platform. This includes specific 272 Include support for MX27 LITEKIT platform. This includes specific
270 configurations for the board and its peripherals. 273 configurations for the board and its peripherals.
@@ -300,4 +303,13 @@ config MACH_MXT_TD60
300 Include support for i-MXT (aka td60) platform. This 303 Include support for i-MXT (aka td60) platform. This
301 includes specific configurations for the module and its peripherals. 304 includes specific configurations for the module and its peripherals.
302 305
306config MACH_IMX27IPCAM
307 bool "IMX27 IPCAM platform"
308 select SOC_IMX27
309 select IMX_HAVE_PLATFORM_IMX2_WDT
310 select IMX_HAVE_PLATFORM_IMX_UART
311 help
312 Include support for IMX27 IPCAM platform. This includes specific
313 configurations for the board and its peripherals.
314
303endif 315endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 77100bf2615..b85794d2799 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -9,10 +9,10 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
9obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o 9obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
10obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o 10obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
11 11
12obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o 12obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
13 13
14obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o 14obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
15obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o 15obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
16 16
17# Support for CMOS sensor interface 17# Support for CMOS sensor interface
18obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o 18obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -36,3 +36,4 @@ obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
36obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o 36obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
37obj-$(CONFIG_MACH_PCA100) += mach-pca100.o 37obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
38obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o 38obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
39obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
index 3938a563b28..dcc41728fe7 100644
--- a/arch/arm/mach-imx/clock-imx1.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -592,6 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
592 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk) 592 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
593 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) 593 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
594 _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk) 594 _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
595 _REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk)
595 _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk) 596 _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
596 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 597 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
597 _REGISTER_CLOCK(NULL, "mshc", mshc_clk) 598 _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
index daa0165b677..a65838fc061 100644
--- a/arch/arm/mach-imx/clock-imx25.c
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -228,6 +228,7 @@ DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0, 3, get_rate_esdhc1, NULL,
228DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2, NULL, NULL); 228DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2, NULL, NULL);
229DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0, 4, get_rate_esdhc2, NULL, 229DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0, 4, get_rate_esdhc2, NULL,
230 &esdhc2_ahb_clk); 230 &esdhc2_ahb_clk);
231DEFINE_CLOCK(sdma_ahb_clk, 0, CCM_CGCR0, 26, NULL, NULL, NULL);
231DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); 232DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
232DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); 233DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
233DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); 234DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
@@ -253,6 +254,7 @@ DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
253DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); 254DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL);
254DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); 255DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
255DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); 256DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
257DEFINE_CLOCK(sdma_clk, 0, CCM_CGCR2, 6, get_rate_ipg, NULL, &sdma_ahb_clk);
256DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGCR1, 13, get_rate_esdhc1, NULL, 258DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
257 &esdhc1_per_clk); 259 &esdhc1_per_clk);
258DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL, 260DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
@@ -304,6 +306,7 @@ static struct clk_lookup lookups[] = {
304 _REGISTER_CLOCK(NULL, "audmux", audmux_clk) 306 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
305 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) 307 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
306 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) 308 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
309 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
307}; 310};
308 311
309int __init mx25_clocks_init(void) 312int __init mx25_clocks_init(void)
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index 81979486218..da593657ff3 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -9,6 +9,10 @@
9#include <mach/mx1.h> 9#include <mach/mx1.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst;
13#define imx1_add_imx_fb(pdata) \
14 imx_add_imx_fb(&imx1_imx_fb_data, pdata)
15
12extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst; 16extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
13#define imx1_add_imx_i2c(pdata) \ 17#define imx1_add_imx_i2c(pdata) \
14 imx_add_imx_i2c(&imx1_imx_i2c_data, pdata) 18 imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
@@ -18,3 +22,10 @@ extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
18 imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata) 22 imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
19#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata) 23#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
20#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata) 24#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
25
26extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst;
27#define imx1_add_cspi(id, pdata) \
28 imx_add_spi_imx(&imx1_cspi_data[id], pdata)
29
30#define imx1_add_spi_imx0(pdata) imx1_add_cspi(0, pdata)
31#define imx1_add_spi_imx1(pdata) imx1_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index bde33caf1b9..b591d72f603 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -81,7 +81,11 @@ imx25_sdhci_esdhc_imx_data[] __initconst;
81 81
82extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; 82extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
83#define imx25_add_spi_imx(id, pdata) \ 83#define imx25_add_spi_imx(id, pdata) \
84 imx_add_spi_imx(&imx25_spi_imx_data[id], pdata) 84 imx_add_spi_imx(&imx25_cspi_data[id], pdata)
85#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) 85#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
86#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) 86#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
87#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) 87#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
88
89extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst;
90#define imx25_add_mxc_pwm(id) \
91 imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index e9f1769b49f..236f1495efa 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -699,7 +699,7 @@ int imx_dma_request(int channel, const char *name)
699 local_irq_restore(flags); 699 local_irq_restore(flags);
700 return -EBUSY; 700 return -EBUSY;
701 } 701 }
702 memset(imxdma, 0, sizeof(imxdma)); 702 memset(imxdma, 0, sizeof(*imxdma));
703 imxdma->name = name; 703 imxdma->name = name;
704 local_irq_restore(flags); /* request_irq() can block */ 704 local_irq_restore(flags); /* request_irq() can block */
705 705
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
new file mode 100644
index 00000000000..865daf0b09e
--- /dev/null
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -0,0 +1,80 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX25_OTG_SIC_SHIFT 29
25#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
26#define MX25_OTG_PM_BIT (1 << 24)
27
28#define MX25_H1_SIC_SHIFT 21
29#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
30#define MX25_H1_PM_BIT (1 << 8)
31#define MX25_H1_IPPUE_UP_BIT (1 << 7)
32#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
33#define MX25_H1_TLL_BIT (1 << 5)
34#define MX25_H1_USBTE_BIT (1 << 4)
35
36int mx25_initialize_usb_hw(int port, unsigned int flags)
37{
38 unsigned int v;
39
40 v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
41
42 switch (port) {
43 case 0: /* OTG port */
44 v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT);
45 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
46
47 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
48 v |= MX25_OTG_PM_BIT;
49
50 break;
51 case 1: /* H1 port */
52 v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT |
53 MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
54 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
55
56 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
57 v |= MX25_H1_PM_BIT;
58
59 if (!(flags & MXC_EHCI_TTL_ENABLED))
60 v |= MX25_H1_TLL_BIT;
61
62 if (flags & MXC_EHCI_INTERNAL_PHY)
63 v |= MX25_H1_USBTE_BIT;
64
65 if (flags & MXC_EHCI_IPPUE_DOWN)
66 v |= MX25_H1_IPPUE_DOWN_BIT;
67
68 if (flags & MXC_EHCI_IPPUE_UP)
69 v |= MX25_H1_IPPUE_UP_BIT;
70
71 break;
72 default:
73 return -EINVAL;
74 }
75
76 writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
77
78 return 0;
79}
80
diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c
new file mode 100644
index 00000000000..fa69419eabd
--- /dev/null
+++ b/arch/arm/mach-imx/ehci-imx27.c
@@ -0,0 +1,82 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX27_OTG_SIC_SHIFT 29
25#define MX27_OTG_SIC_MASK (0x3 << MX27_OTG_SIC_SHIFT)
26#define MX27_OTG_PM_BIT (1 << 24)
27
28#define MX27_H2_SIC_SHIFT 21
29#define MX27_H2_SIC_MASK (0x3 << MX27_H2_SIC_SHIFT)
30#define MX27_H2_PM_BIT (1 << 16)
31#define MX27_H2_DT_BIT (1 << 5)
32
33#define MX27_H1_SIC_SHIFT 13
34#define MX27_H1_SIC_MASK (0x3 << MX27_H1_SIC_SHIFT)
35#define MX27_H1_PM_BIT (1 << 8)
36#define MX27_H1_DT_BIT (1 << 4)
37
38int mx27_initialize_usb_hw(int port, unsigned int flags)
39{
40 unsigned int v;
41
42 v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
43
44 switch (port) {
45 case 0: /* OTG port */
46 v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT);
47 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT;
48
49 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
50 v |= MX27_OTG_PM_BIT;
51 break;
52 case 1: /* H1 port */
53 v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT);
54 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT;
55
56 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
57 v |= MX27_H1_PM_BIT;
58
59 if (!(flags & MXC_EHCI_TTL_ENABLED))
60 v |= MX27_H1_DT_BIT;
61
62 break;
63 case 2: /* H2 port */
64 v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT);
65 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT;
66
67 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
68 v |= MX27_H2_PM_BIT;
69
70 if (!(flags & MXC_EHCI_TTL_ENABLED))
71 v |= MX27_H2_DT_BIT;
72
73 break;
74 default:
75 return -EINVAL;
76 }
77
78 writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
79
80 return 0;
81}
82
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 275c8589d79..fa5288018ba 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -249,7 +249,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
249 249
250#define ADS7846_PENDOWN (GPIO_PORTD | 25) 250#define ADS7846_PENDOWN (GPIO_PORTD | 25)
251 251
252static void ads7846_dev_init(void) 252static void __maybe_unused ads7846_dev_init(void)
253{ 253{
254 if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) { 254 if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
255 printk(KERN_ERR "can't get ads746 pen down GPIO\n"); 255 printk(KERN_ERR "can't get ads746 pen down GPIO\n");
@@ -268,7 +268,8 @@ static struct ads7846_platform_data ads7846_config __initdata = {
268 .keep_vref_on = 1, 268 .keep_vref_on = 1,
269}; 269};
270 270
271static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = { 271static struct spi_board_info __maybe_unused
272 eukrea_mbimx27_spi_board_info[] __initdata = {
272 [0] = { 273 [0] = {
273 .modalias = "ads7846", 274 .modalias = "ads7846",
274 .bus_num = 0, 275 .bus_num = 0,
@@ -357,13 +358,11 @@ void __init eukrea_mbimx27_baseboard_init(void)
357 ads7846_dev_init(); 358 ads7846_dev_init();
358#endif 359#endif
359 360
360#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
361 /* SPI_CS0 init */ 361 /* SPI_CS0 init */
362 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT); 362 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
363 imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data); 363 imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
364 spi_register_board_info(eukrea_mbimx27_spi_board_info, 364 spi_register_board_info(eukrea_mbimx27_spi_board_info,
365 ARRAY_SIZE(eukrea_mbimx27_spi_board_info)); 365 ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
366#endif
367 366
368 /* Leds configuration */ 367 /* Leds configuration */
369 mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT); 368 mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 6cf04da2456..759299bb035 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -209,17 +209,25 @@ static struct platform_device serial_device = {
209}; 209};
210#endif 210#endif
211 211
212#if defined(CONFIG_USB_ULPI) 212static int eukrea_cpuimx27_otg_init(struct platform_device *pdev)
213{
214 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
215}
216
213static struct mxc_usbh_platform_data otg_pdata __initdata = { 217static struct mxc_usbh_platform_data otg_pdata __initdata = {
218 .init = eukrea_cpuimx27_otg_init,
214 .portsc = MXC_EHCI_MODE_ULPI, 219 .portsc = MXC_EHCI_MODE_ULPI,
215 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
216}; 220};
217 221
222static int eukrea_cpuimx27_usbh2_init(struct platform_device *pdev)
223{
224 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
225}
226
218static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 227static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
228 .init = eukrea_cpuimx27_usbh2_init,
219 .portsc = MXC_EHCI_MODE_ULPI, 229 .portsc = MXC_EHCI_MODE_ULPI,
220 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
221}; 230};
222#endif
223 231
224static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 232static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
225 .operating_mode = FSL_USB2_DR_DEVICE, 233 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -273,21 +281,19 @@ static void __init eukrea_cpuimx27_init(void)
273 platform_device_register(&serial_device); 281 platform_device_register(&serial_device);
274#endif 282#endif
275 283
276#if defined(CONFIG_USB_ULPI)
277 if (otg_mode_host) { 284 if (otg_mode_host) {
278 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 285 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
279 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 286 ULPI_OTG_DRVVBUS_EXT);
280 287 if (otg_pdata.otg)
281 imx27_add_mxc_ehci_otg(&otg_pdata); 288 imx27_add_mxc_ehci_otg(&otg_pdata);
289 } else {
290 imx27_add_fsl_usb2_udc(&otg_device_pdata);
282 } 291 }
283 292
284 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 293 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
285 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 294 ULPI_OTG_DRVVBUS_EXT);
286 295 if (usbh2_pdata.otg)
287 imx27_add_mxc_ehci_hs(2, &usbh2_pdata); 296 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
288#endif
289 if (!otg_mode_host)
290 imx27_add_fsl_usb2_udc(&otg_device_pdata);
291 297
292#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD 298#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
293 eukrea_mbimx27_baseboard_init(); 299 eukrea_mbimx27_baseboard_init();
@@ -304,9 +310,10 @@ static struct sys_timer eukrea_cpuimx27_timer = {
304}; 310};
305 311
306MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") 312MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
307 .boot_params = MX27_PHYS_OFFSET + 0x100, 313 .boot_params = MX27_PHYS_OFFSET + 0x100,
308 .map_io = mx27_map_io, 314 .map_io = mx27_map_io,
309 .init_irq = mx27_init_irq, 315 .init_early = imx27_init_early,
310 .init_machine = eukrea_cpuimx27_init, 316 .init_irq = mx27_init_irq,
311 .timer = &eukrea_cpuimx27_timer, 317 .timer = &eukrea_cpuimx27_timer,
318 .init_machine = eukrea_cpuimx27_init,
312MACHINE_END 319MACHINE_END
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index eb395aba923..9da8d18eeb0 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -84,15 +84,25 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
84 }, 84 },
85}; 85};
86 86
87static int eukrea_cpuimx25_otg_init(struct platform_device *pdev)
88{
89 return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
90}
91
87static const struct mxc_usbh_platform_data otg_pdata __initconst = { 92static const struct mxc_usbh_platform_data otg_pdata __initconst = {
93 .init = eukrea_cpuimx25_otg_init,
88 .portsc = MXC_EHCI_MODE_UTMI, 94 .portsc = MXC_EHCI_MODE_UTMI,
89 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
90}; 95};
91 96
97static int eukrea_cpuimx25_usbh2_init(struct platform_device *pdev)
98{
99 return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
100 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
101}
102
92static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { 103static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
104 .init = eukrea_cpuimx25_usbh2_init,
93 .portsc = MXC_EHCI_MODE_SERIAL, 105 .portsc = MXC_EHCI_MODE_SERIAL,
94 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
95 MXC_EHCI_IPPUE_DOWN,
96}; 106};
97 107
98static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 108static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -153,9 +163,10 @@ static struct sys_timer eukrea_cpuimx25_timer = {
153 163
154MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25") 164MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
155 /* Maintainer: Eukrea Electromatique */ 165 /* Maintainer: Eukrea Electromatique */
156 .boot_params = MX25_PHYS_OFFSET + 0x100, 166 .boot_params = MX25_PHYS_OFFSET + 0x100,
157 .map_io = mx25_map_io, 167 .map_io = mx25_map_io,
158 .init_irq = mx25_init_irq, 168 .init_early = imx25_init_early,
159 .init_machine = eukrea_cpuimx25_init, 169 .init_irq = mx25_init_irq,
160 .timer = &eukrea_cpuimx25_timer, 170 .timer = &eukrea_cpuimx25_timer,
171 .init_machine = eukrea_cpuimx25_init,
161MACHINE_END 172MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 40a3666ea63..d7e0d219726 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -30,6 +30,7 @@
30#include <linux/gpio_keys.h> 30#include <linux/gpio_keys.h>
31#include <linux/input.h> 31#include <linux/input.h>
32#include <linux/gpio.h> 32#include <linux/gpio.h>
33#include <linux/delay.h>
33#include <asm/mach-types.h> 34#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
35#include <asm/mach/time.h> 36#include <asm/mach/time.h>
@@ -66,6 +67,11 @@ static const int visstrim_m10_pins[] __initconst = {
66 PD15_AOUT_FEC_COL, 67 PD15_AOUT_FEC_COL,
67 PD16_AIN_FEC_TX_ER, 68 PD16_AIN_FEC_TX_ER,
68 PF23_AIN_FEC_TX_EN, 69 PF23_AIN_FEC_TX_EN,
70 /* SSI1 */
71 PC20_PF_SSI1_FS,
72 PC21_PF_SSI1_RXD,
73 PC22_PF_SSI1_TXD,
74 PC23_PF_SSI1_CLK,
69 /* SDHC1 */ 75 /* SDHC1 */
70 PE18_PF_SD1_D0, 76 PE18_PF_SD1_D0,
71 PE19_PF_SD1_D1, 77 PE19_PF_SD1_D1,
@@ -204,20 +210,30 @@ static struct i2c_board_info visstrim_m10_i2c_devices[] = {
204 I2C_BOARD_INFO("pca9555", 0x20), 210 I2C_BOARD_INFO("pca9555", 0x20),
205 .platform_data = &visstrim_m10_pca9555_pdata, 211 .platform_data = &visstrim_m10_pca9555_pdata,
206 }, 212 },
213 {
214 I2C_BOARD_INFO("tlv320aic32x4", 0x18),
215 }
207}; 216};
208 217
209/* USB OTG */ 218/* USB OTG */
210static int otg_phy_init(struct platform_device *pdev) 219static int otg_phy_init(struct platform_device *pdev)
211{ 220{
212 gpio_set_value(OTG_PHY_CS_GPIO, 0); 221 gpio_set_value(OTG_PHY_CS_GPIO, 0);
213 return 0; 222
223 mdelay(10);
224
225 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
214} 226}
215 227
216static const struct mxc_usbh_platform_data 228static const struct mxc_usbh_platform_data
217visstrim_m10_usbotg_pdata __initconst = { 229visstrim_m10_usbotg_pdata __initconst = {
218 .init = otg_phy_init, 230 .init = otg_phy_init,
219 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 231 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
220 .flags = MXC_EHCI_POWER_PINS_ENABLED, 232};
233
234/* SSI */
235static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
236 .flags = IMX_SSI_DMA | IMX_SSI_SYN,
221}; 237};
222 238
223static void __init visstrim_m10_board_init(void) 239static void __init visstrim_m10_board_init(void)
@@ -229,6 +245,7 @@ static void __init visstrim_m10_board_init(void)
229 if (ret) 245 if (ret)
230 pr_err("Failed to setup pins (%d)\n", ret); 246 pr_err("Failed to setup pins (%d)\n", ret);
231 247
248 imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
232 imx27_add_imx_uart0(&uart_pdata); 249 imx27_add_imx_uart0(&uart_pdata);
233 250
234 i2c_register_board_info(0, visstrim_m10_i2c_devices, 251 i2c_register_board_info(0, visstrim_m10_i2c_devices,
@@ -251,9 +268,10 @@ static struct sys_timer visstrim_m10_timer = {
251}; 268};
252 269
253MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") 270MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
254 .boot_params = MX27_PHYS_OFFSET + 0x100, 271 .boot_params = MX27_PHYS_OFFSET + 0x100,
255 .map_io = mx27_map_io, 272 .map_io = mx27_map_io,
256 .init_irq = mx27_init_irq, 273 .init_early = imx27_init_early,
257 .init_machine = visstrim_m10_board_init, 274 .init_irq = mx27_init_irq,
258 .timer = &visstrim_m10_timer, 275 .timer = &visstrim_m10_timer,
276 .init_machine = visstrim_m10_board_init,
259MACHINE_END 277MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
new file mode 100644
index 00000000000..9be6cd6fbf8
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -0,0 +1,78 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <asm/mach-types.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/time.h>
20#include <mach/hardware.h>
21#include <mach/common.h>
22#include <mach/iomux-mx27.h>
23
24#include "devices-imx27.h"
25
26static const int mx27ipcam_pins[] __initconst = {
27 /* UART1 */
28 PE12_PF_UART1_TXD,
29 PE13_PF_UART1_RXD,
30 /* FEC */
31 PD0_AIN_FEC_TXD0,
32 PD1_AIN_FEC_TXD1,
33 PD2_AIN_FEC_TXD2,
34 PD3_AIN_FEC_TXD3,
35 PD4_AOUT_FEC_RX_ER,
36 PD5_AOUT_FEC_RXD1,
37 PD6_AOUT_FEC_RXD2,
38 PD7_AOUT_FEC_RXD3,
39 PD8_AF_FEC_MDIO,
40 PD9_AIN_FEC_MDC,
41 PD10_AOUT_FEC_CRS,
42 PD11_AOUT_FEC_TX_CLK,
43 PD12_AOUT_FEC_RXD0,
44 PD13_AOUT_FEC_RX_DV,
45 PD14_AOUT_FEC_RX_CLK,
46 PD15_AOUT_FEC_COL,
47 PD16_AIN_FEC_TX_ER,
48 PF23_AIN_FEC_TX_EN,
49};
50
51static void __init mx27ipcam_init(void)
52{
53 mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins),
54 "mx27ipcam");
55
56 imx27_add_imx_uart0(NULL);
57 imx27_add_fec(NULL);
58 imx27_add_imx2_wdt(NULL);
59}
60
61static void __init mx27ipcam_timer_init(void)
62{
63 mx27_clocks_init(25000000);
64}
65
66static struct sys_timer mx27ipcam_timer = {
67 .init = mx27ipcam_timer_init,
68};
69
70MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
71 /* maintainer: Freescale Semiconductor, Inc. */
72 .boot_params = MX27_PHYS_OFFSET + 0x100,
73 .map_io = mx27_map_io,
74 .init_early = imx27_init_early,
75 .init_irq = mx27_init_irq,
76 .timer = &mx27ipcam_timer,
77 .init_machine = mx27ipcam_init,
78MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 3a1202e4721..841140516ed 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -75,9 +75,10 @@ static struct sys_timer mx27lite_timer = {
75}; 75};
76 76
77MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") 77MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
78 .boot_params = MX27_PHYS_OFFSET + 0x100, 78 .boot_params = MX27_PHYS_OFFSET + 0x100,
79 .map_io = mx27_map_io, 79 .map_io = mx27_map_io,
80 .init_irq = mx27_init_irq, 80 .init_early = imx27_init_early,
81 .init_machine = mx27lite_init, 81 .init_irq = mx27_init_irq,
82 .timer = &mx27lite_timer, 82 .timer = &mx27lite_timer,
83 .init_machine = mx27lite_init,
83MACHINE_END 84MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 1f446e5eb63..47cf56ac6d5 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -144,17 +144,19 @@ struct sys_timer mx1ads_timer = {
144 144
145MACHINE_START(MX1ADS, "Freescale MX1ADS") 145MACHINE_START(MX1ADS, "Freescale MX1ADS")
146 /* Maintainer: Sascha Hauer, Pengutronix */ 146 /* Maintainer: Sascha Hauer, Pengutronix */
147 .boot_params = MX1_PHYS_OFFSET + 0x100, 147 .boot_params = MX1_PHYS_OFFSET + 0x100,
148 .map_io = mx1_map_io, 148 .map_io = mx1_map_io,
149 .init_irq = mx1_init_irq, 149 .init_early = imx1_init_early,
150 .timer = &mx1ads_timer, 150 .init_irq = mx1_init_irq,
151 .init_machine = mx1ads_init, 151 .timer = &mx1ads_timer,
152 .init_machine = mx1ads_init,
152MACHINE_END 153MACHINE_END
153 154
154MACHINE_START(MXLADS, "Freescale MXLADS") 155MACHINE_START(MXLADS, "Freescale MXLADS")
155 .boot_params = MX1_PHYS_OFFSET + 0x100, 156 .boot_params = MX1_PHYS_OFFSET + 0x100,
156 .map_io = mx1_map_io, 157 .map_io = mx1_map_io,
157 .init_irq = mx1_init_irq, 158 .init_early = imx1_init_early,
158 .timer = &mx1ads_timer, 159 .init_irq = mx1_init_irq,
159 .init_machine = mx1ads_init, 160 .timer = &mx1ads_timer,
161 .init_machine = mx1ads_init,
160MACHINE_END 162MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 0a372577c2a..fa52a1086ea 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -304,9 +304,10 @@ static struct sys_timer mx21ads_timer = {
304 304
305MACHINE_START(MX21ADS, "Freescale i.MX21ADS") 305MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
306 /* maintainer: Freescale Semiconductor, Inc. */ 306 /* maintainer: Freescale Semiconductor, Inc. */
307 .boot_params = MX21_PHYS_OFFSET + 0x100, 307 .boot_params = MX21_PHYS_OFFSET + 0x100,
308 .map_io = mx21ads_map_io, 308 .map_io = mx21ads_map_io,
309 .init_irq = mx21_init_irq, 309 .init_early = imx21_init_early,
310 .init_machine = mx21ads_board_init, 310 .init_irq = mx21_init_irq,
311 .timer = &mx21ads_timer, 311 .timer = &mx21ads_timer,
312 .init_machine = mx21ads_board_init,
312MACHINE_END 313MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 8382e790207..06da438282a 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -103,14 +103,18 @@ static iomux_v3_cfg_t mx25pdk_pads[] = {
103 MX25_PAD_SD1_DATA1__SD1_DATA1, 103 MX25_PAD_SD1_DATA1__SD1_DATA1,
104 MX25_PAD_SD1_DATA2__SD1_DATA2, 104 MX25_PAD_SD1_DATA2__SD1_DATA2,
105 MX25_PAD_SD1_DATA3__SD1_DATA3, 105 MX25_PAD_SD1_DATA3__SD1_DATA3,
106
107 /* I2C1 */
108 MX25_PAD_I2C1_CLK__I2C1_CLK,
109 MX25_PAD_I2C1_DAT__I2C1_DAT,
106}; 110};
107 111
108static const struct fec_platform_data mx25_fec_pdata __initconst = { 112static const struct fec_platform_data mx25_fec_pdata __initconst = {
109 .phy = PHY_INTERFACE_MODE_RMII, 113 .phy = PHY_INTERFACE_MODE_RMII,
110}; 114};
111 115
112#define FEC_ENABLE_GPIO 35 116#define FEC_ENABLE_GPIO IMX_GPIO_NR(2, 3)
113#define FEC_RESET_B_GPIO 104 117#define FEC_RESET_B_GPIO IMX_GPIO_NR(4, 8)
114 118
115static void __init mx25pdk_fec_reset(void) 119static void __init mx25pdk_fec_reset(void)
116{ 120{
@@ -185,9 +189,14 @@ static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
185 .keymap_size = ARRAY_SIZE(mx25pdk_keymap), 189 .keymap_size = ARRAY_SIZE(mx25pdk_keymap),
186}; 190};
187 191
192static int mx25pdk_usbh2_init(struct platform_device *pdev)
193{
194 return mx25_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
195}
196
188static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { 197static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
198 .init = mx25pdk_usbh2_init,
189 .portsc = MXC_EHCI_MODE_SERIAL, 199 .portsc = MXC_EHCI_MODE_SERIAL,
190 .flags = MXC_EHCI_INTERNAL_PHY,
191}; 200};
192 201
193static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 202static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -195,6 +204,10 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
195 .phy_mode = FSL_USB2_PHY_UTMI, 204 .phy_mode = FSL_USB2_PHY_UTMI,
196}; 205};
197 206
207static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
208 .bitrate = 100000,
209};
210
198static void __init mx25pdk_init(void) 211static void __init mx25pdk_init(void)
199{ 212{
200 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, 213 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
@@ -213,6 +226,7 @@ static void __init mx25pdk_init(void)
213 imx25_add_imx_keypad(&mx25pdk_keymap_data); 226 imx25_add_imx_keypad(&mx25pdk_keymap_data);
214 227
215 imx25_add_sdhci_esdhc_imx(0, NULL); 228 imx25_add_sdhci_esdhc_imx(0, NULL);
229 imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
216} 230}
217 231
218static void __init mx25pdk_timer_init(void) 232static void __init mx25pdk_timer_init(void)
@@ -226,10 +240,10 @@ static struct sys_timer mx25pdk_timer = {
226 240
227MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") 241MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
228 /* Maintainer: Freescale Semiconductor, Inc. */ 242 /* Maintainer: Freescale Semiconductor, Inc. */
229 .boot_params = MX25_PHYS_OFFSET + 0x100, 243 .boot_params = MX25_PHYS_OFFSET + 0x100,
230 .map_io = mx25_map_io, 244 .map_io = mx25_map_io,
231 .init_irq = mx25_init_irq, 245 .init_early = imx25_init_early,
232 .init_machine = mx25pdk_init, 246 .init_irq = mx25_init_irq,
233 .timer = &mx25pdk_timer, 247 .timer = &mx25pdk_timer,
248 .init_machine = mx25pdk_init,
234MACHINE_END 249MACHINE_END
235
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 164331518bd..614b3c00c4a 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -98,6 +98,9 @@ static const int mx27pdk_pins[] __initconst = {
98 PD22_PF_CSPI2_SCLK, 98 PD22_PF_CSPI2_SCLK,
99 PD23_PF_CSPI2_MISO, 99 PD23_PF_CSPI2_MISO,
100 PD24_PF_CSPI2_MOSI, 100 PD24_PF_CSPI2_MOSI,
101 /* I2C1 */
102 PD17_PF_I2C_DATA,
103 PD18_PF_I2C_CLK,
101}; 104};
102 105
103static const struct imxuart_platform_data uart_pdata __initconst = { 106static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -159,13 +162,15 @@ static int otg_phy_init(void)
159 return 0; 162 return 0;
160} 163}
161 164
162#if defined(CONFIG_USB_ULPI) 165static int mx27_3ds_otg_init(struct platform_device *pdev)
166{
167 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
168}
163 169
164static struct mxc_usbh_platform_data otg_pdata __initdata = { 170static struct mxc_usbh_platform_data otg_pdata __initdata = {
171 .init = mx27_3ds_otg_init,
165 .portsc = MXC_EHCI_MODE_ULPI, 172 .portsc = MXC_EHCI_MODE_ULPI,
166 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
167}; 173};
168#endif
169 174
170static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 175static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
171 .operating_mode = FSL_USB2_DR_DEVICE, 176 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -216,7 +221,7 @@ static struct regulator_init_data vgen_init = {
216 .consumer_supplies = vgen_consumers, 221 .consumer_supplies = vgen_consumers,
217}; 222};
218 223
219static struct mc13783_regulator_init_data mx27_3ds_regulators[] = { 224static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
220 { 225 {
221 .id = MC13783_REG_VMMC1, 226 .id = MC13783_REG_VMMC1,
222 .init_data = &vmmc1_init, 227 .init_data = &vmmc1_init,
@@ -227,10 +232,10 @@ static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
227}; 232};
228 233
229/* MC13783 */ 234/* MC13783 */
230static struct mc13783_platform_data mc13783_pdata __initdata = { 235static struct mc13xxx_platform_data mc13783_pdata __initdata = {
231 .regulators = mx27_3ds_regulators, 236 .regulators = mx27_3ds_regulators,
232 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), 237 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
233 .flags = MC13783_USE_REGULATOR, 238 .flags = MC13XXX_USE_REGULATOR,
234}; 239};
235 240
236/* SPI */ 241/* SPI */
@@ -253,6 +258,9 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
253 }, 258 },
254}; 259};
255 260
261static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
262 .bitrate = 100000,
263};
256 264
257static void __init mx27pdk_init(void) 265static void __init mx27pdk_init(void)
258{ 266{
@@ -265,14 +273,15 @@ static void __init mx27pdk_init(void)
265 imx27_add_mxc_mmc(0, &sdhc1_pdata); 273 imx27_add_mxc_mmc(0, &sdhc1_pdata);
266 imx27_add_imx2_wdt(NULL); 274 imx27_add_imx2_wdt(NULL);
267 otg_phy_init(); 275 otg_phy_init();
268#if defined(CONFIG_USB_ULPI) 276
269 if (otg_mode_host) { 277 if (otg_mode_host) {
270 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 278 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
271 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 279 ULPI_OTG_DRVVBUS_EXT);
272 280
273 imx27_add_mxc_ehci_otg(&otg_pdata); 281 if (otg_pdata.otg)
282 imx27_add_mxc_ehci_otg(&otg_pdata);
274 } 283 }
275#endif 284
276 if (!otg_mode_host) 285 if (!otg_mode_host)
277 imx27_add_fsl_usb2_udc(&otg_device_pdata); 286 imx27_add_fsl_usb2_udc(&otg_device_pdata);
278 287
@@ -282,6 +291,7 @@ static void __init mx27pdk_init(void)
282 291
283 if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT)) 292 if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
284 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); 293 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
294 imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
285} 295}
286 296
287static void __init mx27pdk_timer_init(void) 297static void __init mx27pdk_timer_init(void)
@@ -295,9 +305,10 @@ static struct sys_timer mx27pdk_timer = {
295 305
296MACHINE_START(MX27_3DS, "Freescale MX27PDK") 306MACHINE_START(MX27_3DS, "Freescale MX27PDK")
297 /* maintainer: Freescale Semiconductor, Inc. */ 307 /* maintainer: Freescale Semiconductor, Inc. */
298 .boot_params = MX27_PHYS_OFFSET + 0x100, 308 .boot_params = MX27_PHYS_OFFSET + 0x100,
299 .map_io = mx27_map_io, 309 .map_io = mx27_map_io,
300 .init_irq = mx27_init_irq, 310 .init_early = imx27_init_early,
301 .init_machine = mx27pdk_init, 311 .init_irq = mx27_init_irq,
302 .timer = &mx27pdk_timer, 312 .timer = &mx27pdk_timer,
313 .init_machine = mx27pdk_init,
303MACHINE_END 314MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index b832f960fec..367d1e4384c 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -344,9 +344,10 @@ static void __init mx27ads_map_io(void)
344 344
345MACHINE_START(MX27ADS, "Freescale i.MX27ADS") 345MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
346 /* maintainer: Freescale Semiconductor, Inc. */ 346 /* maintainer: Freescale Semiconductor, Inc. */
347 .boot_params = MX27_PHYS_OFFSET + 0x100, 347 .boot_params = MX27_PHYS_OFFSET + 0x100,
348 .map_io = mx27ads_map_io, 348 .map_io = mx27ads_map_io,
349 .init_irq = mx27_init_irq, 349 .init_early = imx27_init_early,
350 .init_machine = mx27ads_board_init, 350 .init_irq = mx27_init_irq,
351 .timer = &mx27ads_timer, 351 .timer = &mx27ads_timer,
352 .init_machine = mx27ads_board_init,
352MACHINE_END 353MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 4ce71b0401d..69787c30c32 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -266,10 +266,10 @@ static struct sys_timer mxt_td60_timer = {
266 266
267MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") 267MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
268 /* maintainer: Maxtrack Industrial */ 268 /* maintainer: Maxtrack Industrial */
269 .boot_params = MX27_PHYS_OFFSET + 0x100, 269 .boot_params = MX27_PHYS_OFFSET + 0x100,
270 .map_io = mx27_map_io, 270 .map_io = mx27_map_io,
271 .init_irq = mx27_init_irq, 271 .init_early = imx27_init_early,
272 .init_machine = mxt_td60_board_init, 272 .init_irq = mx27_init_irq,
273 .timer = &mxt_td60_timer, 273 .timer = &mxt_td60_timer,
274 .init_machine = mxt_td60_board_init,
274MACHINE_END 275MACHINE_END
275
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index cccc0a0a9c7..63e18255677 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -187,7 +187,6 @@ static struct i2c_board_info pca100_i2c_devices[] = {
187 } 187 }
188}; 188};
189 189
190#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
191static struct spi_eeprom at25320 = { 190static struct spi_eeprom at25320 = {
192 .name = "at25320an", 191 .name = "at25320an",
193 .byte_len = 4096, 192 .byte_len = 4096,
@@ -211,7 +210,6 @@ static const struct spi_imx_master pca100_spi0_data __initconst = {
211 .chipselect = pca100_spi_cs, 210 .chipselect = pca100_spi_cs,
212 .num_chipselect = ARRAY_SIZE(pca100_spi_cs), 211 .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
213}; 212};
214#endif
215 213
216static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) 214static void pca100_ac97_warm_reset(struct snd_ac97 *ac97)
217{ 215{
@@ -269,31 +267,33 @@ static const struct imxmmc_platform_data sdhc_pdata __initconst = {
269 .exit = pca100_sdhc2_exit, 267 .exit = pca100_sdhc2_exit,
270}; 268};
271 269
272#if defined(CONFIG_USB_ULPI)
273static int otg_phy_init(struct platform_device *pdev) 270static int otg_phy_init(struct platform_device *pdev)
274{ 271{
275 gpio_set_value(OTG_PHY_CS_GPIO, 0); 272 gpio_set_value(OTG_PHY_CS_GPIO, 0);
276 return 0; 273
274 mdelay(10);
275
276 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
277} 277}
278 278
279static struct mxc_usbh_platform_data otg_pdata __initdata = { 279static struct mxc_usbh_platform_data otg_pdata __initdata = {
280 .init = otg_phy_init, 280 .init = otg_phy_init,
281 .portsc = MXC_EHCI_MODE_ULPI, 281 .portsc = MXC_EHCI_MODE_ULPI,
282 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
283}; 282};
284 283
285static int usbh2_phy_init(struct platform_device *pdev) 284static int usbh2_phy_init(struct platform_device *pdev)
286{ 285{
287 gpio_set_value(USBH2_PHY_CS_GPIO, 0); 286 gpio_set_value(USBH2_PHY_CS_GPIO, 0);
288 return 0; 287
288 mdelay(10);
289
290 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
289} 291}
290 292
291static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 293static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
292 .init = usbh2_phy_init, 294 .init = usbh2_phy_init,
293 .portsc = MXC_EHCI_MODE_ULPI, 295 .portsc = MXC_EHCI_MODE_ULPI,
294 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
295}; 296};
296#endif
297 297
298static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 298static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
299 .operating_mode = FSL_USB2_DR_DEVICE, 299 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -389,36 +389,33 @@ static void __init pca100_init(void)
389 389
390 imx27_add_imx_i2c(1, &pca100_i2c1_data); 390 imx27_add_imx_i2c(1, &pca100_i2c1_data);
391 391
392#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
393 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); 392 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
394 mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN); 393 mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
395 spi_register_board_info(pca100_spi_board_info, 394 spi_register_board_info(pca100_spi_board_info,
396 ARRAY_SIZE(pca100_spi_board_info)); 395 ARRAY_SIZE(pca100_spi_board_info));
397 imx27_add_spi_imx0(&pca100_spi0_data); 396 imx27_add_spi_imx0(&pca100_spi0_data);
398#endif
399 397
400 gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); 398 gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
401 gpio_direction_output(OTG_PHY_CS_GPIO, 1); 399 gpio_direction_output(OTG_PHY_CS_GPIO, 1);
402 gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs"); 400 gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
403 gpio_direction_output(USBH2_PHY_CS_GPIO, 1); 401 gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
404 402
405#if defined(CONFIG_USB_ULPI)
406 if (otg_mode_host) { 403 if (otg_mode_host) {
407 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 404 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
408 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 405 ULPI_OTG_DRVVBUS_EXT);
409 406
410 imx27_add_mxc_ehci_otg(&otg_pdata); 407 if (otg_pdata.otg)
408 imx27_add_mxc_ehci_otg(&otg_pdata);
409 } else {
410 gpio_set_value(OTG_PHY_CS_GPIO, 0);
411 imx27_add_fsl_usb2_udc(&otg_device_pdata);
411 } 412 }
412 413
413 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 414 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
414 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 415 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
415 416
416 imx27_add_mxc_ehci_hs(2, &usbh2_pdata); 417 if (usbh2_pdata.otg)
417#endif 418 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
418 if (!otg_mode_host) {
419 gpio_set_value(OTG_PHY_CS_GPIO, 0);
420 imx27_add_fsl_usb2_udc(&otg_device_pdata);
421 }
422 419
423 imx27_add_imx_fb(&pca100_fb_data); 420 imx27_add_imx_fb(&pca100_fb_data);
424 421
@@ -437,10 +434,10 @@ static struct sys_timer pca100_timer = {
437}; 434};
438 435
439MACHINE_START(PCA100, "phyCARD-i.MX27") 436MACHINE_START(PCA100, "phyCARD-i.MX27")
440 .boot_params = MX27_PHYS_OFFSET + 0x100, 437 .boot_params = MX27_PHYS_OFFSET + 0x100,
441 .map_io = mx27_map_io, 438 .map_io = mx27_map_io,
442 .init_irq = mx27_init_irq, 439 .init_early = imx27_init_early,
443 .init_machine = pca100_init, 440 .init_irq = mx27_init_irq,
444 .timer = &pca100_timer, 441 .init_machine = pca100_init,
442 .timer = &pca100_timer,
445MACHINE_END 443MACHINE_END
446
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 505614803bc..38c77084b61 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -252,7 +252,7 @@ static struct regulator_init_data cam_data = {
252 .consumer_supplies = cam_consumers, 252 .consumer_supplies = cam_consumers,
253}; 253};
254 254
255static struct mc13783_regulator_init_data pcm038_regulators[] = { 255static struct mc13xxx_regulator_init_data pcm038_regulators[] = {
256 { 256 {
257 .id = MC13783_REG_VCAM, 257 .id = MC13783_REG_VCAM,
258 .init_data = &cam_data, 258 .init_data = &cam_data,
@@ -262,11 +262,11 @@ static struct mc13783_regulator_init_data pcm038_regulators[] = {
262 }, 262 },
263}; 263};
264 264
265static struct mc13783_platform_data pcm038_pmic = { 265static struct mc13xxx_platform_data pcm038_pmic = {
266 .regulators = pcm038_regulators, 266 .regulators = pcm038_regulators,
267 .num_regulators = ARRAY_SIZE(pcm038_regulators), 267 .num_regulators = ARRAY_SIZE(pcm038_regulators),
268 .flags = MC13783_USE_ADC | MC13783_USE_REGULATOR | 268 .flags = MC13XXX_USE_ADC | MC13XXX_USE_REGULATOR |
269 MC13783_USE_TOUCHSCREEN, 269 MC13XXX_USE_TOUCHSCREEN,
270}; 270};
271 271
272static struct spi_board_info pcm038_spi_board_info[] __initdata = { 272static struct spi_board_info pcm038_spi_board_info[] __initdata = {
@@ -281,9 +281,15 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
281 } 281 }
282}; 282};
283 283
284static int pcm038_usbh2_init(struct platform_device *pdev)
285{
286 return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
287 MXC_EHCI_INTERFACE_DIFF_UNI);
288}
289
284static const struct mxc_usbh_platform_data usbh2_pdata __initconst = { 290static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
291 .init = pcm038_usbh2_init,
285 .portsc = MXC_EHCI_MODE_ULPI, 292 .portsc = MXC_EHCI_MODE_ULPI,
286 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
287}; 293};
288 294
289static void __init pcm038_init(void) 295static void __init pcm038_init(void)
@@ -340,9 +346,10 @@ static struct sys_timer pcm038_timer = {
340}; 346};
341 347
342MACHINE_START(PCM038, "phyCORE-i.MX27") 348MACHINE_START(PCM038, "phyCORE-i.MX27")
343 .boot_params = MX27_PHYS_OFFSET + 0x100, 349 .boot_params = MX27_PHYS_OFFSET + 0x100,
344 .map_io = mx27_map_io, 350 .map_io = mx27_map_io,
345 .init_irq = mx27_init_irq, 351 .init_early = imx27_init_early,
346 .init_machine = pcm038_init, 352 .init_irq = mx27_init_irq,
347 .timer = &pcm038_timer, 353 .timer = &pcm038_timer,
354 .init_machine = pcm038_init,
348MACHINE_END 355MACHINE_END
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index eae878f306c..dcaee043628 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -145,10 +145,11 @@ static struct sys_timer scb9328_timer = {
145}; 145};
146 146
147MACHINE_START(SCB9328, "Synertronixx scb9328") 147MACHINE_START(SCB9328, "Synertronixx scb9328")
148 /* Sascha Hauer */ 148 /* Sascha Hauer */
149 .boot_params = 0x08000100, 149 .boot_params = 0x08000100,
150 .map_io = mx1_map_io, 150 .map_io = mx1_map_io,
151 .init_irq = mx1_init_irq, 151 .init_early = imx1_init_early,
152 .timer = &scb9328_timer, 152 .init_irq = mx1_init_irq,
153 .init_machine = scb9328_init, 153 .timer = &scb9328_timer,
154 .init_machine = scb9328_init,
154MACHINE_END 155MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 729ae0915af..2e482ba5a0e 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -23,6 +23,9 @@
23 23
24#include <mach/common.h> 24#include <mach/common.h>
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26#include <mach/gpio.h>
27#include <mach/irqs.h>
28#include <mach/iomux-v1.h>
26 29
27static struct map_desc imx_io_desc[] __initdata = { 30static struct map_desc imx_io_desc[] __initdata = {
28 imx_map_entry(MX1, IO, MT_DEVICE), 31 imx_map_entry(MX1, IO, MT_DEVICE),
@@ -30,16 +33,26 @@ static struct map_desc imx_io_desc[] __initdata = {
30 33
31void __init mx1_map_io(void) 34void __init mx1_map_io(void)
32{ 35{
36 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
37}
38
39void __init imx1_init_early(void)
40{
33 mxc_set_cpu_type(MXC_CPU_MX1); 41 mxc_set_cpu_type(MXC_CPU_MX1);
34 mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); 42 mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
35 43 imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
36 iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc)); 44 MX1_NUM_GPIO_PORT);
37} 45}
38 46
39int imx1_register_gpios(void); 47static struct mxc_gpio_port imx1_gpio_ports[] = {
48 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
49 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
50 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
51 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
52};
40 53
41void __init mx1_init_irq(void) 54void __init mx1_init_irq(void)
42{ 55{
43 mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR)); 56 mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
44 imx1_register_gpios(); 57 mxc_gpio_init(imx1_gpio_ports, ARRAY_SIZE(imx1_gpio_ports));
45} 58}
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index e728af81d1b..7a0c500ac2c 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -24,6 +24,9 @@
24#include <mach/common.h> 24#include <mach/common.h>
25#include <asm/pgtable.h> 25#include <asm/pgtable.h>
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27#include <mach/gpio.h>
28#include <mach/irqs.h>
29#include <mach/iomux-v1.h>
27 30
28/* MX21 memory map definition */ 31/* MX21 memory map definition */
29static struct map_desc imx21_io_desc[] __initdata = { 32static struct map_desc imx21_io_desc[] __initdata = {
@@ -56,16 +59,28 @@ static struct map_desc imx21_io_desc[] __initdata = {
56 */ 59 */
57void __init mx21_map_io(void) 60void __init mx21_map_io(void)
58{ 61{
62 iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
63}
64
65void __init imx21_init_early(void)
66{
59 mxc_set_cpu_type(MXC_CPU_MX21); 67 mxc_set_cpu_type(MXC_CPU_MX21);
60 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); 68 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
61 69 imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
62 iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); 70 MX21_NUM_GPIO_PORT);
63} 71}
64 72
65int imx21_register_gpios(void); 73static struct mxc_gpio_port imx21_gpio_ports[] = {
74 DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
75 DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
76 DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
77 DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
78 DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
79 DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
80};
66 81
67void __init mx21_init_irq(void) 82void __init mx21_init_irq(void)
68{ 83{
69 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); 84 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
70 imx21_register_gpios(); 85 mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
71} 86}
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 2edec6ce8fe..02f7b5c7fa8 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -27,6 +27,8 @@
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/mx25.h> 28#include <mach/mx25.h>
29#include <mach/iomux-v3.h> 29#include <mach/iomux-v3.h>
30#include <mach/gpio.h>
31#include <mach/irqs.h>
30 32
31/* 33/*
32 * This table defines static virtual address mappings for I/O regions. 34 * This table defines static virtual address mappings for I/O regions.
@@ -45,18 +47,26 @@ static struct map_desc mx25_io_desc[] __initdata = {
45 */ 47 */
46void __init mx25_map_io(void) 48void __init mx25_map_io(void)
47{ 49{
50 iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
51}
52
53void __init imx25_init_early(void)
54{
48 mxc_set_cpu_type(MXC_CPU_MX25); 55 mxc_set_cpu_type(MXC_CPU_MX25);
49 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); 56 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
50 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); 57 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
51
52 iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
53} 58}
54 59
55int imx25_register_gpios(void); 60static struct mxc_gpio_port imx25_gpio_ports[] = {
61 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
62 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
63 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
64 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
65};
56 66
57void __init mx25_init_irq(void) 67void __init mx25_init_irq(void)
58{ 68{
59 mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); 69 mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
60 imx25_register_gpios(); 70 mxc_gpio_init(imx25_gpio_ports, ARRAY_SIZE(imx25_gpio_ports));
61} 71}
62 72
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 374e48b7a41..a6761a39f08 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -24,6 +24,9 @@
24#include <mach/common.h> 24#include <mach/common.h>
25#include <asm/pgtable.h> 25#include <asm/pgtable.h>
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27#include <mach/gpio.h>
28#include <mach/irqs.h>
29#include <mach/iomux-v1.h>
27 30
28/* MX27 memory map definition */ 31/* MX27 memory map definition */
29static struct map_desc imx27_io_desc[] __initdata = { 32static struct map_desc imx27_io_desc[] __initdata = {
@@ -56,16 +59,28 @@ static struct map_desc imx27_io_desc[] __initdata = {
56 */ 59 */
57void __init mx27_map_io(void) 60void __init mx27_map_io(void)
58{ 61{
62 iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
63}
64
65void __init imx27_init_early(void)
66{
59 mxc_set_cpu_type(MXC_CPU_MX27); 67 mxc_set_cpu_type(MXC_CPU_MX27);
60 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); 68 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
61 69 imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
62 iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); 70 MX27_NUM_GPIO_PORT);
63} 71}
64 72
65int imx27_register_gpios(void); 73static struct mxc_gpio_port imx27_gpio_ports[] = {
74 DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
75 DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
76 DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
77 DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
78 DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
79 DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
80};
66 81
67void __init mx27_init_irq(void) 82void __init mx27_init_irq(void)
68{ 83{
69 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); 84 mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
70 imx27_register_gpios(); 85 mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
71} 86}
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 0717f887cba..340809a7d23 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -94,6 +94,7 @@ config MACH_MX31_3DS
94 select MXC_DEBUG_BOARD 94 select MXC_DEBUG_BOARD
95 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 95 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
96 select IMX_HAVE_PLATFORM_IMX2_WDT 96 select IMX_HAVE_PLATFORM_IMX2_WDT
97 select IMX_HAVE_PLATFORM_IMX_I2C
97 select IMX_HAVE_PLATFORM_IMX_KEYPAD 98 select IMX_HAVE_PLATFORM_IMX_KEYPAD
98 select IMX_HAVE_PLATFORM_IMX_UART 99 select IMX_HAVE_PLATFORM_IMX_UART
99 select IMX_HAVE_PLATFORM_MXC_EHCI 100 select IMX_HAVE_PLATFORM_MXC_EHCI
@@ -183,6 +184,7 @@ config MACH_MX35_3DS
183 select MXC_DEBUG_BOARD 184 select MXC_DEBUG_BOARD
184 select IMX_HAVE_PLATFORM_FSL_USB2_UDC 185 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
185 select IMX_HAVE_PLATFORM_IMX2_WDT 186 select IMX_HAVE_PLATFORM_IMX2_WDT
187 select IMX_HAVE_PLATFORM_IMX_I2C
186 select IMX_HAVE_PLATFORM_IMX_UART 188 select IMX_HAVE_PLATFORM_IMX_UART
187 select IMX_HAVE_PLATFORM_MXC_EHCI 189 select IMX_HAVE_PLATFORM_MXC_EHCI
188 select IMX_HAVE_PLATFORM_MXC_NAND 190 select IMX_HAVE_PLATFORM_MXC_NAND
@@ -199,6 +201,15 @@ config MACH_KZM_ARM11_01
199 Include support for KZM-ARM11-01. This includes specific 201 Include support for KZM-ARM11-01. This includes specific
200 configurations for the board and its peripherals. 202 configurations for the board and its peripherals.
201 203
204config MACH_BUG
205 bool "Support Buglabs BUGBase platform"
206 select SOC_IMX31
207 select IMX_HAVE_PLATFORM_IMX_UART
208 default y
209 help
210 Include support for BUGBase 1.3 platform. This includes specific
211 configurations for the board and its peripherals.
212
202config MACH_EUKREA_CPUIMX35 213config MACH_EUKREA_CPUIMX35
203 bool "Support Eukrea CPUIMX35 Platform" 214 bool "Support Eukrea CPUIMX35 Platform"
204 select SOC_IMX35 215 select SOC_IMX35
@@ -229,4 +240,18 @@ config MACH_EUKREA_MBIMXSD35_BASEBOARD
229 240
230endchoice 241endchoice
231 242
243config MACH_VPR200
244 bool "Support VPR200 platform"
245 select SOC_IMX35
246 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
247 select IMX_HAVE_PLATFORM_IMX2_WDT
248 select IMX_HAVE_PLATFORM_IMX_UART
249 select IMX_HAVE_PLATFORM_IMX_I2C
250 select IMX_HAVE_PLATFORM_MXC_EHCI
251 select IMX_HAVE_PLATFORM_MXC_NAND
252 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
253 help
254 Include support for VPR200 platform. This includes specific
255 configurations for the board and its peripherals.
256
232endif 257endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 8db13294ad2..a54faf2cf5f 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -5,8 +5,8 @@
5# Object file lists. 5# Object file lists.
6 6
7obj-y := mm.o devices.o cpu.o 7obj-y := mm.o devices.o cpu.o
8obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o 8obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o ehci-imx31.o
9obj-$(CONFIG_SOC_IMX35) += clock-imx35.o 9obj-$(CONFIG_SOC_IMX35) += clock-imx35.o ehci-imx35.o
10obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o 10obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
11obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o 11obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
12obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o 12obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
@@ -20,5 +20,7 @@ obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
20obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o 20obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
21obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o 21obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
22obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o 22obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
23obj-$(CONFIG_MACH_BUG) += mach-bug.o
23obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o 24obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
24obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o 25obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o
26obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index 677b18aa7ae..d545d86cc20 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -35,7 +35,7 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
35#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) 35#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
36 36
37extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst; 37extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
38#define imx31_add_imx_keypad(pdata) \ 38#define imx35_add_imx_keypad(pdata) \
39 imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) 39 imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
40 40
41extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; 41extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-mx3/ehci-imx31.c
new file mode 100644
index 00000000000..314a983ac61
--- /dev/null
+++ b/arch/arm/mach-mx3/ehci-imx31.c
@@ -0,0 +1,83 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX31_OTG_SIC_SHIFT 29
25#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
26#define MX31_OTG_PM_BIT (1 << 24)
27
28#define MX31_H2_SIC_SHIFT 21
29#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
30#define MX31_H2_PM_BIT (1 << 16)
31#define MX31_H2_DT_BIT (1 << 5)
32
33#define MX31_H1_SIC_SHIFT 13
34#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
35#define MX31_H1_PM_BIT (1 << 8)
36#define MX31_H1_DT_BIT (1 << 4)
37
38int mx31_initialize_usb_hw(int port, unsigned int flags)
39{
40 unsigned int v;
41
42 v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
43
44 switch (port) {
45 case 0: /* OTG port */
46 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
47 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
48
49 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
50 v |= MX31_OTG_PM_BIT;
51
52 break;
53 case 1: /* H1 port */
54 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
55 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
56
57 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
58 v |= MX31_H1_PM_BIT;
59
60 if (!(flags & MXC_EHCI_TTL_ENABLED))
61 v |= MX31_H1_DT_BIT;
62
63 break;
64 case 2: /* H2 port */
65 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
66 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
67
68 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
69 v |= MX31_H2_PM_BIT;
70
71 if (!(flags & MXC_EHCI_TTL_ENABLED))
72 v |= MX31_H2_DT_BIT;
73
74 break;
75 default:
76 return -EINVAL;
77 }
78
79 writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
80
81 return 0;
82}
83
diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-mx3/ehci-imx35.c
new file mode 100644
index 00000000000..33983a478c6
--- /dev/null
+++ b/arch/arm/mach-mx3/ehci-imx35.c
@@ -0,0 +1,80 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX35_OTG_SIC_SHIFT 29
25#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
26#define MX35_OTG_PM_BIT (1 << 24)
27
28#define MX35_H1_SIC_SHIFT 21
29#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
30#define MX35_H1_PM_BIT (1 << 8)
31#define MX35_H1_IPPUE_UP_BIT (1 << 7)
32#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
33#define MX35_H1_TLL_BIT (1 << 5)
34#define MX35_H1_USBTE_BIT (1 << 4)
35
36int mx35_initialize_usb_hw(int port, unsigned int flags)
37{
38 unsigned int v;
39
40 v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
41
42 switch (port) {
43 case 0: /* OTG port */
44 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
45 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
46
47 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
48 v |= MX35_OTG_PM_BIT;
49
50 break;
51 case 1: /* H1 port */
52 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
53 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
54 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
55
56 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
57 v |= MX35_H1_PM_BIT;
58
59 if (!(flags & MXC_EHCI_TTL_ENABLED))
60 v |= MX35_H1_TLL_BIT;
61
62 if (flags & MXC_EHCI_INTERNAL_PHY)
63 v |= MX35_H1_USBTE_BIT;
64
65 if (flags & MXC_EHCI_IPPUE_DOWN)
66 v |= MX35_H1_IPPUE_DOWN_BIT;
67
68 if (flags & MXC_EHCI_IPPUE_UP)
69 v |= MX35_H1_IPPUE_UP_BIT;
70
71 break;
72 default:
73 return -EINVAL;
74 }
75
76 writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
77
78 return 0;
79}
80
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index 14a5ffc939a..80761474c0f 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -165,8 +165,8 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
165 MX35_PAD_SD1_DATA3__ESDHC1_DAT3, 165 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
166}; 166};
167 167
168#define GPIO_LED1 (2 * 32 + 29) 168#define GPIO_LED1 IMX_GPIO_NR(3, 29)
169#define GPIO_SWITCH1 (2 * 32 + 25) 169#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25)
170#define GPIO_LCDPWR (4) 170#define GPIO_LCDPWR (4)
171 171
172static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd, 172static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-mx3/iomux-imx31.c
index a1d7fa5123d..cf8f8099ebd 100644
--- a/arch/arm/mach-mx3/iomux-imx31.c
+++ b/arch/arm/mach-mx3/iomux-imx31.c
@@ -97,7 +97,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad);
97 * - reserves the pin so that it is not claimed by another driver 97 * - reserves the pin so that it is not claimed by another driver
98 * - setups the iomux according to the configuration 98 * - setups the iomux according to the configuration
99 */ 99 */
100int mxc_iomux_alloc_pin(const unsigned int pin, const char *label) 100int mxc_iomux_alloc_pin(unsigned int pin, const char *label)
101{ 101{
102 unsigned pad = pin & IOMUX_PADNUM_MASK; 102 unsigned pad = pin & IOMUX_PADNUM_MASK;
103 103
@@ -118,10 +118,10 @@ int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
118} 118}
119EXPORT_SYMBOL(mxc_iomux_alloc_pin); 119EXPORT_SYMBOL(mxc_iomux_alloc_pin);
120 120
121int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, 121int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
122 const char *label) 122 const char *label)
123{ 123{
124 unsigned int *p = pin_list; 124 const unsigned int *p = pin_list;
125 int i; 125 int i;
126 int ret = -EINVAL; 126 int ret = -EINVAL;
127 127
@@ -139,7 +139,7 @@ setup_error:
139} 139}
140EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); 140EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
141 141
142void mxc_iomux_release_pin(const unsigned int pin) 142void mxc_iomux_release_pin(unsigned int pin)
143{ 143{
144 unsigned pad = pin & IOMUX_PADNUM_MASK; 144 unsigned pad = pin & IOMUX_PADNUM_MASK;
145 145
@@ -148,9 +148,9 @@ void mxc_iomux_release_pin(const unsigned int pin)
148} 148}
149EXPORT_SYMBOL(mxc_iomux_release_pin); 149EXPORT_SYMBOL(mxc_iomux_release_pin);
150 150
151void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count) 151void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
152{ 152{
153 unsigned int *p = pin_list; 153 const unsigned int *p = pin_list;
154 int i; 154 int i;
155 155
156 for (i = 0; i < count; i++) { 156 for (i = 0; i < count; i++) {
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 28b6f414b5d..226829bf7c2 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -133,7 +133,6 @@ static int armadillo5x0_pins[] = {
133}; 133};
134 134
135/* USB */ 135/* USB */
136#if defined(CONFIG_USB_ULPI)
137 136
138#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4) 137#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
139#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6) 138#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
@@ -176,8 +175,10 @@ static int usbotg_init(struct platform_device *pdev)
176 gpio_set_value(OTG_RESET, 0/*LOW*/); 175 gpio_set_value(OTG_RESET, 0/*LOW*/);
177 mdelay(5); 176 mdelay(5);
178 gpio_set_value(OTG_RESET, 1/*HIGH*/); 177 gpio_set_value(OTG_RESET, 1/*HIGH*/);
178 mdelay(10);
179 179
180 return 0; 180 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
181 MXC_EHCI_INTERFACE_DIFF_UNI);
181 182
182otg_free_reset: 183otg_free_reset:
183 gpio_free(OTG_RESET); 184 gpio_free(OTG_RESET);
@@ -233,8 +234,10 @@ static int usbh2_init(struct platform_device *pdev)
233 gpio_set_value(USBH2_RESET, 0/*LOW*/); 234 gpio_set_value(USBH2_RESET, 0/*LOW*/);
234 mdelay(5); 235 mdelay(5);
235 gpio_set_value(USBH2_RESET, 1/*HIGH*/); 236 gpio_set_value(USBH2_RESET, 1/*HIGH*/);
237 mdelay(10);
236 238
237 return 0; 239 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
240 MXC_EHCI_INTERFACE_DIFF_UNI);
238 241
239h2_free_reset: 242h2_free_reset:
240 gpio_free(USBH2_RESET); 243 gpio_free(USBH2_RESET);
@@ -246,15 +249,12 @@ h2_free_cs:
246static struct mxc_usbh_platform_data usbotg_pdata __initdata = { 249static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
247 .init = usbotg_init, 250 .init = usbotg_init,
248 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 251 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
249 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
250}; 252};
251 253
252static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 254static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
253 .init = usbh2_init, 255 .init = usbh2_init,
254 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 256 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
255 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
256}; 257};
257#endif /* CONFIG_USB_ULPI */
258 258
259/* RTC over I2C*/ 259/* RTC over I2C*/
260#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4) 260#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
@@ -547,15 +547,15 @@ static void __init armadillo5x0_init(void)
547 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); 547 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
548 548
549 /* USB */ 549 /* USB */
550#if defined(CONFIG_USB_ULPI) 550
551 usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 551 usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
552 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 552 ULPI_OTG_DRVVBUS_EXT);
553 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 553 if (usbotg_pdata.otg)
554 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 554 imx31_add_mxc_ehci_otg(&usbotg_pdata);
555 555 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
556 imx31_add_mxc_ehci_otg(&usbotg_pdata); 556 ULPI_OTG_DRVVBUS_EXT);
557 imx31_add_mxc_ehci_hs(2, &usbh2_pdata); 557 if (usbh2_pdata.otg)
558#endif 558 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
559} 559}
560 560
561static void __init armadillo5x0_timer_init(void) 561static void __init armadillo5x0_timer_init(void)
@@ -569,9 +569,10 @@ static struct sys_timer armadillo5x0_timer = {
569 569
570MACHINE_START(ARMADILLO5X0, "Armadillo-500") 570MACHINE_START(ARMADILLO5X0, "Armadillo-500")
571 /* Maintainer: Alberto Panizzo */ 571 /* Maintainer: Alberto Panizzo */
572 .boot_params = MX3x_PHYS_OFFSET + 0x100, 572 .boot_params = MX3x_PHYS_OFFSET + 0x100,
573 .map_io = mx31_map_io, 573 .map_io = mx31_map_io,
574 .init_irq = mx31_init_irq, 574 .init_early = imx31_init_early,
575 .timer = &armadillo5x0_timer, 575 .init_irq = mx31_init_irq,
576 .init_machine = armadillo5x0_init, 576 .timer = &armadillo5x0_timer,
577 .init_machine = armadillo5x0_init,
577MACHINE_END 578MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-bug.c b/arch/arm/mach-mx3/mach-bug.c
new file mode 100644
index 00000000000..d137d7078ee
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-bug.c
@@ -0,0 +1,66 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21
22#include <mach/iomux-mx3.h>
23#include <mach/imx-uart.h>
24#include <mach/hardware.h>
25#include <mach/common.h>
26
27#include <asm/mach/time.h>
28#include <asm/mach/arch.h>
29#include <asm/mach-types.h>
30
31#include "devices-imx31.h"
32
33static const struct imxuart_platform_data uart_pdata __initconst = {
34 .flags = IMXUART_HAVE_RTSCTS,
35};
36
37static const unsigned int bug_pins[] __initconst = {
38 MX31_PIN_PC_RST__CTS5,
39 MX31_PIN_PC_VS2__RTS5,
40 MX31_PIN_PC_BVD2__TXD5,
41 MX31_PIN_PC_BVD1__RXD5,
42};
43
44static void __init bug_board_init(void)
45{
46 mxc_iomux_setup_multiple_pins(bug_pins,
47 ARRAY_SIZE(bug_pins), "uart-4");
48 imx31_add_imx_uart4(&uart_pdata);
49}
50
51static void __init bug_timer_init(void)
52{
53 mx31_clocks_init(26000000);
54}
55
56static struct sys_timer bug_timer = {
57 .init = bug_timer_init,
58};
59
60MACHINE_START(BUG, "BugLabs BUGBase")
61 .map_io = mx31_map_io,
62 .init_early = imx31_init_early,
63 .init_irq = mx31_init_irq,
64 .timer = &bug_timer,
65 .init_machine = bug_board_init,
66MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 26ae90f0258..ec63d998f64 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -60,7 +60,7 @@ static struct tsc2007_platform_data tsc2007_info = {
60 .x_plate_ohms = 180, 60 .x_plate_ohms = 180,
61}; 61};
62 62
63#define TSC2007_IRQGPIO (2 * 32 + 2) 63#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 2)
64static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { 64static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
65 { 65 {
66 I2C_BOARD_INFO("pcf8563", 0x51), 66 I2C_BOARD_INFO("pcf8563", 0x51),
@@ -111,15 +111,25 @@ static const struct mxc_nand_platform_data
111 .flash_bbt = 1, 111 .flash_bbt = 1,
112}; 112};
113 113
114static int eukrea_cpuimx35_otg_init(struct platform_device *pdev)
115{
116 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
117}
118
114static const struct mxc_usbh_platform_data otg_pdata __initconst = { 119static const struct mxc_usbh_platform_data otg_pdata __initconst = {
120 .init = eukrea_cpuimx35_otg_init,
115 .portsc = MXC_EHCI_MODE_UTMI, 121 .portsc = MXC_EHCI_MODE_UTMI,
116 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
117}; 122};
118 123
124static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev)
125{
126 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
127 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
128}
129
119static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { 130static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
131 .init = eukrea_cpuimx35_usbh1_init,
120 .portsc = MXC_EHCI_MODE_SERIAL, 132 .portsc = MXC_EHCI_MODE_SERIAL,
121 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
122 MXC_EHCI_IPPUE_DOWN,
123}; 133};
124 134
125static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 135static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
@@ -146,7 +156,7 @@ __setup("otg_mode=", eukrea_cpuimx35_otg_mode);
146/* 156/*
147 * Board specific initialization. 157 * Board specific initialization.
148 */ 158 */
149static void __init mxc_board_init(void) 159static void __init eukrea_cpuimx35_init(void)
150{ 160{
151 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, 161 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
152 ARRAY_SIZE(eukrea_cpuimx35_pads)); 162 ARRAY_SIZE(eukrea_cpuimx35_pads));
@@ -184,9 +194,10 @@ struct sys_timer eukrea_cpuimx35_timer = {
184 194
185MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35") 195MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
186 /* Maintainer: Eukrea Electromatique */ 196 /* Maintainer: Eukrea Electromatique */
187 .boot_params = MX3x_PHYS_OFFSET + 0x100, 197 .boot_params = MX3x_PHYS_OFFSET + 0x100,
188 .map_io = mx35_map_io, 198 .map_io = mx35_map_io,
189 .init_irq = mx35_init_irq, 199 .init_early = imx35_init_early,
190 .init_machine = mxc_board_init, 200 .init_irq = mx35_init_irq,
191 .timer = &eukrea_cpuimx35_timer, 201 .timer = &eukrea_cpuimx35_timer,
202 .init_machine = eukrea_cpuimx35_init,
192MACHINE_END 203MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index a5f3eb24e4d..d3cc7393a6b 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -266,17 +266,14 @@ static void __init kzm_timer_init(void)
266} 266}
267 267
268static struct sys_timer kzm_timer = { 268static struct sys_timer kzm_timer = {
269 .init = kzm_timer_init, 269 .init = kzm_timer_init,
270}; 270};
271 271
272/*
273 * The following uses standard kernel macros define in arch.h in order to
274 * initialize __mach_desc_KZM_ARM11_01 data structure.
275 */
276MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") 272MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
277 .boot_params = MX3x_PHYS_OFFSET + 0x100, 273 .boot_params = MX3x_PHYS_OFFSET + 0x100,
278 .map_io = kzm_map_io, 274 .map_io = kzm_map_io,
279 .init_irq = mx31_init_irq, 275 .init_early = imx31_init_early,
280 .init_machine = kzm_board_init, 276 .init_irq = mx31_init_irq,
281 .timer = &kzm_timer, 277 .timer = &kzm_timer,
278 .init_machine = kzm_board_init,
282MACHINE_END 279MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 0d65db885be..544d3e414f5 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -21,9 +21,13 @@
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/mfd/mc13783.h> 22#include <linux/mfd/mc13783.h>
23#include <linux/spi/spi.h> 23#include <linux/spi/spi.h>
24#include <linux/spi/l4f00242t03.h>
24#include <linux/regulator/machine.h> 25#include <linux/regulator/machine.h>
25#include <linux/usb/otg.h> 26#include <linux/usb/otg.h>
26#include <linux/usb/ulpi.h> 27#include <linux/usb/ulpi.h>
28#include <linux/memblock.h>
29
30#include <media/soc_camera.h>
27 31
28#include <mach/hardware.h> 32#include <mach/hardware.h>
29#include <asm/mach-types.h> 33#include <asm/mach-types.h>
@@ -35,6 +39,10 @@
35#include <mach/iomux-mx3.h> 39#include <mach/iomux-mx3.h>
36#include <mach/3ds_debugboard.h> 40#include <mach/3ds_debugboard.h>
37#include <mach/ulpi.h> 41#include <mach/ulpi.h>
42#include <mach/mmc.h>
43#include <mach/ipu.h>
44#include <mach/mx3fb.h>
45#include <mach/mx3_camera.h>
38 46
39#include "devices-imx31.h" 47#include "devices-imx31.h"
40#include "devices.h" 48#include "devices.h"
@@ -42,10 +50,6 @@
42/* CPLD IRQ line for external uart, external ethernet etc */ 50/* CPLD IRQ line for external uart, external ethernet etc */
43#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) 51#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
44 52
45/*
46 * This file contains the board-specific initialization routines.
47 */
48
49static int mx31_3ds_pins[] = { 53static int mx31_3ds_pins[] = {
50 /* UART1 */ 54 /* UART1 */
51 MX31_PIN_CTS1__CTS1, 55 MX31_PIN_CTS1__CTS1,
@@ -53,6 +57,12 @@ static int mx31_3ds_pins[] = {
53 MX31_PIN_TXD1__TXD1, 57 MX31_PIN_TXD1__TXD1,
54 MX31_PIN_RXD1__RXD1, 58 MX31_PIN_RXD1__RXD1,
55 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), 59 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
60 /*SPI0*/
61 MX31_PIN_CSPI1_SCLK__SCLK,
62 MX31_PIN_CSPI1_MOSI__MOSI,
63 MX31_PIN_CSPI1_MISO__MISO,
64 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
65 MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
56 /* SPI 1 */ 66 /* SPI 1 */
57 MX31_PIN_CSPI2_SCLK__SCLK, 67 MX31_PIN_CSPI2_SCLK__SCLK,
58 MX31_PIN_CSPI2_MOSI__MOSI, 68 MX31_PIN_CSPI2_MOSI__MOSI,
@@ -100,6 +110,252 @@ static int mx31_3ds_pins[] = {
100 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), 110 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
101 /* USB Host2 reset */ 111 /* USB Host2 reset */
102 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), 112 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
113 /* I2C1 */
114 MX31_PIN_I2C_CLK__I2C1_SCL,
115 MX31_PIN_I2C_DAT__I2C1_SDA,
116 /* SDHC1 */
117 MX31_PIN_SD1_DATA3__SD1_DATA3,
118 MX31_PIN_SD1_DATA2__SD1_DATA2,
119 MX31_PIN_SD1_DATA1__SD1_DATA1,
120 MX31_PIN_SD1_DATA0__SD1_DATA0,
121 MX31_PIN_SD1_CLK__SD1_CLK,
122 MX31_PIN_SD1_CMD__SD1_CMD,
123 MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
124 MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
125 /* Framebuffer */
126 MX31_PIN_LD0__LD0,
127 MX31_PIN_LD1__LD1,
128 MX31_PIN_LD2__LD2,
129 MX31_PIN_LD3__LD3,
130 MX31_PIN_LD4__LD4,
131 MX31_PIN_LD5__LD5,
132 MX31_PIN_LD6__LD6,
133 MX31_PIN_LD7__LD7,
134 MX31_PIN_LD8__LD8,
135 MX31_PIN_LD9__LD9,
136 MX31_PIN_LD10__LD10,
137 MX31_PIN_LD11__LD11,
138 MX31_PIN_LD12__LD12,
139 MX31_PIN_LD13__LD13,
140 MX31_PIN_LD14__LD14,
141 MX31_PIN_LD15__LD15,
142 MX31_PIN_LD16__LD16,
143 MX31_PIN_LD17__LD17,
144 MX31_PIN_VSYNC3__VSYNC3,
145 MX31_PIN_HSYNC__HSYNC,
146 MX31_PIN_FPSHIFT__FPSHIFT,
147 MX31_PIN_CONTRAST__CONTRAST,
148 /* CSI */
149 MX31_PIN_CSI_D6__CSI_D6,
150 MX31_PIN_CSI_D7__CSI_D7,
151 MX31_PIN_CSI_D8__CSI_D8,
152 MX31_PIN_CSI_D9__CSI_D9,
153 MX31_PIN_CSI_D10__CSI_D10,
154 MX31_PIN_CSI_D11__CSI_D11,
155 MX31_PIN_CSI_D12__CSI_D12,
156 MX31_PIN_CSI_D13__CSI_D13,
157 MX31_PIN_CSI_D14__CSI_D14,
158 MX31_PIN_CSI_D15__CSI_D15,
159 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
160 MX31_PIN_CSI_MCLK__CSI_MCLK,
161 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
162 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
163 MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
164 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
165};
166
167/*
168 * Camera support
169 */
170static phys_addr_t mx3_camera_base __initdata;
171#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
172
173#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
174#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
175
176static struct gpio mx31_3ds_camera_gpios[] = {
177 { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
178 { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
179};
180
181static int __init mx31_3ds_camera_alloc_dma(void)
182{
183 int dma;
184
185 if (!mx3_camera_base)
186 return -ENOMEM;
187
188 dma = dma_declare_coherent_memory(&mx3_camera.dev,
189 mx3_camera_base, mx3_camera_base,
190 MX31_3DS_CAMERA_BUF_SIZE,
191 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
192
193 if (!(dma & DMA_MEMORY_MAP))
194 return -ENOMEM;
195
196 return 0;
197}
198
199static int mx31_3ds_camera_power(struct device *dev, int on)
200{
201 /* enable or disable the camera */
202 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
203 gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
204
205 if (!on)
206 goto out;
207
208 /* If enabled, give a reset impulse */
209 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
210 msleep(20);
211 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
212 msleep(100);
213
214out:
215 return 0;
216}
217
218static struct i2c_board_info mx31_3ds_i2c_camera = {
219 I2C_BOARD_INFO("ov2640", 0x30),
220};
221
222static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
223 { .supply = "cmos_vcore" },
224 { .supply = "cmos_2v8" },
225};
226
227static struct soc_camera_link iclink_ov2640 = {
228 .bus_id = 0,
229 .board_info = &mx31_3ds_i2c_camera,
230 .i2c_adapter_id = 0,
231 .power = mx31_3ds_camera_power,
232 .regulators = mx31_3ds_camera_regs,
233 .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
234};
235
236static struct platform_device mx31_3ds_ov2640 = {
237 .name = "soc-camera-pdrv",
238 .id = 0,
239 .dev = {
240 .platform_data = &iclink_ov2640,
241 },
242};
243
244struct mx3_camera_pdata mx31_3ds_camera_pdata = {
245 .dma_dev = &mx3_ipu.dev,
246 .flags = MX3_CAMERA_DATAWIDTH_10,
247 .mclk_10khz = 2600,
248};
249
250/*
251 * FB support
252 */
253static const struct fb_videomode fb_modedb[] = {
254 { /* 480x640 @ 60 Hz */
255 .name = "Epson-VGA",
256 .refresh = 60,
257 .xres = 480,
258 .yres = 640,
259 .pixclock = 41701,
260 .left_margin = 20,
261 .right_margin = 41,
262 .upper_margin = 10,
263 .lower_margin = 5,
264 .hsync_len = 20,
265 .vsync_len = 10,
266 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
267 .vmode = FB_VMODE_NONINTERLACED,
268 .flag = 0,
269 },
270};
271
272static struct ipu_platform_data mx3_ipu_data = {
273 .irq_base = MXC_IPU_IRQ_START,
274};
275
276static struct mx3fb_platform_data mx3fb_pdata = {
277 .dma_dev = &mx3_ipu.dev,
278 .name = "Epson-VGA",
279 .mode = fb_modedb,
280 .num_modes = ARRAY_SIZE(fb_modedb),
281};
282
283/* LCD */
284static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
285 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
286 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
287 .core_supply = "lcd_2v8",
288 .io_supply = "vdd_lcdio",
289};
290
291/*
292 * Support for SD card slot in personality board
293 */
294#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
295#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
296
297static struct gpio mx31_3ds_sdhc1_gpios[] = {
298 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
299 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
300};
301
302static int mx31_3ds_sdhc1_init(struct device *dev,
303 irq_handler_t detect_irq,
304 void *data)
305{
306 int ret;
307
308 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
309 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
310 if (ret) {
311 pr_warning("Unable to request the SD/MMC GPIOs.\n");
312 return ret;
313 }
314
315 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
316 detect_irq, IRQF_DISABLED |
317 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
318 "sdhc1-detect", data);
319 if (ret) {
320 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
321 goto gpio_free;
322 }
323
324 return 0;
325
326gpio_free:
327 gpio_free_array(mx31_3ds_sdhc1_gpios,
328 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
329 return ret;
330}
331
332static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
333{
334 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
335 gpio_free_array(mx31_3ds_sdhc1_gpios,
336 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
337}
338
339static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
340{
341 /*
342 * While the voltage stuff is done by the driver, activate the
343 * Buffer Enable Pin only if there is a card in slot to fix the card
344 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
345 * Done here because at this stage we have for sure a debounced value
346 * of the presence of the card, showed by the value of vdd.
347 * 7 == ilog2(MMC_VDD_165_195)
348 */
349 if (vdd > 7)
350 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
351 else
352 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
353}
354
355static struct imxmmc_platform_data sdhc1_pdata = {
356 .init = mx31_3ds_sdhc1_init,
357 .exit = mx31_3ds_sdhc1_exit,
358 .setpower = mx31_3ds_sdhc1_setpower,
103}; 359};
104 360
105/* 361/*
@@ -138,7 +394,71 @@ static struct regulator_init_data gpo_init = {
138 } 394 }
139}; 395};
140 396
141static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { 397static struct regulator_consumer_supply vmmc2_consumers[] = {
398 REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
399};
400
401static struct regulator_init_data vmmc2_init = {
402 .constraints = {
403 .min_uV = 3000000,
404 .max_uV = 3000000,
405 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
406 REGULATOR_CHANGE_STATUS,
407 },
408 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
409 .consumer_supplies = vmmc2_consumers,
410};
411
412static struct regulator_consumer_supply vmmc1_consumers[] = {
413 REGULATOR_SUPPLY("lcd_2v8", NULL),
414 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
415};
416
417static struct regulator_init_data vmmc1_init = {
418 .constraints = {
419 .min_uV = 2800000,
420 .max_uV = 2800000,
421 .apply_uV = 1,
422 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
423 REGULATOR_CHANGE_STATUS,
424 },
425 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
426 .consumer_supplies = vmmc1_consumers,
427};
428
429static struct regulator_consumer_supply vgen_consumers[] = {
430 REGULATOR_SUPPLY("vdd_lcdio", NULL),
431};
432
433static struct regulator_init_data vgen_init = {
434 .constraints = {
435 .min_uV = 1800000,
436 .max_uV = 1800000,
437 .apply_uV = 1,
438 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
439 REGULATOR_CHANGE_STATUS,
440 },
441 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
442 .consumer_supplies = vgen_consumers,
443};
444
445static struct regulator_consumer_supply vvib_consumers[] = {
446 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
447};
448
449static struct regulator_init_data vvib_init = {
450 .constraints = {
451 .min_uV = 1300000,
452 .max_uV = 1300000,
453 .apply_uV = 1,
454 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
455 REGULATOR_CHANGE_STATUS,
456 },
457 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
458 .consumer_supplies = vvib_consumers,
459};
460
461static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
142 { 462 {
143 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ 463 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
144 .init_data = &pwgtx_init, 464 .init_data = &pwgtx_init,
@@ -152,17 +472,38 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
152 }, { 472 }, {
153 .id = MC13783_REG_GPO3, /* Turn on 3.3V */ 473 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
154 .init_data = &gpo_init, 474 .init_data = &gpo_init,
475 }, {
476 .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
477 .init_data = &vmmc2_init,
478 }, {
479 .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
480 .init_data = &vmmc1_init,
481 }, {
482 .id = MC13783_REG_VGEN, /* Power LCD */
483 .init_data = &vgen_init,
484 }, {
485 .id = MC13783_REG_VVIB, /* Power CMOS */
486 .init_data = &vvib_init,
155 }, 487 },
156}; 488};
157 489
158/* MC13783 */ 490/* MC13783 */
159static struct mc13783_platform_data mc13783_pdata __initdata = { 491static struct mc13xxx_platform_data mc13783_pdata __initdata = {
160 .regulators = mx31_3ds_regulators, 492 .regulators = mx31_3ds_regulators,
161 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), 493 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
162 .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN, 494 .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_TOUCHSCREEN
163}; 495};
164 496
165/* SPI */ 497/* SPI */
498static int spi0_internal_chipselect[] = {
499 MXC_SPI_CS(2),
500};
501
502static const struct spi_imx_master spi0_pdata __initconst = {
503 .chipselect = spi0_internal_chipselect,
504 .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
505};
506
166static int spi1_internal_chipselect[] = { 507static int spi1_internal_chipselect[] = {
167 MXC_SPI_CS(0), 508 MXC_SPI_CS(0),
168 MXC_SPI_CS(2), 509 MXC_SPI_CS(2),
@@ -182,6 +523,12 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
182 .platform_data = &mc13783_pdata, 523 .platform_data = &mc13783_pdata,
183 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), 524 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
184 .mode = SPI_CS_HIGH, 525 .mode = SPI_CS_HIGH,
526 }, {
527 .modalias = "l4f00242t03",
528 .max_speed_hz = 5000000,
529 .bus_num = 0,
530 .chip_select = 0, /* SS2 */
531 .platform_data = &mx31_3ds_l4f00242t03_pdata,
185 }, 532 },
186}; 533};
187 534
@@ -245,6 +592,11 @@ usbotg_free_reset:
245 return err; 592 return err;
246} 593}
247 594
595static int mx31_3ds_otg_init(struct platform_device *pdev)
596{
597 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
598}
599
248static int mx31_3ds_host2_init(struct platform_device *pdev) 600static int mx31_3ds_host2_init(struct platform_device *pdev)
249{ 601{
250 int err; 602 int err;
@@ -276,25 +628,25 @@ static int mx31_3ds_host2_init(struct platform_device *pdev)
276 628
277 mdelay(1); 629 mdelay(1);
278 gpio_set_value(USBH2_RST_B, 1); 630 gpio_set_value(USBH2_RST_B, 1);
279 return 0; 631
632 mdelay(10);
633
634 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
280 635
281usbotg_free_reset: 636usbotg_free_reset:
282 gpio_free(USBH2_RST_B); 637 gpio_free(USBH2_RST_B);
283 return err; 638 return err;
284} 639}
285 640
286#if defined(CONFIG_USB_ULPI)
287static struct mxc_usbh_platform_data otg_pdata __initdata = { 641static struct mxc_usbh_platform_data otg_pdata __initdata = {
642 .init = mx31_3ds_otg_init,
288 .portsc = MXC_EHCI_MODE_ULPI, 643 .portsc = MXC_EHCI_MODE_ULPI,
289 .flags = MXC_EHCI_POWER_PINS_ENABLED,
290}; 644};
291 645
292static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 646static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
293 .init = mx31_3ds_host2_init, 647 .init = mx31_3ds_host2_init,
294 .portsc = MXC_EHCI_MODE_ULPI, 648 .portsc = MXC_EHCI_MODE_ULPI,
295 .flags = MXC_EHCI_POWER_PINS_ENABLED,
296}; 649};
297#endif
298 650
299static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { 651static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
300 .operating_mode = FSL_USB2_DR_DEVICE, 652 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -320,19 +672,18 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
320 .flags = IMXUART_HAVE_RTSCTS, 672 .flags = IMXUART_HAVE_RTSCTS,
321}; 673};
322 674
323/* 675static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
324 * Set up static virtual mappings. 676 .bitrate = 100000,
325 */ 677};
326static void __init mx31_3ds_map_io(void)
327{
328 mx31_map_io();
329}
330 678
331/*! 679static struct platform_device *devices[] __initdata = {
332 * Board specific initialization. 680 &mx31_3ds_ov2640,
333 */ 681};
334static void __init mxc_board_init(void) 682
683static void __init mx31_3ds_init(void)
335{ 684{
685 int ret;
686
336 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), 687 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
337 "mx31_3ds"); 688 "mx31_3ds");
338 689
@@ -343,20 +694,22 @@ static void __init mxc_board_init(void)
343 spi_register_board_info(mx31_3ds_spi_devs, 694 spi_register_board_info(mx31_3ds_spi_devs,
344 ARRAY_SIZE(mx31_3ds_spi_devs)); 695 ARRAY_SIZE(mx31_3ds_spi_devs));
345 696
697 platform_add_devices(devices, ARRAY_SIZE(devices));
698
346 imx31_add_imx_keypad(&mx31_3ds_keymap_data); 699 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
347 700
348 mx31_3ds_usbotg_init(); 701 mx31_3ds_usbotg_init();
349#if defined(CONFIG_USB_ULPI)
350 if (otg_mode_host) { 702 if (otg_mode_host) {
351 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 703 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
352 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 704 ULPI_OTG_DRVVBUS_EXT);
353 705 if (otg_pdata.otg)
354 imx31_add_mxc_ehci_otg(&otg_pdata); 706 imx31_add_mxc_ehci_otg(&otg_pdata);
355 } 707 }
356 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 708 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
357 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 709 ULPI_OTG_DRVVBUS_EXT);
358 imx31_add_mxc_ehci_hs(2, &usbh2_pdata); 710 if (usbh2_pdata.otg)
359#endif 711 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
712
360 if (!otg_mode_host) 713 if (!otg_mode_host)
361 imx31_add_fsl_usb2_udc(&usbotg_pdata); 714 imx31_add_fsl_usb2_udc(&usbotg_pdata);
362 715
@@ -364,6 +717,26 @@ static void __init mxc_board_init(void)
364 printk(KERN_WARNING "Init of the debug board failed, all " 717 printk(KERN_WARNING "Init of the debug board failed, all "
365 "devices on the debug board are unusable.\n"); 718 "devices on the debug board are unusable.\n");
366 imx31_add_imx2_wdt(NULL); 719 imx31_add_imx2_wdt(NULL);
720 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
721 imx31_add_mxc_mmc(0, &sdhc1_pdata);
722
723 imx31_add_spi_imx0(&spi0_pdata);
724 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
725 mxc_register_device(&mx3_fb, &mx3fb_pdata);
726
727 /* CSI */
728 /* Camera power: default - off */
729 ret = gpio_request_array(mx31_3ds_camera_gpios,
730 ARRAY_SIZE(mx31_3ds_camera_gpios));
731 if (ret) {
732 pr_err("Failed to request camera gpios");
733 iclink_ov2640.power = NULL;
734 }
735
736 if (!mx31_3ds_camera_alloc_dma())
737 mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
738 else
739 pr_err("Failed to allocate dma memory for camera");
367} 740}
368 741
369static void __init mx31_3ds_timer_init(void) 742static void __init mx31_3ds_timer_init(void)
@@ -375,15 +748,22 @@ static struct sys_timer mx31_3ds_timer = {
375 .init = mx31_3ds_timer_init, 748 .init = mx31_3ds_timer_init,
376}; 749};
377 750
378/* 751static void __init mx31_3ds_reserve(void)
379 * The following uses standard kernel macros defined in arch.h in order to 752{
380 * initialize __mach_desc_MX31_3DS data structure. 753 /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
381 */ 754 mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
755 MX31_3DS_CAMERA_BUF_SIZE);
756 memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
757 memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
758}
759
382MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") 760MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
383 /* Maintainer: Freescale Semiconductor, Inc. */ 761 /* Maintainer: Freescale Semiconductor, Inc. */
384 .boot_params = MX3x_PHYS_OFFSET + 0x100, 762 .boot_params = MX3x_PHYS_OFFSET + 0x100,
385 .map_io = mx31_3ds_map_io, 763 .map_io = mx31_map_io,
386 .init_irq = mx31_init_irq, 764 .init_early = imx31_init_early,
387 .init_machine = mxc_board_init, 765 .init_irq = mx31_init_irq,
388 .timer = &mx31_3ds_timer, 766 .timer = &mx31_3ds_timer,
767 .init_machine = mx31_3ds_init,
768 .reserve = mx31_3ds_reserve,
389MACHINE_END 769MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 88b97d62b57..4e4b780c481 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -69,12 +69,8 @@
69#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11) 69#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
70 70
71#define MXC_MAX_EXP_IO_LINES 16 71#define MXC_MAX_EXP_IO_LINES 16
72/*
73 * This file contains the board-specific initialization routines.
74 */
75 72
76#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 73/*
77/*!
78 * The serial port definition structure. 74 * The serial port definition structure.
79 */ 75 */
80static struct plat_serial8250_port serial_platform_data[] = { 76static struct plat_serial8250_port serial_platform_data[] = {
@@ -110,14 +106,7 @@ static int __init mxc_init_extuart(void)
110{ 106{
111 return platform_device_register(&serial_device); 107 return platform_device_register(&serial_device);
112} 108}
113#else
114static inline int mxc_init_extuart(void)
115{
116 return 0;
117}
118#endif
119 109
120#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
121static const struct imxuart_platform_data uart_pdata __initconst = { 110static const struct imxuart_platform_data uart_pdata __initconst = {
122 .flags = IMXUART_HAVE_RTSCTS, 111 .flags = IMXUART_HAVE_RTSCTS,
123}; 112};
@@ -134,11 +123,6 @@ static inline void mxc_init_imx_uart(void)
134 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); 123 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
135 imx31_add_imx_uart0(&uart_pdata); 124 imx31_add_imx_uart0(&uart_pdata);
136} 125}
137#else /* !SERIAL_IMX */
138static inline void mxc_init_imx_uart(void)
139{
140}
141#endif /* !SERIAL_IMX */
142 126
143static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc) 127static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
144{ 128{
@@ -160,7 +144,7 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
160 144
161/* 145/*
162 * Disable an expio pin's interrupt by setting the bit in the imr. 146 * Disable an expio pin's interrupt by setting the bit in the imr.
163 * @param irq an expio virtual irq number 147 * @param d an expio virtual irq description
164 */ 148 */
165static void expio_mask_irq(struct irq_data *d) 149static void expio_mask_irq(struct irq_data *d)
166{ 150{
@@ -172,7 +156,7 @@ static void expio_mask_irq(struct irq_data *d)
172 156
173/* 157/*
174 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. 158 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
175 * @param irq an expanded io virtual irq number 159 * @param d an expio virtual irq description
176 */ 160 */
177static void expio_ack_irq(struct irq_data *d) 161static void expio_ack_irq(struct irq_data *d)
178{ 162{
@@ -183,7 +167,7 @@ static void expio_ack_irq(struct irq_data *d)
183 167
184/* 168/*
185 * Enable a expio pin's interrupt by clearing the bit in the imr. 169 * Enable a expio pin's interrupt by clearing the bit in the imr.
186 * @param irq a expio virtual irq number 170 * @param d an expio virtual irq description
187 */ 171 */
188static void expio_unmask_irq(struct irq_data *d) 172static void expio_unmask_irq(struct irq_data *d)
189{ 173{
@@ -476,7 +460,6 @@ static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
476}; 460};
477#endif 461#endif
478 462
479#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
480static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = { 463static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
481#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 464#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
482 { 465 {
@@ -497,11 +480,6 @@ static void mxc_init_i2c(void)
497 480
498 imx31_add_imx_i2c1(NULL); 481 imx31_add_imx_i2c1(NULL);
499} 482}
500#else
501static void mxc_init_i2c(void)
502{
503}
504#endif
505 483
506static unsigned int ssi_pins[] = { 484static unsigned int ssi_pins[] = {
507 MX31_PIN_SFS5__SFS5, 485 MX31_PIN_SFS5__SFS5,
@@ -516,9 +494,7 @@ static void mxc_init_audio(void)
516 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); 494 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
517} 495}
518 496
519/*! 497/* static mappings */
520 * This structure defines static mappings for the i.MX31ADS board.
521 */
522static struct map_desc mx31ads_io_desc[] __initdata = { 498static struct map_desc mx31ads_io_desc[] __initdata = {
523 { 499 {
524 .virtual = MX31_CS4_BASE_ADDR_VIRT, 500 .virtual = MX31_CS4_BASE_ADDR_VIRT,
@@ -528,9 +504,6 @@ static struct map_desc mx31ads_io_desc[] __initdata = {
528 }, 504 },
529}; 505};
530 506
531/*!
532 * Set up static virtual mappings.
533 */
534static void __init mx31ads_map_io(void) 507static void __init mx31ads_map_io(void)
535{ 508{
536 mx31_map_io(); 509 mx31_map_io();
@@ -543,10 +516,7 @@ static void __init mx31ads_init_irq(void)
543 mx31ads_init_expio(); 516 mx31ads_init_expio();
544} 517}
545 518
546/*! 519static void __init mx31ads_init(void)
547 * Board specific initialization.
548 */
549static void __init mxc_board_init(void)
550{ 520{
551 mxc_init_extuart(); 521 mxc_init_extuart();
552 mxc_init_imx_uart(); 522 mxc_init_imx_uart();
@@ -563,15 +533,12 @@ static struct sys_timer mx31ads_timer = {
563 .init = mx31ads_timer_init, 533 .init = mx31ads_timer_init,
564}; 534};
565 535
566/*
567 * The following uses standard kernel macros defined in arch.h in order to
568 * initialize __mach_desc_MX31ADS data structure.
569 */
570MACHINE_START(MX31ADS, "Freescale MX31ADS") 536MACHINE_START(MX31ADS, "Freescale MX31ADS")
571 /* Maintainer: Freescale Semiconductor, Inc. */ 537 /* Maintainer: Freescale Semiconductor, Inc. */
572 .boot_params = MX3x_PHYS_OFFSET + 0x100, 538 .boot_params = MX3x_PHYS_OFFSET + 0x100,
573 .map_io = mx31ads_map_io, 539 .map_io = mx31ads_map_io,
574 .init_irq = mx31ads_init_irq, 540 .init_early = imx31_init_early,
575 .init_machine = mxc_board_init, 541 .init_irq = mx31ads_init_irq,
576 .timer = &mx31ads_timer, 542 .timer = &mx31ads_timer,
543 .init_machine = mx31ads_init,
577MACHINE_END 544MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 2c595483f35..ed95745163b 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -24,6 +24,7 @@
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27#include <linux/delay.h>
27#include <linux/platform_device.h> 28#include <linux/platform_device.h>
28#include <linux/interrupt.h> 29#include <linux/interrupt.h>
29#include <linux/smsc911x.h> 30#include <linux/smsc911x.h>
@@ -110,55 +111,9 @@ static struct platform_device physmap_flash_device = {
110 111
111/* USB */ 112/* USB */
112 113
113#if defined(CONFIG_USB_ULPI)
114
115#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ 114#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
116 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) 115 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
117 116
118static int usbotg_init(struct platform_device *pdev)
119{
120 unsigned int pins[] = {
121 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
122 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
123 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
124 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
125 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
126 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
127 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
128 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
129 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
130 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
131 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
132 MX31_PIN_USBOTG_STP__USBOTG_STP,
133 };
134
135 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG");
136
137 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
138 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
139 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
140 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
141 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
142 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
143 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
144 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
145 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
146 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
147 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
148 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
149
150 mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true);
151 mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true);
152
153 /* chip select */
154 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO),
155 "USBOTG_CS");
156 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS");
157 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0);
158
159 return 0;
160}
161
162static int usbh1_init(struct platform_device *pdev) 117static int usbh1_init(struct platform_device *pdev)
163{ 118{
164 int pins[] = { 119 int pins[] = {
@@ -183,7 +138,10 @@ static int usbh1_init(struct platform_device *pdev)
183 138
184 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); 139 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
185 140
186 return 0; 141 mdelay(10);
142
143 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
144 MXC_EHCI_INTERFACE_SINGLE_UNI);
187} 145}
188 146
189static int usbh2_init(struct platform_device *pdev) 147static int usbh2_init(struct platform_device *pdev)
@@ -220,41 +178,30 @@ static int usbh2_init(struct platform_device *pdev)
220 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); 178 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
221 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); 179 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
222 180
223 return 0; 181 mdelay(10);
224}
225 182
226static struct mxc_usbh_platform_data usbotg_pdata = { 183 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
227 .init = usbotg_init, 184}
228 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
229 .flags = MXC_EHCI_POWER_PINS_ENABLED,
230};
231 185
232static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { 186static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
233 .init = usbh1_init, 187 .init = usbh1_init,
234 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, 188 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
235 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
236}; 189};
237 190
238static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 191static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
239 .init = usbh2_init, 192 .init = usbh2_init,
240 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 193 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
241 .flags = MXC_EHCI_POWER_PINS_ENABLED,
242}; 194};
243 195
244static void lilly1131_usb_init(void) 196static void lilly1131_usb_init(void)
245{ 197{
246 usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
247 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
248 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
249 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
250
251 imx31_add_mxc_ehci_hs(1, &usbh1_pdata); 198 imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
252 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
253}
254 199
255#else 200 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
256static inline void lilly1131_usb_init(void) {} 201 ULPI_OTG_DRVVBUS_EXT);
257#endif /* CONFIG_USB_ULPI */ 202 if (usbh2_pdata.otg)
203 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
204}
258 205
259/* SPI */ 206/* SPI */
260 207
@@ -274,8 +221,8 @@ static const struct spi_imx_master spi1_pdata __initconst = {
274 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), 221 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
275}; 222};
276 223
277static struct mc13783_platform_data mc13783_pdata __initdata = { 224static struct mc13xxx_platform_data mc13783_pdata __initdata = {
278 .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN, 225 .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
279}; 226};
280 227
281static struct spi_board_info mc13783_dev __initdata = { 228static struct spi_board_info mc13783_dev __initdata = {
@@ -347,10 +294,10 @@ static struct sys_timer mx31lilly_timer = {
347}; 294};
348 295
349MACHINE_START(LILLY1131, "INCO startec LILLY-1131") 296MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
350 .boot_params = MX3x_PHYS_OFFSET + 0x100, 297 .boot_params = MX3x_PHYS_OFFSET + 0x100,
351 .map_io = mx31_map_io, 298 .map_io = mx31_map_io,
352 .init_irq = mx31_init_irq, 299 .init_early = imx31_init_early,
353 .init_machine = mx31lilly_board_init, 300 .init_irq = mx31_init_irq,
354 .timer = &mx31lilly_timer, 301 .timer = &mx31lilly_timer,
302 .init_machine = mx31lilly_board_init,
355MACHINE_END 303MACHINE_END
356
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 9e64c66396e..24a21a384bf 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -27,6 +27,7 @@
27#include <linux/usb/otg.h> 27#include <linux/usb/otg.h>
28#include <linux/usb/ulpi.h> 28#include <linux/usb/ulpi.h>
29#include <linux/mtd/physmap.h> 29#include <linux/mtd/physmap.h>
30#include <linux/delay.h>
30 31
31#include <asm/mach-types.h> 32#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
@@ -111,9 +112,9 @@ static const struct spi_imx_master spi1_pdata __initconst = {
111 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), 112 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
112}; 113};
113 114
114static struct mc13783_platform_data mc13783_pdata __initdata = { 115static struct mc13xxx_platform_data mc13783_pdata __initdata = {
115 .flags = MC13783_USE_RTC | 116 .flags = MC13XXX_USE_RTC |
116 MC13783_USE_REGULATOR, 117 MC13XXX_USE_REGULATOR,
117}; 118};
118 119
119static struct spi_board_info mc13783_spi_dev __initdata = { 120static struct spi_board_info mc13783_spi_dev __initdata = {
@@ -129,7 +130,6 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
129 * USB 130 * USB
130 */ 131 */
131 132
132#if defined(CONFIG_USB_ULPI)
133#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ 133#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
134 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) 134 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
135 135
@@ -167,15 +167,15 @@ static int usbh2_init(struct platform_device *pdev)
167 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); 167 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
168 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); 168 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
169 169
170 return 0; 170 mdelay(10);
171
172 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
171} 173}
172 174
173static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 175static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
174 .init = usbh2_init, 176 .init = usbh2_init,
175 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 177 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
176 .flags = MXC_EHCI_POWER_PINS_ENABLED,
177}; 178};
178#endif
179 179
180/* 180/*
181 * NOR flash 181 * NOR flash
@@ -227,7 +227,7 @@ void __init mx31lite_map_io(void)
227static int mx31lite_baseboard; 227static int mx31lite_baseboard;
228core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444); 228core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
229 229
230static void __init mxc_board_init(void) 230static void __init mx31lite_init(void)
231{ 231{
232 int ret; 232 int ret;
233 233
@@ -252,13 +252,11 @@ static void __init mxc_board_init(void)
252 imx31_add_spi_imx1(&spi1_pdata); 252 imx31_add_spi_imx1(&spi1_pdata);
253 spi_register_board_info(&mc13783_spi_dev, 1); 253 spi_register_board_info(&mc13783_spi_dev, 1);
254 254
255#if defined(CONFIG_USB_ULPI)
256 /* USB */ 255 /* USB */
257 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 256 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
258 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 257 ULPI_OTG_DRVVBUS_EXT);
259 258 if (usbh2_pdata.otg)
260 imx31_add_mxc_ehci_hs(2, &usbh2_pdata); 259 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
261#endif
262 260
263 /* SMSC9117 IRQ pin */ 261 /* SMSC9117 IRQ pin */
264 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); 262 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
@@ -281,9 +279,10 @@ struct sys_timer mx31lite_timer = {
281 279
282MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") 280MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
283 /* Maintainer: Freescale Semiconductor, Inc. */ 281 /* Maintainer: Freescale Semiconductor, Inc. */
284 .boot_params = MX3x_PHYS_OFFSET + 0x100, 282 .boot_params = MX3x_PHYS_OFFSET + 0x100,
285 .map_io = mx31lite_map_io, 283 .map_io = mx31lite_map_io,
286 .init_irq = mx31_init_irq, 284 .init_early = imx31_init_early,
287 .init_machine = mxc_board_init, 285 .init_irq = mx31_init_irq,
288 .timer = &mx31lite_timer, 286 .timer = &mx31lite_timer,
287 .init_machine = mx31lite_init,
289MACHINE_END 288MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 1aa8d65fccb..6f3692bccb8 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -214,7 +214,7 @@ static struct regulator_init_data cam_vreg_data = {
214 .consumer_supplies = cam_consumers, 214 .consumer_supplies = cam_consumers,
215}; 215};
216 216
217static struct mc13783_regulator_init_data moboard_regulators[] = { 217static struct mc13xxx_regulator_init_data moboard_regulators[] = {
218 { 218 {
219 .id = MC13783_REG_VMMC1, 219 .id = MC13783_REG_VMMC1,
220 .init_data = &sdhc_vreg_data, 220 .init_data = &sdhc_vreg_data,
@@ -267,12 +267,12 @@ static struct mc13783_leds_platform_data moboard_leds = {
267 .tc2_period = MC13783_LED_PERIOD_10MS, 267 .tc2_period = MC13783_LED_PERIOD_10MS,
268}; 268};
269 269
270static struct mc13783_platform_data moboard_pmic = { 270static struct mc13xxx_platform_data moboard_pmic = {
271 .regulators = moboard_regulators, 271 .regulators = moboard_regulators,
272 .num_regulators = ARRAY_SIZE(moboard_regulators), 272 .num_regulators = ARRAY_SIZE(moboard_regulators),
273 .leds = &moboard_leds, 273 .leds = &moboard_leds,
274 .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC | 274 .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_RTC |
275 MC13783_USE_ADC | MC13783_USE_LED, 275 MC13XXX_USE_ADC | MC13XXX_USE_LED,
276}; 276};
277 277
278static struct spi_board_info moboard_spi_board_info[] __initdata = { 278static struct spi_board_info moboard_spi_board_info[] __initdata = {
@@ -400,19 +400,24 @@ static void usb_xcvr_reset(void)
400 mdelay(1); 400 mdelay(1);
401} 401}
402 402
403#if defined(CONFIG_USB_ULPI) 403static int moboard_usbh2_init_hw(struct platform_device *pdev)
404{
405 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
406}
404 407
405static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 408static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
409 .init = moboard_usbh2_init_hw,
406 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 410 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
407 .flags = MXC_EHCI_POWER_PINS_ENABLED,
408}; 411};
409 412
410static int __init moboard_usbh2_init(void) 413static int __init moboard_usbh2_init(void)
411{ 414{
412 struct platform_device *pdev; 415 struct platform_device *pdev;
413 416
414 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 417 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
415 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 418 ULPI_OTG_DRVVBUS_EXT);
419 if (!usbh2_pdata.otg)
420 return -ENODEV;
416 421
417 pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); 422 pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
418 if (IS_ERR(pdev)) 423 if (IS_ERR(pdev))
@@ -420,10 +425,6 @@ static int __init moboard_usbh2_init(void)
420 425
421 return 0; 426 return 0;
422} 427}
423#else
424static inline int moboard_usbh2_init(void) { return 0; }
425#endif
426
427 428
428static struct gpio_led mx31moboard_leds[] = { 429static struct gpio_led mx31moboard_leds[] = {
429 { 430 {
@@ -503,7 +504,7 @@ core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
503/* 504/*
504 * Board specific initialization. 505 * Board specific initialization.
505 */ 506 */
506static void __init mxc_board_init(void) 507static void __init mx31moboard_init(void)
507{ 508{
508 mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins), 509 mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
509 "moboard"); 510 "moboard");
@@ -564,10 +565,10 @@ struct sys_timer mx31moboard_timer = {
564 565
565MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") 566MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
566 /* Maintainer: Valentin Longchamp, EPFL Mobots group */ 567 /* Maintainer: Valentin Longchamp, EPFL Mobots group */
567 .boot_params = MX3x_PHYS_OFFSET + 0x100, 568 .boot_params = MX3x_PHYS_OFFSET + 0x100,
568 .map_io = mx31_map_io, 569 .map_io = mx31_map_io,
569 .init_irq = mx31_init_irq, 570 .init_early = imx31_init_early,
570 .init_machine = mxc_board_init, 571 .init_irq = mx31_init_irq,
571 .timer = &mx31moboard_timer, 572 .timer = &mx31moboard_timer,
573 .init_machine = mx31moboard_init,
572MACHINE_END 574MACHINE_END
573
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index b1963f257c2..ff5fe231b8d 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -118,24 +118,42 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
118 MX35_PAD_SD1_DATA1__ESDHC1_DAT1, 118 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
119 MX35_PAD_SD1_DATA2__ESDHC1_DAT2, 119 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
120 MX35_PAD_SD1_DATA3__ESDHC1_DAT3, 120 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
121 /* I2C1 */
122 MX35_PAD_I2C1_CLK__I2C1_SCL,
123 MX35_PAD_I2C1_DAT__I2C1_SDA,
121}; 124};
122 125
126static int mx35_3ds_otg_init(struct platform_device *pdev)
127{
128 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
129}
130
123/* OTG config */ 131/* OTG config */
124static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { 132static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
125 .operating_mode = FSL_USB2_DR_DEVICE, 133 .operating_mode = FSL_USB2_DR_DEVICE,
126 .phy_mode = FSL_USB2_PHY_UTMI_WIDE, 134 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
135 .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
136/*
137 * ENGCM09152 also requires a hardware change.
138 * Please check the MX35 Chip Errata document for details.
139 */
127}; 140};
128 141
129static struct mxc_usbh_platform_data otg_pdata __initdata = { 142static struct mxc_usbh_platform_data otg_pdata __initdata = {
143 .init = mx35_3ds_otg_init,
130 .portsc = MXC_EHCI_MODE_UTMI, 144 .portsc = MXC_EHCI_MODE_UTMI,
131 .flags = MXC_EHCI_INTERNAL_PHY,
132}; 145};
133 146
147static int mx35_3ds_usbh_init(struct platform_device *pdev)
148{
149 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
150 MXC_EHCI_INTERNAL_PHY);
151}
152
134/* USB HOST config */ 153/* USB HOST config */
135static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { 154static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
155 .init = mx35_3ds_usbh_init,
136 .portsc = MXC_EHCI_MODE_SERIAL, 156 .portsc = MXC_EHCI_MODE_SERIAL,
137 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI |
138 MXC_EHCI_INTERNAL_PHY,
139}; 157};
140 158
141static int otg_mode_host; 159static int otg_mode_host;
@@ -153,10 +171,14 @@ static int __init mx35_3ds_otg_mode(char *options)
153} 171}
154__setup("otg_mode=", mx35_3ds_otg_mode); 172__setup("otg_mode=", mx35_3ds_otg_mode);
155 173
174static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
175 .bitrate = 100000,
176};
177
156/* 178/*
157 * Board specific initialization. 179 * Board specific initialization.
158 */ 180 */
159static void __init mxc_board_init(void) 181static void __init mx35_3ds_init(void)
160{ 182{
161 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); 183 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
162 184
@@ -180,6 +202,7 @@ static void __init mxc_board_init(void)
180 if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) 202 if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
181 pr_warn("Init of the debugboard failed, all " 203 pr_warn("Init of the debugboard failed, all "
182 "devices on the debugboard are unusable.\n"); 204 "devices on the debugboard are unusable.\n");
205 imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
183} 206}
184 207
185static void __init mx35pdk_timer_init(void) 208static void __init mx35pdk_timer_init(void)
@@ -193,9 +216,10 @@ struct sys_timer mx35pdk_timer = {
193 216
194MACHINE_START(MX35_3DS, "Freescale MX35PDK") 217MACHINE_START(MX35_3DS, "Freescale MX35PDK")
195 /* Maintainer: Freescale Semiconductor, Inc */ 218 /* Maintainer: Freescale Semiconductor, Inc */
196 .boot_params = MX3x_PHYS_OFFSET + 0x100, 219 .boot_params = MX3x_PHYS_OFFSET + 0x100,
197 .map_io = mx35_map_io, 220 .map_io = mx35_map_io,
198 .init_irq = mx35_init_irq, 221 .init_early = imx35_init_early,
199 .init_machine = mxc_board_init, 222 .init_irq = mx35_init_irq,
200 .timer = &mx35pdk_timer, 223 .timer = &mx35pdk_timer,
224 .init_machine = mx35_3ds_init,
201MACHINE_END 225MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index b752f6bc20a..f07d3bded67 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -533,17 +533,25 @@ static struct platform_device pcm970_sja1000 = {
533 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), 533 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
534}; 534};
535 535
536#if defined(CONFIG_USB_ULPI) 536static int pcm037_otg_init(struct platform_device *pdev)
537{
538 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
539}
540
537static struct mxc_usbh_platform_data otg_pdata __initdata = { 541static struct mxc_usbh_platform_data otg_pdata __initdata = {
542 .init = pcm037_otg_init,
538 .portsc = MXC_EHCI_MODE_ULPI, 543 .portsc = MXC_EHCI_MODE_ULPI,
539 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
540}; 544};
541 545
546static int pcm037_usbh2_init(struct platform_device *pdev)
547{
548 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
549}
550
542static struct mxc_usbh_platform_data usbh2_pdata __initdata = { 551static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
552 .init = pcm037_usbh2_init,
543 .portsc = MXC_EHCI_MODE_ULPI, 553 .portsc = MXC_EHCI_MODE_ULPI,
544 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
545}; 554};
546#endif
547 555
548static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 556static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
549 .operating_mode = FSL_USB2_DR_DEVICE, 557 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -568,7 +576,7 @@ __setup("otg_mode=", pcm037_otg_mode);
568/* 576/*
569 * Board specific initialization. 577 * Board specific initialization.
570 */ 578 */
571static void __init mxc_board_init(void) 579static void __init pcm037_init(void)
572{ 580{
573 int ret; 581 int ret;
574 582
@@ -646,19 +654,18 @@ static void __init mxc_board_init(void)
646 654
647 platform_device_register(&pcm970_sja1000); 655 platform_device_register(&pcm970_sja1000);
648 656
649#if defined(CONFIG_USB_ULPI)
650 if (otg_mode_host) { 657 if (otg_mode_host) {
651 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 658 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
652 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 659 ULPI_OTG_DRVVBUS_EXT);
653 660 if (otg_pdata.otg)
654 imx31_add_mxc_ehci_otg(&otg_pdata); 661 imx31_add_mxc_ehci_otg(&otg_pdata);
655 } 662 }
656 663
657 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 664 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
658 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 665 ULPI_OTG_DRVVBUS_EXT);
666 if (usbh2_pdata.otg)
667 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
659 668
660 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
661#endif
662 if (!otg_mode_host) 669 if (!otg_mode_host)
663 imx31_add_fsl_usb2_udc(&otg_device_pdata); 670 imx31_add_fsl_usb2_udc(&otg_device_pdata);
664 671
@@ -675,9 +682,10 @@ struct sys_timer pcm037_timer = {
675 682
676MACHINE_START(PCM037, "Phytec Phycore pcm037") 683MACHINE_START(PCM037, "Phytec Phycore pcm037")
677 /* Maintainer: Pengutronix */ 684 /* Maintainer: Pengutronix */
678 .boot_params = MX3x_PHYS_OFFSET + 0x100, 685 .boot_params = MX3x_PHYS_OFFSET + 0x100,
679 .map_io = mx31_map_io, 686 .map_io = mx31_map_io,
680 .init_irq = mx31_init_irq, 687 .init_early = imx31_init_early,
681 .init_machine = mxc_board_init, 688 .init_irq = mx31_init_irq,
682 .timer = &pcm037_timer, 689 .timer = &pcm037_timer,
690 .init_machine = pcm037_init,
683MACHINE_END 691MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index fda56545d2f..df6fb07d037 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -180,9 +180,7 @@ static int __init eet_init_devices(void)
180 180
181 /* SPI */ 181 /* SPI */
182 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); 182 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
183#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
184 imx31_add_spi_imx0(&pcm037_spi1_pdata); 183 imx31_add_spi_imx0(&pcm037_spi1_pdata);
185#endif
186 184
187 platform_device_register(&pcm037_gpio_keys_device); 185 platform_device_register(&pcm037_gpio_keys_device);
188 186
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index bcf83fc7e70..b3ecfb22d24 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -115,7 +115,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
115 .flags = IMXUART_HAVE_RTSCTS, 115 .flags = IMXUART_HAVE_RTSCTS,
116}; 116};
117 117
118#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
119static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { 118static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
120 .bitrate = 50000, 119 .bitrate = 50000,
121}; 120};
@@ -134,7 +133,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
134 I2C_BOARD_INFO("pcf8563", 0x51), 133 I2C_BOARD_INFO("pcf8563", 0x51),
135 } 134 }
136}; 135};
137#endif
138 136
139static struct platform_device *devices[] __initdata = { 137static struct platform_device *devices[] __initdata = {
140 &pcm043_flash, 138 &pcm043_flash,
@@ -221,9 +219,9 @@ static iomux_v3_cfg_t pcm043_pads[] = {
221 MX35_PAD_SD1_DATA3__ESDHC1_DAT3, 219 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
222}; 220};
223 221
224#define AC97_GPIO_TXFS (1 * 32 + 31) 222#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
225#define AC97_GPIO_TXD (1 * 32 + 28) 223#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
226#define AC97_GPIO_RESET (1 * 32 + 0) 224#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
227 225
228static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) 226static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
229{ 227{
@@ -307,18 +305,26 @@ pcm037_nand_board_info __initconst = {
307 .hw_ecc = 1, 305 .hw_ecc = 1,
308}; 306};
309 307
310#if defined(CONFIG_USB_ULPI) 308static int pcm043_otg_init(struct platform_device *pdev)
309{
310 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
311}
312
311static struct mxc_usbh_platform_data otg_pdata __initdata = { 313static struct mxc_usbh_platform_data otg_pdata __initdata = {
314 .init = pcm043_otg_init,
312 .portsc = MXC_EHCI_MODE_UTMI, 315 .portsc = MXC_EHCI_MODE_UTMI,
313 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
314}; 316};
315 317
318static int pcm043_usbh1_init(struct platform_device *pdev)
319{
320 return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
321 MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
322}
323
316static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { 324static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
325 .init = pcm043_usbh1_init,
317 .portsc = MXC_EHCI_MODE_SERIAL, 326 .portsc = MXC_EHCI_MODE_SERIAL,
318 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
319 MXC_EHCI_IPPUE_DOWN,
320}; 327};
321#endif
322 328
323static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { 329static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
324 .operating_mode = FSL_USB2_DR_DEVICE, 330 .operating_mode = FSL_USB2_DR_DEVICE,
@@ -343,7 +349,7 @@ __setup("otg_mode=", pcm043_otg_mode);
343/* 349/*
344 * Board specific initialization. 350 * Board specific initialization.
345 */ 351 */
346static void __init mxc_board_init(void) 352static void __init pcm043_init(void)
347{ 353{
348 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); 354 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
349 355
@@ -369,26 +375,22 @@ static void __init mxc_board_init(void)
369 375
370 imx35_add_imx_uart1(&uart_pdata); 376 imx35_add_imx_uart1(&uart_pdata);
371 377
372#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
373 i2c_register_board_info(0, pcm043_i2c_devices, 378 i2c_register_board_info(0, pcm043_i2c_devices,
374 ARRAY_SIZE(pcm043_i2c_devices)); 379 ARRAY_SIZE(pcm043_i2c_devices));
375 380
376 imx35_add_imx_i2c0(&pcm043_i2c0_data); 381 imx35_add_imx_i2c0(&pcm043_i2c0_data);
377#endif
378 382
379 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 383 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
380 mxc_register_device(&mx3_fb, &mx3fb_pdata); 384 mxc_register_device(&mx3_fb, &mx3fb_pdata);
381 385
382#if defined(CONFIG_USB_ULPI)
383 if (otg_mode_host) { 386 if (otg_mode_host) {
384 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 387 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
385 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 388 ULPI_OTG_DRVVBUS_EXT);
386 389 if (otg_pdata.otg)
387 imx35_add_mxc_ehci_otg(&otg_pdata); 390 imx35_add_mxc_ehci_otg(&otg_pdata);
388 } 391 }
389
390 imx35_add_mxc_ehci_hs(&usbh1_pdata); 392 imx35_add_mxc_ehci_hs(&usbh1_pdata);
391#endif 393
392 if (!otg_mode_host) 394 if (!otg_mode_host)
393 imx35_add_fsl_usb2_udc(&otg_device_pdata); 395 imx35_add_fsl_usb2_udc(&otg_device_pdata);
394 396
@@ -407,10 +409,10 @@ struct sys_timer pcm043_timer = {
407 409
408MACHINE_START(PCM043, "Phytec Phycore pcm043") 410MACHINE_START(PCM043, "Phytec Phycore pcm043")
409 /* Maintainer: Pengutronix */ 411 /* Maintainer: Pengutronix */
410 .boot_params = MX3x_PHYS_OFFSET + 0x100, 412 .boot_params = MX3x_PHYS_OFFSET + 0x100,
411 .map_io = mx35_map_io, 413 .map_io = mx35_map_io,
412 .init_irq = mx35_init_irq, 414 .init_early = imx35_init_early,
413 .init_machine = mxc_board_init, 415 .init_irq = mx35_init_irq,
414 .timer = &pcm043_timer, 416 .timer = &pcm043_timer,
417 .init_machine = pcm043_init,
415MACHINE_END 418MACHINE_END
416
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index fd1050c4096..17f758b7762 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -54,10 +54,6 @@
54 54
55#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1) 55#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
56 56
57/*
58 * This file contains the board-specific initialization routines.
59 */
60
61static const struct imxuart_platform_data uart_pdata __initconst = { 57static const struct imxuart_platform_data uart_pdata __initconst = {
62 .flags = IMXUART_HAVE_RTSCTS, 58 .flags = IMXUART_HAVE_RTSCTS,
63}; 59};
@@ -247,7 +243,7 @@ static void __init qong_init_fpga(void)
247/* 243/*
248 * Board specific initialization. 244 * Board specific initialization.
249 */ 245 */
250static void __init mxc_board_init(void) 246static void __init qong_init(void)
251{ 247{
252 mxc_init_imx_uart(); 248 mxc_init_imx_uart();
253 qong_init_nor_mtd(); 249 qong_init_nor_mtd();
@@ -263,16 +259,12 @@ static struct sys_timer qong_timer = {
263 .init = qong_timer_init, 259 .init = qong_timer_init,
264}; 260};
265 261
266/*
267 * The following uses standard kernel macros defined in arch.h in order to
268 * initialize __mach_desc_QONG data structure.
269 */
270
271MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") 262MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
272 /* Maintainer: DENX Software Engineering GmbH */ 263 /* Maintainer: DENX Software Engineering GmbH */
273 .boot_params = MX3x_PHYS_OFFSET + 0x100, 264 .boot_params = MX3x_PHYS_OFFSET + 0x100,
274 .map_io = mx31_map_io, 265 .map_io = mx31_map_io,
275 .init_irq = mx31_init_irq, 266 .init_early = imx31_init_early,
276 .init_machine = mxc_board_init, 267 .init_irq = mx31_init_irq,
277 .timer = &qong_timer, 268 .timer = &qong_timer,
269 .init_machine = qong_init,
278MACHINE_END 270MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-mx3/mach-vpr200.c
new file mode 100644
index 00000000000..2cf390fbd98
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-vpr200.c
@@ -0,0 +1,328 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
4 * Copyright 2010 Creative Product Design
5 *
6 * Derived from mx35 3stack.
7 * Original author: Fabio Estevam <fabio.estevam@freescale.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/physmap.h>
24#include <linux/memory.h>
25#include <linux/gpio.h>
26
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/time.h>
30
31#include <mach/hardware.h>
32#include <mach/common.h>
33#include <mach/iomux-mx35.h>
34#include <mach/irqs.h>
35#include <mach/ipu.h>
36#include <mach/mx3fb.h>
37
38#include <linux/i2c.h>
39#include <linux/i2c/at24.h>
40#include <linux/mfd/mc13xxx.h>
41#include <linux/gpio_keys.h>
42
43#include "devices-imx35.h"
44#include "devices.h"
45
46#define GPIO_LCDPWR IMX_GPIO_NR(1, 2)
47#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
48
49#define GPIO_BUTTON1 IMX_GPIO_NR(1, 4)
50#define GPIO_BUTTON2 IMX_GPIO_NR(1, 5)
51#define GPIO_BUTTON3 IMX_GPIO_NR(1, 7)
52#define GPIO_BUTTON4 IMX_GPIO_NR(1, 8)
53#define GPIO_BUTTON5 IMX_GPIO_NR(1, 9)
54#define GPIO_BUTTON6 IMX_GPIO_NR(1, 10)
55#define GPIO_BUTTON7 IMX_GPIO_NR(1, 11)
56#define GPIO_BUTTON8 IMX_GPIO_NR(1, 12)
57
58static const struct fb_videomode fb_modedb[] = {
59 {
60 /* 800x480 @ 60 Hz */
61 .name = "PT0708048",
62 .refresh = 60,
63 .xres = 800,
64 .yres = 480,
65 .pixclock = KHZ2PICOS(33260),
66 .left_margin = 50,
67 .right_margin = 156,
68 .upper_margin = 10,
69 .lower_margin = 10,
70 .hsync_len = 1, /* note: DE only display */
71 .vsync_len = 1, /* note: DE only display */
72 .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
73 .vmode = FB_VMODE_NONINTERLACED,
74 .flag = 0,
75 }, {
76 /* 800x480 @ 60 Hz */
77 .name = "CTP-CLAA070LC0ACW",
78 .refresh = 60,
79 .xres = 800,
80 .yres = 480,
81 .pixclock = KHZ2PICOS(27000),
82 .left_margin = 50,
83 .right_margin = 50, /* whole line should have 900 clocks */
84 .upper_margin = 10,
85 .lower_margin = 10, /* whole frame should have 500 lines */
86 .hsync_len = 1, /* note: DE only display */
87 .vsync_len = 1, /* note: DE only display */
88 .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
89 .vmode = FB_VMODE_NONINTERLACED,
90 .flag = 0,
91 }
92};
93
94static struct ipu_platform_data mx3_ipu_data = {
95 .irq_base = MXC_IPU_IRQ_START,
96};
97
98static struct mx3fb_platform_data mx3fb_pdata = {
99 .dma_dev = &mx3_ipu.dev,
100 .name = "PT0708048",
101 .mode = fb_modedb,
102 .num_modes = ARRAY_SIZE(fb_modedb),
103};
104
105static struct physmap_flash_data vpr200_flash_data = {
106 .width = 2,
107};
108
109static struct resource vpr200_flash_resource = {
110 .start = MX35_CS0_BASE_ADDR,
111 .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
112 .flags = IORESOURCE_MEM,
113};
114
115static struct platform_device vpr200_flash = {
116 .name = "physmap-flash",
117 .id = 0,
118 .dev = {
119 .platform_data = &vpr200_flash_data,
120 },
121 .resource = &vpr200_flash_resource,
122 .num_resources = 1,
123};
124
125static const struct mxc_nand_platform_data
126 vpr200_nand_board_info __initconst = {
127 .width = 1,
128 .hw_ecc = 1,
129 .flash_bbt = 1,
130};
131
132#define VPR_KEY_DEBOUNCE 500
133static struct gpio_keys_button vpr200_gpio_keys_table[] = {
134 {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE},
135 {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE},
136 {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE},
137 {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE},
138 {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE},
139 {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE},
140 {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE},
141 {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
142};
143
144static struct gpio_keys_platform_data vpr200_gpio_keys_data = {
145 .buttons = vpr200_gpio_keys_table,
146 .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
147};
148
149static struct platform_device vpr200_device_gpiokeys = {
150 .name = "gpio-keys",
151 .dev = {
152 .platform_data = &vpr200_gpio_keys_data,
153 }
154};
155
156static struct mc13xxx_platform_data vpr200_pmic = {
157 .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
158};
159
160static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = {
161 .bitrate = 50000,
162};
163
164static struct at24_platform_data vpr200_eeprom = {
165 .byte_len = 2048 / 8,
166 .page_size = 1,
167};
168
169static struct i2c_board_info vpr200_i2c_devices[] = {
170 {
171 I2C_BOARD_INFO("at24", 0x50), /* E0=0, E1=0, E2=0 */
172 .platform_data = &vpr200_eeprom,
173 }, {
174 I2C_BOARD_INFO("mc13892", 0x08),
175 .platform_data = &vpr200_pmic,
176 .irq = gpio_to_irq(GPIO_PMIC_INT),
177 }
178};
179
180static iomux_v3_cfg_t vpr200_pads[] = {
181 /* UART1 */
182 MX35_PAD_TXD1__UART1_TXD_MUX,
183 MX35_PAD_RXD1__UART1_RXD_MUX,
184 /* UART3 */
185 MX35_PAD_ATA_DATA10__UART3_RXD_MUX,
186 MX35_PAD_ATA_DATA11__UART3_TXD_MUX,
187 /* FEC */
188 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
189 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
190 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
191 MX35_PAD_FEC_COL__FEC_COL,
192 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
193 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
194 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
195 MX35_PAD_FEC_MDC__FEC_MDC,
196 MX35_PAD_FEC_MDIO__FEC_MDIO,
197 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
198 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
199 MX35_PAD_FEC_CRS__FEC_CRS,
200 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
201 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
202 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
203 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
204 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
205 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
206 /* Display */
207 MX35_PAD_LD0__IPU_DISPB_DAT_0,
208 MX35_PAD_LD1__IPU_DISPB_DAT_1,
209 MX35_PAD_LD2__IPU_DISPB_DAT_2,
210 MX35_PAD_LD3__IPU_DISPB_DAT_3,
211 MX35_PAD_LD4__IPU_DISPB_DAT_4,
212 MX35_PAD_LD5__IPU_DISPB_DAT_5,
213 MX35_PAD_LD6__IPU_DISPB_DAT_6,
214 MX35_PAD_LD7__IPU_DISPB_DAT_7,
215 MX35_PAD_LD8__IPU_DISPB_DAT_8,
216 MX35_PAD_LD9__IPU_DISPB_DAT_9,
217 MX35_PAD_LD10__IPU_DISPB_DAT_10,
218 MX35_PAD_LD11__IPU_DISPB_DAT_11,
219 MX35_PAD_LD12__IPU_DISPB_DAT_12,
220 MX35_PAD_LD13__IPU_DISPB_DAT_13,
221 MX35_PAD_LD14__IPU_DISPB_DAT_14,
222 MX35_PAD_LD15__IPU_DISPB_DAT_15,
223 MX35_PAD_LD16__IPU_DISPB_DAT_16,
224 MX35_PAD_LD17__IPU_DISPB_DAT_17,
225 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
226 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
227 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
228 /* LCD Enable */
229 MX35_PAD_D3_VSYNC__GPIO1_2,
230 /* USBOTG */
231 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
232 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
233 /* SDCARD */
234 MX35_PAD_SD1_CMD__ESDHC1_CMD,
235 MX35_PAD_SD1_CLK__ESDHC1_CLK,
236 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
237 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
238 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
239 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
240 /* PMIC */
241 MX35_PAD_GPIO2_0__GPIO2_0,
242 /* GPIO keys */
243 MX35_PAD_SCKR__GPIO1_4,
244 MX35_PAD_COMPARE__GPIO1_5,
245 MX35_PAD_SCKT__GPIO1_7,
246 MX35_PAD_FST__GPIO1_8,
247 MX35_PAD_HCKT__GPIO1_9,
248 MX35_PAD_TX5_RX0__GPIO1_10,
249 MX35_PAD_TX4_RX1__GPIO1_11,
250 MX35_PAD_TX3_RX2__GPIO1_12,
251};
252
253/* USB Device config */
254static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
255 .operating_mode = FSL_USB2_DR_DEVICE,
256 .phy_mode = FSL_USB2_PHY_UTMI,
257 .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
258};
259
260/* USB HOST config */
261static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
262 .portsc = MXC_EHCI_MODE_SERIAL,
263 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI |
264 MXC_EHCI_INTERNAL_PHY,
265};
266
267static struct platform_device *devices[] __initdata = {
268 &vpr200_flash,
269 &vpr200_device_gpiokeys,
270};
271
272/*
273 * Board specific initialization.
274 */
275static void __init vpr200_board_init(void)
276{
277 mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
278
279 imx35_add_fec(NULL);
280 imx35_add_imx2_wdt(NULL);
281
282 platform_add_devices(devices, ARRAY_SIZE(devices));
283
284 if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR"))
285 printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n");
286 else
287 gpio_direction_output(GPIO_LCDPWR, 0);
288
289 if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT"))
290 printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n");
291 else
292 gpio_direction_input(GPIO_PMIC_INT);
293
294 imx35_add_imx_uart0(NULL);
295 imx35_add_imx_uart2(NULL);
296
297 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
298 mxc_register_device(&mx3_fb, &mx3fb_pdata);
299
300 imx35_add_fsl_usb2_udc(&otg_device_pdata);
301 imx35_add_mxc_ehci_hs(&usb_host_pdata);
302
303 imx35_add_mxc_nand(&vpr200_nand_board_info);
304 imx35_add_sdhci_esdhc_imx(0, NULL);
305
306 i2c_register_board_info(0, vpr200_i2c_devices,
307 ARRAY_SIZE(vpr200_i2c_devices));
308
309 imx35_add_imx_i2c0(&vpr200_i2c0_data);
310}
311
312static void __init vpr200_timer_init(void)
313{
314 mx35_clocks_init();
315}
316
317struct sys_timer vpr200_timer = {
318 .init = vpr200_timer_init,
319};
320
321MACHINE_START(VPR200, "VPR200")
322 /* Maintainer: Creative Product Design */
323 .map_io = mx35_map_io,
324 .init_early = imx35_init_early,
325 .init_irq = mx35_init_irq,
326 .timer = &vpr200_timer,
327 .init_machine = vpr200_board_init,
328MACHINE_END
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 47118f76024..54d7174b420 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -27,14 +27,8 @@
27#include <mach/common.h> 27#include <mach/common.h>
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/iomux-v3.h> 29#include <mach/iomux-v3.h>
30 30#include <mach/gpio.h>
31/*! 31#include <mach/irqs.h>
32 * @file mm.c
33 *
34 * @brief This file creates static virtual to physical mappings, common to all MX3 boards.
35 *
36 * @ingroup Memory
37 */
38 32
39#ifdef CONFIG_SOC_IMX31 33#ifdef CONFIG_SOC_IMX31
40static struct map_desc mx31_io_desc[] __initdata = { 34static struct map_desc mx31_io_desc[] __initdata = {
@@ -52,17 +46,25 @@ static struct map_desc mx31_io_desc[] __initdata = {
52 */ 46 */
53void __init mx31_map_io(void) 47void __init mx31_map_io(void)
54{ 48{
49 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
50}
51
52void __init imx31_init_early(void)
53{
55 mxc_set_cpu_type(MXC_CPU_MX31); 54 mxc_set_cpu_type(MXC_CPU_MX31);
56 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); 55 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
57
58 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
59} 56}
60 57
61int imx31_register_gpios(void); 58static struct mxc_gpio_port imx31_gpio_ports[] = {
59 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
60 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
61 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
62};
63
62void __init mx31_init_irq(void) 64void __init mx31_init_irq(void)
63{ 65{
64 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); 66 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
65 imx31_register_gpios(); 67 mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
66} 68}
67#endif /* ifdef CONFIG_SOC_IMX31 */ 69#endif /* ifdef CONFIG_SOC_IMX31 */
68 70
@@ -77,18 +79,26 @@ static struct map_desc mx35_io_desc[] __initdata = {
77 79
78void __init mx35_map_io(void) 80void __init mx35_map_io(void)
79{ 81{
82 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
83}
84
85void __init imx35_init_early(void)
86{
80 mxc_set_cpu_type(MXC_CPU_MX35); 87 mxc_set_cpu_type(MXC_CPU_MX35);
81 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); 88 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
82 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); 89 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
83
84 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
85} 90}
86 91
87int imx35_register_gpios(void); 92static struct mxc_gpio_port imx35_gpio_ports[] = {
93 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
94 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
95 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
96};
97
88void __init mx35_init_irq(void) 98void __init mx35_init_irq(void)
89{ 99{
90 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); 100 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
91 imx35_register_gpios(); 101 mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
92} 102}
93#endif /* ifdef CONFIG_SOC_IMX35 */ 103#endif /* ifdef CONFIG_SOC_IMX35 */
94 104
@@ -129,4 +139,3 @@ static int mxc_init_l2x0(void)
129 139
130arch_initcall(mxc_init_l2x0); 140arch_initcall(mxc_init_l2x0);
131#endif 141#endif
132
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 94a0b9e4b7f..6410b9c48a0 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -15,6 +15,7 @@
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/delay.h>
18#include <linux/platform_device.h> 19#include <linux/platform_device.h>
19#include <linux/slab.h> 20#include <linux/slab.h>
20#include <linux/types.h> 21#include <linux/types.h>
@@ -149,7 +150,10 @@ static int devboard_usbh1_hw_init(struct platform_device *pdev)
149 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); 150 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
150 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); 151 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
151 152
152 return 0; 153 mdelay(10);
154
155 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
156 MXC_EHCI_INTERFACE_SINGLE_UNI);
153} 157}
154 158
155#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) 159#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
@@ -187,7 +191,6 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
187static struct mxc_usbh_platform_data usbh1_pdata __initdata = { 191static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
188 .init = devboard_usbh1_hw_init, 192 .init = devboard_usbh1_hw_init,
189 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, 193 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
190 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
191}; 194};
192 195
193static int __init devboard_usbh1_init(void) 196static int __init devboard_usbh1_init(void)
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index f449a97ae1a..57f7b00cb70 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -265,7 +265,10 @@ static int marxbot_usbh1_hw_init(struct platform_device *pdev)
265 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); 265 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
266 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); 266 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
267 267
268 return 0; 268 mdelay(10);
269
270 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
271 MXC_EHCI_INTERFACE_SINGLE_UNI);
269} 272}
270 273
271#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) 274#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
@@ -303,7 +306,6 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
303static struct mxc_usbh_platform_data usbh1_pdata __initdata = { 306static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
304 .init = marxbot_usbh1_hw_init, 307 .init = marxbot_usbh1_hw_init,
305 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, 308 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
306 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
307}; 309};
308 310
309static int __init marxbot_usbh1_init(void) 311static int __init marxbot_usbh1_init(void)
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index bbec3c82264..35f806e737c 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -123,17 +123,24 @@ static const struct fsl_usb2_platform_data usb_pdata __initconst = {
123 123
124#if defined(CONFIG_USB_ULPI) 124#if defined(CONFIG_USB_ULPI)
125 125
126static int smartbot_otg_init(struct platform_device *pdev)
127{
128 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
129}
130
126static struct mxc_usbh_platform_data otg_host_pdata __initdata = { 131static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
132 .init = smartbot_otg_init,
127 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 133 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
128 .flags = MXC_EHCI_POWER_PINS_ENABLED,
129}; 134};
130 135
131static int __init smartbot_otg_host_init(void) 136static int __init smartbot_otg_host_init(void)
132{ 137{
133 struct platform_device *pdev; 138 struct platform_device *pdev;
134 139
135 otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 140 otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
136 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 141 ULPI_OTG_DRVVBUS_EXT);
142 if (!otg_host_pdata.otg)
143 return -ENODEV;
137 144
138 pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); 145 pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
139 if (IS_ERR(pdev)) 146 if (IS_ERR(pdev))
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index de4fa992fc3..83ee08847d4 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,5 +1,6 @@
1if ARCH_MX5 1if ARCH_MX5
2# ARCH_MX51 and ARCH_MX50 are left for compatibility 2# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single
3# image. So for most time, SOC_IMX50/51/53 should be used.
3 4
4config ARCH_MX50 5config ARCH_MX50
5 bool 6 bool
@@ -50,6 +51,7 @@ config MACH_MX51_BABBAGE
50config MACH_MX51_3DS 51config MACH_MX51_3DS
51 bool "Support MX51PDK (3DS)" 52 bool "Support MX51PDK (3DS)"
52 select SOC_IMX51 53 select SOC_IMX51
54 select IMX_HAVE_PLATFORM_IMX2_WDT
53 select IMX_HAVE_PLATFORM_IMX_KEYPAD 55 select IMX_HAVE_PLATFORM_IMX_KEYPAD
54 select IMX_HAVE_PLATFORM_IMX_UART 56 select IMX_HAVE_PLATFORM_IMX_UART
55 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 57 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -112,19 +114,32 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
112 114
113endchoice 115endchoice
114 116
115config MACH_MX51_EFIKAMX 117config MX51_EFIKA_COMMON
116 bool "Support MX51 Genesi Efika MX nettop" 118 bool
117 select SOC_IMX51 119 select SOC_IMX51
118 select IMX_HAVE_PLATFORM_IMX_UART 120 select IMX_HAVE_PLATFORM_IMX_UART
119 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 121 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
120 select IMX_HAVE_PLATFORM_SPI_IMX 122 select IMX_HAVE_PLATFORM_SPI_IMX
123 select MXC_ULPI if USB_ULPI
124
125config MACH_MX51_EFIKAMX
126 bool "Support MX51 Genesi Efika MX nettop"
127 select MX51_EFIKA_COMMON
121 help 128 help
122 Include support for Genesi Efika MX nettop. This includes specific 129 Include support for Genesi Efika MX nettop. This includes specific
123 configurations for the board and its peripherals. 130 configurations for the board and its peripherals.
124 131
132config MACH_MX51_EFIKASB
133 bool "Support MX51 Genesi Efika Smartbook"
134 select MX51_EFIKA_COMMON
135 help
136 Include support for Genesi Efika Smartbook. This includes specific
137 configurations for the board and its peripherals.
138
125config MACH_MX53_EVK 139config MACH_MX53_EVK
126 bool "Support MX53 EVK platforms" 140 bool "Support MX53 EVK platforms"
127 select SOC_IMX53 141 select SOC_IMX53
142 select IMX_HAVE_PLATFORM_IMX2_WDT
128 select IMX_HAVE_PLATFORM_IMX_UART 143 select IMX_HAVE_PLATFORM_IMX_UART
129 select IMX_HAVE_PLATFORM_IMX_I2C 144 select IMX_HAVE_PLATFORM_IMX_I2C
130 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 145 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -136,6 +151,8 @@ config MACH_MX53_EVK
136config MACH_MX53_SMD 151config MACH_MX53_SMD
137 bool "Support MX53 SMD platforms" 152 bool "Support MX53 SMD platforms"
138 select SOC_IMX53 153 select SOC_IMX53
154 select IMX_HAVE_PLATFORM_IMX2_WDT
155 select IMX_HAVE_PLATFORM_IMX_I2C
139 select IMX_HAVE_PLATFORM_IMX_UART 156 select IMX_HAVE_PLATFORM_IMX_UART
140 help 157 help
141 Include support for MX53 SMD platform. This includes specific 158 Include support for MX53 SMD platform. This includes specific
@@ -144,7 +161,10 @@ config MACH_MX53_SMD
144config MACH_MX53_LOCO 161config MACH_MX53_LOCO
145 bool "Support MX53 LOCO platforms" 162 bool "Support MX53 LOCO platforms"
146 select SOC_IMX53 163 select SOC_IMX53
164 select IMX_HAVE_PLATFORM_IMX2_WDT
165 select IMX_HAVE_PLATFORM_IMX_I2C
147 select IMX_HAVE_PLATFORM_IMX_UART 166 select IMX_HAVE_PLATFORM_IMX_UART
167 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
148 help 168 help
149 Include support for MX53 LOCO platform. This includes specific 169 Include support for MX53 LOCO platform. This includes specific
150 configurations for the board and its peripherals. 170 configurations for the board and its peripherals.
@@ -157,6 +177,7 @@ config MACH_MX50_RDP
157 select IMX_HAVE_PLATFORM_IMX_UART 177 select IMX_HAVE_PLATFORM_IMX_UART
158 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 178 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
159 select IMX_HAVE_PLATFORM_SPI_IMX 179 select IMX_HAVE_PLATFORM_SPI_IMX
180 select IMX_HAVE_PLATFORM_FEC
160 help 181 help
161 Include support for MX50 reference design platform (RDP) board. This 182 Include support for MX50 reference design platform (RDP) board. This
162 includes specific configurations for the board and its peripherals. 183 includes specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0d43be98e51..4f63048be3c 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Object file lists. 5# Object file lists.
6obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o 6obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o
7obj-$(CONFIG_SOC_IMX50) += mm-mx50.o 7obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
8 8
9obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o 9obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
@@ -16,5 +16,7 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
16obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o 16obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
17obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o 17obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
18obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o 18obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
19obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
19obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o 20obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
21obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
20obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o 22obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index f8652ef25f8..d0296a94c47 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -60,7 +60,6 @@
60#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 60#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
61#define MX51_USB_PLL_DIV_24_MHZ 0x02 61#define MX51_USB_PLL_DIV_24_MHZ 0x02
62 62
63#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
64static struct plat_serial8250_port serial_platform_data[] = { 63static struct plat_serial8250_port serial_platform_data[] = {
65 { 64 {
66 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000), 65 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
@@ -105,12 +104,9 @@ static struct platform_device serial_device = {
105 .platform_data = serial_platform_data, 104 .platform_data = serial_platform_data,
106 }, 105 },
107}; 106};
108#endif
109 107
110static struct platform_device *devices[] __initdata = { 108static struct platform_device *devices[] __initdata = {
111#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
112 &serial_device, 109 &serial_device,
113#endif
114}; 110};
115 111
116static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { 112static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
@@ -188,7 +184,10 @@ static int initialize_otg_port(struct platform_device *pdev)
188 v |= MX51_USB_PLL_DIV_19_2_MHZ; 184 v |= MX51_USB_PLL_DIV_19_2_MHZ;
189 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); 185 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
190 iounmap(usb_base); 186 iounmap(usb_base);
191 return 0; 187
188 mdelay(10);
189
190 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
192} 191}
193 192
194static int initialize_usbh1_port(struct platform_device *pdev) 193static int initialize_usbh1_port(struct platform_device *pdev)
@@ -206,13 +205,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
206 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); 205 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
207 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); 206 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
208 iounmap(usb_base); 207 iounmap(usb_base);
209 return 0; 208
209 mdelay(10);
210
211 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
212 MXC_EHCI_ITC_NO_THRESHOLD);
210} 213}
211 214
212static struct mxc_usbh_platform_data dr_utmi_config = { 215static struct mxc_usbh_platform_data dr_utmi_config = {
213 .init = initialize_otg_port, 216 .init = initialize_otg_port,
214 .portsc = MXC_EHCI_UTMI_16BIT, 217 .portsc = MXC_EHCI_UTMI_16BIT,
215 .flags = MXC_EHCI_INTERNAL_PHY,
216}; 218};
217 219
218static struct fsl_usb2_platform_data usb_pdata = { 220static struct fsl_usb2_platform_data usb_pdata = {
@@ -223,7 +225,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
223static struct mxc_usbh_platform_data usbh1_config = { 225static struct mxc_usbh_platform_data usbh1_config = {
224 .init = initialize_usbh1_port, 226 .init = initialize_usbh1_port,
225 .portsc = MXC_EHCI_MODE_ULPI, 227 .portsc = MXC_EHCI_MODE_ULPI,
226 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
227}; 228};
228 229
229static int otg_mode_host; 230static int otg_mode_host;
@@ -298,7 +299,8 @@ MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
298 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 299 /* Maintainer: Eric Bénard <eric@eukrea.com> */
299 .boot_params = MX51_PHYS_OFFSET + 0x100, 300 .boot_params = MX51_PHYS_OFFSET + 0x100,
300 .map_io = mx51_map_io, 301 .map_io = mx51_map_io,
302 .init_early = imx51_init_early,
301 .init_irq = mx51_init_irq, 303 .init_irq = mx51_init_irq,
302 .init_machine = eukrea_cpuimx51_init,
303 .timer = &mxc_timer, 304 .timer = &mxc_timer,
305 .init_machine = eukrea_cpuimx51_init,
304MACHINE_END 306MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index ad931895d8b..29b180823bf 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -42,6 +42,7 @@
42 42
43#include "devices-imx51.h" 43#include "devices-imx51.h"
44#include "devices.h" 44#include "devices.h"
45#include "cpu_op-mx51.h"
45 46
46#define USBH1_RST IMX_GPIO_NR(2, 28) 47#define USBH1_RST IMX_GPIO_NR(2, 28)
47#define ETH_RST IMX_GPIO_NR(2, 31) 48#define ETH_RST IMX_GPIO_NR(2, 31)
@@ -109,7 +110,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
109 110
110 /* Touchscreen */ 111 /* Touchscreen */
111 /* IRQ */ 112 /* IRQ */
112 _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | 113 _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
113 PAD_CTL_PKE | PAD_CTL_SRE_FAST | 114 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
114 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS), 115 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
115}; 116};
@@ -118,15 +119,9 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
118 .flags = IMXUART_HAVE_RTSCTS, 119 .flags = IMXUART_HAVE_RTSCTS,
119}; 120};
120 121
121static int ts_get_pendown_state(void)
122{
123 return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
124}
125
126static struct tsc2007_platform_data tsc2007_info = { 122static struct tsc2007_platform_data tsc2007_info = {
127 .model = 2007, 123 .model = 2007,
128 .x_plate_ohms = 180, 124 .x_plate_ohms = 180,
129 .get_pendown_state = ts_get_pendown_state,
130}; 125};
131 126
132static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = { 127static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
@@ -167,7 +162,10 @@ static int initialize_otg_port(struct platform_device *pdev)
167 v |= MX51_USB_PLL_DIV_19_2_MHZ; 162 v |= MX51_USB_PLL_DIV_19_2_MHZ;
168 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); 163 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
169 iounmap(usb_base); 164 iounmap(usb_base);
170 return 0; 165
166 mdelay(10);
167
168 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
171} 169}
172 170
173static int initialize_usbh1_port(struct platform_device *pdev) 171static int initialize_usbh1_port(struct platform_device *pdev)
@@ -186,13 +184,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
186 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, 184 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
187 usbother_base + MX51_USB_CTRL_1_OFFSET); 185 usbother_base + MX51_USB_CTRL_1_OFFSET);
188 iounmap(usb_base); 186 iounmap(usb_base);
189 return 0; 187
188 mdelay(10);
189
190 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
191 MXC_EHCI_ITC_NO_THRESHOLD);
190} 192}
191 193
192static struct mxc_usbh_platform_data dr_utmi_config = { 194static struct mxc_usbh_platform_data dr_utmi_config = {
193 .init = initialize_otg_port, 195 .init = initialize_otg_port,
194 .portsc = MXC_EHCI_UTMI_16BIT, 196 .portsc = MXC_EHCI_UTMI_16BIT,
195 .flags = MXC_EHCI_INTERNAL_PHY,
196}; 197};
197 198
198static struct fsl_usb2_platform_data usb_pdata = { 199static struct fsl_usb2_platform_data usb_pdata = {
@@ -203,7 +204,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
203static struct mxc_usbh_platform_data usbh1_config = { 204static struct mxc_usbh_platform_data usbh1_config = {
204 .init = initialize_usbh1_port, 205 .init = initialize_usbh1_port,
205 .portsc = MXC_EHCI_MODE_ULPI, 206 .portsc = MXC_EHCI_MODE_ULPI,
206 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
207}; 207};
208 208
209static int otg_mode_host; 209static int otg_mode_host;
@@ -242,7 +242,7 @@ static struct mcp251x_platform_data mcp251x_info = {
242static struct spi_board_info cpuimx51sd_spi_device[] = { 242static struct spi_board_info cpuimx51sd_spi_device[] = {
243 { 243 {
244 .modalias = "mcp2515", 244 .modalias = "mcp2515",
245 .max_speed_hz = 6500000, 245 .max_speed_hz = 10000000,
246 .bus_num = 0, 246 .bus_num = 0,
247 .mode = SPI_MODE_0, 247 .mode = SPI_MODE_0,
248 .chip_select = 0, 248 .chip_select = 0,
@@ -269,6 +269,10 @@ static void __init eukrea_cpuimx51sd_init(void)
269 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads, 269 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
270 ARRAY_SIZE(eukrea_cpuimx51sd_pads)); 270 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
271 271
272#if defined(CONFIG_CPU_FREQ_IMX)
273 get_cpu_op = mx51_get_cpu_op;
274#endif
275
272 imx51_add_imx_uart(0, &uart_pdata); 276 imx51_add_imx_uart(0, &uart_pdata);
273 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); 277 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
274 278
@@ -329,7 +333,8 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
329 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 333 /* Maintainer: Eric Bénard <eric@eukrea.com> */
330 .boot_params = MX51_PHYS_OFFSET + 0x100, 334 .boot_params = MX51_PHYS_OFFSET + 0x100,
331 .map_io = mx51_map_io, 335 .map_io = mx51_map_io,
336 .init_early = imx51_init_early,
332 .init_irq = mx51_init_irq, 337 .init_irq = mx51_init_irq,
333 .init_machine = eukrea_cpuimx51sd_init,
334 .timer = &mxc_timer, 338 .timer = &mxc_timer,
339 .init_machine = eukrea_cpuimx51sd_init,
335MACHINE_END 340MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index fd32e4c450e..dedf7f2d6d0 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -35,7 +35,10 @@
35#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
36#include <asm/mach/time.h> 36#include <asm/mach/time.h>
37 37
38#include "devices-mx50.h" 38#include "devices-imx50.h"
39
40#define FEC_EN IMX_GPIO_NR(6, 23)
41#define FEC_RESET_B IMX_GPIO_NR(4, 12)
39 42
40static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = { 43static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
41 /* SD1 */ 44 /* SD1 */
@@ -102,7 +105,7 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
102 MX50_PAD_I2C3_SCL__USBOTG_OC, 105 MX50_PAD_I2C3_SCL__USBOTG_OC,
103 106
104 MX50_PAD_SSI_RXC__FEC_MDIO, 107 MX50_PAD_SSI_RXC__FEC_MDIO,
105 MX50_PAD_SSI_RXC__FEC_MDIO, 108 MX50_PAD_SSI_RXFS__FEC_MDC,
106 MX50_PAD_DISP_D0__FEC_TXCLK, 109 MX50_PAD_DISP_D0__FEC_TXCLK,
107 MX50_PAD_DISP_D1__FEC_RX_ER, 110 MX50_PAD_DISP_D1__FEC_RX_ER,
108 MX50_PAD_DISP_D2__FEC_RX_DV, 111 MX50_PAD_DISP_D2__FEC_RX_DV,
@@ -111,7 +114,6 @@ static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
111 MX50_PAD_DISP_D5__FEC_TX_EN, 114 MX50_PAD_DISP_D5__FEC_TX_EN,
112 MX50_PAD_DISP_D6__FEC_TXD1, 115 MX50_PAD_DISP_D6__FEC_TXD1,
113 MX50_PAD_DISP_D7__FEC_TXD0, 116 MX50_PAD_DISP_D7__FEC_TXD0,
114 MX50_PAD_SSI_RXFS__FEC_MDC,
115 MX50_PAD_I2C3_SDA__GPIO_6_23, 117 MX50_PAD_I2C3_SDA__GPIO_6_23,
116 MX50_PAD_ECSPI1_SCLK__GPIO_4_12, 118 MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
117 119
@@ -168,6 +170,24 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
168 .flags = IMXUART_HAVE_RTSCTS, 170 .flags = IMXUART_HAVE_RTSCTS,
169}; 171};
170 172
173static const struct fec_platform_data fec_data __initconst = {
174 .phy = PHY_INTERFACE_MODE_RMII,
175};
176
177static inline void mx50_rdp_fec_reset(void)
178{
179 gpio_request(FEC_EN, "fec-en");
180 gpio_direction_output(FEC_EN, 0);
181 gpio_request(FEC_RESET_B, "fec-reset_b");
182 gpio_direction_output(FEC_RESET_B, 0);
183 msleep(1);
184 gpio_set_value(FEC_RESET_B, 1);
185}
186
187static const struct imxi2c_platform_data i2c_data __initconst = {
188 .bitrate = 100000,
189};
190
171/* 191/*
172 * Board specific initialization. 192 * Board specific initialization.
173 */ 193 */
@@ -178,6 +198,11 @@ static void __init mx50_rdp_board_init(void)
178 198
179 imx50_add_imx_uart(0, &uart_pdata); 199 imx50_add_imx_uart(0, &uart_pdata);
180 imx50_add_imx_uart(1, &uart_pdata); 200 imx50_add_imx_uart(1, &uart_pdata);
201 mx50_rdp_fec_reset();
202 imx50_add_fec(&fec_data);
203 imx50_add_imx_i2c(0, &i2c_data);
204 imx50_add_imx_i2c(1, &i2c_data);
205 imx50_add_imx_i2c(2, &i2c_data);
181} 206}
182 207
183static void __init mx50_rdp_timer_init(void) 208static void __init mx50_rdp_timer_init(void)
@@ -191,7 +216,8 @@ static struct sys_timer mx50_rdp_timer = {
191 216
192MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") 217MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
193 .map_io = mx50_map_io, 218 .map_io = mx50_map_io,
219 .init_early = imx50_init_early,
194 .init_irq = mx50_init_irq, 220 .init_irq = mx50_init_irq,
195 .init_machine = mx50_rdp_board_init,
196 .timer = &mx50_rdp_timer, 221 .timer = &mx50_rdp_timer,
222 .init_machine = mx50_rdp_board_init,
197MACHINE_END 223MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 49d64484237..63dfbeafbc1 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -71,24 +71,10 @@ static iomux_v3_cfg_t mx51_3ds_pads[] = {
71}; 71};
72 72
73/* Serial ports */ 73/* Serial ports */
74#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
75static const struct imxuart_platform_data uart_pdata __initconst = { 74static const struct imxuart_platform_data uart_pdata __initconst = {
76 .flags = IMXUART_HAVE_RTSCTS, 75 .flags = IMXUART_HAVE_RTSCTS,
77}; 76};
78 77
79static inline void mxc_init_imx_uart(void)
80{
81 imx51_add_imx_uart(0, &uart_pdata);
82 imx51_add_imx_uart(1, &uart_pdata);
83 imx51_add_imx_uart(2, &uart_pdata);
84}
85#else /* !SERIAL_IMX */
86static inline void mxc_init_imx_uart(void)
87{
88}
89#endif /* SERIAL_IMX */
90
91#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
92static int mx51_3ds_board_keymap[] = { 78static int mx51_3ds_board_keymap[] = {
93 KEY(0, 0, KEY_1), 79 KEY(0, 0, KEY_1),
94 KEY(0, 1, KEY_2), 80 KEY(0, 1, KEY_2),
@@ -124,16 +110,6 @@ static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
124 .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap), 110 .keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap),
125}; 111};
126 112
127static void mxc_init_keypad(void)
128{
129 imx51_add_imx_keypad(&mx51_3ds_map_data);
130}
131#else
132static inline void mxc_init_keypad(void)
133{
134}
135#endif
136
137static int mx51_3ds_spi2_cs[] = { 113static int mx51_3ds_spi2_cs[] = {
138 MXC_SPI_CS(0), 114 MXC_SPI_CS(0),
139 MX51_3DS_ECSPI2_CS, 115 MX51_3DS_ECSPI2_CS,
@@ -157,11 +133,14 @@ static struct spi_board_info mx51_3ds_spi_nor_device[] = {
157/* 133/*
158 * Board specific initialization. 134 * Board specific initialization.
159 */ 135 */
160static void __init mxc_board_init(void) 136static void __init mx51_3ds_init(void)
161{ 137{
162 mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads, 138 mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
163 ARRAY_SIZE(mx51_3ds_pads)); 139 ARRAY_SIZE(mx51_3ds_pads));
164 mxc_init_imx_uart(); 140
141 imx51_add_imx_uart(0, &uart_pdata);
142 imx51_add_imx_uart(1, &uart_pdata);
143 imx51_add_imx_uart(2, &uart_pdata);
165 144
166 imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata); 145 imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
167 spi_register_board_info(mx51_3ds_spi_nor_device, 146 spi_register_board_info(mx51_3ds_spi_nor_device,
@@ -172,7 +151,8 @@ static void __init mxc_board_init(void)
172 "devices on the board are unusable.\n"); 151 "devices on the board are unusable.\n");
173 152
174 imx51_add_sdhci_esdhc_imx(0, NULL); 153 imx51_add_sdhci_esdhc_imx(0, NULL);
175 mxc_init_keypad(); 154 imx51_add_imx_keypad(&mx51_3ds_map_data);
155 imx51_add_imx2_wdt(0, NULL);
176} 156}
177 157
178static void __init mx51_3ds_timer_init(void) 158static void __init mx51_3ds_timer_init(void)
@@ -180,15 +160,16 @@ static void __init mx51_3ds_timer_init(void)
180 mx51_clocks_init(32768, 24000000, 22579200, 0); 160 mx51_clocks_init(32768, 24000000, 22579200, 0);
181} 161}
182 162
183static struct sys_timer mxc_timer = { 163static struct sys_timer mx51_3ds_timer = {
184 .init = mx51_3ds_timer_init, 164 .init = mx51_3ds_timer_init,
185}; 165};
186 166
187MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") 167MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
188 /* Maintainer: Freescale Semiconductor, Inc. */ 168 /* Maintainer: Freescale Semiconductor, Inc. */
189 .boot_params = MX51_PHYS_OFFSET + 0x100, 169 .boot_params = MX51_PHYS_OFFSET + 0x100,
190 .map_io = mx51_map_io, 170 .map_io = mx51_map_io,
171 .init_early = imx51_init_early,
191 .init_irq = mx51_init_irq, 172 .init_irq = mx51_init_irq,
192 .init_machine = mxc_board_init, 173 .timer = &mx51_3ds_timer,
193 .timer = &mxc_timer, 174 .init_machine = mx51_3ds_init,
194MACHINE_END 175MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 1d231e84107..b2ecd194e76 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -161,23 +161,10 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
161}; 161};
162 162
163/* Serial ports */ 163/* Serial ports */
164#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
165static const struct imxuart_platform_data uart_pdata __initconst = { 164static const struct imxuart_platform_data uart_pdata __initconst = {
166 .flags = IMXUART_HAVE_RTSCTS, 165 .flags = IMXUART_HAVE_RTSCTS,
167}; 166};
168 167
169static inline void mxc_init_imx_uart(void)
170{
171 imx51_add_imx_uart(0, &uart_pdata);
172 imx51_add_imx_uart(1, &uart_pdata);
173 imx51_add_imx_uart(2, &uart_pdata);
174}
175#else /* !SERIAL_IMX */
176static inline void mxc_init_imx_uart(void)
177{
178}
179#endif /* SERIAL_IMX */
180
181static const struct imxi2c_platform_data babbage_i2c_data __initconst = { 168static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
182 .bitrate = 100000, 169 .bitrate = 100000,
183}; 170};
@@ -272,7 +259,10 @@ static int initialize_otg_port(struct platform_device *pdev)
272 v |= MX51_USB_PLL_DIV_19_2_MHZ; 259 v |= MX51_USB_PLL_DIV_19_2_MHZ;
273 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); 260 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
274 iounmap(usb_base); 261 iounmap(usb_base);
275 return 0; 262
263 mdelay(10);
264
265 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
276} 266}
277 267
278static int initialize_usbh1_port(struct platform_device *pdev) 268static int initialize_usbh1_port(struct platform_device *pdev)
@@ -290,13 +280,16 @@ static int initialize_usbh1_port(struct platform_device *pdev)
290 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); 280 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
291 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); 281 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
292 iounmap(usb_base); 282 iounmap(usb_base);
293 return 0; 283
284 mdelay(10);
285
286 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
287 MXC_EHCI_ITC_NO_THRESHOLD);
294} 288}
295 289
296static struct mxc_usbh_platform_data dr_utmi_config = { 290static struct mxc_usbh_platform_data dr_utmi_config = {
297 .init = initialize_otg_port, 291 .init = initialize_otg_port,
298 .portsc = MXC_EHCI_UTMI_16BIT, 292 .portsc = MXC_EHCI_UTMI_16BIT,
299 .flags = MXC_EHCI_INTERNAL_PHY,
300}; 293};
301 294
302static struct fsl_usb2_platform_data usb_pdata = { 295static struct fsl_usb2_platform_data usb_pdata = {
@@ -307,7 +300,6 @@ static struct fsl_usb2_platform_data usb_pdata = {
307static struct mxc_usbh_platform_data usbh1_config = { 300static struct mxc_usbh_platform_data usbh1_config = {
308 .init = initialize_usbh1_port, 301 .init = initialize_usbh1_port,
309 .portsc = MXC_EHCI_MODE_ULPI, 302 .portsc = MXC_EHCI_MODE_ULPI,
310 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
311}; 303};
312 304
313static int otg_mode_host; 305static int otg_mode_host;
@@ -349,7 +341,7 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
349/* 341/*
350 * Board specific initialization. 342 * Board specific initialization.
351 */ 343 */
352static void __init mxc_board_init(void) 344static void __init mx51_babbage_init(void)
353{ 345{
354 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; 346 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
355 iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 | 347 iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
@@ -360,7 +352,11 @@ static void __init mxc_board_init(void)
360#endif 352#endif
361 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, 353 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
362 ARRAY_SIZE(mx51babbage_pads)); 354 ARRAY_SIZE(mx51babbage_pads));
363 mxc_init_imx_uart(); 355
356 imx51_add_imx_uart(0, &uart_pdata);
357 imx51_add_imx_uart(1, &uart_pdata);
358 imx51_add_imx_uart(2, &uart_pdata);
359
364 babbage_fec_reset(); 360 babbage_fec_reset();
365 imx51_add_fec(NULL); 361 imx51_add_fec(NULL);
366 362
@@ -399,15 +395,16 @@ static void __init mx51_babbage_timer_init(void)
399 mx51_clocks_init(32768, 24000000, 22579200, 0); 395 mx51_clocks_init(32768, 24000000, 22579200, 0);
400} 396}
401 397
402static struct sys_timer mxc_timer = { 398static struct sys_timer mx51_babbage_timer = {
403 .init = mx51_babbage_timer_init, 399 .init = mx51_babbage_timer_init,
404}; 400};
405 401
406MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") 402MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
407 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */ 403 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
408 .boot_params = MX51_PHYS_OFFSET + 0x100, 404 .boot_params = MX51_PHYS_OFFSET + 0x100,
409 .map_io = mx51_map_io, 405 .map_io = mx51_map_io,
406 .init_early = imx51_init_early,
410 .init_irq = mx51_init_irq, 407 .init_irq = mx51_init_irq,
411 .init_machine = mxc_board_init, 408 .timer = &mx51_babbage_timer,
412 .timer = &mxc_timer, 409 .init_machine = mx51_babbage_init,
413MACHINE_END 410MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index b7946f8e8d4..acab1911cb3 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -25,6 +25,9 @@
25#include <linux/fsl_devices.h> 25#include <linux/fsl_devices.h>
26#include <linux/spi/flash.h> 26#include <linux/spi/flash.h>
27#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
28#include <linux/mfd/mc13892.h>
29#include <linux/regulator/machine.h>
30#include <linux/regulator/consumer.h>
28 31
29#include <mach/common.h> 32#include <mach/common.h>
30#include <mach/hardware.h> 33#include <mach/hardware.h>
@@ -40,8 +43,7 @@
40 43
41#include "devices-imx51.h" 44#include "devices-imx51.h"
42#include "devices.h" 45#include "devices.h"
43 46#include "efika.h"
44#define MX51_USB_PLL_DIV_24_MHZ 0x01
45 47
46#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16) 48#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
47#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17) 49#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
@@ -53,13 +55,14 @@
53 55
54#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31) 56#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
55 57
56#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
57#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
58
59/* board 1.1 doesn't have same reset gpio */ 58/* board 1.1 doesn't have same reset gpio */
60#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2) 59#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
61#define EFIKAMX_RESET IMX_GPIO_NR(1, 4) 60#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
62 61
62#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13)
63
64#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
65
63/* the pci ids pin have pull up. they're driven low according to board id */ 66/* the pci ids pin have pull up. they're driven low according to board id */
64#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) 67#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
65#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP) 68#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
@@ -67,38 +70,11 @@
67#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE) 70#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
68 71
69static iomux_v3_cfg_t mx51efikamx_pads[] = { 72static iomux_v3_cfg_t mx51efikamx_pads[] = {
70 /* UART1 */
71 MX51_PAD_UART1_RXD__UART1_RXD,
72 MX51_PAD_UART1_TXD__UART1_TXD,
73 MX51_PAD_UART1_RTS__UART1_RTS,
74 MX51_PAD_UART1_CTS__UART1_CTS,
75 /* board id */ 73 /* board id */
76 MX51_PAD_PCBID0, 74 MX51_PAD_PCBID0,
77 MX51_PAD_PCBID1, 75 MX51_PAD_PCBID1,
78 MX51_PAD_PCBID2, 76 MX51_PAD_PCBID2,
79 77
80 /* SD 1 */
81 MX51_PAD_SD1_CMD__SD1_CMD,
82 MX51_PAD_SD1_CLK__SD1_CLK,
83 MX51_PAD_SD1_DATA0__SD1_DATA0,
84 MX51_PAD_SD1_DATA1__SD1_DATA1,
85 MX51_PAD_SD1_DATA2__SD1_DATA2,
86 MX51_PAD_SD1_DATA3__SD1_DATA3,
87
88 /* SD 2 */
89 MX51_PAD_SD2_CMD__SD2_CMD,
90 MX51_PAD_SD2_CLK__SD2_CLK,
91 MX51_PAD_SD2_DATA0__SD2_DATA0,
92 MX51_PAD_SD2_DATA1__SD2_DATA1,
93 MX51_PAD_SD2_DATA2__SD2_DATA2,
94 MX51_PAD_SD2_DATA3__SD2_DATA3,
95
96 /* SD/MMC WP/CD */
97 MX51_PAD_GPIO1_0__SD1_CD,
98 MX51_PAD_GPIO1_1__SD1_WP,
99 MX51_PAD_GPIO1_7__SD2_WP,
100 MX51_PAD_GPIO1_8__SD2_CD,
101
102 /* leds */ 78 /* leds */
103 MX51_PAD_CSI1_D9__GPIO3_13, 79 MX51_PAD_CSI1_D9__GPIO3_13,
104 MX51_PAD_CSI1_VSYNC__GPIO3_14, 80 MX51_PAD_CSI1_VSYNC__GPIO3_14,
@@ -107,64 +83,12 @@ static iomux_v3_cfg_t mx51efikamx_pads[] = {
107 /* power key */ 83 /* power key */
108 MX51_PAD_PWRKEY, 84 MX51_PAD_PWRKEY,
109 85
110 /* spi */
111 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
112 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
113 MX51_PAD_CSPI1_SS0__GPIO4_24,
114 MX51_PAD_CSPI1_SS1__GPIO4_25,
115 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
116 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
117
118 /* reset */ 86 /* reset */
119 MX51_PAD_DI1_PIN13__GPIO3_2, 87 MX51_PAD_DI1_PIN13__GPIO3_2,
120 MX51_PAD_GPIO1_4__GPIO1_4, 88 MX51_PAD_GPIO1_4__GPIO1_4,
121};
122 89
123/* Serial ports */ 90 /* power off */
124#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) 91 MX51_PAD_CSI2_VSYNC__GPIO4_13,
125static const struct imxuart_platform_data uart_pdata = {
126 .flags = IMXUART_HAVE_RTSCTS,
127};
128
129static inline void mxc_init_imx_uart(void)
130{
131 imx51_add_imx_uart(0, &uart_pdata);
132 imx51_add_imx_uart(1, &uart_pdata);
133 imx51_add_imx_uart(2, &uart_pdata);
134}
135#else /* !SERIAL_IMX */
136static inline void mxc_init_imx_uart(void)
137{
138}
139#endif /* SERIAL_IMX */
140
141/* This function is board specific as the bit mask for the plldiv will also
142 * be different for other Freescale SoCs, thus a common bitmask is not
143 * possible and cannot get place in /plat-mxc/ehci.c.
144 */
145static int initialize_otg_port(struct platform_device *pdev)
146{
147 u32 v;
148 void __iomem *usb_base;
149 void __iomem *usbother_base;
150 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
151 if (!usb_base)
152 return -ENOMEM;
153 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
154
155 /* Set the PHY clock to 19.2MHz */
156 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
157 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
158 v |= MX51_USB_PLL_DIV_24_MHZ;
159 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
160 iounmap(usb_base);
161 return 0;
162}
163
164static struct mxc_usbh_platform_data dr_utmi_config = {
165 .init = initialize_otg_port,
166 .portsc = MXC_EHCI_UTMI_16BIT,
167 .flags = MXC_EHCI_INTERNAL_PHY,
168}; 92};
169 93
170/* PCBID2 PCBID1 PCBID0 STATE 94/* PCBID2 PCBID1 PCBID0 STATE
@@ -265,47 +189,6 @@ static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initcon
265 .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey), 189 .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
266}; 190};
267 191
268static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = {
269 {
270 .name = "u-boot",
271 .offset = 0,
272 .size = SZ_256K,
273 },
274 {
275 .name = "config",
276 .offset = MTDPART_OFS_APPEND,
277 .size = SZ_64K,
278 },
279};
280
281static struct flash_platform_data mx51_efikamx_spi_flash_data = {
282 .name = "spi_flash",
283 .parts = mx51_efikamx_spi_nor_partitions,
284 .nr_parts = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions),
285 .type = "sst25vf032b",
286};
287
288static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = {
289 {
290 .modalias = "m25p80",
291 .max_speed_hz = 25000000,
292 .bus_num = 0,
293 .chip_select = 1,
294 .platform_data = &mx51_efikamx_spi_flash_data,
295 .irq = -1,
296 },
297};
298
299static int mx51_efikamx_spi_cs[] = {
300 EFIKAMX_SPI_CS0,
301 EFIKAMX_SPI_CS1,
302};
303
304static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = {
305 .chipselect = mx51_efikamx_spi_cs,
306 .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs),
307};
308
309void mx51_efikamx_reset(void) 192void mx51_efikamx_reset(void)
310{ 193{
311 if (system_rev == 0x11) 194 if (system_rev == 0x11)
@@ -314,14 +197,53 @@ void mx51_efikamx_reset(void)
314 gpio_direction_output(EFIKAMX_RESET, 0); 197 gpio_direction_output(EFIKAMX_RESET, 0);
315} 198}
316 199
317static void __init mxc_board_init(void) 200static struct regulator *pwgt1, *pwgt2, *coincell;
201
202static void mx51_efikamx_power_off(void)
203{
204 if (!IS_ERR(coincell))
205 regulator_disable(coincell);
206
207 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
208 regulator_disable(pwgt2);
209 regulator_disable(pwgt1);
210 }
211 gpio_direction_output(EFIKAMX_POWEROFF, 1);
212}
213
214static int __init mx51_efikamx_power_init(void)
215{
216 if (machine_is_mx51_efikamx()) {
217 pwgt1 = regulator_get(NULL, "pwgt1");
218 pwgt2 = regulator_get(NULL, "pwgt2");
219 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
220 regulator_enable(pwgt1);
221 regulator_enable(pwgt2);
222 }
223 gpio_request(EFIKAMX_POWEROFF, "poweroff");
224 pm_power_off = mx51_efikamx_power_off;
225
226 /* enable coincell charger. maybe need a small power driver ? */
227 coincell = regulator_get(NULL, "coincell");
228 if (!IS_ERR(coincell)) {
229 regulator_set_voltage(coincell, 3000000, 3000000);
230 regulator_enable(coincell);
231 }
232
233 regulator_has_full_constraints();
234 }
235
236 return 0;
237}
238late_initcall(mx51_efikamx_power_init);
239
240static void __init mx51_efikamx_init(void)
318{ 241{
319 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, 242 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
320 ARRAY_SIZE(mx51efikamx_pads)); 243 ARRAY_SIZE(mx51efikamx_pads));
244 efika_board_common_init();
245
321 mx51_efikamx_board_id(); 246 mx51_efikamx_board_id();
322 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
323 mxc_init_imx_uart();
324 imx51_add_sdhci_esdhc_imx(0, NULL);
325 247
326 /* on < 1.2 boards both SD controllers are used */ 248 /* on < 1.2 boards both SD controllers are used */
327 if (system_rev < 0x12) { 249 if (system_rev < 0x12) {
@@ -332,10 +254,6 @@ static void __init mxc_board_init(void)
332 platform_device_register(&mx51_efikamx_leds_device); 254 platform_device_register(&mx51_efikamx_leds_device);
333 imx51_add_gpio_keys(&mx51_efikamx_powerkey_data); 255 imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
334 256
335 spi_register_board_info(mx51_efikamx_spi_board_info,
336 ARRAY_SIZE(mx51_efikamx_spi_board_info));
337 imx51_add_ecspi(0, &mx51_efikamx_spi_pdata);
338
339 if (system_rev == 0x11) { 257 if (system_rev == 0x11) {
340 gpio_request(EFIKAMX_RESET1_1, "reset"); 258 gpio_request(EFIKAMX_RESET1_1, "reset");
341 gpio_direction_output(EFIKAMX_RESET1_1, 1); 259 gpio_direction_output(EFIKAMX_RESET1_1, 1);
@@ -343,6 +261,20 @@ static void __init mxc_board_init(void)
343 gpio_request(EFIKAMX_RESET, "reset"); 261 gpio_request(EFIKAMX_RESET, "reset");
344 gpio_direction_output(EFIKAMX_RESET, 1); 262 gpio_direction_output(EFIKAMX_RESET, 1);
345 } 263 }
264
265 /*
266 * enable wifi by default only on mx
267 * sb and mx have same wlan pin but the value to enable it are
268 * different :/
269 */
270 gpio_request(EFIKA_WLAN_EN, "wlan_en");
271 gpio_direction_output(EFIKA_WLAN_EN, 0);
272 msleep(10);
273
274 gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
275 gpio_direction_output(EFIKA_WLAN_RESET, 0);
276 msleep(10);
277 gpio_set_value(EFIKA_WLAN_RESET, 1);
346} 278}
347 279
348static void __init mx51_efikamx_timer_init(void) 280static void __init mx51_efikamx_timer_init(void)
@@ -350,15 +282,16 @@ static void __init mx51_efikamx_timer_init(void)
350 mx51_clocks_init(32768, 24000000, 22579200, 24576000); 282 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
351} 283}
352 284
353static struct sys_timer mxc_timer = { 285static struct sys_timer mx51_efikamx_timer = {
354 .init = mx51_efikamx_timer_init, 286 .init = mx51_efikamx_timer_init,
355}; 287};
356 288
357MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") 289MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
358 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */ 290 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
359 .boot_params = MX51_PHYS_OFFSET + 0x100, 291 .boot_params = MX51_PHYS_OFFSET + 0x100,
360 .map_io = mx51_map_io, 292 .map_io = mx51_map_io,
293 .init_early = imx51_init_early,
361 .init_irq = mx51_init_irq, 294 .init_irq = mx51_init_irq,
362 .init_machine = mxc_board_init, 295 .timer = &mx51_efikamx_timer,
363 .timer = &mxc_timer, 296 .init_machine = mx51_efikamx_init,
364MACHINE_END 297MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
new file mode 100644
index 00000000000..db04ce8462d
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -0,0 +1,283 @@
1/*
2 * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/fsl_devices.h>
26#include <linux/spi/flash.h>
27#include <linux/spi/spi.h>
28#include <linux/mfd/mc13892.h>
29#include <linux/regulator/machine.h>
30#include <linux/regulator/consumer.h>
31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
33#include <mach/ulpi.h>
34
35#include <mach/common.h>
36#include <mach/hardware.h>
37#include <mach/iomux-mx51.h>
38#include <mach/i2c.h>
39#include <mach/mxc_ehci.h>
40
41#include <asm/irq.h>
42#include <asm/setup.h>
43#include <asm/mach-types.h>
44#include <asm/mach/arch.h>
45#include <asm/mach/time.h>
46
47#include "devices-imx51.h"
48#include "devices.h"
49#include "efika.h"
50
51#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20)
52#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3)
53#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25)
54#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28)
55#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29)
56#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31)
57#define EFIKASB_LID IMX_GPIO_NR(3, 14)
58#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13)
59#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1)
60
61#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
62
63static iomux_v3_cfg_t mx51efikasb_pads[] = {
64 /* USB HOST2 */
65 MX51_PAD_EIM_D16__USBH2_DATA0,
66 MX51_PAD_EIM_D17__USBH2_DATA1,
67 MX51_PAD_EIM_D18__USBH2_DATA2,
68 MX51_PAD_EIM_D19__USBH2_DATA3,
69 MX51_PAD_EIM_D20__USBH2_DATA4,
70 MX51_PAD_EIM_D21__USBH2_DATA5,
71 MX51_PAD_EIM_D22__USBH2_DATA6,
72 MX51_PAD_EIM_D23__USBH2_DATA7,
73 MX51_PAD_EIM_A24__USBH2_CLK,
74 MX51_PAD_EIM_A25__USBH2_DIR,
75 MX51_PAD_EIM_A26__USBH2_STP,
76 MX51_PAD_EIM_A27__USBH2_NXT,
77
78 /* leds */
79 MX51_PAD_EIM_CS0__GPIO2_25,
80 MX51_PAD_GPIO1_3__GPIO1_3,
81
82 /* pcb id */
83 MX51_PAD_EIM_CS3__GPIO2_28,
84 MX51_PAD_EIM_CS4__GPIO2_29,
85
86 /* lid */
87 MX51_PAD_CSI1_VSYNC__GPIO3_14,
88
89 /* power key*/
90 MX51_PAD_PWRKEY,
91
92 /* wifi/bt button */
93 MX51_PAD_DI1_PIN12__GPIO3_1,
94
95 /* power off */
96 MX51_PAD_CSI2_VSYNC__GPIO4_13,
97
98 /* wdog reset */
99 MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
100
101 /* BT */
102 MX51_PAD_EIM_A17__GPIO2_11,
103};
104
105static int initialize_usbh2_port(struct platform_device *pdev)
106{
107 iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
108 iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
109
110 mxc_iomux_v3_setup_pad(usbh2gpio);
111 gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
112 gpio_direction_output(EFIKASB_USBH2_STP, 0);
113 msleep(1);
114 gpio_set_value(EFIKASB_USBH2_STP, 1);
115 msleep(1);
116
117 gpio_free(EFIKASB_USBH2_STP);
118 mxc_iomux_v3_setup_pad(usbh2stp);
119
120 mdelay(10);
121
122 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
123}
124
125static struct mxc_usbh_platform_data usbh2_config = {
126 .init = initialize_usbh2_port,
127 .portsc = MXC_EHCI_MODE_ULPI,
128};
129
130static void __init mx51_efikasb_usb(void)
131{
132 usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
133 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
134 if (usbh2_config.otg)
135 mxc_register_device(&mxc_usbh2_device, &usbh2_config);
136}
137
138static struct gpio_led mx51_efikasb_leds[] = {
139 {
140 .name = "efikasb:green",
141 .default_trigger = "default-on",
142 .gpio = EFIKASB_GREEN_LED,
143 .active_low = 1,
144 },
145 {
146 .name = "efikasb:white",
147 .default_trigger = "caps",
148 .gpio = EFIKASB_WHITE_LED,
149 },
150};
151
152static struct gpio_led_platform_data mx51_efikasb_leds_data = {
153 .leds = mx51_efikasb_leds,
154 .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
155};
156
157static struct platform_device mx51_efikasb_leds_device = {
158 .name = "leds-gpio",
159 .id = -1,
160 .dev = {
161 .platform_data = &mx51_efikasb_leds_data,
162 },
163};
164
165static struct gpio_keys_button mx51_efikasb_keys[] = {
166 {
167 .code = KEY_POWER,
168 .gpio = EFIKASB_PWRKEY,
169 .type = EV_PWR,
170 .desc = "Power Button",
171 .wakeup = 1,
172 .debounce_interval = 10, /* ms */
173 },
174 {
175 .code = SW_LID,
176 .gpio = EFIKASB_LID,
177 .type = EV_SW,
178 .desc = "Lid Switch",
179 },
180 {
181 /* SW_RFKILLALL vs KEY_RFKILL ? */
182 .code = SW_RFKILL_ALL,
183 .gpio = EFIKASB_RFKILL,
184 .type = EV_SW,
185 .desc = "rfkill",
186 },
187};
188
189static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
190 .buttons = mx51_efikasb_keys,
191 .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
192};
193
194static struct regulator *pwgt1, *pwgt2;
195
196static void mx51_efikasb_power_off(void)
197{
198 gpio_set_value(EFIKA_USB_PHY_RESET, 0);
199
200 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
201 regulator_disable(pwgt2);
202 regulator_disable(pwgt1);
203 }
204 gpio_direction_output(EFIKASB_POWEROFF, 1);
205}
206
207static int __init mx51_efikasb_power_init(void)
208{
209 if (machine_is_mx51_efikasb()) {
210 pwgt1 = regulator_get(NULL, "pwgt1");
211 pwgt2 = regulator_get(NULL, "pwgt2");
212 if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
213 regulator_enable(pwgt1);
214 regulator_enable(pwgt2);
215 }
216 gpio_request(EFIKASB_POWEROFF, "poweroff");
217 pm_power_off = mx51_efikasb_power_off;
218
219 regulator_has_full_constraints();
220 }
221
222 return 0;
223}
224late_initcall(mx51_efikasb_power_init);
225
226/* 01 R1.3 board
227 10 R2.0 board */
228static void __init mx51_efikasb_board_id(void)
229{
230 int id;
231
232 gpio_request(EFIKASB_PCBID0, "pcb id0");
233 gpio_direction_input(EFIKASB_PCBID0);
234 gpio_request(EFIKASB_PCBID1, "pcb id1");
235 gpio_direction_input(EFIKASB_PCBID1);
236
237 id = gpio_get_value(EFIKASB_PCBID0);
238 id |= gpio_get_value(EFIKASB_PCBID1) << 1;
239
240 switch (id) {
241 default:
242 break;
243 case 1:
244 system_rev = 0x13;
245 break;
246 case 2:
247 system_rev = 0x20;
248 break;
249 }
250}
251
252static void __init efikasb_board_init(void)
253{
254 mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
255 ARRAY_SIZE(mx51efikasb_pads));
256 efika_board_common_init();
257
258 mx51_efikasb_board_id();
259 mx51_efikasb_usb();
260 imx51_add_sdhci_esdhc_imx(1, NULL);
261
262 platform_device_register(&mx51_efikasb_leds_device);
263 imx51_add_gpio_keys(&mx51_efikasb_keys_data);
264
265}
266
267static void __init mx51_efikasb_timer_init(void)
268{
269 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
270}
271
272static struct sys_timer mx51_efikasb_timer = {
273 .init = mx51_efikasb_timer_init,
274};
275
276MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
277 .boot_params = MX51_PHYS_OFFSET + 0x100,
278 .map_io = mx51_map_io,
279 .init_early = imx51_init_early,
280 .init_irq = mx51_init_irq,
281 .init_machine = efikasb_board_init,
282 .timer = &mx51_efikasb_timer,
283MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index caee04c0823..7b5735c5ea5 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org> 3 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
4 */ 4 */
5 5
@@ -42,28 +42,24 @@
42#include "devices-imx53.h" 42#include "devices-imx53.h"
43 43
44static iomux_v3_cfg_t mx53_evk_pads[] = { 44static iomux_v3_cfg_t mx53_evk_pads[] = {
45 MX53_PAD_CSI0_D10__UART1_TXD, 45 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
46 MX53_PAD_CSI0_D11__UART1_RXD, 46 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
47 MX53_PAD_ATA_DIOW__UART1_TXD,
48 MX53_PAD_ATA_DMACK__UART1_RXD,
49 47
50 MX53_PAD_ATA_BUFFER_EN__UART2_RXD, 48 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
51 MX53_PAD_ATA_DMARQ__UART2_TXD, 49 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
52 MX53_PAD_ATA_DIOR__UART2_RTS, 50 MX53_PAD_PATA_DIOR__UART2_RTS,
53 MX53_PAD_ATA_INTRQ__UART2_CTS, 51 MX53_PAD_PATA_INTRQ__UART2_CTS,
54 52
55 MX53_PAD_ATA_CS_0__UART3_TXD, 53 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
56 MX53_PAD_ATA_CS_1__UART3_RXD, 54 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
57 MX53_PAD_ATA_DA_1__UART3_CTS,
58 MX53_PAD_ATA_DA_2__UART3_RTS,
59 55
60 MX53_PAD_EIM_D16__CSPI1_SCLK, 56 MX53_PAD_EIM_D16__ECSPI1_SCLK,
61 MX53_PAD_EIM_D17__CSPI1_MISO, 57 MX53_PAD_EIM_D17__ECSPI1_MISO,
62 MX53_PAD_EIM_D18__CSPI1_MOSI, 58 MX53_PAD_EIM_D18__ECSPI1_MOSI,
63 59
64 /* ecspi chip select lines */ 60 /* ecspi chip select lines */
65 MX53_PAD_EIM_EB2__GPIO_2_30, 61 MX53_PAD_EIM_EB2__GPIO2_30,
66 MX53_PAD_EIM_D19__GPIO_3_19, 62 MX53_PAD_EIM_D19__GPIO3_19,
67}; 63};
68 64
69static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { 65static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
@@ -72,9 +68,9 @@ static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
72 68
73static inline void mx53_evk_init_uart(void) 69static inline void mx53_evk_init_uart(void)
74{ 70{
75 imx53_add_imx_uart(0, &mx53_evk_uart_pdata); 71 imx53_add_imx_uart(0, NULL);
76 imx53_add_imx_uart(1, &mx53_evk_uart_pdata); 72 imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
77 imx53_add_imx_uart(2, &mx53_evk_uart_pdata); 73 imx53_add_imx_uart(2, NULL);
78} 74}
79 75
80static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = { 76static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
@@ -139,6 +135,7 @@ static void __init mx53_evk_board_init(void)
139 spi_register_board_info(mx53_evk_spi_board_info, 135 spi_register_board_info(mx53_evk_spi_board_info,
140 ARRAY_SIZE(mx53_evk_spi_board_info)); 136 ARRAY_SIZE(mx53_evk_spi_board_info));
141 imx53_add_ecspi(0, &mx53_evk_spi_data); 137 imx53_add_ecspi(0, &mx53_evk_spi_data);
138 imx53_add_imx2_wdt(0, NULL);
142} 139}
143 140
144static void __init mx53_evk_timer_init(void) 141static void __init mx53_evk_timer_init(void)
@@ -152,7 +149,8 @@ static struct sys_timer mx53_evk_timer = {
152 149
153MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") 150MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
154 .map_io = mx53_map_io, 151 .map_io = mx53_map_io,
152 .init_early = imx53_init_early,
155 .init_irq = mx53_init_irq, 153 .init_irq = mx53_init_irq,
156 .init_machine = mx53_evk_board_init,
157 .timer = &mx53_evk_timer, 154 .timer = &mx53_evk_timer,
155 .init_machine = mx53_evk_board_init,
158MACHINE_END 156MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index d1348e04ace..0a18f8d23eb 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -39,33 +39,147 @@
39#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) 39#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
40 40
41static iomux_v3_cfg_t mx53_loco_pads[] = { 41static iomux_v3_cfg_t mx53_loco_pads[] = {
42 MX53_PAD_CSI0_D10__UART1_TXD, 42 /* FEC */
43 MX53_PAD_CSI0_D11__UART1_RXD, 43 MX53_PAD_FEC_MDC__FEC_MDC,
44 MX53_PAD_ATA_DIOW__UART1_TXD, 44 MX53_PAD_FEC_MDIO__FEC_MDIO,
45 MX53_PAD_ATA_DMACK__UART1_RXD, 45 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
46 46 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
47 MX53_PAD_ATA_BUFFER_EN__UART2_RXD, 47 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
48 MX53_PAD_ATA_DMARQ__UART2_TXD, 48 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
49 MX53_PAD_ATA_DIOR__UART2_RTS, 49 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
50 MX53_PAD_ATA_INTRQ__UART2_CTS, 50 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
51 51 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
52 MX53_PAD_ATA_CS_0__UART3_TXD, 52 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
53 MX53_PAD_ATA_CS_1__UART3_RXD, 53 /* FEC_nRST */
54 MX53_PAD_ATA_DA_1__UART3_CTS, 54 MX53_PAD_PATA_DA_0__GPIO7_6,
55 MX53_PAD_ATA_DA_2__UART3_RTS, 55 /* FEC_nINT */
56 MX53_PAD_PATA_DATA4__GPIO2_4,
57 /* AUDMUX5 */
58 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
59 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
60 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
61 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
62 /* I2C2 */
63 MX53_PAD_KEY_COL3__I2C2_SCL,
64 MX53_PAD_KEY_ROW3__I2C2_SDA,
65 /* SD1 */
66 MX53_PAD_SD1_CMD__ESDHC1_CMD,
67 MX53_PAD_SD1_CLK__ESDHC1_CLK,
68 MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
69 MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
70 MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
71 MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
72 /* SD3 */
73 MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
74 MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
75 MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
76 MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
77 MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
78 MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
79 MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
80 MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
81 MX53_PAD_PATA_IORDY__ESDHC3_CLK,
82 MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
83 /* SD3_CD */
84 MX53_PAD_EIM_DA11__GPIO3_11,
85 /* SD3_WP */
86 MX53_PAD_EIM_DA12__GPIO3_12,
87 /* VGA */
88 MX53_PAD_EIM_OE__IPU_DI1_PIN7,
89 MX53_PAD_EIM_RW__IPU_DI1_PIN8,
90 /* DISPLB */
91 MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
92 MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
93 MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
94 MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
95 /* DISP0_POWER_EN */
96 MX53_PAD_EIM_D24__GPIO3_24,
97 /* DISP0 DET INT */
98 MX53_PAD_EIM_D31__GPIO3_31,
99 /* LVDS */
100 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
101 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
102 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
103 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
104 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
105 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
106 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
107 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
108 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
109 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
110 /* I2C1 */
111 MX53_PAD_CSI0_DAT8__I2C1_SDA,
112 MX53_PAD_CSI0_DAT9__I2C1_SCL,
113 /* UART1 */
114 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
115 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
116 /* CSI0 */
117 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
118 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
119 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
120 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
121 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
122 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
123 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
124 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
125 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
126 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
127 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
128 /* DISPLAY */
129 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
130 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
131 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
132 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
133 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
134 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
135 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
136 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
137 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
138 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
139 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
140 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
141 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
142 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
143 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
144 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
145 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
146 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
147 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
148 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
149 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
150 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
151 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
152 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
153 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
154 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
155 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
156 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
157 /* Audio CLK*/
158 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
159 /* PWM */
160 MX53_PAD_GPIO_1__PWM2_PWMO,
161 /* SPDIF */
162 MX53_PAD_GPIO_7__SPDIF_PLOCK,
163 MX53_PAD_GPIO_17__SPDIF_OUT1,
164 /* GPIO */
165 MX53_PAD_PATA_DA_1__GPIO7_7,
166 MX53_PAD_PATA_DA_2__GPIO7_8,
167 MX53_PAD_PATA_DATA5__GPIO2_5,
168 MX53_PAD_PATA_DATA6__GPIO2_6,
169 MX53_PAD_PATA_DATA14__GPIO2_14,
170 MX53_PAD_PATA_DATA15__GPIO2_15,
171 MX53_PAD_PATA_INTRQ__GPIO7_2,
172 MX53_PAD_EIM_WAIT__GPIO5_0,
173 MX53_PAD_NANDF_WP_B__GPIO6_9,
174 MX53_PAD_NANDF_RB0__GPIO6_10,
175 MX53_PAD_NANDF_CS1__GPIO6_14,
176 MX53_PAD_NANDF_CS2__GPIO6_15,
177 MX53_PAD_NANDF_CS3__GPIO6_16,
178 MX53_PAD_GPIO_5__GPIO1_5,
179 MX53_PAD_GPIO_16__GPIO7_11,
180 MX53_PAD_GPIO_8__GPIO1_8,
56}; 181};
57 182
58static const struct imxuart_platform_data mx53_loco_uart_data __initconst = {
59 .flags = IMXUART_HAVE_RTSCTS,
60};
61
62static inline void mx53_loco_init_uart(void)
63{
64 imx53_add_imx_uart(0, &mx53_loco_uart_data);
65 imx53_add_imx_uart(1, &mx53_loco_uart_data);
66 imx53_add_imx_uart(2, &mx53_loco_uart_data);
67}
68
69static inline void mx53_loco_fec_reset(void) 183static inline void mx53_loco_fec_reset(void)
70{ 184{
71 int ret; 185 int ret;
@@ -85,13 +199,22 @@ static struct fec_platform_data mx53_loco_fec_data = {
85 .phy = PHY_INTERFACE_MODE_RMII, 199 .phy = PHY_INTERFACE_MODE_RMII,
86}; 200};
87 201
202static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
203 .bitrate = 100000,
204};
205
88static void __init mx53_loco_board_init(void) 206static void __init mx53_loco_board_init(void)
89{ 207{
90 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, 208 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
91 ARRAY_SIZE(mx53_loco_pads)); 209 ARRAY_SIZE(mx53_loco_pads));
92 mx53_loco_init_uart(); 210 imx53_add_imx_uart(0, NULL);
93 mx53_loco_fec_reset(); 211 mx53_loco_fec_reset();
94 imx53_add_fec(&mx53_loco_fec_data); 212 imx53_add_fec(&mx53_loco_fec_data);
213 imx53_add_imx2_wdt(0, NULL);
214 imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
215 imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
216 imx53_add_sdhci_esdhc_imx(0, NULL);
217 imx53_add_sdhci_esdhc_imx(2, NULL);
95} 218}
96 219
97static void __init mx53_loco_timer_init(void) 220static void __init mx53_loco_timer_init(void)
@@ -105,7 +228,8 @@ static struct sys_timer mx53_loco_timer = {
105 228
106MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board") 229MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
107 .map_io = mx53_map_io, 230 .map_io = mx53_map_io,
231 .init_early = imx53_init_early,
108 .init_irq = mx53_init_irq, 232 .init_irq = mx53_init_irq,
109 .init_machine = mx53_loco_board_init,
110 .timer = &mx53_loco_timer, 233 .timer = &mx53_loco_timer,
234 .init_machine = mx53_loco_board_init,
111MACHINE_END 235MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index 7970f7a4858..31e173267ed 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -39,20 +39,19 @@
39#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) 39#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
40 40
41static iomux_v3_cfg_t mx53_smd_pads[] = { 41static iomux_v3_cfg_t mx53_smd_pads[] = {
42 MX53_PAD_CSI0_D10__UART1_TXD, 42 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
43 MX53_PAD_CSI0_D11__UART1_RXD, 43 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
44 MX53_PAD_ATA_DIOW__UART1_TXD, 44
45 MX53_PAD_ATA_DMACK__UART1_RXD, 45 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
46 46 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
47 MX53_PAD_ATA_BUFFER_EN__UART2_RXD, 47
48 MX53_PAD_ATA_DMARQ__UART2_TXD, 48 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
49 MX53_PAD_ATA_DIOR__UART2_RTS, 49 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
50 MX53_PAD_ATA_INTRQ__UART2_CTS, 50 MX53_PAD_PATA_DA_1__UART3_CTS,
51 51 MX53_PAD_PATA_DA_2__UART3_RTS,
52 MX53_PAD_ATA_CS_0__UART3_TXD, 52 /* I2C1 */
53 MX53_PAD_ATA_CS_1__UART3_RXD, 53 MX53_PAD_CSI0_DAT8__I2C1_SDA,
54 MX53_PAD_ATA_DA_1__UART3_CTS, 54 MX53_PAD_CSI0_DAT9__I2C1_SCL,
55 MX53_PAD_ATA_DA_2__UART3_RTS,
56}; 55};
57 56
58static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { 57static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
@@ -61,8 +60,8 @@ static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
61 60
62static inline void mx53_smd_init_uart(void) 61static inline void mx53_smd_init_uart(void)
63{ 62{
64 imx53_add_imx_uart(0, &mx53_smd_uart_data); 63 imx53_add_imx_uart(0, NULL);
65 imx53_add_imx_uart(1, &mx53_smd_uart_data); 64 imx53_add_imx_uart(1, NULL);
66 imx53_add_imx_uart(2, &mx53_smd_uart_data); 65 imx53_add_imx_uart(2, &mx53_smd_uart_data);
67} 66}
68 67
@@ -85,6 +84,10 @@ static struct fec_platform_data mx53_smd_fec_data = {
85 .phy = PHY_INTERFACE_MODE_RMII, 84 .phy = PHY_INTERFACE_MODE_RMII,
86}; 85};
87 86
87static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
88 .bitrate = 100000,
89};
90
88static void __init mx53_smd_board_init(void) 91static void __init mx53_smd_board_init(void)
89{ 92{
90 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, 93 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
@@ -92,6 +95,8 @@ static void __init mx53_smd_board_init(void)
92 mx53_smd_init_uart(); 95 mx53_smd_init_uart();
93 mx53_smd_fec_reset(); 96 mx53_smd_fec_reset();
94 imx53_add_fec(&mx53_smd_fec_data); 97 imx53_add_fec(&mx53_smd_fec_data);
98 imx53_add_imx2_wdt(0, NULL);
99 imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
95} 100}
96 101
97static void __init mx53_smd_timer_init(void) 102static void __init mx53_smd_timer_init(void)
@@ -105,7 +110,8 @@ static struct sys_timer mx53_smd_timer = {
105 110
106MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") 111MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
107 .map_io = mx53_map_io, 112 .map_io = mx53_map_io,
113 .init_early = imx53_init_early,
108 .init_irq = mx53_init_irq, 114 .init_irq = mx53_init_irq,
109 .init_machine = mx53_smd_board_init,
110 .timer = &mx53_smd_timer, 115 .timer = &mx53_smd_timer,
116 .init_machine = mx53_smd_board_init,
111MACHINE_END 117MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 0a19e7567c0..652ace41382 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -42,6 +42,9 @@ static struct clk usboh3_clk;
42static struct clk emi_fast_clk; 42static struct clk emi_fast_clk;
43static struct clk ipu_clk; 43static struct clk ipu_clk;
44static struct clk mipi_hsc1_clk; 44static struct clk mipi_hsc1_clk;
45static struct clk esdhc1_clk;
46static struct clk esdhc2_clk;
47static struct clk esdhc3_mx53_clk;
45 48
46#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ 49#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
47 50
@@ -867,10 +870,6 @@ static struct clk gpt_32k_clk = {
867 .parent = &ckil_clk, 870 .parent = &ckil_clk,
868}; 871};
869 872
870static struct clk kpp_clk = {
871 .id = 0,
872};
873
874static struct clk dummy_clk = { 873static struct clk dummy_clk = {
875 .id = 0, 874 .id = 0,
876}; 875};
@@ -1147,10 +1146,80 @@ CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1147CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1) 1146CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
1148CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1) 1147CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
1149 1148
1149/* mx51 specific */
1150CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2) 1150CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1151CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2) 1151CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
1152CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2) 1152CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
1153 1153
1154static int clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
1155{
1156 u32 reg;
1157
1158 reg = __raw_readl(MXC_CCM_CSCMR1);
1159 if (parent == &esdhc1_clk)
1160 reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1161 else if (parent == &esdhc2_clk)
1162 reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL;
1163 else
1164 return -EINVAL;
1165 __raw_writel(reg, MXC_CCM_CSCMR1);
1166
1167 return 0;
1168}
1169
1170static int clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
1171{
1172 u32 reg;
1173
1174 reg = __raw_readl(MXC_CCM_CSCMR1);
1175 if (parent == &esdhc1_clk)
1176 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1177 else if (parent == &esdhc2_clk)
1178 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1179 else
1180 return -EINVAL;
1181 __raw_writel(reg, MXC_CCM_CSCMR1);
1182
1183 return 0;
1184}
1185
1186/* mx53 specific */
1187static int clk_esdhc2_mx53_set_parent(struct clk *clk, struct clk *parent)
1188{
1189 u32 reg;
1190
1191 reg = __raw_readl(MXC_CCM_CSCMR1);
1192 if (parent == &esdhc1_clk)
1193 reg &= ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1194 else if (parent == &esdhc3_mx53_clk)
1195 reg |= MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL;
1196 else
1197 return -EINVAL;
1198 __raw_writel(reg, MXC_CCM_CSCMR1);
1199
1200 return 0;
1201}
1202
1203CLK_GET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1204CLK_SET_PARENT(esdhc3_mx53, 1, ESDHC3_MX53)
1205CLK_SET_RATE(esdhc3_mx53, 1, ESDHC3_MX53)
1206
1207static int clk_esdhc4_mx53_set_parent(struct clk *clk, struct clk *parent)
1208{
1209 u32 reg;
1210
1211 reg = __raw_readl(MXC_CCM_CSCMR1);
1212 if (parent == &esdhc1_clk)
1213 reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1214 else if (parent == &esdhc3_mx53_clk)
1215 reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
1216 else
1217 return -EINVAL;
1218 __raw_writel(reg, MXC_CCM_CSCMR1);
1219
1220 return 0;
1221}
1222
1154#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ 1223#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
1155 static struct clk name = { \ 1224 static struct clk name = { \
1156 .id = i, \ 1225 .id = i, \
@@ -1255,9 +1324,62 @@ DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1255 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk); 1324 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1256DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET, 1325DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1257 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL); 1326 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1327DEFINE_CLOCK_FULL(esdhc3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG4_OFFSET,
1328 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1329DEFINE_CLOCK_FULL(esdhc4_ipg_clk, 3, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG6_OFFSET,
1330 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1331
1332/* mx51 specific */
1258DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, 1333DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1259 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); 1334 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1260 1335
1336static struct clk esdhc3_clk = {
1337 .id = 2,
1338 .parent = &esdhc1_clk,
1339 .set_parent = clk_esdhc3_set_parent,
1340 .enable_reg = MXC_CCM_CCGR3,
1341 .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1342 .enable = _clk_max_enable,
1343 .disable = _clk_max_disable,
1344 .secondary = &esdhc3_ipg_clk,
1345};
1346static struct clk esdhc4_clk = {
1347 .id = 3,
1348 .parent = &esdhc1_clk,
1349 .set_parent = clk_esdhc4_set_parent,
1350 .enable_reg = MXC_CCM_CCGR3,
1351 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1352 .enable = _clk_max_enable,
1353 .disable = _clk_max_disable,
1354 .secondary = &esdhc4_ipg_clk,
1355};
1356
1357/* mx53 specific */
1358static struct clk esdhc2_mx53_clk = {
1359 .id = 2,
1360 .parent = &esdhc1_clk,
1361 .set_parent = clk_esdhc2_mx53_set_parent,
1362 .enable_reg = MXC_CCM_CCGR3,
1363 .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1364 .enable = _clk_max_enable,
1365 .disable = _clk_max_disable,
1366 .secondary = &esdhc3_ipg_clk,
1367};
1368
1369DEFINE_CLOCK_MAX(esdhc3_mx53_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG5_OFFSET,
1370 clk_esdhc3_mx53, &pll2_sw_clk, &esdhc2_ipg_clk);
1371
1372static struct clk esdhc4_mx53_clk = {
1373 .id = 3,
1374 .parent = &esdhc1_clk,
1375 .set_parent = clk_esdhc4_mx53_set_parent,
1376 .enable_reg = MXC_CCM_CCGR3,
1377 .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1378 .enable = _clk_max_enable,
1379 .disable = _clk_max_disable,
1380 .secondary = &esdhc4_ipg_clk,
1381};
1382
1261DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk); 1383DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
1262DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk); 1384DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
1263DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk); 1385DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
@@ -1302,7 +1424,7 @@ static struct clk_lookup mx51_lookups[] = {
1302 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk) 1424 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
1303 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) 1425 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1304 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) 1426 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1305 _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk) 1427 _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
1306 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) 1428 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1307 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) 1429 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1308 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) 1430 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
@@ -1316,6 +1438,8 @@ static struct clk_lookup mx51_lookups[] = {
1316 _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) 1438 _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
1317 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) 1439 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1318 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) 1440 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
1441 _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
1442 _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk)
1319 _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) 1443 _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
1320 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk) 1444 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1321 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk) 1445 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
@@ -1336,10 +1460,14 @@ static struct clk_lookup mx53_lookups[] = {
1336 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) 1460 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1337 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) 1461 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1338 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) 1462 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1339 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) 1463 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
1464 _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
1465 _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
1340 _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk) 1466 _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
1341 _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk) 1467 _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
1342 _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk) 1468 _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
1469 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1470 _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1343}; 1471};
1344 1472
1345static void clk_tree_init(void) 1473static void clk_tree_init(void)
@@ -1427,6 +1555,14 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1427 mx53_revision(); 1555 mx53_revision();
1428 clk_disable(&iim_clk); 1556 clk_disable(&iim_clk);
1429 1557
1558 /* Set SDHC parents to be PLL2 */
1559 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1560 clk_set_parent(&esdhc3_mx53_clk, &pll2_sw_clk);
1561
1562 /* set SDHC root clock as 200MHZ*/
1563 clk_set_rate(&esdhc1_clk, 200000000);
1564 clk_set_rate(&esdhc3_mx53_clk, 200000000);
1565
1430 /* System timer */ 1566 /* System timer */
1431 mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), 1567 mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
1432 MX53_INT_GPT); 1568 MX53_INT_GPT);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index d40671da437..df46b5e6085 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -78,11 +78,16 @@ static int get_mx53_srev(void)
78 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); 78 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
79 u32 rev = readl(iim_base + IIM_SREV) & 0xff; 79 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
80 80
81 if (rev == 0x0) 81 switch (rev) {
82 case 0x0:
82 return IMX_CHIP_REVISION_1_0; 83 return IMX_CHIP_REVISION_1_0;
83 else if (rev == 0x10) 84 case 0x2:
84 return IMX_CHIP_REVISION_2_0; 85 return IMX_CHIP_REVISION_2_0;
85 return 0; 86 case 0x3:
87 return IMX_CHIP_REVISION_2_1;
88 default:
89 return IMX_CHIP_REVISION_UNKNOWN;
90 }
86} 91}
87 92
88/* 93/*
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index b462c22f53d..87c0c58f27a 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -217,9 +217,12 @@
217#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) 217#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
218#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) 218#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
219#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) 219#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
220#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
220#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) 221#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
221#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) 222#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
222#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) 223#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
224#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
225#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
223#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) 226#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
224#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) 227#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
225#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) 228#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
@@ -271,6 +274,10 @@
271#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) 274#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
272#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) 275#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
273#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) 276#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
277#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
278#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
279#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
280#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
274#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) 281#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
275#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) 282#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
276#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) 283#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
diff --git a/arch/arm/mach-mx5/devices-mx50.h b/arch/arm/mach-mx5/devices-imx50.h
index 98ab07468a0..c9e42823c7e 100644
--- a/arch/arm/mach-mx5/devices-mx50.h
+++ b/arch/arm/mach-mx5/devices-imx50.h
@@ -24,3 +24,11 @@
24extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst; 24extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
25#define imx50_add_imx_uart(id, pdata) \ 25#define imx50_add_imx_uart(id, pdata) \
26 imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata) 26 imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
27
28extern const struct imx_fec_data imx50_fec_data __initconst;
29#define imx50_add_fec(pdata) \
30 imx_add_fec(&imx50_fec_data, pdata)
31
32extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst;
33#define imx50_add_imx_i2c(id, pdata) \
34 imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 8639735a117..9251008dad1 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -29,3 +29,7 @@ imx53_sdhci_esdhc_imx_data[] __initconst;
29extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst; 29extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
30#define imx53_add_ecspi(id, pdata) \ 30#define imx53_add_ecspi(id, pdata) \
31 imx_add_spi_imx(&imx53_ecspi_data[id], pdata) 31 imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
32
33extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
34#define imx53_add_imx2_wdt(id, pdata) \
35 imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-mx5/efika.h
new file mode 100644
index 00000000000..014aa985faa
--- /dev/null
+++ b/arch/arm/mach-mx5/efika.h
@@ -0,0 +1,10 @@
1#ifndef _EFIKA_H
2#define _EFIKA_H
3
4#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16)
5#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10)
6#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9)
7
8void __init efika_board_common_init(void);
9
10#endif
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-mx5/ehci.c
new file mode 100644
index 00000000000..7ce12c804a3
--- /dev/null
+++ b/arch/arm/mach-mx5/ehci.c
@@ -0,0 +1,156 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define MXC_OTG_OFFSET 0
23#define MXC_H1_OFFSET 0x200
24#define MXC_H2_OFFSET 0x400
25
26/* USB_CTRL */
27#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
28#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
29#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
30#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
31#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
32
33/* USB_PHY_CTRL_FUNC */
34#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
35#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
36
37/* USBH2CTRL */
38#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
39#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
40#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
41
42#define MXC_USBCMD_OFFSET 0x140
43
44/* USBCMD */
45#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
46
47int mx51_initialize_usb_hw(int port, unsigned int flags)
48{
49 unsigned int v;
50 void __iomem *usb_base;
51 void __iomem *usbotg_base;
52 void __iomem *usbother_base;
53 int ret = 0;
54
55 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
56 if (!usb_base) {
57 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
58 return -ENOMEM;
59 }
60
61 switch (port) {
62 case 0: /* OTG port */
63 usbotg_base = usb_base + MXC_OTG_OFFSET;
64 break;
65 case 1: /* Host 1 port */
66 usbotg_base = usb_base + MXC_H1_OFFSET;
67 break;
68 case 2: /* Host 2 port */
69 usbotg_base = usb_base + MXC_H2_OFFSET;
70 break;
71 default:
72 printk(KERN_ERR"%s no such port %d\n", __func__, port);
73 ret = -ENOENT;
74 goto error;
75 }
76 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
77
78 switch (port) {
79 case 0: /*OTG port */
80 if (flags & MXC_EHCI_INTERNAL_PHY) {
81 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
82
83 if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
84 /* OC/USBPWR is not used */
85 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
86 } else {
87 /* OC/USBPWR is used */
88 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
89 }
90 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
91
92 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
93 if (flags & MXC_EHCI_WAKEUP_ENABLED)
94 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
95 else
96 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
97 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
98 v |= MXC_OTG_UCTRL_OPM_BIT;
99 else
100 v &= ~MXC_OTG_UCTRL_OPM_BIT;
101 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
102 }
103 break;
104 case 1: /* Host 1 */
105 /*Host ULPI */
106 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
107 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
108 /* HOST1 wakeup/ULPI intr enable */
109 v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
110 } else {
111 /* HOST1 wakeup/ULPI intr disable */
112 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
113 }
114
115 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
116 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
117 else
118 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
119 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
120
121 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
122 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
123 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
124 else
125 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
126 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
127
128 v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
129 if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
130 /* Interrupt Threshold Control:Immediate (no threshold) */
131 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
132 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
133 break;
134 case 2: /* Host 2 ULPI */
135 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
136 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
137 /* HOST1 wakeup/ULPI intr enable */
138 v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
139 } else {
140 /* HOST1 wakeup/ULPI intr disable */
141 v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
142 }
143
144 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
145 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
146 else
147 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
148 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
149 break;
150 }
151
152error:
153 iounmap(usb_base);
154 return ret;
155}
156
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
index 8c6540e5839..b9c363b514a 100644
--- a/arch/arm/mach-mx5/mm-mx50.c
+++ b/arch/arm/mach-mx5/mm-mx50.c
@@ -26,6 +26,8 @@
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/common.h> 27#include <mach/common.h>
28#include <mach/iomux-v3.h> 28#include <mach/iomux-v3.h>
29#include <mach/gpio.h>
30#include <mach/irqs.h>
29 31
30/* 32/*
31 * Define the MX50 memory map. 33 * Define the MX50 memory map.
@@ -44,16 +46,27 @@ static struct map_desc mx50_io_desc[] __initdata = {
44 */ 46 */
45void __init mx50_map_io(void) 47void __init mx50_map_io(void)
46{ 48{
49 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
50}
51
52void __init imx50_init_early(void)
53{
47 mxc_set_cpu_type(MXC_CPU_MX50); 54 mxc_set_cpu_type(MXC_CPU_MX50);
48 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR)); 55 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
49 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); 56 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
50 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
51} 57}
52 58
53int imx50_register_gpios(void); 59static struct mxc_gpio_port imx50_gpio_ports[] = {
60 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
61 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
62 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
63 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
64 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
65 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
66};
54 67
55void __init mx50_init_irq(void) 68void __init mx50_init_irq(void)
56{ 69{
57 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR)); 70 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
58 imx50_register_gpios(); 71 mxc_gpio_init(imx50_gpio_ports, ARRAY_SIZE(imx50_gpio_ports));
59} 72}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 457f9f95204..ff557301b42 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -47,18 +47,26 @@ static struct map_desc mx53_io_desc[] __initdata = {
47 */ 47 */
48void __init mx51_map_io(void) 48void __init mx51_map_io(void)
49{ 49{
50 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
51}
52
53void __init imx51_init_early(void)
54{
50 mxc_set_cpu_type(MXC_CPU_MX51); 55 mxc_set_cpu_type(MXC_CPU_MX51);
51 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); 56 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
52 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); 57 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
53 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
54} 58}
55 59
56void __init mx53_map_io(void) 60void __init mx53_map_io(void)
57{ 61{
62 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
63}
64
65void __init imx53_init_early(void)
66{
58 mxc_set_cpu_type(MXC_CPU_MX53); 67 mxc_set_cpu_type(MXC_CPU_MX53);
59 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); 68 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
60 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR)); 69 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
61 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
62} 70}
63 71
64int imx51_register_gpios(void); 72int imx51_register_gpios(void);
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
new file mode 100644
index 00000000000..51a67fc7f0e
--- /dev/null
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -0,0 +1,636 @@
1/*
2 * based on code from the following
3 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
5 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
6 *
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/i2c.h>
18#include <linux/gpio.h>
19#include <linux/leds.h>
20#include <linux/input.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/fsl_devices.h>
24#include <linux/spi/flash.h>
25#include <linux/spi/spi.h>
26#include <linux/mfd/mc13892.h>
27#include <linux/regulator/machine.h>
28#include <linux/regulator/consumer.h>
29
30#include <mach/common.h>
31#include <mach/hardware.h>
32#include <mach/iomux-mx51.h>
33#include <mach/i2c.h>
34#include <mach/mxc_ehci.h>
35
36#include <linux/usb/otg.h>
37#include <linux/usb/ulpi.h>
38#include <mach/ulpi.h>
39
40#include <asm/irq.h>
41#include <asm/setup.h>
42#include <asm/mach-types.h>
43#include <asm/mach/arch.h>
44#include <asm/mach/time.h>
45#include <asm/mach-types.h>
46
47#include "devices-imx51.h"
48#include "devices.h"
49#include "efika.h"
50#include "cpu_op-mx51.h"
51
52#define MX51_USB_CTRL_1_OFFSET 0x10
53#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
54#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
55
56#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
57#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
58
59#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
60#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
61
62#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
63
64static iomux_v3_cfg_t mx51efika_pads[] = {
65 /* UART1 */
66 MX51_PAD_UART1_RXD__UART1_RXD,
67 MX51_PAD_UART1_TXD__UART1_TXD,
68 MX51_PAD_UART1_RTS__UART1_RTS,
69 MX51_PAD_UART1_CTS__UART1_CTS,
70
71 /* SD 1 */
72 MX51_PAD_SD1_CMD__SD1_CMD,
73 MX51_PAD_SD1_CLK__SD1_CLK,
74 MX51_PAD_SD1_DATA0__SD1_DATA0,
75 MX51_PAD_SD1_DATA1__SD1_DATA1,
76 MX51_PAD_SD1_DATA2__SD1_DATA2,
77 MX51_PAD_SD1_DATA3__SD1_DATA3,
78
79 /* SD 2 */
80 MX51_PAD_SD2_CMD__SD2_CMD,
81 MX51_PAD_SD2_CLK__SD2_CLK,
82 MX51_PAD_SD2_DATA0__SD2_DATA0,
83 MX51_PAD_SD2_DATA1__SD2_DATA1,
84 MX51_PAD_SD2_DATA2__SD2_DATA2,
85 MX51_PAD_SD2_DATA3__SD2_DATA3,
86
87 /* SD/MMC WP/CD */
88 MX51_PAD_GPIO1_0__SD1_CD,
89 MX51_PAD_GPIO1_1__SD1_WP,
90 MX51_PAD_GPIO1_7__SD2_WP,
91 MX51_PAD_GPIO1_8__SD2_CD,
92
93 /* spi */
94 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
95 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
96 MX51_PAD_CSPI1_SS0__GPIO4_24,
97 MX51_PAD_CSPI1_SS1__GPIO4_25,
98 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
99 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
100 MX51_PAD_GPIO1_6__GPIO1_6,
101
102 /* USB HOST1 */
103 MX51_PAD_USBH1_CLK__USBH1_CLK,
104 MX51_PAD_USBH1_DIR__USBH1_DIR,
105 MX51_PAD_USBH1_NXT__USBH1_NXT,
106 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
107 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
108 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
109 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
110 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
111 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
112 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
113 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
114
115 /* USB HUB RESET */
116 MX51_PAD_GPIO1_5__GPIO1_5,
117
118 /* WLAN */
119 MX51_PAD_EIM_A22__GPIO2_16,
120 MX51_PAD_EIM_A16__GPIO2_10,
121
122 /* USB PHY RESET */
123 MX51_PAD_EIM_D27__GPIO2_9,
124};
125
126/* Serial ports */
127static const struct imxuart_platform_data uart_pdata = {
128 .flags = IMXUART_HAVE_RTSCTS,
129};
130
131/* This function is board specific as the bit mask for the plldiv will also
132 * be different for other Freescale SoCs, thus a common bitmask is not
133 * possible and cannot get place in /plat-mxc/ehci.c.
134 */
135static int initialize_otg_port(struct platform_device *pdev)
136{
137 u32 v;
138 void __iomem *usb_base;
139 void __iomem *usbother_base;
140 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
141 if (!usb_base)
142 return -ENOMEM;
143 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
144
145 /* Set the PHY clock to 19.2MHz */
146 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
147 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
148 v |= MX51_USB_PLL_DIV_19_2_MHZ;
149 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
150 iounmap(usb_base);
151
152 mdelay(10);
153
154 return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
155}
156
157static struct mxc_usbh_platform_data dr_utmi_config = {
158 .init = initialize_otg_port,
159 .portsc = MXC_EHCI_UTMI_16BIT,
160};
161
162static int initialize_usbh1_port(struct platform_device *pdev)
163{
164 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
165 iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
166 u32 v;
167 void __iomem *usb_base;
168 void __iomem *socregs_base;
169
170 mxc_iomux_v3_setup_pad(usbh1gpio);
171 gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
172 gpio_direction_output(EFIKAMX_USBH1_STP, 0);
173 msleep(1);
174 gpio_set_value(EFIKAMX_USBH1_STP, 1);
175 msleep(1);
176
177 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
178 socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
179
180 /* The clock for the USBH1 ULPI port will come externally */
181 /* from the PHY. */
182 v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
183 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
184 socregs_base + MX51_USB_CTRL_1_OFFSET);
185
186 iounmap(usb_base);
187
188 gpio_free(EFIKAMX_USBH1_STP);
189 mxc_iomux_v3_setup_pad(usbh1stp);
190
191 mdelay(10);
192
193 return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD);
194}
195
196static struct mxc_usbh_platform_data usbh1_config = {
197 .init = initialize_usbh1_port,
198 .portsc = MXC_EHCI_MODE_ULPI,
199};
200
201static void mx51_efika_hubreset(void)
202{
203 gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
204 gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
205 msleep(1);
206 gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
207 msleep(1);
208 gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
209}
210
211static void __init mx51_efika_usb(void)
212{
213 mx51_efika_hubreset();
214
215 /* pulling it low, means no USB at all... */
216 gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
217 gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
218 msleep(1);
219 gpio_set_value(EFIKA_USB_PHY_RESET, 1);
220
221 usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
222 ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
223
224 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
225 if (usbh1_config.otg)
226 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
227}
228
229static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
230 {
231 .name = "u-boot",
232 .offset = 0,
233 .size = SZ_256K,
234 },
235 {
236 .name = "config",
237 .offset = MTDPART_OFS_APPEND,
238 .size = SZ_64K,
239 },
240};
241
242static struct flash_platform_data mx51_efika_spi_flash_data = {
243 .name = "spi_flash",
244 .parts = mx51_efika_spi_nor_partitions,
245 .nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
246 .type = "sst25vf032b",
247};
248
249static struct regulator_consumer_supply sw1_consumers[] = {
250 {
251 .supply = "cpu_vcc",
252 }
253};
254
255static struct regulator_consumer_supply vdig_consumers[] = {
256 /* sgtl5000 */
257 REGULATOR_SUPPLY("VDDA", "1-000a"),
258 REGULATOR_SUPPLY("VDDD", "1-000a"),
259};
260
261static struct regulator_consumer_supply vvideo_consumers[] = {
262 /* sgtl5000 */
263 REGULATOR_SUPPLY("VDDIO", "1-000a"),
264};
265
266static struct regulator_consumer_supply vsd_consumers[] = {
267 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
268 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
269};
270
271static struct regulator_consumer_supply pwgt1_consumer[] = {
272 {
273 .supply = "pwgt1",
274 }
275};
276
277static struct regulator_consumer_supply pwgt2_consumer[] = {
278 {
279 .supply = "pwgt2",
280 }
281};
282
283static struct regulator_consumer_supply coincell_consumer[] = {
284 {
285 .supply = "coincell",
286 }
287};
288
289static struct regulator_init_data sw1_init = {
290 .constraints = {
291 .name = "SW1",
292 .min_uV = 600000,
293 .max_uV = 1375000,
294 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
295 .valid_modes_mask = 0,
296 .always_on = 1,
297 .boot_on = 1,
298 .state_mem = {
299 .uV = 850000,
300 .mode = REGULATOR_MODE_NORMAL,
301 .enabled = 1,
302 },
303 },
304 .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
305 .consumer_supplies = sw1_consumers,
306};
307
308static struct regulator_init_data sw2_init = {
309 .constraints = {
310 .name = "SW2",
311 .min_uV = 900000,
312 .max_uV = 1850000,
313 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
314 .always_on = 1,
315 .boot_on = 1,
316 .state_mem = {
317 .uV = 950000,
318 .mode = REGULATOR_MODE_NORMAL,
319 .enabled = 1,
320 },
321 }
322};
323
324static struct regulator_init_data sw3_init = {
325 .constraints = {
326 .name = "SW3",
327 .min_uV = 1100000,
328 .max_uV = 1850000,
329 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
330 .always_on = 1,
331 .boot_on = 1,
332 }
333};
334
335static struct regulator_init_data sw4_init = {
336 .constraints = {
337 .name = "SW4",
338 .min_uV = 1100000,
339 .max_uV = 1850000,
340 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
341 .always_on = 1,
342 .boot_on = 1,
343 }
344};
345
346static struct regulator_init_data viohi_init = {
347 .constraints = {
348 .name = "VIOHI",
349 .boot_on = 1,
350 .always_on = 1,
351 }
352};
353
354static struct regulator_init_data vusb_init = {
355 .constraints = {
356 .name = "VUSB",
357 .boot_on = 1,
358 .always_on = 1,
359 }
360};
361
362static struct regulator_init_data swbst_init = {
363 .constraints = {
364 .name = "SWBST",
365 }
366};
367
368static struct regulator_init_data vdig_init = {
369 .constraints = {
370 .name = "VDIG",
371 .min_uV = 1050000,
372 .max_uV = 1800000,
373 .valid_ops_mask =
374 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
375 .boot_on = 1,
376 .always_on = 1,
377 },
378 .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
379 .consumer_supplies = vdig_consumers,
380};
381
382static struct regulator_init_data vpll_init = {
383 .constraints = {
384 .name = "VPLL",
385 .min_uV = 1050000,
386 .max_uV = 1800000,
387 .valid_ops_mask =
388 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
389 .boot_on = 1,
390 .always_on = 1,
391 }
392};
393
394static struct regulator_init_data vusb2_init = {
395 .constraints = {
396 .name = "VUSB2",
397 .min_uV = 2400000,
398 .max_uV = 2775000,
399 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
400 .boot_on = 1,
401 .always_on = 1,
402 }
403};
404
405static struct regulator_init_data vvideo_init = {
406 .constraints = {
407 .name = "VVIDEO",
408 .min_uV = 2775000,
409 .max_uV = 2775000,
410 .valid_ops_mask =
411 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
412 .boot_on = 1,
413 .apply_uV = 1,
414 },
415 .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
416 .consumer_supplies = vvideo_consumers,
417};
418
419static struct regulator_init_data vaudio_init = {
420 .constraints = {
421 .name = "VAUDIO",
422 .min_uV = 2300000,
423 .max_uV = 3000000,
424 .valid_ops_mask =
425 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
426 .boot_on = 1,
427 }
428};
429
430static struct regulator_init_data vsd_init = {
431 .constraints = {
432 .name = "VSD",
433 .min_uV = 1800000,
434 .max_uV = 3150000,
435 .valid_ops_mask =
436 REGULATOR_CHANGE_VOLTAGE,
437 .boot_on = 1,
438 },
439 .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
440 .consumer_supplies = vsd_consumers,
441};
442
443static struct regulator_init_data vcam_init = {
444 .constraints = {
445 .name = "VCAM",
446 .min_uV = 2500000,
447 .max_uV = 3000000,
448 .valid_ops_mask =
449 REGULATOR_CHANGE_VOLTAGE |
450 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
451 .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
452 .boot_on = 1,
453 }
454};
455
456static struct regulator_init_data vgen1_init = {
457 .constraints = {
458 .name = "VGEN1",
459 .min_uV = 1200000,
460 .max_uV = 3150000,
461 .valid_ops_mask =
462 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
463 .boot_on = 1,
464 .always_on = 1,
465 }
466};
467
468static struct regulator_init_data vgen2_init = {
469 .constraints = {
470 .name = "VGEN2",
471 .min_uV = 1200000,
472 .max_uV = 3150000,
473 .valid_ops_mask =
474 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
475 .boot_on = 1,
476 .always_on = 1,
477 }
478};
479
480static struct regulator_init_data vgen3_init = {
481 .constraints = {
482 .name = "VGEN3",
483 .min_uV = 1800000,
484 .max_uV = 2900000,
485 .valid_ops_mask =
486 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
487 .boot_on = 1,
488 .always_on = 1,
489 }
490};
491
492static struct regulator_init_data gpo1_init = {
493 .constraints = {
494 .name = "GPO1",
495 }
496};
497
498static struct regulator_init_data gpo2_init = {
499 .constraints = {
500 .name = "GPO2",
501 }
502};
503
504static struct regulator_init_data gpo3_init = {
505 .constraints = {
506 .name = "GPO3",
507 }
508};
509
510static struct regulator_init_data gpo4_init = {
511 .constraints = {
512 .name = "GPO4",
513 }
514};
515
516static struct regulator_init_data pwgt1_init = {
517 .constraints = {
518 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
519 .boot_on = 1,
520 },
521 .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
522 .consumer_supplies = pwgt1_consumer,
523};
524
525static struct regulator_init_data pwgt2_init = {
526 .constraints = {
527 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
528 .boot_on = 1,
529 },
530 .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
531 .consumer_supplies = pwgt2_consumer,
532};
533
534static struct regulator_init_data vcoincell_init = {
535 .constraints = {
536 .name = "COINCELL",
537 .min_uV = 3000000,
538 .max_uV = 3000000,
539 .valid_ops_mask =
540 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
541 },
542 .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
543 .consumer_supplies = coincell_consumer,
544};
545
546static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
547 { .id = MC13892_SW1, .init_data = &sw1_init },
548 { .id = MC13892_SW2, .init_data = &sw2_init },
549 { .id = MC13892_SW3, .init_data = &sw3_init },
550 { .id = MC13892_SW4, .init_data = &sw4_init },
551 { .id = MC13892_SWBST, .init_data = &swbst_init },
552 { .id = MC13892_VIOHI, .init_data = &viohi_init },
553 { .id = MC13892_VPLL, .init_data = &vpll_init },
554 { .id = MC13892_VDIG, .init_data = &vdig_init },
555 { .id = MC13892_VSD, .init_data = &vsd_init },
556 { .id = MC13892_VUSB2, .init_data = &vusb2_init },
557 { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
558 { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
559 { .id = MC13892_VCAM, .init_data = &vcam_init },
560 { .id = MC13892_VGEN1, .init_data = &vgen1_init },
561 { .id = MC13892_VGEN2, .init_data = &vgen2_init },
562 { .id = MC13892_VGEN3, .init_data = &vgen3_init },
563 { .id = MC13892_VUSB, .init_data = &vusb_init },
564 { .id = MC13892_GPO1, .init_data = &gpo1_init },
565 { .id = MC13892_GPO2, .init_data = &gpo2_init },
566 { .id = MC13892_GPO3, .init_data = &gpo3_init },
567 { .id = MC13892_GPO4, .init_data = &gpo4_init },
568 { .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
569 { .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
570 { .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
571};
572
573static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
574 .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
575 .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
576 .regulators = mx51_efika_regulators,
577};
578
579static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
580 {
581 .modalias = "m25p80",
582 .max_speed_hz = 25000000,
583 .bus_num = 0,
584 .chip_select = 1,
585 .platform_data = &mx51_efika_spi_flash_data,
586 .irq = -1,
587 },
588 {
589 .modalias = "mc13892",
590 .max_speed_hz = 1000000,
591 .bus_num = 0,
592 .chip_select = 0,
593 .platform_data = &mx51_efika_mc13892_data,
594 .irq = gpio_to_irq(EFIKAMX_PMIC),
595 },
596};
597
598static int mx51_efika_spi_cs[] = {
599 EFIKAMX_SPI_CS0,
600 EFIKAMX_SPI_CS1,
601};
602
603static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
604 .chipselect = mx51_efika_spi_cs,
605 .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
606};
607
608void __init efika_board_common_init(void)
609{
610 mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
611 ARRAY_SIZE(mx51efika_pads));
612 imx51_add_imx_uart(0, &uart_pdata);
613 mx51_efika_usb();
614 imx51_add_sdhci_esdhc_imx(0, NULL);
615
616 /* FIXME: comes from original code. check this. */
617 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
618 sw2_init.constraints.state_mem.uV = 1100000;
619 else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
620 sw2_init.constraints.state_mem.uV = 1250000;
621 sw1_init.constraints.state_mem.uV = 1000000;
622 }
623 if (machine_is_mx51_efikasb())
624 vgen1_init.constraints.max_uV = 1200000;
625
626 gpio_request(EFIKAMX_PMIC, "pmic irq");
627 gpio_direction_input(EFIKAMX_PMIC);
628 spi_register_board_info(mx51_efika_spi_board_info,
629 ARRAY_SIZE(mx51_efika_spi_board_info));
630 imx51_add_ecspi(0, &mx51_efika_spi_pdata);
631
632#if defined(CONFIG_CPU_FREQ_IMX)
633 get_cpu_op = mx51_get_cpu_op;
634#endif
635}
636
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
index 405d9b19d89..66fc41cbf2c 100644
--- a/arch/arm/mach-mxc91231/iomux.c
+++ b/arch/arm/mach-mxc91231/iomux.c
@@ -50,7 +50,7 @@ unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
50/* 50/*
51 * set the mode for a IOMUX pin. 51 * set the mode for a IOMUX pin.
52 */ 52 */
53int mxc_iomux_mode(const unsigned int pin_mode) 53int mxc_iomux_mode(unsigned int pin_mode)
54{ 54{
55 u32 side, field, l, mode, ret = 0; 55 u32 side, field, l, mode, ret = 0;
56 void __iomem *reg; 56 void __iomem *reg;
@@ -114,7 +114,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad);
114 * - reserves the pin so that it is not claimed by another driver 114 * - reserves the pin so that it is not claimed by another driver
115 * - setups the iomux according to the configuration 115 * - setups the iomux according to the configuration
116 */ 116 */
117int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label) 117int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label)
118{ 118{
119 unsigned pad = PIN_GLOBAL_NUM(pin_mode); 119 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
120 if (pad >= (PIN_MAX + 1)) { 120 if (pad >= (PIN_MAX + 1)) {
@@ -134,10 +134,10 @@ int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
134} 134}
135EXPORT_SYMBOL(mxc_iomux_alloc_pin); 135EXPORT_SYMBOL(mxc_iomux_alloc_pin);
136 136
137int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, 137int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
138 const char *label) 138 const char *label)
139{ 139{
140 unsigned int *p = pin_list; 140 const unsigned int *p = pin_list;
141 int i; 141 int i;
142 int ret = -EINVAL; 142 int ret = -EINVAL;
143 143
@@ -155,7 +155,7 @@ setup_error:
155} 155}
156EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); 156EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
157 157
158void mxc_iomux_release_pin(const unsigned int pin_mode) 158void mxc_iomux_release_pin(unsigned int pin_mode)
159{ 159{
160 unsigned pad = PIN_GLOBAL_NUM(pin_mode); 160 unsigned pad = PIN_GLOBAL_NUM(pin_mode);
161 161
@@ -164,9 +164,9 @@ void mxc_iomux_release_pin(const unsigned int pin_mode)
164} 164}
165EXPORT_SYMBOL(mxc_iomux_release_pin); 165EXPORT_SYMBOL(mxc_iomux_release_pin);
166 166
167void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count) 167void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
168{ 168{
169 unsigned int *p = pin_list; 169 const unsigned int *p = pin_list;
170 int i; 170 int i;
171 171
172 for (i = 0; i < count; i++) { 172 for (i = 0; i < count; i++) {
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
index 395d83be8c9..f31a45e5a0b 100644
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -53,9 +53,10 @@ struct sys_timer zn5_timer = {
53}; 53};
54 54
55MACHINE_START(MAGX_ZN5, "Motorola Zn5") 55MACHINE_START(MAGX_ZN5, "Motorola Zn5")
56 .boot_params = MXC91231_PHYS_OFFSET + 0x100, 56 .boot_params = MXC91231_PHYS_OFFSET + 0x100,
57 .map_io = mxc91231_map_io, 57 .map_io = mxc91231_map_io,
58 .init_irq = mxc91231_init_irq, 58 .init_early = mxc91231_init_early,
59 .timer = &zn5_timer, 59 .init_irq = mxc91231_init_irq,
60 .init_machine = zn5_init, 60 .timer = &zn5_timer,
61 .init_machine = zn5_init,
61MACHINE_END 62MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index 7652c301da8..a77f6daf6a2 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -45,11 +45,14 @@ static struct map_desc mxc91231_io_desc[] __initdata = {
45 */ 45 */
46void __init mxc91231_map_io(void) 46void __init mxc91231_map_io(void)
47{ 47{
48 mxc_set_cpu_type(MXC_CPU_MXC91231);
49
50 iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc)); 48 iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
51} 49}
52 50
51void __init mxc91231_init_early(void)
52{
53 mxc_set_cpu_type(MXC_CPU_MXC91231);
54}
55
53int mxc91231_register_gpios(void); 56int mxc91231_register_gpios(void);
54 57
55void __init mxc91231_init_irq(void) 58void __init mxc91231_init_irq(void)
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 8bfc8df5461..4f6f174af6c 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -2,13 +2,18 @@ if ARCH_MXS
2 2
3source "arch/arm/mach-mxs/devices/Kconfig" 3source "arch/arm/mach-mxs/devices/Kconfig"
4 4
5config MXS_OCOTP
6 bool
7
5config SOC_IMX23 8config SOC_IMX23
6 bool 9 bool
7 select CPU_ARM926T 10 select CPU_ARM926T
11 select HAVE_PWM
8 12
9config SOC_IMX28 13config SOC_IMX28
10 bool 14 bool
11 select CPU_ARM926T 15 select CPU_ARM926T
16 select HAVE_PWM
12 17
13comment "MXS platforms:" 18comment "MXS platforms:"
14 19
@@ -16,6 +21,8 @@ config MACH_MX23EVK
16 bool "Support MX23EVK Platform" 21 bool "Support MX23EVK Platform"
17 select SOC_IMX23 22 select SOC_IMX23
18 select MXS_HAVE_AMBA_DUART 23 select MXS_HAVE_AMBA_DUART
24 select MXS_HAVE_PLATFORM_AUART
25 select MXS_HAVE_PLATFORM_MXSFB
19 default y 26 default y
20 help 27 help
21 Include support for MX23EVK platform. This includes specific 28 Include support for MX23EVK platform. This includes specific
@@ -25,10 +32,27 @@ config MACH_MX28EVK
25 bool "Support MX28EVK Platform" 32 bool "Support MX28EVK Platform"
26 select SOC_IMX28 33 select SOC_IMX28
27 select MXS_HAVE_AMBA_DUART 34 select MXS_HAVE_AMBA_DUART
35 select MXS_HAVE_PLATFORM_AUART
28 select MXS_HAVE_PLATFORM_FEC 36 select MXS_HAVE_PLATFORM_FEC
37 select MXS_HAVE_PLATFORM_FLEXCAN
38 select MXS_HAVE_PLATFORM_MXSFB
39 select MXS_OCOTP
29 default y 40 default y
30 help 41 help
31 Include support for MX28EVK platform. This includes specific 42 Include support for MX28EVK platform. This includes specific
32 configurations for the board and its peripherals. 43 configurations for the board and its peripherals.
33 44
45config MODULE_TX28
46 bool
47 select SOC_IMX28
48 select MXS_HAVE_AMBA_DUART
49 select MXS_HAVE_PLATFORM_AUART
50 select MXS_HAVE_PLATFORM_FEC
51 select MXS_HAVE_PLATFORM_MXS_I2C
52 select MXS_HAVE_PLATFORM_MXS_PWM
53
54config MACH_TX28
55 bool "Ka-Ro TX28 module"
56 select MODULE_TX28
57
34endif 58endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 39d3f9c2a84..2f1f6141ca7 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,10 +1,15 @@
1# Common support 1# Common support
2obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o 2obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
3 3
4obj-$(CONFIG_MXS_OCOTP) += ocotp.o
5obj-$(CONFIG_PM) += pm.o
6
4obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o 7obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
5obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o 8obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
6 9
7obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o 10obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
8obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o 11obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
12obj-$(CONFIG_MODULE_TX28) += module-tx28.o
13obj-$(CONFIG_MACH_TX28) += mach-tx28.o
9 14
10obj-y += devices/ 15obj-y += devices/
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index ca72a05ed9c..d133c7f3094 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -442,11 +442,18 @@ static struct clk_lookup lookups[] = {
442 _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk) 442 _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
443 /* for amba-pl011 driver */ 443 /* for amba-pl011 driver */
444 _REGISTER_CLOCK("duart", NULL, uart_clk) 444 _REGISTER_CLOCK("duart", NULL, uart_clk)
445 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
445 _REGISTER_CLOCK("rtc", NULL, rtc_clk) 446 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
446 _REGISTER_CLOCK(NULL, "hclk", hbus_clk) 447 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
448 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
447 _REGISTER_CLOCK(NULL, "usb", usb_clk) 449 _REGISTER_CLOCK(NULL, "usb", usb_clk)
448 _REGISTER_CLOCK(NULL, "audio", audio_clk) 450 _REGISTER_CLOCK(NULL, "audio", audio_clk)
449 _REGISTER_CLOCK(NULL, "pwm", pwm_clk) 451 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
452 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
453 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
454 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
455 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
456 _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
450}; 457};
451 458
452static int clk_misc_init(void) 459static int clk_misc_init(void)
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index fd1c4c54b8e..5e489a2b202 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -609,17 +609,30 @@ static struct clk_lookup lookups[] = {
609 _REGISTER_CLOCK("duart", NULL, uart_clk) 609 _REGISTER_CLOCK("duart", NULL, uart_clk)
610 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk) 610 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
611 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk) 611 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
612 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
613 _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
614 _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
615 _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
616 _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
612 _REGISTER_CLOCK("rtc", NULL, rtc_clk) 617 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
613 _REGISTER_CLOCK("pll2", NULL, pll2_clk) 618 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
614 _REGISTER_CLOCK(NULL, "hclk", hbus_clk) 619 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
615 _REGISTER_CLOCK(NULL, "xclk", xbus_clk) 620 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
616 _REGISTER_CLOCK(NULL, "can0", can0_clk) 621 _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
617 _REGISTER_CLOCK(NULL, "can1", can1_clk) 622 _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
618 _REGISTER_CLOCK(NULL, "usb0", usb0_clk) 623 _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
619 _REGISTER_CLOCK(NULL, "usb1", usb1_clk) 624 _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
620 _REGISTER_CLOCK(NULL, "pwm", pwm_clk) 625 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
626 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
627 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
628 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
629 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
630 _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
631 _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
632 _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
621 _REGISTER_CLOCK(NULL, "lradc", lradc_clk) 633 _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
622 _REGISTER_CLOCK(NULL, "spdif", spdif_clk) 634 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
635 _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
623}; 636};
624 637
625static int clk_misc_init(void) 638static int clk_misc_init(void)
@@ -737,6 +750,8 @@ int __init mx28_clocks_init(void)
737 clk_enable(&emi_clk); 750 clk_enable(&emi_clk);
738 clk_enable(&uart_clk); 751 clk_enable(&uart_clk);
739 752
753 clk_set_parent(&lcdif_clk, &ref_pix_clk);
754
740 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 755 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
741 756
742 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0); 757 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 1256788561d..c7e14f4e366 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -10,7 +10,18 @@
10 */ 10 */
11#include <mach/mx23.h> 11#include <mach/mx23.h>
12#include <mach/devices-common.h> 12#include <mach/devices-common.h>
13#include <mach/mxsfb.h>
13 14
14extern const struct amba_device mx23_duart_device __initconst; 15extern const struct amba_device mx23_duart_device __initconst;
15#define mx23_add_duart() \ 16#define mx23_add_duart() \
16 mxs_add_duart(&mx23_duart_device) 17 mxs_add_duart(&mx23_duart_device)
18
19extern const struct mxs_auart_data mx23_auart_data[] __initconst;
20#define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id])
21#define mx23_add_auart0() mx23_add_auart(0)
22#define mx23_add_auart1() mx23_add_auart(1)
23
24#define mx23_add_mxs_pwm(id) mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id)
25
26struct platform_device *__init mx23_add_mxsfb(
27 const struct mxsfb_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 33773a6333a..9d08555c4cf 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -10,11 +10,34 @@
10 */ 10 */
11#include <mach/mx28.h> 11#include <mach/mx28.h>
12#include <mach/devices-common.h> 12#include <mach/devices-common.h>
13#include <mach/mxsfb.h>
13 14
14extern const struct amba_device mx28_duart_device __initconst; 15extern const struct amba_device mx28_duart_device __initconst;
15#define mx28_add_duart() \ 16#define mx28_add_duart() \
16 mxs_add_duart(&mx28_duart_device) 17 mxs_add_duart(&mx28_duart_device)
17 18
19extern const struct mxs_auart_data mx28_auart_data[] __initconst;
20#define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id])
21#define mx28_add_auart0() mx28_add_auart(0)
22#define mx28_add_auart1() mx28_add_auart(1)
23#define mx28_add_auart2() mx28_add_auart(2)
24#define mx28_add_auart3() mx28_add_auart(3)
25#define mx28_add_auart4() mx28_add_auart(4)
26
18extern const struct mxs_fec_data mx28_fec_data[] __initconst; 27extern const struct mxs_fec_data mx28_fec_data[] __initconst;
19#define mx28_add_fec(id, pdata) \ 28#define mx28_add_fec(id, pdata) \
20 mxs_add_fec(&mx28_fec_data[id], pdata) 29 mxs_add_fec(&mx28_fec_data[id], pdata)
30
31extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
32#define mx28_add_flexcan(id, pdata) \
33 mxs_add_flexcan(&mx28_flexcan_data[id], pdata)
34#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata)
35#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata)
36
37extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
38#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
39
40#define mx28_add_mxs_pwm(id) mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id)
41
42struct platform_device *__init mx28_add_mxsfb(
43 const struct mxsfb_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index c20d54740b0..cfdb6b28470 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -66,6 +66,8 @@ struct platform_device *__init mxs_add_platform_device_dmamask(
66 ret = platform_device_add(pdev); 66 ret = platform_device_add(pdev);
67 if (ret) { 67 if (ret) {
68err: 68err:
69 if (dmamask)
70 kfree(pdev->dev.dma_mask);
69 platform_device_put(pdev); 71 platform_device_put(pdev);
70 return ERR_PTR(ret); 72 return ERR_PTR(ret);
71 } 73 }
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index cf7dc1ae575..1451ad060d8 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -2,5 +2,21 @@ config MXS_HAVE_AMBA_DUART
2 bool 2 bool
3 select ARM_AMBA 3 select ARM_AMBA
4 4
5config MXS_HAVE_PLATFORM_AUART
6 bool
7
5config MXS_HAVE_PLATFORM_FEC 8config MXS_HAVE_PLATFORM_FEC
6 bool 9 bool
10
11config MXS_HAVE_PLATFORM_FLEXCAN
12 select HAVE_CAN_FLEXCAN if CAN
13 bool
14
15config MXS_HAVE_PLATFORM_MXS_I2C
16 bool
17
18config MXS_HAVE_PLATFORM_MXS_PWM
19 bool
20
21config MXS_HAVE_PLATFORM_MXSFB
22 bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index d0a09f6934b..0d9bea30b0a 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -1,2 +1,8 @@
1obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o 1obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
2obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
3obj-y += platform-dma.o
2obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o 4obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
5obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
6obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
7obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
8obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c
new file mode 100644
index 00000000000..796606cce0c
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-auart.c
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/mx23.h>
11#include <mach/mx28.h>
12#include <mach/devices-common.h>
13
14#define mxs_auart_data_entry_single(soc, _id, hwid) \
15 { \
16 .id = _id, \
17 .iobase = soc ## _AUART ## hwid ## _BASE_ADDR, \
18 .irq = soc ## _INT_AUART ## hwid, \
19 }
20
21#define mxs_auart_data_entry(soc, _id, hwid) \
22 [_id] = mxs_auart_data_entry_single(soc, _id, hwid)
23
24#ifdef CONFIG_SOC_IMX23
25const struct mxs_auart_data mx23_auart_data[] __initconst = {
26#define mx23_auart_data_entry(_id, hwid) \
27 mxs_auart_data_entry(MX23, _id, hwid)
28 mx23_auart_data_entry(0, 1),
29 mx23_auart_data_entry(1, 2),
30};
31#endif
32
33#ifdef CONFIG_SOC_IMX28
34const struct mxs_auart_data mx28_auart_data[] __initconst = {
35#define mx28_auart_data_entry(_id) \
36 mxs_auart_data_entry(MX28, _id, _id)
37 mx28_auart_data_entry(0),
38 mx28_auart_data_entry(1),
39 mx28_auart_data_entry(2),
40 mx28_auart_data_entry(3),
41 mx28_auart_data_entry(4),
42};
43#endif
44
45struct platform_device *__init mxs_add_auart(
46 const struct mxs_auart_data *data)
47{
48 struct resource res[] = {
49 {
50 .start = data->iobase,
51 .end = data->iobase + SZ_8K - 1,
52 .flags = IORESOURCE_MEM,
53 }, {
54 .start = data->irq,
55 .end = data->irq,
56 .flags = IORESOURCE_IRQ,
57 },
58 };
59
60 return mxs_add_platform_device_dmamask("mxs-auart", data->id,
61 res, ARRAY_SIZE(res), NULL, 0,
62 DMA_BIT_MASK(32));
63}
64
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
new file mode 100644
index 00000000000..295c4424d5d
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-dma.c
@@ -0,0 +1,49 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <linux/compiler.h>
9#include <linux/err.h>
10#include <linux/init.h>
11
12#include <mach/mx23.h>
13#include <mach/mx28.h>
14#include <mach/devices-common.h>
15
16static struct platform_device *__init mxs_add_dma(const char *devid,
17 resource_size_t base)
18{
19 struct resource res[] = {
20 {
21 .start = base,
22 .end = base + SZ_8K - 1,
23 .flags = IORESOURCE_MEM,
24 }
25 };
26
27 return mxs_add_platform_device_dmamask(devid, -1,
28 res, ARRAY_SIZE(res), NULL, 0,
29 DMA_BIT_MASK(32));
30}
31
32static int __init mxs_add_mxs_dma(void)
33{
34 char *apbh = "mxs-dma-apbh";
35 char *apbx = "mxs-dma-apbx";
36
37 if (cpu_is_mx23()) {
38 mxs_add_dma(apbh, MX23_APBH_DMA_BASE_ADDR);
39 mxs_add_dma(apbx, MX23_APBX_DMA_BASE_ADDR);
40 }
41
42 if (cpu_is_mx28()) {
43 mxs_add_dma(apbh, MX28_APBH_DMA_BASE_ADDR);
44 mxs_add_dma(apbx, MX28_APBX_DMA_BASE_ADDR);
45 }
46
47 return 0;
48}
49arch_initcall(mxs_add_mxs_dma);
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
index c42dff72b46..9859cf28333 100644
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ b/arch/arm/mach-mxs/devices/platform-fec.c
@@ -45,6 +45,7 @@ struct platform_device *__init mxs_add_fec(
45 }, 45 },
46 }; 46 };
47 47
48 return mxs_add_platform_device("imx28-fec", data->id, 48 return mxs_add_platform_device_dmamask("imx28-fec", data->id,
49 res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); 49 res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
50 DMA_BIT_MASK(32));
50} 51}
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c
new file mode 100644
index 00000000000..43a6b4bae6f
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-flexcan.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright (C) 2010, 2011 Pengutronix,
3 * Marc Kleine-Budde <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/mx28.h>
11#include <mach/devices-common.h>
12
13#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \
17 .iosize = _size, \
18 .irq = soc ## _INT_CAN ## _hwid, \
19 }
20
21#define mxs_flexcan_data_entry(soc, _id, _hwid, _size) \
22 [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)
23
24#ifdef CONFIG_SOC_IMX28
25const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = {
26#define mx28_flexcan_data_entry(_id, _hwid) \
27 mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K)
28 mx28_flexcan_data_entry(0, 0),
29 mx28_flexcan_data_entry(1, 1),
30};
31#endif /* ifdef CONFIG_SOC_IMX28 */
32
33struct platform_device *__init mxs_add_flexcan(
34 const struct mxs_flexcan_data *data,
35 const struct flexcan_platform_data *pdata)
36{
37 struct resource res[] = {
38 {
39 .start = data->iobase,
40 .end = data->iobase + data->iosize - 1,
41 .flags = IORESOURCE_MEM,
42 }, {
43 .start = data->irq,
44 .end = data->irq,
45 .flags = IORESOURCE_IRQ,
46 },
47 };
48
49 return mxs_add_platform_device("flexcan", data->id,
50 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
51}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
new file mode 100644
index 00000000000..eab3a06836d
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright (C) 2011 Pengutronix
3 * Wolfram Sang <w.sang@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/mx28.h>
11#include <mach/devices-common.h>
12
13#define mxs_i2c_data_entry_single(soc, _id) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _I2C ## _id ## _BASE_ADDR, \
17 .errirq = soc ## _INT_I2C ## _id ## _ERROR, \
18 .dmairq = soc ## _INT_I2C ## _id ## _DMA, \
19 }
20
21#define mxs_i2c_data_entry(soc, _id) \
22 [_id] = mxs_i2c_data_entry_single(soc, _id)
23
24#ifdef CONFIG_SOC_IMX28
25const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
26 mxs_i2c_data_entry(MX28, 0),
27 mxs_i2c_data_entry(MX28, 1),
28};
29#endif
30
31struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data)
32{
33 struct resource res[] = {
34 {
35 .start = data->iobase,
36 .end = data->iobase + SZ_8K - 1,
37 .flags = IORESOURCE_MEM,
38 }, {
39 .start = data->errirq,
40 .end = data->errirq,
41 .flags = IORESOURCE_IRQ,
42 }, {
43 .start = data->dmairq,
44 .end = data->dmairq,
45 .flags = IORESOURCE_IRQ,
46 },
47 };
48
49 return mxs_add_platform_device("mxs-i2c", data->id, res,
50 ARRAY_SIZE(res), NULL, 0);
51}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
new file mode 100644
index 00000000000..680f5a90293
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/devices-common.h>
11
12struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id)
13{
14 struct resource res = {
15 .flags = IORESOURCE_MEM,
16 };
17
18 res.start = iobase + 0x10 + 0x20 * id;
19 res.end = res.start + 0x1f;
20
21 return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0);
22}
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
new file mode 100644
index 00000000000..bf72c9b8dbd
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c
@@ -0,0 +1,46 @@
1/*
2 * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <asm/sizes.h>
9#include <mach/mx23.h>
10#include <mach/mx28.h>
11#include <mach/devices-common.h>
12#include <mach/mxsfb.h>
13
14#ifdef CONFIG_SOC_IMX23
15struct platform_device *__init mx23_add_mxsfb(
16 const struct mxsfb_platform_data *pdata)
17{
18 struct resource res[] = {
19 {
20 .start = MX23_LCDIF_BASE_ADDR,
21 .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1,
22 .flags = IORESOURCE_MEM,
23 },
24 };
25
26 return mxs_add_platform_device_dmamask("imx23-fb", -1,
27 res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
28}
29#endif /* ifdef CONFIG_SOC_IMX23 */
30
31#ifdef CONFIG_SOC_IMX28
32struct platform_device *__init mx28_add_mxsfb(
33 const struct mxsfb_platform_data *pdata)
34{
35 struct resource res[] = {
36 {
37 .start = MX28_LCDIF_BASE_ADDR,
38 .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1,
39 .flags = IORESOURCE_MEM,
40 },
41 };
42
43 return mxs_add_platform_device_dmamask("imx28-fb", -1,
44 res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
45}
46#endif /* ifdef CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
index cb0c0e83a52..5120ab58707 100644
--- a/arch/arm/mach-mxs/gpio.c
+++ b/arch/arm/mach-mxs/gpio.c
@@ -182,6 +182,7 @@ static int mxs_gpio_set_wake_irq(u32 irq, u32 enable)
182} 182}
183 183
184static struct irq_chip gpio_irq_chip = { 184static struct irq_chip gpio_irq_chip = {
185 .name = "mxs gpio",
185 .ack = mxs_gpio_ack_irq, 186 .ack = mxs_gpio_ack_irq,
186 .mask = mxs_gpio_mask_irq, 187 .mask = mxs_gpio_mask_irq,
187 .unmask = mxs_gpio_unmask_irq, 188 .unmask = mxs_gpio_unmask_irq,
@@ -289,39 +290,42 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
289 return 0; 290 return 0;
290} 291}
291 292
292#define DEFINE_MXS_GPIO_PORT(soc, _id) \ 293#define MX23_GPIO_BASE MX23_IO_ADDRESS(MX23_PINCTRL_BASE_ADDR)
294#define MX28_GPIO_BASE MX28_IO_ADDRESS(MX28_PINCTRL_BASE_ADDR)
295
296#define DEFINE_MXS_GPIO_PORT(_base, _irq, _id) \
293 { \ 297 { \
294 .chip.label = "gpio-" #_id, \ 298 .chip.label = "gpio-" #_id, \
295 .id = _id, \ 299 .id = _id, \
296 .irq = soc ## _INT_GPIO ## _id, \ 300 .irq = _irq, \
297 .base = soc ## _IO_ADDRESS( \ 301 .base = _base, \
298 soc ## _PINCTRL ## _BASE_ADDR), \
299 .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \ 302 .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \
300 } 303 }
301 304
302#define DEFINE_REGISTER_FUNCTION(prefix) \
303int __init prefix ## _register_gpios(void) \
304{ \
305 return mxs_gpio_init(prefix ## _gpio_ports, \
306 ARRAY_SIZE(prefix ## _gpio_ports)); \
307}
308
309#ifdef CONFIG_SOC_IMX23 305#ifdef CONFIG_SOC_IMX23
310static struct mxs_gpio_port mx23_gpio_ports[] = { 306static struct mxs_gpio_port mx23_gpio_ports[] = {
311 DEFINE_MXS_GPIO_PORT(MX23, 0), 307 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO0, 0),
312 DEFINE_MXS_GPIO_PORT(MX23, 1), 308 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO1, 1),
313 DEFINE_MXS_GPIO_PORT(MX23, 2), 309 DEFINE_MXS_GPIO_PORT(MX23_GPIO_BASE, MX23_INT_GPIO2, 2),
314}; 310};
315DEFINE_REGISTER_FUNCTION(mx23) 311
312int __init mx23_register_gpios(void)
313{
314 return mxs_gpio_init(mx23_gpio_ports, ARRAY_SIZE(mx23_gpio_ports));
315}
316#endif 316#endif
317 317
318#ifdef CONFIG_SOC_IMX28 318#ifdef CONFIG_SOC_IMX28
319static struct mxs_gpio_port mx28_gpio_ports[] = { 319static struct mxs_gpio_port mx28_gpio_ports[] = {
320 DEFINE_MXS_GPIO_PORT(MX28, 0), 320 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO0, 0),
321 DEFINE_MXS_GPIO_PORT(MX28, 1), 321 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO1, 1),
322 DEFINE_MXS_GPIO_PORT(MX28, 2), 322 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO2, 2),
323 DEFINE_MXS_GPIO_PORT(MX28, 3), 323 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO3, 3),
324 DEFINE_MXS_GPIO_PORT(MX28, 4), 324 DEFINE_MXS_GPIO_PORT(MX28_GPIO_BASE, MX28_INT_GPIO4, 4),
325}; 325};
326DEFINE_REGISTER_FUNCTION(mx28) 326
327int __init mx28_register_gpios(void)
328{
329 return mxs_gpio_init(mx28_gpio_ports, ARRAY_SIZE(mx28_gpio_ports));
330}
327#endif 331#endif
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 59133eb3cc9..635bb5d9a20 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -13,6 +13,7 @@
13 13
14struct clk; 14struct clk;
15 15
16extern const u32 *mxs_get_ocotp(void);
16extern int mxs_reset_block(void __iomem *); 17extern int mxs_reset_block(void __iomem *);
17extern void mxs_timer_init(struct clk *, int); 18extern void mxs_timer_init(struct clk *, int);
18 19
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 6c3d1a10343..71f24484b04 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -30,6 +30,16 @@ int __init mxs_add_amba_device(const struct amba_device *dev);
30/* duart */ 30/* duart */
31int __init mxs_add_duart(const struct amba_device *dev); 31int __init mxs_add_duart(const struct amba_device *dev);
32 32
33/* auart */
34struct mxs_auart_data {
35 int id;
36 resource_size_t iobase;
37 resource_size_t iosize;
38 resource_size_t irq;
39};
40struct platform_device *__init mxs_add_auart(
41 const struct mxs_auart_data *data);
42
33/* fec */ 43/* fec */
34#include <linux/fec.h> 44#include <linux/fec.h>
35struct mxs_fec_data { 45struct mxs_fec_data {
@@ -41,3 +51,28 @@ struct mxs_fec_data {
41struct platform_device *__init mxs_add_fec( 51struct platform_device *__init mxs_add_fec(
42 const struct mxs_fec_data *data, 52 const struct mxs_fec_data *data,
43 const struct fec_platform_data *pdata); 53 const struct fec_platform_data *pdata);
54
55/* flexcan */
56#include <linux/can/platform/flexcan.h>
57struct mxs_flexcan_data {
58 int id;
59 resource_size_t iobase;
60 resource_size_t iosize;
61 resource_size_t irq;
62};
63struct platform_device *__init mxs_add_flexcan(
64 const struct mxs_flexcan_data *data,
65 const struct flexcan_platform_data *pdata);
66
67/* i2c */
68struct mxs_i2c_data {
69 int id;
70 resource_size_t iobase;
71 resource_size_t errirq;
72 resource_size_t dmairq;
73};
74struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data);
75
76/* pwm */
77struct platform_device *__init mxs_add_mxs_pwm(
78 resource_size_t iobase, int id);
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
index 94e5dd83cdb..b0190a4822f 100644
--- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
@@ -254,102 +254,102 @@
254#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) 254#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2)
255 255
256/* MUXSEL_GPIO */ 256/* MUXSEL_GPIO */
257#define MX23_PAD_GPMI_D00__GPO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) 257#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO)
258#define MX23_PAD_GPMI_D01__GPO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) 258#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO)
259#define MX23_PAD_GPMI_D02__GPO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) 259#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO)
260#define MX23_PAD_GPMI_D03__GPO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) 260#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO)
261#define MX23_PAD_GPMI_D04__GPO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) 261#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO)
262#define MX23_PAD_GPMI_D05__GPO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) 262#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO)
263#define MX23_PAD_GPMI_D06__GPO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) 263#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO)
264#define MX23_PAD_GPMI_D07__GPO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) 264#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO)
265#define MX23_PAD_GPMI_D08__GPO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) 265#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO)
266#define MX23_PAD_GPMI_D09__GPO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) 266#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO)
267#define MX23_PAD_GPMI_D10__GPO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) 267#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
268#define MX23_PAD_GPMI_D11__GPO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) 268#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
269#define MX23_PAD_GPMI_D12__GPO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) 269#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
270#define MX23_PAD_GPMI_D13__GPO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) 270#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
271#define MX23_PAD_GPMI_D14__GPO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) 271#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
272#define MX23_PAD_GPMI_D15__GPO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) 272#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
273#define MX23_PAD_GPMI_CLE__GPO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) 273#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
274#define MX23_PAD_GPMI_ALE__GPO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) 274#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
275#define MX23_PAD_GPMI_CE2N__GPO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) 275#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
276#define MX23_PAD_GPMI_RDY0__GPO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) 276#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
277#define MX23_PAD_GPMI_RDY1__GPO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) 277#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
278#define MX23_PAD_GPMI_RDY2__GPO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) 278#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
279#define MX23_PAD_GPMI_RDY3__GPO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) 279#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
280#define MX23_PAD_GPMI_WPN__GPO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) 280#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
281#define MX23_PAD_GPMI_WRN__GPO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) 281#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
282#define MX23_PAD_GPMI_RDN__GPO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) 282#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
283#define MX23_PAD_AUART1_CTS__GPO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) 283#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
284#define MX23_PAD_AUART1_RTS__GPO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) 284#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
285#define MX23_PAD_AUART1_RX__GPO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) 285#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
286#define MX23_PAD_AUART1_TX__GPO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) 286#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
287#define MX23_PAD_I2C_SCL__GPO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) 287#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
288#define MX23_PAD_I2C_SDA__GPO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) 288#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
289 289
290#define MX23_PAD_LCD_D00__GPO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) 290#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO)
291#define MX23_PAD_LCD_D01__GPO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) 291#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO)
292#define MX23_PAD_LCD_D02__GPO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) 292#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO)
293#define MX23_PAD_LCD_D03__GPO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) 293#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO)
294#define MX23_PAD_LCD_D04__GPO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) 294#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO)
295#define MX23_PAD_LCD_D05__GPO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) 295#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO)
296#define MX23_PAD_LCD_D06__GPO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) 296#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO)
297#define MX23_PAD_LCD_D07__GPO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) 297#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO)
298#define MX23_PAD_LCD_D08__GPO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) 298#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO)
299#define MX23_PAD_LCD_D09__GPO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) 299#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO)
300#define MX23_PAD_LCD_D10__GPO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) 300#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
301#define MX23_PAD_LCD_D11__GPO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) 301#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
302#define MX23_PAD_LCD_D12__GPO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) 302#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
303#define MX23_PAD_LCD_D13__GPO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) 303#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
304#define MX23_PAD_LCD_D14__GPO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) 304#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
305#define MX23_PAD_LCD_D15__GPO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) 305#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
306#define MX23_PAD_LCD_D16__GPO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) 306#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
307#define MX23_PAD_LCD_D17__GPO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) 307#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
308#define MX23_PAD_LCD_RESET__GPO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) 308#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
309#define MX23_PAD_LCD_RS__GPO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) 309#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
310#define MX23_PAD_LCD_WR__GPO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) 310#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
311#define MX23_PAD_LCD_CS__GPO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) 311#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
312#define MX23_PAD_LCD_DOTCK__GPO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) 312#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
313#define MX23_PAD_LCD_ENABLE__GPO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) 313#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
314#define MX23_PAD_LCD_HSYNC__GPO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) 314#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
315#define MX23_PAD_LCD_VSYNC__GPO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) 315#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
316#define MX23_PAD_PWM0__GPO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) 316#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
317#define MX23_PAD_PWM1__GPO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) 317#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
318#define MX23_PAD_PWM2__GPO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) 318#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
319#define MX23_PAD_PWM3__GPO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) 319#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
320#define MX23_PAD_PWM4__GPO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) 320#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
321 321
322#define MX23_PAD_SSP1_CMD__GPO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) 322#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO)
323#define MX23_PAD_SSP1_DETECT__GPO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) 323#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO)
324#define MX23_PAD_SSP1_DATA0__GPO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) 324#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO)
325#define MX23_PAD_SSP1_DATA1__GPO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) 325#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO)
326#define MX23_PAD_SSP1_DATA2__GPO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) 326#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO)
327#define MX23_PAD_SSP1_DATA3__GPO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) 327#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO)
328#define MX23_PAD_SSP1_SCK__GPO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) 328#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO)
329#define MX23_PAD_ROTARYA__GPO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) 329#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO)
330#define MX23_PAD_ROTARYB__GPO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) 330#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO)
331#define MX23_PAD_EMI_A00__GPO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) 331#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO)
332#define MX23_PAD_EMI_A01__GPO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) 332#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
333#define MX23_PAD_EMI_A02__GPO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) 333#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
334#define MX23_PAD_EMI_A03__GPO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) 334#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
335#define MX23_PAD_EMI_A04__GPO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) 335#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
336#define MX23_PAD_EMI_A05__GPO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) 336#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
337#define MX23_PAD_EMI_A06__GPO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) 337#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
338#define MX23_PAD_EMI_A07__GPO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) 338#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
339#define MX23_PAD_EMI_A08__GPO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) 339#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
340#define MX23_PAD_EMI_A09__GPO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) 340#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
341#define MX23_PAD_EMI_A10__GPO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) 341#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
342#define MX23_PAD_EMI_A11__GPO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) 342#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
343#define MX23_PAD_EMI_A12__GPO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) 343#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
344#define MX23_PAD_EMI_BA0__GPO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) 344#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
345#define MX23_PAD_EMI_BA1__GPO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) 345#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
346#define MX23_PAD_EMI_CASN__GPO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) 346#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
347#define MX23_PAD_EMI_CE0N__GPO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) 347#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
348#define MX23_PAD_EMI_CE1N__GPO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) 348#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
349#define MX23_PAD_GPMI_CE1N__GPO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) 349#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
350#define MX23_PAD_GPMI_CE0N__GPO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) 350#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
351#define MX23_PAD_EMI_CKE__GPO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) 351#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
352#define MX23_PAD_EMI_RASN__GPO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) 352#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
353#define MX23_PAD_EMI_WEN__GPO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) 353#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
354 354
355#endif /* __MACH_IOMUX_MX23_H__ */ 355#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
index fe558e3c5a9..7abdf58b8bb 100644
--- a/arch/arm/mach-mxs/include/mach/iomux.h
+++ b/arch/arm/mach-mxs/include/mach/iomux.h
@@ -91,6 +91,9 @@ typedef u32 iomux_cfg_t;
91#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ 91#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
92 MXS_PAD_PULL_VALID_MASK) 92 MXS_PAD_PULL_VALID_MASK)
93 93
94/* generic pad control used in most cases */
95#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
96
94#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ 97#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \
95 (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ 98 (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \
96 ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ 99 ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
index 9edd02ec8e3..c0a18c23084 100644
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -93,7 +93,7 @@
93#define MX23_INT_USB_WAKEUP 12 93#define MX23_INT_USB_WAKEUP 12
94#define MX23_INT_GPMI_DMA 13 94#define MX23_INT_GPMI_DMA 13
95#define MX23_INT_SSP1_DMA 14 95#define MX23_INT_SSP1_DMA 14
96#define MX23_INT_SSP_ERROR 15 96#define MX23_INT_SSP1_ERROR 15
97#define MX23_INT_GPIO0 16 97#define MX23_INT_GPIO0 16
98#define MX23_INT_GPIO1 17 98#define MX23_INT_GPIO1 17
99#define MX23_INT_GPIO2 18 99#define MX23_INT_GPIO2 18
@@ -101,9 +101,9 @@
101#define MX23_INT_SSP2_DMA 20 101#define MX23_INT_SSP2_DMA 20
102#define MX23_INT_ECC8_IRQ 21 102#define MX23_INT_ECC8_IRQ 21
103#define MX23_INT_RTC_ALARM 22 103#define MX23_INT_RTC_ALARM 22
104#define MX23_INT_UARTAPP_TX_DMA 23 104#define MX23_INT_AUART1_TX_DMA 23
105#define MX23_INT_UARTAPP_INTERNAL 24 105#define MX23_INT_AUART1 24
106#define MX23_INT_UARTAPP_RX_DMA 25 106#define MX23_INT_AUART1_RX_DMA 25
107#define MX23_INT_I2C_DMA 26 107#define MX23_INT_I2C_DMA 26
108#define MX23_INT_I2C_ERROR 27 108#define MX23_INT_I2C_ERROR 27
109#define MX23_INT_TIMER0 28 109#define MX23_INT_TIMER0 28
@@ -135,11 +135,35 @@
135#define MX23_INT_DCP 54 135#define MX23_INT_DCP 54
136#define MX23_INT_BCH 56 136#define MX23_INT_BCH 56
137#define MX23_INT_PXP 57 137#define MX23_INT_PXP 57
138#define MX23_INT_UARTAPP2_TX_DMA 58 138#define MX23_INT_AUART2_TX_DMA 58
139#define MX23_INT_UARTAPP2_INTERNAL 59 139#define MX23_INT_AUART2 59
140#define MX23_INT_UARTAPP2_RX_DMA 60 140#define MX23_INT_AUART2_RX_DMA 60
141#define MX23_INT_VDAC_DETECT 61 141#define MX23_INT_VDAC_DETECT 61
142#define MX23_INT_VDD5V_DROOP 64 142#define MX23_INT_VDD5V_DROOP 64
143#define MX23_INT_DCDC4P2_BO 65 143#define MX23_INT_DCDC4P2_BO 65
144 144
145/*
146 * APBH DMA
147 */
148#define MX23_DMA_SSP1 1
149#define MX23_DMA_SSP2 2
150#define MX23_DMA_GPMI0 4
151#define MX23_DMA_GPMI1 5
152#define MX23_DMA_GPMI2 6
153#define MX23_DMA_GPMI3 7
154
155/*
156 * APBX DMA
157 */
158#define MX23_DMA_ADC 0
159#define MX23_DMA_DAC 1
160#define MX23_DMA_SPDIF 2
161#define MX23_DMA_I2C 3
162#define MX23_DMA_SAIF0 4
163#define MX23_DMA_UART0_RX 6
164#define MX23_DMA_UART0_TX 7
165#define MX23_DMA_UART1_RX 8
166#define MX23_DMA_UART1_TX 9
167#define MX23_DMA_SAIF1 10
168
145#endif /* __MACH_MX23_H__ */ 169#endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
index 0716745267a..75d86118b76 100644
--- a/arch/arm/mach-mxs/include/mach/mx28.h
+++ b/arch/arm/mach-mxs/include/mach/mx28.h
@@ -163,10 +163,10 @@
163#define MX28_INT_USB0 93 163#define MX28_INT_USB0 93
164#define MX28_INT_USB1_WAKEUP 94 164#define MX28_INT_USB1_WAKEUP 94
165#define MX28_INT_USB0_WAKEUP 95 165#define MX28_INT_USB0_WAKEUP 95
166#define MX28_INT_SSP0 96 166#define MX28_INT_SSP0_ERROR 96
167#define MX28_INT_SSP1 97 167#define MX28_INT_SSP1_ERROR 97
168#define MX28_INT_SSP2 98 168#define MX28_INT_SSP2_ERROR 98
169#define MX28_INT_SSP3 99 169#define MX28_INT_SSP3_ERROR 99
170#define MX28_INT_ENET_SWI 100 170#define MX28_INT_ENET_SWI 100
171#define MX28_INT_ENET_MAC0 101 171#define MX28_INT_ENET_MAC0 101
172#define MX28_INT_ENET_MAC1 102 172#define MX28_INT_ENET_MAC1 102
@@ -185,4 +185,41 @@
185#define MX28_INT_GPIO1 126 185#define MX28_INT_GPIO1 126
186#define MX28_INT_GPIO0 127 186#define MX28_INT_GPIO0 127
187 187
188/*
189 * APBH DMA
190 */
191#define MX28_DMA_SSP0 0
192#define MX28_DMA_SSP1 1
193#define MX28_DMA_SSP2 2
194#define MX28_DMA_SSP3 3
195#define MX28_DMA_GPMI0 4
196#define MX28_DMA_GPMI1 5
197#define MX28_DMA_GPMI2 6
198#define MX28_DMA_GPMI3 7
199#define MX28_DMA_GPMI4 8
200#define MX28_DMA_GPMI5 9
201#define MX28_DMA_GPMI6 10
202#define MX28_DMA_GPMI7 11
203#define MX28_DMA_HSADC 12
204#define MX28_DMA_LCDIF 13
205
206/*
207 * APBX DMA
208 */
209#define MX28_DMA_AUART4_RX 0
210#define MX28_DMA_AUART4_TX 1
211#define MX28_DMA_SPDIF_TX 2
212#define MX28_DMA_SAIF0 4
213#define MX28_DMA_SAIF1 5
214#define MX28_DMA_I2C0 6
215#define MX28_DMA_I2C1 7
216#define MX28_DMA_AUART0_RX 8
217#define MX28_DMA_AUART0_TX 9
218#define MX28_DMA_AUART1_RX 10
219#define MX28_DMA_AUART1_TX 11
220#define MX28_DMA_AUART2_RX 12
221#define MX28_DMA_AUART2_TX 13
222#define MX28_DMA_AUART3_RX 14
223#define MX28_DMA_AUART3_TX 15
224
188#endif /* __MACH_MX28_H__ */ 225#endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
index f186c08c291..35a89dd2724 100644
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -28,8 +28,13 @@
28/* 28/*
29 * MXS CPU types 29 * MXS CPU types
30 */ 30 */
31#define cpu_is_mx23() (machine_is_mx23evk()) 31#define cpu_is_mx23() ( \
32#define cpu_is_mx28() (machine_is_mx28evk()) 32 machine_is_mx23evk() || \
33 0)
34#define cpu_is_mx28() ( \
35 machine_is_mx28evk() || \
36 machine_is_tx28() || \
37 0)
33 38
34/* 39/*
35 * IO addresses common to MXS-based 40 * IO addresses common to MXS-based
diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h
new file mode 100644
index 00000000000..e4d79791515
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mxsfb.h
@@ -0,0 +1,49 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
14 * MA 02110-1301, USA.
15 */
16
17#ifndef __MACH_FB_H
18#define __MACH_FB_H
19
20#include <linux/fb.h>
21
22#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */
23#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
24#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
25#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
26
27#define FB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
28#define FB_SYNC_DOTCLK_FAILING_ACT (1 << 7) /* failing/negtive edge sampling */
29
30struct mxsfb_platform_data {
31 struct fb_videomode *mode_list;
32 unsigned mode_count;
33
34 unsigned default_bpp;
35
36 unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */
37 unsigned ld_intf_width; /* refer STMLCDIF_* macros */
38
39 unsigned fb_size; /* Size of the video memory. If zero a
40 * default will be used
41 */
42 unsigned long fb_phys; /* physical address for the video memory. If
43 * zero the framebuffer memory will be dynamically
44 * allocated. If specified,fb_size must also be specified.
45 * fb_phys must be unused by Linux.
46 */
47};
48
49#endif /* __MACH_FB_H */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index a005e76f34f..f12a1732d8b 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -63,6 +63,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
63 mxs_duart_base = MX23_DUART_BASE_ADDR; 63 mxs_duart_base = MX23_DUART_BASE_ADDR;
64 break; 64 break;
65 case MACH_TYPE_MX28EVK: 65 case MACH_TYPE_MX28EVK:
66 case MACH_TYPE_TX28:
66 mxs_duart_base = MX28_DUART_BASE_ADDR; 67 mxs_duart_base = MX28_DUART_BASE_ADDR;
67 break; 68 break;
68 default: 69 default:
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index aa0640052f5..a66994f0518 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -26,17 +26,103 @@
26 26
27#include "devices-mx23.h" 27#include "devices-mx23.h"
28 28
29#define MX23EVK_LCD_ENABLE MXS_GPIO_NR(1, 18)
30#define MX23EVK_BL_ENABLE MXS_GPIO_NR(1, 28)
31
29static const iomux_cfg_t mx23evk_pads[] __initconst = { 32static const iomux_cfg_t mx23evk_pads[] __initconst = {
30 /* duart */ 33 /* duart */
31 MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA, 34 MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
32 MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA, 35 MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
36
37 /* auart */
38 MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
39 MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
40 MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL,
41 MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL,
42
43 /* mxsfb (lcdif) */
44 MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL,
45 MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL,
46 MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL,
47 MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL,
48 MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL,
49 MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL,
50 MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL,
51 MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL,
52 MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL,
53 MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL,
54 MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
55 MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
56 MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
57 MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
58 MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
59 MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
60 MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
61 MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
62 MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL,
63 MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL,
64 MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL,
65 MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL,
66 MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL,
67 MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL,
68 MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
69 MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
70 MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL,
71 MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
72 /* LCD panel enable */
73 MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL,
74 /* backlight control */
75 MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL,
76};
77
78/* mxsfb (lcdif) */
79static struct fb_videomode mx23evk_video_modes[] = {
80 {
81 .name = "Samsung-LMS430HF02",
82 .refresh = 60,
83 .xres = 480,
84 .yres = 272,
85 .pixclock = 108096, /* picosecond (9.2 MHz) */
86 .left_margin = 15,
87 .right_margin = 8,
88 .upper_margin = 12,
89 .lower_margin = 4,
90 .hsync_len = 1,
91 .vsync_len = 1,
92 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT |
93 FB_SYNC_DOTCLK_FAILING_ACT,
94 },
95};
96
97static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = {
98 .mode_list = mx23evk_video_modes,
99 .mode_count = ARRAY_SIZE(mx23evk_video_modes),
100 .default_bpp = 32,
101 .ld_intf_width = STMLCDIF_24BIT,
33}; 102};
34 103
35static void __init mx23evk_init(void) 104static void __init mx23evk_init(void)
36{ 105{
106 int ret;
107
37 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads)); 108 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
38 109
39 mx23_add_duart(); 110 mx23_add_duart();
111 mx23_add_auart0();
112
113 ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
114 if (ret)
115 pr_warn("failed to request gpio lcd-enable: %d\n", ret);
116 else
117 gpio_set_value(MX23EVK_LCD_ENABLE, 1);
118
119 ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
120 if (ret)
121 pr_warn("failed to request gpio bl-enable: %d\n", ret);
122 else
123 gpio_set_value(MX23EVK_BL_ENABLE, 1);
124
125 mx23_add_mxsfb(&mx23evk_mxsfb_pdata);
40} 126}
41 127
42static void __init mx23evk_timer_init(void) 128static void __init mx23evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 8e2c5975001..08002d02267 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -28,54 +28,93 @@
28#include "devices-mx28.h" 28#include "devices-mx28.h"
29#include "gpio.h" 29#include "gpio.h"
30 30
31#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
31#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15) 32#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15)
33#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18)
34#define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30)
32#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13) 35#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
33 36
34static const iomux_cfg_t mx28evk_pads[] __initconst = { 37static const iomux_cfg_t mx28evk_pads[] __initconst = {
35 /* duart */ 38 /* duart */
36 MX28_PAD_PWM0__DUART_RX | 39 MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
37 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 40 MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
38 MX28_PAD_PWM1__DUART_TX |
39 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
40 41
42 /* auart0 */
43 MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
44 MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
45 MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
46 MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
47 /* auart3 */
48 MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
49 MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
50 MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
51 MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
52
53#define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
41 /* fec0 */ 54 /* fec0 */
42 MX28_PAD_ENET0_MDC__ENET0_MDC | 55 MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
43 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 56 MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
44 MX28_PAD_ENET0_MDIO__ENET0_MDIO | 57 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
45 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 58 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
46 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | 59 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
47 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 60 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
48 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | 61 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
49 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 62 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
50 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | 63 MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
51 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
52 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN |
53 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
54 MX28_PAD_ENET0_TXD0__ENET0_TXD0 |
55 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
56 MX28_PAD_ENET0_TXD1__ENET0_TXD1 |
57 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
58 MX28_PAD_ENET_CLK__CLKCTRL_ENET |
59 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
60 /* fec1 */ 64 /* fec1 */
61 MX28_PAD_ENET0_CRS__ENET1_RX_EN | 65 MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
62 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 66 MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
63 MX28_PAD_ENET0_RXD2__ENET1_RXD0 | 67 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
64 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 68 MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
65 MX28_PAD_ENET0_RXD3__ENET1_RXD1 | 69 MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
66 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), 70 MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
67 MX28_PAD_ENET0_COL__ENET1_TX_EN |
68 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
69 MX28_PAD_ENET0_TXD2__ENET1_TXD0 |
70 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
71 MX28_PAD_ENET0_TXD3__ENET1_TXD1 |
72 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
73 /* phy power line */ 71 /* phy power line */
74 MX28_PAD_SSP1_DATA3__GPIO_2_15 | 72 MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL,
75 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
76 /* phy reset line */ 73 /* phy reset line */
77 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | 74 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL,
78 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), 75
76 /* flexcan0 */
77 MX28_PAD_GPMI_RDY2__CAN0_TX,
78 MX28_PAD_GPMI_RDY3__CAN0_RX,
79 /* flexcan1 */
80 MX28_PAD_GPMI_CE2N__CAN1_TX,
81 MX28_PAD_GPMI_CE3N__CAN1_RX,
82 /* transceiver power control */
83 MX28_PAD_SSP1_CMD__GPIO_2_13,
84
85 /* mxsfb (lcdif) */
86 MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
87 MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
88 MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
89 MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
90 MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
91 MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
92 MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
93 MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
94 MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
95 MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
96 MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
97 MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
98 MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
99 MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
100 MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
101 MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
102 MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
103 MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
104 MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
105 MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
106 MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
107 MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
108 MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
109 MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
110 MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
111 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
112 MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
113 MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL,
114 /* LCD panel enable */
115 MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
116 /* backlight control */
117 MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL,
79}; 118};
80 119
81/* fec */ 120/* fec */
@@ -119,7 +158,7 @@ static void __init mx28evk_fec_reset(void)
119 gpio_set_value(MX28EVK_FEC_PHY_RESET, 1); 158 gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
120} 159}
121 160
122static struct fec_platform_data mx28_fec_pdata[] = { 161static struct fec_platform_data mx28_fec_pdata[] __initdata = {
123 { 162 {
124 /* fec0 */ 163 /* fec0 */
125 .phy = PHY_INTERFACE_MODE_RMII, 164 .phy = PHY_INTERFACE_MODE_RMII,
@@ -129,15 +168,135 @@ static struct fec_platform_data mx28_fec_pdata[] = {
129 }, 168 },
130}; 169};
131 170
171static int __init mx28evk_fec_get_mac(void)
172{
173 int i;
174 u32 val;
175 const u32 *ocotp = mxs_get_ocotp();
176
177 if (!ocotp)
178 goto error;
179
180 /*
181 * OCOTP only stores the last 4 octets for each mac address,
182 * so hard-code Freescale OUI (00:04:9f) here.
183 */
184 for (i = 0; i < 2; i++) {
185 val = ocotp[i * 4];
186 mx28_fec_pdata[i].mac[0] = 0x00;
187 mx28_fec_pdata[i].mac[1] = 0x04;
188 mx28_fec_pdata[i].mac[2] = 0x9f;
189 mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
190 mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
191 mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
192 }
193
194 return 0;
195
196error:
197 pr_err("%s: timeout when reading fec mac from OCOTP\n", __func__);
198 return -ETIMEDOUT;
199}
200
201/*
202 * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
203 */
204static int flexcan0_en, flexcan1_en;
205
206static void mx28evk_flexcan_switch(void)
207{
208 if (flexcan0_en || flexcan1_en)
209 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
210 else
211 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
212}
213
214static void mx28evk_flexcan0_switch(int enable)
215{
216 flexcan0_en = enable;
217 mx28evk_flexcan_switch();
218}
219
220static void mx28evk_flexcan1_switch(int enable)
221{
222 flexcan1_en = enable;
223 mx28evk_flexcan_switch();
224}
225
226static const struct flexcan_platform_data
227 mx28evk_flexcan_pdata[] __initconst = {
228 {
229 .transceiver_switch = mx28evk_flexcan0_switch,
230 }, {
231 .transceiver_switch = mx28evk_flexcan1_switch,
232 }
233};
234
235/* mxsfb (lcdif) */
236static struct fb_videomode mx28evk_video_modes[] = {
237 {
238 .name = "Seiko-43WVF1G",
239 .refresh = 60,
240 .xres = 800,
241 .yres = 480,
242 .pixclock = 29851, /* picosecond (33.5 MHz) */
243 .left_margin = 89,
244 .right_margin = 164,
245 .upper_margin = 23,
246 .lower_margin = 10,
247 .hsync_len = 10,
248 .vsync_len = 10,
249 .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT |
250 FB_SYNC_DOTCLK_FAILING_ACT,
251 },
252};
253
254static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = {
255 .mode_list = mx28evk_video_modes,
256 .mode_count = ARRAY_SIZE(mx28evk_video_modes),
257 .default_bpp = 32,
258 .ld_intf_width = STMLCDIF_24BIT,
259};
260
132static void __init mx28evk_init(void) 261static void __init mx28evk_init(void)
133{ 262{
263 int ret;
264
134 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads)); 265 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
135 266
136 mx28_add_duart(); 267 mx28_add_duart();
268 mx28_add_auart0();
269 mx28_add_auart3();
270
271 if (mx28evk_fec_get_mac())
272 pr_warn("%s: failed on fec mac setup\n", __func__);
137 273
138 mx28evk_fec_reset(); 274 mx28evk_fec_reset();
139 mx28_add_fec(0, &mx28_fec_pdata[0]); 275 mx28_add_fec(0, &mx28_fec_pdata[0]);
140 mx28_add_fec(1, &mx28_fec_pdata[1]); 276 mx28_add_fec(1, &mx28_fec_pdata[1]);
277
278 ret = gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
279 "flexcan-switch");
280 if (ret) {
281 pr_err("failed to request gpio flexcan-switch: %d\n", ret);
282 } else {
283 mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
284 mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
285 }
286
287 ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
288 if (ret)
289 pr_warn("failed to request gpio lcd-enable: %d\n", ret);
290 else
291 gpio_set_value(MX28EVK_LCD_ENABLE, 1);
292
293 ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
294 if (ret)
295 pr_warn("failed to request gpio bl-enable: %d\n", ret);
296 else
297 gpio_set_value(MX28EVK_BL_ENABLE, 1);
298
299 mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
141} 300}
142 301
143static void __init mx28evk_timer_init(void) 302static void __init mx28evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
new file mode 100644
index 00000000000..b65e3719cbc
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -0,0 +1,183 @@
1/*
2 * Copyright (C) 2010 <LW@KARO-electronics.de>
3 *
4 * based on: mach-mx28_evk.c
5 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation
10 */
11#include <linux/kernel.h>
12#include <linux/gpio.h>
13#include <linux/leds.h>
14#include <linux/platform_device.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/spi_gpio.h>
17#include <linux/i2c.h>
18
19#include <asm/mach/arch.h>
20#include <asm/mach/time.h>
21
22#include <mach/common.h>
23#include <mach/iomux-mx28.h>
24
25#include "devices-mx28.h"
26#include "module-tx28.h"
27
28#define TX28_STK5_GPIO_LED MXS_GPIO_NR(4, 10)
29
30static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
31 /* LED */
32 MX28_PAD_ENET0_RXD3__GPIO_4_10 |
33 MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL,
34
35 /* framebuffer */
36#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA)
37 MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE,
38 MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE,
39 MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE,
40 MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE,
41 MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE,
42 MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE,
43 MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE,
44 MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE,
45 MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE,
46 MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE,
47 MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE,
48 MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE,
49 MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE,
50 MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE,
51 MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE,
52 MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE,
53 MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE,
54 MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE,
55 MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE,
56 MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE,
57 MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE,
58 MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE,
59 MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE,
60 MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE,
61 MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE,
62 MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE,
63 MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE,
64 MX28_PAD_LCD_CS__LCD_CS | LCD_MODE,
65 MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE,
66 MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE,
67 MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE,
68 MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE,
69 MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE,
70 MX28_PAD_PWM0__PWM_0 | LCD_MODE,
71
72 /* UART1 */
73 MX28_PAD_AUART0_CTS__DUART_RX,
74 MX28_PAD_AUART0_RTS__DUART_TX,
75 MX28_PAD_AUART0_TX__DUART_RTS,
76 MX28_PAD_AUART0_RX__DUART_CTS,
77
78 /* UART2 */
79 MX28_PAD_AUART1_RX__AUART1_RX,
80 MX28_PAD_AUART1_TX__AUART1_TX,
81 MX28_PAD_AUART1_RTS__AUART1_RTS,
82 MX28_PAD_AUART1_CTS__AUART1_CTS,
83
84 /* CAN */
85 MX28_PAD_GPMI_RDY2__CAN0_TX,
86 MX28_PAD_GPMI_RDY3__CAN0_RX,
87
88 /* I2C */
89 MX28_PAD_I2C0_SCL__I2C0_SCL,
90 MX28_PAD_I2C0_SDA__I2C0_SDA,
91
92 /* TSC2007 */
93 MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
94
95 /* MMC0 */
96 MX28_PAD_SSP0_DATA0__SSP0_D0 |
97 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
98 MX28_PAD_SSP0_DATA1__SSP0_D1 |
99 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
100 MX28_PAD_SSP0_DATA2__SSP0_D2 |
101 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
102 MX28_PAD_SSP0_DATA3__SSP0_D3 |
103 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
104 MX28_PAD_SSP0_DATA4__SSP0_D4 |
105 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
106 MX28_PAD_SSP0_DATA5__SSP0_D5 |
107 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
108 MX28_PAD_SSP0_DATA6__SSP0_D6 |
109 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
110 MX28_PAD_SSP0_DATA7__SSP0_D7 |
111 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
112 MX28_PAD_SSP0_CMD__SSP0_CMD |
113 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
114 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
115 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
116 MX28_PAD_SSP0_SCK__SSP0_SCK |
117 (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
118};
119
120static struct gpio_led tx28_stk5v3_leds[] = {
121 {
122 .name = "GPIO-LED",
123 .default_trigger = "heartbeat",
124 .gpio = TX28_STK5_GPIO_LED,
125 },
126};
127
128static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = {
129 .leds = tx28_stk5v3_leds,
130 .num_leds = ARRAY_SIZE(tx28_stk5v3_leds),
131};
132
133static struct spi_board_info tx28_spi_board_info[] = {
134 {
135 .modalias = "spidev",
136 .max_speed_hz = 20000000,
137 .bus_num = 0,
138 .chip_select = 1,
139 .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT,
140 .mode = SPI_MODE_0,
141 },
142};
143
144static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
145 {
146 I2C_BOARD_INFO("ds1339", 0x68),
147 },
148};
149
150static void __init tx28_stk5v3_init(void)
151{
152 mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
153 ARRAY_SIZE(tx28_stk5v3_pads));
154
155 mx28_add_duart(); /* UART1 */
156 mx28_add_auart(1); /* UART2 */
157
158 tx28_add_fec0();
159 /* spi via ssp will be added when available */
160 spi_register_board_info(tx28_spi_board_info,
161 ARRAY_SIZE(tx28_spi_board_info));
162 mxs_add_platform_device("leds-gpio", 0, NULL, 0,
163 &tx28_stk5v3_led_data, sizeof(tx28_stk5v3_led_data));
164 mx28_add_mxs_i2c(0);
165 i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
166 ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
167}
168
169static void __init tx28_timer_init(void)
170{
171 mx28_clocks_init();
172}
173
174static struct sys_timer tx28_timer = {
175 .init = tx28_timer_init,
176};
177
178MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
179 .map_io = mx28_map_io,
180 .init_irq = mx28_init_irq,
181 .init_machine = tx28_stk5v3_init,
182 .timer = &tx28_timer,
183MACHINE_END
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
new file mode 100644
index 00000000000..fa0b154da67
--- /dev/null
+++ b/arch/arm/mach-mxs/module-tx28.c
@@ -0,0 +1,131 @@
1/*
2 * Copyright (C) 2010 <LW@KARO-electronics.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8
9#include <linux/delay.h>
10#include <linux/fec.h>
11#include <linux/gpio.h>
12
13#include <mach/iomux-mx28.h>
14#include "../devices-mx28.h"
15
16#include "module-tx28.h"
17
18#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29)
19#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
20
21static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = {
22 /* PHY POWER */
23 MX28_PAD_PWM4__GPIO_3_29 |
24 MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
25 /* PHY RESET */
26 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
27 MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
28 /* Mode strap pins 0-2 */
29 MX28_PAD_ENET0_RXD0__GPIO_4_3 |
30 MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
31 MX28_PAD_ENET0_RXD1__GPIO_4_4 |
32 MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
33 MX28_PAD_ENET0_RX_EN__GPIO_4_2 |
34 MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
35 /* nINT */
36 MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
37 MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
38
39 MX28_PAD_ENET0_MDC__GPIO_4_0,
40 MX28_PAD_ENET0_MDIO__GPIO_4_1,
41 MX28_PAD_ENET0_TX_EN__GPIO_4_6,
42 MX28_PAD_ENET0_TXD0__GPIO_4_7,
43 MX28_PAD_ENET0_TXD1__GPIO_4_8,
44 MX28_PAD_ENET_CLK__GPIO_4_16,
45};
46
47#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3)
48static const iomux_cfg_t tx28_fec_pads[] __initconst = {
49 MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE,
50 MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE,
51 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE,
52 MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE,
53 MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE,
54 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE,
55 MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE,
56 MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE,
57 MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE,
58};
59
60static const struct fec_platform_data tx28_fec_data __initconst = {
61 .phy = PHY_INTERFACE_MODE_RMII,
62};
63
64int __init tx28_add_fec0(void)
65{
66 int i, ret;
67
68 pr_debug("%s: Switching FEC PHY power off\n", __func__);
69 ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads,
70 ARRAY_SIZE(tx28_fec_gpio_pads));
71 for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) {
72 unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
73 PAD_PIN(tx28_fec_gpio_pads[i]));
74
75 ret = gpio_request(gpio, "FEC");
76 if (ret) {
77 pr_err("Failed to request GPIO_%d_%d: %d\n",
78 PAD_BANK(tx28_fec_gpio_pads[i]),
79 PAD_PIN(tx28_fec_gpio_pads[i]), ret);
80 goto free_gpios;
81 }
82 ret = gpio_direction_output(gpio, 0);
83 if (ret) {
84 pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n",
85 gpio / 32 + 1, gpio % 32, ret);
86 goto free_gpios;
87 }
88 }
89
90 /* Power up fec phy */
91 pr_debug("%s: Switching FEC PHY power on\n", __func__);
92 ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1);
93 if (ret) {
94 pr_err("Failed to power on PHY: %d\n", ret);
95 goto free_gpios;
96 }
97 mdelay(26); /* 25ms according to data sheet */
98
99 /* nINT */
100 gpio_direction_input(MXS_GPIO_NR(4, 5));
101 /* Mode strap pins */
102 gpio_direction_output(MXS_GPIO_NR(4, 2), 1);
103 gpio_direction_output(MXS_GPIO_NR(4, 3), 1);
104 gpio_direction_output(MXS_GPIO_NR(4, 4), 1);
105
106 udelay(100); /* minimum assertion time for nRST */
107
108 pr_debug("%s: Deasserting FEC PHY RESET\n", __func__);
109 gpio_set_value(TX28_FEC_PHY_RESET, 1);
110
111 ret = mxs_iomux_setup_multiple_pads(tx28_fec_pads,
112 ARRAY_SIZE(tx28_fec_pads));
113 if (ret) {
114 pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
115 __func__, ret);
116 goto free_gpios;
117 }
118 pr_debug("%s: Registering FEC device\n", __func__);
119 mx28_add_fec(0, &tx28_fec_data);
120 return 0;
121
122free_gpios:
123 while (--i >= 0) {
124 unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
125 PAD_PIN(tx28_fec_gpio_pads[i]));
126
127 gpio_free(gpio);
128 }
129
130 return ret;
131}
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h
new file mode 100644
index 00000000000..df9e1b6e81b
--- /dev/null
+++ b/arch/arm/mach-mxs/module-tx28.h
@@ -0,0 +1,9 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9int __init tx28_add_fec0(void);
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
new file mode 100644
index 00000000000..65157a35dbb
--- /dev/null
+++ b/arch/arm/mach-mxs/ocotp.c
@@ -0,0 +1,90 @@
1/*
2 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/mutex.h>
18
19#include <mach/mxs.h>
20
21#define OCOTP_WORD_OFFSET 0x20
22#define OCOTP_WORD_COUNT 0x20
23
24#define BM_OCOTP_CTRL_BUSY (1 << 8)
25#define BM_OCOTP_CTRL_ERROR (1 << 9)
26#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
27
28static DEFINE_MUTEX(ocotp_mutex);
29static u32 ocotp_words[OCOTP_WORD_COUNT];
30
31const u32 *mxs_get_ocotp(void)
32{
33 void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
34 int timeout = 0x400;
35 size_t i;
36 static int once = 0;
37
38 if (once)
39 return ocotp_words;
40
41 mutex_lock(&ocotp_mutex);
42
43 /*
44 * clk_enable(hbus_clk) for ocotp can be skipped
45 * as it must be on when system is running.
46 */
47
48 /* try to clear ERROR bit */
49 __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
50
51 /* check both BUSY and ERROR cleared */
52 while ((__raw_readl(ocotp_base) &
53 (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
54 cpu_relax();
55
56 if (unlikely(!timeout))
57 goto error_unlock;
58
59 /* open OCOTP banks for read */
60 __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
61
62 /* approximately wait 32 hclk cycles */
63 udelay(1);
64
65 /* poll BUSY bit becoming cleared */
66 timeout = 0x400;
67 while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
68 cpu_relax();
69
70 if (unlikely(!timeout))
71 goto error_unlock;
72
73 for (i = 0; i < OCOTP_WORD_COUNT; i++)
74 ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
75 i * 0x10);
76
77 /* close banks for power saving */
78 __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
79
80 once = 1;
81
82 mutex_unlock(&ocotp_mutex);
83
84 return ocotp_words;
85
86error_unlock:
87 mutex_unlock(&ocotp_mutex);
88 pr_err("%s: timeout in reading OCOTP\n", __func__);
89 return NULL;
90}
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
new file mode 100644
index 00000000000..fb042da29bd
--- /dev/null
+++ b/arch/arm/mach-mxs/pm.c
@@ -0,0 +1,43 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/suspend.h>
17#include <linux/io.h>
18#include <mach/system.h>
19
20static int mxs_suspend_enter(suspend_state_t state)
21{
22 switch (state) {
23 case PM_SUSPEND_MEM:
24 arch_idle();
25 break;
26
27 default:
28 return -EINVAL;
29 }
30 return 0;
31}
32
33static struct platform_suspend_ops mxs_suspend_ops = {
34 .enter = mxs_suspend_enter,
35 .valid = suspend_valid_only_mem,
36};
37
38static int __init mxs_pm_init(void)
39{
40 suspend_set_ops(&mxs_suspend_ops);
41 return 0;
42}
43device_initcall(mxs_pm_init);
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
index dbc04747b69..0ea5c9d0e2b 100644
--- a/arch/arm/mach-mxs/regs-clkctrl-mx23.h
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
@@ -33,10 +33,6 @@
33#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008) 33#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
34#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c) 34#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
35 35
36#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30
37#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000
38#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
39 (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
40#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 36#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
41#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 37#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
42#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ 38#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
@@ -45,10 +41,6 @@
45#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 41#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
46#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 42#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
47#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 43#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
48#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26
49#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000
50#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \
51 (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
52#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 44#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
53#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 45#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
54#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ 46#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
@@ -57,10 +49,6 @@
57#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 49#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
58#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 50#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
59#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 51#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
60#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22
61#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000
62#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \
63 (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
64#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 52#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
65#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 53#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
66#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ 54#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
@@ -69,23 +57,13 @@
69#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 57#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
70#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 58#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
71#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 59#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
72#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000
73#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 60#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
74#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000
75#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 61#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
76#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0
77#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF
78#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \
79 (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
80 62
81#define HW_CLKCTRL_PLLCTRL1 (0x00000010) 63#define HW_CLKCTRL_PLLCTRL1 (0x00000010)
82 64
83#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 65#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
84#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 66#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
85#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16
86#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000
87#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \
88 (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
89#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 67#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
90#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF 68#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
91#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ 69#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
@@ -96,29 +74,15 @@
96#define HW_CLKCTRL_CPU_CLR (0x00000028) 74#define HW_CLKCTRL_CPU_CLR (0x00000028)
97#define HW_CLKCTRL_CPU_TOG (0x0000002c) 75#define HW_CLKCTRL_CPU_TOG (0x0000002c)
98 76
99#define BP_CLKCTRL_CPU_RSRVD5 30
100#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
101#define BF_CLKCTRL_CPU_RSRVD5(v) \
102 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
103#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 77#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
104#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 78#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
105#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
106#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 79#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
107#define BP_CLKCTRL_CPU_DIV_XTAL 16 80#define BP_CLKCTRL_CPU_DIV_XTAL 16
108#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 81#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
109#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ 82#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
110 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) 83 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
111#define BP_CLKCTRL_CPU_RSRVD3 13
112#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
113#define BF_CLKCTRL_CPU_RSRVD3(v) \
114 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
115#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 84#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
116#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
117#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 85#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
118#define BP_CLKCTRL_CPU_RSRVD1 6
119#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
120#define BF_CLKCTRL_CPU_RSRVD1(v) \
121 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
122#define BP_CLKCTRL_CPU_DIV_CPU 0 86#define BP_CLKCTRL_CPU_DIV_CPU 0
123#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F 87#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
124#define BF_CLKCTRL_CPU_DIV_CPU(v) \ 88#define BF_CLKCTRL_CPU_DIV_CPU(v) \
@@ -129,10 +93,6 @@
129#define HW_CLKCTRL_HBUS_CLR (0x00000038) 93#define HW_CLKCTRL_HBUS_CLR (0x00000038)
130#define HW_CLKCTRL_HBUS_TOG (0x0000003c) 94#define HW_CLKCTRL_HBUS_TOG (0x0000003c)
131 95
132#define BP_CLKCTRL_HBUS_RSRVD4 30
133#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000
134#define BF_CLKCTRL_HBUS_RSRVD4(v) \
135 (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
136#define BM_CLKCTRL_HBUS_BUSY 0x20000000 96#define BM_CLKCTRL_HBUS_BUSY 0x20000000
137#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 97#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
138#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 98#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
@@ -143,7 +103,6 @@
143#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 103#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
144#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 104#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
145#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 105#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
146#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000
147#define BP_CLKCTRL_HBUS_SLOW_DIV 16 106#define BP_CLKCTRL_HBUS_SLOW_DIV 16
148#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 107#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
149#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ 108#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
@@ -154,10 +113,6 @@
154#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 113#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
155#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 114#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
156#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 115#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
157#define BP_CLKCTRL_HBUS_RSRVD1 6
158#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
159#define BF_CLKCTRL_HBUS_RSRVD1(v) \
160 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
161#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 116#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
162#define BP_CLKCTRL_HBUS_DIV 0 117#define BP_CLKCTRL_HBUS_DIV 0
163#define BM_CLKCTRL_HBUS_DIV 0x0000001F 118#define BM_CLKCTRL_HBUS_DIV 0x0000001F
@@ -167,10 +122,6 @@
167#define HW_CLKCTRL_XBUS (0x00000040) 122#define HW_CLKCTRL_XBUS (0x00000040)
168 123
169#define BM_CLKCTRL_XBUS_BUSY 0x80000000 124#define BM_CLKCTRL_XBUS_BUSY 0x80000000
170#define BP_CLKCTRL_XBUS_RSRVD1 11
171#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800
172#define BF_CLKCTRL_XBUS_RSRVD1(v) \
173 (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
174#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 125#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
175#define BP_CLKCTRL_XBUS_DIV 0 126#define BP_CLKCTRL_XBUS_DIV 0
176#define BM_CLKCTRL_XBUS_DIV 0x000003FF 127#define BM_CLKCTRL_XBUS_DIV 0x000003FF
@@ -192,10 +143,6 @@
192#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 143#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
193#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 144#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
194#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 145#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
195#define BP_CLKCTRL_XTAL_RSRVD1 2
196#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
197#define BF_CLKCTRL_XTAL_RSRVD1(v) \
198 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
199#define BP_CLKCTRL_XTAL_DIV_UART 0 146#define BP_CLKCTRL_XTAL_DIV_UART 0
200#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 147#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
201#define BF_CLKCTRL_XTAL_DIV_UART(v) \ 148#define BF_CLKCTRL_XTAL_DIV_UART(v) \
@@ -205,12 +152,7 @@
205 152
206#define BP_CLKCTRL_PIX_CLKGATE 31 153#define BP_CLKCTRL_PIX_CLKGATE 31
207#define BM_CLKCTRL_PIX_CLKGATE 0x80000000 154#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
208#define BM_CLKCTRL_PIX_RSRVD2 0x40000000
209#define BM_CLKCTRL_PIX_BUSY 0x20000000 155#define BM_CLKCTRL_PIX_BUSY 0x20000000
210#define BP_CLKCTRL_PIX_RSRVD1 13
211#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000
212#define BF_CLKCTRL_PIX_RSRVD1(v) \
213 (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
214#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 156#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
215#define BP_CLKCTRL_PIX_DIV 0 157#define BP_CLKCTRL_PIX_DIV 0
216#define BM_CLKCTRL_PIX_DIV 0x00000FFF 158#define BM_CLKCTRL_PIX_DIV 0x00000FFF
@@ -221,12 +163,7 @@
221 163
222#define BP_CLKCTRL_SSP_CLKGATE 31 164#define BP_CLKCTRL_SSP_CLKGATE 31
223#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 165#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
224#define BM_CLKCTRL_SSP_RSRVD2 0x40000000
225#define BM_CLKCTRL_SSP_BUSY 0x20000000 166#define BM_CLKCTRL_SSP_BUSY 0x20000000
226#define BP_CLKCTRL_SSP_RSRVD1 10
227#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00
228#define BF_CLKCTRL_SSP_RSRVD1(v) \
229 (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
230#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 167#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
231#define BP_CLKCTRL_SSP_DIV 0 168#define BP_CLKCTRL_SSP_DIV 0
232#define BM_CLKCTRL_SSP_DIV 0x000001FF 169#define BM_CLKCTRL_SSP_DIV 0x000001FF
@@ -237,12 +174,7 @@
237 174
238#define BP_CLKCTRL_GPMI_CLKGATE 31 175#define BP_CLKCTRL_GPMI_CLKGATE 31
239#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 176#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
240#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
241#define BM_CLKCTRL_GPMI_BUSY 0x20000000 177#define BM_CLKCTRL_GPMI_BUSY 0x20000000
242#define BP_CLKCTRL_GPMI_RSRVD1 11
243#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
244#define BF_CLKCTRL_GPMI_RSRVD1(v) \
245 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
246#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 178#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
247#define BP_CLKCTRL_GPMI_DIV 0 179#define BP_CLKCTRL_GPMI_DIV 0
248#define BM_CLKCTRL_GPMI_DIV 0x000003FF 180#define BM_CLKCTRL_GPMI_DIV 0x000003FF
@@ -252,10 +184,6 @@
252#define HW_CLKCTRL_SPDIF (0x00000090) 184#define HW_CLKCTRL_SPDIF (0x00000090)
253 185
254#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 186#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
255#define BP_CLKCTRL_SPDIF_RSRVD 0
256#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
257#define BF_CLKCTRL_SPDIF_RSRVD(v) \
258 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
259 187
260#define HW_CLKCTRL_EMI (0x000000a0) 188#define HW_CLKCTRL_EMI (0x000000a0)
261 189
@@ -266,24 +194,12 @@
266#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 194#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
267#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 195#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
268#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 196#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
269#define BP_CLKCTRL_EMI_RSRVD3 18
270#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
271#define BF_CLKCTRL_EMI_RSRVD3(v) \
272 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
273#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 197#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
274#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 198#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
275#define BP_CLKCTRL_EMI_RSRVD2 12
276#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
277#define BF_CLKCTRL_EMI_RSRVD2(v) \
278 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
279#define BP_CLKCTRL_EMI_DIV_XTAL 8 199#define BP_CLKCTRL_EMI_DIV_XTAL 8
280#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 200#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
281#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ 201#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
282 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) 202 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
283#define BP_CLKCTRL_EMI_RSRVD1 6
284#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
285#define BF_CLKCTRL_EMI_RSRVD1(v) \
286 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
287#define BP_CLKCTRL_EMI_DIV_EMI 0 203#define BP_CLKCTRL_EMI_DIV_EMI 0
288#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F 204#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
289#define BF_CLKCTRL_EMI_DIV_EMI(v) \ 205#define BF_CLKCTRL_EMI_DIV_EMI(v) \
@@ -292,22 +208,13 @@
292#define HW_CLKCTRL_IR (0x000000b0) 208#define HW_CLKCTRL_IR (0x000000b0)
293 209
294#define BM_CLKCTRL_IR_CLKGATE 0x80000000 210#define BM_CLKCTRL_IR_CLKGATE 0x80000000
295#define BM_CLKCTRL_IR_RSRVD3 0x40000000
296#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 211#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
297#define BM_CLKCTRL_IR_IR_BUSY 0x10000000 212#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
298#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 213#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
299#define BP_CLKCTRL_IR_RSRVD2 25
300#define BM_CLKCTRL_IR_RSRVD2 0x06000000
301#define BF_CLKCTRL_IR_RSRVD2(v) \
302 (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
303#define BP_CLKCTRL_IR_IROV_DIV 16 214#define BP_CLKCTRL_IR_IROV_DIV 16
304#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 215#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
305#define BF_CLKCTRL_IR_IROV_DIV(v) \ 216#define BF_CLKCTRL_IR_IROV_DIV(v) \
306 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) 217 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
307#define BP_CLKCTRL_IR_RSRVD1 10
308#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00
309#define BF_CLKCTRL_IR_RSRVD1(v) \
310 (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
311#define BP_CLKCTRL_IR_IR_DIV 0 218#define BP_CLKCTRL_IR_IR_DIV 0
312#define BM_CLKCTRL_IR_IR_DIV 0x000003FF 219#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
313#define BF_CLKCTRL_IR_IR_DIV(v) \ 220#define BF_CLKCTRL_IR_IR_DIV(v) \
@@ -316,12 +223,7 @@
316#define HW_CLKCTRL_SAIF (0x000000c0) 223#define HW_CLKCTRL_SAIF (0x000000c0)
317 224
318#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 225#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
319#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000
320#define BM_CLKCTRL_SAIF_BUSY 0x20000000 226#define BM_CLKCTRL_SAIF_BUSY 0x20000000
321#define BP_CLKCTRL_SAIF_RSRVD1 17
322#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000
323#define BF_CLKCTRL_SAIF_RSRVD1(v) \
324 (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
325#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 227#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
326#define BP_CLKCTRL_SAIF_DIV 0 228#define BP_CLKCTRL_SAIF_DIV 0
327#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF 229#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
@@ -332,20 +234,11 @@
332 234
333#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 235#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
334#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 236#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
335#define BP_CLKCTRL_TV_RSRVD 0
336#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF
337#define BF_CLKCTRL_TV_RSRVD(v) \
338 (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
339 237
340#define HW_CLKCTRL_ETM (0x000000e0) 238#define HW_CLKCTRL_ETM (0x000000e0)
341 239
342#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 240#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
343#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
344#define BM_CLKCTRL_ETM_BUSY 0x20000000 241#define BM_CLKCTRL_ETM_BUSY 0x20000000
345#define BP_CLKCTRL_ETM_RSRVD1 7
346#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80
347#define BF_CLKCTRL_ETM_RSRVD1(v) \
348 (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
349#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 242#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
350#define BP_CLKCTRL_ETM_DIV 0 243#define BP_CLKCTRL_ETM_DIV 0
351#define BM_CLKCTRL_ETM_DIV 0x0000003F 244#define BM_CLKCTRL_ETM_DIV 0x0000003F
@@ -393,36 +286,23 @@
393 286
394#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 287#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
395#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 288#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
396#define BP_CLKCTRL_FRAC1_RSRVD1 0
397#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
398#define BF_CLKCTRL_FRAC1_RSRVD1(v) \
399 (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
400 289
401#define HW_CLKCTRL_CLKSEQ (0x00000110) 290#define HW_CLKCTRL_CLKSEQ (0x00000110)
402#define HW_CLKCTRL_CLKSEQ_SET (0x00000114) 291#define HW_CLKCTRL_CLKSEQ_SET (0x00000114)
403#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118) 292#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118)
404#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c) 293#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c)
405 294
406#define BP_CLKCTRL_CLKSEQ_RSRVD1 9
407#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00
408#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
409 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
410#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 295#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
411#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 296#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
412#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 297#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
413#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 298#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
414#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 299#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
415#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 300#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
416#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004
417#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 301#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
418#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 302#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
419 303
420#define HW_CLKCTRL_RESET (0x00000120) 304#define HW_CLKCTRL_RESET (0x00000120)
421 305
422#define BP_CLKCTRL_RESET_RSRVD 2
423#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC
424#define BF_CLKCTRL_RESET_RSRVD(v) \
425 (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
426#define BM_CLKCTRL_RESET_CHIP 0x00000002 306#define BM_CLKCTRL_RESET_CHIP 0x00000002
427#define BM_CLKCTRL_RESET_DIG 0x00000001 307#define BM_CLKCTRL_RESET_DIG 0x00000001
428 308
@@ -432,10 +312,6 @@
432#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 312#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
433#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ 313#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
434 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) 314 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
435#define BP_CLKCTRL_STATUS_RSRVD 0
436#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
437#define BF_CLKCTRL_STATUS_RSRVD(v) \
438 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
439 315
440#define HW_CLKCTRL_VERSION (0x00000140) 316#define HW_CLKCTRL_VERSION (0x00000140)
441 317
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
index 661df18755f..7d1b061d794 100644
--- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
@@ -31,10 +31,6 @@
31#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008) 31#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
32#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c) 32#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
33 33
34#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30
35#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000
36#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
37 (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
38#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28 34#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28
39#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000 35#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
40#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \ 36#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \
@@ -43,10 +39,6 @@
43#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1 39#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
44#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2 40#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
45#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3 41#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
46#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26
47#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000
48#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \
49 (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
50#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24 42#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24
51#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000 43#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
52#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \ 44#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \
@@ -55,10 +47,6 @@
55#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1 47#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1
56#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2 48#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2
57#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3 49#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
58#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22
59#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000
60#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \
61 (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
62#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20 50#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20
63#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000 51#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000
64#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \ 52#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \
@@ -67,22 +55,13 @@
67#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1 55#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1
68#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2 56#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2
69#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3 57#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
70#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000
71#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000 58#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000
72#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000 59#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000
73#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0
74#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF
75#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \
76 (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
77 60
78#define HW_CLKCTRL_PLL0CTRL1 (0x00000010) 61#define HW_CLKCTRL_PLL0CTRL1 (0x00000010)
79 62
80#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000 63#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000
81#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000 64#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
82#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16
83#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000
84#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \
85 (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
86#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0 65#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
87#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF 66#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
88#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \ 67#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \
@@ -94,7 +73,6 @@
94#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c) 73#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c)
95 74
96#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000 75#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
97#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000
98#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28 76#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28
99#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000 77#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000
100#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \ 78#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \
@@ -103,10 +81,6 @@
103#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1 81#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1
104#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2 82#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2
105#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3 83#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
106#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26
107#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000
108#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \
109 (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
110#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24 84#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24
111#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000 85#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000
112#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \ 86#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \
@@ -115,10 +89,6 @@
115#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1 89#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1
116#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2 90#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2
117#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3 91#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
118#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22
119#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000
120#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \
121 (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
122#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20 92#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20
123#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000 93#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000
124#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \ 94#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \
@@ -127,22 +97,13 @@
127#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1 97#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1
128#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2 98#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2
129#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3 99#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
130#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000
131#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000 100#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000
132#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000 101#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000
133#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0
134#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF
135#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \
136 (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
137 102
138#define HW_CLKCTRL_PLL1CTRL1 (0x00000030) 103#define HW_CLKCTRL_PLL1CTRL1 (0x00000030)
139 104
140#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000 105#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000
141#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000 106#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
142#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16
143#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000
144#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \
145 (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
146#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0 107#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
147#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF 108#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
148#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \ 109#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \
@@ -154,51 +115,31 @@
154#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c) 115#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c)
155 116
156#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000 117#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000
157#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000
158#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28 118#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28
159#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000 119#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000
160#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \ 120#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \
161 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL) 121 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
162#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000
163#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000 122#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000
164#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24 123#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24
165#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000 124#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000
166#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \ 125#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \
167 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL) 126 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
168#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000 127#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000
169#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0
170#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF
171#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \
172 (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
173 128
174#define HW_CLKCTRL_CPU (0x00000050) 129#define HW_CLKCTRL_CPU (0x00000050)
175#define HW_CLKCTRL_CPU_SET (0x00000054) 130#define HW_CLKCTRL_CPU_SET (0x00000054)
176#define HW_CLKCTRL_CPU_CLR (0x00000058) 131#define HW_CLKCTRL_CPU_CLR (0x00000058)
177#define HW_CLKCTRL_CPU_TOG (0x0000005c) 132#define HW_CLKCTRL_CPU_TOG (0x0000005c)
178 133
179#define BP_CLKCTRL_CPU_RSRVD5 30
180#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
181#define BF_CLKCTRL_CPU_RSRVD5(v) \
182 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
183#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 134#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
184#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 135#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
185#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
186#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 136#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
187#define BP_CLKCTRL_CPU_DIV_XTAL 16 137#define BP_CLKCTRL_CPU_DIV_XTAL 16
188#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 138#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
189#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ 139#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
190 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) 140 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
191#define BP_CLKCTRL_CPU_RSRVD3 13
192#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
193#define BF_CLKCTRL_CPU_RSRVD3(v) \
194 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
195#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 141#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
196#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
197#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 142#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
198#define BP_CLKCTRL_CPU_RSRVD1 6
199#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
200#define BF_CLKCTRL_CPU_RSRVD1(v) \
201 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
202#define BP_CLKCTRL_CPU_DIV_CPU 0 143#define BP_CLKCTRL_CPU_DIV_CPU 0
203#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F 144#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
204#define BF_CLKCTRL_CPU_DIV_CPU(v) \ 145#define BF_CLKCTRL_CPU_DIV_CPU(v) \
@@ -212,7 +153,6 @@
212#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000 153#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000
213#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000 154#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000
214#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000 155#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000
215#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000
216#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000 156#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000
217#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 157#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
218#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 158#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
@@ -232,10 +172,6 @@
232#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 172#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
233#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 173#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
234#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 174#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
235#define BP_CLKCTRL_HBUS_RSRVD1 6
236#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
237#define BF_CLKCTRL_HBUS_RSRVD1(v) \
238 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
239#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 175#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
240#define BP_CLKCTRL_HBUS_DIV 0 176#define BP_CLKCTRL_HBUS_DIV 0
241#define BM_CLKCTRL_HBUS_DIV 0x0000001F 177#define BM_CLKCTRL_HBUS_DIV 0x0000001F
@@ -245,10 +181,6 @@
245#define HW_CLKCTRL_XBUS (0x00000070) 181#define HW_CLKCTRL_XBUS (0x00000070)
246 182
247#define BM_CLKCTRL_XBUS_BUSY 0x80000000 183#define BM_CLKCTRL_XBUS_BUSY 0x80000000
248#define BP_CLKCTRL_XBUS_RSRVD1 12
249#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000
250#define BF_CLKCTRL_XBUS_RSRVD1(v) \
251 (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
252#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800 184#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800
253#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 185#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
254#define BP_CLKCTRL_XBUS_DIV 0 186#define BP_CLKCTRL_XBUS_DIV 0
@@ -263,19 +195,10 @@
263 195
264#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31 196#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
265#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 197#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
266#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000
267#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29 198#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
268#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 199#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
269#define BP_CLKCTRL_XTAL_RSRVD2 27
270#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000
271#define BF_CLKCTRL_XTAL_RSRVD2(v) \
272 (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
273#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26 200#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
274#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 201#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
275#define BP_CLKCTRL_XTAL_RSRVD1 2
276#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
277#define BF_CLKCTRL_XTAL_RSRVD1(v) \
278 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
279#define BP_CLKCTRL_XTAL_DIV_UART 0 202#define BP_CLKCTRL_XTAL_DIV_UART 0
280#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 203#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
281#define BF_CLKCTRL_XTAL_DIV_UART(v) \ 204#define BF_CLKCTRL_XTAL_DIV_UART(v) \
@@ -285,12 +208,7 @@
285 208
286#define BP_CLKCTRL_SSP0_CLKGATE 31 209#define BP_CLKCTRL_SSP0_CLKGATE 31
287#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000 210#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
288#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000
289#define BM_CLKCTRL_SSP0_BUSY 0x20000000 211#define BM_CLKCTRL_SSP0_BUSY 0x20000000
290#define BP_CLKCTRL_SSP0_RSRVD1 10
291#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00
292#define BF_CLKCTRL_SSP0_RSRVD1(v) \
293 (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
294#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200 212#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200
295#define BP_CLKCTRL_SSP0_DIV 0 213#define BP_CLKCTRL_SSP0_DIV 0
296#define BM_CLKCTRL_SSP0_DIV 0x000001FF 214#define BM_CLKCTRL_SSP0_DIV 0x000001FF
@@ -301,12 +219,7 @@
301 219
302#define BP_CLKCTRL_SSP1_CLKGATE 31 220#define BP_CLKCTRL_SSP1_CLKGATE 31
303#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000 221#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
304#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000
305#define BM_CLKCTRL_SSP1_BUSY 0x20000000 222#define BM_CLKCTRL_SSP1_BUSY 0x20000000
306#define BP_CLKCTRL_SSP1_RSRVD1 10
307#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00
308#define BF_CLKCTRL_SSP1_RSRVD1(v) \
309 (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
310#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200 223#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200
311#define BP_CLKCTRL_SSP1_DIV 0 224#define BP_CLKCTRL_SSP1_DIV 0
312#define BM_CLKCTRL_SSP1_DIV 0x000001FF 225#define BM_CLKCTRL_SSP1_DIV 0x000001FF
@@ -317,12 +230,7 @@
317 230
318#define BP_CLKCTRL_SSP2_CLKGATE 31 231#define BP_CLKCTRL_SSP2_CLKGATE 31
319#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000 232#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
320#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000
321#define BM_CLKCTRL_SSP2_BUSY 0x20000000 233#define BM_CLKCTRL_SSP2_BUSY 0x20000000
322#define BP_CLKCTRL_SSP2_RSRVD1 10
323#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00
324#define BF_CLKCTRL_SSP2_RSRVD1(v) \
325 (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
326#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200 234#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200
327#define BP_CLKCTRL_SSP2_DIV 0 235#define BP_CLKCTRL_SSP2_DIV 0
328#define BM_CLKCTRL_SSP2_DIV 0x000001FF 236#define BM_CLKCTRL_SSP2_DIV 0x000001FF
@@ -333,12 +241,7 @@
333 241
334#define BP_CLKCTRL_SSP3_CLKGATE 31 242#define BP_CLKCTRL_SSP3_CLKGATE 31
335#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000 243#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
336#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000
337#define BM_CLKCTRL_SSP3_BUSY 0x20000000 244#define BM_CLKCTRL_SSP3_BUSY 0x20000000
338#define BP_CLKCTRL_SSP3_RSRVD1 10
339#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00
340#define BF_CLKCTRL_SSP3_RSRVD1(v) \
341 (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
342#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200 245#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200
343#define BP_CLKCTRL_SSP3_DIV 0 246#define BP_CLKCTRL_SSP3_DIV 0
344#define BM_CLKCTRL_SSP3_DIV 0x000001FF 247#define BM_CLKCTRL_SSP3_DIV 0x000001FF
@@ -349,12 +252,7 @@
349 252
350#define BP_CLKCTRL_GPMI_CLKGATE 31 253#define BP_CLKCTRL_GPMI_CLKGATE 31
351#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 254#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
352#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
353#define BM_CLKCTRL_GPMI_BUSY 0x20000000 255#define BM_CLKCTRL_GPMI_BUSY 0x20000000
354#define BP_CLKCTRL_GPMI_RSRVD1 11
355#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
356#define BF_CLKCTRL_GPMI_RSRVD1(v) \
357 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
358#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 256#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
359#define BP_CLKCTRL_GPMI_DIV 0 257#define BP_CLKCTRL_GPMI_DIV 0
360#define BM_CLKCTRL_GPMI_DIV 0x000003FF 258#define BM_CLKCTRL_GPMI_DIV 0x000003FF
@@ -365,10 +263,6 @@
365 263
366#define BP_CLKCTRL_SPDIF_CLKGATE 31 264#define BP_CLKCTRL_SPDIF_CLKGATE 31
367#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 265#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
368#define BP_CLKCTRL_SPDIF_RSRVD 0
369#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
370#define BF_CLKCTRL_SPDIF_RSRVD(v) \
371 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
372 266
373#define HW_CLKCTRL_EMI (0x000000f0) 267#define HW_CLKCTRL_EMI (0x000000f0)
374 268
@@ -379,24 +273,12 @@
379#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 273#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
380#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 274#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
381#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 275#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
382#define BP_CLKCTRL_EMI_RSRVD3 18
383#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
384#define BF_CLKCTRL_EMI_RSRVD3(v) \
385 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
386#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 276#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
387#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 277#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
388#define BP_CLKCTRL_EMI_RSRVD2 12
389#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
390#define BF_CLKCTRL_EMI_RSRVD2(v) \
391 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
392#define BP_CLKCTRL_EMI_DIV_XTAL 8 278#define BP_CLKCTRL_EMI_DIV_XTAL 8
393#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 279#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
394#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ 280#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
395 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) 281 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
396#define BP_CLKCTRL_EMI_RSRVD1 6
397#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
398#define BF_CLKCTRL_EMI_RSRVD1(v) \
399 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
400#define BP_CLKCTRL_EMI_DIV_EMI 0 282#define BP_CLKCTRL_EMI_DIV_EMI 0
401#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F 283#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
402#define BF_CLKCTRL_EMI_DIV_EMI(v) \ 284#define BF_CLKCTRL_EMI_DIV_EMI(v) \
@@ -406,12 +288,7 @@
406 288
407#define BP_CLKCTRL_SAIF0_CLKGATE 31 289#define BP_CLKCTRL_SAIF0_CLKGATE 31
408#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000 290#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000
409#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
410#define BM_CLKCTRL_SAIF0_BUSY 0x20000000 291#define BM_CLKCTRL_SAIF0_BUSY 0x20000000
411#define BP_CLKCTRL_SAIF0_RSRVD1 17
412#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
413#define BF_CLKCTRL_SAIF0_RSRVD1(v) \
414 (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
415#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000 292#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000
416#define BP_CLKCTRL_SAIF0_DIV 0 293#define BP_CLKCTRL_SAIF0_DIV 0
417#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF 294#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF
@@ -422,12 +299,7 @@
422 299
423#define BP_CLKCTRL_SAIF1_CLKGATE 31 300#define BP_CLKCTRL_SAIF1_CLKGATE 31
424#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000 301#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000
425#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
426#define BM_CLKCTRL_SAIF1_BUSY 0x20000000 302#define BM_CLKCTRL_SAIF1_BUSY 0x20000000
427#define BP_CLKCTRL_SAIF1_RSRVD1 17
428#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
429#define BF_CLKCTRL_SAIF1_RSRVD1(v) \
430 (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
431#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000 303#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000
432#define BP_CLKCTRL_SAIF1_DIV 0 304#define BP_CLKCTRL_SAIF1_DIV 0
433#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF 305#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF
@@ -438,12 +310,7 @@
438 310
439#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31 311#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31
440#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000 312#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000
441#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000
442#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000 313#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000
443#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14
444#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000
445#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \
446 (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
447#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000 314#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000
448#define BP_CLKCTRL_DIS_LCDIF_DIV 0 315#define BP_CLKCTRL_DIS_LCDIF_DIV 0
449#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF 316#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF
@@ -453,12 +320,7 @@
453#define HW_CLKCTRL_ETM (0x00000130) 320#define HW_CLKCTRL_ETM (0x00000130)
454 321
455#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 322#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
456#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
457#define BM_CLKCTRL_ETM_BUSY 0x20000000 323#define BM_CLKCTRL_ETM_BUSY 0x20000000
458#define BP_CLKCTRL_ETM_RSRVD1 8
459#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00
460#define BF_CLKCTRL_ETM_RSRVD1(v) \
461 (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
462#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080 324#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080
463#define BP_CLKCTRL_ETM_DIV 0 325#define BP_CLKCTRL_ETM_DIV 0
464#define BM_CLKCTRL_ETM_DIV 0x0000007F 326#define BM_CLKCTRL_ETM_DIV 0x0000007F
@@ -471,7 +333,6 @@
471#define BP_CLKCTRL_ENET_DISABLE 30 333#define BP_CLKCTRL_ENET_DISABLE 30
472#define BM_CLKCTRL_ENET_DISABLE 0x40000000 334#define BM_CLKCTRL_ENET_DISABLE 0x40000000
473#define BM_CLKCTRL_ENET_STATUS 0x20000000 335#define BM_CLKCTRL_ENET_STATUS 0x20000000
474#define BM_CLKCTRL_ENET_RSRVD1 0x10000000
475#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000 336#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000
476#define BP_CLKCTRL_ENET_DIV_TIME 21 337#define BP_CLKCTRL_ENET_DIV_TIME 21
477#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000 338#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000
@@ -493,37 +354,23 @@
493#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000 354#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000
494#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000 355#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000
495#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000 356#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000
496#define BP_CLKCTRL_ENET_RSRVD0 0
497#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF
498#define BF_CLKCTRL_ENET_RSRVD0(v) \
499 (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
500 357
501#define HW_CLKCTRL_HSADC (0x00000150) 358#define HW_CLKCTRL_HSADC (0x00000150)
502 359
503#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
504#define BM_CLKCTRL_HSADC_RESETB 0x40000000 360#define BM_CLKCTRL_HSADC_RESETB 0x40000000
505#define BP_CLKCTRL_HSADC_FREQDIV 28 361#define BP_CLKCTRL_HSADC_FREQDIV 28
506#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000 362#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000
507#define BF_CLKCTRL_HSADC_FREQDIV(v) \ 363#define BF_CLKCTRL_HSADC_FREQDIV(v) \
508 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV) 364 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
509#define BP_CLKCTRL_HSADC_RSRVD1 0
510#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
511#define BF_CLKCTRL_HSADC_RSRVD1(v) \
512 (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
513 365
514#define HW_CLKCTRL_FLEXCAN (0x00000160) 366#define HW_CLKCTRL_FLEXCAN (0x00000160)
515 367
516#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000
517#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30 368#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30
518#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000 369#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000
519#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000 370#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
520#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28 371#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28
521#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000 372#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000
522#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000 373#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
523#define BP_CLKCTRL_FLEXCAN_RSRVD1 0
524#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF
525#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \
526 (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
527 374
528#define HW_CLKCTRL_FRAC0 (0x000001b0) 375#define HW_CLKCTRL_FRAC0 (0x000001b0)
529#define HW_CLKCTRL_FRAC0_SET (0x000001b4) 376#define HW_CLKCTRL_FRAC0_SET (0x000001b4)
@@ -564,10 +411,6 @@
564#define HW_CLKCTRL_FRAC1_CLR (0x000001c8) 411#define HW_CLKCTRL_FRAC1_CLR (0x000001c8)
565#define HW_CLKCTRL_FRAC1_TOG (0x000001cc) 412#define HW_CLKCTRL_FRAC1_TOG (0x000001cc)
566 413
567#define BP_CLKCTRL_FRAC1_RSRVD2 24
568#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
569#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
570 (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
571#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23 414#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23
572#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000 415#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000
573#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000 416#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000
@@ -595,22 +438,10 @@
595#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8) 438#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8)
596#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc) 439#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc)
597 440
598#define BP_CLKCTRL_CLKSEQ_RSRVD0 19
599#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000
600#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
601 (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
602#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000 441#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000
603#define BP_CLKCTRL_CLKSEQ_RSRVD1 15
604#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000
605#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
606 (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
607#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000 442#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000
608#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1 443#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
609#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0 444#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0
610#define BP_CLKCTRL_CLKSEQ_RSRVD2 9
611#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00
612#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \
613 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
614#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 445#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
615#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080 446#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080
616#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040 447#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040
@@ -623,10 +454,6 @@
623 454
624#define HW_CLKCTRL_RESET (0x000001e0) 455#define HW_CLKCTRL_RESET (0x000001e0)
625 456
626#define BP_CLKCTRL_RESET_RSRVD 6
627#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0
628#define BF_CLKCTRL_RESET_RSRVD(v) \
629 (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
630#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020 457#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020
631#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010 458#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
632#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008 459#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008
@@ -640,10 +467,6 @@
640#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 467#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
641#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ 468#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
642 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) 469 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
643#define BP_CLKCTRL_STATUS_RSRVD 0
644#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
645#define BF_CLKCTRL_STATUS_RSRVD(v) \
646 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
647 470
648#define HW_CLKCTRL_VERSION (0x00000200) 471#define HW_CLKCTRL_VERSION (0x00000200)
649 472
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 9343d7edd4f..20ec3bddf7c 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -22,6 +22,7 @@
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/module.h>
25 26
26#include <asm/proc-fns.h> 27#include <asm/proc-fns.h>
27#include <asm/system.h> 28#include <asm/system.h>
@@ -135,3 +136,4 @@ error:
135 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); 136 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
136 return -ETIMEDOUT; 137 return -ETIMEDOUT;
137} 138}
139EXPORT_SYMBOL(mxs_reset_block);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e4509bae8fc..2bd4ccfb353 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -811,7 +811,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
811config CACHE_L2X0 811config CACHE_L2X0
812 bool "Enable the L2x0 outer cache controller" 812 bool "Enable the L2x0 outer cache controller"
813 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 813 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
814 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ 814 REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
815 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ 815 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
816 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE 816 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
817 default y 817 default y
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 389f2179501..b0cb4258e38 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -33,6 +33,7 @@ config ARCH_MX3
33config ARCH_MXC91231 33config ARCH_MXC91231
34 bool "MXC91231-based" 34 bool "MXC91231-based"
35 select CPU_V6 35 select CPU_V6
36 select MXC_AVIC
36 help 37 help
37 This enables support for systems based on the Freescale MXC91231 family 38 This enables support for systems based on the Freescale MXC91231 family
38 39
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 5fd20e96876..a1387875a49 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -13,7 +13,6 @@ obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
13obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 13obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
14obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o 14obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
15obj-$(CONFIG_MXC_PWM) += pwm.o 15obj-$(CONFIG_MXC_PWM) += pwm.o
16obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
17obj-$(CONFIG_MXC_ULPI) += ulpi.o 16obj-$(CONFIG_MXC_ULPI) += ulpi.o
18obj-$(CONFIG_MXC_USE_EPIT) += epit.o 17obj-$(CONFIG_MXC_USE_EPIT) += epit.o
19obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o 18obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index e9bcefe79a4..eee1b6096a0 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -81,6 +81,8 @@ struct platform_device *__init imx_add_platform_device_dmamask(
81 ret = platform_device_add(pdev); 81 ret = platform_device_add(pdev);
82 if (ret) { 82 if (ret) {
83err: 83err:
84 if (dmamask)
85 kfree(pdev->dev.dma_mask);
84 platform_device_put(pdev); 86 platform_device_put(pdev);
85 return ERR_PTR(ret); 87 return ERR_PTR(ret);
86 } 88 }
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index b50c3517d08..6561c9df5f0 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -31,6 +31,11 @@ const struct imx_fec_data imx35_fec_data __initconst =
31 imx_fec_data_entry_single(MX35); 31 imx_fec_data_entry_single(MX35);
32#endif 32#endif
33 33
34#ifdef CONFIG_SOC_IMX50
35const struct imx_fec_data imx50_fec_data __initconst =
36 imx_fec_data_entry_single(MX50);
37#endif
38
34#ifdef CONFIG_SOC_IMX51 39#ifdef CONFIG_SOC_IMX51
35const struct imx_fec_data imx51_fec_data __initconst = 40const struct imx_fec_data imx51_fec_data __initconst =
36 imx_fec_data_entry_single(MX51); 41 imx_fec_data_entry_single(MX51);
@@ -57,7 +62,7 @@ struct platform_device *__init imx_add_fec(
57 }, 62 },
58 }; 63 };
59 64
60 return imx_add_platform_device("fec", 0 /* -1? */, 65 return imx_add_platform_device_dmamask("fec", 0,
61 res, ARRAY_SIZE(res), 66 res, ARRAY_SIZE(res),
62 pdata, sizeof(*pdata)); 67 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
63} 68}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index 33530d2d5ed..3538b85ede9 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -94,7 +94,7 @@ static struct sdma_script_start_addrs addr_imx25_to1 = {
94}; 94};
95#endif 95#endif
96 96
97#ifdef CONFIG_ARCH_MX31 97#ifdef CONFIG_SOC_IMX31
98static struct sdma_script_start_addrs addr_imx31_to1 = { 98static struct sdma_script_start_addrs addr_imx31_to1 = {
99 .per_2_per_addr = 1677, 99 .per_2_per_addr = 1677,
100}; 100};
@@ -106,7 +106,7 @@ static struct sdma_script_start_addrs addr_imx31_to2 = {
106}; 106};
107#endif 107#endif
108 108
109#ifdef CONFIG_ARCH_MX35 109#ifdef CONFIG_SOC_IMX35
110static struct sdma_script_start_addrs addr_imx35_to1 = { 110static struct sdma_script_start_addrs addr_imx35_to1 = {
111 .ap_2_ap_addr = 642, 111 .ap_2_ap_addr = 642,
112 .uart_2_mcu_addr = 817, 112 .uart_2_mcu_addr = 817,
@@ -194,7 +194,7 @@ static int __init imxXX_add_imx_dma(void)
194 } else 194 } else
195#endif 195#endif
196 196
197#if defined(CONFIG_ARCH_MX51) 197#if defined(CONFIG_SOC_IMX51)
198 if (cpu_is_mx51()) { 198 if (cpu_is_mx51()) {
199 imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1; 199 imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1;
200 ret = imx_add_imx_sdma(&imx51_imx_sdma_data); 200 ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c
index 6100a7d824d..79a1cb18a5b 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-fb.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c
@@ -16,6 +16,11 @@
16 .irq = soc ## _INT_LCDC, \ 16 .irq = soc ## _INT_LCDC, \
17 } 17 }
18 18
19#ifdef CONFIG_SOC_IMX1
20const struct imx_imx_fb_data imx1_imx_fb_data __initconst =
21 imx_imx_fb_data_entry_single(MX1, SZ_4K);
22#endif /* ifdef CONFIG_SOC_IMX1 */
23
19#ifdef CONFIG_SOC_IMX21 24#ifdef CONFIG_SOC_IMX21
20const struct imx_imx_fb_data imx21_imx_fb_data __initconst = 25const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
21 imx_imx_fb_data_entry_single(MX21, SZ_4K); 26 imx_imx_fb_data_entry_single(MX21, SZ_4K);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 7ba94e1bbda..2ab74f0da9a 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -69,6 +69,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
69}; 69};
70#endif /* ifdef CONFIG_SOC_IMX35 */ 70#endif /* ifdef CONFIG_SOC_IMX35 */
71 71
72#ifdef CONFIG_SOC_IMX50
73const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
74#define imx50_imx_i2c_data_entry(_id, _hwid) \
75 imx_imx_i2c_data_entry(MX50, _id, _hwid, SZ_4K)
76 imx50_imx_i2c_data_entry(0, 1),
77 imx50_imx_i2c_data_entry(1, 2),
78 imx50_imx_i2c_data_entry(2, 3),
79};
80#endif /* ifdef CONFIG_SOC_IMX51 */
81
72#ifdef CONFIG_SOC_IMX51 82#ifdef CONFIG_SOC_IMX51
73const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { 83const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
74#define imx51_imx_i2c_data_entry(_id, _hwid) \ 84#define imx51_imx_i2c_data_entry(_id, _hwid) \
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
index e0aec61177f..5e07ef2bf1c 100644
--- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
+++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
@@ -53,6 +53,15 @@ const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
53}; 53};
54#endif /* ifdef CONFIG_SOC_IMX51 */ 54#endif /* ifdef CONFIG_SOC_IMX51 */
55 55
56#ifdef CONFIG_SOC_IMX53
57const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = {
58#define imx53_imx2_wdt_data_entry(_id, _hwid) \
59 imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K)
60 imx53_imx2_wdt_data_entry(0, 1),
61 imx53_imx2_wdt_data_entry(1, 2),
62};
63#endif /* ifdef CONFIG_SOC_IMX53 */
64
56struct platform_device *__init imx_add_imx2_wdt( 65struct platform_device *__init imx_add_imx2_wdt(
57 const struct imx_imx2_wdt_data *data) 66 const struct imx_imx2_wdt_data *data)
58{ 67{
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 013c85f20b5..f4a60ab6763 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -21,6 +21,15 @@
21#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \ 21#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \
22 [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size) 22 [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
23 23
24#ifdef CONFIG_SOC_IMX1
25const struct imx_spi_imx_data imx1_cspi_data[] __initconst = {
26#define imx1_cspi_data_entry(_id, _hwid) \
27 imx_spi_imx_data_entry(MX1, CSPI, "imx1-cspi", _id, _hwid, SZ_4K)
28 imx1_cspi_data_entry(0, 1),
29 imx1_cspi_data_entry(1, 2),
30};
31#endif
32
24#ifdef CONFIG_SOC_IMX21 33#ifdef CONFIG_SOC_IMX21
25const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { 34const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
26#define imx21_cspi_data_entry(_id, _hwid) \ 35#define imx21_cspi_data_entry(_id, _hwid) \
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
deleted file mode 100644
index 8772ce346a5..00000000000
--- a/arch/arm/plat-mxc/ehci.c
+++ /dev/null
@@ -1,369 +0,0 @@
1/*
2 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20#include <mach/mxc_ehci.h>
21
22#define USBCTRL_OTGBASE_OFFSET 0x600
23
24#define MX31_OTG_SIC_SHIFT 29
25#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
26#define MX31_OTG_PM_BIT (1 << 24)
27
28#define MX31_H2_SIC_SHIFT 21
29#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
30#define MX31_H2_PM_BIT (1 << 16)
31#define MX31_H2_DT_BIT (1 << 5)
32
33#define MX31_H1_SIC_SHIFT 13
34#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
35#define MX31_H1_PM_BIT (1 << 8)
36#define MX31_H1_DT_BIT (1 << 4)
37
38#define MX35_OTG_SIC_SHIFT 29
39#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
40#define MX35_OTG_PM_BIT (1 << 24)
41
42#define MX35_H1_SIC_SHIFT 21
43#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
44#define MX35_H1_PM_BIT (1 << 8)
45#define MX35_H1_IPPUE_UP_BIT (1 << 7)
46#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
47#define MX35_H1_TLL_BIT (1 << 5)
48#define MX35_H1_USBTE_BIT (1 << 4)
49
50#define MXC_OTG_OFFSET 0
51#define MXC_H1_OFFSET 0x200
52#define MXC_H2_OFFSET 0x400
53
54/* USB_CTRL */
55#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
56#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
57#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
58#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
59#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
60
61/* USB_PHY_CTRL_FUNC */
62#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
63#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
64
65/* USBH2CTRL */
66#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
67#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
68#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
69
70#define MXC_USBCMD_OFFSET 0x140
71
72/* USBCMD */
73#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
74
75int mxc_initialize_usb_hw(int port, unsigned int flags)
76{
77 unsigned int v;
78#if defined(CONFIG_SOC_IMX25)
79 if (cpu_is_mx25()) {
80 v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
81 USBCTRL_OTGBASE_OFFSET));
82
83 switch (port) {
84 case 0: /* OTG port */
85 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
86 v |= (flags & MXC_EHCI_INTERFACE_MASK)
87 << MX35_OTG_SIC_SHIFT;
88 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
89 v |= MX35_OTG_PM_BIT;
90
91 break;
92 case 1: /* H1 port */
93 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
94 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
95 v |= (flags & MXC_EHCI_INTERFACE_MASK)
96 << MX35_H1_SIC_SHIFT;
97 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
98 v |= MX35_H1_PM_BIT;
99
100 if (!(flags & MXC_EHCI_TTL_ENABLED))
101 v |= MX35_H1_TLL_BIT;
102
103 if (flags & MXC_EHCI_INTERNAL_PHY)
104 v |= MX35_H1_USBTE_BIT;
105
106 if (flags & MXC_EHCI_IPPUE_DOWN)
107 v |= MX35_H1_IPPUE_DOWN_BIT;
108
109 if (flags & MXC_EHCI_IPPUE_UP)
110 v |= MX35_H1_IPPUE_UP_BIT;
111
112 break;
113 default:
114 return -EINVAL;
115 }
116
117 writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
118 USBCTRL_OTGBASE_OFFSET));
119 return 0;
120 }
121#endif /* if defined(CONFIG_SOC_IMX25) */
122#if defined(CONFIG_ARCH_MX3)
123 if (cpu_is_mx31()) {
124 v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
125 USBCTRL_OTGBASE_OFFSET));
126
127 switch (port) {
128 case 0: /* OTG port */
129 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
130 v |= (flags & MXC_EHCI_INTERFACE_MASK)
131 << MX31_OTG_SIC_SHIFT;
132 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
133 v |= MX31_OTG_PM_BIT;
134
135 break;
136 case 1: /* H1 port */
137 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
138 v |= (flags & MXC_EHCI_INTERFACE_MASK)
139 << MX31_H1_SIC_SHIFT;
140 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
141 v |= MX31_H1_PM_BIT;
142
143 if (!(flags & MXC_EHCI_TTL_ENABLED))
144 v |= MX31_H1_DT_BIT;
145
146 break;
147 case 2: /* H2 port */
148 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
149 v |= (flags & MXC_EHCI_INTERFACE_MASK)
150 << MX31_H2_SIC_SHIFT;
151 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
152 v |= MX31_H2_PM_BIT;
153
154 if (!(flags & MXC_EHCI_TTL_ENABLED))
155 v |= MX31_H2_DT_BIT;
156
157 break;
158 default:
159 return -EINVAL;
160 }
161
162 writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
163 USBCTRL_OTGBASE_OFFSET));
164 return 0;
165 }
166
167 if (cpu_is_mx35()) {
168 v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
169 USBCTRL_OTGBASE_OFFSET));
170
171 switch (port) {
172 case 0: /* OTG port */
173 v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
174 v |= (flags & MXC_EHCI_INTERFACE_MASK)
175 << MX35_OTG_SIC_SHIFT;
176 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
177 v |= MX35_OTG_PM_BIT;
178
179 break;
180 case 1: /* H1 port */
181 v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
182 MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
183 v |= (flags & MXC_EHCI_INTERFACE_MASK)
184 << MX35_H1_SIC_SHIFT;
185 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
186 v |= MX35_H1_PM_BIT;
187
188 if (!(flags & MXC_EHCI_TTL_ENABLED))
189 v |= MX35_H1_TLL_BIT;
190
191 if (flags & MXC_EHCI_INTERNAL_PHY)
192 v |= MX35_H1_USBTE_BIT;
193
194 if (flags & MXC_EHCI_IPPUE_DOWN)
195 v |= MX35_H1_IPPUE_DOWN_BIT;
196
197 if (flags & MXC_EHCI_IPPUE_UP)
198 v |= MX35_H1_IPPUE_UP_BIT;
199
200 break;
201 default:
202 return -EINVAL;
203 }
204
205 writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
206 USBCTRL_OTGBASE_OFFSET));
207 return 0;
208 }
209#endif /* CONFIG_ARCH_MX3 */
210#ifdef CONFIG_MACH_MX27
211 if (cpu_is_mx27()) {
212 /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
213 * are identical
214 */
215 v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
216 USBCTRL_OTGBASE_OFFSET));
217 switch (port) {
218 case 0: /* OTG port */
219 v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
220 v |= (flags & MXC_EHCI_INTERFACE_MASK)
221 << MX31_OTG_SIC_SHIFT;
222 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
223 v |= MX31_OTG_PM_BIT;
224 break;
225 case 1: /* H1 port */
226 v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
227 v |= (flags & MXC_EHCI_INTERFACE_MASK)
228 << MX31_H1_SIC_SHIFT;
229 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
230 v |= MX31_H1_PM_BIT;
231
232 if (!(flags & MXC_EHCI_TTL_ENABLED))
233 v |= MX31_H1_DT_BIT;
234
235 break;
236 case 2: /* H2 port */
237 v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
238 v |= (flags & MXC_EHCI_INTERFACE_MASK)
239 << MX31_H2_SIC_SHIFT;
240 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
241 v |= MX31_H2_PM_BIT;
242
243 if (!(flags & MXC_EHCI_TTL_ENABLED))
244 v |= MX31_H2_DT_BIT;
245
246 break;
247 default:
248 return -EINVAL;
249 }
250 writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
251 USBCTRL_OTGBASE_OFFSET));
252 return 0;
253 }
254#endif /* CONFIG_MACH_MX27 */
255#ifdef CONFIG_SOC_IMX51
256 if (cpu_is_mx51()) {
257 void __iomem *usb_base;
258 void __iomem *usbotg_base;
259 void __iomem *usbother_base;
260 int ret = 0;
261
262 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
263 if (!usb_base) {
264 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
265 return -ENOMEM;
266 }
267
268 switch (port) {
269 case 0: /* OTG port */
270 usbotg_base = usb_base + MXC_OTG_OFFSET;
271 break;
272 case 1: /* Host 1 port */
273 usbotg_base = usb_base + MXC_H1_OFFSET;
274 break;
275 case 2: /* Host 2 port */
276 usbotg_base = usb_base + MXC_H2_OFFSET;
277 break;
278 default:
279 printk(KERN_ERR"%s no such port %d\n", __func__, port);
280 ret = -ENOENT;
281 goto error;
282 }
283 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
284
285 switch (port) {
286 case 0: /*OTG port */
287 if (flags & MXC_EHCI_INTERNAL_PHY) {
288 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
289
290 if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
291 /* OC/USBPWR is not used */
292 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
293 } else {
294 /* OC/USBPWR is used */
295 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
296 }
297 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
298
299 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
300 if (flags & MXC_EHCI_WAKEUP_ENABLED)
301 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
302 else
303 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
304 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
305 v |= MXC_OTG_UCTRL_OPM_BIT;
306 else
307 v &= ~MXC_OTG_UCTRL_OPM_BIT;
308 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
309 }
310 break;
311 case 1: /* Host 1 */
312 /*Host ULPI */
313 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
314 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
315 /* HOST1 wakeup/ULPI intr enable */
316 v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
317 } else {
318 /* HOST1 wakeup/ULPI intr disable */
319 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
320 }
321
322 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
323 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
324 else
325 v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
326 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
327
328 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
329 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
330 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
331 else
332 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
333 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
334
335 v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
336 if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
337 /* Interrupt Threshold Control:Immediate (no threshold) */
338 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
339 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
340 break;
341 case 2: /* Host 2 ULPI */
342 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
343 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
344 /* HOST1 wakeup/ULPI intr enable */
345 v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
346 } else {
347 /* HOST1 wakeup/ULPI intr disable */
348 v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
349 }
350
351 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
352 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
353 else
354 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
355 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
356 break;
357 }
358
359error:
360 iounmap(usb_base);
361 return ret;
362 }
363#endif
364 printk(KERN_WARNING
365 "%s() unable to setup USBCONTROL for this CPU\n", __func__);
366 return -EINVAL;
367}
368EXPORT_SYMBOL(mxc_initialize_usb_hw);
369
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index d17b3c996b8..57d59855f9e 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -233,6 +233,7 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
233} 233}
234 234
235static struct irq_chip gpio_irq_chip = { 235static struct irq_chip gpio_irq_chip = {
236 .name = "GPIO",
236 .irq_ack = gpio_ack_irq, 237 .irq_ack = gpio_ack_irq,
237 .irq_mask = gpio_mask_irq, 238 .irq_mask = gpio_mask_irq,
238 .irq_unmask = gpio_unmask_irq, 239 .irq_unmask = gpio_unmask_irq,
@@ -349,113 +350,3 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
349 350
350 return 0; 351 return 0;
351} 352}
352
353#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
354 { \
355 .chip.label = "gpio-" #_id, \
356 .irq = _irq, \
357 .irq_high = _irq_high, \
358 .base = soc ## _IO_ADDRESS( \
359 soc ## _GPIO ## _hwid ## _BASE_ADDR), \
360 .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
361 }
362
363#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
364 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
365#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
366 DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
367
368#define DEFINE_REGISTER_FUNCTION(prefix) \
369int __init prefix ## _register_gpios(void) \
370{ \
371 return mxc_gpio_init(prefix ## _gpio_ports, \
372 ARRAY_SIZE(prefix ## _gpio_ports)); \
373}
374
375#if defined(CONFIG_SOC_IMX1)
376static struct mxc_gpio_port imx1_gpio_ports[] = {
377 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
378 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
379 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
380 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
381};
382
383DEFINE_REGISTER_FUNCTION(imx1)
384
385#endif /* if defined(CONFIG_SOC_IMX1) */
386
387#if defined(CONFIG_SOC_IMX21)
388static struct mxc_gpio_port imx21_gpio_ports[] = {
389 DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
390 DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
391 DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
392 DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
393 DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
394 DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
395};
396
397DEFINE_REGISTER_FUNCTION(imx21)
398
399#endif /* if defined(CONFIG_SOC_IMX21) */
400
401#if defined(CONFIG_SOC_IMX25)
402static struct mxc_gpio_port imx25_gpio_ports[] = {
403 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
404 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
405 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
406 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
407};
408
409DEFINE_REGISTER_FUNCTION(imx25)
410
411#endif /* if defined(CONFIG_SOC_IMX25) */
412
413#if defined(CONFIG_SOC_IMX27)
414static struct mxc_gpio_port imx27_gpio_ports[] = {
415 DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
416 DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
417 DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
418 DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
419 DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
420 DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
421};
422
423DEFINE_REGISTER_FUNCTION(imx27)
424
425#endif /* if defined(CONFIG_SOC_IMX27) */
426
427#if defined(CONFIG_SOC_IMX31)
428static struct mxc_gpio_port imx31_gpio_ports[] = {
429 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
430 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
431 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
432};
433
434DEFINE_REGISTER_FUNCTION(imx31)
435
436#endif /* if defined(CONFIG_SOC_IMX31) */
437
438#if defined(CONFIG_SOC_IMX35)
439static struct mxc_gpio_port imx35_gpio_ports[] = {
440 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
441 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
442 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
443};
444
445DEFINE_REGISTER_FUNCTION(imx35)
446
447#endif /* if defined(CONFIG_SOC_IMX35) */
448
449#if defined(CONFIG_SOC_IMX50)
450static struct mxc_gpio_port imx50_gpio_ports[] = {
451 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
452 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
453 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
454 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
455 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
456 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
457};
458
459DEFINE_REGISTER_FUNCTION(imx50)
460
461#endif /* if defined(CONFIG_SOC_IMX50) */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index aea2cd3b6d1..a22ebe11a60 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -24,6 +24,16 @@ extern void mx50_map_io(void);
24extern void mx51_map_io(void); 24extern void mx51_map_io(void);
25extern void mx53_map_io(void); 25extern void mx53_map_io(void);
26extern void mxc91231_map_io(void); 26extern void mxc91231_map_io(void);
27extern void imx1_init_early(void);
28extern void imx21_init_early(void);
29extern void imx25_init_early(void);
30extern void imx27_init_early(void);
31extern void imx31_init_early(void);
32extern void imx35_init_early(void);
33extern void imx50_init_early(void);
34extern void imx51_init_early(void);
35extern void imx53_init_early(void);
36extern void mxc91231_init_early(void);
27extern void mxc_init_irq(void __iomem *); 37extern void mxc_init_irq(void __iomem *);
28extern void tzic_init_irq(void __iomem *); 38extern void tzic_init_irq(void __iomem *);
29extern void mx1_init_irq(void); 39extern void mx1_init_irq(void);
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 0044e2f1bea..a2747f12813 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -46,6 +46,21 @@ struct mxc_gpio_port {
46 spinlock_t lock; 46 spinlock_t lock;
47}; 47};
48 48
49#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
50 { \
51 .chip.label = "gpio-" #_id, \
52 .irq = _irq, \
53 .irq_high = _irq_high, \
54 .base = soc ## _IO_ADDRESS( \
55 soc ## _GPIO ## _hwid ## _BASE_ADDR), \
56 .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
57 }
58
59#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
60 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
61#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
62 DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
63
49int mxc_gpio_init(struct mxc_gpio_port*, int); 64int mxc_gpio_init(struct mxc_gpio_port*, int);
50 65
51#endif 66#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index cbaed295a2b..c92f0b1f216 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -112,12 +112,12 @@ enum iomux_gp_func {
112 * - setups the iomux according to the configuration 112 * - setups the iomux according to the configuration
113 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib 113 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
114 */ 114 */
115int mxc_iomux_alloc_pin(const unsigned int pin, const char *label); 115int mxc_iomux_alloc_pin(unsigned int pin, const char *label);
116/* 116/*
117 * setups mutliple pins 117 * setups mutliple pins
118 * convenient way to call the above function with tables 118 * convenient way to call the above function with tables
119 */ 119 */
120int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, 120int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
121 const char *label); 121 const char *label);
122 122
123/* 123/*
@@ -126,12 +126,12 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
126 * - frees the GPIO if the pin was configured as GPIO 126 * - frees the GPIO if the pin was configured as GPIO
127 * - DOES NOT reconfigure the IOMUX in its reset state 127 * - DOES NOT reconfigure the IOMUX in its reset state
128 */ 128 */
129void mxc_iomux_release_pin(const unsigned int pin); 129void mxc_iomux_release_pin(unsigned int pin);
130/* 130/*
131 * releases multiple pins 131 * releases multiple pins
132 * convenvient way to call the above function with tables 132 * convenvient way to call the above function with tables
133 */ 133 */
134void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count); 134void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
135 135
136/* 136/*
137 * This function enables/disables the general purpose function for a particular 137 * This function enables/disables the general purpose function for a particular
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
index 2a24bae1b87..3117c18bbbd 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h
@@ -989,13 +989,13 @@
989#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL) 989#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL)
990#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL) 990#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL)
991 991
992#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6e8, 0x288, 0, 0x0, 0, NO_PAD_CTRL) 992#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
993#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL) 993#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL)
994#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) 994#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL)
995#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) 995#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL)
996#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL) 996#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL)
997#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6e8, 0x288, 6, 0x0, 0, NO_PAD_CTRL) 997#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL)
998#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6e8, 0x288, 7, 0x0, 0, NO_PAD_CTRL) 998#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL)
999 999
1000#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL) 1000#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL)
1001#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL) 1001#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
index 058a922ca14..98e7fd0b908 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx50.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
@@ -86,7 +86,7 @@
86#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \ 86#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
87 MX50_I2C_PAD_CTRL) 87 MX50_I2C_PAD_CTRL)
88#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL) 88#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
89#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL) 89#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x0, 0, MX50_UART_PAD_CTRL)
90 90
91#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \ 91#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
92 MX50_I2C_PAD_CTRL) 92 MX50_I2C_PAD_CTRL)
@@ -96,7 +96,7 @@
96#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \ 96#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
97 MX50_I2C_PAD_CTRL) 97 MX50_I2C_PAD_CTRL)
98#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL) 98#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL) 99#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x0, 0, MX50_UART_PAD_CTRL)
100#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL) 100#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
101 101
102#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \ 102#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
@@ -172,7 +172,7 @@
172 172
173#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL) 173#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
174#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL) 174#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
175#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL) 175#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
176#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL) 176#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
177#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD) 177#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
178#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH) 178#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
@@ -186,25 +186,25 @@
186#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL) 186#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
187#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL) 187#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
188 188
189#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL) 189#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x0, 0, MX50_UART_PAD_CTRL)
190#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL) 190#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
191 191
192#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL) 192#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
193#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL) 193#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
194 194
195#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL) 195#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
196#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL) 196#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
197#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL) 197#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x0, 0, MX50_UART_PAD_CTRL)
198#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL) 198#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
199#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL) 199#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
200 200
201#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL) 201#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
202#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL) 202#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
203#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL) 203#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
204#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL) 204#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x764, 0, MX50_SD_PAD_CTRL)
205#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL) 205#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x748, 0, MX50_SD_PAD_CTRL)
206 206
207#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL) 207#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x0, 0, MX50_UART_PAD_CTRL)
208#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL) 208#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
209#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL) 209#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
210#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL) 210#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
@@ -214,7 +214,7 @@
214#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL) 214#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
215#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL) 215#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
216 216
217#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL) 217#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x0, 0, MX50_UART_PAD_CTRL)
218#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL) 218#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
219#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL) 219#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
220#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL) 220#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
@@ -224,7 +224,7 @@
224#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL) 224#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
225#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL) 225#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
226 226
227#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL) 227#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x0, 0, MX50_UART_PAD_CTRL)
228#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL) 228#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
229#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL) 229#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
230#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL) 230#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
@@ -238,9 +238,9 @@
238#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL) 238#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
239#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL) 239#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
240 240
241#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL) 241#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x0, 0, MX50_UART_PAD_CTRL)
242#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) 242#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
243#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL) 243#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x0, 0, MX50_UART_PAD_CTRL)
244#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL) 244#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
245#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL) 245#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
246#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL) 246#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
@@ -278,7 +278,7 @@
278#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL) 278#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
279#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD) 279#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
280#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD) 280#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
281#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL) 281#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
282#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL) 282#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
283#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL) 283#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
284 284
@@ -294,7 +294,7 @@
294#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) 294#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
295#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD) 295#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
296#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD) 296#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
297#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL) 297#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x0, 0, MX50_UART_PAD_CTRL)
298#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL) 298#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
299#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL) 299#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
300 300
@@ -311,17 +311,17 @@
311#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL) 311#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
312#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL) 312#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
313#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD) 313#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
314#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL) 314#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x0, 0, MX50_UART_PAD_CTRL)
315#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL) 315#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
316#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL) 316#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
317#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL) 317#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
318 318
319#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL) 319#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
320#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP) 320#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
321#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL) 321#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
322#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD) 322#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
323#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL) 323#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x0, 0, MX50_UART_PAD_CTRL)
324#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL) 324#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x73c, 0, NO_PAD_CTRL)
325#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL) 325#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
326#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL) 326#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
327 327
@@ -503,7 +503,7 @@
503#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL) 503#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
504#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL) 504#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
505 505
506#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) 506#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
507#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL) 507#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
508#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL) 508#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
509#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL) 509#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
@@ -691,8 +691,8 @@
691 691
692#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) 692#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
693#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL) 693#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
694#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL) 694#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x810, 2, NO_PAD_CTRL)
695#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL) 695#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
696 696
697#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) 697#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
698#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL) 698#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index b6767f90ef1..df6acc066fb 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -473,7 +473,7 @@
473#define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0) 473#define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0)
474#define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0) 474#define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0)
475#define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0) 475#define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0)
476#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0) 476#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x0000, 0, 0)
477#define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0) 477#define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0)
478#define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0) 478#define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0)
479#define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0) 479#define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0)
@@ -528,7 +528,7 @@
528#define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0) 528#define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0)
529#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0) 529#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0)
530#define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0) 530#define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0)
531#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0) 531#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x0000, 0, 0)
532#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0) 532#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0)
533#define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0) 533#define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0)
534#define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0) 534#define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0)
@@ -985,11 +985,11 @@
985#define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 985#define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
986#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) 986#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
987#define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL)) 987#define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
988#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 988#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
989#define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 989#define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
990#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)) 990#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
991#define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL)) 991#define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
992#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 992#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
993#define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 993#define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
994#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)) 994#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
995#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL)) 995#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -999,18 +999,18 @@
999#define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 999#define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1000#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)) 1000#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1001#define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL)) 1001#define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
1002#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1002#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1003#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1003#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1004#define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1004#define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1005#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1005#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1006#define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL)) 1006#define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
1007#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1007#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1008#define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1008#define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1009#define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1009#define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1010#define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1010#define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1011#define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1011#define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1012#define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL)) 1012#define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
1013#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) 1013#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1014#define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL)) 1014#define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
1015#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1015#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1016#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2)) 1016#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
@@ -1036,41 +1036,41 @@
1036#define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1036#define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1037#define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1037#define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1038#define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1038#define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1039#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) 1039#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1040#define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) 1040#define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1041#define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) 1041#define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1042#define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1042#define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1043#define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1043#define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1044#define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1044#define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1045#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1045#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1046#define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) 1046#define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1047#define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) 1047#define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1048#define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1048#define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1049#define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1049#define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1050#define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1050#define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1051#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1051#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1052#define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL)) 1052#define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
1053#define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) 1053#define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1054#define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1054#define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1055#define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1055#define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1056#define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1056#define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1057#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1057#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1058#define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL)) 1058#define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
1059#define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1059#define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1060#define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) 1060#define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1061#define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1061#define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1062#define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1062#define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1063#define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1063#define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1064#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1064#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1065#define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5)) 1065#define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1066#define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1066#define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1067#define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1067#define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1068#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)) 1068#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1069#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1069#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1070#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4)) 1070#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
1071#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1071#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1072#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL)) 1072#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
1073#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL)) 1073#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1074#define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1074#define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1075#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL)) 1075#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1076#define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1076#define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1479,26 +1479,26 @@
1479#define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) 1479#define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1480#define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL)) 1480#define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1481#define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1481#define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1482#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1482#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1483#define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1483#define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1484#define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1484#define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1485#define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1485#define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1486#define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1486#define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1487#define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL)) 1487#define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1488#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1488#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1489#define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1489#define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1490#define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1490#define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1491#define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1491#define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1492#define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1492#define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1493#define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)) 1493#define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1494#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1494#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1495#define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1495#define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1496#define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1496#define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1497#define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1497#define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1498#define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1498#define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1499#define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL)) 1499#define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1500#define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1500#define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1501#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1501#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1502#define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1502#define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1503#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1503#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1504#define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL)) 1504#define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
@@ -1517,16 +1517,16 @@
1517#define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)) 1517#define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1518#define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1518#define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1519#define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1519#define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1520#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1520#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1521#define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1521#define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1522#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1522#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1523#define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL)) 1523#define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1524#define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1524#define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1525#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1525#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1526#define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL)) 1526#define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1527#define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL)) 1527#define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1528#define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1528#define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1529#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1529#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1530#define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1530#define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1531#define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL)) 1531#define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1532#define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL)) 1532#define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 68e11d7ab79..e95d9cb8aeb 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by 5 * it under the terms of the GNU General Public License as published by
@@ -21,305 +21,2358 @@
21 21
22#include <mach/iomux-v3.h> 22#include <mach/iomux-v3.h>
23 23
24/*
25 * various IOMUX alternate output functions (1-7)
26 */
27typedef enum iomux_config {
28 IOMUX_CONFIG_ALT0,
29 IOMUX_CONFIG_ALT1,
30 IOMUX_CONFIG_ALT2,
31 IOMUX_CONFIG_ALT3,
32 IOMUX_CONFIG_ALT4,
33 IOMUX_CONFIG_ALT5,
34 IOMUX_CONFIG_ALT6,
35 IOMUX_CONFIG_ALT7,
36 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
37} iomux_pin_cfg_t;
38
39/* These 2 defines are for pins that may not have a mux register, but could 24/* These 2 defines are for pins that may not have a mux register, but could
40 * have a pad setting register, and vice-versa. */ 25 * have a pad setting register, and vice-versa. */
41#define NON_MUX_I 0x00
42#define NON_PAD_I 0x00 26#define NON_PAD_I 0x00
43 27
44#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 28#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
45 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 29 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46/* UART1 */ 30#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
47#define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL) 31 PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
48#define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL) 32 PAD_CTL_SRE_FAST)
49#define MX53_PAD_ATA_DIOW__UART1_TXD IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL)
50#define MX53_PAD_ATA_DMACK__UART1_RXD IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL)
51
52/* UART2 */
53#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
54#define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL)
55#define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
56#define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL)
57 33
58/* UART3 */ 34#define _MX53_PAD_GPIO_19__KPP_COL_5 IOMUX_PAD(0x348, 0x20, 0, 0x840, 0, 0)
59#define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL) 35#define _MX53_PAD_GPIO_19__GPIO4_5 IOMUX_PAD(0x348, 0x20, 1, 0x0, 0, 0)
60#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL) 36#define _MX53_PAD_GPIO_19__CCM_CLKO IOMUX_PAD(0x348, 0x20, 2, 0x0, 0, 0)
61#define MX53_PAD_ATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL) 37#define _MX53_PAD_GPIO_19__SPDIF_OUT1 IOMUX_PAD(0x348, 0x20, 3, 0x0, 0, 0)
62#define MX53_PAD_ATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL) 38#define _MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 IOMUX_PAD(0x348, 0x20, 4, 0x0, 0, 0)
39#define _MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0)
40#define _MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0)
41#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0)
42#define _MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x24, o, 0x0, 0, 0)
43#define _MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0)
44#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0)
45#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x24, 4, 0x890, 0, 0)
46#define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0)
47#define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0)
48#define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0)
49#define _MX53_PAD_KEY_ROW0__KPP_ROW_0 IOMUX_PAD(0x350, 0x28, 0, 0x0, 0, 0)
50#define _MX53_PAD_KEY_ROW0__GPIO4_7 IOMUX_PAD(0x350, 0x28, 1, 0x0, 0, 0)
51#define _MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD IOMUX_PAD(0x350, 0x28, 2, 0x74C, 0, 0)
52#define _MX53_PAD_KEY_ROW0__UART4_RXD_MUX IOMUX_PAD(0x350, 0x28, 4, 0x890, 1, 0)
53#define _MX53_PAD_KEY_ROW0__ECSPI1_MOSI IOMUX_PAD(0x350, 0x28, 5, 0x7A4, 0, 0)
54#define _MX53_PAD_KEY_ROW0__FEC_TX_ER IOMUX_PAD(0x350, 0x28, 6, 0x0, 0, 0)
55#define _MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0)
56#define _MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0)
57#define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0)
58#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x2C, 4, 0x898, 0, 0)
59#define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0)
60#define _MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0)
61#define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0)
62#define _MX53_PAD_KEY_ROW1__KPP_ROW_1 IOMUX_PAD(0x358, 0x30, 0, 0x0, 0, 0)
63#define _MX53_PAD_KEY_ROW1__GPIO4_9 IOMUX_PAD(0x358, 0x30, 1, 0x0, 0, 0)
64#define _MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD IOMUX_PAD(0x358, 0x30, 2, 0x748, 0, 0)
65#define _MX53_PAD_KEY_ROW1__UART5_RXD_MUX IOMUX_PAD(0x358, 0x30, 4, 0x898, 1, 0)
66#define _MX53_PAD_KEY_ROW1__ECSPI1_SS0 IOMUX_PAD(0x358, 0x30, 5, 0x7A8, 0, 0)
67#define _MX53_PAD_KEY_ROW1__FEC_COL IOMUX_PAD(0x358, 0x30, 6, 0x800, 0, 0)
68#define _MX53_PAD_KEY_ROW1__USBPHY1_RXVALID IOMUX_PAD(0x358, 0x30, 7, 0x0, 0, 0)
69#define _MX53_PAD_KEY_COL2__KPP_COL_2 IOMUX_PAD(0x35C, 0x34, 0, 0x0, 0, 0)
70#define _MX53_PAD_KEY_COL2__GPIO4_10 IOMUX_PAD(0x35C, 0x34, 1, 0x0, 0, 0)
71#define _MX53_PAD_KEY_COL2__CAN1_TXCAN IOMUX_PAD(0x35C, 0x34, 2, 0x0, 0, 0)
72#define _MX53_PAD_KEY_COL2__FEC_MDIO IOMUX_PAD(0x35C, 0x34, 4, 0x804, 0, 0)
73#define _MX53_PAD_KEY_COL2__ECSPI1_SS1 IOMUX_PAD(0x35C, 0x34, 5, 0x7AC, 0, 0)
74#define _MX53_PAD_KEY_COL2__FEC_RDATA_2 IOMUX_PAD(0x35C, 0x34, 6, 0x0, 0, 0)
75#define _MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE IOMUX_PAD(0x35C, 0x34, 7, 0x0, 0, 0)
76#define _MX53_PAD_KEY_ROW2__KPP_ROW_2 IOMUX_PAD(0x360, 0x38, 0, 0x0, 0, 0)
77#define _MX53_PAD_KEY_ROW2__GPIO4_11 IOMUX_PAD(0x360, 0x38, 1, 0x0, 0, 0)
78#define _MX53_PAD_KEY_ROW2__CAN1_RXCAN IOMUX_PAD(0x360, 0x38, 2, 0x760, 0, 0)
79#define _MX53_PAD_KEY_ROW2__FEC_MDC IOMUX_PAD(0x360, 0x38, 4, 0x0, 0, 0)
80#define _MX53_PAD_KEY_ROW2__ECSPI1_SS2 IOMUX_PAD(0x360, 0x38, 5, 0x7B0, 0, 0)
81#define _MX53_PAD_KEY_ROW2__FEC_TDATA_2 IOMUX_PAD(0x360, 0x38, 6, 0x0, 0, 0)
82#define _MX53_PAD_KEY_ROW2__USBPHY1_RXERROR IOMUX_PAD(0x360, 0x38, 7, 0x0, 0, 0)
83#define _MX53_PAD_KEY_COL3__KPP_COL_3 IOMUX_PAD(0x364, 0x3C, 0, 0x0, 0, 0)
84#define _MX53_PAD_KEY_COL3__GPIO4_12 IOMUX_PAD(0x364, 0x3C, 1, 0x0, 0, 0)
85#define _MX53_PAD_KEY_COL3__USBOH3_H2_DP IOMUX_PAD(0x364, 0x3C, 2, 0x0, 0, 0)
86#define _MX53_PAD_KEY_COL3__SPDIF_IN1 IOMUX_PAD(0x364, 0x3C, 3, 0x870, 0, 0)
87#define _MX53_PAD_KEY_COL3__I2C2_SCL IOMUX_PAD(0x364, 0x3C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, 0)
88#define _MX53_PAD_KEY_COL3__ECSPI1_SS3 IOMUX_PAD(0x364, 0x3C, 5, 0x7B4, 0, 0)
89#define _MX53_PAD_KEY_COL3__FEC_CRS IOMUX_PAD(0x364, 0x3C, 6, 0x0, 0, 0)
90#define _MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK IOMUX_PAD(0x364, 0x3C, 7, 0x0, 0, 0)
91#define _MX53_PAD_KEY_ROW3__KPP_ROW_3 IOMUX_PAD(0x368, 0x40, 0, 0x0, 0, 0)
92#define _MX53_PAD_KEY_ROW3__GPIO4_13 IOMUX_PAD(0x368, 0x40, 1, 0x0, 0, 0)
93#define _MX53_PAD_KEY_ROW3__USBOH3_H2_DM IOMUX_PAD(0x368, 0x40, 2, 0x0, 0, 0)
94#define _MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK IOMUX_PAD(0x368, 0x40, 3, 0x768, 0, 0)
95#define _MX53_PAD_KEY_ROW3__I2C2_SDA IOMUX_PAD(0x368, 0x40, 4 | IOMUX_CONFIG_SION, 0x820, 0, 0)
96#define _MX53_PAD_KEY_ROW3__OSC32K_32K_OUT IOMUX_PAD(0x368, 0x40, 5, 0x0, 0, 0)
97#define _MX53_PAD_KEY_ROW3__CCM_PLL4_BYP IOMUX_PAD(0x368, 0x40, 6, 0x77C, 0, 0)
98#define _MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 IOMUX_PAD(0x368, 0x40, 7, 0x0, 0, 0)
99#define _MX53_PAD_KEY_COL4__KPP_COL_4 IOMUX_PAD(0x36C, 0x44, 0, 0x0, 0, 0)
100#define _MX53_PAD_KEY_COL4__GPIO4_14 IOMUX_PAD(0x36C, 0x44, 1, 0x0, 0, 0)
101#define _MX53_PAD_KEY_COL4__CAN2_TXCAN IOMUX_PAD(0x36C, 0x44, 2, 0x0, 0, 0)
102#define _MX53_PAD_KEY_COL4__IPU_SISG_4 IOMUX_PAD(0x36C, 0x44, 3, 0x0, 0, 0)
103#define _MX53_PAD_KEY_COL4__UART5_RTS IOMUX_PAD(0x36C, 0x44, 4, 0x894, 0, 0)
104#define _MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC IOMUX_PAD(0x36C, 0x44, 5, 0x89C, 0, 0)
105#define _MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 IOMUX_PAD(0x36C, 0x44, 7, 0x0, 0, 0)
106#define _MX53_PAD_KEY_ROW4__KPP_ROW_4 IOMUX_PAD(0x370, 0x48, 0, 0x0, 0, 0)
107#define _MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0)
108#define _MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0)
109#define _MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0)
110#define _MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x48, 4, 0x894, 1, 0)
111#define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0)
112#define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0)
113#define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0)
114#define _MX53_PAD_DI0_DISP_CLK__GPIO4_16 IOMUX_PAD(0x378, 0x4C, 1, 0x0, 0, 0)
115#define _MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR IOMUX_PAD(0x378, 0x4C, 2, 0x0, 0, 0)
116#define _MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 IOMUX_PAD(0x378, 0x4C, 5, 0x0, 0, 0)
117#define _MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 IOMUX_PAD(0x378, 0x4C, 6, 0x0, 0, 0)
118#define _MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID IOMUX_PAD(0x378, 0x4C, 7, 0x0, 0, 0)
119#define _MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 IOMUX_PAD(0x37C, 0x50, 0, 0x0, 0, 0)
120#define _MX53_PAD_DI0_PIN15__GPIO4_17 IOMUX_PAD(0x37C, 0x50, 1, 0x0, 0, 0)
121#define _MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC IOMUX_PAD(0x37C, 0x50, 2, 0x0, 0, 0)
122#define _MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 IOMUX_PAD(0x37C, 0x50, 5, 0x0, 0, 0)
123#define _MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 IOMUX_PAD(0x37C, 0x50, 6, 0x0, 0, 0)
124#define _MX53_PAD_DI0_PIN15__USBPHY1_BVALID IOMUX_PAD(0x37C, 0x50, 7, 0x0, 0, 0)
125#define _MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 IOMUX_PAD(0x380, 0x54, 0, 0x0, 0, 0)
126#define _MX53_PAD_DI0_PIN2__GPIO4_18 IOMUX_PAD(0x380, 0x54, 1, 0x0, 0, 0)
127#define _MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD IOMUX_PAD(0x380, 0x54, 2, 0x0, 0, 0)
128#define _MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 IOMUX_PAD(0x380, 0x54, 5, 0x0, 0, 0)
129#define _MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 IOMUX_PAD(0x380, 0x54, 6, 0x0, 0, 0)
130#define _MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION IOMUX_PAD(0x380, 0x54, 7, 0x0, 0, 0)
131#define _MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 IOMUX_PAD(0x384, 0x58, 0, 0x0, 0, 0)
132#define _MX53_PAD_DI0_PIN3__GPIO4_19 IOMUX_PAD(0x384, 0x58, 1, 0x0, 0, 0)
133#define _MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x384, 0x58, 2, 0x0, 0, 0)
134#define _MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 IOMUX_PAD(0x384, 0x58, 5, 0x0, 0, 0)
135#define _MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 IOMUX_PAD(0x384, 0x58, 6, 0x0, 0, 0)
136#define _MX53_PAD_DI0_PIN3__USBPHY1_IDDIG IOMUX_PAD(0x384, 0x58, 7, 0x0, 0, 0)
137#define _MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 IOMUX_PAD(0x388, 0x5C, 0, 0x0, 0, 0)
138#define _MX53_PAD_DI0_PIN4__GPIO4_20 IOMUX_PAD(0x388, 0x5C, 1, 0x0, 0, 0)
139#define _MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD IOMUX_PAD(0x388, 0x5C, 2, 0x0, 0, 0)
140#define _MX53_PAD_DI0_PIN4__ESDHC1_WP IOMUX_PAD(0x388, 0x5C, 3, 0x7FC, 0, 0)
141#define _MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD IOMUX_PAD(0x388, 0x5C, 5, 0x0, 0, 0)
142#define _MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 IOMUX_PAD(0x388, 0x5C, 6, 0x0, 0, 0)
143#define _MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT IOMUX_PAD(0x388, 0x5C, 7, 0x0, 0, 0)
144#define _MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 IOMUX_PAD(0x38C, 0x60, 0, 0x0, 0, 0)
145#define _MX53_PAD_DISP0_DAT0__GPIO4_21 IOMUX_PAD(0x38C, 0x60, 1, 0x0, 0, 0)
146#define _MX53_PAD_DISP0_DAT0__CSPI_SCLK IOMUX_PAD(0x38C, 0x60, 2, 0x780, 0, 0)
147#define _MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 IOMUX_PAD(0x38C, 0x60, 3, 0x0, 0, 0)
148#define _MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN IOMUX_PAD(0x38C, 0x60, 5, 0x0, 0, 0)
149#define _MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 IOMUX_PAD(0x38C, 0x60, 6, 0x0, 0, 0)
150#define _MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY IOMUX_PAD(0x38C, 0x60, 7, 0x0, 0, 0)
151#define _MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 IOMUX_PAD(0x390, 0x64, 0, 0x0, 0, 0)
152#define _MX53_PAD_DISP0_DAT1__GPIO4_22 IOMUX_PAD(0x390, 0x64, 1, 0x0, 0, 0)
153#define _MX53_PAD_DISP0_DAT1__CSPI_MOSI IOMUX_PAD(0x390, 0x64, 2, 0x788, 0, 0)
154#define _MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 IOMUX_PAD(0x390, 0x64, 3, 0x0, 0, 0)
155#define _MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x390, 0x64, 5, 0x0, 0, 0)
156#define _MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 IOMUX_PAD(0x390, 0x64, 6, 0x0, 0, 0)
157#define _MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID IOMUX_PAD(0x390, 0x64, 7, 0x0, 0, 0)
158#define _MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 IOMUX_PAD(0x394, 0x68, 0, 0x0, 0, 0)
159#define _MX53_PAD_DISP0_DAT2__GPIO4_23 IOMUX_PAD(0x394, 0x68, 1, 0x0, 0, 0)
160#define _MX53_PAD_DISP0_DAT2__CSPI_MISO IOMUX_PAD(0x394, 0x68, 2, 0x784, 0, 0)
161#define _MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 IOMUX_PAD(0x394, 0x68, 3, 0x0, 0, 0)
162#define _MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE IOMUX_PAD(0x394, 0x68, 5, 0x0, 0, 0)
163#define _MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 IOMUX_PAD(0x394, 0x68, 6, 0x0, 0, 0)
164#define _MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE IOMUX_PAD(0x394, 0x68, 7, 0x0, 0, 0)
165#define _MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 IOMUX_PAD(0x398, 0x6C, 0, 0x0, 0, 0)
166#define _MX53_PAD_DISP0_DAT3__GPIO4_24 IOMUX_PAD(0x398, 0x6C, 1, 0x0, 0, 0)
167#define _MX53_PAD_DISP0_DAT3__CSPI_SS0 IOMUX_PAD(0x398, 0x6C, 2, 0x78C, 0, 0)
168#define _MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 IOMUX_PAD(0x398, 0x6C, 3, 0x0, 0, 0)
169#define _MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x398, 0x6C, 5, 0x0, 0, 0)
170#define _MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 IOMUX_PAD(0x398, 0x6C, 6, 0x0, 0, 0)
171#define _MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR IOMUX_PAD(0x398, 0x6C, 7, 0x0, 0, 0)
172#define _MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 IOMUX_PAD(0x39C, 0x70, 0, 0x0, 0, 0)
173#define _MX53_PAD_DISP0_DAT4__GPIO4_25 IOMUX_PAD(0x39C, 0x70, 1, 0x0, 0, 0)
174#define _MX53_PAD_DISP0_DAT4__CSPI_SS1 IOMUX_PAD(0x39C, 0x70, 2, 0x790, 0, 0)
175#define _MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 IOMUX_PAD(0x39C, 0x70, 3, 0x0, 0, 0)
176#define _MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x39C, 0x70, 5, 0x0, 0, 0)
177#define _MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 IOMUX_PAD(0x39C, 0x70, 6, 0x0, 0, 0)
178#define _MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK IOMUX_PAD(0x39C, 0x70, 7, 0x0, 0, 0)
179#define _MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 IOMUX_PAD(0x3A0, 0x74, 0, 0x0, 0, 0)
180#define _MX53_PAD_DISP0_DAT5__GPIO4_26 IOMUX_PAD(0x3A0, 0x74, 1, 0x0, 0, 0)
181#define _MX53_PAD_DISP0_DAT5__CSPI_SS2 IOMUX_PAD(0x3A0, 0x74, 2, 0x794, 0, 0)
182#define _MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 IOMUX_PAD(0x3A0, 0x74, 3, 0x0, 0, 0)
183#define _MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x3A0, 0x74, 5, 0x0, 0, 0)
184#define _MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 IOMUX_PAD(0x3A0, 0x74, 6, 0x0, 0, 0)
185#define _MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 IOMUX_PAD(0x3A0, 0x74, 7, 0x0, 0, 0)
186#define _MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 IOMUX_PAD(0x3A4, 0x78, 0, 0x0, 0, 0)
187#define _MX53_PAD_DISP0_DAT6__GPIO4_27 IOMUX_PAD(0x3A4, 0x78, 1, 0x0, 0, 0)
188#define _MX53_PAD_DISP0_DAT6__CSPI_SS3 IOMUX_PAD(0x3A4, 0x78, 2, 0x798, 0, 0)
189#define _MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 IOMUX_PAD(0x3A4, 0x78, 3, 0x0, 0, 0)
190#define _MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x3A4, 0x78, 5, 0x0, 0, 0)
191#define _MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 IOMUX_PAD(0x3A4, 0x78, 6, 0x0, 0, 0)
192#define _MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 IOMUX_PAD(0x3A4, 0x78, 7, 0x0, 0, 0)
193#define _MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 IOMUX_PAD(0x3A8, 0x7C, 0, 0x0, 0, 0)
194#define _MX53_PAD_DISP0_DAT7__GPIO4_28 IOMUX_PAD(0x3A8, 0x7C, 1, 0x0, 0, 0)
195#define _MX53_PAD_DISP0_DAT7__CSPI_RDY IOMUX_PAD(0x3A8, 0x7C, 2, 0x0, 0, 0)
196#define _MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 IOMUX_PAD(0x3A8, 0x7C, 3, 0x0, 0, 0)
197#define _MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x7C, 5, 0x0, 0, 0)
198#define _MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 IOMUX_PAD(0x3A8, 0x7C, 6, 0x0, 0, 0)
199#define _MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID IOMUX_PAD(0x3A8, 0x7C, 7, 0x0, 0, 0)
200#define _MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 IOMUX_PAD(0x3AC, 0x80, 0, 0x0, 0, 0)
201#define _MX53_PAD_DISP0_DAT8__GPIO4_29 IOMUX_PAD(0x3AC, 0x80, 1, 0x0, 0, 0)
202#define _MX53_PAD_DISP0_DAT8__PWM1_PWMO IOMUX_PAD(0x3AC, 0x80, 2, 0x0, 0, 0)
203#define _MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B IOMUX_PAD(0x3AC, 0x80, 3, 0x0, 0, 0)
204#define _MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x80, 5, 0x0, 0, 0)
205#define _MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 IOMUX_PAD(0x3AC, 0x80, 6, 0x0, 0, 0)
206#define _MX53_PAD_DISP0_DAT8__USBPHY2_AVALID IOMUX_PAD(0x3AC, 0x80, 7, 0x0, 0, 0)
207#define _MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 IOMUX_PAD(0x3B0, 0x84, 0, 0x0, 0, 0)
208#define _MX53_PAD_DISP0_DAT9__GPIO4_30 IOMUX_PAD(0x3B0, 0x84, 1, 0x0, 0, 0)
209#define _MX53_PAD_DISP0_DAT9__PWM2_PWMO IOMUX_PAD(0x3B0, 0x84, 2, 0x0, 0, 0)
210#define _MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B IOMUX_PAD(0x3B0, 0x84, 3, 0x0, 0, 0)
211#define _MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x84, 5, 0x0, 0, 0)
212#define _MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 IOMUX_PAD(0x3B0, 0x84, 6, 0x0, 0, 0)
213#define _MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 IOMUX_PAD(0x3B0, 0x84, 7, 0x0, 0, 0)
214#define _MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 IOMUX_PAD(0x3B4, 0x88, 0, 0x0, 0, 0)
215#define _MX53_PAD_DISP0_DAT10__GPIO4_31 IOMUX_PAD(0x3B4, 0x88, 1, 0x0, 0, 0)
216#define _MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP IOMUX_PAD(0x3B4, 0x88, 2, 0x0, 0, 0)
217#define _MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x3B4, 0x88, 5, 0x0, 0, 0)
218#define _MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 IOMUX_PAD(0x3B4, 0x88, 6, 0x0, 0, 0)
219#define _MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 IOMUX_PAD(0x3B4, 0x88, 7, 0x0, 0, 0)
220#define _MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 IOMUX_PAD(0x3B8, 0x8C, 0, 0x0, 0, 0)
221#define _MX53_PAD_DISP0_DAT11__GPIO5_5 IOMUX_PAD(0x3B8, 0x8C, 1, 0x0, 0, 0)
222#define _MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT IOMUX_PAD(0x3B8, 0x8C, 2, 0x0, 0, 0)
223#define _MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x3B8, 0x8C, 5, 0x0, 0, 0)
224#define _MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 IOMUX_PAD(0x3B8, 0x8C, 6, 0x0, 0, 0)
225#define _MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 IOMUX_PAD(0x3B8, 0x8C, 7, 0x0, 0, 0)
226#define _MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 IOMUX_PAD(0x3BC, 0x90, 0, 0x0, 0, 0)
227#define _MX53_PAD_DISP0_DAT12__GPIO5_6 IOMUX_PAD(0x3BC, 0x90, 1, 0x0, 0, 0)
228#define _MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK IOMUX_PAD(0x3BC, 0x90, 2, 0x0, 0, 0)
229#define _MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x3BC, 0x90, 5, 0x0, 0, 0)
230#define _MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 IOMUX_PAD(0x3BC, 0x90, 6, 0x0, 0, 0)
231#define _MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 IOMUX_PAD(0x3BC, 0x90, 7, 0x0, 0, 0)
232#define _MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 IOMUX_PAD(0x3C0, 0x94, 0, 0x0, 0, 0)
233#define _MX53_PAD_DISP0_DAT13__GPIO5_7 IOMUX_PAD(0x3C0, 0x94, 1, 0x0, 0, 0)
234#define _MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS IOMUX_PAD(0x3C0, 0x94, 3, 0x754, 0, 0)
235#define _MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 IOMUX_PAD(0x3C0, 0x94, 5, 0x0, 0, 0)
236#define _MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 IOMUX_PAD(0x3C0, 0x94, 6, 0x0, 0, 0)
237#define _MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 IOMUX_PAD(0x3C0, 0x94, 7, 0x0, 0, 0)
238#define _MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 IOMUX_PAD(0x3C4, 0x98, 0, 0x0, 0, 0)
239#define _MX53_PAD_DISP0_DAT14__GPIO5_8 IOMUX_PAD(0x3C4, 0x98, 1, 0x0, 0, 0)
240#define _MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC IOMUX_PAD(0x3C4, 0x98, 3, 0x750, 0, 0)
241#define _MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 IOMUX_PAD(0x3C4, 0x98, 5, 0x0, 0, 0)
242#define _MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 IOMUX_PAD(0x3C4, 0x98, 6, 0x0, 0, 0)
243#define _MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 IOMUX_PAD(0x3C4, 0x98, 7, 0x0, 0, 0)
244#define _MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 IOMUX_PAD(0x3C8, 0x9C, 0, 0x0, 0, 0)
245#define _MX53_PAD_DISP0_DAT15__GPIO5_9 IOMUX_PAD(0x3C8, 0x9C, 1, 0x0, 0, 0)
246#define _MX53_PAD_DISP0_DAT15__ECSPI1_SS1 IOMUX_PAD(0x3C8, 0x9C, 2, 0x7AC, 1, 0)
247#define _MX53_PAD_DISP0_DAT15__ECSPI2_SS1 IOMUX_PAD(0x3C8, 0x9C, 3, 0x7C8, 0, 0)
248#define _MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 IOMUX_PAD(0x3C8, 0x9C, 5, 0x0, 0, 0)
249#define _MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 IOMUX_PAD(0x3C8, 0x9C, 6, 0x0, 0, 0)
250#define _MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 IOMUX_PAD(0x3C8, 0x9C, 7, 0x0, 0, 0)
251#define _MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 IOMUX_PAD(0x3CC, 0xA0, 0, 0x0, 0, 0)
252#define _MX53_PAD_DISP0_DAT16__GPIO5_10 IOMUX_PAD(0x3CC, 0xA0, 1, 0x0, 0, 0)
253#define _MX53_PAD_DISP0_DAT16__ECSPI2_MOSI IOMUX_PAD(0x3CC, 0xA0, 2, 0x7C0, 0, 0)
254#define _MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC IOMUX_PAD(0x3CC, 0xA0, 3, 0x758, 1, 0)
255#define _MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 IOMUX_PAD(0x3CC, 0xA0, 4, 0x868, 0, 0)
256#define _MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 IOMUX_PAD(0x3CC, 0xA0, 5, 0x0, 0, 0)
257#define _MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 IOMUX_PAD(0x3CC, 0xA0, 6, 0x0, 0, 0)
258#define _MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 IOMUX_PAD(0x3CC, 0xA0, 7, 0x0, 0, 0)
259#define _MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 IOMUX_PAD(0x3D0, 0xA4, 0, 0x0, 0, 0)
260#define _MX53_PAD_DISP0_DAT17__GPIO5_11 IOMUX_PAD(0x3D0, 0xA4, 1, 0x0, 0, 0)
261#define _MX53_PAD_DISP0_DAT17__ECSPI2_MISO IOMUX_PAD(0x3D0, 0xA4, 2, 0x7BC, 0, 0)
262#define _MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD IOMUX_PAD(0x3D0, 0xA4, 3, 0x74C, 1, 0)
263#define _MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 IOMUX_PAD(0x3D0, 0xA4, 4, 0x86C, 0, 0)
264#define _MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 IOMUX_PAD(0x3D0, 0xA4, 5, 0x0, 0, 0)
265#define _MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 IOMUX_PAD(0x3D0, 0xA4, 6, 0x0, 0, 0)
266#define _MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 IOMUX_PAD(0x3D4, 0xA8, 0, 0x0, 0, 0)
267#define _MX53_PAD_DISP0_DAT18__GPIO5_12 IOMUX_PAD(0x3D4, 0xA8, 1, 0x0, 0, 0)
268#define _MX53_PAD_DISP0_DAT18__ECSPI2_SS0 IOMUX_PAD(0x3D4, 0xA8, 2, 0x7C4, 0, 0)
269#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS IOMUX_PAD(0x3D4, 0xA8, 3, 0x75C, 1, 0)
270#define _MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS IOMUX_PAD(0x3D4, 0xA8, 4, 0x73C, 0, 0)
271#define _MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 IOMUX_PAD(0x3D4, 0xA8, 5, 0x0, 0, 0)
272#define _MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 IOMUX_PAD(0x3D4, 0xA8, 6, 0x0, 0, 0)
273#define _MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 IOMUX_PAD(0x3D4, 0xA8, 7, 0x0, 0, 0)
274#define _MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 IOMUX_PAD(0x3D8, 0xAC, 0, 0x0, 0, 0)
275#define _MX53_PAD_DISP0_DAT19__GPIO5_13 IOMUX_PAD(0x3D8, 0xAC, 1, 0x0, 0, 0)
276#define _MX53_PAD_DISP0_DAT19__ECSPI2_SCLK IOMUX_PAD(0x3D8, 0xAC, 2, 0x7B8, 0, 0)
277#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD IOMUX_PAD(0x3D8, 0xAC, 3, 0x748, 1, 0)
278#define _MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC IOMUX_PAD(0x3D8, 0xAC, 4, 0x738, 0, 0)
279#define _MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 IOMUX_PAD(0x3D8, 0xAC, 5, 0x0, 0, 0)
280#define _MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 IOMUX_PAD(0x3D8, 0xAC, 6, 0x0, 0, 0)
281#define _MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 IOMUX_PAD(0x3D8, 0xAC, 7, 0x0, 0, 0)
282#define _MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 IOMUX_PAD(0x3DC, 0xB0, 0, 0x0, 0, 0)
283#define _MX53_PAD_DISP0_DAT20__GPIO5_14 IOMUX_PAD(0x3DC, 0xB0, 1, 0x0, 0, 0)
284#define _MX53_PAD_DISP0_DAT20__ECSPI1_SCLK IOMUX_PAD(0x3DC, 0xB0, 2, 0x79C, 1, 0)
285#define _MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC IOMUX_PAD(0x3DC, 0xB0, 3, 0x740, 0, 0)
286#define _MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 IOMUX_PAD(0x3DC, 0xB0, 5, 0x0, 0, 0)
287#define _MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 IOMUX_PAD(0x3DC, 0xB0, 6, 0x0, 0, 0)
288#define _MX53_PAD_DISP0_DAT20__SATA_PHY_TDI IOMUX_PAD(0x3DC, 0xB0, 7, 0x0, 0, 0)
289#define _MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 IOMUX_PAD(0x3E0, 0xB4, 0, 0x0, 0, 0)
290#define _MX53_PAD_DISP0_DAT21__GPIO5_15 IOMUX_PAD(0x3E0, 0xB4, 1, 0x0, 0, 0)
291#define _MX53_PAD_DISP0_DAT21__ECSPI1_MOSI IOMUX_PAD(0x3E0, 0xB4, 2, 0x7A4, 1, 0)
292#define _MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD IOMUX_PAD(0x3E0, 0xB4, 3, 0x734, 0, 0)
293#define _MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x3E0, 0xB4, 5, 0x0, 0, 0)
294#define _MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 IOMUX_PAD(0x3E0, 0xB4, 6, 0x0, 0, 0)
295#define _MX53_PAD_DISP0_DAT21__SATA_PHY_TDO IOMUX_PAD(0x3E0, 0xB4, 7, 0x0, 0, 0)
296#define _MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 IOMUX_PAD(0x3E4, 0xB8, 0, 0x0, 0, 0)
297#define _MX53_PAD_DISP0_DAT22__GPIO5_16 IOMUX_PAD(0x3E4, 0xB8, 1, 0x0, 0, 0)
298#define _MX53_PAD_DISP0_DAT22__ECSPI1_MISO IOMUX_PAD(0x3E4, 0xB8, 2, 0x7A0, 1, 0)
299#define _MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS IOMUX_PAD(0x3E4, 0xB8, 3, 0x744, 0, 0)
300#define _MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x3E4, 0xB8, 5, 0x0, 0, 0)
301#define _MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 IOMUX_PAD(0x3E4, 0xB8, 6, 0x0, 0, 0)
302#define _MX53_PAD_DISP0_DAT22__SATA_PHY_TCK IOMUX_PAD(0x3E4, 0xB8, 7, 0x0, 0, 0)
303#define _MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 IOMUX_PAD(0x3E8, 0xBC, 0, 0x0, 0, 0)
304#define _MX53_PAD_DISP0_DAT23__GPIO5_17 IOMUX_PAD(0x3E8, 0xBC, 1, 0x0, 0, 0)
305#define _MX53_PAD_DISP0_DAT23__ECSPI1_SS0 IOMUX_PAD(0x3E8, 0xBC, 2, 0x7A8, 1, 0)
306#define _MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD IOMUX_PAD(0x3E8, 0xBC, 3, 0x730, 0, 0)
307#define _MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x3E8, 0xBC, 5, 0x0, 0, 0)
308#define _MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 IOMUX_PAD(0x3E8, 0xBC, 6, 0x0, 0, 0)
309#define _MX53_PAD_DISP0_DAT23__SATA_PHY_TMS IOMUX_PAD(0x3E8, 0xBC, 7, 0x0, 0, 0)
310#define _MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK IOMUX_PAD(0x3EC, 0xC0, 0, 0x0, 0, 0)
311#define _MX53_PAD_CSI0_PIXCLK__GPIO5_18 IOMUX_PAD(0x3EC, 0xC0, 1, 0x0, 0, 0)
312#define _MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 IOMUX_PAD(0x3EC, 0xC0, 5, 0x0, 0, 0)
313#define _MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 IOMUX_PAD(0x3EC, 0xC0, 6, 0x0, 0, 0)
314#define _MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC IOMUX_PAD(0x3F0, 0xC4, 0, 0x0, 0, 0)
315#define _MX53_PAD_CSI0_MCLK__GPIO5_19 IOMUX_PAD(0x3F0, 0xC4, 1, 0x0, 0, 0)
316#define _MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK IOMUX_PAD(0x3F0, 0xC4, 2, 0x0, 0, 0)
317#define _MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 IOMUX_PAD(0x3F0, 0xC4, 5, 0x0, 0, 0)
318#define _MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 IOMUX_PAD(0x3F0, 0xC4, 6, 0x0, 0, 0)
319#define _MX53_PAD_CSI0_MCLK__TPIU_TRCTL IOMUX_PAD(0x3F0, 0xC4, 7, 0x0, 0, 0)
320#define _MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN IOMUX_PAD(0x3F4, 0xC8, 0, 0x0, 0, 0)
321#define _MX53_PAD_CSI0_DATA_EN__GPIO5_20 IOMUX_PAD(0x3F4, 0xC8, 1, 0x0, 0, 0)
322#define _MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 IOMUX_PAD(0x3F4, 0xC8, 5, 0x0, 0, 0)
323#define _MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 IOMUX_PAD(0x3F4, 0xC8, 6, 0x0, 0, 0)
324#define _MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK IOMUX_PAD(0x3F4, 0xC8, 7, 0x0, 0, 0)
325#define _MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC IOMUX_PAD(0x3F8, 0xCC, 0, 0x0, 0, 0)
326#define _MX53_PAD_CSI0_VSYNC__GPIO5_21 IOMUX_PAD(0x3F8, 0xCC, 1, 0x0, 0, 0)
327#define _MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 IOMUX_PAD(0x3F8, 0xCC, 5, 0x0, 0, 0)
328#define _MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 IOMUX_PAD(0x3F8, 0xCC, 6, 0x0, 0, 0)
329#define _MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 IOMUX_PAD(0x3F8, 0xCC, 7, 0x0, 0, 0)
330#define _MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 IOMUX_PAD(0x3FC, 0xD0, 0, 0x0, 0, 0)
331#define _MX53_PAD_CSI0_DAT4__GPIO5_22 IOMUX_PAD(0x3FC, 0xD0, 1, 0x0, 0, 0)
332#define _MX53_PAD_CSI0_DAT4__KPP_COL_5 IOMUX_PAD(0x3FC, 0xD0, 2, 0x840, 1, 0)
333#define _MX53_PAD_CSI0_DAT4__ECSPI1_SCLK IOMUX_PAD(0x3FC, 0xD0, 3, 0x79C, 2, 0)
334#define _MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP IOMUX_PAD(0x3FC, 0xD0, 4, 0x0, 0, 0)
335#define _MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC IOMUX_PAD(0x3FC, 0xD0, 5, 0x0, 0, 0)
336#define _MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 IOMUX_PAD(0x3FC, 0xD0, 6, 0x0, 0, 0)
337#define _MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 IOMUX_PAD(0x3FC, 0xD0, 7, 0x0, 0, 0)
338#define _MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 IOMUX_PAD(0x400, 0xD4, 0, 0x0, 0, 0)
339#define _MX53_PAD_CSI0_DAT5__GPIO5_23 IOMUX_PAD(0x400, 0xD4, 1, 0x0, 0, 0)
340#define _MX53_PAD_CSI0_DAT5__KPP_ROW_5 IOMUX_PAD(0x400, 0xD4, 2, 0x84C, 0, 0)
341#define _MX53_PAD_CSI0_DAT5__ECSPI1_MOSI IOMUX_PAD(0x400, 0xD4, 3, 0x7A4, 2, 0)
342#define _MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT IOMUX_PAD(0x400, 0xD4, 4, 0x0, 0, 0)
343#define _MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD IOMUX_PAD(0x400, 0xD4, 5, 0x0, 0, 0)
344#define _MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 IOMUX_PAD(0x400, 0xD4, 6, 0x0, 0, 0)
345#define _MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 IOMUX_PAD(0x400, 0xD4, 7, 0x0, 0, 0)
346#define _MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 IOMUX_PAD(0x404, 0xD8, 0, 0x0, 0, 0)
347#define _MX53_PAD_CSI0_DAT6__GPIO5_24 IOMUX_PAD(0x404, 0xD8, 1, 0x0, 0, 0)
348#define _MX53_PAD_CSI0_DAT6__KPP_COL_6 IOMUX_PAD(0x404, 0xD8, 2, 0x844, 0, 0)
349#define _MX53_PAD_CSI0_DAT6__ECSPI1_MISO IOMUX_PAD(0x404, 0xD8, 3, 0x7A0, 2, 0)
350#define _MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK IOMUX_PAD(0x404, 0xD8, 4, 0x0, 0, 0)
351#define _MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS IOMUX_PAD(0x404, 0xD8, 5, 0x0, 0, 0)
352#define _MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 IOMUX_PAD(0x404, 0xD8, 6, 0x0, 0, 0)
353#define _MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 IOMUX_PAD(0x404, 0xD8, 7, 0x0, 0, 0)
354#define _MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 IOMUX_PAD(0x408, 0xDC, 0, 0x0, 0, 0)
355#define _MX53_PAD_CSI0_DAT7__GPIO5_25 IOMUX_PAD(0x408, 0xDC, 1, 0x0, 0, 0)
356#define _MX53_PAD_CSI0_DAT7__KPP_ROW_6 IOMUX_PAD(0x408, 0xDC, 2, 0x850, 0, 0)
357#define _MX53_PAD_CSI0_DAT7__ECSPI1_SS0 IOMUX_PAD(0x408, 0xDC, 3, 0x7A8, 2, 0)
358#define _MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR IOMUX_PAD(0x408, 0xDC, 4, 0x0, 0, 0)
359#define _MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD IOMUX_PAD(0x408, 0xDC, 5, 0x0, 0, 0)
360#define _MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 IOMUX_PAD(0x408, 0xDC, 6, 0x0, 0, 0)
361#define _MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 IOMUX_PAD(0x408, 0xDC, 7, 0x0, 0, 0)
362#define _MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 IOMUX_PAD(0x40C, 0xE0, 0, 0x0, 0, 0)
363#define _MX53_PAD_CSI0_DAT8__GPIO5_26 IOMUX_PAD(0x40C, 0xE0, 1, 0x0, 0, 0)
364#define _MX53_PAD_CSI0_DAT8__KPP_COL_7 IOMUX_PAD(0x40C, 0xE0, 2, 0x848, 0, 0)
365#define _MX53_PAD_CSI0_DAT8__ECSPI2_SCLK IOMUX_PAD(0x40C, 0xE0, 3, 0x7B8, 1, 0)
366#define _MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC IOMUX_PAD(0x40C, 0xE0, 4, 0x0, 0, 0)
367#define _MX53_PAD_CSI0_DAT8__I2C1_SDA IOMUX_PAD(0x40C, 0xE0, 5 | IOMUX_CONFIG_SION, 0x818, 0, 0)
368#define _MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 IOMUX_PAD(0x40C, 0xE0, 6, 0x0, 0, 0)
369#define _MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 IOMUX_PAD(0x40C, 0xE0, 7, 0x0, 0, 0)
370#define _MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 IOMUX_PAD(0x410, 0xE4, 0, 0x0, 0, 0)
371#define _MX53_PAD_CSI0_DAT9__GPIO5_27 IOMUX_PAD(0x410, 0xE4, 1, 0x0, 0, 0)
372#define _MX53_PAD_CSI0_DAT9__KPP_ROW_7 IOMUX_PAD(0x410, 0xE4, 2, 0x854, 0, 0)
373#define _MX53_PAD_CSI0_DAT9__ECSPI2_MOSI IOMUX_PAD(0x410, 0xE4, 3, 0x7C0, 1, 0)
374#define _MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR IOMUX_PAD(0x410, 0xE4, 4, 0x0, 0, 0)
375#define _MX53_PAD_CSI0_DAT9__I2C1_SCL IOMUX_PAD(0x410, 0xE4, 5 | IOMUX_CONFIG_SION, 0x814, 0, 0)
376#define _MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 IOMUX_PAD(0x410, 0xE4, 6, 0x0, 0, 0)
377#define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0)
378#define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0)
379#define _MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0)
380#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0xE8, 2, 0x878, 0, 0)
381#define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0)
382#define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0)
383#define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0)
384#define _MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 IOMUX_PAD(0x414, 0xE8, 6, 0x0, 0, 0)
385#define _MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 IOMUX_PAD(0x414, 0xE8, 7, 0x0, 0, 0)
386#define _MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 IOMUX_PAD(0x418, 0xEC, 0, 0x0, 0, 0)
387#define _MX53_PAD_CSI0_DAT11__GPIO5_29 IOMUX_PAD(0x418, 0xEC, 1, 0x0, 0, 0)
388#define _MX53_PAD_CSI0_DAT11__UART1_RXD_MUX IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, 0)
389#define _MX53_PAD_CSI0_DAT11__ECSPI2_SS0 IOMUX_PAD(0x418, 0xEC, 3, 0x7C4, 1, 0)
390#define _MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS IOMUX_PAD(0x418, 0xEC, 4, 0x0, 0, 0)
391#define _MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 IOMUX_PAD(0x418, 0xEC, 5, 0x0, 0, 0)
392#define _MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 IOMUX_PAD(0x418, 0xEC, 6, 0x0, 0, 0)
393#define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0)
394#define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0)
395#define _MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0)
396#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0xF0, 2, 0x890, 2, 0)
397#define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0)
398#define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0)
399#define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0)
400#define _MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 IOMUX_PAD(0x41C, 0xF0, 7, 0x0, 0, 0)
401#define _MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 IOMUX_PAD(0x420, 0xF4, 0, 0x0, 0, 0)
402#define _MX53_PAD_CSI0_DAT13__GPIO5_31 IOMUX_PAD(0x420, 0xF4, 1, 0x0, 0, 0)
403#define _MX53_PAD_CSI0_DAT13__UART4_RXD_MUX IOMUX_PAD(0x420, 0xF4, 2, 0x890, 3, 0)
404#define _MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 IOMUX_PAD(0x420, 0xF4, 4, 0x0, 0, 0)
405#define _MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 IOMUX_PAD(0x420, 0xF4, 5, 0x0, 0, 0)
406#define _MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 IOMUX_PAD(0x420, 0xF4, 6, 0x0, 0, 0)
407#define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0)
408#define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0)
409#define _MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0)
410#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0xF8, 2, 0x898, 2, 0)
411#define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0)
412#define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0)
413#define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0)
414#define _MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 IOMUX_PAD(0x424, 0xF8, 7, 0x0, 0, 0)
415#define _MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 IOMUX_PAD(0x428, 0xFC, 0, 0x0, 0, 0)
416#define _MX53_PAD_CSI0_DAT15__GPIO6_1 IOMUX_PAD(0x428, 0xFC, 1, 0x0, 0, 0)
417#define _MX53_PAD_CSI0_DAT15__UART5_RXD_MUX IOMUX_PAD(0x428, 0xFC, 2, 0x898, 3, 0)
418#define _MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 IOMUX_PAD(0x428, 0xFC, 4, 0x0, 0, 0)
419#define _MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 IOMUX_PAD(0x428, 0xFC, 5, 0x0, 0, 0)
420#define _MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 IOMUX_PAD(0x428, 0xFC, 6, 0x0, 0, 0)
421#define _MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 IOMUX_PAD(0x428, 0xFC, 7, 0x0, 0, 0)
422#define _MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 IOMUX_PAD(0x42C, 0x100, 0, 0x0, 0, 0)
423#define _MX53_PAD_CSI0_DAT16__GPIO6_2 IOMUX_PAD(0x42C, 0x100, 1, 0x0, 0, 0)
424#define _MX53_PAD_CSI0_DAT16__UART4_RTS IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, 0)
425#define _MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 IOMUX_PAD(0x42C, 0x100, 4, 0x0, 0, 0)
426#define _MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 IOMUX_PAD(0x42C, 0x100, 5, 0x0, 0, 0)
427#define _MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 IOMUX_PAD(0x42C, 0x100, 6, 0x0, 0, 0)
428#define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0)
429#define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0)
430#define _MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0)
431#define _MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, 0x88C, 1, 0)
432#define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0)
433#define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0)
434#define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0)
435#define _MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 IOMUX_PAD(0x430, 0x104, 7, 0x0, 0, 0)
436#define _MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 IOMUX_PAD(0x434, 0x108, 0, 0x0, 0, 0)
437#define _MX53_PAD_CSI0_DAT18__GPIO6_4 IOMUX_PAD(0x434, 0x108, 1, 0x0, 0, 0)
438#define _MX53_PAD_CSI0_DAT18__UART5_RTS IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, 0)
439#define _MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 IOMUX_PAD(0x434, 0x108, 4, 0x0, 0, 0)
440#define _MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 IOMUX_PAD(0x434, 0x108, 5, 0x0, 0, 0)
441#define _MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 IOMUX_PAD(0x434, 0x108, 6, 0x0, 0, 0)
442#define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0)
443#define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0)
444#define _MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0)
445#define _MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, 0x894, 3, 0)
446#define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0)
447#define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0)
448#define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0)
449#define _MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK IOMUX_PAD(0x438, 0x10C, 7, 0x0, 0, 0)
450#define _MX53_PAD_EIM_A25__EMI_WEIM_A_25 IOMUX_PAD(0x458, 0x110, 0, 0x0, 0, 0)
451#define _MX53_PAD_EIM_A25__GPIO5_2 IOMUX_PAD(0x458, 0x110, 1, 0x0, 0, 0)
452#define _MX53_PAD_EIM_A25__ECSPI2_RDY IOMUX_PAD(0x458, 0x110, 2, 0x0, 0, 0)
453#define _MX53_PAD_EIM_A25__IPU_DI1_PIN12 IOMUX_PAD(0x458, 0x110, 3, 0x0, 0, 0)
454#define _MX53_PAD_EIM_A25__CSPI_SS1 IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, 0)
455#define _MX53_PAD_EIM_A25__IPU_DI0_D1_CS IOMUX_PAD(0x458, 0x110, 6, 0x0, 0, 0)
456#define _MX53_PAD_EIM_A25__USBPHY1_BISTOK IOMUX_PAD(0x458, 0x110, 7, 0x0, 0, 0)
457#define _MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 IOMUX_PAD(0x45C, 0x114, 0, 0x0, 0, 0)
458#define _MX53_PAD_EIM_EB2__GPIO2_30 IOMUX_PAD(0x45C, 0x114, 1, 0x0, 0, 0)
459#define _MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, 0)
460#define _MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS IOMUX_PAD(0x45C, 0x114, 3, 0x0, 0, 0)
461#define _MX53_PAD_EIM_EB2__ECSPI1_SS0 IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, 0)
462#define _MX53_PAD_EIM_EB2__I2C2_SCL IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, 0)
463#define _MX53_PAD_EIM_D16__EMI_WEIM_D_16 IOMUX_PAD(0x460, 0x118, 0, 0x0, 0, 0)
464#define _MX53_PAD_EIM_D16__GPIO3_16 IOMUX_PAD(0x460, 0x118, 1, 0x0, 0, 0)
465#define _MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0)
466#define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0)
467#define _MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0)
468#define _MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5, 0x820, 1, 0)
469#define _MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0)
470#define _MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0)
471#define _MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0)
472#define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0)
473#define _MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0)
474#define _MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5, 0x824, 0, 0)
475#define _MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0)
476#define _MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0)
477#define _MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0)
478#define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0)
479#define _MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0)
480#define _MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5, 0x828, 0, 0)
481#define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0)
482#define _MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0)
483#define _MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0)
484#define _MX53_PAD_EIM_D19__IPU_DI0_PIN8 IOMUX_PAD(0x46C, 0x124, 2, 0x0, 0, 0)
485#define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0)
486#define _MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0)
487#define _MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0)
488#define _MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, 0x874, 0, 0)
489#define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0)
490#define _MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0)
491#define _MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0)
492#define _MX53_PAD_EIM_D20__IPU_DI0_PIN16 IOMUX_PAD(0x470, 0x128, 2, 0x0, 0, 0)
493#define _MX53_PAD_EIM_D20__IPU_SER_DISP0_CS IOMUX_PAD(0x470, 0x128, 3, 0x0, 0, 0)
494#define _MX53_PAD_EIM_D20__CSPI_SS0 IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, 0)
495#define _MX53_PAD_EIM_D20__EPIT2_EPITO IOMUX_PAD(0x470, 0x128, 5, 0x0, 0, 0)
496#define _MX53_PAD_EIM_D20__UART1_RTS IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, 0)
497#define _MX53_PAD_EIM_D20__USBOH3_USBH2_PWR IOMUX_PAD(0x470, 0x128, 7, 0x0, 0, 0)
498#define _MX53_PAD_EIM_D21__EMI_WEIM_D_21 IOMUX_PAD(0x474, 0x12C, 0, 0x0, 0, 0)
499#define _MX53_PAD_EIM_D21__GPIO3_21 IOMUX_PAD(0x474, 0x12C, 1, 0x0, 0, 0)
500#define _MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0)
501#define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0)
502#define _MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0)
503#define _MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5, 0x814, 1, 0)
504#define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0)
505#define _MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0)
506#define _MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0)
507#define _MX53_PAD_EIM_D22__IPU_DI0_PIN1 IOMUX_PAD(0x478, 0x130, 2, 0x0, 0, 0)
508#define _MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, 0)
509#define _MX53_PAD_EIM_D22__CSPI_MISO IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, 0)
510#define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0)
511#define _MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0)
512#define _MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0)
513#define _MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, 0x884, 0, 0)
514#define _MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0)
515#define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0)
516#define _MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0)
517#define _MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, 0)
518#define _MX53_PAD_EIM_D23__IPU_DI1_PIN14 IOMUX_PAD(0x47C, 0x134, 7, 0x0, 0, 0)
519#define _MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 IOMUX_PAD(0x480, 0x138, 0, 0x0, 0, 0)
520#define _MX53_PAD_EIM_EB3__GPIO2_31 IOMUX_PAD(0x480, 0x138, 1, 0x0, 0, 0)
521#define _MX53_PAD_EIM_EB3__UART3_RTS IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, 0)
522#define _MX53_PAD_EIM_EB3__UART1_RI IOMUX_PAD(0x480, 0x138, 3, 0x0, 0, 0)
523#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN3 IOMUX_PAD(0x480, 0x138, 5, 0x0, 0, 0)
524#define _MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, 0)
525#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0)
526#define _MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0)
527#define _MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0)
528#define _MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, 0x888, 0, 0)
529#define _MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0)
530#define _MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0)
531#define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0)
532#define _MX53_PAD_EIM_D24__ECSPI2_SS2 IOMUX_PAD(0x484, 0x13C, 6, 0x0, 0, 0)
533#define _MX53_PAD_EIM_D24__UART1_DTR IOMUX_PAD(0x484, 0x13C, 7, 0x0, 0, 0)
534#define _MX53_PAD_EIM_D25__EMI_WEIM_D_25 IOMUX_PAD(0x488, 0x140, 0, 0x0, 0, 0)
535#define _MX53_PAD_EIM_D25__GPIO3_25 IOMUX_PAD(0x488, 0x140, 1, 0x0, 0, 0)
536#define _MX53_PAD_EIM_D25__UART3_RXD_MUX IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, 0)
537#define _MX53_PAD_EIM_D25__ECSPI1_SS3 IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, 0)
538#define _MX53_PAD_EIM_D25__CSPI_SS3 IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, 0)
539#define _MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, 0)
540#define _MX53_PAD_EIM_D25__ECSPI2_SS3 IOMUX_PAD(0x488, 0x140, 6, 0x0, 0, 0)
541#define _MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0)
542#define _MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0)
543#define _MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0)
544#define _MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, 0x880, 0, 0)
545#define _MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0)
546#define _MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0)
547#define _MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0)
548#define _MX53_PAD_EIM_D26__IPU_SISG_2 IOMUX_PAD(0x48C, 0x144, 6, 0x0, 0, 0)
549#define _MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 IOMUX_PAD(0x48C, 0x144, 7, 0x0, 0, 0)
550#define _MX53_PAD_EIM_D27__EMI_WEIM_D_27 IOMUX_PAD(0x490, 0x148, 0, 0x0, 0, 0)
551#define _MX53_PAD_EIM_D27__GPIO3_27 IOMUX_PAD(0x490, 0x148, 1, 0x0, 0, 0)
552#define _MX53_PAD_EIM_D27__UART2_RXD_MUX IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, 0)
553#define _MX53_PAD_EIM_D27__FIRI_TXD IOMUX_PAD(0x490, 0x148, 3, 0x0, 0, 0)
554#define _MX53_PAD_EIM_D27__IPU_CSI0_D_0 IOMUX_PAD(0x490, 0x148, 4, 0x0, 0, 0)
555#define _MX53_PAD_EIM_D27__IPU_DI1_PIN13 IOMUX_PAD(0x490, 0x148, 5, 0x0, 0, 0)
556#define _MX53_PAD_EIM_D27__IPU_SISG_3 IOMUX_PAD(0x490, 0x148, 6, 0x0, 0, 0)
557#define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0)
558#define _MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0)
559#define _MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0)
560#define _MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, 0x87C, 0, 0)
561#define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0)
562#define _MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0)
563#define _MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5, 0x818, 1, 0)
564#define _MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0)
565#define _MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0)
566#define _MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0)
567#define _MX53_PAD_EIM_D29__GPIO3_29 IOMUX_PAD(0x498, 0x150, 1, 0x0, 0, 0)
568#define _MX53_PAD_EIM_D29__UART2_RTS IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, 0)
569#define _MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS IOMUX_PAD(0x498, 0x150, 3, 0x0, 0, 0)
570#define _MX53_PAD_EIM_D29__CSPI_SS0 IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, 0)
571#define _MX53_PAD_EIM_D29__IPU_DI1_PIN15 IOMUX_PAD(0x498, 0x150, 5, 0x0, 0, 0)
572#define _MX53_PAD_EIM_D29__IPU_CSI1_VSYNC IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, 0)
573#define _MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0)
574#define _MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0)
575#define _MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0)
576#define _MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, 0x884, 2, 0)
577#define _MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0)
578#define _MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0)
579#define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0)
580#define _MX53_PAD_EIM_D30__USBOH3_USBH1_OC IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, 0)
581#define _MX53_PAD_EIM_D30__USBOH3_USBH2_OC IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, 0)
582#define _MX53_PAD_EIM_D31__EMI_WEIM_D_31 IOMUX_PAD(0x4A0, 0x158, 0, 0x0, 0, 0)
583#define _MX53_PAD_EIM_D31__GPIO3_31 IOMUX_PAD(0x4A0, 0x158, 1, 0x0, 0, 0)
584#define _MX53_PAD_EIM_D31__UART3_RTS IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, 0)
585#define _MX53_PAD_EIM_D31__IPU_CSI0_D_2 IOMUX_PAD(0x4A0, 0x158, 3, 0x0, 0, 0)
586#define _MX53_PAD_EIM_D31__IPU_DI0_PIN12 IOMUX_PAD(0x4A0, 0x158, 4, 0x0, 0, 0)
587#define _MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 IOMUX_PAD(0x4A0, 0x158, 5, 0x0, 0, 0)
588#define _MX53_PAD_EIM_D31__USBOH3_USBH1_PWR IOMUX_PAD(0x4A0, 0x158, 6, 0x0, 0, 0)
589#define _MX53_PAD_EIM_D31__USBOH3_USBH2_PWR IOMUX_PAD(0x4A0, 0x158, 7, 0x0, 0, 0)
590#define _MX53_PAD_EIM_A24__EMI_WEIM_A_24 IOMUX_PAD(0x4A8, 0x15C, 0, 0x0, 0, 0)
591#define _MX53_PAD_EIM_A24__GPIO5_4 IOMUX_PAD(0x4A8, 0x15C, 1, 0x0, 0, 0)
592#define _MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 IOMUX_PAD(0x4A8, 0x15C, 2, 0x0, 0, 0)
593#define _MX53_PAD_EIM_A24__IPU_CSI1_D_19 IOMUX_PAD(0x4A8, 0x15C, 3, 0x0, 0, 0)
594#define _MX53_PAD_EIM_A24__IPU_SISG_2 IOMUX_PAD(0x4A8, 0x15C, 6, 0x0, 0, 0)
595#define _MX53_PAD_EIM_A24__USBPHY2_BVALID IOMUX_PAD(0x4A8, 0x15C, 7, 0x0, 0, 0)
596#define _MX53_PAD_EIM_A23__EMI_WEIM_A_23 IOMUX_PAD(0x4AC, 0x160, 0, 0x0, 0, 0)
597#define _MX53_PAD_EIM_A23__GPIO6_6 IOMUX_PAD(0x4AC, 0x160, 1, 0x0, 0, 0)
598#define _MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 IOMUX_PAD(0x4AC, 0x160, 2, 0x0, 0, 0)
599#define _MX53_PAD_EIM_A23__IPU_CSI1_D_18 IOMUX_PAD(0x4AC, 0x160, 3, 0x0, 0, 0)
600#define _MX53_PAD_EIM_A23__IPU_SISG_3 IOMUX_PAD(0x4AC, 0x160, 6, 0x0, 0, 0)
601#define _MX53_PAD_EIM_A23__USBPHY2_ENDSESSION IOMUX_PAD(0x4AC, 0x160, 7, 0x0, 0, 0)
602#define _MX53_PAD_EIM_A22__EMI_WEIM_A_22 IOMUX_PAD(0x4B0, 0x164, 0, 0x0, 0, 0)
603#define _MX53_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x4B0, 0x164, 1, 0x0, 0, 0)
604#define _MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 IOMUX_PAD(0x4B0, 0x164, 2, 0x0, 0, 0)
605#define _MX53_PAD_EIM_A22__IPU_CSI1_D_17 IOMUX_PAD(0x4B0, 0x164, 3, 0x0, 0, 0)
606#define _MX53_PAD_EIM_A22__SRC_BT_CFG1_7 IOMUX_PAD(0x4B0, 0x164, 7, 0x0, 0, 0)
607#define _MX53_PAD_EIM_A21__EMI_WEIM_A_21 IOMUX_PAD(0x4B4, 0x168, 0, 0x0, 0, 0)
608#define _MX53_PAD_EIM_A21__GPIO2_17 IOMUX_PAD(0x4B4, 0x168, 1, 0x0, 0, 0)
609#define _MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 IOMUX_PAD(0x4B4, 0x168, 2, 0x0, 0, 0)
610#define _MX53_PAD_EIM_A21__IPU_CSI1_D_16 IOMUX_PAD(0x4B4, 0x168, 3, 0x0, 0, 0)
611#define _MX53_PAD_EIM_A21__SRC_BT_CFG1_6 IOMUX_PAD(0x4B4, 0x168, 7, 0x0, 0, 0)
612#define _MX53_PAD_EIM_A20__EMI_WEIM_A_20 IOMUX_PAD(0x4B8, 0x16C, 0, 0x0, 0, 0)
613#define _MX53_PAD_EIM_A20__GPIO2_18 IOMUX_PAD(0x4B8, 0x16C, 1, 0x0, 0, 0)
614#define _MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 IOMUX_PAD(0x4B8, 0x16C, 2, 0x0, 0, 0)
615#define _MX53_PAD_EIM_A20__IPU_CSI1_D_15 IOMUX_PAD(0x4B8, 0x16C, 3, 0x0, 0, 0)
616#define _MX53_PAD_EIM_A20__SRC_BT_CFG1_5 IOMUX_PAD(0x4B8, 0x16C, 7, 0x0, 0, 0)
617#define _MX53_PAD_EIM_A19__EMI_WEIM_A_19 IOMUX_PAD(0x4BC, 0x170, 0, 0x0, 0, 0)
618#define _MX53_PAD_EIM_A19__GPIO2_19 IOMUX_PAD(0x4BC, 0x170, 1, 0x0, 0, 0)
619#define _MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 IOMUX_PAD(0x4BC, 0x170, 2, 0x0, 0, 0)
620#define _MX53_PAD_EIM_A19__IPU_CSI1_D_14 IOMUX_PAD(0x4BC, 0x170, 3, 0x0, 0, 0)
621#define _MX53_PAD_EIM_A19__SRC_BT_CFG1_4 IOMUX_PAD(0x4BC, 0x170, 7, 0x0, 0, 0)
622#define _MX53_PAD_EIM_A18__EMI_WEIM_A_18 IOMUX_PAD(0x4C0, 0x174, 0, 0x0, 0, 0)
623#define _MX53_PAD_EIM_A18__GPIO2_20 IOMUX_PAD(0x4C0, 0x174, 1, 0x0, 0, 0)
624#define _MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 IOMUX_PAD(0x4C0, 0x174, 2, 0x0, 0, 0)
625#define _MX53_PAD_EIM_A18__IPU_CSI1_D_13 IOMUX_PAD(0x4C0, 0x174, 3, 0x0, 0, 0)
626#define _MX53_PAD_EIM_A18__SRC_BT_CFG1_3 IOMUX_PAD(0x4C0, 0x174, 7, 0x0, 0, 0)
627#define _MX53_PAD_EIM_A17__EMI_WEIM_A_17 IOMUX_PAD(0x4C4, 0x178, 0, 0x0, 0, 0)
628#define _MX53_PAD_EIM_A17__GPIO2_21 IOMUX_PAD(0x4C4, 0x178, 1, 0x0, 0, 0)
629#define _MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 IOMUX_PAD(0x4C4, 0x178, 2, 0x0, 0, 0)
630#define _MX53_PAD_EIM_A17__IPU_CSI1_D_12 IOMUX_PAD(0x4C4, 0x178, 3, 0x0, 0, 0)
631#define _MX53_PAD_EIM_A17__SRC_BT_CFG1_2 IOMUX_PAD(0x4C4, 0x178, 7, 0x0, 0, 0)
632#define _MX53_PAD_EIM_A16__EMI_WEIM_A_16 IOMUX_PAD(0x4C8, 0x17C, 0, 0x0, 0, 0)
633#define _MX53_PAD_EIM_A16__GPIO2_22 IOMUX_PAD(0x4C8, 0x17C, 1, 0x0, 0, 0)
634#define _MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK IOMUX_PAD(0x4C8, 0x17C, 2, 0x0, 0, 0)
635#define _MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK IOMUX_PAD(0x4C8, 0x17C, 3, 0x0, 0, 0)
636#define _MX53_PAD_EIM_A16__SRC_BT_CFG1_1 IOMUX_PAD(0x4C8, 0x17C, 7, 0x0, 0, 0)
637#define _MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 IOMUX_PAD(0x4CC, 0x180, 0, 0x0, 0, 0)
638#define _MX53_PAD_EIM_CS0__GPIO2_23 IOMUX_PAD(0x4CC, 0x180, 1, 0x0, 0, 0)
639#define _MX53_PAD_EIM_CS0__ECSPI2_SCLK IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, 0)
640#define _MX53_PAD_EIM_CS0__IPU_DI1_PIN5 IOMUX_PAD(0x4CC, 0x180, 3, 0x0, 0, 0)
641#define _MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 IOMUX_PAD(0x4D0, 0x184, 0, 0x0, 0, 0)
642#define _MX53_PAD_EIM_CS1__GPIO2_24 IOMUX_PAD(0x4D0, 0x184, 1, 0x0, 0, 0)
643#define _MX53_PAD_EIM_CS1__ECSPI2_MOSI IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, 0)
644#define _MX53_PAD_EIM_CS1__IPU_DI1_PIN6 IOMUX_PAD(0x4D0, 0x184, 3, 0x0, 0, 0)
645#define _MX53_PAD_EIM_OE__EMI_WEIM_OE IOMUX_PAD(0x4D4, 0x188, 0, 0x0, 0, 0)
646#define _MX53_PAD_EIM_OE__GPIO2_25 IOMUX_PAD(0x4D4, 0x188, 1, 0x0, 0, 0)
647#define _MX53_PAD_EIM_OE__ECSPI2_MISO IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, 0)
648#define _MX53_PAD_EIM_OE__IPU_DI1_PIN7 IOMUX_PAD(0x4D4, 0x188, 3, 0x0, 0, 0)
649#define _MX53_PAD_EIM_OE__USBPHY2_IDDIG IOMUX_PAD(0x4D4, 0x188, 7, 0x0, 0, 0)
650#define _MX53_PAD_EIM_RW__EMI_WEIM_RW IOMUX_PAD(0x4D8, 0x18C, 0, 0x0, 0, 0)
651#define _MX53_PAD_EIM_RW__GPIO2_26 IOMUX_PAD(0x4D8, 0x18C, 1, 0x0, 0, 0)
652#define _MX53_PAD_EIM_RW__ECSPI2_SS0 IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, 0)
653#define _MX53_PAD_EIM_RW__IPU_DI1_PIN8 IOMUX_PAD(0x4D8, 0x18C, 3, 0x0, 0, 0)
654#define _MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT IOMUX_PAD(0x4D8, 0x18C, 7, 0x0, 0, 0)
655#define _MX53_PAD_EIM_LBA__EMI_WEIM_LBA IOMUX_PAD(0x4DC, 0x190, 0, 0x0, 0, 0)
656#define _MX53_PAD_EIM_LBA__GPIO2_27 IOMUX_PAD(0x4DC, 0x190, 1, 0x0, 0, 0)
657#define _MX53_PAD_EIM_LBA__ECSPI2_SS1 IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, 0)
658#define _MX53_PAD_EIM_LBA__IPU_DI1_PIN17 IOMUX_PAD(0x4DC, 0x190, 3, 0x0, 0, 0)
659#define _MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 IOMUX_PAD(0x4DC, 0x190, 7, 0x0, 0, 0)
660#define _MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 IOMUX_PAD(0x4E4, 0x194, 0, 0x0, 0, 0)
661#define _MX53_PAD_EIM_EB0__GPIO2_28 IOMUX_PAD(0x4E4, 0x194, 1, 0x0, 0, 0)
662#define _MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 IOMUX_PAD(0x4E4, 0x194, 3, 0x0, 0, 0)
663#define _MX53_PAD_EIM_EB0__IPU_CSI1_D_11 IOMUX_PAD(0x4E4, 0x194, 4, 0x0, 0, 0)
664#define _MX53_PAD_EIM_EB0__GPC_PMIC_RDY IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, 0)
665#define _MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 IOMUX_PAD(0x4E4, 0x194, 7, 0x0, 0, 0)
666#define _MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 IOMUX_PAD(0x4E8, 0x198, 0, 0x0, 0, 0)
667#define _MX53_PAD_EIM_EB1__GPIO2_29 IOMUX_PAD(0x4E8, 0x198, 1, 0x0, 0, 0)
668#define _MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 IOMUX_PAD(0x4E8, 0x198, 3, 0x0, 0, 0)
669#define _MX53_PAD_EIM_EB1__IPU_CSI1_D_10 IOMUX_PAD(0x4E8, 0x198, 4, 0x0, 0, 0)
670#define _MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 IOMUX_PAD(0x4E8, 0x198, 7, 0x0, 0, 0)
671#define _MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 IOMUX_PAD(0x4EC, 0x19C, 0, 0x0, 0, 0)
672#define _MX53_PAD_EIM_DA0__GPIO3_0 IOMUX_PAD(0x4EC, 0x19C, 1, 0x0, 0, 0)
673#define _MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 IOMUX_PAD(0x4EC, 0x19C, 3, 0x0, 0, 0)
674#define _MX53_PAD_EIM_DA0__IPU_CSI1_D_9 IOMUX_PAD(0x4EC, 0x19C, 4, 0x0, 0, 0)
675#define _MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 IOMUX_PAD(0x4EC, 0x19C, 7, 0x0, 0, 0)
676#define _MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 IOMUX_PAD(0x4F0, 0x1A0, 0, 0x0, 0, 0)
677#define _MX53_PAD_EIM_DA1__GPIO3_1 IOMUX_PAD(0x4F0, 0x1A0, 1, 0x0, 0, 0)
678#define _MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 IOMUX_PAD(0x4F0, 0x1A0, 3, 0x0, 0, 0)
679#define _MX53_PAD_EIM_DA1__IPU_CSI1_D_8 IOMUX_PAD(0x4F0, 0x1A0, 4, 0x0, 0, 0)
680#define _MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 IOMUX_PAD(0x4F0, 0x1A0, 7, 0x0, 0, 0)
681#define _MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 IOMUX_PAD(0x4F4, 0x1A4, 0, 0x0, 0, 0)
682#define _MX53_PAD_EIM_DA2__GPIO3_2 IOMUX_PAD(0x4F4, 0x1A4, 1, 0x0, 0, 0)
683#define _MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 IOMUX_PAD(0x4F4, 0x1A4, 3, 0x0, 0, 0)
684#define _MX53_PAD_EIM_DA2__IPU_CSI1_D_7 IOMUX_PAD(0x4F4, 0x1A4, 4, 0x0, 0, 0)
685#define _MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 IOMUX_PAD(0x4F4, 0x1A4, 7, 0x0, 0, 0)
686#define _MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 IOMUX_PAD(0x4F8, 0x1A8, 0, 0x0, 0, 0)
687#define _MX53_PAD_EIM_DA3__GPIO3_3 IOMUX_PAD(0x4F8, 0x1A8, 1, 0x0, 0, 0)
688#define _MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 IOMUX_PAD(0x4F8, 0x1A8, 3, 0x0, 0, 0)
689#define _MX53_PAD_EIM_DA3__IPU_CSI1_D_6 IOMUX_PAD(0x4F8, 0x1A8, 4, 0x0, 0, 0)
690#define _MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 IOMUX_PAD(0x4F8, 0x1A8, 7, 0x0, 0, 0)
691#define _MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 IOMUX_PAD(0x4FC, 0x1AC, 0, 0x0, 0, 0)
692#define _MX53_PAD_EIM_DA4__GPIO3_4 IOMUX_PAD(0x4FC, 0x1AC, 1, 0x0, 0, 0)
693#define _MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 IOMUX_PAD(0x4FC, 0x1AC, 3, 0x0, 0, 0)
694#define _MX53_PAD_EIM_DA4__IPU_CSI1_D_5 IOMUX_PAD(0x4FC, 0x1AC, 4, 0x0, 0, 0)
695#define _MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 IOMUX_PAD(0x4FC, 0x1AC, 7, 0x0, 0, 0)
696#define _MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 IOMUX_PAD(0x500, 0x1B0, 0, 0x0, 0, 0)
697#define _MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0)
698#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0)
699#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0)
700#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 17, 0x0, 0, 0)
701#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0)
702#define _MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0)
703#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0)
704#define _MX53_PAD_EIM_DA6__IPU_CSI1_D_3 IOMUX_PAD(0x504, 0x1B4, 4, 0x0, 0, 0)
705#define _MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 IOMUX_PAD(0x504, 0x1B4, 7, 0x0, 0, 0)
706#define _MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 IOMUX_PAD(0x508, 0x1B8, 0, 0x0, 0, 0)
707#define _MX53_PAD_EIM_DA7__GPIO3_7 IOMUX_PAD(0x508, 0x1B8, 1, 0x0, 0, 0)
708#define _MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 IOMUX_PAD(0x508, 0x1B8, 3, 0x0, 0, 0)
709#define _MX53_PAD_EIM_DA7__IPU_CSI1_D_2 IOMUX_PAD(0x508, 0x1B8, 4, 0x0, 0, 0)
710#define _MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 IOMUX_PAD(0x508, 0x1B8, 7, 0x0, 0, 0)
711#define _MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 IOMUX_PAD(0x50C, 0x1BC, 0, 0x0, 0, 0)
712#define _MX53_PAD_EIM_DA8__GPIO3_8 IOMUX_PAD(0x50C, 0x1BC, 1, 0x0, 0, 0)
713#define _MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 IOMUX_PAD(0x50C, 0x1BC, 3, 0x0, 0, 0)
714#define _MX53_PAD_EIM_DA8__IPU_CSI1_D_1 IOMUX_PAD(0x50C, 0x1BC, 4, 0x0, 0, 0)
715#define _MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 IOMUX_PAD(0x50C, 0x1BC, 7, 0x0, 0, 0)
716#define _MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 IOMUX_PAD(0x510, 0x1C0, 0, 0x0, 0, 0)
717#define _MX53_PAD_EIM_DA9__GPIO3_9 IOMUX_PAD(0x510, 0x1C0, 1, 0x0, 0, 0)
718#define _MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 IOMUX_PAD(0x510, 0x1C0, 3, 0x0, 0, 0)
719#define _MX53_PAD_EIM_DA9__IPU_CSI1_D_0 IOMUX_PAD(0x510, 0x1C0, 4, 0x0, 0, 0)
720#define _MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 IOMUX_PAD(0x510, 0x1C0, 7, 0x0, 0, 0)
721#define _MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 IOMUX_PAD(0x514, 0x1C4, 0, 0x0, 0, 0)
722#define _MX53_PAD_EIM_DA10__GPIO3_10 IOMUX_PAD(0x514, 0x1C4, 1, 0x0, 0, 0)
723#define _MX53_PAD_EIM_DA10__IPU_DI1_PIN15 IOMUX_PAD(0x514, 0x1C4, 3, 0x0, 0, 0)
724#define _MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, 0)
725#define _MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 IOMUX_PAD(0x514, 0x1C4, 7, 0x0, 0, 0)
726#define _MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 IOMUX_PAD(0x518, 0x1C8, 0, 0x0, 0, 0)
727#define _MX53_PAD_EIM_DA11__GPIO3_11 IOMUX_PAD(0x518, 0x1C8, 1, 0x0, 0, 0)
728#define _MX53_PAD_EIM_DA11__IPU_DI1_PIN2 IOMUX_PAD(0x518, 0x1C8, 3, 0x0, 0, 0)
729#define _MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, 0)
730#define _MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 IOMUX_PAD(0x51C, 0x1CC, 0, 0x0, 0, 0)
731#define _MX53_PAD_EIM_DA12__GPIO3_12 IOMUX_PAD(0x51C, 0x1CC, 1, 0x0, 0, 0)
732#define _MX53_PAD_EIM_DA12__IPU_DI1_PIN3 IOMUX_PAD(0x51C, 0x1CC, 3, 0x0, 0, 0)
733#define _MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, 0)
734#define _MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 IOMUX_PAD(0x520, 0x1D0, 0, 0x0, 0, 0)
735#define _MX53_PAD_EIM_DA13__GPIO3_13 IOMUX_PAD(0x520, 0x1D0, 1, 0x0, 0, 0)
736#define _MX53_PAD_EIM_DA13__IPU_DI1_D0_CS IOMUX_PAD(0x520, 0x1D0, 3, 0x0, 0, 0)
737#define _MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, 0)
738#define _MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 IOMUX_PAD(0x524, 0x1D4, 0, 0x0, 0, 0)
739#define _MX53_PAD_EIM_DA14__GPIO3_14 IOMUX_PAD(0x524, 0x1D4, 1, 0x0, 0, 0)
740#define _MX53_PAD_EIM_DA14__IPU_DI1_D1_CS IOMUX_PAD(0x524, 0x1D4, 3, 0x0, 0, 0)
741#define _MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK IOMUX_PAD(0x524, 0x1D4, 4, 0x0, 0, 0)
742#define _MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 IOMUX_PAD(0x528, 0x1D8, 0, 0x0, 0, 0)
743#define _MX53_PAD_EIM_DA15__GPIO3_15 IOMUX_PAD(0x528, 0x1D8, 1, 0x0, 0, 0)
744#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN1 IOMUX_PAD(0x528, 0x1D8, 3, 0x0, 0, 0)
745#define _MX53_PAD_EIM_DA15__IPU_DI1_PIN4 IOMUX_PAD(0x528, 0x1D8, 4, 0x0, 0, 0)
746#define _MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B IOMUX_PAD(0x52C, 0x1DC, 0, 0x0, 0, 0)
747#define _MX53_PAD_NANDF_WE_B__GPIO6_12 IOMUX_PAD(0x52C, 0x1DC, 1, 0x0, 0, 0)
748#define _MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B IOMUX_PAD(0x530, 0x1E0, 0, 0x0, 0, 0)
749#define _MX53_PAD_NANDF_RE_B__GPIO6_13 IOMUX_PAD(0x530, 0x1E0, 1, 0x0, 0, 0)
750#define _MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT IOMUX_PAD(0x534, 0x1E4, 0, 0x0, 0, 0)
751#define _MX53_PAD_EIM_WAIT__GPIO5_0 IOMUX_PAD(0x534, 0x1E4, 1, 0x0, 0, 0)
752#define _MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B IOMUX_PAD(0x534, 0x1E4, 2, 0x0, 0, 0)
753#define _MX53_PAD_LVDS1_TX3_P__GPIO6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, 0, 0x0, 0, 0)
754#define _MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 IOMUX_PAD(NON_PAD_I, 0x1EC, 1, 0x0, 0, 0)
755#define _MX53_PAD_LVDS1_TX2_P__GPIO6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, 0, 0x0, 0, 0)
756#define _MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 IOMUX_PAD(NON_PAD_I, 0x1F0, 1, 0x0, 0, 0)
757#define _MX53_PAD_LVDS1_CLK_P__GPIO6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, 0, 0x0, 0, 0)
758#define _MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK IOMUX_PAD(NON_PAD_I, 0x1F4, 1, 0x0, 0, 0)
759#define _MX53_PAD_LVDS1_TX1_P__GPIO6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, 0, 0x0, 0, 0)
760#define _MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 IOMUX_PAD(NON_PAD_I, 0x1F8, 1, 0x0, 0, 0)
761#define _MX53_PAD_LVDS1_TX0_P__GPIO6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, 0, 0x0, 0, 0)
762#define _MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 IOMUX_PAD(NON_PAD_I, 0x1FC, 1, 0x0, 0, 0)
763#define _MX53_PAD_LVDS0_TX3_P__GPIO7_22 IOMUX_PAD(NON_PAD_I, 0x200, 0, 0x0, 0, 0)
764#define _MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 IOMUX_PAD(NON_PAD_I, 0x200, 1, 0x0, 0, 0)
765#define _MX53_PAD_LVDS0_CLK_P__GPIO7_24 IOMUX_PAD(NON_PAD_I, 0x204, 0, 0x0, 0, 0)
766#define _MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK IOMUX_PAD(NON_PAD_I, 0x204, 1, 0x0, 0, 0)
767#define _MX53_PAD_LVDS0_TX2_P__GPIO7_26 IOMUX_PAD(NON_PAD_I, 0x208, 0, 0x0, 0, 0)
768#define _MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 IOMUX_PAD(NON_PAD_I, 0x208, 1, 0x0, 0, 0)
769#define _MX53_PAD_LVDS0_TX1_P__GPIO7_28 IOMUX_PAD(NON_PAD_I, 0x20C, 0, 0x0, 0, 0)
770#define _MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 IOMUX_PAD(NON_PAD_I, 0x20C, 1, 0x0, 0, 0)
771#define _MX53_PAD_LVDS0_TX0_P__GPIO7_30 IOMUX_PAD(NON_PAD_I, 0x210, 0, 0x0, 0, 0)
772#define _MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 IOMUX_PAD(NON_PAD_I, 0x210, 1, 0x0, 0, 0)
773#define _MX53_PAD_GPIO_10__GPIO4_0 IOMUX_PAD(0x540, 0x214, 0, 0x0, 0, 0)
774#define _MX53_PAD_GPIO_10__OSC32k_32K_OUT IOMUX_PAD(0x540, 0x214, 1, 0x0, 0, 0)
775#define _MX53_PAD_GPIO_11__GPIO4_1 IOMUX_PAD(0x544, 0x218, 0, 0x0, 0, 0)
776#define _MX53_PAD_GPIO_12__GPIO4_2 IOMUX_PAD(0x548, 0x21C, 0, 0x0, 0, 0)
777#define _MX53_PAD_GPIO_13__GPIO4_3 IOMUX_PAD(0x54C, 0x220, 0, 0x0, 0, 0)
778#define _MX53_PAD_GPIO_14__GPIO4_4 IOMUX_PAD(0x550, 0x224, 0, 0x0, 0, 0)
779#define _MX53_PAD_NANDF_CLE__EMI_NANDF_CLE IOMUX_PAD(0x5A0, 0x228, 0, 0x0, 0, 0)
780#define _MX53_PAD_NANDF_CLE__GPIO6_7 IOMUX_PAD(0x5A0, 0x228, 1, 0x0, 0, 0)
781#define _MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 IOMUX_PAD(0x5A0, 0x228, 7, 0x0, 0, 0)
782#define _MX53_PAD_NANDF_ALE__EMI_NANDF_ALE IOMUX_PAD(0x5A4, 0x22C, 0, 0x0, 0, 0)
783#define _MX53_PAD_NANDF_ALE__GPIO6_8 IOMUX_PAD(0x5A4, 0x22C, 1, 0x0, 0, 0)
784#define _MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 IOMUX_PAD(0x5A4, 0x22C, 7, 0x0, 0, 0)
785#define _MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B IOMUX_PAD(0x5A8, 0x230, 0, 0x0, 0, 0)
786#define _MX53_PAD_NANDF_WP_B__GPIO6_9 IOMUX_PAD(0x5A8, 0x230, 1, 0x0, 0, 0)
787#define _MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 IOMUX_PAD(0x5A8, 0x230, 7, 0x0, 0, 0)
788#define _MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 IOMUX_PAD(0x5AC, 0x234, 0, 0x0, 0, 0)
789#define _MX53_PAD_NANDF_RB0__GPIO6_10 IOMUX_PAD(0x5AC, 0x234, 1, 0x0, 0, 0)
790#define _MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 IOMUX_PAD(0x5AC, 0x234, 7, 0x0, 0, 0)
791#define _MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 IOMUX_PAD(0x5B0, 0x238, 0, 0x0, 0, 0)
792#define _MX53_PAD_NANDF_CS0__GPIO6_11 IOMUX_PAD(0x5B0, 0x238, 1, 0x0, 0, 0)
793#define _MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 IOMUX_PAD(0x5B0, 0x238, 7, 0x0, 0, 0)
794#define _MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 IOMUX_PAD(0x5B4, 0x23C, 0, 0x0, 0, 0)
795#define _MX53_PAD_NANDF_CS1__GPIO6_14 IOMUX_PAD(0x5B4, 0x23C, 1, 0x0, 0, 0)
796#define _MX53_PAD_NANDF_CS1__MLB_MLBCLK IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, 0)
797#define _MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 IOMUX_PAD(0x5B4, 0x23C, 7, 0x0, 0, 0)
798#define _MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 IOMUX_PAD(0x5B8, 0x240, 0, 0x0, 0, 0)
799#define _MX53_PAD_NANDF_CS2__GPIO6_15 IOMUX_PAD(0x5B8, 0x240, 1, 0x0, 0, 0)
800#define _MX53_PAD_NANDF_CS2__IPU_SISG_0 IOMUX_PAD(0x5B8, 0x240, 2, 0x0, 0, 0)
801#define _MX53_PAD_NANDF_CS2__ESAI1_TX0 IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, 0)
802#define _MX53_PAD_NANDF_CS2__EMI_WEIM_CRE IOMUX_PAD(0x5B8, 0x240, 4, 0x0, 0, 0)
803#define _MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK IOMUX_PAD(0x5B8, 0x240, 5, 0x0, 0, 0)
804#define _MX53_PAD_NANDF_CS2__MLB_MLBSIG IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, 0)
805#define _MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 IOMUX_PAD(0x5B8, 0x240, 7, 0x0, 0, 0)
806#define _MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 IOMUX_PAD(0x5BC, 0x244, 0, 0x0, 0, 0)
807#define _MX53_PAD_NANDF_CS3__GPIO6_16 IOMUX_PAD(0x5BC, 0x244, 1, 0x0, 0, 0)
808#define _MX53_PAD_NANDF_CS3__IPU_SISG_1 IOMUX_PAD(0x5BC, 0x244, 2, 0x0, 0, 0)
809#define _MX53_PAD_NANDF_CS3__ESAI1_TX1 IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, 0)
810#define _MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 IOMUX_PAD(0x5BC, 0x244, 4, 0x0, 0, 0)
811#define _MX53_PAD_NANDF_CS3__MLB_MLBDAT IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, 0)
812#define _MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 IOMUX_PAD(0x5BC, 0x244, 7, 0x0, 0, 0)
813#define _MX53_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, 0)
814#define _MX53_PAD_FEC_MDIO__GPIO1_22 IOMUX_PAD(0x5C4, 0x248, 1, 0x0, 0, 0)
815#define _MX53_PAD_FEC_MDIO__ESAI1_SCKR IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, 0)
816#define _MX53_PAD_FEC_MDIO__FEC_COL IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, 0)
817#define _MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 IOMUX_PAD(0x5C4, 0x248, 4, 0x0, 0, 0)
818#define _MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x5C4, 0x248, 5, 0x0, 0, 0)
819#define _MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 IOMUX_PAD(0x5C4, 0x248, 6, 0x0, 0, 0)
820#define _MX53_PAD_FEC_REF_CLK__FEC_TX_CLK IOMUX_PAD(0x5C8, 0x24C, 0, 0x0, 0, 0)
821#define _MX53_PAD_FEC_REF_CLK__GPIO1_23 IOMUX_PAD(0x5C8, 0x24C, 1, 0x0, 0, 0)
822#define _MX53_PAD_FEC_REF_CLK__ESAI1_FSR IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, 0)
823#define _MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 IOMUX_PAD(0x5C8, 0x24C, 5, 0x0, 0, 0)
824#define _MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 IOMUX_PAD(0x5C8, 0x24C, 6, 0x0, 0, 0)
825#define _MX53_PAD_FEC_RX_ER__FEC_RX_ER IOMUX_PAD(0x5CC, 0x250, 0, 0x0, 0, 0)
826#define _MX53_PAD_FEC_RX_ER__GPIO1_24 IOMUX_PAD(0x5CC, 0x250, 1, 0x0, 0, 0)
827#define _MX53_PAD_FEC_RX_ER__ESAI1_HCKR IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, 0)
828#define _MX53_PAD_FEC_RX_ER__FEC_RX_CLK IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, 0)
829#define _MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 IOMUX_PAD(0x5CC, 0x250, 4, 0x0, 0, 0)
830#define _MX53_PAD_FEC_CRS_DV__FEC_RX_DV IOMUX_PAD(0x5D0, 0x254, 0, 0x0, 0, 0)
831#define _MX53_PAD_FEC_CRS_DV__GPIO1_25 IOMUX_PAD(0x5D0, 0x254, 1, 0x0, 0, 0)
832#define _MX53_PAD_FEC_CRS_DV__ESAI1_SCKT IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, 0)
833#define _MX53_PAD_FEC_RXD1__FEC_RDATA_1 IOMUX_PAD(0x5D4, 0x258, 0, 0x0, 0, 0)
834#define _MX53_PAD_FEC_RXD1__GPIO1_26 IOMUX_PAD(0x5D4, 0x258, 1, 0x0, 0, 0)
835#define _MX53_PAD_FEC_RXD1__ESAI1_FST IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, 0)
836#define _MX53_PAD_FEC_RXD1__MLB_MLBSIG IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, 0)
837#define _MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 IOMUX_PAD(0x5D4, 0x258, 4, 0x0, 0, 0)
838#define _MX53_PAD_FEC_RXD0__FEC_RDATA_0 IOMUX_PAD(0x5D8, 0x25C, 0, 0x0, 0, 0)
839#define _MX53_PAD_FEC_RXD0__GPIO1_27 IOMUX_PAD(0x5D8, 0x25C, 1, 0x0, 0, 0)
840#define _MX53_PAD_FEC_RXD0__ESAI1_HCKT IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, 0)
841#define _MX53_PAD_FEC_RXD0__OSC32k_32K_OUT IOMUX_PAD(0x5D8, 0x25C, 3, 0x0, 0, 0)
842#define _MX53_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x5DC, 0x260, 0, 0x0, 0, 0)
843#define _MX53_PAD_FEC_TX_EN__GPIO1_28 IOMUX_PAD(0x5DC, 0x260, 1, 0x0, 0, 0)
844#define _MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, 0)
845#define _MX53_PAD_FEC_TXD1__FEC_TDATA_1 IOMUX_PAD(0x5E0, 0x264, 0, 0x0, 0, 0)
846#define _MX53_PAD_FEC_TXD1__GPIO1_29 IOMUX_PAD(0x5E0, 0x264, 1, 0x0, 0, 0)
847#define _MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, 0)
848#define _MX53_PAD_FEC_TXD1__MLB_MLBCLK IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, 0)
849#define _MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK IOMUX_PAD(0x5E0, 0x264, 4, 0x0, 0, 0)
850#define _MX53_PAD_FEC_TXD0__FEC_TDATA_0 IOMUX_PAD(0x5E4, 0x268, 0, 0x0, 0, 0)
851#define _MX53_PAD_FEC_TXD0__GPIO1_30 IOMUX_PAD(0x5E4, 0x268, 1, 0x0, 0, 0)
852#define _MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, 0)
853#define _MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 IOMUX_PAD(0x5E4, 0x268, 7, 0x0, 0, 0)
854#define _MX53_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x5E8, 0x26C, 0, 0x0, 0, 0)
855#define _MX53_PAD_FEC_MDC__GPIO1_31 IOMUX_PAD(0x5E8, 0x26C, 1, 0x0, 0, 0)
856#define _MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, 0)
857#define _MX53_PAD_FEC_MDC__MLB_MLBDAT IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, 0)
858#define _MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG IOMUX_PAD(0x5E8, 0x26C, 4, 0x0, 0, 0)
859#define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0)
860#define _MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0)
861#define _MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0)
862#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, 0x878, 2, 0)
863#define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0)
864#define _MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0)
865#define _MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0)
866#define _MX53_PAD_PATA_DMACK__UART1_RXD_MUX IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, 0)
867#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0)
868#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0)
869#define _MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0)
870#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0x880, 2, 0)
871#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0)
872#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0)
873#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0)
874#define _MX53_PAD_PATA_BUFFER_EN__GPIO7_1 IOMUX_PAD(0x5FC, 0x27C, 1, 0x0, 0, 0)
875#define _MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, 0)
876#define _MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 IOMUX_PAD(0x5FC, 0x27C, 5, 0x0, 0, 0)
877#define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0)
878#define _MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0)
879#define _MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0)
880#define _MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x87C, 2, 0)
881#define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0)
882#define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0)
883#define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0)
884#define _MX53_PAD_PATA_DIOR__PATA_DIOR IOMUX_PAD(0x604, 0x284, 0, 0x0, 0, 0)
885#define _MX53_PAD_PATA_DIOR__GPIO7_3 IOMUX_PAD(0x604, 0x284, 1, 0x0, 0, 0)
886#define _MX53_PAD_PATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, 0)
887#define _MX53_PAD_PATA_DIOR__CAN1_RXCAN IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, 0)
888#define _MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 IOMUX_PAD(0x604, 0x284, 7, 0x0, 0, 0)
889#define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0)
890#define _MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0)
891#define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0)
892#define _MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, 0x874, 2, 0)
893#define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0)
894#define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0)
895#define _MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0)
896#define _MX53_PAD_PATA_IORDY__GPIO7_5 IOMUX_PAD(0x60C, 0x28C, 1, 0x0, 0, 0)
897#define _MX53_PAD_PATA_IORDY__ESDHC3_CLK IOMUX_PAD(0x60C, 0x28C, 2, 0x0, 0, 0)
898#define _MX53_PAD_PATA_IORDY__UART1_RTS IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, 0)
899#define _MX53_PAD_PATA_IORDY__CAN2_RXCAN IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, 0)
900#define _MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 IOMUX_PAD(0x60C, 0x28C, 7, 0x0, 0, 0)
901#define _MX53_PAD_PATA_DA_0__PATA_DA_0 IOMUX_PAD(0x610, 0x290, 0, 0x0, 0, 0)
902#define _MX53_PAD_PATA_DA_0__GPIO7_6 IOMUX_PAD(0x610, 0x290, 1, 0x0, 0, 0)
903#define _MX53_PAD_PATA_DA_0__ESDHC3_RST IOMUX_PAD(0x610, 0x290, 2, 0x0, 0, 0)
904#define _MX53_PAD_PATA_DA_0__OWIRE_LINE IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, 0)
905#define _MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 IOMUX_PAD(0x610, 0x290, 7, 0x0, 0, 0)
906#define _MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0)
907#define _MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0)
908#define _MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0)
909#define _MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x884, 4, 0)
910#define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0)
911#define _MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0)
912#define _MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0)
913#define _MX53_PAD_PATA_DA_2__ESDHC4_CLK IOMUX_PAD(0x618, 0x298, 2, 0x0, 0, 0)
914#define _MX53_PAD_PATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, 0)
915#define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0)
916#define _MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0)
917#define _MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0)
918#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, 0x888, 2, 0)
919#define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0)
920#define _MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0)
921#define _MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0)
922#define _MX53_PAD_PATA_CS_1__UART3_RXD_MUX IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, 0)
923#define _MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 IOMUX_PAD(0x620, 0x2A0, 7, 0x0, 0, 0)
924#define _MX53_PAD_PATA_DATA0__PATA_DATA_0 IOMUX_PAD(0x628, 0x2A4, 0, 0x0, 0, 0)
925#define _MX53_PAD_PATA_DATA0__GPIO2_0 IOMUX_PAD(0x628, 0x2A4, 1, 0x0, 0, 0)
926#define _MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 IOMUX_PAD(0x628, 0x2A4, 3, 0x0, 0, 0)
927#define _MX53_PAD_PATA_DATA0__ESDHC3_DAT4 IOMUX_PAD(0x628, 0x2A4, 4, 0x0, 0, 0)
928#define _MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 IOMUX_PAD(0x628, 0x2A4, 5, 0x0, 0, 0)
929#define _MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 IOMUX_PAD(0x628, 0x2A4, 6, 0x0, 0, 0)
930#define _MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 IOMUX_PAD(0x628, 0x2A4, 7, 0x0, 0, 0)
931#define _MX53_PAD_PATA_DATA1__PATA_DATA_1 IOMUX_PAD(0x62C, 0x2A8, 0, 0x0, 0, 0)
932#define _MX53_PAD_PATA_DATA1__GPIO2_1 IOMUX_PAD(0x62C, 0x2A8, 1, 0x0, 0, 0)
933#define _MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 IOMUX_PAD(0x62C, 0x2A8, 3, 0x0, 0, 0)
934#define _MX53_PAD_PATA_DATA1__ESDHC3_DAT5 IOMUX_PAD(0x62C, 0x2A8, 4, 0x0, 0, 0)
935#define _MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 IOMUX_PAD(0x62C, 0x2A8, 5, 0x0, 0, 0)
936#define _MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 IOMUX_PAD(0x62C, 0x2A8, 6, 0x0, 0, 0)
937#define _MX53_PAD_PATA_DATA2__PATA_DATA_2 IOMUX_PAD(0x630, 0x2AC, 0, 0x0, 0, 0)
938#define _MX53_PAD_PATA_DATA2__GPIO2_2 IOMUX_PAD(0x630, 0x2AC, 1, 0x0, 0, 0)
939#define _MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 IOMUX_PAD(0x630, 0x2AC, 3, 0x0, 0, 0)
940#define _MX53_PAD_PATA_DATA2__ESDHC3_DAT6 IOMUX_PAD(0x630, 0x2AC, 4, 0x0, 0, 0)
941#define _MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 IOMUX_PAD(0x630, 0x2AC, 5, 0x0, 0, 0)
942#define _MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 IOMUX_PAD(0x630, 0x2AC, 6, 0x0, 0, 0)
943#define _MX53_PAD_PATA_DATA3__PATA_DATA_3 IOMUX_PAD(0x634, 0x2B0, 0, 0x0, 0, 0)
944#define _MX53_PAD_PATA_DATA3__GPIO2_3 IOMUX_PAD(0x634, 0x2B0, 1, 0x0, 0, 0)
945#define _MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 IOMUX_PAD(0x634, 0x2B0, 3, 0x0, 0, 0)
946#define _MX53_PAD_PATA_DATA3__ESDHC3_DAT7 IOMUX_PAD(0x634, 0x2B0, 4, 0x0, 0, 0)
947#define _MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 IOMUX_PAD(0x634, 0x2B0, 5, 0x0, 0, 0)
948#define _MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 IOMUX_PAD(0x634, 0x2B0, 6, 0x0, 0, 0)
949#define _MX53_PAD_PATA_DATA4__PATA_DATA_4 IOMUX_PAD(0x638, 0x2B4, 0, 0x0, 0, 0)
950#define _MX53_PAD_PATA_DATA4__GPIO2_4 IOMUX_PAD(0x638, 0x2B4, 1, 0x0, 0, 0)
951#define _MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 IOMUX_PAD(0x638, 0x2B4, 3, 0x0, 0, 0)
952#define _MX53_PAD_PATA_DATA4__ESDHC4_DAT4 IOMUX_PAD(0x638, 0x2B4, 4, 0x0, 0, 0)
953#define _MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 IOMUX_PAD(0x638, 0x2B4, 5, 0x0, 0, 0)
954#define _MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 IOMUX_PAD(0x638, 0x2B4, 6, 0x0, 0, 0)
955#define _MX53_PAD_PATA_DATA5__PATA_DATA_5 IOMUX_PAD(0x63C, 0x2B8, 0, 0x0, 0, 0)
956#define _MX53_PAD_PATA_DATA5__GPIO2_5 IOMUX_PAD(0x63C, 0x2B8, 1, 0x0, 0, 0)
957#define _MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 IOMUX_PAD(0x63C, 0x2B8, 3, 0x0, 0, 0)
958#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0)
959#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0)
960#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0)
961#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
962#define _MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
963#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
964#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
965#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
966#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
967#define _MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0)
968#define _MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0)
969#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0)
970#define _MX53_PAD_PATA_DATA7__ESDHC4_DAT7 IOMUX_PAD(0x644, 0x2C0, 4, 0x0, 0, 0)
971#define _MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 IOMUX_PAD(0x644, 0x2C0, 5, 0x0, 0, 0)
972#define _MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 IOMUX_PAD(0x644, 0x2C0, 6, 0x0, 0, 0)
973#define _MX53_PAD_PATA_DATA8__PATA_DATA_8 IOMUX_PAD(0x648, 0x2C4, 0, 0x0, 0, 0)
974#define _MX53_PAD_PATA_DATA8__GPIO2_8 IOMUX_PAD(0x648, 0x2C4, 1, 0x0, 0, 0)
975#define _MX53_PAD_PATA_DATA8__ESDHC1_DAT4 IOMUX_PAD(0x648, 0x2C4, 2, 0x0, 0, 0)
976#define _MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 IOMUX_PAD(0x648, 0x2C4, 3, 0x0, 0, 0)
977#define _MX53_PAD_PATA_DATA8__ESDHC3_DAT0 IOMUX_PAD(0x648, 0x2C4, 4, 0x0, 0, 0)
978#define _MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 IOMUX_PAD(0x648, 0x2C4, 5, 0x0, 0, 0)
979#define _MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 IOMUX_PAD(0x648, 0x2C4, 6, 0x0, 0, 0)
980#define _MX53_PAD_PATA_DATA9__PATA_DATA_9 IOMUX_PAD(0x64C, 0x2C8, 0, 0x0, 0, 0)
981#define _MX53_PAD_PATA_DATA9__GPIO2_9 IOMUX_PAD(0x64C, 0x2C8, 1, 0x0, 0, 0)
982#define _MX53_PAD_PATA_DATA9__ESDHC1_DAT5 IOMUX_PAD(0x64C, 0x2C8, 2, 0x0, 0, 0)
983#define _MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 IOMUX_PAD(0x64C, 0x2C8, 3, 0x0, 0, 0)
984#define _MX53_PAD_PATA_DATA9__ESDHC3_DAT1 IOMUX_PAD(0x64C, 0x2C8, 4, 0x0, 0, 0)
985#define _MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 IOMUX_PAD(0x64C, 0x2C8, 5, 0x0, 0, 0)
986#define _MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 IOMUX_PAD(0x64C, 0x2C8, 6, 0x0, 0, 0)
987#define _MX53_PAD_PATA_DATA10__PATA_DATA_10 IOMUX_PAD(0x650, 0x2CC, 0, 0x0, 0, 0)
988#define _MX53_PAD_PATA_DATA10__GPIO2_10 IOMUX_PAD(0x650, 0x2CC, 1, 0x0, 0, 0)
989#define _MX53_PAD_PATA_DATA10__ESDHC1_DAT6 IOMUX_PAD(0x650, 0x2CC, 2, 0x0, 0, 0)
990#define _MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 IOMUX_PAD(0x650, 0x2CC, 3, 0x0, 0, 0)
991#define _MX53_PAD_PATA_DATA10__ESDHC3_DAT2 IOMUX_PAD(0x650, 0x2CC, 4, 0x0, 0, 0)
992#define _MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 IOMUX_PAD(0x650, 0x2CC, 5, 0x0, 0, 0)
993#define _MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 IOMUX_PAD(0x650, 0x2CC, 6, 0x0, 0, 0)
994#define _MX53_PAD_PATA_DATA11__PATA_DATA_11 IOMUX_PAD(0x654, 0x2D0, 0, 0x0, 0, 0)
995#define _MX53_PAD_PATA_DATA11__GPIO2_11 IOMUX_PAD(0x654, 0x2D0, 1, 0x0, 0, 0)
996#define _MX53_PAD_PATA_DATA11__ESDHC1_DAT7 IOMUX_PAD(0x654, 0x2D0, 2, 0x0, 0, 0)
997#define _MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 IOMUX_PAD(0x654, 0x2D0, 3, 0x0, 0, 0)
998#define _MX53_PAD_PATA_DATA11__ESDHC3_DAT3 IOMUX_PAD(0x654, 0x2D0, 4, 0x0, 0, 0)
999#define _MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 IOMUX_PAD(0x654, 0x2D0, 5, 0x0, 0, 0)
1000#define _MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 IOMUX_PAD(0x654, 0x2D0, 6, 0x0, 0, 0)
1001#define _MX53_PAD_PATA_DATA12__PATA_DATA_12 IOMUX_PAD(0x658, 0x2D4, 0, 0x0, 0, 0)
1002#define _MX53_PAD_PATA_DATA12__GPIO2_12 IOMUX_PAD(0x658, 0x2D4, 1, 0x0, 0, 0)
1003#define _MX53_PAD_PATA_DATA12__ESDHC2_DAT4 IOMUX_PAD(0x658, 0x2D4, 2, 0x0, 0, 0)
1004#define _MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 IOMUX_PAD(0x658, 0x2D4, 3, 0x0, 0, 0)
1005#define _MX53_PAD_PATA_DATA12__ESDHC4_DAT0 IOMUX_PAD(0x658, 0x2D4, 4, 0x0, 0, 0)
1006#define _MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 IOMUX_PAD(0x658, 0x2D4, 5, 0x0, 0, 0)
1007#define _MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 IOMUX_PAD(0x658, 0x2D4, 6, 0x0, 0, 0)
1008#define _MX53_PAD_PATA_DATA13__PATA_DATA_13 IOMUX_PAD(0x65C, 0x2D8, 0, 0x0, 0, 0)
1009#define _MX53_PAD_PATA_DATA13__GPIO2_13 IOMUX_PAD(0x65C, 0x2D8, 1, 0x0, 0, 0)
1010#define _MX53_PAD_PATA_DATA13__ESDHC2_DAT5 IOMUX_PAD(0x65C, 0x2D8, 2, 0x0, 0, 0)
1011#define _MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 IOMUX_PAD(0x65C, 0x2D8, 3, 0x0, 0, 0)
1012#define _MX53_PAD_PATA_DATA13__ESDHC4_DAT1 IOMUX_PAD(0x65C, 0x2D8, 4, 0x0, 0, 0)
1013#define _MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 IOMUX_PAD(0x65C, 0x2D8, 5, 0x0, 0, 0)
1014#define _MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 IOMUX_PAD(0x65C, 0x2D8, 6, 0x0, 0, 0)
1015#define _MX53_PAD_PATA_DATA14__PATA_DATA_14 IOMUX_PAD(0x660, 0x2DC, 0, 0x0, 0, 0)
1016#define _MX53_PAD_PATA_DATA14__GPIO2_14 IOMUX_PAD(0x660, 0x2DC, 1, 0x0, 0, 0)
1017#define _MX53_PAD_PATA_DATA14__ESDHC2_DAT6 IOMUX_PAD(0x660, 0x2DC, 2, 0x0, 0, 0)
1018#define _MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 IOMUX_PAD(0x660, 0x2DC, 3, 0x0, 0, 0)
1019#define _MX53_PAD_PATA_DATA14__ESDHC4_DAT2 IOMUX_PAD(0x660, 0x2DC, 4, 0x0, 0, 0)
1020#define _MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 IOMUX_PAD(0x660, 0x2DC, 5, 0x0, 0, 0)
1021#define _MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 IOMUX_PAD(0x660, 0x2DC, 6, 0x0, 0, 0)
1022#define _MX53_PAD_PATA_DATA15__PATA_DATA_15 IOMUX_PAD(0x664, 0x2E0, 0, 0x0, 0, 0)
1023#define _MX53_PAD_PATA_DATA15__GPIO2_15 IOMUX_PAD(0x664, 0x2E0, 1, 0x0, 0, 0)
1024#define _MX53_PAD_PATA_DATA15__ESDHC2_DAT7 IOMUX_PAD(0x664, 0x2E0, 2, 0x0, 0, 0)
1025#define _MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 IOMUX_PAD(0x664, 0x2E0, 3, 0x0, 0, 0)
1026#define _MX53_PAD_PATA_DATA15__ESDHC4_DAT3 IOMUX_PAD(0x664, 0x2E0, 4, 0x0, 0, 0)
1027#define _MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 IOMUX_PAD(0x664, 0x2E0, 5, 0x0, 0, 0)
1028#define _MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 IOMUX_PAD(0x664, 0x2E0, 6, 0x0, 0, 0)
1029#define _MX53_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x66C, 0x2E4, 0, 0x0, 0, 0)
1030#define _MX53_PAD_SD1_DATA0__GPIO1_16 IOMUX_PAD(0x66C, 0x2E4, 1, 0x0, 0, 0)
1031#define _MX53_PAD_SD1_DATA0__GPT_CAPIN1 IOMUX_PAD(0x66C, 0x2E4, 3, 0x0, 0, 0)
1032#define _MX53_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, 0)
1033#define _MX53_PAD_SD1_DATA0__CCM_PLL3_BYP IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, 0)
1034#define _MX53_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x670, 0x2E8, 0, 0x0, 0, 0)
1035#define _MX53_PAD_SD1_DATA1__GPIO1_17 IOMUX_PAD(0x670, 0x2E8, 1, 0x0, 0, 0)
1036#define _MX53_PAD_SD1_DATA1__GPT_CAPIN2 IOMUX_PAD(0x670, 0x2E8, 3, 0x0, 0, 0)
1037#define _MX53_PAD_SD1_DATA1__CSPI_SS0 IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, 0)
1038#define _MX53_PAD_SD1_DATA1__CCM_PLL4_BYP IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, 0)
1039#define _MX53_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x674, 0x2EC, IOMUX_CONFIG_SION, 0x0, 0, 0)
1040#define _MX53_PAD_SD1_CMD__GPIO1_18 IOMUX_PAD(0x674, 0x2EC, 1, 0x0, 0, 0)
1041#define _MX53_PAD_SD1_CMD__GPT_CMPOUT1 IOMUX_PAD(0x674, 0x2EC, 3, 0x0, 0, 0)
1042#define _MX53_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, 0)
1043#define _MX53_PAD_SD1_CMD__CCM_PLL1_BYP IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, 0)
1044#define _MX53_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x678, 0x2F0, 0, 0x0, 0, 0)
1045#define _MX53_PAD_SD1_DATA2__GPIO1_19 IOMUX_PAD(0x678, 0x2F0, 1, 0x0, 0, 0)
1046#define _MX53_PAD_SD1_DATA2__GPT_CMPOUT2 IOMUX_PAD(0x678, 0x2F0, 2, 0x0, 0, 0)
1047#define _MX53_PAD_SD1_DATA2__PWM2_PWMO IOMUX_PAD(0x678, 0x2F0, 3, 0x0, 0, 0)
1048#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_B IOMUX_PAD(0x678, 0x2F0, 4, 0x0, 0, 0)
1049#define _MX53_PAD_SD1_DATA2__CSPI_SS1 IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, 0)
1050#define _MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB IOMUX_PAD(0x678, 0x2F0, 6, 0x0, 0, 0)
1051#define _MX53_PAD_SD1_DATA2__CCM_PLL2_BYP IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, 0)
1052#define _MX53_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x67C, 0x2F4, 0, 0x0, 0, 0)
1053#define _MX53_PAD_SD1_CLK__GPIO1_20 IOMUX_PAD(0x67C, 0x2F4, 1, 0x0, 0, 0)
1054#define _MX53_PAD_SD1_CLK__OSC32k_32K_OUT IOMUX_PAD(0x67C, 0x2F4, 2, 0x0, 0, 0)
1055#define _MX53_PAD_SD1_CLK__GPT_CLKIN IOMUX_PAD(0x67C, 0x2F4, 3, 0x0, 0, 0)
1056#define _MX53_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, 0)
1057#define _MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 IOMUX_PAD(0x67C, 0x2F4, 7, 0x0, 0, 0)
1058#define _MX53_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x680, 0x2F8, 0, 0x0, 0, 0)
1059#define _MX53_PAD_SD1_DATA3__GPIO1_21 IOMUX_PAD(0x680, 0x2F8, 1, 0x0, 0, 0)
1060#define _MX53_PAD_SD1_DATA3__GPT_CMPOUT3 IOMUX_PAD(0x680, 0x2F8, 2, 0x0, 0, 0)
1061#define _MX53_PAD_SD1_DATA3__PWM1_PWMO IOMUX_PAD(0x680, 0x2F8, 3, 0x0, 0, 0)
1062#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_B IOMUX_PAD(0x680, 0x2F8, 4, 0x0, 0, 0)
1063#define _MX53_PAD_SD1_DATA3__CSPI_SS2 IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, 0)
1064#define _MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB IOMUX_PAD(0x680, 0x2F8, 6, 0x0, 0, 0)
1065#define _MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 IOMUX_PAD(0x680, 0x2F8, 7, 0x0, 0, 0)
1066#define _MX53_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x688, 0x2FC, 0, 0x0, 0, 0)
1067#define _MX53_PAD_SD2_CLK__GPIO1_10 IOMUX_PAD(0x688, 0x2FC, 1, 0x0, 0, 0)
1068#define _MX53_PAD_SD2_CLK__KPP_COL_5 IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, 0)
1069#define _MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, 0)
1070#define _MX53_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, 0)
1071#define _MX53_PAD_SD2_CLK__SCC_RANDOM_V IOMUX_PAD(0x688, 0x2FC, 7, 0x0, 0, 0)
1072#define _MX53_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x68C, 0x300, 0, 0x0, 0, 0)
1073#define _MX53_PAD_SD2_CMD__GPIO1_11 IOMUX_PAD(0x68C, 0x300, 1, 0x0, 0, 0)
1074#define _MX53_PAD_SD2_CMD__KPP_ROW_5 IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, 0)
1075#define _MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, 0)
1076#define _MX53_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, 0)
1077#define _MX53_PAD_SD2_CMD__SCC_RANDOM IOMUX_PAD(0x68C, 0x300, 7, 0x0, 0, 0)
1078#define _MX53_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x690, 0x304, 0, 0x0, 0, 0)
1079#define _MX53_PAD_SD2_DATA3__GPIO1_12 IOMUX_PAD(0x690, 0x304, 1, 0x0, 0, 0)
1080#define _MX53_PAD_SD2_DATA3__KPP_COL_6 IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, 0)
1081#define _MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, 0)
1082#define _MX53_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, 0)
1083#define _MX53_PAD_SD2_DATA3__SJC_DONE IOMUX_PAD(0x690, 0x304, 7, 0x0, 0, 0)
1084#define _MX53_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x694, 0x308, 0, 0x0, 0, 0)
1085#define _MX53_PAD_SD2_DATA2__GPIO1_13 IOMUX_PAD(0x694, 0x308, 1, 0x0, 0, 0)
1086#define _MX53_PAD_SD2_DATA2__KPP_ROW_6 IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, 0)
1087#define _MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, 0)
1088#define _MX53_PAD_SD2_DATA2__CSPI_SS1 IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, 0)
1089#define _MX53_PAD_SD2_DATA2__SJC_FAIL IOMUX_PAD(0x694, 0x308, 7, 0x0, 0, 0)
1090#define _MX53_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x698, 0x30C, 0, 0x0, 0, 0)
1091#define _MX53_PAD_SD2_DATA1__GPIO1_14 IOMUX_PAD(0x698, 0x30C, 1, 0x0, 0, 0)
1092#define _MX53_PAD_SD2_DATA1__KPP_COL_7 IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, 0)
1093#define _MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, 0)
1094#define _MX53_PAD_SD2_DATA1__CSPI_SS0 IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, 0)
1095#define _MX53_PAD_SD2_DATA1__RTIC_SEC_VIO IOMUX_PAD(0x698, 0x30C, 7, 0x0, 0, 0)
1096#define _MX53_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x69C, 0x310, 0, 0x0, 0, 0)
1097#define _MX53_PAD_SD2_DATA0__GPIO1_15 IOMUX_PAD(0x69C, 0x310, 1, 0x0, 0, 0)
1098#define _MX53_PAD_SD2_DATA0__KPP_ROW_7 IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, 0)
1099#define _MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, 0)
1100#define _MX53_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, 0)
1101#define _MX53_PAD_SD2_DATA0__RTIC_DONE_INT IOMUX_PAD(0x69C, 0x310, 7, 0x0, 0, 0)
1102#define _MX53_PAD_GPIO_0__CCM_CLKO IOMUX_PAD(0x6A4, 0x314, 0, 0x0, 0, 0)
1103#define _MX53_PAD_GPIO_0__GPIO1_0 IOMUX_PAD(0x6A4, 0x314, 1, 0x0, 0, 0)
1104#define _MX53_PAD_GPIO_0__KPP_COL_5 IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, 0)
1105#define _MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK IOMUX_PAD(0x6A4, 0x314, 3, 0x0, 0, 0)
1106#define _MX53_PAD_GPIO_0__EPIT1_EPITO IOMUX_PAD(0x6A4, 0x314, 4, 0x0, 0, 0)
1107#define _MX53_PAD_GPIO_0__SRTC_ALARM_DEB IOMUX_PAD(0x6A4, 0x314, 5, 0x0, 0, 0)
1108#define _MX53_PAD_GPIO_0__USBOH3_USBH1_PWR IOMUX_PAD(0x6A4, 0x314, 6, 0x0, 0, 0)
1109#define _MX53_PAD_GPIO_0__CSU_TD IOMUX_PAD(0x6A4, 0x314, 7, 0x0, 0, 0)
1110#define _MX53_PAD_GPIO_1__ESAI1_SCKR IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, 0)
1111#define _MX53_PAD_GPIO_1__GPIO1_1 IOMUX_PAD(0x6A8, 0x318, 1, 0x0, 0, 0)
1112#define _MX53_PAD_GPIO_1__KPP_ROW_5 IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, 0)
1113#define _MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK IOMUX_PAD(0x6A8, 0x318, 3, 0x0, 0, 0)
1114#define _MX53_PAD_GPIO_1__PWM2_PWMO IOMUX_PAD(0x6A8, 0x318, 4, 0x0, 0, 0)
1115#define _MX53_PAD_GPIO_1__WDOG2_WDOG_B IOMUX_PAD(0x6A8, 0x318, 5, 0x0, 0, 0)
1116#define _MX53_PAD_GPIO_1__ESDHC1_CD IOMUX_PAD(0x6A8, 0x318, 6, 0x0, 0, 0)
1117#define _MX53_PAD_GPIO_1__SRC_TESTER_ACK IOMUX_PAD(0x6A8, 0x318, 7, 0x0, 0, 0)
1118#define _MX53_PAD_GPIO_9__ESAI1_FSR IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, 0)
1119#define _MX53_PAD_GPIO_9__GPIO1_9 IOMUX_PAD(0x6AC, 0x31C, 1, 0x0, 0, 0)
1120#define _MX53_PAD_GPIO_9__KPP_COL_6 IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, 0)
1121#define _MX53_PAD_GPIO_9__CCM_REF_EN_B IOMUX_PAD(0x6AC, 0x31C, 3, 0x0, 0, 0)
1122#define _MX53_PAD_GPIO_9__PWM1_PWMO IOMUX_PAD(0x6AC, 0x31C, 4, 0x0, 0, 0)
1123#define _MX53_PAD_GPIO_9__WDOG1_WDOG_B IOMUX_PAD(0x6AC, 0x31C, 5, 0x0, 0, 0)
1124#define _MX53_PAD_GPIO_9__ESDHC1_WP IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, 0)
1125#define _MX53_PAD_GPIO_9__SCC_FAIL_STATE IOMUX_PAD(0x6AC, 0x31C, 7, 0x0, 0, 0)
1126#define _MX53_PAD_GPIO_3__ESAI1_HCKR IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, 0)
1127#define _MX53_PAD_GPIO_3__GPIO1_3 IOMUX_PAD(0x6B0, 0x320, 1, 0x0, 0, 0)
1128#define _MX53_PAD_GPIO_3__I2C3_SCL IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, 0)
1129#define _MX53_PAD_GPIO_3__DPLLIP1_TOG_EN IOMUX_PAD(0x6B0, 0x320, 3, 0x0, 0, 0)
1130#define _MX53_PAD_GPIO_3__CCM_CLKO2 IOMUX_PAD(0x6B0, 0x320, 4, 0x0, 0, 0)
1131#define _MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 IOMUX_PAD(0x6B0, 0x320, 5, 0x0, 0, 0)
1132#define _MX53_PAD_GPIO_3__USBOH3_USBH1_OC IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, 0)
1133#define _MX53_PAD_GPIO_3__MLB_MLBCLK IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, 0)
1134#define _MX53_PAD_GPIO_6__ESAI1_SCKT IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, 0)
1135#define _MX53_PAD_GPIO_6__GPIO1_6 IOMUX_PAD(0x6B4, 0x324, 1, 0x0, 0, 0)
1136#define _MX53_PAD_GPIO_6__I2C3_SDA IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, 0)
1137#define _MX53_PAD_GPIO_6__CCM_CCM_OUT_0 IOMUX_PAD(0x6B4, 0x324, 3, 0x0, 0, 0)
1138#define _MX53_PAD_GPIO_6__CSU_CSU_INT_DEB IOMUX_PAD(0x6B4, 0x324, 4, 0x0, 0, 0)
1139#define _MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 IOMUX_PAD(0x6B4, 0x324, 5, 0x0, 0, 0)
1140#define _MX53_PAD_GPIO_6__ESDHC2_LCTL IOMUX_PAD(0x6B4, 0x324, 6, 0x0, 0, 0)
1141#define _MX53_PAD_GPIO_6__MLB_MLBSIG IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, 0)
1142#define _MX53_PAD_GPIO_2__ESAI1_FST IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, 0)
1143#define _MX53_PAD_GPIO_2__GPIO1_2 IOMUX_PAD(0x6B8, 0x328, 1, 0x0, 0, 0)
1144#define _MX53_PAD_GPIO_2__KPP_ROW_6 IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, 0)
1145#define _MX53_PAD_GPIO_2__CCM_CCM_OUT_1 IOMUX_PAD(0x6B8, 0x328, 3, 0x0, 0, 0)
1146#define _MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 IOMUX_PAD(0x6B8, 0x328, 4, 0x0, 0, 0)
1147#define _MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 IOMUX_PAD(0x6B8, 0x328, 5, 0x0, 0, 0)
1148#define _MX53_PAD_GPIO_2__ESDHC2_WP IOMUX_PAD(0x6B8, 0x328, 6, 0x0, 0, 0)
1149#define _MX53_PAD_GPIO_2__MLB_MLBDAT IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, 0)
1150#define _MX53_PAD_GPIO_4__ESAI1_HCKT IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, 0)
1151#define _MX53_PAD_GPIO_4__GPIO1_4 IOMUX_PAD(0x6BC, 0x32C, 1, 0x0, 0, 0)
1152#define _MX53_PAD_GPIO_4__KPP_COL_7 IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, 0)
1153#define _MX53_PAD_GPIO_4__CCM_CCM_OUT_2 IOMUX_PAD(0x6BC, 0x32C, 3, 0x0, 0, 0)
1154#define _MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 IOMUX_PAD(0x6BC, 0x32C, 4, 0x0, 0, 0)
1155#define _MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 IOMUX_PAD(0x6BC, 0x32C, 5, 0x0, 0, 0)
1156#define _MX53_PAD_GPIO_4__ESDHC2_CD IOMUX_PAD(0x6BC, 0x32C, 6, 0x0, 0, 0)
1157#define _MX53_PAD_GPIO_4__SCC_SEC_STATE IOMUX_PAD(0x6BC, 0x32C, 7, 0x0, 0, 0)
1158#define _MX53_PAD_GPIO_5__ESAI1_TX2_RX3 IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, 0)
1159#define _MX53_PAD_GPIO_5__GPIO1_5 IOMUX_PAD(0x6C0, 0x330, 1, 0x0, 0, 0)
1160#define _MX53_PAD_GPIO_5__KPP_ROW_7 IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, 0)
1161#define _MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0)
1162#define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0)
1163#define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0)
1164#define _MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6, 0x824, 2, 0)
1165#define _MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0)
1166#define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0)
1167#define _MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0)
1168#define _MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0)
1169#define _MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0)
1170#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x880, 4, 0)
1171#define _MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0)
1172#define _MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0)
1173#define _MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0)
1174#define _MX53_PAD_GPIO_8__ESAI1_TX5_RX0 IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, 0)
1175#define _MX53_PAD_GPIO_8__GPIO1_8 IOMUX_PAD(0x6C8, 0x338, 1, 0x0, 0, 0)
1176#define _MX53_PAD_GPIO_8__EPIT2_EPITO IOMUX_PAD(0x6C8, 0x338, 2, 0x0, 0, 0)
1177#define _MX53_PAD_GPIO_8__CAN1_RXCAN IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, 0)
1178#define _MX53_PAD_GPIO_8__UART2_RXD_MUX IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, 0)
1179#define _MX53_PAD_GPIO_8__FIRI_TXD IOMUX_PAD(0x6C8, 0x338, 5, 0x0, 0, 0)
1180#define _MX53_PAD_GPIO_8__SPDIF_SRCLK IOMUX_PAD(0x6C8, 0x338, 6, 0x0, 0, 0)
1181#define _MX53_PAD_GPIO_8__CCM_PLL3_BYP IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, 0)
1182#define _MX53_PAD_GPIO_16__ESAI1_TX3_RX2 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, 0)
1183#define _MX53_PAD_GPIO_16__GPIO7_11 IOMUX_PAD(0x6CC, 0x33C, 1, 0x0, 0, 0)
1184#define _MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT IOMUX_PAD(0x6CC, 0x33C, 2, 0x0, 0, 0)
1185#define _MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 IOMUX_PAD(0x6CC, 0x33C, 4, 0x0, 0, 0)
1186#define _MX53_PAD_GPIO_16__SPDIF_IN1 IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, 0)
1187#define _MX53_PAD_GPIO_16__I2C3_SDA IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, 0)
1188#define _MX53_PAD_GPIO_16__SJC_DE_B IOMUX_PAD(0x6CC, 0x33C, 7, 0x0, 0, 0)
1189#define _MX53_PAD_GPIO_17__ESAI1_TX0 IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, 0)
1190#define _MX53_PAD_GPIO_17__GPIO7_12 IOMUX_PAD(0x6D0, 0x340, 1, 0x0, 0, 0)
1191#define _MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, 0)
1192#define _MX53_PAD_GPIO_17__GPC_PMIC_RDY IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, 0)
1193#define _MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG IOMUX_PAD(0x6D0, 0x340, 4, 0x0, 0, 0)
1194#define _MX53_PAD_GPIO_17__SPDIF_OUT1 IOMUX_PAD(0x6D0, 0x340, 5, 0x0, 0, 0)
1195#define _MX53_PAD_GPIO_17__IPU_SNOOP2 IOMUX_PAD(0x6D0, 0x340, 6, 0x0, 0, 0)
1196#define _MX53_PAD_GPIO_17__SJC_JTAG_ACT IOMUX_PAD(0x6D0, 0x340, 7, 0x0, 0, 0)
1197#define _MX53_PAD_GPIO_18__ESAI1_TX1 IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, 0)
1198#define _MX53_PAD_GPIO_18__GPIO7_13 IOMUX_PAD(0x6D4, 0x344, 1, 0x0, 0, 0)
1199#define _MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, 0)
1200#define _MX53_PAD_GPIO_18__OWIRE_LINE IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, 0)
1201#define _MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG IOMUX_PAD(0x6D4, 0x344, 4, 0x0, 0, 0)
1202#define _MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, 0)
1203#define _MX53_PAD_GPIO_18__ESDHC1_LCTL IOMUX_PAD(0x6D4, 0x344, 6, 0x0, 0, 0)
1204#define _MX53_PAD_GPIO_18__SRC_SYSTEM_RST IOMUX_PAD(0x6D4, 0x344, 7, 0x0, 0, 0)
63 1205
64#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1206#define MX53_PAD_GPIO_19__KPP_COL_5 (_MX53_PAD_GPIO_19__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
65#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1207#define MX53_PAD_GPIO_19__GPIO4_5 (_MX53_PAD_GPIO_19__GPIO4_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
66#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1208#define MX53_PAD_GPIO_19__CCM_CLKO (_MX53_PAD_GPIO_19__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
67#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1209#define MX53_PAD_GPIO_19__SPDIF_OUT1 (_MX53_PAD_GPIO_19__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
68#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1210#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 (_MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 | MUX_PAD_CTRL(NO_PAD_CTRL))
69#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1211#define MX53_PAD_GPIO_19__ECSPI1_RDY (_MX53_PAD_GPIO_19__ECSPI1_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
70#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1212#define MX53_PAD_GPIO_19__FEC_TDATA_3 (_MX53_PAD_GPIO_19__FEC_TDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
71#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1213#define MX53_PAD_GPIO_19__SRC_INT_BOOT (_MX53_PAD_GPIO_19__SRC_INT_BOOT | MUX_PAD_CTRL(NO_PAD_CTRL))
72#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1214#define MX53_PAD_KEY_COL0__KPP_COL_0 (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
73#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1215#define MX53_PAD_KEY_COL0__GPIO4_6 (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
74#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1216#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
75#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1217#define MX53_PAD_KEY_COL0__UART4_TXD_MUX (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
76#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1218#define MX53_PAD_KEY_COL0__ECSPI1_SCLK (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
77#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1219#define MX53_PAD_KEY_COL0__FEC_RDATA_3 (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
78#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1220#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
79#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1221#define MX53_PAD_KEY_ROW0__KPP_ROW_0 (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
80#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1222#define MX53_PAD_KEY_ROW0__GPIO4_7 (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
81#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1223#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
82#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1224#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
83#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1225#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
84#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1226#define MX53_PAD_KEY_ROW0__FEC_TX_ER (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
85#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1227#define MX53_PAD_KEY_COL1__KPP_COL_1 (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
86#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1228#define MX53_PAD_KEY_COL1__GPIO4_8 (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
87#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1229#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
88#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1230#define MX53_PAD_KEY_COL1__UART5_TXD_MUX (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
89#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1231#define MX53_PAD_KEY_COL1__ECSPI1_MISO (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
90#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1232#define MX53_PAD_KEY_COL1__FEC_RX_CLK (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
91#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1233#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
92#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1234#define MX53_PAD_KEY_ROW1__KPP_ROW_1 (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
93#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1235#define MX53_PAD_KEY_ROW1__GPIO4_9 (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
94#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1236#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
95#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1237#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
96#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1238#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
97#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1239#define MX53_PAD_KEY_ROW1__FEC_COL (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
98#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1240#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
99#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1241#define MX53_PAD_KEY_COL2__KPP_COL_2 (_MX53_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
100#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1242#define MX53_PAD_KEY_COL2__GPIO4_10 (_MX53_PAD_KEY_COL2__GPIO4_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
101#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1243#define MX53_PAD_KEY_COL2__CAN1_TXCAN (_MX53_PAD_KEY_COL2__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
102#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1244#define MX53_PAD_KEY_COL2__FEC_MDIO (_MX53_PAD_KEY_COL2__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
103#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1245#define MX53_PAD_KEY_COL2__ECSPI1_SS1 (_MX53_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
104#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1246#define MX53_PAD_KEY_COL2__FEC_RDATA_2 (_MX53_PAD_KEY_COL2__FEC_RDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
105#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1247#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE (_MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
106#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1248#define MX53_PAD_KEY_ROW2__KPP_ROW_2 (_MX53_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
107#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1249#define MX53_PAD_KEY_ROW2__GPIO4_11 (_MX53_PAD_KEY_ROW2__GPIO4_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
108#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1250#define MX53_PAD_KEY_ROW2__CAN1_RXCAN (_MX53_PAD_KEY_ROW2__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
109#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1251#define MX53_PAD_KEY_ROW2__FEC_MDC (_MX53_PAD_KEY_ROW2__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
110#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1252#define MX53_PAD_KEY_ROW2__ECSPI1_SS2 (_MX53_PAD_KEY_ROW2__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
111#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1253#define MX53_PAD_KEY_ROW2__FEC_TDATA_2 (_MX53_PAD_KEY_ROW2__FEC_TDATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
112#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1254#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR (_MX53_PAD_KEY_ROW2__USBPHY1_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
113#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1255#define MX53_PAD_KEY_COL3__KPP_COL_3 (_MX53_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
114#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1256#define MX53_PAD_KEY_COL3__GPIO4_12 (_MX53_PAD_KEY_COL3__GPIO4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
115#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1257#define MX53_PAD_KEY_COL3__USBOH3_H2_DP (_MX53_PAD_KEY_COL3__USBOH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
116#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1258#define MX53_PAD_KEY_COL3__SPDIF_IN1 (_MX53_PAD_KEY_COL3__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
117#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1259#define MX53_PAD_KEY_COL3__I2C2_SCL (_MX53_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
118#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1260#define MX53_PAD_KEY_COL3__ECSPI1_SS3 (_MX53_PAD_KEY_COL3__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
119#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1261#define MX53_PAD_KEY_COL3__FEC_CRS (_MX53_PAD_KEY_COL3__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
120#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1262#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK (_MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
121#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1263#define MX53_PAD_KEY_ROW3__KPP_ROW_3 (_MX53_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
122#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1264#define MX53_PAD_KEY_ROW3__GPIO4_13 (_MX53_PAD_KEY_ROW3__GPIO4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
123#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1265#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM (_MX53_PAD_KEY_ROW3__USBOH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
124#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1266#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK (_MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
125#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1267#define MX53_PAD_KEY_ROW3__I2C2_SDA (_MX53_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
126#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1268#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT (_MX53_PAD_KEY_ROW3__OSC32K_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
127#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1269#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP (_MX53_PAD_KEY_ROW3__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
128#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1270#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 (_MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
129#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1271#define MX53_PAD_KEY_COL4__KPP_COL_4 (_MX53_PAD_KEY_COL4__KPP_COL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
130#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1272#define MX53_PAD_KEY_COL4__GPIO4_14 (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
131#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1273#define MX53_PAD_KEY_COL4__CAN2_TXCAN (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
132#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1274#define MX53_PAD_KEY_COL4__IPU_SISG_4 (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
133#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1275#define MX53_PAD_KEY_COL4__UART5_RTS (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
134#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1276#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
135#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1277#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
136#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1278#define MX53_PAD_KEY_ROW4__KPP_ROW_4 (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
137#define MX53_PAD_EIM_D16__CSPI1_SCLK IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT4, 0x79c, 3, NO_PAD_CTRL) 1279#define MX53_PAD_KEY_ROW4__GPIO4_15 (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
138#define MX53_PAD_EIM_D17__CSPI1_MISO IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT4, 0x7a0, 3, NO_PAD_CTRL) 1280#define MX53_PAD_KEY_ROW4__CAN2_RXCAN (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
139#define MX53_PAD_EIM_D18__CSPI1_MOSI IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT4, 0x7a4, 3, NO_PAD_CTRL) 1281#define MX53_PAD_KEY_ROW4__IPU_SISG_5 (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
140#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1282#define MX53_PAD_KEY_ROW4__UART5_CTS (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
141#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1283#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
142#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1284#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
143#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1285#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
144#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1286#define MX53_PAD_DI0_DISP_CLK__GPIO4_16 (_MX53_PAD_DI0_DISP_CLK__GPIO4_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
145#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1287#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR (_MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
146#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1288#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 (_MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
147#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1289#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 (_MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
148#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1290#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID (_MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
149#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1291#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 (_MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
150#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1292#define MX53_PAD_DI0_PIN15__GPIO4_17 (_MX53_PAD_DI0_PIN15__GPIO4_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
151#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1293#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC (_MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
152#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1294#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 (_MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
153#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1295#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 (_MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
154#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1296#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID (_MX53_PAD_DI0_PIN15__USBPHY1_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
155#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1297#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 (_MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
156#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1298#define MX53_PAD_DI0_PIN2__GPIO4_18 (_MX53_PAD_DI0_PIN2__GPIO4_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
157#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1299#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD (_MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
158#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1300#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 (_MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
159#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1301#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 (_MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
160#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1302#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION (_MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
161#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1303#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 (_MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
162#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1304#define MX53_PAD_DI0_PIN3__GPIO4_19 (_MX53_PAD_DI0_PIN3__GPIO4_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
163#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1305#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS (_MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
164#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1306#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 (_MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
165#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1307#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 (_MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
166#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1308#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG (_MX53_PAD_DI0_PIN3__USBPHY1_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
167#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1309#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 (_MX53_PAD_DI0_PIN4__IPU_DI0_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
168#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1310#define MX53_PAD_DI0_PIN4__GPIO4_20 (_MX53_PAD_DI0_PIN4__GPIO4_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
169#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1311#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD (_MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
170#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1312#define MX53_PAD_DI0_PIN4__ESDHC1_WP (_MX53_PAD_DI0_PIN4__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
171#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1313#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD (_MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD | MUX_PAD_CTRL(NO_PAD_CTRL))
172#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1314#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 (_MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
173#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1315#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT (_MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
174#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1316#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 (_MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
175#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1317#define MX53_PAD_DISP0_DAT0__GPIO4_21 (_MX53_PAD_DISP0_DAT0__GPIO4_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
176#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1318#define MX53_PAD_DISP0_DAT0__CSPI_SCLK (_MX53_PAD_DISP0_DAT0__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
177#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1319#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 (_MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
178#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1320#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN (_MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN | MUX_PAD_CTRL(NO_PAD_CTRL))
179#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1321#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 (_MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
180#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1322#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY (_MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
181#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1323#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 (_MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
182#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1324#define MX53_PAD_DISP0_DAT1__GPIO4_22 (_MX53_PAD_DISP0_DAT1__GPIO4_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
183#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1325#define MX53_PAD_DISP0_DAT1__CSPI_MOSI (_MX53_PAD_DISP0_DAT1__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
184#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1326#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 (_MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
185#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1327#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL (_MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
186#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1328#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 (_MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
187#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1329#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID (_MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
188#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1330#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 (_MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
189#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1331#define MX53_PAD_DISP0_DAT2__GPIO4_23 (_MX53_PAD_DISP0_DAT2__GPIO4_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
190#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1332#define MX53_PAD_DISP0_DAT2__CSPI_MISO (_MX53_PAD_DISP0_DAT2__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
191#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1333#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 (_MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
192#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1334#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE (_MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE | MUX_PAD_CTRL(NO_PAD_CTRL))
193#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1335#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 (_MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
194#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1336#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE (_MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE | MUX_PAD_CTRL(NO_PAD_CTRL))
195#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1337#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 (_MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
196#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1338#define MX53_PAD_DISP0_DAT3__GPIO4_24 (_MX53_PAD_DISP0_DAT3__GPIO4_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
197#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1339#define MX53_PAD_DISP0_DAT3__CSPI_SS0 (_MX53_PAD_DISP0_DAT3__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
198#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1340#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 (_MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
199#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1341#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR (_MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
200#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1342#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 (_MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
201#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1343#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR (_MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR | MUX_PAD_CTRL(NO_PAD_CTRL))
202#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1344#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 (_MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
203#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1345#define MX53_PAD_DISP0_DAT4__GPIO4_25 (_MX53_PAD_DISP0_DAT4__GPIO4_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
204#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1346#define MX53_PAD_DISP0_DAT4__CSPI_SS1 (_MX53_PAD_DISP0_DAT4__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
205#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1347#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 (_MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
206#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1348#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB (_MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB | MUX_PAD_CTRL(NO_PAD_CTRL))
207#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1349#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 (_MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
208#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1350#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK (_MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
209#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1351#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 (_MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
210#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1352#define MX53_PAD_DISP0_DAT5__GPIO4_26 (_MX53_PAD_DISP0_DAT5__GPIO4_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
211#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1353#define MX53_PAD_DISP0_DAT5__CSPI_SS2 (_MX53_PAD_DISP0_DAT5__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
212#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1354#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 (_MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
213#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1355#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS (_MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS | MUX_PAD_CTRL(NO_PAD_CTRL))
214#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1356#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 (_MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
215#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1357#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 (_MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
216#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1358#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 (_MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
217#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1359#define MX53_PAD_DISP0_DAT6__GPIO4_27 (_MX53_PAD_DISP0_DAT6__GPIO4_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
218#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1360#define MX53_PAD_DISP0_DAT6__CSPI_SS3 (_MX53_PAD_DISP0_DAT6__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
219#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1361#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 (_MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
220#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1362#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE (_MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE | MUX_PAD_CTRL(NO_PAD_CTRL))
221#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1363#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 (_MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
222#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1364#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 (_MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
223#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1365#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 (_MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
224#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1366#define MX53_PAD_DISP0_DAT7__GPIO4_28 (_MX53_PAD_DISP0_DAT7__GPIO4_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
225#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1367#define MX53_PAD_DISP0_DAT7__CSPI_RDY (_MX53_PAD_DISP0_DAT7__CSPI_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
226#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1368#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 (_MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
227#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1369#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 (_MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
228#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1370#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 (_MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
229#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1371#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID (_MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
230#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1372#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 (_MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
231#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1373#define MX53_PAD_DISP0_DAT8__GPIO4_29 (_MX53_PAD_DISP0_DAT8__GPIO4_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
232#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1374#define MX53_PAD_DISP0_DAT8__PWM1_PWMO (_MX53_PAD_DISP0_DAT8__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
233#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1375#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B (_MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
234#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1376#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 (_MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
235#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1377#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 (_MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
236#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1378#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID (_MX53_PAD_DISP0_DAT8__USBPHY2_AVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
237#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1379#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 (_MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
238#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1380#define MX53_PAD_DISP0_DAT9__GPIO4_30 (_MX53_PAD_DISP0_DAT9__GPIO4_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
239#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1381#define MX53_PAD_DISP0_DAT9__PWM2_PWMO (_MX53_PAD_DISP0_DAT9__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
240#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1382#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B (_MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
241#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1383#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 (_MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
242#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1384#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 (_MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
243#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1385#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 (_MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
244#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1386#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 (_MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
245#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1387#define MX53_PAD_DISP0_DAT10__GPIO4_31 (_MX53_PAD_DISP0_DAT10__GPIO4_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
246#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1388#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP (_MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
247#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1389#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 (_MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
248#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1390#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 (_MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
249#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1391#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 (_MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
250#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1392#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 (_MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
251#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1393#define MX53_PAD_DISP0_DAT11__GPIO5_5 (_MX53_PAD_DISP0_DAT11__GPIO5_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
252#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1394#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT (_MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
253#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1395#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 (_MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
254#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1396#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 (_MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
255#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1397#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 (_MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
256#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1398#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 (_MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
257#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1399#define MX53_PAD_DISP0_DAT12__GPIO5_6 (_MX53_PAD_DISP0_DAT12__GPIO5_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
258#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1400#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK (_MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
259#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1401#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 (_MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
260#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1402#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 (_MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
261#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1403#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 (_MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
262#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1404#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 (_MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
263#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1405#define MX53_PAD_DISP0_DAT13__GPIO5_7 (_MX53_PAD_DISP0_DAT13__GPIO5_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
264#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1406#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS (_MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
265#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1407#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 (_MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
266#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1408#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 (_MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
267#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1409#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 (_MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
268#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1410#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 (_MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
269#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1411#define MX53_PAD_DISP0_DAT14__GPIO5_8 (_MX53_PAD_DISP0_DAT14__GPIO5_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
270#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1412#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC (_MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
271#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1413#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 (_MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
272#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1414#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 (_MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
273#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1415#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 (_MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
274#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1416#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 (_MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
275#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1417#define MX53_PAD_DISP0_DAT15__GPIO5_9 (_MX53_PAD_DISP0_DAT15__GPIO5_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
276#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1418#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
277#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1419#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1 (_MX53_PAD_DISP0_DAT15__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
278#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1420#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 (_MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
279#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1421#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 (_MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
280#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1422#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 (_MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
281#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1423#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 (_MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
282#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1424#define MX53_PAD_DISP0_DAT16__GPIO5_10 (_MX53_PAD_DISP0_DAT16__GPIO5_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
283#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1425#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI (_MX53_PAD_DISP0_DAT16__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
284#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1426#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC (_MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
285#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1427#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 (_MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
286#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1428#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 (_MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
287#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1429#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 (_MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
288#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1430#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 (_MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
289#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1431#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 (_MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
290#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1432#define MX53_PAD_DISP0_DAT17__GPIO5_11 (_MX53_PAD_DISP0_DAT17__GPIO5_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
291#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1433#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO (_MX53_PAD_DISP0_DAT17__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
292#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1434#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD (_MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
293#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1435#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 (_MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
294#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1436#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 (_MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
295#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1437#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 (_MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
296#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1438#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 (_MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
297#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1439#define MX53_PAD_DISP0_DAT18__GPIO5_12 (_MX53_PAD_DISP0_DAT18__GPIO5_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
298#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1440#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0 (_MX53_PAD_DISP0_DAT18__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
299#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1441#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
300#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1442#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS (_MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
301#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1443#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 (_MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
302#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1444#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 (_MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
303#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1445#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 (_MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
304#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL) 1446#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 (_MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
305#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1447#define MX53_PAD_DISP0_DAT19__GPIO5_13 (_MX53_PAD_DISP0_DAT19__GPIO5_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
306#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1448#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK (_MX53_PAD_DISP0_DAT19__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
307#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1449#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
308#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1450#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC (_MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
309#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1451#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 (_MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
310#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1452#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 (_MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
311#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1453#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 (_MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
312#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1454#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 (_MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
313#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1455#define MX53_PAD_DISP0_DAT20__GPIO5_14 (_MX53_PAD_DISP0_DAT20__GPIO5_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
314#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1456#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK (_MX53_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
315#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1457#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC (_MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
316#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1458#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 (_MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
317#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1459#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 (_MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
318#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1460#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI (_MX53_PAD_DISP0_DAT20__SATA_PHY_TDI | MUX_PAD_CTRL(NO_PAD_CTRL))
319#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1461#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 (_MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
320#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1462#define MX53_PAD_DISP0_DAT21__GPIO5_15 (_MX53_PAD_DISP0_DAT21__GPIO5_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
321#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1463#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI (_MX53_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
322#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1464#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD (_MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
323#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL) 1465#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 (_MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1466#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 (_MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1467#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO (_MX53_PAD_DISP0_DAT21__SATA_PHY_TDO | MUX_PAD_CTRL(NO_PAD_CTRL))
1468#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 (_MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1469#define MX53_PAD_DISP0_DAT22__GPIO5_16 (_MX53_PAD_DISP0_DAT22__GPIO5_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1470#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO (_MX53_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1471#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS (_MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1472#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 (_MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1473#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 (_MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
1474#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK (_MX53_PAD_DISP0_DAT22__SATA_PHY_TCK | MUX_PAD_CTRL(NO_PAD_CTRL))
1475#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 (_MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1476#define MX53_PAD_DISP0_DAT23__GPIO5_17 (_MX53_PAD_DISP0_DAT23__GPIO5_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1477#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0 (_MX53_PAD_DISP0_DAT23__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1478#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD (_MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1479#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 (_MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1480#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 (_MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1481#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS (_MX53_PAD_DISP0_DAT23__SATA_PHY_TMS | MUX_PAD_CTRL(NO_PAD_CTRL))
1482#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK (_MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1483#define MX53_PAD_CSI0_PIXCLK__GPIO5_18 (_MX53_PAD_CSI0_PIXCLK__GPIO5_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1484#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 (_MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1485#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 (_MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1486#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC (_MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1487#define MX53_PAD_CSI0_MCLK__GPIO5_19 (_MX53_PAD_CSI0_MCLK__GPIO5_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1488#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK (_MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1489#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 (_MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1490#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 (_MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1491#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL (_MX53_PAD_CSI0_MCLK__TPIU_TRCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
1492#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN (_MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1493#define MX53_PAD_CSI0_DATA_EN__GPIO5_20 (_MX53_PAD_CSI0_DATA_EN__GPIO5_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1494#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 (_MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1495#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 (_MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1496#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK (_MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1497#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC (_MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1498#define MX53_PAD_CSI0_VSYNC__GPIO5_21 (_MX53_PAD_CSI0_VSYNC__GPIO5_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1499#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 (_MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1500#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 (_MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32 | MUX_PAD_CTRL(NO_PAD_CTRL))
1501#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 (_MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1502#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 (_MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1503#define MX53_PAD_CSI0_DAT4__GPIO5_22 (_MX53_PAD_CSI0_DAT4__GPIO5_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1504#define MX53_PAD_CSI0_DAT4__KPP_COL_5 (_MX53_PAD_CSI0_DAT4__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1505#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK (_MX53_PAD_CSI0_DAT4__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1506#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP (_MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
1507#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC (_MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1508#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 (_MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33 | MUX_PAD_CTRL(NO_PAD_CTRL))
1509#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 (_MX53_PAD_CSI0_DAT4__TPIU_TRACE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1510#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 (_MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1511#define MX53_PAD_CSI0_DAT5__GPIO5_23 (_MX53_PAD_CSI0_DAT5__GPIO5_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1512#define MX53_PAD_CSI0_DAT5__KPP_ROW_5 (_MX53_PAD_CSI0_DAT5__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1513#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI (_MX53_PAD_CSI0_DAT5__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1514#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT (_MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
1515#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD (_MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1516#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 (_MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34 | MUX_PAD_CTRL(NO_PAD_CTRL))
1517#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 (_MX53_PAD_CSI0_DAT5__TPIU_TRACE_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1518#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 (_MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1519#define MX53_PAD_CSI0_DAT6__GPIO5_24 (_MX53_PAD_CSI0_DAT6__GPIO5_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1520#define MX53_PAD_CSI0_DAT6__KPP_COL_6 (_MX53_PAD_CSI0_DAT6__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1521#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO (_MX53_PAD_CSI0_DAT6__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1522#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK (_MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1523#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS (_MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1524#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 (_MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35 | MUX_PAD_CTRL(NO_PAD_CTRL))
1525#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 (_MX53_PAD_CSI0_DAT6__TPIU_TRACE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1526#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 (_MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1527#define MX53_PAD_CSI0_DAT7__GPIO5_25 (_MX53_PAD_CSI0_DAT7__GPIO5_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
1528#define MX53_PAD_CSI0_DAT7__KPP_ROW_6 (_MX53_PAD_CSI0_DAT7__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1529#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0 (_MX53_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1530#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR (_MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
1531#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD (_MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1532#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 (_MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36 | MUX_PAD_CTRL(NO_PAD_CTRL))
1533#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 (_MX53_PAD_CSI0_DAT7__TPIU_TRACE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1534#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 (_MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1535#define MX53_PAD_CSI0_DAT8__GPIO5_26 (_MX53_PAD_CSI0_DAT8__GPIO5_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1536#define MX53_PAD_CSI0_DAT8__KPP_COL_7 (_MX53_PAD_CSI0_DAT8__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1537#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK (_MX53_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1538#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC (_MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1539#define MX53_PAD_CSI0_DAT8__I2C1_SDA (_MX53_PAD_CSI0_DAT8__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1540#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 (_MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37 | MUX_PAD_CTRL(NO_PAD_CTRL))
1541#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 (_MX53_PAD_CSI0_DAT8__TPIU_TRACE_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1542#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 (_MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1543#define MX53_PAD_CSI0_DAT9__GPIO5_27 (_MX53_PAD_CSI0_DAT9__GPIO5_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
1544#define MX53_PAD_CSI0_DAT9__KPP_ROW_7 (_MX53_PAD_CSI0_DAT9__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1545#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI (_MX53_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1546#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR (_MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1547#define MX53_PAD_CSI0_DAT9__I2C1_SCL (_MX53_PAD_CSI0_DAT9__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1548#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 (_MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38 | MUX_PAD_CTRL(NO_PAD_CTRL))
1549#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 (_MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1550#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 (_MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1551#define MX53_PAD_CSI0_DAT10__GPIO5_28 (_MX53_PAD_CSI0_DAT10__GPIO5_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1552#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX (_MX53_PAD_CSI0_DAT10__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
1553#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO (_MX53_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1554#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC (_MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1555#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 (_MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1556#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 (_MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39 | MUX_PAD_CTRL(NO_PAD_CTRL))
1557#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 (_MX53_PAD_CSI0_DAT10__TPIU_TRACE_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1558#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 (_MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1559#define MX53_PAD_CSI0_DAT11__GPIO5_29 (_MX53_PAD_CSI0_DAT11__GPIO5_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1560#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX (_MX53_PAD_CSI0_DAT11__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
1561#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0 (_MX53_PAD_CSI0_DAT11__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1562#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS (_MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1563#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 (_MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1564#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 (_MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40 | MUX_PAD_CTRL(NO_PAD_CTRL))
1565#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1566#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1567#define MX53_PAD_CSI0_DAT12__GPIO5_30 (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1568#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1569#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1570#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1571#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
1572#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1573#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1574#define MX53_PAD_CSI0_DAT13__GPIO5_31 (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1575#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1576#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1577#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1578#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
1579#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1580#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1581#define MX53_PAD_CSI0_DAT14__GPIO6_0 (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1582#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1583#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1584#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1585#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
1586#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1587#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1588#define MX53_PAD_CSI0_DAT15__GPIO6_1 (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1589#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1590#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1591#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1592#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
1593#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1594#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1595#define MX53_PAD_CSI0_DAT16__GPIO6_2 (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1596#define MX53_PAD_CSI0_DAT16__UART4_RTS (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1597#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1598#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1599#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
1600#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1601#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1602#define MX53_PAD_CSI0_DAT17__GPIO6_3 (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1603#define MX53_PAD_CSI0_DAT17__UART4_CTS (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1604#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1605#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1606#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
1607#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1608#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1609#define MX53_PAD_CSI0_DAT18__GPIO6_4 (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1610#define MX53_PAD_CSI0_DAT18__UART5_RTS (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1611#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1612#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1613#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
1614#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1615#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1616#define MX53_PAD_CSI0_DAT19__GPIO6_5 (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1617#define MX53_PAD_CSI0_DAT19__UART5_CTS (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1618#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1619#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1620#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
1621#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK (_MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
1622#define MX53_PAD_EIM_A25__EMI_WEIM_A_25 (_MX53_PAD_EIM_A25__EMI_WEIM_A_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
1623#define MX53_PAD_EIM_A25__GPIO5_2 (_MX53_PAD_EIM_A25__GPIO5_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1624#define MX53_PAD_EIM_A25__ECSPI2_RDY (_MX53_PAD_EIM_A25__ECSPI2_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
1625#define MX53_PAD_EIM_A25__IPU_DI1_PIN12 (_MX53_PAD_EIM_A25__IPU_DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1626#define MX53_PAD_EIM_A25__CSPI_SS1 (_MX53_PAD_EIM_A25__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1627#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS (_MX53_PAD_EIM_A25__IPU_DI0_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1628#define MX53_PAD_EIM_A25__USBPHY1_BISTOK (_MX53_PAD_EIM_A25__USBPHY1_BISTOK | MUX_PAD_CTRL(NO_PAD_CTRL))
1629#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 (_MX53_PAD_EIM_EB2__EMI_WEIM_EB_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1630#define MX53_PAD_EIM_EB2__GPIO2_30 (_MX53_PAD_EIM_EB2__GPIO2_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1631#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1632#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS (_MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1633#define MX53_PAD_EIM_EB2__ECSPI1_SS0 (_MX53_PAD_EIM_EB2__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1634#define MX53_PAD_EIM_EB2__I2C2_SCL (_MX53_PAD_EIM_EB2__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1635#define MX53_PAD_EIM_D16__EMI_WEIM_D_16 (_MX53_PAD_EIM_D16__EMI_WEIM_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1636#define MX53_PAD_EIM_D16__GPIO3_16 (_MX53_PAD_EIM_D16__GPIO3_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1637#define MX53_PAD_EIM_D16__IPU_DI0_PIN5 (_MX53_PAD_EIM_D16__IPU_DI0_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1638#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK (_MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1639#define MX53_PAD_EIM_D16__ECSPI1_SCLK (_MX53_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1640#define MX53_PAD_EIM_D16__I2C2_SDA (_MX53_PAD_EIM_D16__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1641#define MX53_PAD_EIM_D17__EMI_WEIM_D_17 (_MX53_PAD_EIM_D17__EMI_WEIM_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1642#define MX53_PAD_EIM_D17__GPIO3_17 (_MX53_PAD_EIM_D17__GPIO3_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1643#define MX53_PAD_EIM_D17__IPU_DI0_PIN6 (_MX53_PAD_EIM_D17__IPU_DI0_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1644#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN (_MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
1645#define MX53_PAD_EIM_D17__ECSPI1_MISO (_MX53_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1646#define MX53_PAD_EIM_D17__I2C3_SCL (_MX53_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1647#define MX53_PAD_EIM_D18__EMI_WEIM_D_18 (_MX53_PAD_EIM_D18__EMI_WEIM_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1648#define MX53_PAD_EIM_D18__GPIO3_18 (_MX53_PAD_EIM_D18__GPIO3_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1649#define MX53_PAD_EIM_D18__IPU_DI0_PIN7 (_MX53_PAD_EIM_D18__IPU_DI0_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1650#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO (_MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1651#define MX53_PAD_EIM_D18__ECSPI1_MOSI (_MX53_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1652#define MX53_PAD_EIM_D18__I2C3_SDA (_MX53_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1653#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS (_MX53_PAD_EIM_D18__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1654#define MX53_PAD_EIM_D19__EMI_WEIM_D_19 (_MX53_PAD_EIM_D19__EMI_WEIM_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1655#define MX53_PAD_EIM_D19__GPIO3_19 (_MX53_PAD_EIM_D19__GPIO3_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1656#define MX53_PAD_EIM_D19__IPU_DI0_PIN8 (_MX53_PAD_EIM_D19__IPU_DI0_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1657#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
1658#define MX53_PAD_EIM_D19__ECSPI1_SS1 (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1659#define MX53_PAD_EIM_D19__EPIT1_EPITO (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
1660#define MX53_PAD_EIM_D19__UART1_CTS (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1661#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1662#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1663#define MX53_PAD_EIM_D20__GPIO3_20 (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1664#define MX53_PAD_EIM_D20__IPU_DI0_PIN16 (_MX53_PAD_EIM_D20__IPU_DI0_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1665#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1666#define MX53_PAD_EIM_D20__CSPI_SS0 (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1667#define MX53_PAD_EIM_D20__EPIT2_EPITO (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
1668#define MX53_PAD_EIM_D20__UART1_RTS (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1669#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1670#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1671#define MX53_PAD_EIM_D21__GPIO3_21 (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1672#define MX53_PAD_EIM_D21__IPU_DI0_PIN17 (_MX53_PAD_EIM_D21__IPU_DI0_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1673#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK (_MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1674#define MX53_PAD_EIM_D21__CSPI_SCLK (_MX53_PAD_EIM_D21__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1675#define MX53_PAD_EIM_D21__I2C1_SCL (_MX53_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
1676#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC (_MX53_PAD_EIM_D21__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1677#define MX53_PAD_EIM_D22__EMI_WEIM_D_22 (_MX53_PAD_EIM_D22__EMI_WEIM_D_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1678#define MX53_PAD_EIM_D22__GPIO3_22 (_MX53_PAD_EIM_D22__GPIO3_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1679#define MX53_PAD_EIM_D22__IPU_DI0_PIN1 (_MX53_PAD_EIM_D22__IPU_DI0_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1680#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN (_MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
1681#define MX53_PAD_EIM_D22__CSPI_MISO (_MX53_PAD_EIM_D22__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1682#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1683#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1684#define MX53_PAD_EIM_D23__GPIO3_23 (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1685#define MX53_PAD_EIM_D23__UART3_CTS (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1686#define MX53_PAD_EIM_D23__UART1_DCD (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL))
1687#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1688#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1689#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1690#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1691#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1692#define MX53_PAD_EIM_EB3__GPIO2_31 (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1693#define MX53_PAD_EIM_EB3__UART3_RTS (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1694#define MX53_PAD_EIM_EB3__UART1_RI (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL))
1695#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1696#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1697#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1698#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1699#define MX53_PAD_EIM_D24__GPIO3_24 (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1700#define MX53_PAD_EIM_D24__UART3_TXD_MUX (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1701#define MX53_PAD_EIM_D24__ECSPI1_SS2 (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1702#define MX53_PAD_EIM_D24__CSPI_SS2 (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1703#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1704#define MX53_PAD_EIM_D24__ECSPI2_SS2 (_MX53_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1705#define MX53_PAD_EIM_D24__UART1_DTR (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
1706#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
1707#define MX53_PAD_EIM_D25__GPIO3_25 (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
1708#define MX53_PAD_EIM_D25__UART3_RXD_MUX (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1709#define MX53_PAD_EIM_D25__ECSPI1_SS3 (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1710#define MX53_PAD_EIM_D25__CSPI_SS3 (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1711#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1712#define MX53_PAD_EIM_D25__ECSPI2_SS3 (_MX53_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1713#define MX53_PAD_EIM_D25__UART1_DSR (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL))
1714#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1715#define MX53_PAD_EIM_D26__GPIO3_26 (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1716#define MX53_PAD_EIM_D26__UART2_TXD_MUX (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1717#define MX53_PAD_EIM_D26__FIRI_RXD (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1718#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1719#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1720#define MX53_PAD_EIM_D26__IPU_SISG_2 (_MX53_PAD_EIM_D26__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1721#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1722#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
1723#define MX53_PAD_EIM_D27__GPIO3_27 (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
1724#define MX53_PAD_EIM_D27__UART2_RXD_MUX (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
1725#define MX53_PAD_EIM_D27__FIRI_TXD (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1726#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1727#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1728#define MX53_PAD_EIM_D27__IPU_SISG_3 (_MX53_PAD_EIM_D27__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1729#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1730#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1731#define MX53_PAD_EIM_D28__GPIO3_28 (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1732#define MX53_PAD_EIM_D28__UART2_CTS (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1733#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1734#define MX53_PAD_EIM_D28__CSPI_MOSI (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1735#define MX53_PAD_EIM_D28__I2C1_SDA (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
1736#define MX53_PAD_EIM_D28__IPU_EXT_TRIG (_MX53_PAD_EIM_D28__IPU_EXT_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
1737#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1738#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1739#define MX53_PAD_EIM_D29__GPIO3_29 (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1740#define MX53_PAD_EIM_D29__UART2_RTS (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1741#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
1742#define MX53_PAD_EIM_D29__CSPI_SS0 (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1743#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1744#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC (_MX53_PAD_EIM_D29__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1745#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1746#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1747#define MX53_PAD_EIM_D30__GPIO3_30 (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1748#define MX53_PAD_EIM_D30__UART3_CTS (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1749#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1750#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1751#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1752#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC (_MX53_PAD_EIM_D30__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1753#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
1754#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1755#define MX53_PAD_EIM_D31__GPIO3_31 (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1756#define MX53_PAD_EIM_D31__UART3_RTS (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
1757#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1758#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1759#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1760#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1761#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D31__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1762#define MX53_PAD_EIM_A24__EMI_WEIM_A_24 (_MX53_PAD_EIM_A24__EMI_WEIM_A_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1763#define MX53_PAD_EIM_A24__GPIO5_4 (_MX53_PAD_EIM_A24__GPIO5_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1764#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 (_MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1765#define MX53_PAD_EIM_A24__IPU_CSI1_D_19 (_MX53_PAD_EIM_A24__IPU_CSI1_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1766#define MX53_PAD_EIM_A24__IPU_SISG_2 (_MX53_PAD_EIM_A24__IPU_SISG_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1767#define MX53_PAD_EIM_A24__USBPHY2_BVALID (_MX53_PAD_EIM_A24__USBPHY2_BVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
1768#define MX53_PAD_EIM_A23__EMI_WEIM_A_23 (_MX53_PAD_EIM_A23__EMI_WEIM_A_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1769#define MX53_PAD_EIM_A23__GPIO6_6 (_MX53_PAD_EIM_A23__GPIO6_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1770#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 (_MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1771#define MX53_PAD_EIM_A23__IPU_CSI1_D_18 (_MX53_PAD_EIM_A23__IPU_CSI1_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1772#define MX53_PAD_EIM_A23__IPU_SISG_3 (_MX53_PAD_EIM_A23__IPU_SISG_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1773#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION (_MX53_PAD_EIM_A23__USBPHY2_ENDSESSION | MUX_PAD_CTRL(NO_PAD_CTRL))
1774#define MX53_PAD_EIM_A22__EMI_WEIM_A_22 (_MX53_PAD_EIM_A22__EMI_WEIM_A_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1775#define MX53_PAD_EIM_A22__GPIO2_16 (_MX53_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1776#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 (_MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1777#define MX53_PAD_EIM_A22__IPU_CSI1_D_17 (_MX53_PAD_EIM_A22__IPU_CSI1_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1778#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7 (_MX53_PAD_EIM_A22__SRC_BT_CFG1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1779#define MX53_PAD_EIM_A21__EMI_WEIM_A_21 (_MX53_PAD_EIM_A21__EMI_WEIM_A_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1780#define MX53_PAD_EIM_A21__GPIO2_17 (_MX53_PAD_EIM_A21__GPIO2_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1781#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 (_MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1782#define MX53_PAD_EIM_A21__IPU_CSI1_D_16 (_MX53_PAD_EIM_A21__IPU_CSI1_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1783#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6 (_MX53_PAD_EIM_A21__SRC_BT_CFG1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1784#define MX53_PAD_EIM_A20__EMI_WEIM_A_20 (_MX53_PAD_EIM_A20__EMI_WEIM_A_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1785#define MX53_PAD_EIM_A20__GPIO2_18 (_MX53_PAD_EIM_A20__GPIO2_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1786#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 (_MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1787#define MX53_PAD_EIM_A20__IPU_CSI1_D_15 (_MX53_PAD_EIM_A20__IPU_CSI1_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1788#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5 (_MX53_PAD_EIM_A20__SRC_BT_CFG1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1789#define MX53_PAD_EIM_A19__EMI_WEIM_A_19 (_MX53_PAD_EIM_A19__EMI_WEIM_A_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1790#define MX53_PAD_EIM_A19__GPIO2_19 (_MX53_PAD_EIM_A19__GPIO2_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1791#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 (_MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1792#define MX53_PAD_EIM_A19__IPU_CSI1_D_14 (_MX53_PAD_EIM_A19__IPU_CSI1_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1793#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4 (_MX53_PAD_EIM_A19__SRC_BT_CFG1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1794#define MX53_PAD_EIM_A18__EMI_WEIM_A_18 (_MX53_PAD_EIM_A18__EMI_WEIM_A_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1795#define MX53_PAD_EIM_A18__GPIO2_20 (_MX53_PAD_EIM_A18__GPIO2_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1796#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 (_MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1797#define MX53_PAD_EIM_A18__IPU_CSI1_D_13 (_MX53_PAD_EIM_A18__IPU_CSI1_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1798#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3 (_MX53_PAD_EIM_A18__SRC_BT_CFG1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1799#define MX53_PAD_EIM_A17__EMI_WEIM_A_17 (_MX53_PAD_EIM_A17__EMI_WEIM_A_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1800#define MX53_PAD_EIM_A17__GPIO2_21 (_MX53_PAD_EIM_A17__GPIO2_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1801#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 (_MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1802#define MX53_PAD_EIM_A17__IPU_CSI1_D_12 (_MX53_PAD_EIM_A17__IPU_CSI1_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1803#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2 (_MX53_PAD_EIM_A17__SRC_BT_CFG1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1804#define MX53_PAD_EIM_A16__EMI_WEIM_A_16 (_MX53_PAD_EIM_A16__EMI_WEIM_A_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1805#define MX53_PAD_EIM_A16__GPIO2_22 (_MX53_PAD_EIM_A16__GPIO2_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1806#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK (_MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1807#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK (_MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1808#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1 (_MX53_PAD_EIM_A16__SRC_BT_CFG1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1809#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 (_MX53_PAD_EIM_CS0__EMI_WEIM_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1810#define MX53_PAD_EIM_CS0__GPIO2_23 (_MX53_PAD_EIM_CS0__GPIO2_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1811#define MX53_PAD_EIM_CS0__ECSPI2_SCLK (_MX53_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1812#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5 (_MX53_PAD_EIM_CS0__IPU_DI1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1813#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 (_MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1814#define MX53_PAD_EIM_CS1__GPIO2_24 (_MX53_PAD_EIM_CS1__GPIO2_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1815#define MX53_PAD_EIM_CS1__ECSPI2_MOSI (_MX53_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1816#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6 (_MX53_PAD_EIM_CS1__IPU_DI1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1817#define MX53_PAD_EIM_OE__EMI_WEIM_OE (_MX53_PAD_EIM_OE__EMI_WEIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
1818#define MX53_PAD_EIM_OE__GPIO2_25 (_MX53_PAD_EIM_OE__GPIO2_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
1819#define MX53_PAD_EIM_OE__ECSPI2_MISO (_MX53_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
1820#define MX53_PAD_EIM_OE__IPU_DI1_PIN7 (_MX53_PAD_EIM_OE__IPU_DI1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1821#define MX53_PAD_EIM_OE__USBPHY2_IDDIG (_MX53_PAD_EIM_OE__USBPHY2_IDDIG | MUX_PAD_CTRL(NO_PAD_CTRL))
1822#define MX53_PAD_EIM_RW__EMI_WEIM_RW (_MX53_PAD_EIM_RW__EMI_WEIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL))
1823#define MX53_PAD_EIM_RW__GPIO2_26 (_MX53_PAD_EIM_RW__GPIO2_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1824#define MX53_PAD_EIM_RW__ECSPI2_SS0 (_MX53_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1825#define MX53_PAD_EIM_RW__IPU_DI1_PIN8 (_MX53_PAD_EIM_RW__IPU_DI1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1826#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT (_MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT | MUX_PAD_CTRL(NO_PAD_CTRL))
1827#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA (_MX53_PAD_EIM_LBA__EMI_WEIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
1828#define MX53_PAD_EIM_LBA__GPIO2_27 (_MX53_PAD_EIM_LBA__GPIO2_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
1829#define MX53_PAD_EIM_LBA__ECSPI2_SS1 (_MX53_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1830#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17 (_MX53_PAD_EIM_LBA__IPU_DI1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1831#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 (_MX53_PAD_EIM_LBA__SRC_BT_CFG1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1832#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 (_MX53_PAD_EIM_EB0__EMI_WEIM_EB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1833#define MX53_PAD_EIM_EB0__GPIO2_28 (_MX53_PAD_EIM_EB0__GPIO2_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1834#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 (_MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1835#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11 (_MX53_PAD_EIM_EB0__IPU_CSI1_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1836#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY (_MX53_PAD_EIM_EB0__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
1837#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 (_MX53_PAD_EIM_EB0__SRC_BT_CFG2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1838#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 (_MX53_PAD_EIM_EB1__EMI_WEIM_EB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1839#define MX53_PAD_EIM_EB1__GPIO2_29 (_MX53_PAD_EIM_EB1__GPIO2_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1840#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 (_MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1841#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10 (_MX53_PAD_EIM_EB1__IPU_CSI1_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1842#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 (_MX53_PAD_EIM_EB1__SRC_BT_CFG2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1843#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 (_MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1844#define MX53_PAD_EIM_DA0__GPIO3_0 (_MX53_PAD_EIM_DA0__GPIO3_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1845#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 (_MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1846#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9 (_MX53_PAD_EIM_DA0__IPU_CSI1_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1847#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 (_MX53_PAD_EIM_DA0__SRC_BT_CFG2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1848#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 (_MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1849#define MX53_PAD_EIM_DA1__GPIO3_1 (_MX53_PAD_EIM_DA1__GPIO3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1850#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 (_MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1851#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8 (_MX53_PAD_EIM_DA1__IPU_CSI1_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1852#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 (_MX53_PAD_EIM_DA1__SRC_BT_CFG2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1853#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 (_MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1854#define MX53_PAD_EIM_DA2__GPIO3_2 (_MX53_PAD_EIM_DA2__GPIO3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1855#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 (_MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1856#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7 (_MX53_PAD_EIM_DA2__IPU_CSI1_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1857#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 (_MX53_PAD_EIM_DA2__SRC_BT_CFG2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1858#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 (_MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1859#define MX53_PAD_EIM_DA3__GPIO3_3 (_MX53_PAD_EIM_DA3__GPIO3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1860#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 (_MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1861#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6 (_MX53_PAD_EIM_DA3__IPU_CSI1_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1862#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 (_MX53_PAD_EIM_DA3__SRC_BT_CFG2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1863#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 (_MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1864#define MX53_PAD_EIM_DA4__GPIO3_4 (_MX53_PAD_EIM_DA4__GPIO3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1865#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 (_MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1866#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5 (_MX53_PAD_EIM_DA4__IPU_CSI1_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1867#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 (_MX53_PAD_EIM_DA4__SRC_BT_CFG3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1868#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 (_MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1869#define MX53_PAD_EIM_DA5__GPIO3_5 (_MX53_PAD_EIM_DA5__GPIO3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1870#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 (_MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1871#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4 (_MX53_PAD_EIM_DA5__IPU_CSI1_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1872#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 (_MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1873#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 (_MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1874#define MX53_PAD_EIM_DA6__GPIO3_6 (_MX53_PAD_EIM_DA6__GPIO3_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1875#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 (_MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1876#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3 (_MX53_PAD_EIM_DA6__IPU_CSI1_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1877#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 (_MX53_PAD_EIM_DA6__SRC_BT_CFG3_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1878#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 (_MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1879#define MX53_PAD_EIM_DA7__GPIO3_7 (_MX53_PAD_EIM_DA7__GPIO3_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1880#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 (_MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1881#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2 (_MX53_PAD_EIM_DA7__IPU_CSI1_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1882#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 (_MX53_PAD_EIM_DA7__SRC_BT_CFG3_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1883#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 (_MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1884#define MX53_PAD_EIM_DA8__GPIO3_8 (_MX53_PAD_EIM_DA8__GPIO3_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1885#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 (_MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1886#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1 (_MX53_PAD_EIM_DA8__IPU_CSI1_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1887#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 (_MX53_PAD_EIM_DA8__SRC_BT_CFG3_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1888#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 (_MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1889#define MX53_PAD_EIM_DA9__GPIO3_9 (_MX53_PAD_EIM_DA9__GPIO3_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1890#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 (_MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1891#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0 (_MX53_PAD_EIM_DA9__IPU_CSI1_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1892#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 (_MX53_PAD_EIM_DA9__SRC_BT_CFG3_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1893#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 (_MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1894#define MX53_PAD_EIM_DA10__GPIO3_10 (_MX53_PAD_EIM_DA10__GPIO3_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1895#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15 (_MX53_PAD_EIM_DA10__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1896#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN (_MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1897#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 (_MX53_PAD_EIM_DA10__SRC_BT_CFG3_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1898#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 (_MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1899#define MX53_PAD_EIM_DA11__GPIO3_11 (_MX53_PAD_EIM_DA11__GPIO3_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1900#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2 (_MX53_PAD_EIM_DA11__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1901#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC (_MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1902#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 (_MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1903#define MX53_PAD_EIM_DA12__GPIO3_12 (_MX53_PAD_EIM_DA12__GPIO3_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1904#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3 (_MX53_PAD_EIM_DA12__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1905#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC (_MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1906#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 (_MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1907#define MX53_PAD_EIM_DA13__GPIO3_13 (_MX53_PAD_EIM_DA13__GPIO3_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1908#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS (_MX53_PAD_EIM_DA13__IPU_DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1909#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK (_MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1910#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 (_MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1911#define MX53_PAD_EIM_DA14__GPIO3_14 (_MX53_PAD_EIM_DA14__GPIO3_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1912#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS (_MX53_PAD_EIM_DA14__IPU_DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1913#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK (_MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1914#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 (_MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1915#define MX53_PAD_EIM_DA15__GPIO3_15 (_MX53_PAD_EIM_DA15__GPIO3_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1916#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1917#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4 (_MX53_PAD_EIM_DA15__IPU_DI1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1918#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B (_MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1919#define MX53_PAD_NANDF_WE_B__GPIO6_12 (_MX53_PAD_NANDF_WE_B__GPIO6_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1920#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B (_MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1921#define MX53_PAD_NANDF_RE_B__GPIO6_13 (_MX53_PAD_NANDF_RE_B__GPIO6_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1922#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT (_MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
1923#define MX53_PAD_EIM_WAIT__GPIO5_0 (_MX53_PAD_EIM_WAIT__GPIO5_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1924#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B (_MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1925#define MX53_PAD_LVDS1_TX3_P__GPIO6_22 (_MX53_PAD_LVDS1_TX3_P__GPIO6_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1926#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 (_MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1927#define MX53_PAD_LVDS1_TX2_P__GPIO6_24 (_MX53_PAD_LVDS1_TX2_P__GPIO6_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1928#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 (_MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1929#define MX53_PAD_LVDS1_CLK_P__GPIO6_26 (_MX53_PAD_LVDS1_CLK_P__GPIO6_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1930#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK (_MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1931#define MX53_PAD_LVDS1_TX1_P__GPIO6_28 (_MX53_PAD_LVDS1_TX1_P__GPIO6_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1932#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 (_MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1933#define MX53_PAD_LVDS1_TX0_P__GPIO6_30 (_MX53_PAD_LVDS1_TX0_P__GPIO6_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1934#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 (_MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1935#define MX53_PAD_LVDS0_TX3_P__GPIO7_22 (_MX53_PAD_LVDS0_TX3_P__GPIO7_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1936#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 (_MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1937#define MX53_PAD_LVDS0_CLK_P__GPIO7_24 (_MX53_PAD_LVDS0_CLK_P__GPIO7_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1938#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK (_MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1939#define MX53_PAD_LVDS0_TX2_P__GPIO7_26 (_MX53_PAD_LVDS0_TX2_P__GPIO7_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1940#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 (_MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1941#define MX53_PAD_LVDS0_TX1_P__GPIO7_28 (_MX53_PAD_LVDS0_TX1_P__GPIO7_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
1942#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 (_MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1943#define MX53_PAD_LVDS0_TX0_P__GPIO7_30 (_MX53_PAD_LVDS0_TX0_P__GPIO7_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1944#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 (_MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1945#define MX53_PAD_GPIO_10__GPIO4_0 (_MX53_PAD_GPIO_10__GPIO4_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1946#define MX53_PAD_GPIO_10__OSC32k_32K_OUT (_MX53_PAD_GPIO_10__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
1947#define MX53_PAD_GPIO_11__GPIO4_1 (_MX53_PAD_GPIO_11__GPIO4_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1948#define MX53_PAD_GPIO_12__GPIO4_2 (_MX53_PAD_GPIO_12__GPIO4_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1949#define MX53_PAD_GPIO_13__GPIO4_3 (_MX53_PAD_GPIO_13__GPIO4_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1950#define MX53_PAD_GPIO_14__GPIO4_4 (_MX53_PAD_GPIO_14__GPIO4_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1951#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE (_MX53_PAD_NANDF_CLE__EMI_NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
1952#define MX53_PAD_NANDF_CLE__GPIO6_7 (_MX53_PAD_NANDF_CLE__GPIO6_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1953#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 (_MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1954#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE (_MX53_PAD_NANDF_ALE__EMI_NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
1955#define MX53_PAD_NANDF_ALE__GPIO6_8 (_MX53_PAD_NANDF_ALE__GPIO6_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1956#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 (_MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1957#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B (_MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1958#define MX53_PAD_NANDF_WP_B__GPIO6_9 (_MX53_PAD_NANDF_WP_B__GPIO6_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1959#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 (_MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1960#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 (_MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1961#define MX53_PAD_NANDF_RB0__GPIO6_10 (_MX53_PAD_NANDF_RB0__GPIO6_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1962#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 (_MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1963#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 (_MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1964#define MX53_PAD_NANDF_CS0__GPIO6_11 (_MX53_PAD_NANDF_CS0__GPIO6_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1965#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 (_MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1966#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 (_MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1967#define MX53_PAD_NANDF_CS1__GPIO6_14 (_MX53_PAD_NANDF_CS1__GPIO6_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1968#define MX53_PAD_NANDF_CS1__MLB_MLBCLK (_MX53_PAD_NANDF_CS1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1969#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 (_MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1970#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 (_MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1971#define MX53_PAD_NANDF_CS2__GPIO6_15 (_MX53_PAD_NANDF_CS2__GPIO6_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1972#define MX53_PAD_NANDF_CS2__IPU_SISG_0 (_MX53_PAD_NANDF_CS2__IPU_SISG_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1973#define MX53_PAD_NANDF_CS2__ESAI1_TX0 (_MX53_PAD_NANDF_CS2__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1974#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE (_MX53_PAD_NANDF_CS2__EMI_WEIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
1975#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK (_MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1976#define MX53_PAD_NANDF_CS2__MLB_MLBSIG (_MX53_PAD_NANDF_CS2__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
1977#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 (_MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1978#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 (_MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1979#define MX53_PAD_NANDF_CS3__GPIO6_16 (_MX53_PAD_NANDF_CS3__GPIO6_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1980#define MX53_PAD_NANDF_CS3__IPU_SISG_1 (_MX53_PAD_NANDF_CS3__IPU_SISG_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1981#define MX53_PAD_NANDF_CS3__ESAI1_TX1 (_MX53_PAD_NANDF_CS3__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1982#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 (_MX53_PAD_NANDF_CS3__EMI_WEIM_A_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
1983#define MX53_PAD_NANDF_CS3__MLB_MLBDAT (_MX53_PAD_NANDF_CS3__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
1984#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 (_MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1985#define MX53_PAD_FEC_MDIO__FEC_MDIO (_MX53_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1986#define MX53_PAD_FEC_MDIO__GPIO1_22 (_MX53_PAD_FEC_MDIO__GPIO1_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1987#define MX53_PAD_FEC_MDIO__ESAI1_SCKR (_MX53_PAD_FEC_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
1988#define MX53_PAD_FEC_MDIO__FEC_COL (_MX53_PAD_FEC_MDIO__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
1989#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 (_MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1990#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 (_MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1991#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 (_MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 | MUX_PAD_CTRL(NO_PAD_CTRL))
1992#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK (_MX53_PAD_FEC_REF_CLK__FEC_TX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1993#define MX53_PAD_FEC_REF_CLK__GPIO1_23 (_MX53_PAD_FEC_REF_CLK__GPIO1_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1994#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR (_MX53_PAD_FEC_REF_CLK__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
1995#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 (_MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1996#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 (_MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50 | MUX_PAD_CTRL(NO_PAD_CTRL))
1997#define MX53_PAD_FEC_RX_ER__FEC_RX_ER (_MX53_PAD_FEC_RX_ER__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
1998#define MX53_PAD_FEC_RX_ER__GPIO1_24 (_MX53_PAD_FEC_RX_ER__GPIO1_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
1999#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR (_MX53_PAD_FEC_RX_ER__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
2000#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK (_MX53_PAD_FEC_RX_ER__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2001#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 (_MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2002#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV (_MX53_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
2003#define MX53_PAD_FEC_CRS_DV__GPIO1_25 (_MX53_PAD_FEC_CRS_DV__GPIO1_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
2004#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT (_MX53_PAD_FEC_CRS_DV__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
2005#define MX53_PAD_FEC_RXD1__FEC_RDATA_1 (_MX53_PAD_FEC_RXD1__FEC_RDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2006#define MX53_PAD_FEC_RXD1__GPIO1_26 (_MX53_PAD_FEC_RXD1__GPIO1_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
2007#define MX53_PAD_FEC_RXD1__ESAI1_FST (_MX53_PAD_FEC_RXD1__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
2008#define MX53_PAD_FEC_RXD1__MLB_MLBSIG (_MX53_PAD_FEC_RXD1__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
2009#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 (_MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2010#define MX53_PAD_FEC_RXD0__FEC_RDATA_0 (_MX53_PAD_FEC_RXD0__FEC_RDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2011#define MX53_PAD_FEC_RXD0__GPIO1_27 (_MX53_PAD_FEC_RXD0__GPIO1_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
2012#define MX53_PAD_FEC_RXD0__ESAI1_HCKT (_MX53_PAD_FEC_RXD0__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
2013#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT (_MX53_PAD_FEC_RXD0__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
2014#define MX53_PAD_FEC_TX_EN__FEC_TX_EN (_MX53_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
2015#define MX53_PAD_FEC_TX_EN__GPIO1_28 (_MX53_PAD_FEC_TX_EN__GPIO1_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
2016#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 (_MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2017#define MX53_PAD_FEC_TXD1__FEC_TDATA_1 (_MX53_PAD_FEC_TXD1__FEC_TDATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2018#define MX53_PAD_FEC_TXD1__GPIO1_29 (_MX53_PAD_FEC_TXD1__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
2019#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 (_MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2020#define MX53_PAD_FEC_TXD1__MLB_MLBCLK (_MX53_PAD_FEC_TXD1__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2021#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK (_MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2022#define MX53_PAD_FEC_TXD0__FEC_TDATA_0 (_MX53_PAD_FEC_TXD0__FEC_TDATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2023#define MX53_PAD_FEC_TXD0__GPIO1_30 (_MX53_PAD_FEC_TXD0__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
2024#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 (_MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2025#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 (_MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2026#define MX53_PAD_FEC_MDC__FEC_MDC (_MX53_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(NO_PAD_CTRL))
2027#define MX53_PAD_FEC_MDC__GPIO1_31 (_MX53_PAD_FEC_MDC__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
2028#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 (_MX53_PAD_FEC_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2029#define MX53_PAD_FEC_MDC__MLB_MLBDAT (_MX53_PAD_FEC_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
2030#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG (_MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
2031#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 (_MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2032#define MX53_PAD_PATA_DIOW__PATA_DIOW (_MX53_PAD_PATA_DIOW__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
2033#define MX53_PAD_PATA_DIOW__GPIO6_17 (_MX53_PAD_PATA_DIOW__GPIO6_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
2034#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX (_MX53_PAD_PATA_DIOW__UART1_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2035#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 (_MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2036#define MX53_PAD_PATA_DMACK__PATA_DMACK (_MX53_PAD_PATA_DMACK__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
2037#define MX53_PAD_PATA_DMACK__GPIO6_18 (_MX53_PAD_PATA_DMACK__GPIO6_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
2038#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX (_MX53_PAD_PATA_DMACK__UART1_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2039#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 (_MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2040#define MX53_PAD_PATA_DMARQ__PATA_DMARQ (_MX53_PAD_PATA_DMARQ__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
2041#define MX53_PAD_PATA_DMARQ__GPIO7_0 (_MX53_PAD_PATA_DMARQ__GPIO7_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2042#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX (_MX53_PAD_PATA_DMARQ__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2043#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 (_MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2044#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 (_MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2045#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN (_MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
2046#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1 (_MX53_PAD_PATA_BUFFER_EN__GPIO7_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2047#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX (_MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2048#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 (_MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2049#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 (_MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2050#define MX53_PAD_PATA_INTRQ__PATA_INTRQ (_MX53_PAD_PATA_INTRQ__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
2051#define MX53_PAD_PATA_INTRQ__GPIO7_2 (_MX53_PAD_PATA_INTRQ__GPIO7_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2052#define MX53_PAD_PATA_INTRQ__UART2_CTS (_MX53_PAD_PATA_INTRQ__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2053#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN (_MX53_PAD_PATA_INTRQ__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2054#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 (_MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2055#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 (_MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2056#define MX53_PAD_PATA_DIOR__PATA_DIOR (_MX53_PAD_PATA_DIOR__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
2057#define MX53_PAD_PATA_DIOR__GPIO7_3 (_MX53_PAD_PATA_DIOR__GPIO7_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2058#define MX53_PAD_PATA_DIOR__UART2_RTS (_MX53_PAD_PATA_DIOR__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2059#define MX53_PAD_PATA_DIOR__CAN1_RXCAN (_MX53_PAD_PATA_DIOR__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2060#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 (_MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2061#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2062#define MX53_PAD_PATA_RESET_B__GPIO7_4 (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2063#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2064#define MX53_PAD_PATA_RESET_B__UART1_CTS (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
2065#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2066#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2067#define MX53_PAD_PATA_IORDY__PATA_IORDY (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
2068#define MX53_PAD_PATA_IORDY__GPIO7_5 (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2069#define MX53_PAD_PATA_IORDY__ESDHC3_CLK (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2070#define MX53_PAD_PATA_IORDY__UART1_RTS (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
2071#define MX53_PAD_PATA_IORDY__CAN2_RXCAN (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2072#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2073#define MX53_PAD_PATA_DA_0__PATA_DA_0 (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2074#define MX53_PAD_PATA_DA_0__GPIO7_6 (_MX53_PAD_PATA_DA_0__GPIO7_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2075#define MX53_PAD_PATA_DA_0__ESDHC3_RST (_MX53_PAD_PATA_DA_0__ESDHC3_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
2076#define MX53_PAD_PATA_DA_0__OWIRE_LINE (_MX53_PAD_PATA_DA_0__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
2077#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 (_MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2078#define MX53_PAD_PATA_DA_1__PATA_DA_1 (_MX53_PAD_PATA_DA_1__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2079#define MX53_PAD_PATA_DA_1__GPIO7_7 (_MX53_PAD_PATA_DA_1__GPIO7_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2080#define MX53_PAD_PATA_DA_1__ESDHC4_CMD (_MX53_PAD_PATA_DA_1__ESDHC4_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2081#define MX53_PAD_PATA_DA_1__UART3_CTS (_MX53_PAD_PATA_DA_1__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2082#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 (_MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2083#define MX53_PAD_PATA_DA_2__PATA_DA_2 (_MX53_PAD_PATA_DA_2__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2084#define MX53_PAD_PATA_DA_2__GPIO7_8 (_MX53_PAD_PATA_DA_2__GPIO7_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2085#define MX53_PAD_PATA_DA_2__ESDHC4_CLK (_MX53_PAD_PATA_DA_2__ESDHC4_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2086#define MX53_PAD_PATA_DA_2__UART3_RTS (_MX53_PAD_PATA_DA_2__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2087#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 (_MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2088#define MX53_PAD_PATA_CS_0__PATA_CS_0 (_MX53_PAD_PATA_CS_0__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2089#define MX53_PAD_PATA_CS_0__GPIO7_9 (_MX53_PAD_PATA_CS_0__GPIO7_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2090#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX (_MX53_PAD_PATA_CS_0__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2091#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 (_MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2092#define MX53_PAD_PATA_CS_1__PATA_CS_1 (_MX53_PAD_PATA_CS_1__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2093#define MX53_PAD_PATA_CS_1__GPIO7_10 (_MX53_PAD_PATA_CS_1__GPIO7_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2094#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX (_MX53_PAD_PATA_CS_1__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
2095#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 (_MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2096#define MX53_PAD_PATA_DATA0__PATA_DATA_0 (_MX53_PAD_PATA_DATA0__PATA_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2097#define MX53_PAD_PATA_DATA0__GPIO2_0 (_MX53_PAD_PATA_DATA0__GPIO2_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2098#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 (_MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2099#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4 (_MX53_PAD_PATA_DATA0__ESDHC3_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2100#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 (_MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2101#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 (_MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2102#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 (_MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2103#define MX53_PAD_PATA_DATA1__PATA_DATA_1 (_MX53_PAD_PATA_DATA1__PATA_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2104#define MX53_PAD_PATA_DATA1__GPIO2_1 (_MX53_PAD_PATA_DATA1__GPIO2_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2105#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 (_MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2106#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5 (_MX53_PAD_PATA_DATA1__ESDHC3_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2107#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 (_MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2108#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 (_MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2109#define MX53_PAD_PATA_DATA2__PATA_DATA_2 (_MX53_PAD_PATA_DATA2__PATA_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2110#define MX53_PAD_PATA_DATA2__GPIO2_2 (_MX53_PAD_PATA_DATA2__GPIO2_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2111#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 (_MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2112#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6 (_MX53_PAD_PATA_DATA2__ESDHC3_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2113#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 (_MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2114#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 (_MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2115#define MX53_PAD_PATA_DATA3__PATA_DATA_3 (_MX53_PAD_PATA_DATA3__PATA_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2116#define MX53_PAD_PATA_DATA3__GPIO2_3 (_MX53_PAD_PATA_DATA3__GPIO2_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2117#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 (_MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2118#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7 (_MX53_PAD_PATA_DATA3__ESDHC3_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2119#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 (_MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2120#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 (_MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2121#define MX53_PAD_PATA_DATA4__PATA_DATA_4 (_MX53_PAD_PATA_DATA4__PATA_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2122#define MX53_PAD_PATA_DATA4__GPIO2_4 (_MX53_PAD_PATA_DATA4__GPIO2_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2123#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 (_MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2124#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4 (_MX53_PAD_PATA_DATA4__ESDHC4_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2125#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 (_MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2126#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 (_MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2127#define MX53_PAD_PATA_DATA5__PATA_DATA_5 (_MX53_PAD_PATA_DATA5__PATA_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2128#define MX53_PAD_PATA_DATA5__GPIO2_5 (_MX53_PAD_PATA_DATA5__GPIO2_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2129#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 (_MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2130#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5 (_MX53_PAD_PATA_DATA5__ESDHC4_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2131#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 (_MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2132#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 (_MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2133#define MX53_PAD_PATA_DATA6__PATA_DATA_6 (_MX53_PAD_PATA_DATA6__PATA_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2134#define MX53_PAD_PATA_DATA6__GPIO2_6 (_MX53_PAD_PATA_DATA6__GPIO2_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2135#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 (_MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2136#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6 (_MX53_PAD_PATA_DATA6__ESDHC4_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2137#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 (_MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2138#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 (_MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2139#define MX53_PAD_PATA_DATA7__PATA_DATA_7 (_MX53_PAD_PATA_DATA7__PATA_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2140#define MX53_PAD_PATA_DATA7__GPIO2_7 (_MX53_PAD_PATA_DATA7__GPIO2_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2141#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 (_MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2142#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7 (_MX53_PAD_PATA_DATA7__ESDHC4_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2143#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 (_MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2144#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 (_MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2145#define MX53_PAD_PATA_DATA8__PATA_DATA_8 (_MX53_PAD_PATA_DATA8__PATA_DATA_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2146#define MX53_PAD_PATA_DATA8__GPIO2_8 (_MX53_PAD_PATA_DATA8__GPIO2_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2147#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4 (_MX53_PAD_PATA_DATA8__ESDHC1_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2148#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 (_MX53_PAD_PATA_DATA8__EMI_NANDF_D_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2149#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0 (_MX53_PAD_PATA_DATA8__ESDHC3_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2150#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 (_MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2151#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 (_MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2152#define MX53_PAD_PATA_DATA9__PATA_DATA_9 (_MX53_PAD_PATA_DATA9__PATA_DATA_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2153#define MX53_PAD_PATA_DATA9__GPIO2_9 (_MX53_PAD_PATA_DATA9__GPIO2_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2154#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5 (_MX53_PAD_PATA_DATA9__ESDHC1_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2155#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 (_MX53_PAD_PATA_DATA9__EMI_NANDF_D_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2156#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1 (_MX53_PAD_PATA_DATA9__ESDHC3_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2157#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 (_MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2158#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 (_MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2159#define MX53_PAD_PATA_DATA10__PATA_DATA_10 (_MX53_PAD_PATA_DATA10__PATA_DATA_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2160#define MX53_PAD_PATA_DATA10__GPIO2_10 (_MX53_PAD_PATA_DATA10__GPIO2_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2161#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6 (_MX53_PAD_PATA_DATA10__ESDHC1_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2162#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 (_MX53_PAD_PATA_DATA10__EMI_NANDF_D_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2163#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2 (_MX53_PAD_PATA_DATA10__ESDHC3_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2164#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 (_MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2165#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 (_MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2166#define MX53_PAD_PATA_DATA11__PATA_DATA_11 (_MX53_PAD_PATA_DATA11__PATA_DATA_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2167#define MX53_PAD_PATA_DATA11__GPIO2_11 (_MX53_PAD_PATA_DATA11__GPIO2_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2168#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7 (_MX53_PAD_PATA_DATA11__ESDHC1_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2169#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 (_MX53_PAD_PATA_DATA11__EMI_NANDF_D_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2170#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3 (_MX53_PAD_PATA_DATA11__ESDHC3_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2171#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 (_MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2172#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 (_MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2173#define MX53_PAD_PATA_DATA12__PATA_DATA_12 (_MX53_PAD_PATA_DATA12__PATA_DATA_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2174#define MX53_PAD_PATA_DATA12__GPIO2_12 (_MX53_PAD_PATA_DATA12__GPIO2_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2175#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4 (_MX53_PAD_PATA_DATA12__ESDHC2_DAT4 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2176#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 (_MX53_PAD_PATA_DATA12__EMI_NANDF_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2177#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0 (_MX53_PAD_PATA_DATA12__ESDHC4_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2178#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 (_MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2179#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 (_MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2180#define MX53_PAD_PATA_DATA13__PATA_DATA_13 (_MX53_PAD_PATA_DATA13__PATA_DATA_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2181#define MX53_PAD_PATA_DATA13__GPIO2_13 (_MX53_PAD_PATA_DATA13__GPIO2_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2182#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5 (_MX53_PAD_PATA_DATA13__ESDHC2_DAT5 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2183#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 (_MX53_PAD_PATA_DATA13__EMI_NANDF_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2184#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1 (_MX53_PAD_PATA_DATA13__ESDHC4_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2185#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 (_MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2186#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 (_MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2187#define MX53_PAD_PATA_DATA14__PATA_DATA_14 (_MX53_PAD_PATA_DATA14__PATA_DATA_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2188#define MX53_PAD_PATA_DATA14__GPIO2_14 (_MX53_PAD_PATA_DATA14__GPIO2_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2189#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6 (_MX53_PAD_PATA_DATA14__ESDHC2_DAT6 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2190#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 (_MX53_PAD_PATA_DATA14__EMI_NANDF_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2191#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2 (_MX53_PAD_PATA_DATA14__ESDHC4_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2192#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 (_MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2193#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 (_MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2194#define MX53_PAD_PATA_DATA15__PATA_DATA_15 (_MX53_PAD_PATA_DATA15__PATA_DATA_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2195#define MX53_PAD_PATA_DATA15__GPIO2_15 (_MX53_PAD_PATA_DATA15__GPIO2_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2196#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7 (_MX53_PAD_PATA_DATA15__ESDHC2_DAT7 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2197#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 (_MX53_PAD_PATA_DATA15__EMI_NANDF_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2198#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3 (_MX53_PAD_PATA_DATA15__ESDHC4_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2199#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 (_MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2200#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 (_MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2201#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0 (_MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2202#define MX53_PAD_SD1_DATA0__GPIO1_16 (_MX53_PAD_SD1_DATA0__GPIO1_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
2203#define MX53_PAD_SD1_DATA0__GPT_CAPIN1 (_MX53_PAD_SD1_DATA0__GPT_CAPIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2204#define MX53_PAD_SD1_DATA0__CSPI_MISO (_MX53_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
2205#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP (_MX53_PAD_SD1_DATA0__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2206#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1 (_MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2207#define MX53_PAD_SD1_DATA1__GPIO1_17 (_MX53_PAD_SD1_DATA1__GPIO1_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
2208#define MX53_PAD_SD1_DATA1__GPT_CAPIN2 (_MX53_PAD_SD1_DATA1__GPT_CAPIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2209#define MX53_PAD_SD1_DATA1__CSPI_SS0 (_MX53_PAD_SD1_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2210#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP (_MX53_PAD_SD1_DATA1__CCM_PLL4_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2211#define MX53_PAD_SD1_CMD__ESDHC1_CMD (_MX53_PAD_SD1_CMD__ESDHC1_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2212#define MX53_PAD_SD1_CMD__GPIO1_18 (_MX53_PAD_SD1_CMD__GPIO1_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
2213#define MX53_PAD_SD1_CMD__GPT_CMPOUT1 (_MX53_PAD_SD1_CMD__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2214#define MX53_PAD_SD1_CMD__CSPI_MOSI (_MX53_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
2215#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP (_MX53_PAD_SD1_CMD__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2216#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2 (_MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2217#define MX53_PAD_SD1_DATA2__GPIO1_19 (_MX53_PAD_SD1_DATA2__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
2218#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2 (_MX53_PAD_SD1_DATA2__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2219#define MX53_PAD_SD1_DATA2__PWM2_PWMO (_MX53_PAD_SD1_DATA2__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
2220#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2221#define MX53_PAD_SD1_DATA2__CSPI_SS1 (_MX53_PAD_SD1_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2222#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
2223#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP (_MX53_PAD_SD1_DATA2__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2224#define MX53_PAD_SD1_CLK__ESDHC1_CLK (_MX53_PAD_SD1_CLK__ESDHC1_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2225#define MX53_PAD_SD1_CLK__GPIO1_20 (_MX53_PAD_SD1_CLK__GPIO1_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
2226#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT (_MX53_PAD_SD1_CLK__OSC32k_32K_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
2227#define MX53_PAD_SD1_CLK__GPT_CLKIN (_MX53_PAD_SD1_CLK__GPT_CLKIN | MUX_PAD_CTRL(NO_PAD_CTRL))
2228#define MX53_PAD_SD1_CLK__CSPI_SCLK (_MX53_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2229#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 (_MX53_PAD_SD1_CLK__SATA_PHY_DTB_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2230#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3 (_MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2231#define MX53_PAD_SD1_DATA3__GPIO1_21 (_MX53_PAD_SD1_DATA3__GPIO1_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
2232#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3 (_MX53_PAD_SD1_DATA3__GPT_CMPOUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2233#define MX53_PAD_SD1_DATA3__PWM1_PWMO (_MX53_PAD_SD1_DATA3__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
2234#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2235#define MX53_PAD_SD1_DATA3__CSPI_SS2 (_MX53_PAD_SD1_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2236#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB (_MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
2237#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 (_MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2238#define MX53_PAD_SD2_CLK__ESDHC2_CLK (_MX53_PAD_SD2_CLK__ESDHC2_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2239#define MX53_PAD_SD2_CLK__GPIO1_10 (_MX53_PAD_SD2_CLK__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
2240#define MX53_PAD_SD2_CLK__KPP_COL_5 (_MX53_PAD_SD2_CLK__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2241#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS (_MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
2242#define MX53_PAD_SD2_CLK__CSPI_SCLK (_MX53_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2243#define MX53_PAD_SD2_CLK__SCC_RANDOM_V (_MX53_PAD_SD2_CLK__SCC_RANDOM_V | MUX_PAD_CTRL(NO_PAD_CTRL))
2244#define MX53_PAD_SD2_CMD__ESDHC2_CMD (_MX53_PAD_SD2_CMD__ESDHC2_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2245#define MX53_PAD_SD2_CMD__GPIO1_11 (_MX53_PAD_SD2_CMD__GPIO1_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2246#define MX53_PAD_SD2_CMD__KPP_ROW_5 (_MX53_PAD_SD2_CMD__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2247#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC (_MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
2248#define MX53_PAD_SD2_CMD__CSPI_MOSI (_MX53_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
2249#define MX53_PAD_SD2_CMD__SCC_RANDOM (_MX53_PAD_SD2_CMD__SCC_RANDOM | MUX_PAD_CTRL(NO_PAD_CTRL))
2250#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3 (_MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2251#define MX53_PAD_SD2_DATA3__GPIO1_12 (_MX53_PAD_SD2_DATA3__GPIO1_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2252#define MX53_PAD_SD2_DATA3__KPP_COL_6 (_MX53_PAD_SD2_DATA3__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2253#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC (_MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
2254#define MX53_PAD_SD2_DATA3__CSPI_SS2 (_MX53_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2255#define MX53_PAD_SD2_DATA3__SJC_DONE (_MX53_PAD_SD2_DATA3__SJC_DONE | MUX_PAD_CTRL(NO_PAD_CTRL))
2256#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2 (_MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2257#define MX53_PAD_SD2_DATA2__GPIO1_13 (_MX53_PAD_SD2_DATA2__GPIO1_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2258#define MX53_PAD_SD2_DATA2__KPP_ROW_6 (_MX53_PAD_SD2_DATA2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2259#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD (_MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
2260#define MX53_PAD_SD2_DATA2__CSPI_SS1 (_MX53_PAD_SD2_DATA2__CSPI_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2261#define MX53_PAD_SD2_DATA2__SJC_FAIL (_MX53_PAD_SD2_DATA2__SJC_FAIL | MUX_PAD_CTRL(NO_PAD_CTRL))
2262#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1 (_MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2263#define MX53_PAD_SD2_DATA1__GPIO1_14 (_MX53_PAD_SD2_DATA1__GPIO1_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
2264#define MX53_PAD_SD2_DATA1__KPP_COL_7 (_MX53_PAD_SD2_DATA1__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2265#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS (_MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
2266#define MX53_PAD_SD2_DATA1__CSPI_SS0 (_MX53_PAD_SD2_DATA1__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2267#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO (_MX53_PAD_SD2_DATA1__RTIC_SEC_VIO | MUX_PAD_CTRL(NO_PAD_CTRL))
2268#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0 (_MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
2269#define MX53_PAD_SD2_DATA0__GPIO1_15 (_MX53_PAD_SD2_DATA0__GPIO1_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
2270#define MX53_PAD_SD2_DATA0__KPP_ROW_7 (_MX53_PAD_SD2_DATA0__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2271#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD (_MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
2272#define MX53_PAD_SD2_DATA0__CSPI_MISO (_MX53_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
2273#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT (_MX53_PAD_SD2_DATA0__RTIC_DONE_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
2274#define MX53_PAD_GPIO_0__CCM_CLKO (_MX53_PAD_GPIO_0__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
2275#define MX53_PAD_GPIO_0__GPIO1_0 (_MX53_PAD_GPIO_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2276#define MX53_PAD_GPIO_0__KPP_COL_5 (_MX53_PAD_GPIO_0__KPP_COL_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2277#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK (_MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2278#define MX53_PAD_GPIO_0__EPIT1_EPITO (_MX53_PAD_GPIO_0__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
2279#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB (_MX53_PAD_GPIO_0__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
2280#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR (_MX53_PAD_GPIO_0__USBOH3_USBH1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
2281#define MX53_PAD_GPIO_0__CSU_TD (_MX53_PAD_GPIO_0__CSU_TD | MUX_PAD_CTRL(NO_PAD_CTRL))
2282#define MX53_PAD_GPIO_1__ESAI1_SCKR (_MX53_PAD_GPIO_1__ESAI1_SCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
2283#define MX53_PAD_GPIO_1__GPIO1_1 (_MX53_PAD_GPIO_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2284#define MX53_PAD_GPIO_1__KPP_ROW_5 (_MX53_PAD_GPIO_1__KPP_ROW_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2285#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK (_MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2286#define MX53_PAD_GPIO_1__PWM2_PWMO (_MX53_PAD_GPIO_1__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
2287#define MX53_PAD_GPIO_1__WDOG2_WDOG_B (_MX53_PAD_GPIO_1__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2288#define MX53_PAD_GPIO_1__ESDHC1_CD (_MX53_PAD_GPIO_1__ESDHC1_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
2289#define MX53_PAD_GPIO_1__SRC_TESTER_ACK (_MX53_PAD_GPIO_1__SRC_TESTER_ACK | MUX_PAD_CTRL(NO_PAD_CTRL))
2290#define MX53_PAD_GPIO_9__ESAI1_FSR (_MX53_PAD_GPIO_9__ESAI1_FSR | MUX_PAD_CTRL(NO_PAD_CTRL))
2291#define MX53_PAD_GPIO_9__GPIO1_9 (_MX53_PAD_GPIO_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
2292#define MX53_PAD_GPIO_9__KPP_COL_6 (_MX53_PAD_GPIO_9__KPP_COL_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2293#define MX53_PAD_GPIO_9__CCM_REF_EN_B (_MX53_PAD_GPIO_9__CCM_REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2294#define MX53_PAD_GPIO_9__PWM1_PWMO (_MX53_PAD_GPIO_9__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
2295#define MX53_PAD_GPIO_9__WDOG1_WDOG_B (_MX53_PAD_GPIO_9__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2296#define MX53_PAD_GPIO_9__ESDHC1_WP (_MX53_PAD_GPIO_9__ESDHC1_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
2297#define MX53_PAD_GPIO_9__SCC_FAIL_STATE (_MX53_PAD_GPIO_9__SCC_FAIL_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
2298#define MX53_PAD_GPIO_3__ESAI1_HCKR (_MX53_PAD_GPIO_3__ESAI1_HCKR | MUX_PAD_CTRL(NO_PAD_CTRL))
2299#define MX53_PAD_GPIO_3__GPIO1_3 (_MX53_PAD_GPIO_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2300#define MX53_PAD_GPIO_3__I2C3_SCL (_MX53_PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
2301#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN (_MX53_PAD_GPIO_3__DPLLIP1_TOG_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
2302#define MX53_PAD_GPIO_3__CCM_CLKO2 (_MX53_PAD_GPIO_3__CCM_CLKO2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2303#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 (_MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2304#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC (_MX53_PAD_GPIO_3__USBOH3_USBH1_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
2305#define MX53_PAD_GPIO_3__MLB_MLBCLK (_MX53_PAD_GPIO_3__MLB_MLBCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2306#define MX53_PAD_GPIO_6__ESAI1_SCKT (_MX53_PAD_GPIO_6__ESAI1_SCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
2307#define MX53_PAD_GPIO_6__GPIO1_6 (_MX53_PAD_GPIO_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2308#define MX53_PAD_GPIO_6__I2C3_SDA (_MX53_PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
2309#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0 (_MX53_PAD_GPIO_6__CCM_CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2310#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB (_MX53_PAD_GPIO_6__CSU_CSU_INT_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
2311#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 (_MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2312#define MX53_PAD_GPIO_6__ESDHC2_LCTL (_MX53_PAD_GPIO_6__ESDHC2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
2313#define MX53_PAD_GPIO_6__MLB_MLBSIG (_MX53_PAD_GPIO_6__MLB_MLBSIG | MUX_PAD_CTRL(NO_PAD_CTRL))
2314#define MX53_PAD_GPIO_2__ESAI1_FST (_MX53_PAD_GPIO_2__ESAI1_FST | MUX_PAD_CTRL(NO_PAD_CTRL))
2315#define MX53_PAD_GPIO_2__GPIO1_2 (_MX53_PAD_GPIO_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2316#define MX53_PAD_GPIO_2__KPP_ROW_6 (_MX53_PAD_GPIO_2__KPP_ROW_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
2317#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1 (_MX53_PAD_GPIO_2__CCM_CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2318#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 (_MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2319#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 (_MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2320#define MX53_PAD_GPIO_2__ESDHC2_WP (_MX53_PAD_GPIO_2__ESDHC2_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
2321#define MX53_PAD_GPIO_2__MLB_MLBDAT (_MX53_PAD_GPIO_2__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL))
2322#define MX53_PAD_GPIO_4__ESAI1_HCKT (_MX53_PAD_GPIO_4__ESAI1_HCKT | MUX_PAD_CTRL(NO_PAD_CTRL))
2323#define MX53_PAD_GPIO_4__GPIO1_4 (_MX53_PAD_GPIO_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2324#define MX53_PAD_GPIO_4__KPP_COL_7 (_MX53_PAD_GPIO_4__KPP_COL_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2325#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2 (_MX53_PAD_GPIO_4__CCM_CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2326#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 (_MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2327#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 (_MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2328#define MX53_PAD_GPIO_4__ESDHC2_CD (_MX53_PAD_GPIO_4__ESDHC2_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
2329#define MX53_PAD_GPIO_4__SCC_SEC_STATE (_MX53_PAD_GPIO_4__SCC_SEC_STATE | MUX_PAD_CTRL(NO_PAD_CTRL))
2330#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3 (_MX53_PAD_GPIO_5__ESAI1_TX2_RX3 | MUX_PAD_CTRL(NO_PAD_CTRL))
2331#define MX53_PAD_GPIO_5__GPIO1_5 (_MX53_PAD_GPIO_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
2332#define MX53_PAD_GPIO_5__KPP_ROW_7 (_MX53_PAD_GPIO_5__KPP_ROW_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2333#define MX53_PAD_GPIO_5__CCM_CLKO (_MX53_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(NO_PAD_CTRL))
2334#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 (_MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2335#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 (_MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
2336#define MX53_PAD_GPIO_5__I2C3_SCL (_MX53_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
2337#define MX53_PAD_GPIO_5__CCM_PLL1_BYP (_MX53_PAD_GPIO_5__CCM_PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2338#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1 (_MX53_PAD_GPIO_7__ESAI1_TX4_RX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2339#define MX53_PAD_GPIO_7__GPIO1_7 (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
2340#define MX53_PAD_GPIO_7__EPIT1_EPITO (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
2341#define MX53_PAD_GPIO_7__CAN1_TXCAN (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2342#define MX53_PAD_GPIO_7__UART2_TXD_MUX (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
2343#define MX53_PAD_GPIO_7__FIRI_RXD (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
2344#define MX53_PAD_GPIO_7__SPDIF_PLOCK (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
2345#define MX53_PAD_GPIO_7__CCM_PLL2_BYP (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2346#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0 (_MX53_PAD_GPIO_8__ESAI1_TX5_RX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2347#define MX53_PAD_GPIO_8__GPIO1_8 (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
2348#define MX53_PAD_GPIO_8__EPIT2_EPITO (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
2349#define MX53_PAD_GPIO_8__CAN1_RXCAN (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
2350#define MX53_PAD_GPIO_8__UART2_RXD_MUX (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
2351#define MX53_PAD_GPIO_8__FIRI_TXD (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
2352#define MX53_PAD_GPIO_8__SPDIF_SRCLK (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2353#define MX53_PAD_GPIO_8__CCM_PLL3_BYP (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
2354#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2 (_MX53_PAD_GPIO_16__ESAI1_TX3_RX2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2355#define MX53_PAD_GPIO_16__GPIO7_11 (_MX53_PAD_GPIO_16__GPIO7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
2356#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT (_MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
2357#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 (_MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2358#define MX53_PAD_GPIO_16__SPDIF_IN1 (_MX53_PAD_GPIO_16__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2359#define MX53_PAD_GPIO_16__I2C3_SDA (_MX53_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
2360#define MX53_PAD_GPIO_16__SJC_DE_B (_MX53_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
2361#define MX53_PAD_GPIO_17__ESAI1_TX0 (_MX53_PAD_GPIO_17__ESAI1_TX0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2362#define MX53_PAD_GPIO_17__GPIO7_12 (_MX53_PAD_GPIO_17__GPIO7_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
2363#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 (_MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
2364#define MX53_PAD_GPIO_17__GPC_PMIC_RDY (_MX53_PAD_GPIO_17__GPC_PMIC_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
2365#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG (_MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
2366#define MX53_PAD_GPIO_17__SPDIF_OUT1 (_MX53_PAD_GPIO_17__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2367#define MX53_PAD_GPIO_17__IPU_SNOOP2 (_MX53_PAD_GPIO_17__IPU_SNOOP2 | MUX_PAD_CTRL(NO_PAD_CTRL))
2368#define MX53_PAD_GPIO_17__SJC_JTAG_ACT (_MX53_PAD_GPIO_17__SJC_JTAG_ACT | MUX_PAD_CTRL(NO_PAD_CTRL))
2369#define MX53_PAD_GPIO_18__ESAI1_TX1 (_MX53_PAD_GPIO_18__ESAI1_TX1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2370#define MX53_PAD_GPIO_18__GPIO7_13 (_MX53_PAD_GPIO_18__GPIO7_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
2371#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 (_MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
2372#define MX53_PAD_GPIO_18__OWIRE_LINE (_MX53_PAD_GPIO_18__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
2373#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG (_MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG | MUX_PAD_CTRL(NO_PAD_CTRL))
2374#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK (_MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
2375#define MX53_PAD_GPIO_18__ESDHC1_LCTL (_MX53_PAD_GPIO_18__ESDHC1_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
2376#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST (_MX53_PAD_GPIO_18__SRC_SYSTEM_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
324 2377
325#endif /* __MACH_IOMUX_MX53_H__ */ 2378#endif /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 15d59510f59..bf28df0d58b 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -46,12 +46,12 @@
46 * - setups the iomux according to the configuration 46 * - setups the iomux according to the configuration
47 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib 47 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
48 */ 48 */
49int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label); 49int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label);
50/* 50/*
51 * setups mutliple pins 51 * setups mutliple pins
52 * convenient way to call the above function with tables 52 * convenient way to call the above function with tables
53 */ 53 */
54int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, 54int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
55 const char *label); 55 const char *label);
56 56
57/* 57/*
@@ -60,12 +60,12 @@ int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
60 * - frees the GPIO if the pin was configured as GPIO 60 * - frees the GPIO if the pin was configured as GPIO
61 * - DOES NOT reconfigure the IOMUX in its reset state 61 * - DOES NOT reconfigure the IOMUX in its reset state
62 */ 62 */
63void mxc_iomux_release_pin(const unsigned int pin_mode); 63void mxc_iomux_release_pin(unsigned int pin_mode);
64/* 64/*
65 * releases multiple pins 65 * releases multiple pins
66 * convenvient way to call the above function with tables 66 * convenvient way to call the above function with tables
67 */ 67 */
68void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count); 68void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
69 69
70#define MUX_SIDE_AP (0) 70#define MUX_SIDE_AP (0)
71#define MUX_SIDE_SP (1) 71#define MUX_SIDE_SP (1)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index 884f5753f27..c07d30210c5 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -100,4 +100,6 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
100 const char *label); 100 const char *label);
101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); 101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
102 102
103extern int __init imx_iomuxv1_init(void __iomem *base, int numports);
104
103#endif /* __MACH_IOMUX_V1_H__ */ 105#endif /* __MACH_IOMUX_V1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index ba65c9231a7..a3d930d3e65 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -23,17 +23,17 @@
23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
24 24
25/* these are ordered by size to support multi-SoC kernels */ 25/* these are ordered by size to support multi-SoC kernels */
26#if defined CONFIG_ARCH_MX53 26#if defined CONFIG_SOC_IMX53
27#define MXC_GPIO_IRQS (32 * 7) 27#define MXC_GPIO_IRQS (32 * 7)
28#elif defined CONFIG_ARCH_MX2 28#elif defined CONFIG_ARCH_MX2
29#define MXC_GPIO_IRQS (32 * 6) 29#define MXC_GPIO_IRQS (32 * 6)
30#elif defined CONFIG_ARCH_MX50 30#elif defined CONFIG_SOC_IMX50
31#define MXC_GPIO_IRQS (32 * 6) 31#define MXC_GPIO_IRQS (32 * 6)
32#elif defined CONFIG_ARCH_MX1 32#elif defined CONFIG_ARCH_MX1
33#define MXC_GPIO_IRQS (32 * 4) 33#define MXC_GPIO_IRQS (32 * 4)
34#elif defined CONFIG_ARCH_MX25 34#elif defined CONFIG_ARCH_MX25
35#define MXC_GPIO_IRQS (32 * 4) 35#define MXC_GPIO_IRQS (32 * 4)
36#elif defined CONFIG_ARCH_MX51 36#elif defined CONFIG_SOC_IMX51
37#define MXC_GPIO_IRQS (32 * 4) 37#define MXC_GPIO_IRQS (32 * 4)
38#elif defined CONFIG_ARCH_MXC91231 38#elif defined CONFIG_ARCH_MXC91231
39#define MXC_GPIO_IRQS (32 * 4) 39#define MXC_GPIO_IRQS (32 * 4)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 75d96214b83..97b19e7800b 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -54,13 +54,13 @@
54#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) 54#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
55#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) 55#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
56#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) 56#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
57#define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) 57#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
58#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) 58#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
59#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) 59#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
60#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) 60#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
61#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) 61#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
62#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) 62#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
63#define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) 63#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
64#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) 64#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
65#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) 65#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
66#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) 66#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
@@ -89,7 +89,7 @@
89#define MX1_GPIO_INT_PORTA 11 89#define MX1_GPIO_INT_PORTA 11
90#define MX1_GPIO_INT_PORTB 12 90#define MX1_GPIO_INT_PORTB 12
91#define MX1_GPIO_INT_PORTC 13 91#define MX1_GPIO_INT_PORTC 13
92#define MX1_LCDC_INT 14 92#define MX1_INT_LCDC 14
93#define MX1_SIM_INT 15 93#define MX1_SIM_INT 15
94#define MX1_SIM_DATA_INT 16 94#define MX1_SIM_DATA_INT 16
95#define MX1_RTC_INT 17 95#define MX1_RTC_INT 17
@@ -112,7 +112,8 @@
112#define MX1_PWM_INT 34 112#define MX1_PWM_INT 34
113#define MX1_SDHC_INT 35 113#define MX1_SDHC_INT 35
114#define MX1_INT_I2C 39 114#define MX1_INT_I2C 39
115#define MX1_CSPI_INT 41 115#define MX1_INT_CSPI2 40
116#define MX1_INT_CSPI1 41
116#define MX1_SSI_TX_INT 42 117#define MX1_SSI_TX_INT 42
117#define MX1_SSI_TX_ERR_INT 43 118#define MX1_SSI_TX_ERR_INT 43
118#define MX1_SSI_RX_INT 44 119#define MX1_SSI_RX_INT 44
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index d7a8e52181e..ace17864575 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -79,7 +79,7 @@
79#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) 79#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
80#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) 80#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
81#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) 81#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
82#define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) 82#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
83#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) 83#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
84#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) 84#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
85#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) 85#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 04c7a26b1f2..7e072637eef 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -103,7 +103,7 @@ extern unsigned int __mxc_cpu_type;
103# define cpu_is_mx27() (0) 103# define cpu_is_mx27() (0)
104#endif 104#endif
105 105
106#ifdef CONFIG_ARCH_MX31 106#ifdef CONFIG_SOC_IMX31
107# ifdef mxc_cpu_type 107# ifdef mxc_cpu_type
108# undef mxc_cpu_type 108# undef mxc_cpu_type
109# define mxc_cpu_type __mxc_cpu_type 109# define mxc_cpu_type __mxc_cpu_type
@@ -115,7 +115,7 @@ extern unsigned int __mxc_cpu_type;
115# define cpu_is_mx31() (0) 115# define cpu_is_mx31() (0)
116#endif 116#endif
117 117
118#ifdef CONFIG_ARCH_MX35 118#ifdef CONFIG_SOC_IMX35
119# ifdef mxc_cpu_type 119# ifdef mxc_cpu_type
120# undef mxc_cpu_type 120# undef mxc_cpu_type
121# define mxc_cpu_type __mxc_cpu_type 121# define mxc_cpu_type __mxc_cpu_type
@@ -127,7 +127,7 @@ extern unsigned int __mxc_cpu_type;
127# define cpu_is_mx35() (0) 127# define cpu_is_mx35() (0)
128#endif 128#endif
129 129
130#ifdef CONFIG_ARCH_MX50 130#ifdef CONFIG_SOC_IMX50
131# ifdef mxc_cpu_type 131# ifdef mxc_cpu_type
132# undef mxc_cpu_type 132# undef mxc_cpu_type
133# define mxc_cpu_type __mxc_cpu_type 133# define mxc_cpu_type __mxc_cpu_type
@@ -139,7 +139,7 @@ extern unsigned int __mxc_cpu_type;
139# define cpu_is_mx50() (0) 139# define cpu_is_mx50() (0)
140#endif 140#endif
141 141
142#ifdef CONFIG_ARCH_MX51 142#ifdef CONFIG_SOC_IMX51
143# ifdef mxc_cpu_type 143# ifdef mxc_cpu_type
144# undef mxc_cpu_type 144# undef mxc_cpu_type
145# define mxc_cpu_type __mxc_cpu_type 145# define mxc_cpu_type __mxc_cpu_type
@@ -151,7 +151,7 @@ extern unsigned int __mxc_cpu_type;
151# define cpu_is_mx51() (0) 151# define cpu_is_mx51() (0)
152#endif 152#endif
153 153
154#ifdef CONFIG_ARCH_MX53 154#ifdef CONFIG_SOC_IMX53
155# ifdef mxc_cpu_type 155# ifdef mxc_cpu_type
156# undef mxc_cpu_type 156# undef mxc_cpu_type
157# define mxc_cpu_type __mxc_cpu_type 157# define mxc_cpu_type __mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index a523a407929..2c159dc2398 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -44,11 +44,14 @@ struct mxc_usbh_platform_data {
44 int (*exit)(struct platform_device *pdev); 44 int (*exit)(struct platform_device *pdev);
45 45
46 unsigned int portsc; 46 unsigned int portsc;
47 unsigned int flags;
48 struct otg_transceiver *otg; 47 struct otg_transceiver *otg;
49}; 48};
50 49
51int mxc_initialize_usb_hw(int port, unsigned int flags); 50int mx51_initialize_usb_hw(int port, unsigned int flags);
51int mx25_initialize_usb_hw(int port, unsigned int flags);
52int mx31_initialize_usb_hw(int port, unsigned int flags);
53int mx35_initialize_usb_hw(int port, unsigned int flags);
54int mx27_initialize_usb_hw(int port, unsigned int flags);
52 55
53#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ 56#endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */
54 57
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h
index 96b6ab4c40c..f9161c96d7b 100644
--- a/arch/arm/plat-mxc/include/mach/ulpi.h
+++ b/arch/arm/plat-mxc/include/mach/ulpi.h
@@ -1,6 +1,15 @@
1#ifndef __MACH_ULPI_H 1#ifndef __MACH_ULPI_H
2#define __MACH_ULPI_H 2#define __MACH_ULPI_H
3 3
4#ifdef CONFIG_USB_ULPI
5struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags);
6#else
7static inline struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags)
8{
9 return NULL;
10}
11#endif
12
4extern struct otg_io_access_ops mxc_ulpi_access_ops; 13extern struct otg_io_access_ops mxc_ulpi_access_ops;
5 14
6#endif /* __MACH_ULPI_H */ 15#endif /* __MACH_ULPI_H */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index ff469c4f1d7..4864b0afd44 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -62,6 +62,7 @@ static inline void flush(void)
62#define MX2X_UART1_BASE_ADDR 0x1000a000 62#define MX2X_UART1_BASE_ADDR 0x1000a000
63#define MX3X_UART1_BASE_ADDR 0x43F90000 63#define MX3X_UART1_BASE_ADDR 0x43F90000
64#define MX3X_UART2_BASE_ADDR 0x43F94000 64#define MX3X_UART2_BASE_ADDR 0x43F94000
65#define MX3X_UART5_BASE_ADDR 0x43FB4000
65#define MX51_UART1_BASE_ADDR 0x73fbc000 66#define MX51_UART1_BASE_ADDR 0x73fbc000
66#define MX50_UART1_BASE_ADDR 0x53fbc000 67#define MX50_UART1_BASE_ADDR 0x53fbc000
67#define MX53_UART1_BASE_ADDR 0x53fbc000 68#define MX53_UART1_BASE_ADDR 0x53fbc000
@@ -83,6 +84,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
83 case MACH_TYPE_MX21ADS: 84 case MACH_TYPE_MX21ADS:
84 case MACH_TYPE_PCA100: 85 case MACH_TYPE_PCA100:
85 case MACH_TYPE_MXT_TD60: 86 case MACH_TYPE_MXT_TD60:
87 case MACH_TYPE_IMX27IPCAM:
86 uart_base = MX2X_UART1_BASE_ADDR; 88 uart_base = MX2X_UART1_BASE_ADDR;
87 break; 89 break;
88 case MACH_TYPE_MX31LITE: 90 case MACH_TYPE_MX31LITE:
@@ -101,6 +103,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
101 case MACH_TYPE_MAGX_ZN5: 103 case MACH_TYPE_MAGX_ZN5:
102 uart_base = MX3X_UART2_BASE_ADDR; 104 uart_base = MX3X_UART2_BASE_ADDR;
103 break; 105 break;
106 case MACH_TYPE_BUG:
107 uart_base = MX3X_UART5_BASE_ADDR;
108 break;
104 case MACH_TYPE_MX51_BABBAGE: 109 case MACH_TYPE_MX51_BABBAGE:
105 case MACH_TYPE_EUKREA_CPUIMX51SD: 110 case MACH_TYPE_EUKREA_CPUIMX51SD:
106 case MACH_TYPE_MX51_3DS: 111 case MACH_TYPE_MX51_3DS:
@@ -110,6 +115,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
110 uart_base = MX50_UART1_BASE_ADDR; 115 uart_base = MX50_UART1_BASE_ADDR;
111 break; 116 break;
112 case MACH_TYPE_MX53_EVK: 117 case MACH_TYPE_MX53_EVK:
118 case MACH_TYPE_MX53_LOCO:
119 case MACH_TYPE_MX53_SMD:
113 uart_base = MX53_UART1_BASE_ADDR; 120 uart_base = MX53_UART1_BASE_ADDR;
114 break; 121 break;
115 default: 122 default:
diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c
index 960a02cbcba..3238c10d4e0 100644
--- a/arch/arm/plat-mxc/iomux-v1.c
+++ b/arch/arm/plat-mxc/iomux-v1.c
@@ -211,28 +211,10 @@ void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
211} 211}
212EXPORT_SYMBOL(mxc_gpio_release_multiple_pins); 212EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
213 213
214static int imx_iomuxv1_init(void) 214int __init imx_iomuxv1_init(void __iomem *base, int numports)
215{ 215{
216#ifdef CONFIG_ARCH_MX1 216 imx_iomuxv1_baseaddr = base;
217 if (cpu_is_mx1()) { 217 imx_iomuxv1_numports = numports;
218 imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR);
219 imx_iomuxv1_numports = MX1_NUM_GPIO_PORT;
220 } else
221#endif
222#ifdef CONFIG_MACH_MX21
223 if (cpu_is_mx21()) {
224 imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR);
225 imx_iomuxv1_numports = MX21_NUM_GPIO_PORT;
226 } else
227#endif
228#ifdef CONFIG_MACH_MX27
229 if (cpu_is_mx27()) {
230 imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR);
231 imx_iomuxv1_numports = MX27_NUM_GPIO_PORT;
232 } else
233#endif
234 return -ENODEV;
235 218
236 return 0; 219 return 0;
237} 220}
238pure_initcall(imx_iomuxv1_init);
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
index 582c6dfaba4..477e45bea1b 100644
--- a/arch/arm/plat-mxc/ulpi.c
+++ b/arch/arm/plat-mxc/ulpi.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/usb/otg.h> 24#include <linux/usb/otg.h>
25#include <linux/usb/ulpi.h>
25 26
26#include <mach/ulpi.h> 27#include <mach/ulpi.h>
27 28
@@ -111,3 +112,7 @@ struct otg_io_access_ops mxc_ulpi_access_ops = {
111}; 112};
112EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops); 113EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
113 114
115struct otg_transceiver *imx_otg_ulpi_create(unsigned int flags)
116{
117 return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
118}