diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-02-06 16:01:39 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-02-06 16:01:39 -0500 |
commit | f6510ec5a96d07897a109ad8919c6af5e9b3f4bc (patch) | |
tree | e882156ce1135a63310cff4d4c0a7a799c07c9a6 | |
parent | 6f5a55f1a6c5abee15a0e878e5c74d9f1569b8b0 (diff) | |
parent | 93533c291a0af78ca57115fc44d2e6c4c9517cd2 (diff) |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: Fix leak of relocs along do_execbuffer error path
drm/i915: slow acpi_lid_open() causes flickering - V2
drm/i915: Disable SR when more than one pipe is enabled
drm/i915: page flip support for Ironlake
drm/i915: Fix the incorrect DMI string for Samsung SX20S laptop
drm/i915: Add support for SDVO composite TV
drm/i915: don't trigger ironlake vblank interrupt at irq install
drm/i915: handle non-flip pending case when unpinning the scanout buffer
drm/i915: Fix the device info of Pineview
drm/i915: enable vblank interrupt on ironlake
drm/i915: Prevent use of uninitialized pointers along error path.
drm/i915: disable hotplug detect before Ironlake CRT detect
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 42 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_crt.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 33 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_lvds.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_sdvo.c | 8 |
7 files changed, 91 insertions, 19 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 46d88965852..ecac882e1d5 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -120,7 +120,7 @@ const static struct intel_device_info intel_gm45_info = { | |||
120 | 120 | ||
121 | const static struct intel_device_info intel_pineview_info = { | 121 | const static struct intel_device_info intel_pineview_info = { |
122 | .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1, | 122 | .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1, |
123 | .has_pipe_cxsr = 1, | 123 | .need_gfx_hws = 1, |
124 | .has_hotplug = 1, | 124 | .has_hotplug = 1, |
125 | }; | 125 | }; |
126 | 126 | ||
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index dda787aafcc..b4c8c023068 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -3564,6 +3564,9 @@ i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, | |||
3564 | uint32_t reloc_count = 0, i; | 3564 | uint32_t reloc_count = 0, i; |
3565 | int ret = 0; | 3565 | int ret = 0; |
3566 | 3566 | ||
3567 | if (relocs == NULL) | ||
3568 | return 0; | ||
3569 | |||
3567 | for (i = 0; i < buffer_count; i++) { | 3570 | for (i = 0; i < buffer_count; i++) { |
3568 | struct drm_i915_gem_relocation_entry __user *user_relocs; | 3571 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
3569 | int unwritten; | 3572 | int unwritten; |
@@ -3653,7 +3656,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |||
3653 | struct drm_gem_object *batch_obj; | 3656 | struct drm_gem_object *batch_obj; |
3654 | struct drm_i915_gem_object *obj_priv; | 3657 | struct drm_i915_gem_object *obj_priv; |
3655 | struct drm_clip_rect *cliprects = NULL; | 3658 | struct drm_clip_rect *cliprects = NULL; |
3656 | struct drm_i915_gem_relocation_entry *relocs; | 3659 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
3657 | int ret = 0, ret2, i, pinned = 0; | 3660 | int ret = 0, ret2, i, pinned = 0; |
3658 | uint64_t exec_offset; | 3661 | uint64_t exec_offset; |
3659 | uint32_t seqno, flush_domains, reloc_index; | 3662 | uint32_t seqno, flush_domains, reloc_index; |
@@ -3722,6 +3725,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |||
3722 | if (object_list[i] == NULL) { | 3725 | if (object_list[i] == NULL) { |
3723 | DRM_ERROR("Invalid object handle %d at index %d\n", | 3726 | DRM_ERROR("Invalid object handle %d at index %d\n", |
3724 | exec_list[i].handle, i); | 3727 | exec_list[i].handle, i); |
3728 | /* prevent error path from reading uninitialized data */ | ||
3729 | args->buffer_count = i + 1; | ||
3725 | ret = -EBADF; | 3730 | ret = -EBADF; |
3726 | goto err; | 3731 | goto err; |
3727 | } | 3732 | } |
@@ -3730,6 +3735,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, | |||
3730 | if (obj_priv->in_execbuffer) { | 3735 | if (obj_priv->in_execbuffer) { |
3731 | DRM_ERROR("Object %p appears more than once in object list\n", | 3736 | DRM_ERROR("Object %p appears more than once in object list\n", |
3732 | object_list[i]); | 3737 | object_list[i]); |
3738 | /* prevent error path from reading uninitialized data */ | ||
3739 | args->buffer_count = i + 1; | ||
3733 | ret = -EBADF; | 3740 | ret = -EBADF; |
3734 | goto err; | 3741 | goto err; |
3735 | } | 3742 | } |
@@ -3926,6 +3933,7 @@ err: | |||
3926 | 3933 | ||
3927 | mutex_unlock(&dev->struct_mutex); | 3934 | mutex_unlock(&dev->struct_mutex); |
3928 | 3935 | ||
3936 | pre_mutex_err: | ||
3929 | /* Copy the updated relocations out regardless of current error | 3937 | /* Copy the updated relocations out regardless of current error |
3930 | * state. Failure to update the relocs would mean that the next | 3938 | * state. Failure to update the relocs would mean that the next |
3931 | * time userland calls execbuf, it would do so with presumed offset | 3939 | * time userland calls execbuf, it would do so with presumed offset |
@@ -3940,7 +3948,6 @@ err: | |||
3940 | ret = ret2; | 3948 | ret = ret2; |
3941 | } | 3949 | } |
3942 | 3950 | ||
3943 | pre_mutex_err: | ||
3944 | drm_free_large(object_list); | 3951 | drm_free_large(object_list); |
3945 | kfree(cliprects); | 3952 | kfree(cliprects); |
3946 | 3953 | ||
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 89a071a3e6f..50ddf4a95c5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -309,6 +309,22 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev) | |||
309 | if (de_iir & DE_GSE) | 309 | if (de_iir & DE_GSE) |
310 | ironlake_opregion_gse_intr(dev); | 310 | ironlake_opregion_gse_intr(dev); |
311 | 311 | ||
312 | if (de_iir & DE_PLANEA_FLIP_DONE) | ||
313 | intel_prepare_page_flip(dev, 0); | ||
314 | |||
315 | if (de_iir & DE_PLANEB_FLIP_DONE) | ||
316 | intel_prepare_page_flip(dev, 1); | ||
317 | |||
318 | if (de_iir & DE_PIPEA_VBLANK) { | ||
319 | drm_handle_vblank(dev, 0); | ||
320 | intel_finish_page_flip(dev, 0); | ||
321 | } | ||
322 | |||
323 | if (de_iir & DE_PIPEB_VBLANK) { | ||
324 | drm_handle_vblank(dev, 1); | ||
325 | intel_finish_page_flip(dev, 1); | ||
326 | } | ||
327 | |||
312 | /* check event from PCH */ | 328 | /* check event from PCH */ |
313 | if ((de_iir & DE_PCH_EVENT) && | 329 | if ((de_iir & DE_PCH_EVENT) && |
314 | (pch_iir & SDE_HOTPLUG_MASK)) { | 330 | (pch_iir & SDE_HOTPLUG_MASK)) { |
@@ -844,11 +860,11 @@ int i915_enable_vblank(struct drm_device *dev, int pipe) | |||
844 | if (!(pipeconf & PIPEACONF_ENABLE)) | 860 | if (!(pipeconf & PIPEACONF_ENABLE)) |
845 | return -EINVAL; | 861 | return -EINVAL; |
846 | 862 | ||
847 | if (IS_IRONLAKE(dev)) | ||
848 | return 0; | ||
849 | |||
850 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | 863 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
851 | if (IS_I965G(dev)) | 864 | if (IS_IRONLAKE(dev)) |
865 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | ||
866 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | ||
867 | else if (IS_I965G(dev)) | ||
852 | i915_enable_pipestat(dev_priv, pipe, | 868 | i915_enable_pipestat(dev_priv, pipe, |
853 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | 869 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
854 | else | 870 | else |
@@ -866,13 +882,14 @@ void i915_disable_vblank(struct drm_device *dev, int pipe) | |||
866 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 882 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
867 | unsigned long irqflags; | 883 | unsigned long irqflags; |
868 | 884 | ||
869 | if (IS_IRONLAKE(dev)) | ||
870 | return; | ||
871 | |||
872 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | 885 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
873 | i915_disable_pipestat(dev_priv, pipe, | 886 | if (IS_IRONLAKE(dev)) |
874 | PIPE_VBLANK_INTERRUPT_ENABLE | | 887 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
875 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | 888 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
889 | else | ||
890 | i915_disable_pipestat(dev_priv, pipe, | ||
891 | PIPE_VBLANK_INTERRUPT_ENABLE | | ||
892 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | ||
876 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | 893 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
877 | } | 894 | } |
878 | 895 | ||
@@ -1015,13 +1032,14 @@ static int ironlake_irq_postinstall(struct drm_device *dev) | |||
1015 | { | 1032 | { |
1016 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 1033 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
1017 | /* enable kind of interrupts always enabled */ | 1034 | /* enable kind of interrupts always enabled */ |
1018 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT; | 1035 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1036 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | ||
1019 | u32 render_mask = GT_USER_INTERRUPT; | 1037 | u32 render_mask = GT_USER_INTERRUPT; |
1020 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | | 1038 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
1021 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | 1039 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; |
1022 | 1040 | ||
1023 | dev_priv->irq_mask_reg = ~display_mask; | 1041 | dev_priv->irq_mask_reg = ~display_mask; |
1024 | dev_priv->de_irq_enable_reg = display_mask; | 1042 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; |
1025 | 1043 | ||
1026 | /* should always can generate irq */ | 1044 | /* should always can generate irq */ |
1027 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | 1045 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index ddefc871edf..79dd4026586 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c | |||
@@ -157,6 +157,9 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) | |||
157 | adpa = I915_READ(PCH_ADPA); | 157 | adpa = I915_READ(PCH_ADPA); |
158 | 158 | ||
159 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; | 159 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
160 | /* disable HPD first */ | ||
161 | I915_WRITE(PCH_ADPA, adpa); | ||
162 | (void)I915_READ(PCH_ADPA); | ||
160 | 163 | ||
161 | adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | | 164 | adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | |
162 | ADPA_CRT_HOTPLUG_WARMUP_10MS | | 165 | ADPA_CRT_HOTPLUG_WARMUP_10MS | |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 45da78ef4a9..12775df1bbf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1638,6 +1638,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
1638 | case DRM_MODE_DPMS_OFF: | 1638 | case DRM_MODE_DPMS_OFF: |
1639 | DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); | 1639 | DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); |
1640 | 1640 | ||
1641 | drm_vblank_off(dev, pipe); | ||
1641 | /* Disable display plane */ | 1642 | /* Disable display plane */ |
1642 | temp = I915_READ(dspcntr_reg); | 1643 | temp = I915_READ(dspcntr_reg); |
1643 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | 1644 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { |
@@ -2519,6 +2520,10 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock, | |||
2519 | sr_entries = roundup(sr_entries / cacheline_size, 1); | 2520 | sr_entries = roundup(sr_entries / cacheline_size, 1); |
2520 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); | 2521 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
2521 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | 2522 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
2523 | } else { | ||
2524 | /* Turn off self refresh if both pipes are enabled */ | ||
2525 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | ||
2526 | & ~FW_BLC_SELF_EN); | ||
2522 | } | 2527 | } |
2523 | 2528 | ||
2524 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", | 2529 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", |
@@ -2562,6 +2567,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock, | |||
2562 | srwm = 1; | 2567 | srwm = 1; |
2563 | srwm &= 0x3f; | 2568 | srwm &= 0x3f; |
2564 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | 2569 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
2570 | } else { | ||
2571 | /* Turn off self refresh if both pipes are enabled */ | ||
2572 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | ||
2573 | & ~FW_BLC_SELF_EN); | ||
2565 | } | 2574 | } |
2566 | 2575 | ||
2567 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | 2576 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
@@ -2630,6 +2639,10 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, | |||
2630 | if (srwm < 0) | 2639 | if (srwm < 0) |
2631 | srwm = 1; | 2640 | srwm = 1; |
2632 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); | 2641 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); |
2642 | } else { | ||
2643 | /* Turn off self refresh if both pipes are enabled */ | ||
2644 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | ||
2645 | & ~FW_BLC_SELF_EN); | ||
2633 | } | 2646 | } |
2634 | 2647 | ||
2635 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | 2648 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
@@ -3984,6 +3997,12 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe) | |||
3984 | spin_lock_irqsave(&dev->event_lock, flags); | 3997 | spin_lock_irqsave(&dev->event_lock, flags); |
3985 | work = intel_crtc->unpin_work; | 3998 | work = intel_crtc->unpin_work; |
3986 | if (work == NULL || !work->pending) { | 3999 | if (work == NULL || !work->pending) { |
4000 | if (work && !work->pending) { | ||
4001 | obj_priv = work->obj->driver_private; | ||
4002 | DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n", | ||
4003 | obj_priv, | ||
4004 | atomic_read(&obj_priv->pending_flip)); | ||
4005 | } | ||
3987 | spin_unlock_irqrestore(&dev->event_lock, flags); | 4006 | spin_unlock_irqrestore(&dev->event_lock, flags); |
3988 | return; | 4007 | return; |
3989 | } | 4008 | } |
@@ -4005,7 +4024,10 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe) | |||
4005 | spin_unlock_irqrestore(&dev->event_lock, flags); | 4024 | spin_unlock_irqrestore(&dev->event_lock, flags); |
4006 | 4025 | ||
4007 | obj_priv = work->obj->driver_private; | 4026 | obj_priv = work->obj->driver_private; |
4008 | if (atomic_dec_and_test(&obj_priv->pending_flip)) | 4027 | |
4028 | /* Initial scanout buffer will have a 0 pending flip count */ | ||
4029 | if ((atomic_read(&obj_priv->pending_flip) == 0) || | ||
4030 | atomic_dec_and_test(&obj_priv->pending_flip)) | ||
4009 | DRM_WAKEUP(&dev_priv->pending_flip_queue); | 4031 | DRM_WAKEUP(&dev_priv->pending_flip_queue); |
4010 | schedule_work(&work->work); | 4032 | schedule_work(&work->work); |
4011 | } | 4033 | } |
@@ -4018,8 +4040,11 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane) | |||
4018 | unsigned long flags; | 4040 | unsigned long flags; |
4019 | 4041 | ||
4020 | spin_lock_irqsave(&dev->event_lock, flags); | 4042 | spin_lock_irqsave(&dev->event_lock, flags); |
4021 | if (intel_crtc->unpin_work) | 4043 | if (intel_crtc->unpin_work) { |
4022 | intel_crtc->unpin_work->pending = 1; | 4044 | intel_crtc->unpin_work->pending = 1; |
4045 | } else { | ||
4046 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | ||
4047 | } | ||
4023 | spin_unlock_irqrestore(&dev->event_lock, flags); | 4048 | spin_unlock_irqrestore(&dev->event_lock, flags); |
4024 | } | 4049 | } |
4025 | 4050 | ||
@@ -4053,6 +4078,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, | |||
4053 | /* We borrow the event spin lock for protecting unpin_work */ | 4078 | /* We borrow the event spin lock for protecting unpin_work */ |
4054 | spin_lock_irqsave(&dev->event_lock, flags); | 4079 | spin_lock_irqsave(&dev->event_lock, flags); |
4055 | if (intel_crtc->unpin_work) { | 4080 | if (intel_crtc->unpin_work) { |
4081 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | ||
4056 | spin_unlock_irqrestore(&dev->event_lock, flags); | 4082 | spin_unlock_irqrestore(&dev->event_lock, flags); |
4057 | kfree(work); | 4083 | kfree(work); |
4058 | mutex_unlock(&dev->struct_mutex); | 4084 | mutex_unlock(&dev->struct_mutex); |
@@ -4066,7 +4092,10 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, | |||
4066 | 4092 | ||
4067 | ret = intel_pin_and_fence_fb_obj(dev, obj); | 4093 | ret = intel_pin_and_fence_fb_obj(dev, obj); |
4068 | if (ret != 0) { | 4094 | if (ret != 0) { |
4095 | DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n", | ||
4096 | obj->driver_private); | ||
4069 | kfree(work); | 4097 | kfree(work); |
4098 | intel_crtc->unpin_work = NULL; | ||
4070 | mutex_unlock(&dev->struct_mutex); | 4099 | mutex_unlock(&dev->struct_mutex); |
4071 | return ret; | 4100 | return ret; |
4072 | } | 4101 | } |
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index aa74e59bec6..b1d0acbae4e 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c | |||
@@ -611,7 +611,7 @@ static const struct dmi_system_id bad_lid_status[] = { | |||
611 | { | 611 | { |
612 | .ident = "Samsung SX20S", | 612 | .ident = "Samsung SX20S", |
613 | .matches = { | 613 | .matches = { |
614 | DMI_MATCH(DMI_SYS_VENDOR, "Phoenix Technologies LTD"), | 614 | DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"), |
615 | DMI_MATCH(DMI_BOARD_NAME, "SX20S"), | 615 | DMI_MATCH(DMI_BOARD_NAME, "SX20S"), |
616 | }, | 616 | }, |
617 | }, | 617 | }, |
@@ -623,6 +623,13 @@ static const struct dmi_system_id bad_lid_status[] = { | |||
623 | }, | 623 | }, |
624 | }, | 624 | }, |
625 | { | 625 | { |
626 | .ident = "Aspire 1810T", | ||
627 | .matches = { | ||
628 | DMI_MATCH(DMI_SYS_VENDOR, "Acer"), | ||
629 | DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 1810T"), | ||
630 | }, | ||
631 | }, | ||
632 | { | ||
626 | .ident = "PC-81005", | 633 | .ident = "PC-81005", |
627 | .matches = { | 634 | .matches = { |
628 | DMI_MATCH(DMI_SYS_VENDOR, "MALATA"), | 635 | DMI_MATCH(DMI_SYS_VENDOR, "MALATA"), |
@@ -643,7 +650,7 @@ static enum drm_connector_status intel_lvds_detect(struct drm_connector *connect | |||
643 | { | 650 | { |
644 | enum drm_connector_status status = connector_status_connected; | 651 | enum drm_connector_status status = connector_status_connected; |
645 | 652 | ||
646 | if (!acpi_lid_open() && !dmi_check_system(bad_lid_status)) | 653 | if (!dmi_check_system(bad_lid_status) && !acpi_lid_open()) |
647 | status = connector_status_disconnected; | 654 | status = connector_status_disconnected; |
648 | 655 | ||
649 | return status; | 656 | return status; |
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index eaacfd0920d..82678d30ab0 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c | |||
@@ -2345,6 +2345,14 @@ intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags) | |||
2345 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | 2345 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
2346 | intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | | 2346 | intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
2347 | (1 << INTEL_ANALOG_CLONE_BIT); | 2347 | (1 << INTEL_ANALOG_CLONE_BIT); |
2348 | } else if (flags & SDVO_OUTPUT_CVBS0) { | ||
2349 | |||
2350 | sdvo_priv->controlled_output = SDVO_OUTPUT_CVBS0; | ||
2351 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; | ||
2352 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; | ||
2353 | sdvo_priv->is_tv = true; | ||
2354 | intel_output->needs_tv_clock = true; | ||
2355 | intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; | ||
2348 | } else if (flags & SDVO_OUTPUT_LVDS0) { | 2356 | } else if (flags & SDVO_OUTPUT_LVDS0) { |
2349 | 2357 | ||
2350 | sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0; | 2358 | sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0; |