diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 33 |
1 files changed, 31 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 45da78ef4a9..12775df1bbf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1638,6 +1638,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) | |||
1638 | case DRM_MODE_DPMS_OFF: | 1638 | case DRM_MODE_DPMS_OFF: |
1639 | DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); | 1639 | DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); |
1640 | 1640 | ||
1641 | drm_vblank_off(dev, pipe); | ||
1641 | /* Disable display plane */ | 1642 | /* Disable display plane */ |
1642 | temp = I915_READ(dspcntr_reg); | 1643 | temp = I915_READ(dspcntr_reg); |
1643 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { | 1644 | if ((temp & DISPLAY_PLANE_ENABLE) != 0) { |
@@ -2519,6 +2520,10 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock, | |||
2519 | sr_entries = roundup(sr_entries / cacheline_size, 1); | 2520 | sr_entries = roundup(sr_entries / cacheline_size, 1); |
2520 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); | 2521 | DRM_DEBUG("self-refresh entries: %d\n", sr_entries); |
2521 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | 2522 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
2523 | } else { | ||
2524 | /* Turn off self refresh if both pipes are enabled */ | ||
2525 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | ||
2526 | & ~FW_BLC_SELF_EN); | ||
2522 | } | 2527 | } |
2523 | 2528 | ||
2524 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", | 2529 | DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n", |
@@ -2562,6 +2567,10 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock, | |||
2562 | srwm = 1; | 2567 | srwm = 1; |
2563 | srwm &= 0x3f; | 2568 | srwm &= 0x3f; |
2564 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | 2569 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
2570 | } else { | ||
2571 | /* Turn off self refresh if both pipes are enabled */ | ||
2572 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | ||
2573 | & ~FW_BLC_SELF_EN); | ||
2565 | } | 2574 | } |
2566 | 2575 | ||
2567 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | 2576 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
@@ -2630,6 +2639,10 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock, | |||
2630 | if (srwm < 0) | 2639 | if (srwm < 0) |
2631 | srwm = 1; | 2640 | srwm = 1; |
2632 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); | 2641 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f)); |
2642 | } else { | ||
2643 | /* Turn off self refresh if both pipes are enabled */ | ||
2644 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | ||
2645 | & ~FW_BLC_SELF_EN); | ||
2633 | } | 2646 | } |
2634 | 2647 | ||
2635 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | 2648 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
@@ -3984,6 +3997,12 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe) | |||
3984 | spin_lock_irqsave(&dev->event_lock, flags); | 3997 | spin_lock_irqsave(&dev->event_lock, flags); |
3985 | work = intel_crtc->unpin_work; | 3998 | work = intel_crtc->unpin_work; |
3986 | if (work == NULL || !work->pending) { | 3999 | if (work == NULL || !work->pending) { |
4000 | if (work && !work->pending) { | ||
4001 | obj_priv = work->obj->driver_private; | ||
4002 | DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n", | ||
4003 | obj_priv, | ||
4004 | atomic_read(&obj_priv->pending_flip)); | ||
4005 | } | ||
3987 | spin_unlock_irqrestore(&dev->event_lock, flags); | 4006 | spin_unlock_irqrestore(&dev->event_lock, flags); |
3988 | return; | 4007 | return; |
3989 | } | 4008 | } |
@@ -4005,7 +4024,10 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe) | |||
4005 | spin_unlock_irqrestore(&dev->event_lock, flags); | 4024 | spin_unlock_irqrestore(&dev->event_lock, flags); |
4006 | 4025 | ||
4007 | obj_priv = work->obj->driver_private; | 4026 | obj_priv = work->obj->driver_private; |
4008 | if (atomic_dec_and_test(&obj_priv->pending_flip)) | 4027 | |
4028 | /* Initial scanout buffer will have a 0 pending flip count */ | ||
4029 | if ((atomic_read(&obj_priv->pending_flip) == 0) || | ||
4030 | atomic_dec_and_test(&obj_priv->pending_flip)) | ||
4009 | DRM_WAKEUP(&dev_priv->pending_flip_queue); | 4031 | DRM_WAKEUP(&dev_priv->pending_flip_queue); |
4010 | schedule_work(&work->work); | 4032 | schedule_work(&work->work); |
4011 | } | 4033 | } |
@@ -4018,8 +4040,11 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane) | |||
4018 | unsigned long flags; | 4040 | unsigned long flags; |
4019 | 4041 | ||
4020 | spin_lock_irqsave(&dev->event_lock, flags); | 4042 | spin_lock_irqsave(&dev->event_lock, flags); |
4021 | if (intel_crtc->unpin_work) | 4043 | if (intel_crtc->unpin_work) { |
4022 | intel_crtc->unpin_work->pending = 1; | 4044 | intel_crtc->unpin_work->pending = 1; |
4045 | } else { | ||
4046 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | ||
4047 | } | ||
4023 | spin_unlock_irqrestore(&dev->event_lock, flags); | 4048 | spin_unlock_irqrestore(&dev->event_lock, flags); |
4024 | } | 4049 | } |
4025 | 4050 | ||
@@ -4053,6 +4078,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, | |||
4053 | /* We borrow the event spin lock for protecting unpin_work */ | 4078 | /* We borrow the event spin lock for protecting unpin_work */ |
4054 | spin_lock_irqsave(&dev->event_lock, flags); | 4079 | spin_lock_irqsave(&dev->event_lock, flags); |
4055 | if (intel_crtc->unpin_work) { | 4080 | if (intel_crtc->unpin_work) { |
4081 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | ||
4056 | spin_unlock_irqrestore(&dev->event_lock, flags); | 4082 | spin_unlock_irqrestore(&dev->event_lock, flags); |
4057 | kfree(work); | 4083 | kfree(work); |
4058 | mutex_unlock(&dev->struct_mutex); | 4084 | mutex_unlock(&dev->struct_mutex); |
@@ -4066,7 +4092,10 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, | |||
4066 | 4092 | ||
4067 | ret = intel_pin_and_fence_fb_obj(dev, obj); | 4093 | ret = intel_pin_and_fence_fb_obj(dev, obj); |
4068 | if (ret != 0) { | 4094 | if (ret != 0) { |
4095 | DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n", | ||
4096 | obj->driver_private); | ||
4069 | kfree(work); | 4097 | kfree(work); |
4098 | intel_crtc->unpin_work = NULL; | ||
4070 | mutex_unlock(&dev->struct_mutex); | 4099 | mutex_unlock(&dev->struct_mutex); |
4071 | return ret; | 4100 | return ret; |
4072 | } | 4101 | } |