| Commit message (Collapse) | Author | Age |
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imx6sx pcie has standalone ldo domain, add the power
control routines.
- pcie pm recovery works when imx6sx pcie is used as rc.
- pcie pm recovery works on both rc and ep modes.
- l2 mode had been validated on imx6sx sdb(rc) and
e1000e (ep) environment.
- fastmix and megamix can be turn off and turn on, during
system suspend/resume.
- hw:
- imx6sx sdb board.
- intel e1000e nic
- xhci pcie2usb device
Signed-off-by: Richard Zhu <r65037@freescale.com>
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- add one imx pcie ep simple skeleton driver to demo
the msi trigger capability in imx6 pcie rc/ep validation
system
- in order to avoid the modification of common codes,
force the msi address to be 0x01ff8000
Test howto:
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images
- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000
root@sabresd_6dq:/ #
- RC side(console command and kernel message):
root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
384: 1 0 0 0 PCI-MSI
- EP side(console command and kernel message):
root@sabresd_6dq:/ # memtool 0x1ff8000=0
Writing 32-bit value 0x0 to address 0x01FF8000
- RC side(console command and kernel message):
root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI
384: 2 0 0 0 PCI-MSI
Signed-off-by: Richard Zhu <r65037@freescale.com>
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HW setup:
* Two i.MX6Q SD boards, one is used as PCIe RC, the other
is used as PCIe EP. Connected by 2*mini_PCIe to standard_PCIe
adaptors, 2*PEX cable adaptors, One PCIe cable.
SW setup:
* When build RC image, make sure that
CONFIG_IMX_PCIE=y
# CONFIG_EP_MODE_IN_EP_RC_SYS is not set
# CONFIG_EP_SELF_IO_TEST is not set
CONFIG_RC_MODE_IN_EP_RC_SYS=y
* When build EP image,(enable if you want ep do self IO test):
CONFIG_EP_MODE_IN_EP_RC_SYS=y
CONFIG_EP_SELF_IO_TEST=y
# CONFIG_RC_MODE_IN_EP_RC_SYS is not set
Features:
* Set-up link between RC and EP by their stand-alone
125MHz running internally.
* In EP's system, EP can access the reserved ddr memory
(default address:0x40000000) of PCIe RC's system, by the
interconnection between PCIe EP and PCIe RC.
* add the configuration methods in the EP side, used to
configure the start address and the size of the reserved
RC's memory window.
- cat /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_info
- echo 0x41000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_start_set
- echo 0x800000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_size_set
* provide one example, howto configure the bar# and so on, when
* pcie ep emaluates one memory ram ep device
Throughput:
* To Be fine-tuned.
NOTE:
* boot up EP platform firstly, then boot up RC platform.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Add support for the PCIe port present on the i.MX6 family of controllers.
These use the Synopsis Designware core tied to their own PHY.
Signed-off-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
(cherry picked from commit bb38919ec56e0758c3ae56dfc091dcde1391353e)
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switch to community upstreamed pcie driver.
Revert "ENGR00275213-4 pcie_imx: enable pcie on imx6 platforms"
This reverts commit dce7d25b770086a978d4dd9838c46f5ff52ee135.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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imx6q and imx6dl platforms have one x1 pcie interface,
this patch used to setup the pcie driver for this
interface.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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Exynos5440 has a PCIe controller which can be used as Root Complex.
This driver supports a PCIe controller as Root Complex mode.
Signed-off-by: Surendranath Gurivireddy Balla <suren.reddy@samsung.com>
Signed-off-by: Siva Reddy Kallam <siva.kallam@samsung.com>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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We allow the pci-mvebu driver to be compiled on the Kirkwood platform,
and add the 'marvell,kirkwood-pcie' as a compatible string supported
by the driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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This driver implements the support for the PCIe interfaces on the
Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
cover earlier families of Marvell SoCs, such as Dove, Orion and
Kirkwood.
The driver implements the hw_pci operations needed by the core ARM PCI
code to setup PCI devices and get their corresponding IRQs, and the
pci_ops operations that are used by the PCI core to read/write the
configuration space of PCI devices.
Since the PCIe interfaces of Marvell SoCs are completely separate and
not linked together in a bus, this driver sets up an emulated PCI host
bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
interface.
In addition, this driver enumerates the different PCIe slots, and for
those having a device plugged in, it sets up the necessary address
decoding windows, using the mvebu-mbus driver.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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