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* ENGR00326135 pcie: pcie ep test fail on imx6q sdRichard Zhu2014-08-06
| | | | | | | | | | | Rootcause: doesn't get the correct mem ranges from DT on imx6q after added imx6sx sdb pcie ep/rc validation system support. solution: Remove the imx6sx specification when get the mem ranges from DT. Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit b42f60a06c77448a8a00b961fb8035c58a5ed8a1)
* ENGR00325494 pcie:delay is requried after clks_enRichard Zhu2014-08-05
| | | | | | | | | | | | | - the async reset input need ref clock to sync internally, when the ref clock comes after reset, internal synced reset time is too short , cannot meet the requirement so, ssp_en should be asserted at least 4us after ref clock stable. - align to the community imx pcie driver, add the about 200us delay to make sure that it can allow the pcie clks stabilize, when pcie clks are enabled on imx6q/dl/solo. Signed-off-by: Richard Zhu <r65037@freescale.com> (cherry picked from commit 5d9635c8d92b21bc12753517fa3e9884417b19be)
* ENGR00320021-3 pcie:add the pcie reg dumpRichard Zhu2014-07-09
| | | | | | | add the pcie related gpr/anatop reg dump into pcie driver Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00322021-2 pcie:can't access pcie dbi registerRichard Zhu2014-07-09
| | | | | | | | | | | | | fixed the but that the pcie dbi reg can't be accessed on the 2014.04 version. rootcause: pcie phy test power down is set in 2014.04 version uboot. solution: clear the pcie phy test power down in the kernel pcie driver initialization. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00319416 pcie: random link down issue after warm-rstRichard Zhu2014-06-23
| | | | | | | | | | | | | | | | | There are about 0.02% percentage on some imx6q/dl/solo hw boards, random pcie link down when warm-reset is used. Make sure to clear the ref_ssp_en bit16 of gpr1 before warm-rst, and set ref_ssp_en after the pcie clks are stable to workaround it. rootcause: * gpr regisers wouldn't be reset by warm-rst, while the ref_ssp_en is required to be reset by pcie. (work-around in u-boot) * ref_ssp_en should be set after pcie clks are stable. (work-around in kernel) Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00314581 pcie: enable pcie ep rc on imx6sxRichard Zhu2014-05-26
| | | | | | enable pcie ep rc validation on imx6sx sdb board. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00314570-2 pcie:add pcie power control on imx6sxRichard Zhu2014-05-26
| | | | | | | | | | | | | | | | | | imx6sx pcie has standalone ldo domain, add the power control routines. - pcie pm recovery works when imx6sx pcie is used as rc. - pcie pm recovery works on both rc and ep modes. - l2 mode had been validated on imx6sx sdb(rc) and e1000e (ep) environment. - fastmix and megamix can be turn off and turn on, during system suspend/resume. - hw: - imx6sx sdb board. - intel e1000e nic - xhci pcie2usb device Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00313685-7 of/irq: Create of_irq_parse_and_map_pci() to consolidate arch ↵Grant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | code. commit 16b84e5a505c790538e534ad8dfda9c288691e40 upstream. Several architectures open code effectively the same code block for finding and mapping PCI irqs. This patch consolidates it down to a single function. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c
* ENGR00313685-3 of/irq: simplify args to irq_create_of_mappingGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | commit e6d30ab1e7d1281784672c0fc2ffa385cfb7279e upstream. All the callers of irq_create_of_mapping() pass the contents of a struct of_phandle_args structure to the function. Since all the callers already have an of_phandle_args pointer, why not pass it directly to irq_create_of_mapping()? Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c kernel/irq/irqdomain.c
* ENGR00313685-2 of/irq: Replace of_irq with of_phandle_argsGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | commit 530210c7814e83564c7ca7bca8192515042c0b63 upstream. struct of_irq and struct of_phandle_args are exactly the same structure. This patch makes the kernel use of_phandle_args everywhere. This in itself isn't a big deal, but it makes some follow-on patches simpler. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c include/linux/of_irq.h
* ENGR00313685-1 of/irq: Rename of_irq_map_* functions to of_irq_parse_*Grant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 0c02c8007ea5554d028f99fd3e29fc201fdeeab3 upstream. The OF irq handling code has been overloading the term 'map' to refer to both parsing the data in the device tree and mapping it to the internal linux irq system. This is probably because the device tree does have the concept of an 'interrupt-map' function for translating interrupt references from one node to another, but 'map' is still confusing when the primary purpose of some of the functions are to parse the DT data. This patch renames all the of_irq_map_* functions to of_irq_parse_* which makes it clear that there is a difference between the parsing phase and the mapping phase. Kernel code can make use of just the parsing or just the mapping support as needed by the subsystem. The patch was generated mechanically with a handful of sed commands. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Conflicts: arch/arm/mach-integrator/pci_v3.c arch/mips/pci/pci-rt3883.c drivers/of/irq.c
* ENGR00304676-3: pci: host: imx6: remove gpc operate codeRobin Gong2014-04-16
| | | | | | | remove the code about gpc, since it will be done in gpc driver. That makes driver more clean and better. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00303325-1 pcie: enable pcie on imx6sxRichard Zhu2014-04-16
| | | | | | | | | | Enable pcie on imx6sx 19x19 socs. - imx6sx pcie has its own power domain, add the standalone power control codes for imx6sx pcie. - the pcie ref (100mhz differential clock) is routed out and used by pcie ep on imx6sx pcie. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00298392 pcie: imx pcie ep rc msi demoRichard Zhu2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add one imx pcie ep simple skeleton driver to demo the msi trigger capability in imx6 pcie rc/ep validation system - in order to avoid the modification of common codes, force the msi address to be 0x01ff8000 Test howto: - Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images - EP side(console command and kernel message): root@sabresd_6dq:/ # memtool 0x1ff8000=0 Writing 32-bit value 0x0 to address 0x01FF8000 root@sabresd_6dq:/ # - RC side(console command and kernel message): root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI 384: 1 0 0 0 PCI-MSI - EP side(console command and kernel message): root@sabresd_6dq:/ # memtool 0x1ff8000=0 Writing 32-bit value 0x0 to address 0x01FF8000 - RC side(console command and kernel message): root@sabresd_6dq:/ # cat /proc/interrupts | grep MSI 384: 2 0 0 0 PCI-MSI Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00298389 pcie: let rc can access mem of epRichard Zhu2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - setup one new outbound memory region at rc side, used to let imx6 pcie rc can access the memory of imx6 pcie ep in imx6 pcie rc ep validation system. - set the default address of the ddr memory to be 0x4000_0000 NOTE: - default address 0x4000_0000 of ep side would be accessed in this demo. Test howto: step1: EP side: 1.1: echo 0x40000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/ep_bar0_addr 1.2: memtool -32 0x40000000 4 E Reading 0x4 count starting at address 0x40000000 0x40000000: 6FE9E9F6 7583FBB9 39EAEFEA FBDCFD78 step2: RC side: memtool -32 0x01000000=58D454DA memtool -32 0x01000004=7332095B step3: EP side: memtool -32 0x40000000 4 E Reading 0x4 count starting at address 0x40000000 0x40000000: 58D454DA 7332095B 39EAEFEA FBDCFD78 Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00289889 pcie: make all pcie gpio be optionalRichard Zhu2014-04-16
| | | | | | | make all pcie gpio be optional, since ard board doesn't have pcie reset gpio pin Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00288407 pcie: add pcie ep rc validation systemRichard Zhu2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HW setup: * Two i.MX6Q SD boards, one is used as PCIe RC, the other is used as PCIe EP. Connected by 2*mini_PCIe to standard_PCIe adaptors, 2*PEX cable adaptors, One PCIe cable. SW setup: * When build RC image, make sure that CONFIG_IMX_PCIE=y # CONFIG_EP_MODE_IN_EP_RC_SYS is not set # CONFIG_EP_SELF_IO_TEST is not set CONFIG_RC_MODE_IN_EP_RC_SYS=y * When build EP image,(enable if you want ep do self IO test): CONFIG_EP_MODE_IN_EP_RC_SYS=y CONFIG_EP_SELF_IO_TEST=y # CONFIG_RC_MODE_IN_EP_RC_SYS is not set Features: * Set-up link between RC and EP by their stand-alone 125MHz running internally. * In EP's system, EP can access the reserved ddr memory (default address:0x40000000) of PCIe RC's system, by the interconnection between PCIe EP and PCIe RC. * add the configuration methods in the EP side, used to configure the start address and the size of the reserved RC's memory window. - cat /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_info - echo 0x41000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_start_set - echo 0x800000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_size_set * provide one example, howto configure the bar# and so on, when * pcie ep emaluates one memory ram ep device Throughput: * To Be fine-tuned. NOTE: * boot up EP platform firstly, then boot up RC platform. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00288406 pcie: imx: enable pcie switch supportRichard Zhu2014-04-16
| | | | | | | | | | | Fix the pcie switch no detection issue Root cause why the switch can't be detected before: * The initialization sequence is not properly, 100ms reset should be just issue before ltssm enable. * Lagency INTx mapping is wrong * remove un-correct IO/MEM iATU outbound mapping. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00286487 pci: imx: eanble pcie msi supportRichard Zhu2014-04-16
| | | | | | | | | eanble pcie msi support on imx6 platforms * add check_device api in the msi chip. * add the quirks into pcie_port struct for the deviation from standard routines. Signed-off-by: Richard Zhu <r65037@freescale.com>
* PCI: designware: Add irq_create_mapping()Pratyush Anand2014-04-16
| | | | | | | | | | | Without irq_create_mapping(), the correct IRQ number cannot be provided. In this case, it makes problems such as NULL dereference. Thus, irq_create_mapping() should be added for MSI. Suggested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: designware: Make dw_pcie_rd_own_conf(), etc., staticBjorn Helgaas2014-04-16
| | | | | | | | | | | | | | | The following variables and functions are used only in pcie-designware.c, so make them static: global_io_offset dw_pcie_rd_own_conf() dw_pcie_wr_own_conf() dw_pcie_setup() dw_pcie_scan_bus() dw_pcie_map_irq() Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com>
* PCI: designware: Add header guardsSeungwon Jeon2014-04-16
| | | | | | | | Add header guards to prevent redundant inclusion. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: exynos: Add missing clk_disable_unprepare() on error pathWei Yongjun2014-04-16
| | | | | | | | | Add the missing clk_disable_unprepare() before return from exynos_pcie_probe() in the error handling case. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jg1.han@samsung.com>
* PCI: exynos: Turn off power of phy block when link failedJingoo Han2014-04-16
| | | | | | | | | When link failed, there is no need to turn on phy block. Also, turning on phy block is added, in order to turn on phy block regardless of the default value of phy registers. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: exynos: Add support for MSIJingoo Han2014-04-16
| | | | | | | | | | | | This patch adds support for Message Signaled Interrupt in the Exynos PCIe driver using Synopsys designware PCIe core IP. Signed-off-by: Siva Reddy Kallam <siva.kallam@samsung.com> Signed-off-by: Srikanth T Shivanand <ts.srikanth@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
* PCI: imx6: Probe the PCIe in fs_initcall()Marek Vasut2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | Probe the PCIe driver in fs_initcall() instead of module_init() to assure that pci_assign_unassigned_resources() will be called early. This function is called in dw_pcie_host_init(), which is in turn called from imx6_add_pcie_port(), which is called from imx6_pcie_probe(). If this is not called early, we will hit resource collisions since pcieport driver is then probed way too late. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Cc: Frank Li <lznuaa@gmail.com> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Richard Zhu <r65037@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Sean Cross <xobs@kosagi.com> Cc: Siva Reddy Kallam <siva.kallam@samsung.com> Cc: Srikanth T Shivanand <ts.srikanth@samsung.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Yinghai Lu <yinghai@kernel.org>(cherry picked from commit f216f57ffe6eede3c8a763add65d331e688f8c56)
* PCI: imx6: Remove redundant of_match_ptrSachin Kamat2014-04-16
| | | | | | | | | | | | imx6_pcie_of_match is always compiled in because PCI_IMX6 depends on SOC_IMX6Q, which only supports OF build. Hence of_match_ptr is not required. [bhelgaas: add changelog details from Shawn] Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Cc: Sean Cross <xobs@kosagi.com>(cherry picked from commit 8bcadbe17207aee0df4a1f5cb41371d71bf3e4b0)
* PCI: imx6: Increase link startup timeoutMarek Vasut2014-04-16
| | | | | | | | | | | A longer link startup timeout is required when certain PCI switches are attached to the root complex. This was tested with a Pericom switch and a PLX switch. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>(cherry picked from commit 017f10e1c78e14d48be7a28f2c33a32dae15fee5)
* PCI: imx6: Fix imprecise abort handlerTim Harvey2014-04-16
| | | | | | | | | | | | | | | | An imprecise abort is triggered when a port behind a switch is accessed and no device is present. At enumeration, imprecise aborts are not enabled thus this ends up getting deferred until the kernel has completed init. At that point we must not adjust PC - the handler must do nothing, but a handler must exist. This fixes random crashes that occur right after freeing init. Tested-by: Marek Vasut <marex@denx.de> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Marek Vasut <marex@denx.de>(cherry picked from commit 4ec3ed7f5e91e9325c810dcb995ef5a55e4a79a6)
* PCI: imx6: Remove redundant dev_err() in imx6_pcie_probe()Wei Yongjun2014-04-16
| | | | | | | | | | | There is an error message within devm_ioremap_resource() already, so remove the dev_err() call to avoid redundant error message. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>(cherry picked from commit 9b5cd0948b67e1750498b5ff85267e87d3b4c5b3)
* PCI: imx6: Add support for i.MX6 PCIe controllerSean Cross2014-04-16
| | | | | | | | | | | Add support for the PCIe port present on the i.MX6 family of controllers. These use the Synopsis Designware core tied to their own PHY. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> (cherry picked from commit bb38919ec56e0758c3ae56dfc091dcde1391353e)
* ENGR00288565 Revert "ENGR00275213-4 pcie_imx: enable pcie on imx6 platforms"Richard Zhu2014-04-16
| | | | | | | | switch to community upstreamed pcie driver. Revert "ENGR00275213-4 pcie_imx: enable pcie on imx6 platforms" This reverts commit dce7d25b770086a978d4dd9838c46f5ff52ee135. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00288562 Revert "ENGR00278492 imx: pcie: delay is required after ↵Richard Zhu2014-04-16
| | | | | | | | | | REF_CLK_EN is set" switch to community upstreamed pcie driver. Revert "ENGR00278492 imx: pcie: delay is required after REF_CLK_EN is set" This reverts commit 1976e889408175354a19824375bc5137f43ef14e. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00278492 imx: pcie: delay is required after REF_CLK_EN is setRichard Zhu2014-04-16
| | | | | | | | delay is required after REF_CLK_EN of GPR1 is set. otherwise, system would be hang when access the registers of PCIe RC when the EARLY_PRINTK is not enabled. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00275213-4 pcie_imx: enable pcie on imx6 platformsRichard Zhu2014-04-16
| | | | | | | | imx6q and imx6dl platforms have one x1 pcie interface, this patch used to setup the pcie driver for this interface. Signed-off-by: Richard Zhu <r65037@freescale.com>
* PCI: exynos: Split into Synopsys part and Exynos partJingoo Han2014-04-16
| | | | | | | | | | | | | | | Exynos PCIe IP consists of Synopsys specific part and Exynos specific part. Only core block is a Synopsys Designware part; other parts are Exynos specific. Also, the Synopsys Designware part can be shared with other platforms; thus, it can be split two parts such as Synopsys Designware part and Exynos specific part. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
* pci: Add PCIe driver for Samsung ExynosJingoo Han2014-04-16
| | | | | | | | | | | | | | Exynos5440 has a PCIe controller which can be used as Root Complex. This driver supports a PCIe controller as Root Complex mode. Signed-off-by: Surendranath Gurivireddy Balla <suren.reddy@samsung.com> Signed-off-by: Siva Reddy Kallam <siva.kallam@samsung.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* pci: mvebu: enable driver usage on KirkwoodThomas Petazzoni2014-04-16
| | | | | | | | | | We allow the pci-mvebu driver to be compiled on the Kirkwood platform, and add the 'marvell,kirkwood-pcie' as a compatible string supported by the driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* pci: PCIe driver for Marvell Armada 370/XP systemsThomas Petazzoni2014-04-16
This driver implements the support for the PCIe interfaces on the Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to cover earlier families of Marvell SoCs, such as Dove, Orion and Kirkwood. The driver implements the hw_pci operations needed by the core ARM PCI code to setup PCI devices and get their corresponding IRQs, and the pci_ops operations that are used by the PCI core to read/write the configuration space of PCI devices. Since the PCIe interfaces of Marvell SoCs are completely separate and not linked together in a bus, this driver sets up an emulated PCI host bridge, with one PCI-to-PCI bridge as child for each hardware PCIe interface. In addition, this driver enumerates the different PCIe slots, and for those having a device plugged in, it sets up the necessary address decoding windows, using the mvebu-mbus driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-21 20:20:47 -0400