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Add mega fast domain power off feature in DSM, it can save about
0.72mW power;
If there is any module in Mega/Fast domain enabled as wakeup source,
then Mega/Fast domain's power will be kept on in DSM.
Signed-off-by: Anson Huang <b20788@freescale.com>
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This patch adds support for dynamically calculating the size of all
low power code (suspend, ddr freq change and low power idle). This allows
for easy code changes in the future.
This patch also moves the DDR frequency change code from lower 8K of the memory
allocated for IRAM page table to regular IRAM. With this the lower 8K of the
IRAM page table only contains suspend/resume and low power IDLE code. This
gives a little more flexibility to the cdoe size for suspend/resume and low
power IDLE.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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When switching to page tables in IRAM, we are switching from a cacheable
to non-cacheable page table. Based on recommendation from ARM, we need to
ensure that branch prediction, L1 data nd L2 are disabled when DDR is put
into self-refresh.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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The suspend/resume code needs to save the ARM registers that is used
in the code. The return paths from the suspend code can be different, based
on if an interrupt is pending. So we cannot depend on the kernel code to
restore the registers.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Set DDR/IO to low power mode for i.MX6SX when system enter
DSM mode, it can save ~8mW power(from 25mA lower to 19mA).
Signed-off-by: Anson Huang <b20788@freescale.com>
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Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.
The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.
This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
This makes it possible to create entries for the IRAM code in the IRAM page table.
We need to ensure that both the DDR and IRAM page table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
a. TTBCR.N = 1
This means the 0-2G virtual address space is translated using TTBR0
and 2G-4G is translated using TTBR1.
b. Set TTBCR.PD0 = 1
With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1
Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible.
This commit is cherry-picked:
93ae491d9dbe34a91e2dd5832b02b0f0a390ddbe
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Enable suspend/resume feature for i.mx6sx 17x17 arm2 board,
for dsm mode, as we use dedicated ocram space for low
power function(start from 0x8f8000), but ROM code still
use previous ocram space(0x900000) for checking jump address,
so we need to enable ROMCP of data patch to workaround this
issue.
This patch only enables the suspend/resume function, will
add low power related operation such as DDR IO HZ mode setting
later, as there is still some necessary reference manual missing.
Signed-off-by: Anson Huang <b20788@freescale.com>
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The LDO analog bypass switch is necessary before entering DSM when LDO
is working at digital bypass mode, previous coding logic is incorrect,
fix it.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Support low power mode DSM for i.MX6SL:
1. No need to enable weak 2P5 for i.MX6SL;
2. Need to disconnect VDDHIGH and VDDSNVS in DSM to lower power leakage;
3. Add DDR IO float in DSM to lower DDR power.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Enable DSM code for imx6, the code porting form kernel 3.5.7.So with the patch,
we can suspend imx6q, imx6dl from iram to decrease power number of DDR IO:
save ~15mA@1.5V on imx6qsabresd, but need more ~30us in suspend and resume back.
Signed-off-by: Robin Gong <b38343@freescale.com>
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