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* Added cache /procNamhoon Kim2014-11-03
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* ENGR00242201 imx: Update specific clock code for MX6DLLoren Huang2014-08-05
| | | | | | | | | | -Update the parent of gpu2d_core for mx6dl. -Update the parent of gpu3d_shader and gpu3d_core for mx6dl. -Update the clock of gpu3d_shader and gpu3d_core for mx6dl. The code change is cherry-picked from patch 00e75bcba16d. Signed-off-by: Loren Huang <b02279@freescale.com> (cherry picked from commit 2b335e6232b807d114a5a57e0b5956ab794786a4)
* ENGR00322509-2 ARM:imx6sl:busfreq: Fix incorrect clk_set_parent() call.Ranjani Vaidyanathan2014-07-15
| | | | | | | | | The code incorrectly attempts to set the parent of periph2_clk to periph2_clk2_sel. Fix this by calling the clk_set_parent() function with the correct parameters. Also replace all calls to clk_set_parent() and clk_set_rate() with imx_clk_set_parent() and imx_clk_set_rate() function that prints out error messages in case of failure. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00322509-1 Revert "ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag ↵Ranjani Vaidyanathan2014-07-15
| | | | | | | | | | | | | | | for PLL clocks" The commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154, which added a check to prevent pll rate changes when PLL is enabled, causes incorrect reporting of MMDC clock during low power IDLE. So revert the patch as the code needs to be improved to handle all cases. Revert "ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks" This reverts commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00318063-11: ARM: imx6: add return check for clock callsShawn Guo2014-07-15
| | | | | | | | | | | | | | There are a bunch of clk_enable_prepare, clk_set_parent and clk_set_rate calls in imx6 clock driver's initialization. They are called without retunr check. If there is something going wrong with the calls, they will just fail silently. The patch creates a set of helper functions imx_clk_enable_prepare, imx_clk_set_parent and imx_clk_set_rate, and use them instead from clock initialization to check the return and print error message to tell failures if any. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00322563 ARM:imx6sl:Ensure that the CPU frequency is maintianed at ↵Ranjani Vaidyanathan2014-07-14
| | | | | | | | | | | | | | | 396MHz in low power idle. In low power IDLE mode, CPU needs to be sourced from PLL1 instead of PLL2_PFD0 as PLL2 needs to be in bypass mode to achieve 24MHz DDR frequency. The original code attempts to relock the PLL1 at frequency that is as close as possible to 396MHz, which results in PLL1 at 648MHz and the ARM freq turns out to be 324MHz instead of 396MHz. This causes issues with CPUFREQ as 324MHz is not a frequency listed in the cpufreq table in the device tree. This patch attempts to fix this mis-match and maintains CPU freq at 396MHz in low power idle. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00322272-1: ARM: imx6sx: hide the buggy ldb_di_sel mux from clk APIShawn Guo2014-07-11
| | | | | | | | | | | | | | | | This is a smilar change for imx6sx clock tree as what we did for imx6q with commit 0bec46131d88 (ENGR00318063-8: ARM: imx6q: hide buggy ldb_di_sel from clk API). As the valid procedure of switching ldb_di_sel on imx6sx is not available yet, we hide this buggy mux by looking at the parent selection done by bootloader and register it statically to clock framework, so that switching this buggy mux becomes impossible. Also, since the bit width of ldb_di_sels is 3, we add two "dummy" entries for ldb_di_sels to avoid out-of-bounds error. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: fix shared gate clockShawn Guo2014-07-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | Let's say clock A and B are two gate clocks that share the same register bit in hardware. Therefore they are registered as shared gate clocks with imx_clk_gate2_shared(). In a scenario that only clock A is enabled by clk_enable(A) while B is not used, the shared gate will be unexpectedly disabled in hardware. It happens because clk_enable(A) increments the share_count from 0 to 1, while clock B is unused to clock core, and therefore the core function will just disable B by calling clk->ops->disable() directly. The consequence of that call is share_count is decremented to 0 and the gate is disabled in hardware, even though clock A is still in use. The patch fixes the issue by initializing the share_count per hardware state and returns enable state per share_count from .is_enabled() hook, in case it's a shared gate. While at it, add a check in clk_gate2_disable() to ensure it's never called with a zero share_count. Reported-by: Fabio Estevam <fabio.estevam@freescale.com> Fixes: f9f28cdf2167 ("ARM: imx: add shared gate clock support") Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* ENGR00321308 ARM: imx: make sure OCOTP clk is enabled in MSLAnson Huang2014-07-04
| | | | | | | | As some modules need to access ocotp in MSL, so we need to make sure it is enabled during MSL, after kernel boot up, clk dirver will disable it in late init. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00321288 ARM: imx: gpc: fix VADC power off while pu management activeRobin Gong2014-07-04
| | | | | | | | | bit17/bit18 of GPC_CNTR worked as VADC power state control, that's function looks different with other bits of this register: write 1 raise power request and write 0 do nothing. Need read and write only the related bit fields of the register to avoid touch bit17/bit18 on i.mx6sx. Also fix the same for pcie power on/off. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00320383-2 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sxAnson Huang2014-07-04
| | | | | | | | | | | Improve DDR3 freq scaling procedure of i.MX6SX: 1. some code of condition check is incorrect; 2. better to keep MMDC command same as ddr script; 3. improve the clock tree change of mmdc path; 4. remove precharge command. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00320383-1 ARM: imx: correct ddr3 busfreq change flow of i.mx6sxAnson Huang2014-07-03
| | | | | | | | | | | Now that we have found the root cause of ddr3 freq scaling of i.MX6SX, we can remove the previous workaround and add correct fix. Revert "ENGR00316496 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sx" This reverts commit 93510bfa720670b2f80a7f35ffb327f69fcb0f21. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00317086-1 clk: Add dcic clock define for imx6qSandor Yu2014-07-03
| | | | | | | Add dcic1 and dcic define in imx6q clock tree. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit 93ae4ba005f1931ed3cd4e0ac0e8948e3752ad68)
* ENGR00320554: ARM: imx: drop unncessary PL310 errataRichard Liu2014-07-02
| | | | | | | | | | | The PL310 integrated on i.MX6 series and VF610 are revision r3p1 and later. Per ARM PL310 errata document, 588369 is fixed in r2p0 and 727915 is fixed in r3p1. Neither is needed for i.MX6 or VF610. So let's drop them. Signed-off-by: Richard Liu <r66033@freescale.com> Acked-by: Jason Liu <r64343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-10: ARM: imx6qdl: update mmdc_ch0_axi name in mux selectionsShawn Guo2014-06-27
| | | | | | | | | | | | | Commit ac166cffc9de (ENGR00318063-7: ARM: imx6q: mmdc_ch_axi clock should be non-gateable) dropped the non-exist gate clock mmdc_ch0_axi by pointing it to mmdc_ch0_axi_podf. But it forgot updating clock name used in clock mux selections. This causes call like clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]) to fail. Fix the failure by updating clock name in mux selections to be "mmdc_ch0_axi_podf". Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00320185-2 IMX6SX/DISPMIX: add dispmix on/off support for 6SX platformFancy Fang2014-06-26
| | | | | | | | Modify the dispmix on/off interfaces to add specific support for 6sx platform. Signed-off-by: Fancy Fang <chen.fang@freescale.com> (cherry picked from commit 31aab0b205ea9438de96f04ac0201c6fec3a669c)
* ENGR00320185-1 IMX6SX/DISPMIX: add dispmix on/off support for 6SX platformFancy Fang2014-06-26
| | | | | | | | Add the required clocks for the dispmix on/off operation. This include clocks definition and initialization. Signed-off-by: Fancy Fang <chen.fang@freescale.com> (cherry picked from commit 638acb3c30b135901631e59c9938e06422cc4b76)
* Revert "ENGR00318063-5: ARM: imx: set CLK_SET_PARENT_GATE flag for glitchy ↵Shawn Guo2014-06-26
| | | | | | | | | | | | | | | | | mux clocks" This reverts commit cf56832a5ddf3a7caf3641bc272f59c7033f0b88. The change has a much bigger impact than we initially thought. It basically requires client drivers to check return of every single clk_set_parent() and clk_set_rate() call to know if they're doing something that clock driver prohibits for sake of glitch. The client drivers haven't been so ready for this change, so let's revert it from release branch and keep developing it on main branch for a while. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00320088 ARM: imx: disable Mega/Fast mix off featureAnson Huang2014-06-26
| | | | | | | As some modules in M/F domain are not ready for this feature, so need to disable it until every driver are ready for it. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00319792 ARM: imx: need to make sure MMDC auto self refresh is enabledAnson Huang2014-06-26
| | | | | | | | | | | When there is busfreq scaling between low power mode and audio bus mode, the enabling of MMDC auto self-refresh code will be skipped as they are both DLL off mode, it will cause DDR power increase, so we just move the enabling of the MMDC auto self-refresh mode to the end of busfreq change to make sure it is enabled after a DDR freq change. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00316496 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sxAnson Huang2014-06-26
| | | | | | | | | | | Improve DDR3 freq scaling procedure of i.MX6SX: 1. some code of condition check is incorrect; 2. better to keep MMDC command same as ddr script; 3. improve the clock tree change of mmdc path; 4. remove CON_REG req for MMDC. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00318063-8: ARM: imx6q: hide buggy ldb_di_sel from clk APIShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | | The clk_set_parent() on the buggy mux ldb_di0_sel and ldb_di1_sel can possibly lock up the downstream divider and result in no clock output. Let's hard-code the parent to be pll2_pfd0_352m at boot time, and hide these two buggy muxes from clk API. Then no clk_set_parent() can be called on these muxes to switch parent clock at run-time. Kernel parameter 'ldb_di_clk_sel' is created to select parent of ldb_di_clk among the following clocks at boot time. 'pll5_video_div' 'pll2_pfd0_352m' 'pll2_pfd2_396m' 'mmdc_ch1_axi' 'pll3_usb_otg' Example format: ldb_di_clk_sel=pll5_video_div If the kernel parameter is absent or invalid, pll2_pfd0_352m will be selected by default. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-7: ARM: imx6q: mmdc_ch_axi clock should be non-gateableShawn Guo2014-06-25
| | | | | | | | | | | | | Per the updated CCM chapter, there is no gate for clock mmdc_ch1_axi. And there is a gate for mmdc_ch0_axi, but the gate also controls FABRIC clock, which means the gate cannot be gated anyway. That said, implementing these two clocks as gate does not make too much sense. Since the clocks are already referenced in quite some places, to minimize the impact of dropping the gate, instead of removing the clocks completely, we choose to point the clocks to their dividers. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocksShawn Guo2014-06-25
| | | | | | | | | | The i.MX6 Reference Manual requires PLLs to be powered down before changing its rate. Let's add flag CLK_SET_RATE_GATE for PLLs and audio/video dividers to enforce the check at clock core level. So any clk_set_rate() call from clients on these clocks will fail if the clocks are not disabled and unprepared. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-5: ARM: imx: set CLK_SET_PARENT_GATE flag for glitchy mux clocksShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | | The mux clocks found on imx6 SoCs are all glitchy ones except pll1_sw_clk_sel, axi_sel, periph_clk_sel and periph2_clk_sel. When switching parent clock of a glitchy mux without gating, a glitch could be generated and propagated into the downstream divider, and hence locks up the divider and results in no clock output. To avoid the situation, the parent switching should happen only when the clock is gated. Add CLK_SET_PARENT_GATE flag for i.MX mux clocks, so that clock core will make that check during clk_set_parent() call. Since glitchless clocks do not need this flag, we create imx_clk_mux_glitchless() without this flag for them. The periph_clk_sel and periph2_clk_sel are registered by imx_clk_busy_mux() which does not set this flag anyway, so they need no change. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-4: ARM: imx: drop flag CLK_SET_RATE_NO_REPARENT for ↵Shawn Guo2014-06-25
| | | | | | | | | | | | | | imx_clk_mux_flags All the users of function imx_clk_mux_flags() set CLK_SET_RATE_PARENT to request rate change propagatiopn up to parent. In this case, it should be good to clear flag CLK_SET_RATE_NO_REPARENT to let clk core find the best parent clock for the requested rate. Let's drop flag CLK_SET_RATE_NO_REPARENT for imx_clk_mux_flags(), so that function imx_clk_mux_flags_reparent() can just be saved. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-3: ARM: imx6sx: fix ocram_sels mux settingShawn Guo2014-06-25
| | | | | | | | | | | | | | | The current imx6sx clock driver combines two mux clocks ocram_alt_sel and ocram_sel into one, while ocram_alt_sel is a glitchy mux and ocram_sel is a glitchless one. Fix it to match the clock tree in Reference Manual. One thing clk API clients need to take care is that clk_set_parent() can be called on glitchy ocram_alt_sel only when ocram_sel selects the other path, i.e. periph. Otherwise, a glitch could be generated on ocram_alt_sel and get propagated into the divider ocram_podf. In that case, ocram_podf gets locked up and ocram clock has no output. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-2: ARM: imx6q: fix axi_sels mux settingShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | The current imx6q clock driver combines two mux clocks axi_alt_sel and axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a glitchless one. Fix it to match the clock tree in Reference Manual, and update busfreq driver regarding parent switching on that. Note, the parent checking before calling clk_set_parent() in busfreq driver isn't really necessary, because clk API will make the check and do nothing if the new parent is the same one as the old. One thing clk API clients need to take care is that clk_set_parent() can be called on glitchy axi_alt_sel only when axi_sel selects the other path, i.e. periph. Otherwise, a glitch could be generated on axi_alt_sel and get propagated into the divider axi_podf. In that case, axi_podf gets locked up and axi clock has no output. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-1: ARM: imx6sl: fix clock name in ocram_selsShawn Guo2014-06-25
| | | | | | | | The clock IMX6SL_CLK_OCRAM_ALT_SEL is registered with name "ocram_alt_sel", so the name in ocram_sels should be "ocram_alt_sel" than "ocram_alt_sels". Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00319455-2 imx6sx: enable can transceiver by default for canfdDong Aisheng2014-06-20
| | | | | | | | Switch on the transceiver by default for board with canfd enabled since canfd driver does not handle it. Two CAN instances share the same switch. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00318259-2 ARM: imx: support mega fast domain power off in DSMAnson Huang2014-06-17
| | | | | | | | | | Add mega fast domain power off feature in DSM, it can save about 0.72mW power; If there is any module in Mega/Fast domain enabled as wakeup source, then Mega/Fast domain's power will be kept on in DSM. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00318392 ARM:imx6x: Save/restore SCU and some CP15 registers across ↵Ranjani Vaidyanathan2014-06-13
| | | | | | | | | | | | | | | suspend/resume This patch ensures that the SCU and certain A9 CP15 registers state are maintained across a suspend/resume cycle: 1. Need to ensure that SCU standby bit is set again after suspend/resume cycle, else the system will never WAIT mode after a suspend/resume cycle. This bit should be enabled on all SMP systems immaterial of whether CPUIDLE is enabled or not. 2. Several A9 errata workarounds involve setting bits in the ARM diagnostic register. Save/restore this register across a suspend/resume cycle. 3. Save and restore the A9 power control register also. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00318207 ARM:imx6x:Busfreq:Fix build warnings in busfreq driver.Ranjani Vaidyanathan2014-06-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build warnings in busfreq driver: /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c: In function 'imx6_dt_find_ddr_sram': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c:736:29: warning: assignment makes integer from pointer without a cast [enabled by default] ddr_freq_change_iram_phys = (void *)ddr_iram_addr; ^ CC drivers/base/firmware_class.o /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6sx': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:404:22: warning: assignment makes pointer from integer without a cast [enabled by default] iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size; ^ /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6q': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:539:22: warning: assignment makes pointer from integer without a cast [enabled by default] iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size; ^ CC arch/arm/mach-imx/busfreq_lpddr2.o /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c: In function 'init_mmdc_lpddr2_settings': /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:96:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement] unsigned long ddr_code_size; ^ /home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:101:3: warning: passing argument 1 of 'memcpy' makes pointer from integer without a cast [enabled by default] mx6_change_lpddr2_freq = (void *)fncpy( Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317542-1 ARM:imx6x: Dynamically calculate the size of low power mode code.Ranjani Vaidyanathan2014-06-12
| | | | | | | | | | | | | This patch adds support for dynamically calculating the size of all low power code (suspend, ddr freq change and low power idle). This allows for easy code changes in the future. This patch also moves the DDR frequency change code from lower 8K of the memory allocated for IRAM page table to regular IRAM. With this the lower 8K of the IRAM page table only contains suspend/resume and low power IDLE code. This gives a little more flexibility to the cdoe size for suspend/resume and low power IDLE. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00317861 ARM: imx: add cpufreq support when VPU running at 352MHzAnson Huang2014-06-11
| | | | | | | | | When VPU 352MHz is supported, PLL2_PFD2 will run at 352MHz instead of 396MHz, CPUFreq driver will use PLL2_PFD2 when it is running at 396MHz setpoint, so when VPU 352MHz is enabled, CPUFreq can be enabled but need to remove the 396MHz setpoint. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00315400 ARM: imx: add lpddr2 busfreq support for i.mx6sxAnson Huang2014-06-04
| | | | | | | | | | Add freq scaling for lpddr2 of i.MX6SX, support 3 setpoints: high -> 400MHz audio -> 100MHz low -> 24MHz Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00314570-1 arm: add pcie power control on imx6sxRichard Zhu2014-05-26
| | | | | | | imx6sx pcie has standalone ldo domain, add the power control routines on the ldo regulator call back. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00314571 pcie: resolve one compile warning on pcie pmRichard Zhu2014-05-26
| | | | | | resolve one compile warning on pcie pm Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00309838 ARM: imx6sl: gpc: add chip revision check for dispmixRobby Cai2014-05-23
| | | | | | | The dispmix feature works without problem since TO1.2. This patch adds the back-compatibility for older chip. Signed-off-by: Robby Cai <r63905@freescale.com>
* ENGR00309881 ARM:imx6: Disable L1 and L2 when DDR is in self-refresh.Ranjani Vaidyanathan2014-05-16
| | | | | | | | | When switching to page tables in IRAM, we are switching from a cacheable to non-cacheable page table. Based on recommendation from ARM, we need to ensure that branch prediction, L1 data nd L2 are disabled when DDR is put into self-refresh. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00313508-01 ARM: imx6sx: add enet sleep mode supportFugang Duan2014-05-15
| | | | | | Add enet sleep mode support for imx6sx arm2 platforms. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00313202 ARM: imx: add VPU 352M support for i.MX6QAnson Huang2014-05-13
| | | | | | | | | | | | | | | | | | When VPU freq is set to 352MHz, it need to source clk from PLL2_PFD2_396M, and PLL2_PFD2_396M need to change freq to 352M. VDDSOC/PU needs to be at highest setpoint when VPU@352Mhz, cpufreq will be disabled as it will not save any power if VDDSOC/PU's voltage stays at highest setpoint. Busfreq will be disabled as it needs PLL2_PFD2 to be as 396MHz to achieve low power audio freq setpoint. To enable VPU 352MHz feature, select it in menuconfig, it is disabled by default. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00312939 ARM:imx6x: Ensure that the suspend/resume code saves the registers.Ranjani Vaidyanathan2014-05-13
| | | | | | | | | The suspend/resume code needs to save the ARM registers that is used in the code. The return paths from the suspend code can be different, based on if an interrupt is pending. So we cannot depend on the kernel code to restore the registers. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00311992-3 ARM: imx: add cpufreq support for i.mx6sxAnson Huang2014-05-08
| | | | | | | | | | | | | | | Enable cpufreq support for i.MX6SX, currently three setpoints are supported, the freq/volt table are as below: VDDARM_CAP VDDSOC_CAP 996M: 1.250V 1.175V 792M: 1.175V 1.175V 396M: 1.075V 1.175V All upper voltages are 25mV higher then the minimum value defined in datasheet, this 25mV is to cover board level IR drop. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00311249 ARM: imx: add DDR/IO low power mode for i.mx6sxAnson Huang2014-05-04
| | | | | | | Set DDR/IO to low power mode for i.MX6SX when system enter DSM mode, it can save ~8mW power(from 25mA lower to 19mA). Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00303665-3 ARM: imx: add busfreq support for i.MX6SXAnson Huang2014-04-30
| | | | | | | | | Add busfreq support for i.MX6SX, add a new ddr3 asm code and use a busfreq info structure to pass necessary info for low level busfreq change function, the structure will be placed in front of ocram function. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00303665-2 ARM: imx: correct clock tree info on i.MX6SXAnson Huang2014-04-30
| | | | | | | | | | From reference manual, periph2_pre's parent list option 3 is pll4_audio_div, not pll2_198m. And periph2_clk2 's parent of option 1 should be osc, not pll2. Need to mask handshake of mmdc ch0. Signed-off-by: Anson Huang <b20788@freescale.com>
* serial: imx: Remove init() and exit() platform callbacksAlexander Shiyan2014-04-29
| | | | | | Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00310878-1 Asoc: fsl: refine clock tree for ESAIShengjiu Wang2014-04-29
| | | | | | | There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Make the clock for ESAI more clear. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00310290 ARM: imx: enable necessary clocks for i.mx6sxAnson Huang2014-04-25
| | | | | | | | On i.MX6SX, when CA9 and CM4 are working together, CA9 can NOT disable those shared modules' clock, so keep those clocks CM4 needs always enabled. Signed-off-by: Anson Huang <b20788@freescale.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-22 03:33:55 -0400