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- inherited mcc ver 001.002 from vibryd mqx release.
- use mu general int4 as the cpu2cpu int (num is 122 at a9 side).
- add linux wait_event/wake_up mechanism on the buffer management
of share memory
- replace wait_event_interruptible### by wait_event###, so the sleep
task wouldn't be waken up by reboot or CTRL+C signals.
- use the offset address to do the MQX_TO_VIRT and VIRT_TO_MQX
exchanges.
- regmap_bits_updat can't write 1 to clear the bit-set asr, use
regmap_read/write
- fix mu irq clear hang issue
only do the regmap once in the isr register func, and
replace the multi-regmap operations in the kinds of mx6sx mcc related
apis by one global imx_mu_reg.
Signed-off-by: Richard Zhu <r65037@freescale.com>
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