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* ENGR00320383-2 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sxAnson Huang2014-07-04
| | | | | | | | | | | Improve DDR3 freq scaling procedure of i.MX6SX: 1. some code of condition check is incorrect; 2. better to keep MMDC command same as ddr script; 3. improve the clock tree change of mmdc path; 4. remove precharge command. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00320383-1 ARM: imx: correct ddr3 busfreq change flow of i.mx6sxAnson Huang2014-07-03
| | | | | | | | | | | Now that we have found the root cause of ddr3 freq scaling of i.MX6SX, we can remove the previous workaround and add correct fix. Revert "ENGR00316496 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sx" This reverts commit 93510bfa720670b2f80a7f35ffb327f69fcb0f21. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00319792 ARM: imx: need to make sure MMDC auto self refresh is enabledAnson Huang2014-06-26
| | | | | | | | | | | When there is busfreq scaling between low power mode and audio bus mode, the enabling of MMDC auto self-refresh code will be skipped as they are both DLL off mode, it will cause DDR power increase, so we just move the enabling of the MMDC auto self-refresh mode to the end of busfreq change to make sure it is enabled after a DDR freq change. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00316496 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sxAnson Huang2014-06-26
| | | | | | | | | | | Improve DDR3 freq scaling procedure of i.MX6SX: 1. some code of condition check is incorrect; 2. better to keep MMDC command same as ddr script; 3. improve the clock tree change of mmdc path; 4. remove CON_REG req for MMDC. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00317542-1 ARM:imx6x: Dynamically calculate the size of low power mode code.Ranjani Vaidyanathan2014-06-12
| | | | | | | | | | | | | This patch adds support for dynamically calculating the size of all low power code (suspend, ddr freq change and low power idle). This allows for easy code changes in the future. This patch also moves the DDR frequency change code from lower 8K of the memory allocated for IRAM page table to regular IRAM. With this the lower 8K of the IRAM page table only contains suspend/resume and low power IDLE code. This gives a little more flexibility to the cdoe size for suspend/resume and low power IDLE. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00303665-3 ARM: imx: add busfreq support for i.MX6SXAnson Huang2014-04-30
Add busfreq support for i.MX6SX, add a new ddr3 asm code and use a busfreq info structure to pass necessary info for low level busfreq change function, the structure will be placed in front of ocram function. Signed-off-by: Anson Huang <b20788@freescale.com>