aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-imx/clk-imx6sx.c
Commit message (Collapse)AuthorAge
* ENGR00322509-1 Revert "ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag ↵Ranjani Vaidyanathan2014-07-15
| | | | | | | | | | | | | | | for PLL clocks" The commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154, which added a check to prevent pll rate changes when PLL is enabled, causes incorrect reporting of MMDC clock during low power IDLE. So revert the patch as the code needs to be improved to handle all cases. Revert "ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks" This reverts commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00318063-11: ARM: imx6: add return check for clock callsShawn Guo2014-07-15
| | | | | | | | | | | | | | There are a bunch of clk_enable_prepare, clk_set_parent and clk_set_rate calls in imx6 clock driver's initialization. They are called without retunr check. If there is something going wrong with the calls, they will just fail silently. The patch creates a set of helper functions imx_clk_enable_prepare, imx_clk_set_parent and imx_clk_set_rate, and use them instead from clock initialization to check the return and print error message to tell failures if any. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00322272-1: ARM: imx6sx: hide the buggy ldb_di_sel mux from clk APIShawn Guo2014-07-11
| | | | | | | | | | | | | | | | This is a smilar change for imx6sx clock tree as what we did for imx6q with commit 0bec46131d88 (ENGR00318063-8: ARM: imx6q: hide buggy ldb_di_sel from clk API). As the valid procedure of switching ldb_di_sel on imx6sx is not available yet, we hide this buggy mux by looking at the parent selection done by bootloader and register it statically to clock framework, so that switching this buggy mux becomes impossible. Also, since the bit width of ldb_di_sels is 3, we add two "dummy" entries for ldb_di_sels to avoid out-of-bounds error. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00321308 ARM: imx: make sure OCOTP clk is enabled in MSLAnson Huang2014-07-04
| | | | | | | | As some modules need to access ocotp in MSL, so we need to make sure it is enabled during MSL, after kernel boot up, clk dirver will disable it in late init. Signed-off-by: Anson Huang <b20788@freescale.com>
* Revert "ENGR00318063-5: ARM: imx: set CLK_SET_PARENT_GATE flag for glitchy ↵Shawn Guo2014-06-26
| | | | | | | | | | | | | | | | | mux clocks" This reverts commit cf56832a5ddf3a7caf3641bc272f59c7033f0b88. The change has a much bigger impact than we initially thought. It basically requires client drivers to check return of every single clk_set_parent() and clk_set_rate() call to know if they're doing something that clock driver prohibits for sake of glitch. The client drivers haven't been so ready for this change, so let's revert it from release branch and keep developing it on main branch for a while. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocksShawn Guo2014-06-25
| | | | | | | | | | The i.MX6 Reference Manual requires PLLs to be powered down before changing its rate. Let's add flag CLK_SET_RATE_GATE for PLLs and audio/video dividers to enforce the check at clock core level. So any clk_set_rate() call from clients on these clocks will fail if the clocks are not disabled and unprepared. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-5: ARM: imx: set CLK_SET_PARENT_GATE flag for glitchy mux clocksShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | | The mux clocks found on imx6 SoCs are all glitchy ones except pll1_sw_clk_sel, axi_sel, periph_clk_sel and periph2_clk_sel. When switching parent clock of a glitchy mux without gating, a glitch could be generated and propagated into the downstream divider, and hence locks up the divider and results in no clock output. To avoid the situation, the parent switching should happen only when the clock is gated. Add CLK_SET_PARENT_GATE flag for i.MX mux clocks, so that clock core will make that check during clk_set_parent() call. Since glitchless clocks do not need this flag, we create imx_clk_mux_glitchless() without this flag for them. The periph_clk_sel and periph2_clk_sel are registered by imx_clk_busy_mux() which does not set this flag anyway, so they need no change. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-4: ARM: imx: drop flag CLK_SET_RATE_NO_REPARENT for ↵Shawn Guo2014-06-25
| | | | | | | | | | | | | | imx_clk_mux_flags All the users of function imx_clk_mux_flags() set CLK_SET_RATE_PARENT to request rate change propagatiopn up to parent. In this case, it should be good to clear flag CLK_SET_RATE_NO_REPARENT to let clk core find the best parent clock for the requested rate. Let's drop flag CLK_SET_RATE_NO_REPARENT for imx_clk_mux_flags(), so that function imx_clk_mux_flags_reparent() can just be saved. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-3: ARM: imx6sx: fix ocram_sels mux settingShawn Guo2014-06-25
| | | | | | | | | | | | | | | The current imx6sx clock driver combines two mux clocks ocram_alt_sel and ocram_sel into one, while ocram_alt_sel is a glitchy mux and ocram_sel is a glitchless one. Fix it to match the clock tree in Reference Manual. One thing clk API clients need to take care is that clk_set_parent() can be called on glitchy ocram_alt_sel only when ocram_sel selects the other path, i.e. periph. Otherwise, a glitch could be generated on ocram_alt_sel and get propagated into the divider ocram_podf. In that case, ocram_podf gets locked up and ocram clock has no output. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00303665-2 ARM: imx: correct clock tree info on i.MX6SXAnson Huang2014-04-30
| | | | | | | | | | From reference manual, periph2_pre's parent list option 3 is pll4_audio_div, not pll2_198m. And periph2_clk2 's parent of option 1 should be osc, not pll2. Need to mask handshake of mmdc ch0. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00310878-1 Asoc: fsl: refine clock tree for ESAIShengjiu Wang2014-04-29
| | | | | | | There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Make the clock for ESAI more clear. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00310290 ARM: imx: enable necessary clocks for i.mx6sxAnson Huang2014-04-25
| | | | | | | | On i.MX6SX, when CA9 and CM4 are working together, CA9 can NOT disable those shared modules' clock, so keep those clocks CM4 needs always enabled. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00309977-1 ARM: imx6sx: Separate SPDIF and Audio clocksNicolin Chen2014-04-23
| | | | | | | | | | | | | | | | | | | Shawn's patch -- ARM: imx: shared gate support for i.MX clk_gate2 clocko has fixed the problem of clock conflicts due to sharing a same gate. So from now on, we can no longer need to take care the shared gate clock for each audio clock route. Thus this patch separates them by using the new clock registering helper function. And meanwhile, we set a proper rate for each route so as to support each module. For S/PDIF, we use 98304000Hz so that the current driver would perfectly get 32000Hz and 48000Hz sample rate playback support, even though we can only get 43885Hz for 44100Hz sample rate in this way -- If user want to playback 44100Hz group sample rates, they need to change the parent rate. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00307014-04 ARM: imx6x: Set vadc clock source from Pll3Sandor Yu2014-04-17
| | | | | | Set vadc clock parent to PLL3 USB OTG. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00308382-2 mcc: enable mcc a9 linux demoRichard Zhu2014-04-16
| | | | | | enable mcc a9 linux demo on imx6sx. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00307635-4 ARM: imx6sx: Use 24.576MHz for both SSI and SAI clocksNicolin Chen2014-04-16
| | | | | | | SAI derives its mclk from SSI_CLK, so this patch sets a default value for them. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00303701-3 ARM: clk: imx6sx: use the 132MHz for the WEIMHuang Shijie2014-04-16
| | | | | | We set the maximum clock frequency for the WEIM module. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00306442-1 ARM: imx6sx: Merge SPDIF and AUDIO clocks into one gate clockNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Solo X, SPDIF and AUDIO clocks shares one single gate to switch two entirely different clock routes: SPDIF <-- <---- SPDIF_PODF ----.... \ / gate1 / \ AUDIO <-- <---- AUDIO_PODF ----.... The two audio modules would easily cause conflict during clock operations if running in the same time: SPDIF <-- gate1 <---- SPDIF_PODF ----.... AUDIO <-- gate1 <---- AUDIO_PODF ----.... To keep them safe, we here have to merge them into one gate clock and limit their rates and parent identical: <---- SPDIF_PODF ----.... / SPDIF, AUDIO <-- gate1 \ <---- AUDIO_PODF ----.... [ The only disadvantage of this modification is that we can not separately set a different clock rates and clock sources to SPDIF and AUDIO clock. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00305648-5 ARM: imx6sx: set Audio clocks to 24.576MHzNicolin Chen2014-04-16
| | | | | | | | | This patch sets a default clock 24.576MHz for ESAI clock and swtich the source of external AUDIO clock from pll4 to pll3 since 24.0Mhz would be more likely recommanded than 24.576MHz to WM8962 audio codec. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00305648-2 ARM: imx6sx: Add SAI ipg clock to the clock treeNicolin Chen2014-04-16
| | | | | | | There's one clock for SAI memory access missing in the clock tree. Thus add it. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00300658-1 clk: imx6sx: correct csi parent clockRobby Cai2014-04-16
| | | | | | correct csi parent clock Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00303542-4 mach:Update gpu clock to 720MLoren HUANG2014-04-16
| | | | | | | -Designed team confirmed GC400T is designed to run 720M. -Update the clock source for GC400T. Signed-off-by: Loren HUANG <b02279@freescale.com>
* ENGR00303122-3 ARM: imx6sx: fix ASRC related clocks in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | According to imx6sx RM, there are three clock providers for ASRC: Module clock Clock root Gate asrck_clock_d spdif0_clk_root N/A ipg_clk ahb_clk_root asrc_clk_enable mem_clk ahb_clk_root asrc_clk_enable while the current clock tree describes a clock named 'ASRC' that only describes the asrc_clk_enable function. Thus this patch first adds the other missing clocks to ASRC. [ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk to ASRC in the devicetree directly. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00302235-2 arm: enable pcie on imx6sxRichard Zhu2014-04-16
| | | | | | | | | - add mandatory pcie related clks in imx6sx clks tree - add pcie dts in imx6sx dts - add pcie kconfig option in imx6sx soc config - add pcie regulate into dts Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00301290-2 ARM: imx6sx: enable usbphy dummy clockPeter Chen2014-04-16
| | | | | | | | If usbphy is enabled, we need to enable usbphy dump clock, it is the requirement from IC engineer, it is used to guarantee some RTL operation correctness without software operation. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00301552-1 ARM: imx6sx: Correct audio_clk in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | We currently has asrc_* clocks in the imx6sx clock tree while actually, according to the Reference Manual, all of them should be named after the audio_clk that controls the external MCLK output from MCLK pad of AUDMUX. Thus fix it along with its gate clock missing in the current clock tree. Meanwhile, this patch also configures a default clock rate for it -- 24MHz. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00300430-12 ARM: clk: add a new helper which can re-parent the clockHuang Shijie2014-04-16
| | | | | | | | | | | | | The clock for qspi may be different when different NOR flashes are connected to the board. So the IMX6SX_CLK_QSPI1_SEL/IMX6SX_CLK_QSPI2_SEL should have the re-parent capability. This patch adds a new helper to register the clock which needs the re-parent capability. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300439-2 imx6sx: fix can_sel parent clockDong Aisheng2014-04-16
| | | | | | The default parent of can_sel clock is invalid, need manually set it. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00299746-2 ARM: imx6sx: correct lcdif clocksRobby Cai2014-04-16
| | | | | | | | | | - correct LCDIF pixel clock's parent selection - correct LCDIF PODF clock's parent - Set LCDIF1_PRE_SEL clock parent to PLL5_VIDEO, and set LCDIF1_SEL clock's parent to LCDIF1_PODF. They are set for pixel clock. Signed-off-by: Sandor Yu <R01008@freescale.com> Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00300074-2 ARM:imx:clk: Remove enet clock gate enabled after system bootFugang Duan2014-04-16
| | | | | | | | After enet bootup, enet disable all clock to save power causes system hang, so there had workaround to enable enet clock gate. Now the issue is fixed, remove the workaround. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00299323-11 ARM: imx: Add i.mx6sx enet clk supportFugang Duan2014-04-16
| | | | | | | | | Add i.mx6sx enet clk support: - Add enet2 refrence clock. - Add PTP clock. - Set enet system AHB clock to 200Mh. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00298524-2 ARM: imx: Add MSL support for i.mx6sxAnson Huang2014-04-16
It adds initial MSL support for i.mx6sx, including below features: 1. add cpu type check; 2. add system timer support; 3. add clock tree support; 4. add machine layer init support; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> Acked-by: Jason Liu
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 15:14:56 -0400