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* ENGR00322509-1 Revert "ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag ↵Ranjani Vaidyanathan2014-07-15
| | | | | | | | | | | | | | | for PLL clocks" The commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154, which added a check to prevent pll rate changes when PLL is enabled, causes incorrect reporting of MMDC clock during low power IDLE. So revert the patch as the code needs to be improved to handle all cases. Revert "ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocks" This reverts commit aabf4911f9971d4a6f02fe74bfdd39e7d74b7154. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00318063-11: ARM: imx6: add return check for clock callsShawn Guo2014-07-15
| | | | | | | | | | | | | | There are a bunch of clk_enable_prepare, clk_set_parent and clk_set_rate calls in imx6 clock driver's initialization. They are called without retunr check. If there is something going wrong with the calls, they will just fail silently. The patch creates a set of helper functions imx_clk_enable_prepare, imx_clk_set_parent and imx_clk_set_rate, and use them instead from clock initialization to check the return and print error message to tell failures if any. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* Revert "ENGR00318063-5: ARM: imx: set CLK_SET_PARENT_GATE flag for glitchy ↵Shawn Guo2014-06-26
| | | | | | | | | | | | | | | | | mux clocks" This reverts commit cf56832a5ddf3a7caf3641bc272f59c7033f0b88. The change has a much bigger impact than we initially thought. It basically requires client drivers to check return of every single clk_set_parent() and clk_set_rate() call to know if they're doing something that clock driver prohibits for sake of glitch. The client drivers haven't been so ready for this change, so let's revert it from release branch and keep developing it on main branch for a while. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-6: ARM: imx6: add CLK_SET_RATE_GATE flag for PLL clocksShawn Guo2014-06-25
| | | | | | | | | | The i.MX6 Reference Manual requires PLLs to be powered down before changing its rate. Let's add flag CLK_SET_RATE_GATE for PLLs and audio/video dividers to enforce the check at clock core level. So any clk_set_rate() call from clients on these clocks will fail if the clocks are not disabled and unprepared. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-5: ARM: imx: set CLK_SET_PARENT_GATE flag for glitchy mux clocksShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | | The mux clocks found on imx6 SoCs are all glitchy ones except pll1_sw_clk_sel, axi_sel, periph_clk_sel and periph2_clk_sel. When switching parent clock of a glitchy mux without gating, a glitch could be generated and propagated into the downstream divider, and hence locks up the divider and results in no clock output. To avoid the situation, the parent switching should happen only when the clock is gated. Add CLK_SET_PARENT_GATE flag for i.MX mux clocks, so that clock core will make that check during clk_set_parent() call. Since glitchless clocks do not need this flag, we create imx_clk_mux_glitchless() without this flag for them. The periph_clk_sel and periph2_clk_sel are registered by imx_clk_busy_mux() which does not set this flag anyway, so they need no change. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-1: ARM: imx6sl: fix clock name in ocram_selsShawn Guo2014-06-25
| | | | | | | | The clock IMX6SL_CLK_OCRAM_ALT_SEL is registered with name "ocram_alt_sel", so the name in ocram_sels should be "ocram_alt_sel" than "ocram_alt_sels". Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00309977-2 ARM: imx6q/sl: Set SPDIF clock to 22736841HzNicolin Chen2014-04-23
| | | | | | | | | | | | | | | | | | | | Since we no longer use clk_set_rate() in spdif driver, the rate we provide to it on imx6q/sl platforms is no more contented for its supporting sample rates. By setting the clock to 22736841Hz, we can get the sample rates: 48008Hz for 48000Hz 32005Hz for 32000Hz 43859Hz for 44100Hz The results for 48KHz and 32KHz has changed comparing to the previous release, but the one for 44100Hz has a bit lose even though it should be the best we can get based on the current clock rate. If user want to playback a perfect 44100Hz, they need to change the parent clock rate. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00289643-1 arm: imx6sl: add missing spba clock to clock treeNicolin Chen2014-04-16
| | | | | | | | We are missing spba clock in imx6sl's clock tree, thus add it. Acked-by: Wang Shengjiu <b02247@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00288123 [iMX6SL] Add low power audio supportRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | Add support for low power audio playback: 1. SSI2 is sourced from PLL4 2. Extern_audio_clk is sourced from pll4 3. PLL4 is in bypass mode during audio playback (based on freq requested by extern_audio_clk and ssi2 clk) 4. DDR is at 100MHz, AHB is at 24MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00286960-1 arm: imx: initialize clock gate statusAnson Huang2014-04-16
| | | | | | | | | | | Some clocks gates need to be set to 2b'01 to allow CCM auto disabling them when system enters WAIT mode, this setting can save many runtime power. These clock gates are normally always enabled, so no need to add another status for clk gate enable function, just set them to right status when system boot up is good enough. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00287081 [iMX6SL] - Make sure MMDC clocks are enabled at bootRanjani Vaidyanathan2014-04-16
| | | | | | | Need to enable MMDC clocks to maintain the correct usecount, else PLL2 can get disabled incorrectly thus hanging the system. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00284019: [iMX6SL] Add low power mode optimizationsRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | | Add optimizations so that the low power IDLE mode numbers match between the 3.10.9 and 3.0.35 kernel. Optimizations include: 1. Disable unused PLLs and PFDs in clock init 2. Some of the drivers call clk_prepare in probe and enable much later. clk_pllv3_prepare locks the PLL disallowing some of the low power optimizations. For iMX6SL ensure that clk_pllv3_prepare does not lock the PLL. 3. Ensure that MMDC_CH0_LPM_HS is set when WAIT mode is entered. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00283496 ARM: clk: imx6sl: update epdc pixel clock treeRobby Cai2014-04-16
| | | | | | | Add CLK_SET_RATE_PARENT flag for epdc pixel clock to allow the rate change operation to propagate up to the clock's parent in order to get desired rate. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00281769 [iMX6SL] Allow uart to be sourced from 24MHz XTALRanjani Vaidyanathan2014-04-16
| | | | | | | | | | In order to optmize low power IDLE numbers all PLLs should be in bypass. On imx6sl, UART can be sourced directly from the 24MHz XTAL. Its frequency is limited to 4MHz due to an internal divide by 6 divider. For customer who don't require higher uart speeds add "uart_at_4M" to the kernel command line. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00281017 [MX6SL]Low power IDLE mode optimizationsRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | | | | | Added a new bus freq mode - ultra_low_bus_freq_mode. In this mode the ARM is the only bus master that is active and the system is already in low power idle mode. And when ARM executes WFI in this mode, we do some aggressive power savings techinques like: 1. Drop DDR freq to 1MHz 2. Drop AHB freq to 3MHz 3. Float the DDR IO pads 4. If all PLLs are in bypass (which should be the case), do some analog power saving options like reducing the OSC-bias current, turning off the regular bandgap, disabling the regular 2P5, enabling the weak 2p5 etc. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00281789-01 imx6sl: add missing enet clock for imx6slFugang Duan2014-04-16
| | | | | | There's a enet clock gate missing in clock tree, thus add it. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00281036: [MX6SL]Align LPDDR2 freq change code to 8-byte boundaryRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | This patch fixes 4 issues: 1. Add the .align 8 directive to the LPDDR2 freq change code, else the fncpy() function fails and the kernel does not boot. 2. Loads the correct L2_BASE_ADDR into register in lpddr2 freq change code 3. Fix the warning in clk_imx6sl.c 4. Change dev_WARN to dev_info in busfreq-imx6.c. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00280101-1 [iMX6SL] Add busfreq supportRanjani Vaidyanathan2014-04-16
| | | | | | | Add support to scale the DDR frequency between 400MHz and 24MHz. Add support to scale AHB between 132MHz and 24MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00277382-2 [MX6SL] Add WaIT mode support for MX6SL.Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | Enable WAIT mode support for MX6SL. Need to ensure that the ARM:IPG clock ratio is maintained at 12:5 when WFI is executed. This is the fix for the WAIT mode issue on MX6SL. Set AHB to 132Mhz at boot, which is the recommended freq for AHB. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00277382-1 [MX6SL] Ensure that PLL1 and PLL2 are always enabled.Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | | Need to ensure that PLL1 and PLL2 have the enabled bit set even when the PLL is powered down and disabled. 1. Modifications to the ARM_PODF bits in the CCM require PLL1 to be enabled. 2. PLL2 will be set to bypass and enabled state (can be powered down) in low power IDLE mode. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00277843-03 ARM: clk: update imx6sl lcdif clock tree.Sandor Yu2014-04-16
| | | | | | Add CLK_SET_RATE_PARENT flag for IMX6SL_CLK_LCDIF_PIX_SEL. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00277715-7 ARM: clk: Config audio clocks for imx6slNicolin Chen2014-04-16
| | | | | | | | * Set extern_audio to 24MHz as audio codec MCLK for WM8962 * Set pll3_pfd3 as spdif's parent Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00277715-6 ARM: clk: Add missing pll4_audio_div for imx6slNicolin Chen2014-04-16
| | | | | | | There's a dividor for pll4_audio clock missing in clock tree, thus add it. Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00277750-2 ARM: clk-imx6sl: lcdif: set lcdif axi clock to 200MHzRobby Cai2014-04-16
| | | | | | | | set lcdif axi clock's parent to 'pll2_pfd2' and lcdif axi clock frequency to 200MHz. Signed-off-by: Robby Cai <R63905@freescale.com> Acked-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00277750-1 ARM: clk-imx6sl: correct some clock parent selectionsRobby Cai2014-04-16
| | | | | | | | | | | | | | | | | This might not be documented clearly or correctly in IC RM (Rev. 1, 04/2013). There's one document describing the CCM change on imx6sl, which is available at http://compass.freescale.net/livelink/livelink?func=ll&objId=223814333&objAction=browse This patch does - split csi_lcdif_sels since 2'b00 for CSI means 'osc' while for LCDIF means 'pll2_bus'. - split epdc_pxp_sels since 3'b101 for EPDC means 'pll3_pfd2' while for PXP means 'pll3_pfd3' - correct 2'b10 for lcdif_axi_sels, should be 'pll3_usb_otg' instead of 'pll3_120m' Signed-off-by: Robby Cai <R63905@freescale.com> Acked-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00276832-5 epdc: set epdc/pxp axi clock to maximum 200MHzRobby Cai2014-04-16
| | | | | | | | | set epdc pix clock's parent clock to pll5_video for imx6sl set epdc/pxp axi clock's parent clock to pll2_pfd2 for imx6dl set epdc/pxp axi clock to 200MHz for both imx6dl and imx6sl (on imx6dl, epdc/pxp axi clock is same one, named 'ipu2') Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00277271 ARM: imx: Disable WAIT mode for i.MX6SL during kernel boot upAnson Huang2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WAIT mode is enabled by default due to hardware reset, so we need to disable it during kernel boot up, otherwise, system may crash without proper setting for WAIT mode. CPUIdle driver will enable WAIT mode later. Below is the stack dump when crash, this patch fix it: Bad mode in data abort handler detected Internal error: Oops - bad mode: 0 [#1] SMP ARM Modules linked in: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.9+ #369 task: 807dba88 ti: 807d0000 task.ti: 807d0000 PC is at 0xffff1044 LR is at arch_cpu_idle+0x48/0x54 pc : [<ffff1044>] lr : [<8000f7dc>] psr: 60000192 sp : 807d1f60 ip : 00000000 fp : 00000000 r10: 807d8954 r9 : 8059980c r8 : 80819280 r7 : 00000001 r6 : 80819280 r5 : 00000000 r4 : 807d0000 r3 : 8001cbe0 r2 : 807d9510 r1 : 0104b000 r0 : 80819540 Flags: nZCv IRQs off FIQs on Mode IRQ_32 ISA ARM Segment kernel Control: 10c53c7d Table: af28804a DAC: 00000017 Process swapper/0 (pid: 0, stack limit = 0x807d0238) Stack: (0x807d1f60 to 0x807d2000) 1f60: 80819540 0104b000 807d9510 8001cbe0 807d0000 00000000 80819280 00000001 1f80: 80819280 8059980c 807d8954 00000000 00000000 807d1f60 8000f7dc ffff1044 1fa0: 60000192 ffffffff 807d0000 8005de44 807d89d0 808193c0 807bf084 807dc86c 1fc0: 8000406a 412fc09a 00000000 8077fb58 ffffffff ffffffff 8077f6b4 00000000 1fe0: 00000000 807bf088 00000000 10c53c7d 807d88d0 80008074 00000000 00000000 [<8000f7dc>] (arch_cpu_idle+0x48/0x54) from [<0104b000>] (0x104b000) Code: bad PC value ---[ end trace c2c7dd3b2230692c ]--- Kernel panic - not syncing: Attempted to kill the idle task Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00276845-2 ARM: imx6sl: move the clock init code to appropriate placeRobby Cai2014-04-16
| | | | | | | It's a cleanup. Move the PLL5_VIDEO clock init code to the clock init code group to avoid the code messed up. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00275031-1 mx6sl fb: support lcdif framebuffer on 3.10Robby Cai2014-04-16
| | | | | | | | | re-use the upstreaming mxsfb.c code. - add the lcdif axi clock for register and dram access - set the lcdif pix's parent as pll5_video to get most accurate pix clock - add binding doc for lcdif dts Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00275821-2 ARM: imx: Enable suspend/resume for i.MX6SLAnson Huang2014-04-16
| | | | | | | Enable suspend/resume function for i.MX6SL, currently support standby and mem mode. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00275542-1 ARM: imx: Enable PU power management for i.MX6SLAnson Huang2014-04-16
| | | | | | Enable dynamical PU power management for i.MX6SL. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00269945: ARM: imx6sl: initialize use count of IPG clockShawn Guo2014-04-16
| | | | | | | | | | | | | | | | | | | | We're running into a system hang during imx6sl boot. It's been tracked down to SDMA driver function sdma_init(). System hangs immediately after the clk_disable() is called in sdma_init(). It turns out that the issue is caused by IPG bus clock which is the parent of sdma clock is turned off accidentally due to the incorrect initial use count. IPG clock is initial on and should be always on when system operates. But the use count of the clock is zero initially. So when the last child clock gets disabled, the use count of IPG clock reaches zero, and thus clock framework will turn off IPG clock (and possibly parent clocks along the way), and causes the system hang. Let's initialize the use count of IPG clock by calling clk_prepare_enable() on it to match the on state of the clock, so that the clock will not be turned off accidentally. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00274009 ARM: imx: gpt clk on i.mx6sl can NOT source from OSCAnson Huang2014-04-16
| | | | | | | | | | | There is no OSC clock source option for gpt on i.mx6sl, it can only source from perclk, and perclk can be from OSC. As perclk is clock source of many low speed devices, set it to be from OSC, this can avoid freq varying when bus clk(ipg) is scaled. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00273512-2 ARM: imx: Change GPT clock source to OSCAnson Huang2014-04-16
| | | | | | | | | | GPT clock is system clock source, need to avoid freq varying, as system bus clock(ipg) may be changed, for i.mx6 series SOCs, all of them except i.mx6q TO1.0 support sourcing GPT clk from OSC directly, so switch gpt clock to OSC if the SOCs support this feature, as OSC freq is constant. Signed-off-by: Anson Huang <b20788@freescale.com>
* ARM: imx6: change some clocks to fixup clocksLiu Ying2014-04-16
| | | | | | | | | | All the clocks controlled by the register 'CCM Serial Clock Multiplexer Register 1' should be fixup clocks. This patch changes those clocks from basic multiplexer or divider clocks to fixup clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6: use common of_clk_init() call to initialize clocksShawn Guo2014-04-16
| | | | | | | | | | | Commit 53bb71da1c5c14267089218923585840f76e2480 upstream. Instead of explicitly calling clock initialization functions, we can declare the functions with CLK_OF_DECLARE() and then call common of_clk_init() to have them invoked properly. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: add clock support for imx6slShawn Guo2014-04-16
Commit 45fe6810347b0a83561a13d9ee656c899a309fc0 upstream. Add clock support for i.MX6 SoloLite. It uses the dtc marco support to define all clock IDs in imx6sl-clock.h, which will be included by both clock driver and device tree sources, so that the data will stay sync all the time between kernel and DT. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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