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Improve DDR3 freq scaling procedure of i.MX6SX:
1. some code of condition check is incorrect;
2. better to keep MMDC command same as ddr script;
3. improve the clock tree change of mmdc path;
4. remove precharge command.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Now that we have found the root cause of ddr3 freq scaling of i.MX6SX,
we can remove the previous workaround and add correct fix.
Revert "ENGR00316496 ARM: imx: fix random failure for ddr3 freq scaling on i.mx6sx"
This reverts commit 93510bfa720670b2f80a7f35ffb327f69fcb0f21.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Improve DDR3 freq scaling procedure of i.MX6SX:
1. some code of condition check is incorrect;
2. better to keep MMDC command same as ddr script;
3. improve the clock tree change of mmdc path;
4. remove CON_REG req for MMDC.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Fix the following build warnings in busfreq driver:
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c: In function 'imx6_dt_find_ddr_sram':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c:736:29: warning: assignment makes integer from pointer
without a cast [enabled by default]
ddr_freq_change_iram_phys = (void *)ddr_iram_addr;
^
CC drivers/base/firmware_class.o
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6sx':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:404:22: warning: assignment makes pointer from integer
without a cast [enabled by default]
iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size;
^
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6q':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:539:22: warning: assignment makes pointer from integer
without a cast [enabled by default]
iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size;
^
CC arch/arm/mach-imx/busfreq_lpddr2.o
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c: In function 'init_mmdc_lpddr2_settings':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:96:2: warning: ISO C90 forbids mixed declarations and
code [-Wdeclaration-after-statement]
unsigned long ddr_code_size;
^
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:101:3: warning: passing argument 1 of 'memcpy' makes
pointer from integer without a cast [enabled by default]
mx6_change_lpddr2_freq = (void *)fncpy(
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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This patch adds support for dynamically calculating the size of all
low power code (suspend, ddr freq change and low power idle). This allows
for easy code changes in the future.
This patch also moves the DDR frequency change code from lower 8K of the memory
allocated for IRAM page table to regular IRAM. With this the lower 8K of the
IRAM page table only contains suspend/resume and low power IDLE code. This
gives a little more flexibility to the cdoe size for suspend/resume and low
power IDLE.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Add busfreq support for i.MX6SX, add a new ddr3 asm code
and use a busfreq info structure to pass necessary info
for low level busfreq change function, the structure will be
placed in front of ocram function.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Allocate page tables in IRAM that will be used when ever DDR is put
into self-refresh. Add support for this to iMX6SX.
Some common files are also changed to accomodate the OCRAM_S address that
is used to store the IRAM page table in iMX6SX.
This patch depends on the following two commits:
ENGR297285-1 [MX6x] Support IRAM page table when DDR is in self-refresh.
ENGR297285-2 [MX6x] Support IRAM page table when DDR is in self-refresh.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Whenever DDR is explicitly put into self-refresh, we need to ensure
that no access are made to the DDR. All the bus masters excpet ARM
are shutdown gracefully.
The ARM core can continue to access the DDR due to:
1. Speculative accesses
This can be prevented by flushing the Branch Target Address Cache
2. Aggressive Prefetching
This can be minimized by adding nops.
Apart from this the TLB architecture in ARM does not guarantee that
an entry remains in the TLB unless its explicitly locked. Even if
free slots are available an entry maybe evicted. So flushing the TLB
does not guarantee a page table walk will not happen.
The solution is to put a minimized page table in IRAM that can be used when
DDR is in self-refresh. The IRAM page tables should have entries for IRAM,
AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR
into self-refresh. It should not contain any entries that point to the DDR.
This patch set accomplishes the following:
1. Set the IRAM to be mapped as 1M sections in the high mem region.
This makes it possible to create entries for the IRAM code in the IRAM page table.
We need to ensure that both the DDR and IRAM page table have mapping for the IRAM code.
2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table.
3. Save TTBR1
4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using
TTBR1 before DDR is put into self-refresh. Ensure the following settings:
a. TTBCR.N = 1
This means the 0-2G virtual address space is translated using TTBR0
and 2G-4G is translated using TTBR1.
b. Set TTBCR.PD0 = 1
With this setting page table walks using TTBR0 are disabled.
4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will
be used for translations now).
5. Restore TTBR1
Even though TTBR1 is only used to decode the top 2G of virtual address
space, ARM requires that we allocate the entire 16KB for the page table.
To minimize IRAM/OCRAM required, we put the code in the bottom 8K and
page table entries in the top 8K.
This requires the low power code be optimized to occupy as little space
as possible.
This commit is cherry-picked:
93ae491d9dbe34a91e2dd5832b02b0f0a390ddbe
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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During DDR frequency change code or in low power IDLE code (in iMX6SL),
we need to ensure that all register addresses accessed in the IRAM
code are in the TLB. There should be no TLB walks when DDR is in self-refresh.
To ensure this flush the TLB before DDR frequency change and before
low power IDLE (only iMX6SL) procedures.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Use for_each_online_cpu instead of for_each_present_cpu to take this case,
otherwise system will crash as below when go into low bus with 'maxcpus=1'
setting in command line.
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = 80004000
[00000000] *pgd=00000000
Internal error: Oops: 817 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 68 Comm: kworker/0:2 Not tainted 3.10.17-16647-g0868f35 #27
Workqueue: events reduce_bus_freq_handler
task: ac156d80 ti: ac2a2000 task.ti: ac2a2000
PC is at update_ddr_freq+0x98/0x2d0
LR is at 0x0
pc : [<80021928>] lr : [<00000000>] psr: 400f0013
sp : ac2a3e98 ip : 00000000 fp : 814db740
r10: 016e3600 r9 : 00000000 r8 : 00000000
r7 : 814de900 r6 : 80c60cc0 r5 : 0000000f r4 : 80c60dc0
r3 : 00000000 r2 : 80c60dc0 r1 : 80c60d34 r0 : 00000000
Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c53c7d Table: 3c49404a DAC: 00000015
Process kworker/0:2 (pid: 68, stack limit = 0xac2a2238)
Stack: (0xac2a3e98 to 0xac2a4000)
3e80: 00000000 00000000
3ea0: 00000000 00000000 00000001 80c60cc0 80c603a4 80c60cc0 814de900 00000000
3ec0: 00000000 ac2a2038 814db740 80020154 00000064 ac02f6c0 00000004 80c2103c
3ee0: 80c60d38 814db740 814de900 80020628 ac135780 8003d7ac 00000001 ac083eb8
3f00: 00000000 00000000 00000003 ac135780 814db754 ac135798 ac2a2000 ac2a2030
3f20: 00000001 ac2a2000 814db740 8003e4b8 8003e380 00000000 00000000 80c5fcc1
3f40: ac2a3f64 ac083ea0 00000000 ac135780 8003e380 00000000 00000000 00000000
3f60: 00000000 800437e0 fd7efff9 00000000 7faf7bfd ac135780 00000000 00000000
3f80: ac2a3f80 ac2a3f80 00000000 00000000 ac2a3f90 ac2a3f90 ac2a3fac ac083ea0
3fa0: 8004372c 00000000 00000000 8000e018 00000000 00000000 00000000 00000000
3fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
3fe0: 00000000 00000000 00000000 00000000 00000013 00000000 fffc7fae d4cadbdb
[<80021928>] (update_ddr_freq+0x98/0x2d0) from [<80020154>] (reduce_bus_freq+
0x58/0x518)
[<80020154>] (reduce_bus_freq+0x58/0x518) from [<80020628>] (reduce_bus_freq_
handler+0x14/0x24)
[<80020628>] (reduce_bus_freq_handler+0x14/0x24) from [<8003d7ac>] (process_one
_work+0x10c/0x374)
[<8003d7ac>] (process_one_work+0x10c/0x374) from [<8003e4b8>] (worker_thread+
0x138/0x3fc)
[<8003e4b8>] (worker_thread+0x138/0x3fc) from [<800437e0>] (kthread+0xb4/0xb8)
[<800437e0>] (kthread+0xb4/0xb8) from [<8000e018>] (ret_from_fork+0x14/0x3c)
Code: e5940014 e3002dc0 e594e018 e34820c6 (e5835000)
---[ end trace 206df98575045d04 ]---
Unable to handle kernel paging request at virtual address ffffffec
pgd = 80004000
[ffffffec] *pgd=3ff7e821, *pte=00000000, *ppte=00000000
Signed-off-by: Robin Gong <b38343@freescale.com>
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Add support to scale the DDR frequency between 400MHz and 24MHz.
Add support to scale AHB between 132MHz and 24MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Fix build warning in arch/arm/mach-imx/busfreq_ddr3.c.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add support to drop DDR and AHB frequency to 24MHz in
system IDLE state.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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