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The code incorrectly attempts to set the parent of periph2_clk to periph2_clk2_sel.
Fix this by calling the clk_set_parent() function with the correct parameters.
Also replace all calls to clk_set_parent() and clk_set_rate() with imx_clk_set_parent()
and imx_clk_set_rate() function that prints out error messages in case of failure.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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396MHz in low power idle.
In low power IDLE mode, CPU needs to be sourced from PLL1 instead of PLL2_PFD0
as PLL2 needs to be in bypass mode to achieve 24MHz DDR frequency.
The original code attempts to relock the PLL1 at frequency that is as close
as possible to 396MHz, which results in PLL1 at 648MHz and the ARM freq turns
out to be 324MHz instead of 396MHz. This causes issues with CPUFREQ as 324MHz is
not a frequency listed in the cpufreq table in the device tree.
This patch attempts to fix this mis-match and maintains CPU freq at 396MHz
in low power idle.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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The current imx6q clock driver combines two mux clocks axi_alt_sel and
axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a
glitchless one. Fix it to match the clock tree in Reference Manual,
and update busfreq driver regarding parent switching on that. Note,
the parent checking before calling clk_set_parent() in busfreq driver
isn't really necessary, because clk API will make the check and do
nothing if the new parent is the same one as the old.
One thing clk API clients need to take care is that clk_set_parent()
can be called on glitchy axi_alt_sel only when axi_sel selects the other
path, i.e. periph. Otherwise, a glitch could be generated on
axi_alt_sel and get propagated into the divider axi_podf. In that case,
axi_podf gets locked up and axi clock has no output.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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Fix the following build warnings in busfreq driver:
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c: In function 'imx6_dt_find_ddr_sram':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq-imx6.c:736:29: warning: assignment makes integer from pointer
without a cast [enabled by default]
ddr_freq_change_iram_phys = (void *)ddr_iram_addr;
^
CC drivers/base/firmware_class.o
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6sx':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:404:22: warning: assignment makes pointer from integer
without a cast [enabled by default]
iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size;
^
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c: In function 'init_mmdc_ddr3_settings_imx6q':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_ddr3.c:539:22: warning: assignment makes pointer from integer
without a cast [enabled by default]
iram_iomux_settings = ddr_freq_change_iram_base + ddr_code_size;
^
CC arch/arm/mach-imx/busfreq_lpddr2.o
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c: In function 'init_mmdc_lpddr2_settings':
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:96:2: warning: ISO C90 forbids mixed declarations and
code [-Wdeclaration-after-statement]
unsigned long ddr_code_size;
^
/home/ra5478/work/linux_3.10.x/arch/arm/mach-imx/busfreq_lpddr2.c:101:3: warning: passing argument 1 of 'memcpy' makes
pointer from integer without a cast [enabled by default]
mx6_change_lpddr2_freq = (void *)fncpy(
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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This patch adds support for dynamically calculating the size of all
low power code (suspend, ddr freq change and low power idle). This allows
for easy code changes in the future.
This patch also moves the DDR frequency change code from lower 8K of the memory
allocated for IRAM page table to regular IRAM. With this the lower 8K of the
IRAM page table only contains suspend/resume and low power IDLE code. This
gives a little more flexibility to the cdoe size for suspend/resume and low
power IDLE.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Add freq scaling for lpddr2 of i.MX6SX, support 3 setpoints:
high -> 400MHz
audio -> 100MHz
low -> 24MHz
Signed-off-by: Anson Huang <b20788@freescale.com>
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When VPU freq is set to 352MHz, it need to source clk
from PLL2_PFD2_396M, and PLL2_PFD2_396M need to change
freq to 352M.
VDDSOC/PU needs to be at highest setpoint when VPU@352Mhz,
cpufreq will be disabled as it will not save any power if
VDDSOC/PU's voltage stays at highest setpoint.
Busfreq will be disabled as it needs PLL2_PFD2 to be
as 396MHz to achieve low power audio freq setpoint.
To enable VPU 352MHz feature, select it in menuconfig,
it is disabled by default.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add busfreq support for i.MX6SX, add a new ddr3 asm code
and use a busfreq info structure to pass necessary info
for low level busfreq change function, the structure will be
placed in front of ocram function.
Signed-off-by: Anson Huang <b20788@freescale.com>
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When ARM executes WFI in audio playback mode, its possible to
lower the power consumed on the VDDHIGH_IN and VDDSOC_IN rails
by:
1. Putting DDR into self-refresh
2. Lower DDR frequency to 25MHz
3. Float DDR IO pads.
Also drop AHB to 8MHz in audio playback mode (aligning with 3.0.35)
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add support for low power audio playback:
1. SSI2 is sourced from PLL4
2. Extern_audio_clk is sourced from pll4
3. PLL4 is in bypass mode during audio playback (based
on freq requested by extern_audio_clk and ssi2 clk)
4. DDR is at 100MHz, AHB is at 24MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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i.MX6DL's axi clock is sourcing from pfd540 by default,
need to switch axi clock from pfd540 to periph when system
enters low bus mode, this is to allow pfd540 to be disabled,
and it also keeps clk tree correct.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Incorrect clock disable of PLL2 caused random hangs during
DDR freq change in iMX6DL.
Remove PERCLK freq change code as this is not required for TO1.1
and later.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Added a new bus freq mode - ultra_low_bus_freq_mode.
In this mode the ARM is the only bus master that is active and
the system is already in low power idle mode.
And when ARM executes WFI in this mode, we do some aggressive
power savings techinques like:
1. Drop DDR freq to 1MHz
2. Drop AHB freq to 3MHz
3. Float the DDR IO pads
4. If all PLLs are in bypass (which should be the case), do
some analog power saving options like reducing the OSC-bias current,
turning off the regular bandgap, disabling the regular 2P5, enabling
the weak 2p5 etc.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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This patch fixes 4 issues:
1. Add the .align 8 directive to the LPDDR2 freq change code,
else the fncpy() function fails and the kernel does not boot.
2. Loads the correct L2_BASE_ADDR into register in lpddr2 freq change code
3. Fix the warning in clk_imx6sl.c
4. Change dev_WARN to dev_info in busfreq-imx6.c.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add support to scale the DDR frequency between 400MHz and 24MHz.
Add support to scale AHB between 132MHz and 24MHz.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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Add support to drop DDR and AHB frequency to 24MHz in
system IDLE state.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
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