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* ENGR00317086-1 clk: Add dcic clock define for imx6qSandor Yu2014-07-03
| | | | | | | Add dcic1 and dcic define in imx6q clock tree. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit 93ae4ba005f1931ed3cd4e0ac0e8948e3752ad68)
* ENGR00318063-8: ARM: imx6q: hide buggy ldb_di_sel from clk APIShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | | The clk_set_parent() on the buggy mux ldb_di0_sel and ldb_di1_sel can possibly lock up the downstream divider and result in no clock output. Let's hard-code the parent to be pll2_pfd0_352m at boot time, and hide these two buggy muxes from clk API. Then no clk_set_parent() can be called on these muxes to switch parent clock at run-time. Kernel parameter 'ldb_di_clk_sel' is created to select parent of ldb_di_clk among the following clocks at boot time. 'pll5_video_div' 'pll2_pfd0_352m' 'pll2_pfd2_396m' 'mmdc_ch1_axi' 'pll3_usb_otg' Example format: ldb_di_clk_sel=pll5_video_div If the kernel parameter is absent or invalid, pll2_pfd0_352m will be selected by default. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-2: ARM: imx6q: fix axi_sels mux settingShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | The current imx6q clock driver combines two mux clocks axi_alt_sel and axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a glitchless one. Fix it to match the clock tree in Reference Manual, and update busfreq driver regarding parent switching on that. Note, the parent checking before calling clk_set_parent() in busfreq driver isn't really necessary, because clk API will make the check and do nothing if the new parent is the same one as the old. One thing clk API clients need to take care is that clk_set_parent() can be called on glitchy axi_alt_sel only when axi_sel selects the other path, i.e. periph. Otherwise, a glitch could be generated on axi_alt_sel and get propagated into the divider axi_podf. In that case, axi_podf gets locked up and axi clock has no output. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00310878-1 Asoc: fsl: refine clock tree for ESAIShengjiu Wang2014-04-29
| | | | | | | There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Make the clock for ESAI more clear. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00303122-2 ARM: imx6q: fix ASRC related clocks in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | According to imx6q RM, there are three clock providers for ASRC: Module clock Clock root Gate asrck_clock_d spdif1_clk_root N/A ipg_clk ahb_clk_root asrc_clk_enable mem_clk ahb_clk_root asrc_clk_enable while the current clock tree describes a confusing clock named 'asrc' that combines this three clocks by rooting its rate from spdif1_clk_root but set its gate from ipg/mem_clk. Thus this patch first fixes the name asrc to the correct one -- spdif1 and adds the missing clocks to ASRC. [ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk to ASRC in the devicetree directly. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00299756-2 ARM: imx6q: Add missing lvds2 clock to the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | | | We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC. And this lvds2, along with lvds1, can be used to provide external clock source to the internal pll, such as pll4_audio and pll5_video. So This patch mainly adds the lvds2 to the clock tree and fix its relationship with pll4 accordingly. [ To reduce the risk from code changing. This patch only takes care of pll4 related part. We might later need to add the relationship with pll5 too. ] Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00298524-2 ARM: imx: Add MSL support for i.mx6sxAnson Huang2014-04-16
| | | | | | | | | | | | | | It adds initial MSL support for i.mx6sx, including below features: 1. add cpu type check; 2. add system timer support; 3. add clock tree support; 4. add machine layer init support; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> Acked-by: Jason Liu
* ENGR00288405: pcie: switch to upstreamed pcie driverRichard Zhu2014-04-16
| | | | | | | | | Based on community patch-set, re-setup pcie driver on imx6 platforms. * re-fine the pcie clks. * add the pcie support in dts files. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00288568 Revert "ENGR00275213-1 arm: pcie: enable pcie on imx6 platforms"Richard Zhu2014-04-16
| | | | | | | | | | | | | switch to community upstreamed pcie driver. Revert "ENGR00275213-1 arm: pcie: enable pcie on imx6 platforms" This reverts commit d33370c77e57aed5a9b6733c9898418541fed54a. Conflicts: Documentation/devicetree/bindings/clock/imx6q-clock.txt arch/arm/mach-imx/clk-imx6q.c Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00285692 arm: imx: add necessary clock gates into clk treeAnson Huang2014-04-16
| | | | | | | | | | 1. add epit1, epit2 and tzasc2 clock gate to clk tree so that clk framework can manage these clock gates; 2. adjust ipu2_di1 clock gate registry code to follow hardware register CG index sequence. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00284981-1 arm: imx: add clock nodes for caamAnson Huang2014-04-16
| | | | | | | Add caam clock gate nodes into clock tree, so that caam driver can manage its clock gate to save power. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00275213-1 arm: pcie: enable pcie on imx6 platformsRichard Zhu2014-04-16
| | | | | | | | | | | | Add PCIe related clocks definitions and select pci on imx6 platforms toggle bit18 of grp1 fix pcie pm issue: Set bit18 of gpr1 before enter into supend, and clean it after resume, can fix the following errata. Errata ERR005723_PCIe PCIe does not support L2 Power Down. Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00276249-2 ARM: imx6q: Add pll4_audio_div to clock treeNicolin Chen2014-04-16
| | | | | | | There's a pll4_audio_div clock, an extra divider for pll4, missing in current clock tree, thus add it. Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00274172-1 ARM: imx6q: refactor some ldb related clocksLiu Ying2014-04-16
| | | | | | | | | | | | | The ldb_di[0|1]_ipu_div dividers may divide their parent clock frequencies by either 3.5 or 7. The non-integral dividers cannot be dealt with the common clock framework, so they cannot be registered as common clock dividers. So this patch adds a fixed factor clock of 1/7 and introduces ldb_di[0|1]_div_sel multiplexers so that the fixed factor clocks of 1/3.5 and 1/7 can be set to be the parents of ldb_di[0|1]_div_sel multiplexers. The ldb_di[0|1]_podf dividers are no longer used then. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00275483-1 ARM: imx6q: clk: add video 27m clockLiu Ying2014-04-16
| | | | | | | | This patch adds the fixed factor video 27m clock in the imx6q clock driver. This clock's parent clock is the pll3_pfd1_540m clock. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00273512-2 ARM: imx: Change GPT clock source to OSCAnson Huang2014-04-16
| | | | | | | | | | GPT clock is system clock source, need to avoid freq varying, as system bus clock(ipg) may be changed, for i.mx6 series SOCs, all of them except i.mx6q TO1.0 support sourcing GPT clk from OSC directly, so switch gpt clock to OSC if the SOCs support this feature, as OSC freq is constant. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00240987: ARM: imx6q: add vdoa gate clockShawn Guo2014-04-16
| | | | | | Add the missing vdoa gate clock for imx6q. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: add the missing cko output selectionShawn Guo2014-04-16
| | | | | | | | The clock output on imx6q CCM_CLKO1 pad is not always cko1 clock, and there is a multiplexer to select between cko1 and cko2. Add this missing selection as the clock cko. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: add cko2 clocksShawn Guo2014-04-16
| | | | | | | It adds the missing cko2 clocks, including multiplexer, divider and gate. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: add spdif gate clockShawn Guo2014-04-16
| | | | | | It adds the missing spdif gate clock into imx6q clock driver. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx6q: clk: add the eim_slow clockHuang Shijie2014-04-16
| | | | | | | | | | Commit 9545b2ed68eef1541219d5c6351c10e698a24f39 upstream. Add the eim_slow clock, since the weim needs it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: add VF610 clock supportJingchang Lu2014-04-16
| | | | | | | | | | | | Commit 1f2c5fd5f0486566f73aa0149577d5f69df90bcc upstream. Add clock support for Vybrid VF610. It uses dtc macro support to define all clock IDs in vf610-clock.h to keep clock IDs coherence between kernel and DT. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: add clock support for imx6slShawn Guo2014-04-16
| | | | | | | | | | | | Commit 45fe6810347b0a83561a13d9ee656c899a309fc0 upstream. Add clock support for i.MX6 SoloLite. It uses the dtc marco support to define all clock IDs in imx6sl-clock.h, which will be included by both clock driver and device tree sources, so that the data will stay sync all the time between kernel and DT. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* Merge tag 'soc-for-linus-3' of ↵Linus Torvalds2013-05-07
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates (part 3) from Arnd Bergmann: "This is the third and smallest of the SoC specific updates. Changes include: - SMP support for the Xilinx zynq platform - Smaller imx changes - LPAE support for mvebu - Moving the orion5x, kirkwood, dove and mvebu platforms to a common "mbus" driver for their internal devices. It would be good to get feedback on the location of the "mbus" driver. Since this is used on multiple platforms may potentially get shared with other architectures (powerpc and arm64), it was moved to drivers/bus/. We expect other similar drivers to get moved to the same place in order to avoid creating more top-level directories under drivers/ or cluttering up the messy drivers/misc/ even more." * tag 'soc-for-linus-3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits) ARM: imx: reset_controller may be disabled ARM: mvebu: Align the internal registers virtual base to support LPAE ARM: mvebu: Limit the DMA zone when LPAE is selected arm: plat-orion: remove addr-map code arm: mach-mv78xx0: convert to use the mvebu-mbus driver arm: mach-orion5x: convert to use mvebu-mbus driver arm: mach-dove: convert to use mvebu-mbus driver arm: mach-kirkwood: convert to use mvebu-mbus driver arm: mach-mvebu: convert to use mvebu-mbus driver ARM i.MX53: set CLK_SET_RATE_PARENT flag on the tve_ext_sel clock ARM i.MX53: tve_di clock is not part of the CCM, but of TVE ARM i.MX53: make tve_ext_sel propagate rate change to PLL ARM i.MX53: Remove unused tve_gate clkdev entry ARM i.MX5: Remove tve_sel clock from i.MX53 clock tree ARM: i.MX5: Add PATA and SRTC clocks ARM: imx: do not bring up unavailable cores ARM: imx: add initial imx6dl support ARM: imx1: mm: add call to mxc_device_init ARM: imx_v4_v5_defconfig: Add CONFIG_GPIO_SYSFS ARM: imx_v6_v7_defconfig: Select CONFIG_PERF_EVENTS ...
| * ARM i.MX53: tve_di clock is not part of the CCM, but of TVEPhilipp Zabel2013-04-12
| | | | | | | | | | | | | | | | | | Remove the tve_di clock from the CCM clock tree. It will be provided by the Television Encoder driver, as this clock is an output signal of the TVE module. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: i.MX5: Add PATA and SRTC clocksSascha Hauer2013-04-12
| | | | | | | | | | | | | | | | This adds the clock gates and the binding documentation for PATA and SRTC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: i.MX53 Add the cko1, cko2 clock outputs.Martin Fuzzey2013-04-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These two clocks connect to external pins and can be muxed to various internal clocks. They are typically used either for debugging or to provide clocks to external chips (eg audio codecs). Currently only the selectable clocks that already exist in the clock tree have been added. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM i.MX6q: Add audio/video PLL post dividers for i.MX6q rev 1.1Philipp Zabel2013-04-12
| | | | | | | | | | | | | | | | Query silicon revision to determine clock tree and add post dividers for newer revisions. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM i.MX53: Add GPU clocks to clock treePhilipp Zabel2013-04-12
| | | | | | | | | | | | | | | | This patch adds the missing GPU2D and GPU3D mux and gate clocks, and the graphics arbiter gate clock. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge tag 'drivers-for-linus' of ↵Linus Torvalds2013-05-04
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver changes from Olof Johansson: "This is a rather large set of patches for device drivers that for one reason or another the subsystem maintainer preferred to get merged through the arm-soc tree. There are both new drivers as well as existing drivers that are getting converted from platform-specific code into standalone drivers using the appropriate subsystem specific interfaces. In particular, we can now have pinctrl, clk, clksource and irqchip drivers in one file per driver, without the need to call into platform specific interface, or to get called from platform specific code, as long as all information about the hardware is provided through a device tree. Most of the drivers we touch this time are for clocksource. Since now most of them are part of drivers/clocksource, I expect that we won't have to touch these again from arm-soc and can let the clocksource maintainers take care of these in the future. Another larger part of this series is specific to the exynos platform, which is seeing some significant effort in upstreaming and modernization of its device drivers this time around, which unfortunately is also the cause for the churn and a lot of the merge conflicts. There is one new subsystem that gets merged as part of this series: the reset controller interface, which is a very simple interface for taking devices on the SoC out of reset or back into reset. Patches to use this interface on i.MX follow later in this merge window, and we are going to have other platforms (at least tegra and sirf) get converted in 3.11. This will let us get rid of platform specific callbacks in a number of platform independent device drivers." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits) irqchip: s3c24xx: add missing __init annotations ARM: dts: Disable the RTC by default on exynos5 clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3} ARM: exynos: restore mach/regs-clock.h for exynos5 clocksource: exynos_mct: fix build error on non-DT pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register() irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure reset: NULL deref on allocation failure reset: Add reset controller API dt: describe base reset signal binding ARM: EXYNOS: Add arm-pmu DT binding for exynos421x ARM: EXYNOS: Add arm-pmu DT binding for exynos5250 ARM: EXYNOS: Enable PMUs for exynos4 irqchip: exynos-combiner: Correct combined IRQs for exynos4 irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq ARM: EXYNOS: fix compilation error introduced due to common clock migration clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} clk: exynos4: export clocks required for fimc-is clk: samsung: Fix compilation error clk: tegra: fix enum tegra114_clk to match binding ...
| * \ Merge tag 'clk-exynos-for-v3.10' of ↵Arnd Bergmann2013-04-09
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers From Kukjin Kim <kgene.kim@samsung.com>: add suppport common clock framework for exynos * tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (73 commits) ARM: EXYNOS: fix compilation error introduced due to common clock migration clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3} clk: exynos4: export clocks required for fimc-is clk: samsung: Fix compilation error clk: exynos5250: register display block gate clocks to common clock framework clk: exynos4: Add support for SoC-specific register save list clk: exynos4: Add missing registers to suspend save list clk: exynos4: Remove E4X12 prefix from SRC_DMC register clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register clk: exynos4: Add E4210 prefix to LCD1 clock registers clk: exynos4: Remove SoC-specific registers from save list clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions clk: exynos4: Define {E,V}PLL registers clk: exynos4: Add missing mout_sata on Exynos4210 clk: exynos4: Add missing CMU_TOP and ISP clocks clk: exynos4: Add G3D clocks clk: exynos4: Add camera related clock definitions clk: exynos4: Export mout_core clock of Exynos4210 clk: samsung: Remove unimplemented ops for pll clk: exynos4: Export clocks used by exynos cpufreq drivers ... [arnd: add missing #address-cells property in mshc DT node] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | clk: exynos4: export clocks required for fimc-isSylwester Nawrocki2013-04-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1, ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1, DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are available to the consumers (Exynos4x12 FIMC-IS subsystem). While at it, indentation of the mux clocks table is corrected. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos5250: register display block gate clocks to common clock frameworkLeela Krishna Amudala2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi. Register it to common clock framework. Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos4: Add missing CMU_TOP and ISP clocksAndrzej Hajda2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos4: Add G3D clocksTomasz Figa2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clocks needed for G3D block present on Exynos 4 SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos4: Add camera related clock definitionsSylwester Nawrocki2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds several gate and mux clocks related to camera and ISP blocks. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos4: Export clocks used by exynos cpufreq driversLukasz Majewski2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch exports clocks used by Exynos cpufreq drivers to allow lookup using device tree. (Support to cpufreq drivers will be added in further patches.) Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos4: Export sclk_pcm0Tomasz Figa2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock is used by PCM interface 0. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos4: Use mout_mpll_user_* on Exynos4x12Tomasz Figa2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos4: Correct sclk_mfc clock definitionSylwester Nawrocki2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock must be exported to allow lookup using device tree. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos5440: register clocks using common clock frameworkThomas Abraham2013-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Exynos5440 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos5250: register clocks using common clock frameworkThomas Abraham2013-03-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Exynos5250 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| | * | clk: exynos4: register clocks using common clock frameworkThomas Abraham2013-03-25
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Exynos4 clocks are statically listed and registered using the Samsung specific common clock helper functions. Both device tree based clock lookup and clkdev based clock lookups are supported. Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * | ARM: tegra: Define Tegra114 CAR bindingPeter De Schrijver2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | The device tree binding models Tegra114 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * | clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad2013-04-04
| | | | | | | | | | | | | | | | | | | | | | | | Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: split into separate driver and device-tree patches] Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | Merge tag 'soc-for-linus' of ↵Linus Torvalds2013-05-02
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "This branch contains part 1 of the platform updates for 3.10. Among the highlights: - Support for the new Atmel Cortex-A5 based platforms (SAMA5D3) - New support for CSR SiRFatlas6 SoCs - A handful of updates for NVidia T114 (a.k.a. Tegra 4) - A bunch of updates for the shmobile platforms - A handful of updates for davinci - A few updates for Qualcomm MSM - Plus a handful of other patches, defconfig updates, etc." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (135 commits) ARM: tegra: pm: fix build error w/o PM_SLEEP ARM: davinci: ensure global variables are declared ARM: davinci: sram.c: fix incorrect type in assignment ARM: davinci: da8xx dt: make file local symbols static ARM: davinci: da8xx: add remoteproc support ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries ARM: socfpga: Add clock entries into device tree ARM: socfpga: Enable soft reset ARM: EXYNOS: replace cpumask by the corresponding macro ARM: EXYNOS: handle properly the return values ARM: EXYNOS: factor out the idle states ARM: OMAP4: Enable fix for Cortex-A9 erratas ARM: OMAP2+: Export SoC information to userspace ARM: OMAP2+: SoC name and revision unification ARM: OMAP2+: Move common part of late init into common function ARM: tegra: pm: remove duplicated include from pm.c ARM: davinci: da850: override mmc DT node device name ARM: davinci: da850: add mmc DT entries mmc: davinci_mmc: add DT support ARM: SAMSUNG: check processor type before cache restoration in resume ...
| * | | ARM: socfpga: Add clock entries into device treeDinh Nguyen2013-04-14
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the main PLL clock groups for SOCFPGA into device tree file so that the clock framework to query the clock and clock rates appropriately. $cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc1 2 2 25000000 sdram_pll 0 0 400000000 s2f_usr2_clk 0 0 66666666 ddr_dq_clk 0 0 200000000 ddr_2x_dqs_clk 0 0 400000000 ddr_dqs_clk 0 0 200000000 periph_pll 2 2 500000000 s2f_usr1_clk 0 0 50000000 per_base_clk 4 4 100000000 per_nand_mmc_clk 0 0 25000000 per_qsi_clk 0 0 250000000 emac1_clk 1 1 125000000 emac0_clk 0 0 125000000 main_pll 1 1 1600000000 cfg_s2f_usr0_clk 0 0 100000000 main_nand_sdmmc_clk 0 0 100000000 main_qspi_clk 0 0 400000000 dbg_base_clk 0 0 400000000 mainclk 0 0 400000000 mpuclk 1 1 800000000 smp_twd 1 1 200000000 Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Signed-off-by: Olof Johansson <olof@lixom.net>
* | | Merge tag 'dt-for-linus' of ↵Linus Torvalds2013-05-02
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device-tree updates from Olof Johansson: "Part 1 of device-tree updates for 3.10. The bulk of the churn in this branch is due to i.MX moving from C-defined pin control over to device tree, which is a one-time conversion that will allow greater flexibility down the road. Besides that, there's PCI-e bindings for Marvell mvebu platforms and a handful of cleanups to tegra due to the new include file functionality of the device tree compiler" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (113 commits) arm: mvebu: PCIe Device Tree informations for Armada XP GP arm: mvebu: PCIe Device Tree informations for Armada 370 DB arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox arm: mvebu: PCIe Device Tree informations for Armada XP DB arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 arm: mvebu: add PCIe Device Tree informations for Armada XP arm: mvebu: add PCIe Device Tree informations for Armada 370 ARM: sunxi: unify osc24M_fixed and osc24M arm: vt8500: Add SDHC support to WM8505 DT ARM: dts: Add a 64 bits version of the skeleton device tree ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board ARM: mvebu: Add support for NOR flash device on Armada XP-GP board ARM: mvebu: Add Device Bus support for Armada 370/XP SoC ARM: dts: imx6dl-wandboard: Add USB Host support ARM: dts: imx51 cpu node ARM: dts: Add missing imx27-phytec-phycore dtb target ARM: dts: Add NFC support for i.MX27 Phytec PCM038 module ARM: i.MX51: Add PATA support ARM: dts: Add initial support for Wandboard Dual-Lite ...
| * | | ARM: mx27: Replace clk_register_clkdev with clock DT lookupFabio Estevam2013-04-09
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Similarly as it was done for mx6q, use a DT lookup in order to make maintainance task for the clock devices easier. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | | clk: add si5351 i2c common clock driverSebastian Hesselbarth2013-04-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a common clock driver for Silicon Labs Si5351a/b/c i2c programmable clock generators. Currently, the driver does not support VXCO feature of si5351b. Passing platform_data or DT bindings selectively allows to overwrite stored Si5351 configuration which is very helpful for clock generators with empty eeprom configuration. Corresponding device tree binding documentation is also added. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Daniel Mack <zonque@gmail.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Michal Bachraty <michal.bachraty@streamunlimited.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-23 03:29:58 -0400