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* mtd: nand: Add a devicetree binding for ECC strength and ECC step sizeEzequiel Garcia2014-04-16
| | | | | | | | | | | | | | | | | | | | Some flashes can only be properly accessed when the ECC mode is specified, so a way to describe such mode is required. Together, the ECC strength and step size define the correction capability, so that we say we will correct "{strength} bit errors per {size} bytes". The interpretation of these parameters is implementation-defined, but they often have ramifications on the formation, interpretation, and placement of correction metadata on the flash. Not all implementations must support all possible combinations. Implementations are encouraged to further define the value(s) they support. Acked-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* of_mtd: Add helpers to get ECC strength and ECC step sizeEzequiel Garcia2014-04-16
| | | | | | | | | | | This commit adds simple helpers to obtain the devicetree properties that specify the ECC strength and ECC step size to use on a given NAND controller. Acked-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* mtd: Add a retlen parameter to _get_{fact,user}_prot_infoChristian Riesch2014-04-16
| | | | | | | Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Artem Bityutskiy <Artem.Bityutskiy@linux.intel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* of_mtd: fix header file include guardPhilipp Rosenberger2014-04-16
| | | | | | | | It seems the include guard was copied from of_net.h. Signed-off-by: Philipp Rosenberger <philipp.rosenberger@xse.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* of_mtd: Add no-op stubs to support CONFIG_OF=nEzequiel Garcia2014-04-16
| | | | | | | | | | | | | Just like the rest of the subsystems, let's add the required no-op functions to implement stubs when CONFIG_OF=n. This prevents MTD drivers from having ugly ifdefs in their code, and instead hide the ifdef monster in the header closet (far away from people's sight). Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00301290-5 usb: chipidea: imx: disable dpdm change wakeup at device modePeter Chen2014-04-16
| | | | | | | | | At imx6sx, there is a new feature that we can disable dpdm change wakeup at device mode when the vbus is not there, it can avoid unexpected wakeup when the phy is no power and imx6 is disconnected from host. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00301290-4 usb: phy-mxs: enable imx6sxPeter Chen2014-04-16
| | | | | | Add compatible string, etc. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00301290-3 usb: chipidea: enable usb for imx6sxPeter Chen2014-04-16
| | | | | | | | Add imx6sx compatible string, and enable bvalid as vbus wakeup source. When vbus as system wakeup source, only bvalid can be vbus wakeup source, the weak2p5 is needed to enable for vbus wakeup. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00301290-2 ARM: imx6sx: enable usbphy dummy clockPeter Chen2014-04-16
| | | | | | | | If usbphy is enabled, we need to enable usbphy dump clock, it is the requirement from IC engineer, it is used to guarantee some RTL operation correctness without software operation. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00301290-1 ARM: imx6sx: add usb supportPeter Chen2014-04-16
| | | | | | | - Add usbotg1 and usbotg2 support - Enable usbotg1 at arm2 board Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00301635 ARM: dts: imx6sx: add thermal monitor supportAnson Huang2014-04-16
| | | | | | add thermal monitor support for i.MX6SX. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00301650 ARM: dts: imx6sx: add anatop regulator supportRobin Gong2014-04-16
| | | | | | Enable Anatop regulator on imx6sx. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00301552-3 ARM: imx6sx: Add sgtl5000 support with SSI for 17x17 ARM2 boardNicolin Chen2014-04-16
| | | | | | | This patch adds SSI and sgtl5000 devicetree nodes for imx6sx 17x17 ARM2 board. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00301552-2 ARM: dtsi: Add SSI, ASRC and AUDMUX support for imx6sxNicolin Chen2014-04-16
| | | | | | | | | This patch adds default nodes for ASRC and AUDMUX/SSI for i.MX6 SoloX. It also appends two pin groups for AUDMUX. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00301552-1 ARM: imx6sx: Correct audio_clk in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | We currently has asrc_* clocks in the imx6sx clock tree while actually, according to the Reference Manual, all of them should be named after the audio_clk that controls the external MCLK output from MCLK pad of AUDMUX. Thus fix it along with its gate clock missing in the current clock tree. Meanwhile, this patch also configures a default clock rate for it -- 24MHz. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00301106 PXP: enable PXP in imx6sx-sdbFancy Fang2014-04-16
| | | | | | | Enable PXP module in imx6sx-sdb by default. This make sure PXP can be used in imx6sx-sdb. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* Xillybus driver added to Kconfig and Makefile in drivers/char/Eli Billauer2014-04-16
| | | | Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
* Add Xillybus driver to driver/char/ in a separate directoryEli Billauer2014-04-16
| | | | | | For more information about Xillybus, see http://xillybus.com Signed-off-by: Eli Billauer <eli.billauer@gmail.com>
* ENGR00301095 gpu:gpu hang when dma memory is used upLoren Huang2014-04-16
| | | | | | | | | | | | | When dma zone memory used up, gckOS_AllocateNonPagedMemory() will try to free non paged memory cache and allocate again. Such operation will cause twice memory mutex request and cause gpu driver hang. The solution is free the memory mutex at first before trying to free non paged memory cache. Date: Feb 27, 2014 Signed-off-by: Loren Huang <b02279@freescale.com> Acked-by: Shawn Guo
* mtd: nand: fix off-by-one read retry mode countingBrian Norris2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A flash may support N read retry voltage threshold modes, numbered 0 through N-1 (where mode 0 represents the initial state). However, nand_do_read_ops() tries to use mode 0 through N. This off-by-one error shows up, for instance, when using nanddump, and we have cycled through available modes: nand: setting READ RETRY mode 0 nand: setting READ RETRY mode 1 nand: setting READ RETRY mode 2 nand: setting READ RETRY mode 3 nand: setting READ RETRY mode 4 nand: setting READ RETRY mode 5 nand: setting READ RETRY mode 6 nand: setting READ RETRY mode 7 nand: setting READ RETRY mode 8 libmtd: error!: cannot read 8192 bytes from mtd0 (eraseblock 20, offset 0) error 22 (Invalid argument) nanddump: error!: mtd_read Tested on Micron MT29F64G08CBCBBH1, with 8 retry modes. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300939 ARM: dts: imx: Add power supply for imx6sx sdb lcdifSandor Yu2014-04-16
| | | | | | | -Change lcd1_reset pin to GPIO mode -Add regulator reg_lcd_3v3 for lcdif Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00300890-2 ARM: imx_v7{_mfg}_defconfig: enable the SPI-NOR frameworkHuang Shijie2014-04-16
| | | | | | enable the SPI NOR framework and the Quadspi driver. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300890-1 mtd: fix the build errorHuang Shijie2014-04-16
| | | | | | | | | | | | | | We may meet the built error: ------------------------------------------------------ drivers/built-in.o: In function `m25p_probe: clk-composite.c:(.text+0xed7b4): undefined reference to `spi_nor_scan drivers/built-in.o: In function `.LANCHOR1: clk-composite.c:(.data+0xe4a0): undefined reference to `spi_nor_ids make: *** [vmlinux] Error 1 ------------------------------------------------------ This error is caused by the missing dependency of SPI NOR framework. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-13 mtd: spi-nor: do not enable the quad mode for Micron NORHuang Shijie2014-04-16
| | | | | | | We use the Extended SPI protocol, and do not need to enable the Quad mode. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-12 ARM: clk: add a new helper which can re-parent the clockHuang Shijie2014-04-16
| | | | | | | | | | | | | The clock for qspi may be different when different NOR flashes are connected to the board. So the IMX6SX_CLK_QSPI1_SEL/IMX6SX_CLK_QSPI2_SEL should have the re-parent capability. This patch adds a new helper to register the clock which needs the re-parent capability. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-11 mtd: spi-nor: enable the quad read feature for n25q256aHuang Shijie2014-04-16
| | | | | | enable the quad read feature for n25q256a Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-10 ARM: dts: imx6sx-17x17-arm2: enable the qspi2Huang Shijie2014-04-16
| | | | | | enable the qspi2. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-9 ARM: dts: imx6sx: add the properties for QuadSpiHuang Shijie2014-04-16
| | | | | | add the qspi2 property and its pinctrl. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-8 mtd: fsl-quadspi: enable the DDR QUAD readHuang Shijie2014-04-16
| | | | | | enable the DDR quad read, this is the temporary code. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-7 mtd: spi-nor: Add Freescale QuadSPI driverHuang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (0) What is the QuadSPI controller? The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. (1) The QuadSPI controller is driven by the LUT(Look-up Table) registers. The LUT registers are a look-up-table for sequences of instructions. A valid sequence consists of four LUT registers. (2) The definition of the LUT register shows below: --------------------------------------------------- | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | --------------------------------------------------- There are several types of INSTRx, such as: CMD : the SPI NOR command. ADDR : the address for the SPI NOR command. DUMMY : the dummy cycles needed by the SPI NOR command. .... There are several types of PADx, such as: PAD1 : use a singe I/O line. PAD2 : use two I/O lines. PAD4 : use quad I/O lines. .... (3) Test this driver with the JFFS2 and UBIFS: For jffs2: ------------- #flash_eraseall /dev/mtd0 #mount -t jffs2 /dev/mtdblock0 tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 For ubifs: ------------- #flash_eraseall /dev/mtd0 #ubiattach /dev/ubi_ctrl -m 0 #ubimkvol /dev/ubi0 -N test -m #mount -t ubifs ubi0:test tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-6 Documentation: add the binding file for Freescale QuadSPI driverHuang Shijie2014-04-16
| | | | | | This patch adds the binding file for Freescale QuadSPI driver. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-5 mtd: spi-nor: add a helper to find the spi_device_idHuang Shijie2014-04-16
| | | | | | | Add the spi_nor_match_id() to find the proper spi_device_id with the NOR flash's name in the spi_nor_ids table. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-4 mtd: m25p80: use the SPI nor frameworkHuang Shijie2014-04-16
| | | | | | | | | | Use the new SPI nor framework, and rewrite the m25p80: (0) remove all the NOR comands. (1) change the m25p->command to an array. (2) implement the necessary hooks, such as m25p80_read/m25p80_write. Tested with the m25p32. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-3 mtd: spi-nor: add the framework for SPI NORHuang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer. Before this patch, the layer is like: MTD ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip After this patch, the layer is like: MTD ------------------------ spi-nor ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip With the spi-nor controller driver(Freescale Quadspi), it looks like: MTD ------------------------ spi-nor ------------------------ fsl-quadspi ------------------------ SPI NOR chip New APIs: spi_nor_scan: used to scan a spi-nor flash. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-2 mtd: spi-nor: add the basic data structuresHuang Shijie2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The spi_nor{} is cloned from the m25p{}. The spi_nor{} can be used by both the m25p80 and spi-nor controller. We also add the spi_nor_xfer_cfg{} which can be used by the two fundamental primitives: read_xfer/write_xfer. 1) the hooks for spi_nor{}: @prepare/unpreare: used to do some work before or after the read/write/erase/lock/unlock. @read_xfer/write_xfer: We can use these two hooks to code all the following hooks if the driver tries to implement them by itself. @read_reg: used to read the registers, such as read status register, read configure register. @write_reg: used to write the registers, such as write enable, erase sector. @read_id: read out the ID info. @wait_till_ready: wait till the NOR becomes ready. @read: read out the data from the NOR. @write: write data to the NOR. @erase: erase a sector of the NOR. 2) Add a new field sst_write_second for the SST NOR write. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-1 mtd: spi-nor: copy the SPI NOR commands to a new header fileHuang Shijie2014-04-16
| | | | | | | | | | This patch adds a new header :spi-nor.h, and copies all the SPI NOR commands and relative macros into this new header. This hearder can be used by the m25p80.c and other spi-nor controller, such as Freescale's Quadspi. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300745 ARM: dts: imx: Add lcdif support for imx6sx sdb boardSandor Yu2014-04-16
| | | | | | | | -Add pin mux setting for pwm3 in imx6sx.dtsi -Add pwm3 setting for lcdif backlight -Add lcdif1 in imx6sx-sdb.dtsi Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00300439-6 dts: imx6sx: add flexcan stop mode supportDong Aisheng2014-04-16
| | | | | | | Add flexcan stop mode support. The driver does not use alias id now, so remove it too. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00300439-5 can: flexcan: parse stop mode control bits from device treeDong Aisheng2014-04-16
| | | | | | | | | | Starting from IMX6, the flexcan stop mode control bits is SoC specific, move it out of IP driver and parse it from devicetree. It's good from maintain perspective and can avoid adding too many SoC specifi bits in driver but with no IP changes when the IMX SoC series keep growing. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00300439-4 dts: imx6sx-arm2: add flexcan supportDong Aisheng2014-04-16
| | | | | | Add flexcan support Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00300439-3 imx6sx: use auxdata for can transceiver settingDong Aisheng2014-04-16
| | | | | | | We still do not have a framework for can tranceiver settings. Use audxdata as workaround as before. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00300439-2 imx6sx: fix can_sel parent clockDong Aisheng2014-04-16
| | | | | | The default parent of can_sel clock is invalid, need manually set it. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00300439-1 dts: imx6sx-17x17-arm2: add usdhc2 and usdhc4 supportDong Aisheng2014-04-16
| | | | | | add usdhc2 and usdhc4 support Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00300665 ARM: dts: imx6sx-sdb: enable VGEN1 always onRobin Gong2014-04-16
| | | | | | | | On imx6sx-sdb board, there is one level shift between soc and enet phy chip, so need keep VGEN1 always on, else system can't mount NFS. Signed-off-by: Robin Gong <b38343@freescale.com>
* USB: EHCI: add delay during suspend to prevent erroneous wakeupsAlan Stern2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | High-speed USB connections revert back to full-speed signalling when the device goes into suspend. This takes several milliseconds, and during that time it's not possible to tell reliably whether the device has been disconnected. On some platforms, the Wake-On-Disconnect circuitry gets confused during this intermediate state. It generates a false wakeup signal, which can prevent the controller from going to sleep. To avoid this problem, this patch adds a 5-ms delay to the ehci_bus_suspend() routine if any ports have to switch over to full-speed signalling. (Actually, the delay was already present for devices using a particular kind of PHY power management; the patch merely causes the delay to be used more widely.) Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Reviewed-by: Peter Chen <Peter.Chen@freescale.com> CC: <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Conflicts: drivers/usb/host/ehci-hub.c
* ENGR00300479-2 ARM: dts: imx6sx-sdb: Add pfuze supportRobin Gong2014-04-16
| | | | | | Add pfuze pmic driver support for imx6sx-sdb board Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00300479-1 ARM: dts: imx6sx-17x17-arm2: Add pfuze supportRobin Gong2014-04-16
| | | | | | Add pfuze support on imx6sx-17x17-arm2 board Signed-off-by: Robin Gong <b38343@freescale.com>
* clk: export fixed-factor, gate & mux registrationMike Turquette2014-04-16
| | | | | | | These registration calls may be used by loadable modules. Export them. Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: mux: Add support for read-only muxes.Tomasz Figa2014-04-16
| | | | | | | | | | | Some platforms have read-only clock muxes that are preconfigured at reset and cannot be changed at runtime. This patch extends mux clock driver to allow handling such read-only muxes by adding new CLK_MUX_READ_ONLY mux flag. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* clk: mux: add CLK_MUX_HIWORD_MASKHaojian Zhuang2014-04-16
| | | | | | | | | | | | | | | | In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds mux flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
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