diff options
| author | Robin Gong <b38343@freescale.com> | 2014-03-03 23:55:50 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:57:48 -0400 |
| commit | 580acfb5288e872f91c64a26ed4c1dcd96fb9457 (patch) | |
| tree | 67219412a1b518ad251a59551eeab4f462959c29 | |
| parent | fa4466773aab9b2af84c23720a56c257da1583f1 (diff) | |
ENGR00301650 ARM: dts: imx6sx: add anatop regulator support
Enable Anatop regulator on imx6sx.
Signed-off-by: Robin Gong <b38343@freescale.com>
| -rw-r--r-- | arch/arm/boot/dts/imx6sx.dtsi | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index f6b35b7fa659..b50bb66d35b9 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi | |||
| @@ -204,6 +204,98 @@ | |||
| 204 | "syscon", "simple-bus"; | 204 | "syscon", "simple-bus"; |
| 205 | reg = <0x020c8000 0x1000>; | 205 | reg = <0x020c8000 0x1000>; |
| 206 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; | 206 | interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; |
| 207 | |||
| 208 | regulator-1p1@110 { | ||
| 209 | compatible = "fsl,anatop-regulator"; | ||
| 210 | regulator-name = "vdd1p1"; | ||
| 211 | regulator-min-microvolt = <800000>; | ||
| 212 | regulator-max-microvolt = <1375000>; | ||
| 213 | regulator-always-on; | ||
| 214 | anatop-reg-offset = <0x110>; | ||
| 215 | anatop-vol-bit-shift = <8>; | ||
| 216 | anatop-vol-bit-width = <5>; | ||
| 217 | anatop-min-bit-val = <4>; | ||
| 218 | anatop-min-voltage = <800000>; | ||
| 219 | anatop-max-voltage = <1375000>; | ||
| 220 | }; | ||
| 221 | |||
| 222 | regulator-3p0@120 { | ||
| 223 | compatible = "fsl,anatop-regulator"; | ||
| 224 | regulator-name = "vdd3p0"; | ||
| 225 | regulator-min-microvolt = <2800000>; | ||
| 226 | regulator-max-microvolt = <3150000>; | ||
| 227 | regulator-always-on; | ||
| 228 | anatop-reg-offset = <0x120>; | ||
| 229 | anatop-vol-bit-shift = <8>; | ||
| 230 | anatop-vol-bit-width = <5>; | ||
| 231 | anatop-min-bit-val = <0>; | ||
| 232 | anatop-min-voltage = <2625000>; | ||
| 233 | anatop-max-voltage = <3400000>; | ||
| 234 | }; | ||
| 235 | |||
| 236 | regulator-2p5@130 { | ||
| 237 | compatible = "fsl,anatop-regulator"; | ||
| 238 | regulator-name = "vdd2p5"; | ||
| 239 | regulator-min-microvolt = <2100000>; | ||
| 240 | regulator-max-microvolt = <2875000>; | ||
| 241 | regulator-always-on; | ||
| 242 | anatop-reg-offset = <0x130>; | ||
| 243 | anatop-vol-bit-shift = <8>; | ||
| 244 | anatop-vol-bit-width = <5>; | ||
| 245 | anatop-min-bit-val = <0>; | ||
| 246 | anatop-min-voltage = <2100000>; | ||
| 247 | anatop-max-voltage = <2875000>; | ||
| 248 | }; | ||
| 249 | |||
| 250 | reg_arm: regulator-vddcore@140 { | ||
| 251 | compatible = "fsl,anatop-regulator"; | ||
| 252 | regulator-name = "cpu"; | ||
| 253 | regulator-min-microvolt = <725000>; | ||
| 254 | regulator-max-microvolt = <1450000>; | ||
| 255 | regulator-always-on; | ||
| 256 | anatop-reg-offset = <0x140>; | ||
| 257 | anatop-vol-bit-shift = <0>; | ||
| 258 | anatop-vol-bit-width = <5>; | ||
| 259 | anatop-delay-reg-offset = <0x170>; | ||
| 260 | anatop-delay-bit-shift = <24>; | ||
| 261 | anatop-delay-bit-width = <2>; | ||
| 262 | anatop-min-bit-val = <1>; | ||
| 263 | anatop-min-voltage = <725000>; | ||
| 264 | anatop-max-voltage = <1450000>; | ||
| 265 | }; | ||
| 266 | |||
| 267 | reg_pcie: regulator-vddpcie@140 { | ||
| 268 | compatible = "fsl,anatop-regulator"; | ||
| 269 | regulator-name = "vddpcie"; | ||
| 270 | regulator-min-microvolt = <725000>; | ||
| 271 | regulator-max-microvolt = <1450000>; | ||
| 272 | anatop-reg-offset = <0x140>; | ||
| 273 | anatop-vol-bit-shift = <9>; | ||
| 274 | anatop-vol-bit-width = <5>; | ||
| 275 | anatop-delay-reg-offset = <0x170>; | ||
| 276 | anatop-delay-bit-shift = <26>; | ||
| 277 | anatop-delay-bit-width = <2>; | ||
| 278 | anatop-min-bit-val = <1>; | ||
| 279 | anatop-min-voltage = <725000>; | ||
| 280 | anatop-max-voltage = <1450000>; | ||
| 281 | }; | ||
| 282 | |||
| 283 | reg_soc: regulator-vddsoc@140 { | ||
| 284 | compatible = "fsl,anatop-regulator"; | ||
| 285 | regulator-name = "vddsoc"; | ||
| 286 | regulator-min-microvolt = <725000>; | ||
| 287 | regulator-max-microvolt = <1450000>; | ||
| 288 | regulator-always-on; | ||
| 289 | anatop-reg-offset = <0x140>; | ||
| 290 | anatop-vol-bit-shift = <18>; | ||
| 291 | anatop-vol-bit-width = <5>; | ||
| 292 | anatop-delay-reg-offset = <0x170>; | ||
| 293 | anatop-delay-bit-shift = <28>; | ||
| 294 | anatop-delay-bit-width = <2>; | ||
| 295 | anatop-min-bit-val = <1>; | ||
| 296 | anatop-min-voltage = <725000>; | ||
| 297 | anatop-max-voltage = <1450000>; | ||
| 298 | }; | ||
| 207 | }; | 299 | }; |
| 208 | 300 | ||
| 209 | flexcan1: can@02090000 { | 301 | flexcan1: can@02090000 { |