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path: root/drivers/net/wireless/ath/ath9k/ar9003_phy.h
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Diffstat (limited to 'drivers/net/wireless/ath/ath9k/ar9003_phy.h')
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 9fe6fbeb66d0..2f4023e66081 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -325,10 +325,10 @@
325 325
326#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200) 326#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
327 327
328#define AR_PHY_CCA_NOM_VAL_9300_2GHZ (AR_SREV_9480(ah) ? -127 : -110) 328#define AR_PHY_CCA_NOM_VAL_9300_2GHZ (AR_SREV_9462(ah) ? -127 : -110)
329#define AR_PHY_CCA_NOM_VAL_9300_5GHZ (AR_SREV_9480(ah) ? -127 : -115) 329#define AR_PHY_CCA_NOM_VAL_9300_5GHZ (AR_SREV_9462(ah) ? -127 : -115)
330#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ (AR_SREV_9480(ah) ? -127 : -125) 330#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ (AR_SREV_9462(ah) ? -127 : -125)
331#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ (AR_SREV_9480(ah) ? -127 : -125) 331#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ (AR_SREV_9462(ah) ? -127 : -125)
332#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95 332#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
333#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100 333#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
334 334
@@ -608,9 +608,9 @@
608#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4) 608#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
609#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8) 609#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
610#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc) 610#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
611#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \ 611#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \
612 0x4c0 : 0x4c4)) 612 0x4c0 : 0x4c4))
613#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \ 613#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \
614 0x4c4 : 0x4c8)) 614 0x4c4 : 0x4c8))
615#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0) 615#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
616#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc) 616#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
@@ -625,7 +625,7 @@
625#define AR_PHY_65NM_CH0_RXTX4 0x1610c 625#define AR_PHY_65NM_CH0_RXTX4 0x1610c
626 626
627#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ 627#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
628 ((AR_SREV_9480(ah) ? 0x1628c : 0x16280))) 628 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
629#define AR_CH0_TOP_XPABIASLVL (0x300) 629#define AR_CH0_TOP_XPABIASLVL (0x300)
630#define AR_CH0_TOP_XPABIASLVL_S (8) 630#define AR_CH0_TOP_XPABIASLVL_S (8)
631 631
@@ -638,8 +638,8 @@
638 638
639#define AR_SWITCH_TABLE_COM_ALL (0xffff) 639#define AR_SWITCH_TABLE_COM_ALL (0xffff)
640#define AR_SWITCH_TABLE_COM_ALL_S (0) 640#define AR_SWITCH_TABLE_COM_ALL_S (0)
641#define AR_SWITCH_TABLE_COM_AR9480_ALL (0xffffff) 641#define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)
642#define AR_SWITCH_TABLE_COM_AR9480_ALL_S (0) 642#define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)
643#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000) 643#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
644#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0) 644#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
645#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4) 645#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
@@ -679,11 +679,11 @@
679#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 679#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
680#define AR_CH0_XTAL_CAPOUTDAC_S 17 680#define AR_CH0_XTAL_CAPOUTDAC_S 17
681 681
682#define AR_PHY_PMU1 (AR_SREV_9480(ah) ? 0x16340 : 0x16c40) 682#define AR_PHY_PMU1 (AR_SREV_9462(ah) ? 0x16340 : 0x16c40)
683#define AR_PHY_PMU1_PWD 0x1 683#define AR_PHY_PMU1_PWD 0x1
684#define AR_PHY_PMU1_PWD_S 0 684#define AR_PHY_PMU1_PWD_S 0
685 685
686#define AR_PHY_PMU2 (AR_SREV_9480(ah) ? 0x16344 : 0x16c44) 686#define AR_PHY_PMU2 (AR_SREV_9462(ah) ? 0x16344 : 0x16c44)
687#define AR_PHY_PMU2_PGM 0x00200000 687#define AR_PHY_PMU2_PGM 0x00200000
688#define AR_PHY_PMU2_PGM_S 21 688#define AR_PHY_PMU2_PGM_S 21
689 689
@@ -921,9 +921,9 @@
921#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0) 921#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
922#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4) 922#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
923#define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8) 923#define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8)
924#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \ 924#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
925 0x4c0 : 0x4c4)) 925 0x4c0 : 0x4c4))
926#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \ 926#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
927 0x4c4 : 0x4c8)) 927 0x4c4 : 0x4c8))
928#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0) 928#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0)
929#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc) 929#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc)
@@ -1001,7 +1001,7 @@
1001#define AR_GLB_BASE 0x20000 1001#define AR_GLB_BASE 0x20000
1002#define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44) 1002#define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44)
1003#define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \ 1003#define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \
1004 (AR_SREV_9480_20(_ah) ? 0x4c : 0x50)) 1004 (AR_SREV_9462_20(_ah) ? 0x4c : 0x50))
1005#define AR_GLB_STATUS (AR_GLB_BASE + 0x48) 1005#define AR_GLB_STATUS (AR_GLB_BASE + 0x48)
1006 1006
1007/* 1007/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 05:47:22 -0500