aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c18
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c182
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_paprd.c6
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h28
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h62
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h68
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/gpio.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c28
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h28
14 files changed, 221 insertions, 221 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index bf08accccbe4..3b262ba6b172 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -3556,7 +3556,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3556 3556
3557 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) 3557 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3558 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); 3558 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3559 else if (AR_SREV_9480(ah)) 3559 else if (AR_SREV_9462(ah))
3560 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3560 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3561 else { 3561 else {
3562 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3562 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
@@ -3635,20 +3635,20 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3635 3635
3636 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); 3636 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3637 3637
3638 if (AR_SREV_9480(ah)) { 3638 if (AR_SREV_9462(ah)) {
3639 if (AR_SREV_9480_10(ah)) { 3639 if (AR_SREV_9462_10(ah)) {
3640 value &= ~AR_SWITCH_TABLE_COM_SPDT; 3640 value &= ~AR_SWITCH_TABLE_COM_SPDT;
3641 value |= 0x00100000; 3641 value |= 0x00100000;
3642 } 3642 }
3643 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3643 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3644 AR_SWITCH_TABLE_COM_AR9480_ALL, value); 3644 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3645 } else 3645 } else
3646 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, 3646 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3647 AR_SWITCH_TABLE_COM_ALL, value); 3647 AR_SWITCH_TABLE_COM_ALL, value);
3648 3648
3649 3649
3650 /* 3650 /*
3651 * AR9480 defines new switch table for BT/WLAN, 3651 * AR9462 defines new switch table for BT/WLAN,
3652 * here's new field name in XXX.ref for both 2G and 5G. 3652 * here's new field name in XXX.ref for both 2G and 5G.
3653 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044) 3653 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3654 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX 3654 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
@@ -3660,7 +3660,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3660 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE 3660 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3661 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE 3661 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3662 */ 3662 */
3663 if (AR_SREV_9480_20_OR_LATER(ah)) { 3663 if (AR_SREV_9462_20_OR_LATER(ah)) {
3664 value = ar9003_switch_com_spdt_get(ah, is2ghz); 3664 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3665 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, 3665 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3666 AR_SWITCH_TABLE_COM_SPDT_ALL, value); 3666 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
@@ -3909,7 +3909,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3909 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); 3909 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3910 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3910 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3911 return; 3911 return;
3912 } else if (AR_SREV_9480(ah)) { 3912 } else if (AR_SREV_9462(ah)) {
3913 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG); 3913 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3914 REG_WRITE(ah, AR_PHY_PMU1, reg_val); 3914 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3915 } else { 3915 } else {
@@ -3940,7 +3940,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3940 while (!REG_READ_FIELD(ah, AR_PHY_PMU2, 3940 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3941 AR_PHY_PMU2_PGM)) 3941 AR_PHY_PMU2_PGM))
3942 udelay(10); 3942 udelay(10);
3943 } else if (AR_SREV_9480(ah)) 3943 } else if (AR_SREV_9462(ah))
3944 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); 3944 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3945 else { 3945 else {
3946 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | 3946 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
@@ -4527,7 +4527,7 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
4527 4527
4528 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope); 4528 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4529 4529
4530 if (AR_SREV_9480_20(ah)) 4530 if (AR_SREV_9462_20(ah))
4531 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, 4531 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4532 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope); 4532 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4533 4533
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 6b2a4d0f60af..fb937ba93e0c 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -35,13 +35,13 @@
35static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 35static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
36{ 36{
37#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \ 37#define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
38 ar9480_pciephy_pll_on_clkreq_disable_L1_2p0 38 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
39 39
40#define AR9480_BB_CTX_COEFJ(x) \ 40#define AR9462_BB_CTX_COEFJ(x) \
41 ar9480_##x##_baseband_core_txfir_coeff_japan_2484 41 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
42 42
43#define AR9480_BBC_TXIFR_COEFFJ \ 43#define AR9462_BBC_TXIFR_COEFFJ \
44 ar9480_2p0_baseband_core_txfir_coeff_japan_2484 44 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
45 if (AR_SREV_9330_11(ah)) { 45 if (AR_SREV_9330_11(ah)) {
46 /* mac */ 46 /* mac */
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@@ -264,107 +264,107 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
264 ar9485_1_1_pcie_phy_clkreq_disable_L1, 264 ar9485_1_1_pcie_phy_clkreq_disable_L1,
265 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1), 265 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
266 2); 266 2);
267 } else if (AR_SREV_9480_10(ah)) { 267 } else if (AR_SREV_9462_10(ah)) {
268 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 268 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
269 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9480_1p0_mac_core, 269 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_1p0_mac_core,
270 ARRAY_SIZE(ar9480_1p0_mac_core), 2); 270 ARRAY_SIZE(ar9462_1p0_mac_core), 2);
271 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 271 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
272 ar9480_1p0_mac_postamble, 272 ar9462_1p0_mac_postamble,
273 ARRAY_SIZE(ar9480_1p0_mac_postamble), 273 ARRAY_SIZE(ar9462_1p0_mac_postamble),
274 5); 274 5);
275 275
276 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 276 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
277 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 277 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
278 ar9480_1p0_baseband_core, 278 ar9462_1p0_baseband_core,
279 ARRAY_SIZE(ar9480_1p0_baseband_core), 279 ARRAY_SIZE(ar9462_1p0_baseband_core),
280 2); 280 2);
281 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 281 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
282 ar9480_1p0_baseband_postamble, 282 ar9462_1p0_baseband_postamble,
283 ARRAY_SIZE(ar9480_1p0_baseband_postamble), 5); 283 ARRAY_SIZE(ar9462_1p0_baseband_postamble), 5);
284 284
285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
286 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 286 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
287 ar9480_1p0_radio_core, 287 ar9462_1p0_radio_core,
288 ARRAY_SIZE(ar9480_1p0_radio_core), 2); 288 ARRAY_SIZE(ar9462_1p0_radio_core), 2);
289 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 289 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
290 ar9480_1p0_radio_postamble, 290 ar9462_1p0_radio_postamble,
291 ARRAY_SIZE(ar9480_1p0_radio_postamble), 5); 291 ARRAY_SIZE(ar9462_1p0_radio_postamble), 5);
292 292
293 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 293 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
294 ar9480_1p0_soc_preamble, 294 ar9462_1p0_soc_preamble,
295 ARRAY_SIZE(ar9480_1p0_soc_preamble), 2); 295 ARRAY_SIZE(ar9462_1p0_soc_preamble), 2);
296 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 296 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
297 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 297 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
298 ar9480_1p0_soc_postamble, 298 ar9462_1p0_soc_postamble,
299 ARRAY_SIZE(ar9480_1p0_soc_postamble), 5); 299 ARRAY_SIZE(ar9462_1p0_soc_postamble), 5);
300 300
301 INIT_INI_ARRAY(&ah->iniModesRxGain, 301 INIT_INI_ARRAY(&ah->iniModesRxGain,
302 ar9480_common_rx_gain_table_1p0, 302 ar9462_common_rx_gain_table_1p0,
303 ARRAY_SIZE(ar9480_common_rx_gain_table_1p0), 2); 303 ARRAY_SIZE(ar9462_common_rx_gain_table_1p0), 2);
304 304
305 /* Awake -> Sleep Setting */ 305 /* Awake -> Sleep Setting */
306 INIT_INI_ARRAY(&ah->iniPcieSerdes, 306 INIT_INI_ARRAY(&ah->iniPcieSerdes,
307 ar9480_pcie_phy_clkreq_disable_L1_1p0, 307 ar9462_pcie_phy_clkreq_disable_L1_1p0,
308 ARRAY_SIZE(ar9480_pcie_phy_clkreq_disable_L1_1p0), 308 ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),
309 2); 309 2);
310 310
311 /* Sleep -> Awake Setting */ 311 /* Sleep -> Awake Setting */
312 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 312 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
313 ar9480_pcie_phy_clkreq_disable_L1_1p0, 313 ar9462_pcie_phy_clkreq_disable_L1_1p0,
314 ARRAY_SIZE(ar9480_pcie_phy_clkreq_disable_L1_1p0), 314 ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),
315 2); 315 2);
316 316
317 INIT_INI_ARRAY(&ah->iniModesAdditional, 317 INIT_INI_ARRAY(&ah->iniModesAdditional,
318 ar9480_modes_fast_clock_1p0, 318 ar9462_modes_fast_clock_1p0,
319 ARRAY_SIZE(ar9480_modes_fast_clock_1p0), 3); 319 ARRAY_SIZE(ar9462_modes_fast_clock_1p0), 3);
320 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 320 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
321 AR9480_BB_CTX_COEFJ(1p0), 321 AR9462_BB_CTX_COEFJ(1p0),
322 ARRAY_SIZE(AR9480_BB_CTX_COEFJ(1p0)), 2); 322 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(1p0)), 2);
323 323
324 } else if (AR_SREV_9480_20(ah)) { 324 } else if (AR_SREV_9462_20(ah)) {
325 325
326 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 326 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
327 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9480_2p0_mac_core, 327 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
328 ARRAY_SIZE(ar9480_2p0_mac_core), 2); 328 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
329 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 329 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
330 ar9480_2p0_mac_postamble, 330 ar9462_2p0_mac_postamble,
331 ARRAY_SIZE(ar9480_2p0_mac_postamble), 5); 331 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
332 332
333 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0); 333 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
334 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 334 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
335 ar9480_2p0_baseband_core, 335 ar9462_2p0_baseband_core,
336 ARRAY_SIZE(ar9480_2p0_baseband_core), 2); 336 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
337 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 337 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
338 ar9480_2p0_baseband_postamble, 338 ar9462_2p0_baseband_postamble,
339 ARRAY_SIZE(ar9480_2p0_baseband_postamble), 5); 339 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
340 340
341 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0); 341 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
342 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 342 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
343 ar9480_2p0_radio_core, 343 ar9462_2p0_radio_core,
344 ARRAY_SIZE(ar9480_2p0_radio_core), 2); 344 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
345 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 345 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
346 ar9480_2p0_radio_postamble, 346 ar9462_2p0_radio_postamble,
347 ARRAY_SIZE(ar9480_2p0_radio_postamble), 5); 347 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
348 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 348 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
349 ar9480_2p0_radio_postamble_sys2ant, 349 ar9462_2p0_radio_postamble_sys2ant,
350 ARRAY_SIZE(ar9480_2p0_radio_postamble_sys2ant), 350 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
351 5); 351 5);
352 352
353 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 353 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
354 ar9480_2p0_soc_preamble, 354 ar9462_2p0_soc_preamble,
355 ARRAY_SIZE(ar9480_2p0_soc_preamble), 2); 355 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
356 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0); 356 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
357 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 357 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
358 ar9480_2p0_soc_postamble, 358 ar9462_2p0_soc_postamble,
359 ARRAY_SIZE(ar9480_2p0_soc_postamble), 5); 359 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
360 360
361 INIT_INI_ARRAY(&ah->iniModesRxGain, 361 INIT_INI_ARRAY(&ah->iniModesRxGain,
362 ar9480_common_rx_gain_table_2p0, 362 ar9462_common_rx_gain_table_2p0,
363 ARRAY_SIZE(ar9480_common_rx_gain_table_2p0), 2); 363 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
364 364
365 INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR, 365 INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR,
366 ar9480_2p0_BTCOEX_MAX_TXPWR_table, 366 ar9462_2p0_BTCOEX_MAX_TXPWR_table,
367 ARRAY_SIZE(ar9480_2p0_BTCOEX_MAX_TXPWR_table), 367 ARRAY_SIZE(ar9462_2p0_BTCOEX_MAX_TXPWR_table),
368 2); 368 2);
369 369
370 /* Awake -> Sleep Setting */ 370 /* Awake -> Sleep Setting */
@@ -380,15 +380,15 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
380 380
381 /* Fast clock modal settings */ 381 /* Fast clock modal settings */
382 INIT_INI_ARRAY(&ah->iniModesAdditional, 382 INIT_INI_ARRAY(&ah->iniModesAdditional,
383 ar9480_modes_fast_clock_2p0, 383 ar9462_modes_fast_clock_2p0,
384 ARRAY_SIZE(ar9480_modes_fast_clock_2p0), 3); 384 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
385 385
386 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 386 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
387 AR9480_BB_CTX_COEFJ(2p0), 387 AR9462_BB_CTX_COEFJ(2p0),
388 ARRAY_SIZE(AR9480_BB_CTX_COEFJ(2p0)), 2); 388 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
389 389
390 INIT_INI_ARRAY(&ah->ini_japan2484, AR9480_BBC_TXIFR_COEFFJ, 390 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
391 ARRAY_SIZE(AR9480_BBC_TXIFR_COEFFJ), 2); 391 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
392 392
393 } else if (AR_SREV_9580(ah)) { 393 } else if (AR_SREV_9580(ah)) {
394 /* mac */ 394 /* mac */
@@ -537,15 +537,15 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
537 ar9580_1p0_lowest_ob_db_tx_gain_table, 537 ar9580_1p0_lowest_ob_db_tx_gain_table,
538 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table), 538 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
539 5); 539 5);
540 else if (AR_SREV_9480_10(ah)) 540 else if (AR_SREV_9462_10(ah))
541 INIT_INI_ARRAY(&ah->iniModesTxGain, 541 INIT_INI_ARRAY(&ah->iniModesTxGain,
542 ar9480_modes_low_ob_db_tx_gain_table_1p0, 542 ar9462_modes_low_ob_db_tx_gain_table_1p0,
543 ARRAY_SIZE(ar9480_modes_low_ob_db_tx_gain_table_1p0), 543 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_1p0),
544 5); 544 5);
545 else if (AR_SREV_9480_20(ah)) 545 else if (AR_SREV_9462_20(ah))
546 INIT_INI_ARRAY(&ah->iniModesTxGain, 546 INIT_INI_ARRAY(&ah->iniModesTxGain,
547 ar9480_modes_low_ob_db_tx_gain_table_2p0, 547 ar9462_modes_low_ob_db_tx_gain_table_2p0,
548 ARRAY_SIZE(ar9480_modes_low_ob_db_tx_gain_table_2p0), 548 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
549 5); 549 5);
550 else 550 else
551 INIT_INI_ARRAY(&ah->iniModesTxGain, 551 INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -581,15 +581,15 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
581 ar9580_1p0_high_ob_db_tx_gain_table, 581 ar9580_1p0_high_ob_db_tx_gain_table,
582 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table), 582 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
583 5); 583 5);
584 else if (AR_SREV_9480_10(ah)) 584 else if (AR_SREV_9462_10(ah))
585 INIT_INI_ARRAY(&ah->iniModesTxGain, 585 INIT_INI_ARRAY(&ah->iniModesTxGain,
586 ar9480_modes_high_ob_db_tx_gain_table_1p0, 586 ar9462_modes_high_ob_db_tx_gain_table_1p0,
587 ARRAY_SIZE(ar9480_modes_high_ob_db_tx_gain_table_1p0), 587 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_1p0),
588 5); 588 5);
589 else if (AR_SREV_9480_20(ah)) 589 else if (AR_SREV_9462_20(ah))
590 INIT_INI_ARRAY(&ah->iniModesTxGain, 590 INIT_INI_ARRAY(&ah->iniModesTxGain,
591 ar9480_modes_high_ob_db_tx_gain_table_2p0, 591 ar9462_modes_high_ob_db_tx_gain_table_2p0,
592 ARRAY_SIZE(ar9480_modes_high_ob_db_tx_gain_table_2p0), 592 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
593 5); 593 5);
594 else 594 else
595 INIT_INI_ARRAY(&ah->iniModesTxGain, 595 INIT_INI_ARRAY(&ah->iniModesTxGain,
@@ -712,15 +712,15 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
712 ar9580_1p0_rx_gain_table, 712 ar9580_1p0_rx_gain_table,
713 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 713 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
714 2); 714 2);
715 else if (AR_SREV_9480_10(ah)) 715 else if (AR_SREV_9462_10(ah))
716 INIT_INI_ARRAY(&ah->iniModesRxGain, 716 INIT_INI_ARRAY(&ah->iniModesRxGain,
717 ar9480_common_rx_gain_table_1p0, 717 ar9462_common_rx_gain_table_1p0,
718 ARRAY_SIZE(ar9480_common_rx_gain_table_1p0), 718 ARRAY_SIZE(ar9462_common_rx_gain_table_1p0),
719 2); 719 2);
720 else if (AR_SREV_9480_20(ah)) 720 else if (AR_SREV_9462_20(ah))
721 INIT_INI_ARRAY(&ah->iniModesRxGain, 721 INIT_INI_ARRAY(&ah->iniModesRxGain,
722 ar9480_common_rx_gain_table_2p0, 722 ar9462_common_rx_gain_table_2p0,
723 ARRAY_SIZE(ar9480_common_rx_gain_table_2p0), 723 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
724 2); 724 2);
725 else 725 else
726 INIT_INI_ARRAY(&ah->iniModesRxGain, 726 INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -751,15 +751,15 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
751 ar9485Common_wo_xlna_rx_gain_1_1, 751 ar9485Common_wo_xlna_rx_gain_1_1,
752 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 752 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
753 2); 753 2);
754 else if (AR_SREV_9480_10(ah)) 754 else if (AR_SREV_9462_10(ah))
755 INIT_INI_ARRAY(&ah->iniModesRxGain, 755 INIT_INI_ARRAY(&ah->iniModesRxGain,
756 ar9480_common_wo_xlna_rx_gain_table_1p0, 756 ar9462_common_wo_xlna_rx_gain_table_1p0,
757 ARRAY_SIZE(ar9480_common_wo_xlna_rx_gain_table_1p0), 757 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_1p0),
758 2); 758 2);
759 else if (AR_SREV_9480_20(ah)) 759 else if (AR_SREV_9462_20(ah))
760 INIT_INI_ARRAY(&ah->iniModesRxGain, 760 INIT_INI_ARRAY(&ah->iniModesRxGain,
761 ar9480_common_wo_xlna_rx_gain_table_2p0, 761 ar9462_common_wo_xlna_rx_gain_table_2p0,
762 ARRAY_SIZE(ar9480_common_wo_xlna_rx_gain_table_2p0), 762 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
763 2); 763 2);
764 else if (AR_SREV_9580(ah)) 764 else if (AR_SREV_9580(ah))
765 INIT_INI_ARRAY(&ah->iniModesRxGain, 765 INIT_INI_ARRAY(&ah->iniModesRxGain,
@@ -775,14 +775,14 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
775 775
776static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) 776static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
777{ 777{
778 if (AR_SREV_9480_10(ah)) 778 if (AR_SREV_9462_10(ah))
779 INIT_INI_ARRAY(&ah->iniModesRxGain, 779 INIT_INI_ARRAY(&ah->iniModesRxGain,
780 ar9480_common_mixed_rx_gain_table_1p0, 780 ar9462_common_mixed_rx_gain_table_1p0,
781 ARRAY_SIZE(ar9480_common_mixed_rx_gain_table_1p0), 2); 781 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_1p0), 2);
782 else if (AR_SREV_9480_20(ah)) 782 else if (AR_SREV_9462_20(ah))
783 INIT_INI_ARRAY(&ah->iniModesRxGain, 783 INIT_INI_ARRAY(&ah->iniModesRxGain,
784 ar9480_common_mixed_rx_gain_table_2p0, 784 ar9462_common_mixed_rx_gain_table_2p0,
785 ARRAY_SIZE(ar9480_common_mixed_rx_gain_table_2p0), 2); 785 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
786} 786}
787 787
788static void ar9003_rx_gain_table_apply(struct ath_hw *ah) 788static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index a1a08b31b33d..0c462c904cbe 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -200,7 +200,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
200 AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28); 200 AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING, 28);
201 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1, 201 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
202 AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1); 202 AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE, 1);
203 val = AR_SREV_9480(ah) ? 0x91 : 147; 203 val = AR_SREV_9462(ah) ? 0x91 : 147;
204 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2, 204 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL2,
205 AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, val); 205 AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN, val);
206 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 206 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
@@ -211,7 +211,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
211 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7); 211 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
212 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 212 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
213 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1); 213 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
214 if (AR_SREV_9485(ah) || AR_SREV_9480(ah)) 214 if (AR_SREV_9485(ah) || AR_SREV_9462(ah))
215 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 215 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
216 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, 216 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
217 -3); 217 -3);
@@ -219,7 +219,7 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
219 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 219 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
220 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, 220 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
221 -6); 221 -6);
222 val = AR_SREV_9480(ah) ? -10 : -15; 222 val = AR_SREV_9462(ah) ? -10 : -15;
223 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3, 223 REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
224 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE, 224 AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,
225 val); 225 val);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index f38307eb24b8..fe96997921d3 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -559,7 +559,7 @@ static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
559 559
560 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) 560 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
561 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 561 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
562 else if (AR_SREV_9480(ah)) 562 else if (AR_SREV_9462(ah))
563 /* xxx only when MCI support is enabled */ 563 /* xxx only when MCI support is enabled */
564 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); 564 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
565 else 565 else
@@ -662,7 +662,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
662 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); 662 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
663 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); 663 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
664 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); 664 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
665 if (i == ATH_INI_POST && AR_SREV_9480_20(ah)) 665 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
666 ar9003_hw_prog_ini(ah, 666 ar9003_hw_prog_ini(ah,
667 &ah->ini_radio_post_sys2ant, 667 &ah->ini_radio_post_sys2ant,
668 modesIndex); 668 modesIndex);
@@ -685,7 +685,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
685 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) 685 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
686 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); 686 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
687 687
688 if (AR_SREV_9480(ah)) 688 if (AR_SREV_9462(ah))
689 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1); 689 ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);
690 690
691 ah->modes_index = modesIndex; 691 ah->modes_index = modesIndex;
@@ -694,7 +694,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
694 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 694 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
695 ath9k_hw_apply_txpower(ah, chan); 695 ath9k_hw_apply_txpower(ah, chan);
696 696
697 if (AR_SREV_9480(ah)) { 697 if (AR_SREV_9462(ah)) {
698 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, 698 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
699 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) 699 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
700 ah->enabled_cals |= TX_IQ_CAL; 700 ah->enabled_cals |= TX_IQ_CAL;
@@ -1300,7 +1300,7 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1300 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); 1300 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1301 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); 1301 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1302 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); 1302 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1303 if (AR_SREV_9480_20(ah)) 1303 if (AR_SREV_9462_20(ah))
1304 ar9003_hw_prog_ini(ah, 1304 ar9003_hw_prog_ini(ah,
1305 &ah->ini_radio_post_sys2ant, 1305 &ah->ini_radio_post_sys2ant,
1306 modesIndex); 1306 modesIndex);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 9fe6fbeb66d0..2f4023e66081 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -325,10 +325,10 @@
325 325
326#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200) 326#define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
327 327
328#define AR_PHY_CCA_NOM_VAL_9300_2GHZ (AR_SREV_9480(ah) ? -127 : -110) 328#define AR_PHY_CCA_NOM_VAL_9300_2GHZ (AR_SREV_9462(ah) ? -127 : -110)
329#define AR_PHY_CCA_NOM_VAL_9300_5GHZ (AR_SREV_9480(ah) ? -127 : -115) 329#define AR_PHY_CCA_NOM_VAL_9300_5GHZ (AR_SREV_9462(ah) ? -127 : -115)
330#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ (AR_SREV_9480(ah) ? -127 : -125) 330#define AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ (AR_SREV_9462(ah) ? -127 : -125)
331#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ (AR_SREV_9480(ah) ? -127 : -125) 331#define AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ (AR_SREV_9462(ah) ? -127 : -125)
332#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95 332#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
333#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100 333#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
334 334
@@ -608,9 +608,9 @@
608#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4) 608#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
609#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8) 609#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
610#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc) 610#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
611#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \ 611#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \
612 0x4c0 : 0x4c4)) 612 0x4c0 : 0x4c4))
613#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9480_10(ah) ? \ 613#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \
614 0x4c4 : 0x4c8)) 614 0x4c4 : 0x4c8))
615#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0) 615#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
616#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc) 616#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
@@ -625,7 +625,7 @@
625#define AR_PHY_65NM_CH0_RXTX4 0x1610c 625#define AR_PHY_65NM_CH0_RXTX4 0x1610c
626 626
627#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ 627#define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
628 ((AR_SREV_9480(ah) ? 0x1628c : 0x16280))) 628 ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
629#define AR_CH0_TOP_XPABIASLVL (0x300) 629#define AR_CH0_TOP_XPABIASLVL (0x300)
630#define AR_CH0_TOP_XPABIASLVL_S (8) 630#define AR_CH0_TOP_XPABIASLVL_S (8)
631 631
@@ -638,8 +638,8 @@
638 638
639#define AR_SWITCH_TABLE_COM_ALL (0xffff) 639#define AR_SWITCH_TABLE_COM_ALL (0xffff)
640#define AR_SWITCH_TABLE_COM_ALL_S (0) 640#define AR_SWITCH_TABLE_COM_ALL_S (0)
641#define AR_SWITCH_TABLE_COM_AR9480_ALL (0xffffff) 641#define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)
642#define AR_SWITCH_TABLE_COM_AR9480_ALL_S (0) 642#define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)
643#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000) 643#define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
644#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0) 644#define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
645#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4) 645#define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
@@ -679,11 +679,11 @@
679#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 679#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
680#define AR_CH0_XTAL_CAPOUTDAC_S 17 680#define AR_CH0_XTAL_CAPOUTDAC_S 17
681 681
682#define AR_PHY_PMU1 (AR_SREV_9480(ah) ? 0x16340 : 0x16c40) 682#define AR_PHY_PMU1 (AR_SREV_9462(ah) ? 0x16340 : 0x16c40)
683#define AR_PHY_PMU1_PWD 0x1 683#define AR_PHY_PMU1_PWD 0x1
684#define AR_PHY_PMU1_PWD_S 0 684#define AR_PHY_PMU1_PWD_S 0
685 685
686#define AR_PHY_PMU2 (AR_SREV_9480(ah) ? 0x16344 : 0x16c44) 686#define AR_PHY_PMU2 (AR_SREV_9462(ah) ? 0x16344 : 0x16c44)
687#define AR_PHY_PMU2_PGM 0x00200000 687#define AR_PHY_PMU2_PGM 0x00200000
688#define AR_PHY_PMU2_PGM_S 21 688#define AR_PHY_PMU2_PGM_S 21
689 689
@@ -921,9 +921,9 @@
921#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0) 921#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
922#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4) 922#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
923#define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8) 923#define AR_PHY_AIC_CTRL_2_B1 (AR_SM1_BASE + 0x4b8)
924#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \ 924#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
925 0x4c0 : 0x4c4)) 925 0x4c0 : 0x4c4))
926#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9480_10(ah) ? \ 926#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + (AR_SREV_9462_10(ah) ? \
927 0x4c4 : 0x4c8)) 927 0x4c4 : 0x4c8))
928#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0) 928#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0)
929#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc) 929#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc)
@@ -1001,7 +1001,7 @@
1001#define AR_GLB_BASE 0x20000 1001#define AR_GLB_BASE 0x20000
1002#define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44) 1002#define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44)
1003#define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \ 1003#define AR_GLB_SCRATCH(_ah) (AR_GLB_BASE + \
1004 (AR_SREV_9480_20(_ah) ? 0x4c : 0x50)) 1004 (AR_SREV_9462_20(_ah) ? 0x4c : 0x50))
1005#define AR_GLB_STATUS (AR_GLB_BASE + 0x48) 1005#define AR_GLB_STATUS (AR_GLB_BASE + 0x48)
1006 1006
1007/* 1007/*
diff --git a/drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h
index 4071bd2bd03f..5c55ae389adb 100644
--- a/drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9462_1p0_initvals.h
@@ -14,12 +14,12 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#ifndef INITVALS_9480_1P0_H 17#ifndef INITVALS_9462_1P0_H
18#define INITVALS_9480_1P0_H 18#define INITVALS_9462_1P0_H
19 19
20/* AR9480 1.0 */ 20/* AR9462 1.0 */
21 21
22static const u32 ar9480_1p0_mac_core[][2] = { 22static const u32 ar9462_1p0_mac_core[][2] = {
23 /* Addr allmodes */ 23 /* Addr allmodes */
24 {0x00000008, 0x00000000}, 24 {0x00000008, 0x00000000},
25 {0x00000030, 0x00060085}, 25 {0x00000030, 0x00060085},
@@ -183,27 +183,27 @@ static const u32 ar9480_1p0_mac_core[][2] = {
183 {0x000083d0, 0x000301ff}, 183 {0x000083d0, 0x000301ff},
184}; 184};
185 185
186static const u32 ar9480_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { 186static const u32 ar9462_1p0_baseband_core_txfir_coeff_japan_2484[][2] = {
187 /* Addr allmodes */ 187 /* Addr allmodes */
188 {0x0000a398, 0x00000000}, 188 {0x0000a398, 0x00000000},
189 {0x0000a39c, 0x6f7f0301}, 189 {0x0000a39c, 0x6f7f0301},
190 {0x0000a3a0, 0xca9228ee}, 190 {0x0000a3a0, 0xca9228ee},
191}; 191};
192 192
193static const u32 ar9480_1p0_sys3ant[][2] = { 193static const u32 ar9462_1p0_sys3ant[][2] = {
194 /* Addr allmodes */ 194 /* Addr allmodes */
195 {0x00063280, 0x00040807}, 195 {0x00063280, 0x00040807},
196 {0x00063284, 0x104ccccc}, 196 {0x00063284, 0x104ccccc},
197}; 197};
198 198
199static const u32 ar9480_pcie_phy_clkreq_enable_L1_1p0[][2] = { 199static const u32 ar9462_pcie_phy_clkreq_enable_L1_1p0[][2] = {
200 /* Addr allmodes */ 200 /* Addr allmodes */
201 {0x00018c00, 0x10053e5e}, 201 {0x00018c00, 0x10053e5e},
202 {0x00018c04, 0x000801d8}, 202 {0x00018c04, 0x000801d8},
203 {0x00018c08, 0x0000580c}, 203 {0x00018c08, 0x0000580c},
204}; 204};
205 205
206static const u32 ar9480_1p0_mac_core_emulation[][2] = { 206static const u32 ar9462_1p0_mac_core_emulation[][2] = {
207 /* Addr allmodes */ 207 /* Addr allmodes */
208 {0x00000030, 0x00060085}, 208 {0x00000030, 0x00060085},
209 {0x00000044, 0x00000008}, 209 {0x00000044, 0x00000008},
@@ -211,7 +211,7 @@ static const u32 ar9480_1p0_mac_core_emulation[][2] = {
211 {0x00008344, 0xaa4a105b}, 211 {0x00008344, 0xaa4a105b},
212}; 212};
213 213
214static const u32 ar9480_common_rx_gain_table_ar9280_2p0_1p0[][2] = { 214static const u32 ar9462_common_rx_gain_table_ar9280_2p0_1p0[][2] = {
215 /* Addr allmodes */ 215 /* Addr allmodes */
216 {0x0000a000, 0x02000101}, 216 {0x0000a000, 0x02000101},
217 {0x0000a004, 0x02000102}, 217 {0x0000a004, 0x02000102},
@@ -513,7 +513,7 @@ static const u32 ar9200_ar9280_2p0_radio_core_1p0[][2] = {
513 {0x00007894, 0x5a108000}, 513 {0x00007894, 0x5a108000},
514}; 514};
515 515
516static const u32 ar9480_1p0_baseband_postamble_emulation[][5] = { 516static const u32 ar9462_1p0_baseband_postamble_emulation[][5] = {
517 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 517 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
518 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 518 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
519 {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221}, 519 {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221},
@@ -535,14 +535,14 @@ static const u32 ar9480_1p0_baseband_postamble_emulation[][5] = {
535 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 535 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
536}; 536};
537 537
538static const u32 ar9480_pcie_phy_pll_on_clkreq_disable_L1_1p0[][2] = { 538static const u32 ar9462_pcie_phy_pll_on_clkreq_disable_L1_1p0[][2] = {
539 /* Addr allmodes */ 539 /* Addr allmodes */
540 {0x00018c00, 0x10012e5e}, 540 {0x00018c00, 0x10012e5e},
541 {0x00018c04, 0x000801d8}, 541 {0x00018c04, 0x000801d8},
542 {0x00018c08, 0x0000580c}, 542 {0x00018c08, 0x0000580c},
543}; 543};
544 544
545static const u32 ar9480_common_rx_gain_table_1p0[][2] = { 545static const u32 ar9462_common_rx_gain_table_1p0[][2] = {
546 /* Addr allmodes */ 546 /* Addr allmodes */
547 {0x0000a000, 0x00010000}, 547 {0x0000a000, 0x00010000},
548 {0x0000a004, 0x00030002}, 548 {0x0000a004, 0x00030002},
@@ -802,7 +802,7 @@ static const u32 ar9480_common_rx_gain_table_1p0[][2] = {
802 {0x0000b1fc, 0x00000196}, 802 {0x0000b1fc, 0x00000196},
803}; 803};
804 804
805static const u32 ar9480_modes_high_ob_db_tx_gain_table_1p0[][5] = { 805static const u32 ar9462_modes_high_ob_db_tx_gain_table_1p0[][5] = {
806 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 806 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
807 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, 807 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
808 {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584}, 808 {0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
@@ -867,7 +867,7 @@ static const u32 ar9480_modes_high_ob_db_tx_gain_table_1p0[][5] = {
867 {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000}, 867 {0x00016448, 0x8db49000, 0x8db49000, 0x8db49000, 0x8db49000},
868}; 868};
869 869
870static const u32 ar9480_common_wo_xlna_rx_gain_table_1p0[][2] = { 870static const u32 ar9462_common_wo_xlna_rx_gain_table_1p0[][2] = {
871 /* Addr allmodes */ 871 /* Addr allmodes */
872 {0x0000a000, 0x00010000}, 872 {0x0000a000, 0x00010000},
873 {0x0000a004, 0x00030002}, 873 {0x0000a004, 0x00030002},
@@ -1127,7 +1127,7 @@ static const u32 ar9480_common_wo_xlna_rx_gain_table_1p0[][2] = {
1127 {0x0000b1fc, 0x00000196}, 1127 {0x0000b1fc, 0x00000196},
1128}; 1128};
1129 1129
1130static const u32 ar9480_1p0_mac_postamble[][5] = { 1130static const u32 ar9462_1p0_mac_postamble[][5] = {
1131 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1131 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1132 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, 1132 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
1133 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, 1133 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
@@ -1139,13 +1139,13 @@ static const u32 ar9480_1p0_mac_postamble[][5] = {
1139 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, 1139 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
1140}; 1140};
1141 1141
1142static const u32 ar9480_1p0_mac_postamble_emulation[][5] = { 1142static const u32 ar9462_1p0_mac_postamble_emulation[][5] = {
1143 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1143 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1144 {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8}, 1144 {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8},
1145 {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017}, 1145 {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017},
1146}; 1146};
1147 1147
1148static const u32 ar9480_1p0_tx_gain_table_baseband_postamble_emulation[][5] = { 1148static const u32 ar9462_1p0_tx_gain_table_baseband_postamble_emulation[][5] = {
1149 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1149 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1150 {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5}, 1150 {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5},
1151 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 1151 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -1163,7 +1163,7 @@ static const u32 ar9480_1p0_tx_gain_table_baseband_postamble_emulation[][5] = {
1163 {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a}, 1163 {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a},
1164}; 1164};
1165 1165
1166static const u32 ar9480_1p0_radio_postamble[][5] = { 1166static const u32 ar9462_1p0_radio_postamble[][5] = {
1167 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1167 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1168 {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524}, 1168 {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
1169 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24646c08, 0x24646c08}, 1169 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24646c08, 0x24646c08},
@@ -1174,12 +1174,12 @@ static const u32 ar9480_1p0_radio_postamble[][5] = {
1174 {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, 1174 {0x00016540, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
1175}; 1175};
1176 1176
1177static const u32 ar9480_1p0_soc_postamble_emulation[][5] = { 1177static const u32 ar9462_1p0_soc_postamble_emulation[][5] = {
1178 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1178 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1179 {0x00007010, 0x00001133, 0x00001133, 0x00001133, 0x00001133}, 1179 {0x00007010, 0x00001133, 0x00001133, 0x00001133, 0x00001133},
1180}; 1180};
1181 1181
1182static const u32 ar9480_1p0_baseband_core[][2] = { 1182static const u32 ar9462_1p0_baseband_core[][2] = {
1183 /* Addr allmodes */ 1183 /* Addr allmodes */
1184 {0x00009800, 0xafe68e30}, 1184 {0x00009800, 0xafe68e30},
1185 {0x00009804, 0xfd14e000}, 1185 {0x00009804, 0xfd14e000},
@@ -1336,7 +1336,7 @@ static const u32 ar9480_1p0_baseband_core[][2] = {
1336 {0x0000b6b4, 0x00c00001}, 1336 {0x0000b6b4, 0x00c00001},
1337}; 1337};
1338 1338
1339static const u32 ar9480_1p0_baseband_postamble[][5] = { 1339static const u32 ar9462_1p0_baseband_postamble[][5] = {
1340 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1340 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1341 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, 1341 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
1342 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e}, 1342 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
@@ -1386,7 +1386,7 @@ static const u32 ar9480_1p0_baseband_postamble[][5] = {
1386 {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, 1386 {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
1387}; 1387};
1388 1388
1389static const u32 ar9480_modes_fast_clock_1p0[][3] = { 1389static const u32 ar9462_modes_fast_clock_1p0[][3] = {
1390 /* Addr 5G_HT20 5G_HT40 */ 1390 /* Addr 5G_HT20 5G_HT40 */
1391 {0x00001030, 0x00000268, 0x000004d0}, 1391 {0x00001030, 0x00000268, 0x000004d0},
1392 {0x00001070, 0x0000018c, 0x00000318}, 1392 {0x00001070, 0x0000018c, 0x00000318},
@@ -1399,7 +1399,7 @@ static const u32 ar9480_modes_fast_clock_1p0[][3] = {
1399 {0x0000a254, 0x00000898, 0x00001130}, 1399 {0x0000a254, 0x00000898, 0x00001130},
1400}; 1400};
1401 1401
1402static const u32 ar9480_modes_low_ob_db_tx_gain_table_1p0[][5] = { 1402static const u32 ar9462_modes_low_ob_db_tx_gain_table_1p0[][5] = {
1403 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1403 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1404 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, 1404 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
1405 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584}, 1405 {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
@@ -1464,12 +1464,12 @@ static const u32 ar9480_modes_low_ob_db_tx_gain_table_1p0[][5] = {
1464 {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000}, 1464 {0x00016448, 0x64992000, 0x64992000, 0x64992000, 0x64992000},
1465}; 1465};
1466 1466
1467static const u32 ar9480_1p0_soc_postamble[][5] = { 1467static const u32 ar9462_1p0_soc_postamble[][5] = {
1468 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1468 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1469 {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233}, 1469 {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233},
1470}; 1470};
1471 1471
1472static const u32 ar9480_common_mixed_rx_gain_table_1p0[][2] = { 1472static const u32 ar9462_common_mixed_rx_gain_table_1p0[][2] = {
1473 /* Addr allmodes */ 1473 /* Addr allmodes */
1474 {0x0000a000, 0x00010000}, 1474 {0x0000a000, 0x00010000},
1475 {0x0000a004, 0x00030002}, 1475 {0x0000a004, 0x00030002},
@@ -1729,14 +1729,14 @@ static const u32 ar9480_common_mixed_rx_gain_table_1p0[][2] = {
1729 {0x0000b1fc, 0x00000196}, 1729 {0x0000b1fc, 0x00000196},
1730}; 1730};
1731 1731
1732static const u32 ar9480_pcie_phy_clkreq_disable_L1_1p0[][2] = { 1732static const u32 ar9462_pcie_phy_clkreq_disable_L1_1p0[][2] = {
1733 /* Addr allmodes */ 1733 /* Addr allmodes */
1734 {0x00018c00, 0x10013e5e}, 1734 {0x00018c00, 0x10013e5e},
1735 {0x00018c04, 0x000801d8}, 1735 {0x00018c04, 0x000801d8},
1736 {0x00018c08, 0x0000580c}, 1736 {0x00018c08, 0x0000580c},
1737}; 1737};
1738 1738
1739static const u32 ar9480_1p0_baseband_core_emulation[][2] = { 1739static const u32 ar9462_1p0_baseband_core_emulation[][2] = {
1740 /* Addr allmodes */ 1740 /* Addr allmodes */
1741 {0x00009800, 0xafa68e30}, 1741 {0x00009800, 0xafa68e30},
1742 {0x00009884, 0x00002842}, 1742 {0x00009884, 0x00002842},
@@ -1758,7 +1758,7 @@ static const u32 ar9480_1p0_baseband_core_emulation[][2] = {
1758 {0x0000a690, 0x00000038}, 1758 {0x0000a690, 0x00000038},
1759}; 1759};
1760 1760
1761static const u32 ar9480_1p0_radio_core[][2] = { 1761static const u32 ar9462_1p0_radio_core[][2] = {
1762 /* Addr allmodes */ 1762 /* Addr allmodes */
1763 {0x00016000, 0x36db6db6}, 1763 {0x00016000, 0x36db6db6},
1764 {0x00016004, 0x6db6db40}, 1764 {0x00016004, 0x6db6db40},
@@ -1818,16 +1818,16 @@ static const u32 ar9480_1p0_radio_core[][2] = {
1818 {0x00016548, 0x000080c0}, 1818 {0x00016548, 0x000080c0},
1819}; 1819};
1820 1820
1821static const u32 ar9480_1p0_soc_preamble[][2] = { 1821static const u32 ar9462_1p0_soc_preamble[][2] = {
1822 /* Addr allmodes */ 1822 /* Addr allmodes */
1823 {0x00007020, 0x00000000}, 1823 {0x00007020, 0x00000000},
1824 {0x00007034, 0x00000002}, 1824 {0x00007034, 0x00000002},
1825 {0x00007038, 0x000004c2}, 1825 {0x00007038, 0x000004c2},
1826}; 1826};
1827 1827
1828static const u32 ar9480_1p0_sys2ant[][2] = { 1828static const u32 ar9462_1p0_sys2ant[][2] = {
1829 /* Addr allmodes */ 1829 /* Addr allmodes */
1830 {0x00063120, 0x00801980}, 1830 {0x00063120, 0x00801980},
1831}; 1831};
1832 1832
1833#endif /* INITVALS_9480_1P0_H */ 1833#endif /* INITVALS_9462_1P0_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
index d54163d8d69f..9c51b395b4ff 100644
--- a/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9462_2p0_initvals.h
@@ -14,12 +14,12 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#ifndef INITVALS_9480_2P0_H 17#ifndef INITVALS_9462_2P0_H
18#define INITVALS_9480_2P0_H 18#define INITVALS_9462_2P0_H
19 19
20/* AR9480 2.0 */ 20/* AR9462 2.0 */
21 21
22static const u32 ar9480_modes_fast_clock_2p0[][3] = { 22static const u32 ar9462_modes_fast_clock_2p0[][3] = {
23 /* Addr 5G_HT20 5G_HT40 */ 23 /* Addr 5G_HT20 5G_HT40 */
24 {0x00001030, 0x00000268, 0x000004d0}, 24 {0x00001030, 0x00000268, 0x000004d0},
25 {0x00001070, 0x0000018c, 0x00000318}, 25 {0x00001070, 0x0000018c, 0x00000318},
@@ -32,14 +32,14 @@ static const u32 ar9480_modes_fast_clock_2p0[][3] = {
32 {0x0000a254, 0x00000898, 0x00001130}, 32 {0x0000a254, 0x00000898, 0x00001130},
33}; 33};
34 34
35static const u32 ar9480_pciephy_clkreq_enable_L1_2p0[][2] = { 35static const u32 ar9462_pciephy_clkreq_enable_L1_2p0[][2] = {
36 /* Addr allmodes */ 36 /* Addr allmodes */
37 {0x00018c00, 0x18253ede}, 37 {0x00018c00, 0x18253ede},
38 {0x00018c04, 0x000801d8}, 38 {0x00018c04, 0x000801d8},
39 {0x00018c08, 0x0003580c}, 39 {0x00018c08, 0x0003580c},
40}; 40};
41 41
42static const u32 ar9480_2p0_baseband_postamble[][5] = { 42static const u32 ar9462_2p0_baseband_postamble[][5] = {
43 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 43 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
44 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, 44 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
45 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e}, 45 {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
@@ -89,7 +89,7 @@ static const u32 ar9480_2p0_baseband_postamble[][5] = {
89 {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550}, 89 {0x0000b284, 0x00000000, 0x00000000, 0x00000550, 0x00000550},
90}; 90};
91 91
92static const u32 ar9480_2p0_mac_core_emulation[][2] = { 92static const u32 ar9462_2p0_mac_core_emulation[][2] = {
93 /* Addr allmodes */ 93 /* Addr allmodes */
94 {0x00000030, 0x000e0085}, 94 {0x00000030, 0x000e0085},
95 {0x00000044, 0x00000008}, 95 {0x00000044, 0x00000008},
@@ -97,7 +97,7 @@ static const u32 ar9480_2p0_mac_core_emulation[][2] = {
97 {0x00008344, 0xaa4a105b}, 97 {0x00008344, 0xaa4a105b},
98}; 98};
99 99
100static const u32 ar9480_common_rx_gain_table_2p0[][2] = { 100static const u32 ar9462_common_rx_gain_table_2p0[][2] = {
101 /* Addr allmodes */ 101 /* Addr allmodes */
102 {0x0000a000, 0x00010000}, 102 {0x0000a000, 0x00010000},
103 {0x0000a004, 0x00030002}, 103 {0x0000a004, 0x00030002},
@@ -357,27 +357,27 @@ static const u32 ar9480_common_rx_gain_table_2p0[][2] = {
357 {0x0000b1fc, 0x00000196}, 357 {0x0000b1fc, 0x00000196},
358}; 358};
359 359
360static const u32 ar9480_pciephy_clkreq_disable_L1_2p0[][2] = { 360static const u32 ar9462_pciephy_clkreq_disable_L1_2p0[][2] = {
361 /* Addr allmodes */ 361 /* Addr allmodes */
362 {0x00018c00, 0x18213ede}, 362 {0x00018c00, 0x18213ede},
363 {0x00018c04, 0x000801d8}, 363 {0x00018c04, 0x000801d8},
364 {0x00018c08, 0x0003580c}, 364 {0x00018c08, 0x0003580c},
365}; 365};
366 366
367static const u32 ar9480_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = { 367static const u32 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0[][2] = {
368 /* Addr allmodes */ 368 /* Addr allmodes */
369 {0x00018c00, 0x18212ede}, 369 {0x00018c00, 0x18212ede},
370 {0x00018c04, 0x000801d8}, 370 {0x00018c04, 0x000801d8},
371 {0x00018c08, 0x0003580c}, 371 {0x00018c08, 0x0003580c},
372}; 372};
373 373
374static const u32 ar9480_2p0_sys3ant[][2] = { 374static const u32 ar9462_2p0_sys3ant[][2] = {
375 /* Addr allmodes */ 375 /* Addr allmodes */
376 {0x00063280, 0x00040807}, 376 {0x00063280, 0x00040807},
377 {0x00063284, 0x104ccccc}, 377 {0x00063284, 0x104ccccc},
378}; 378};
379 379
380static const u32 ar9480_common_rx_gain_table_ar9280_2p0[][2] = { 380static const u32 ar9462_common_rx_gain_table_ar9280_2p0[][2] = {
381 /* Addr allmodes */ 381 /* Addr allmodes */
382 {0x0000a000, 0x02000101}, 382 {0x0000a000, 0x02000101},
383 {0x0000a004, 0x02000102}, 383 {0x0000a004, 0x02000102},
@@ -679,20 +679,20 @@ static const u32 ar9200_ar9280_2p0_radio_core[][2] = {
679 {0x00007894, 0x5a108000}, 679 {0x00007894, 0x5a108000},
680}; 680};
681 681
682static const u32 ar9480_2p0_mac_postamble_emulation[][5] = { 682static const u32 ar9462_2p0_mac_postamble_emulation[][5] = {
683 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 683 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
684 {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8}, 684 {0x00008014, 0x10f810f8, 0x10f810f8, 0x10f810f8, 0x10f810f8},
685 {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017}, 685 {0x0000801c, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017, 0x0e8d8017},
686}; 686};
687 687
688static const u32 ar9480_2p0_radio_postamble_sys3ant[][5] = { 688static const u32 ar9462_2p0_radio_postamble_sys3ant[][5] = {
689 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 689 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
690 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, 690 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
691 {0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, 691 {0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
692 {0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, 692 {0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
693}; 693};
694 694
695static const u32 ar9480_2p0_baseband_postamble_emulation[][5] = { 695static const u32 ar9462_2p0_baseband_postamble_emulation[][5] = {
696 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 696 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
697 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 697 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
698 {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221}, 698 {0x00009e3c, 0xcf946221, 0xcf946221, 0xcf946221, 0xcf946221},
@@ -714,14 +714,14 @@ static const u32 ar9480_2p0_baseband_postamble_emulation[][5] = {
714 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 714 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
715}; 715};
716 716
717static const u32 ar9480_2p0_radio_postamble_sys2ant[][5] = { 717static const u32 ar9462_2p0_radio_postamble_sys2ant[][5] = {
718 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 718 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
719 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, 719 {0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808},
720 {0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, 720 {0x00016140, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
721 {0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008}, 721 {0x00016540, 0x10804008, 0x10804008, 0x90804008, 0x90804008},
722}; 722};
723 723
724static const u32 ar9480_common_wo_xlna_rx_gain_table_2p0[][2] = { 724static const u32 ar9462_common_wo_xlna_rx_gain_table_2p0[][2] = {
725 /* Addr allmodes */ 725 /* Addr allmodes */
726 {0x0000a000, 0x00010000}, 726 {0x0000a000, 0x00010000},
727 {0x0000a004, 0x00030002}, 727 {0x0000a004, 0x00030002},
@@ -981,14 +981,14 @@ static const u32 ar9480_common_wo_xlna_rx_gain_table_2p0[][2] = {
981 {0x0000b1fc, 0x00000196}, 981 {0x0000b1fc, 0x00000196},
982}; 982};
983 983
984static const u32 ar9480_2p0_baseband_core_txfir_coeff_japan_2484[][2] = { 984static const u32 ar9462_2p0_baseband_core_txfir_coeff_japan_2484[][2] = {
985 /* Addr allmodes */ 985 /* Addr allmodes */
986 {0x0000a398, 0x00000000}, 986 {0x0000a398, 0x00000000},
987 {0x0000a39c, 0x6f7f0301}, 987 {0x0000a39c, 0x6f7f0301},
988 {0x0000a3a0, 0xca9228ee}, 988 {0x0000a3a0, 0xca9228ee},
989}; 989};
990 990
991static const u32 ar9480_modes_low_ob_db_tx_gain_table_2p0[][5] = { 991static const u32 ar9462_modes_low_ob_db_tx_gain_table_2p0[][5] = {
992 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 992 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
993 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, 993 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
994 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352}, 994 {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
@@ -1057,12 +1057,12 @@ static const u32 ar9480_modes_low_ob_db_tx_gain_table_2p0[][5] = {
1057 {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, 1057 {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
1058}; 1058};
1059 1059
1060static const u32 ar9480_2p0_soc_postamble[][5] = { 1060static const u32 ar9462_2p0_soc_postamble[][5] = {
1061 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1061 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1062 {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233}, 1062 {0x00007010, 0x00002233, 0x00002233, 0x00002233, 0x00002233},
1063}; 1063};
1064 1064
1065static const u32 ar9480_2p0_baseband_core[][2] = { 1065static const u32 ar9462_2p0_baseband_core[][2] = {
1066 /* Addr allmodes */ 1066 /* Addr allmodes */
1067 {0x00009800, 0xafe68e30}, 1067 {0x00009800, 0xafe68e30},
1068 {0x00009804, 0xfd14e000}, 1068 {0x00009804, 0xfd14e000},
@@ -1221,7 +1221,7 @@ static const u32 ar9480_2p0_baseband_core[][2] = {
1221 {0x0000b6b4, 0x00000001}, 1221 {0x0000b6b4, 0x00000001},
1222}; 1222};
1223 1223
1224static const u32 ar9480_2p0_radio_postamble[][5] = { 1224static const u32 ar9462_2p0_radio_postamble[][5] = {
1225 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1225 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1226 {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524}, 1226 {0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524},
1227 {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70}, 1227 {0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70},
@@ -1229,7 +1229,7 @@ static const u32 ar9480_2p0_radio_postamble[][5] = {
1229 {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000}, 1229 {0x0001650c, 0x48000000, 0x40000000, 0x40000000, 0x40000000},
1230}; 1230};
1231 1231
1232static const u32 ar9480_modes_high_ob_db_tx_gain_table_2p0[][5] = { 1232static const u32 ar9462_modes_high_ob_db_tx_gain_table_2p0[][5] = {
1233 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1233 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1234 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002}, 1234 {0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
1235 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, 1235 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
@@ -1298,7 +1298,7 @@ static const u32 ar9480_modes_high_ob_db_tx_gain_table_2p0[][5] = {
1298 {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000}, 1298 {0x00016454, 0x6db60000, 0x6db60000, 0x6db60000, 0x6db60000},
1299}; 1299};
1300 1300
1301static const u32 ar9480_2p0_radio_core[][2] = { 1301static const u32 ar9462_2p0_radio_core[][2] = {
1302 /* Addr allmodes */ 1302 /* Addr allmodes */
1303 {0x00016000, 0x36db6db6}, 1303 {0x00016000, 0x36db6db6},
1304 {0x00016004, 0x6db6db40}, 1304 {0x00016004, 0x6db6db40},
@@ -1356,7 +1356,7 @@ static const u32 ar9480_2p0_radio_core[][2] = {
1356 {0x00016548, 0x000080c0}, 1356 {0x00016548, 0x000080c0},
1357}; 1357};
1358 1358
1359static const u32 ar9480_2p0_tx_gain_table_baseband_postamble_emulation[][5] = { 1359static const u32 ar9462_2p0_tx_gain_table_baseband_postamble_emulation[][5] = {
1360 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1360 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1361 {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5}, 1361 {0x0000a410, 0x000000d5, 0x000000d5, 0x000000d5, 0x000000d5},
1362 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 1362 {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -1374,19 +1374,19 @@ static const u32 ar9480_2p0_tx_gain_table_baseband_postamble_emulation[][5] = {
1374 {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a}, 1374 {0x0000a534, 0x00034e8a, 0x00034e8a, 0x00034e8a, 0x00034e8a},
1375}; 1375};
1376 1376
1377static const u32 ar9480_2p0_soc_preamble[][2] = { 1377static const u32 ar9462_2p0_soc_preamble[][2] = {
1378 /* Addr allmodes */ 1378 /* Addr allmodes */
1379 {0x00007020, 0x00000000}, 1379 {0x00007020, 0x00000000},
1380 {0x00007034, 0x00000002}, 1380 {0x00007034, 0x00000002},
1381 {0x00007038, 0x000004c2}, 1381 {0x00007038, 0x000004c2},
1382}; 1382};
1383 1383
1384static const u32 ar9480_2p0_sys2ant[][2] = { 1384static const u32 ar9462_2p0_sys2ant[][2] = {
1385 /* Addr allmodes */ 1385 /* Addr allmodes */
1386 {0x00063120, 0x00801980}, 1386 {0x00063120, 0x00801980},
1387}; 1387};
1388 1388
1389static const u32 ar9480_2p0_mac_core[][2] = { 1389static const u32 ar9462_2p0_mac_core[][2] = {
1390 /* Addr allmodes */ 1390 /* Addr allmodes */
1391 {0x00000008, 0x00000000}, 1391 {0x00000008, 0x00000000},
1392 {0x00000030, 0x000e0085}, 1392 {0x00000030, 0x000e0085},
@@ -1550,7 +1550,7 @@ static const u32 ar9480_2p0_mac_core[][2] = {
1550 {0x000083d0, 0x000301ff}, 1550 {0x000083d0, 0x000301ff},
1551}; 1551};
1552 1552
1553static const u32 ar9480_2p0_mac_postamble[][5] = { 1553static const u32 ar9462_2p0_mac_postamble[][5] = {
1554 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1554 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1555 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160}, 1555 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
1556 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c}, 1556 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
@@ -1562,7 +1562,7 @@ static const u32 ar9480_2p0_mac_postamble[][5] = {
1562 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440}, 1562 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
1563}; 1563};
1564 1564
1565static const u32 ar9480_common_mixed_rx_gain_table_2p0[][2] = { 1565static const u32 ar9462_common_mixed_rx_gain_table_2p0[][2] = {
1566 /* Addr allmodes */ 1566 /* Addr allmodes */
1567 {0x0000a000, 0x00010000}, 1567 {0x0000a000, 0x00010000},
1568 {0x0000a004, 0x00030002}, 1568 {0x0000a004, 0x00030002},
@@ -1822,7 +1822,7 @@ static const u32 ar9480_common_mixed_rx_gain_table_2p0[][2] = {
1822 {0x0000b1fc, 0x00000196}, 1822 {0x0000b1fc, 0x00000196},
1823}; 1823};
1824 1824
1825static const u32 ar9480_modes_green_ob_db_tx_gain_table_2p0[][5] = { 1825static const u32 ar9462_modes_green_ob_db_tx_gain_table_2p0[][5] = {
1826 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ 1826 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
1827 {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003}, 1827 {0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
1828 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352}, 1828 {0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
@@ -1891,7 +1891,7 @@ static const u32 ar9480_modes_green_ob_db_tx_gain_table_2p0[][5] = {
1891 {0x00016454, 0x6db60180, 0x6db60180, 0x6db60180, 0x6db60180}, 1891 {0x00016454, 0x6db60180, 0x6db60180, 0x6db60180, 0x6db60180},
1892}; 1892};
1893 1893
1894static const u32 ar9480_2p0_BTCOEX_MAX_TXPWR_table[][2] = { 1894static const u32 ar9462_2p0_BTCOEX_MAX_TXPWR_table[][2] = {
1895 /* Addr allmodes */ 1895 /* Addr allmodes */
1896 {0x000018c0, 0x10101010}, 1896 {0x000018c0, 0x10101010},
1897 {0x000018c4, 0x10101010}, 1897 {0x000018c4, 0x10101010},
@@ -1903,7 +1903,7 @@ static const u32 ar9480_2p0_BTCOEX_MAX_TXPWR_table[][2] = {
1903 {0x000018dc, 0x10101010}, 1903 {0x000018dc, 0x10101010},
1904}; 1904};
1905 1905
1906static const u32 ar9480_2p0_baseband_core_emulation[][2] = { 1906static const u32 ar9462_2p0_baseband_core_emulation[][2] = {
1907 /* Addr allmodes */ 1907 /* Addr allmodes */
1908 {0x00009800, 0xafa68e30}, 1908 {0x00009800, 0xafa68e30},
1909 {0x00009884, 0x00002842}, 1909 {0x00009884, 0x00002842},
@@ -1925,4 +1925,4 @@ static const u32 ar9480_2p0_baseband_core_emulation[][2] = {
1925 {0x0000a690, 0x00000038}, 1925 {0x0000a690, 0x00000038},
1926}; 1926};
1927 1927
1928#endif /* INITVALS_9480_2P0_H */ 1928#endif /* INITVALS_9462_2P0_H */
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 1e8614783181..1c269f50822b 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -458,7 +458,7 @@ void ath9k_btcoex_timer_pause(struct ath_softc *sc);
458#define ATH_LED_PIN_9287 8 458#define ATH_LED_PIN_9287 8
459#define ATH_LED_PIN_9300 10 459#define ATH_LED_PIN_9300 10
460#define ATH_LED_PIN_9485 6 460#define ATH_LED_PIN_9485 6
461#define ATH_LED_PIN_9480 0 461#define ATH_LED_PIN_9462 0
462 462
463#ifdef CONFIG_MAC80211_LEDS 463#ifdef CONFIG_MAC80211_LEDS
464void ath_init_leds(struct ath_softc *sc); 464void ath_init_leds(struct ath_softc *sc);
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index 3721770c238e..49abd34be741 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -108,7 +108,7 @@
108#define EEP_RFSILENT_ENABLED_S 0 108#define EEP_RFSILENT_ENABLED_S 0
109#define EEP_RFSILENT_POLARITY 0x0002 109#define EEP_RFSILENT_POLARITY 0x0002
110#define EEP_RFSILENT_POLARITY_S 1 110#define EEP_RFSILENT_POLARITY_S 1
111#define EEP_RFSILENT_GPIO_SEL (AR_SREV_9480(ah) ? 0x00fc : 0x001c) 111#define EEP_RFSILENT_GPIO_SEL (AR_SREV_9462(ah) ? 0x00fc : 0x001c)
112#define EEP_RFSILENT_GPIO_SEL_S 2 112#define EEP_RFSILENT_GPIO_SEL_S 2
113 113
114#define AR5416_OPFLAGS_11A 0x01 114#define AR5416_OPFLAGS_11A 0x01
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
index 61eee8c49a14..655576c8fdab 100644
--- a/drivers/net/wireless/ath/ath9k/gpio.c
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -48,8 +48,8 @@ void ath_init_leds(struct ath_softc *sc)
48 sc->sc_ah->led_pin = ATH_LED_PIN_9485; 48 sc->sc_ah->led_pin = ATH_LED_PIN_9485;
49 else if (AR_SREV_9300(sc->sc_ah)) 49 else if (AR_SREV_9300(sc->sc_ah))
50 sc->sc_ah->led_pin = ATH_LED_PIN_9300; 50 sc->sc_ah->led_pin = ATH_LED_PIN_9300;
51 else if (AR_SREV_9480(sc->sc_ah)) 51 else if (AR_SREV_9462(sc->sc_ah))
52 sc->sc_ah->led_pin = ATH_LED_PIN_9480; 52 sc->sc_ah->led_pin = ATH_LED_PIN_9462;
53 else 53 else
54 sc->sc_ah->led_pin = ATH_LED_PIN_DEF; 54 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
55 } 55 }
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 67831a3fca6b..f16d2033081f 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -285,7 +285,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
287 287
288 if (AR_SREV_9480(ah)) 288 if (AR_SREV_9462(ah))
289 ah->is_pciexpress = true; 289 ah->is_pciexpress = true;
290 else 290 else
291 ah->is_pciexpress = (val & 291 ah->is_pciexpress = (val &
@@ -541,7 +541,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
541 return -EIO; 541 return -EIO;
542 } 542 }
543 543
544 if (AR_SREV_9480(ah)) 544 if (AR_SREV_9462(ah))
545 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; 545 ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;
546 546
547 ath9k_hw_init_defaults(ah); 547 ath9k_hw_init_defaults(ah);
@@ -587,7 +587,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
587 case AR_SREV_VERSION_9330: 587 case AR_SREV_VERSION_9330:
588 case AR_SREV_VERSION_9485: 588 case AR_SREV_VERSION_9485:
589 case AR_SREV_VERSION_9340: 589 case AR_SREV_VERSION_9340:
590 case AR_SREV_VERSION_9480: 590 case AR_SREV_VERSION_9462:
591 break; 591 break;
592 default: 592 default:
593 ath_err(common, 593 ath_err(common,
@@ -672,7 +672,7 @@ int ath9k_hw_init(struct ath_hw *ah)
672 case AR9300_DEVID_AR9330: 672 case AR9300_DEVID_AR9330:
673 case AR9300_DEVID_AR9340: 673 case AR9300_DEVID_AR9340:
674 case AR9300_DEVID_AR9580: 674 case AR9300_DEVID_AR9580:
675 case AR9300_DEVID_AR9480: 675 case AR9300_DEVID_AR9462:
676 break; 676 break;
677 default: 677 default:
678 if (common->bus_ops->ath_bus_type == ATH_USB) 678 if (common->bus_ops->ath_bus_type == ATH_USB)
@@ -1790,7 +1790,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1790{ 1790{
1791 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1791 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1792 if (setChip) { 1792 if (setChip) {
1793 if (AR_SREV_9480(ah)) { 1793 if (AR_SREV_9462(ah)) {
1794 REG_WRITE(ah, AR_TIMER_MODE, 1794 REG_WRITE(ah, AR_TIMER_MODE,
1795 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); 1795 REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
1796 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah, 1796 REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah,
@@ -1808,7 +1808,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1808 */ 1808 */
1809 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); 1809 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1810 1810
1811 if (AR_SREV_9480(ah)) 1811 if (AR_SREV_9462(ah))
1812 udelay(100); 1812 udelay(100);
1813 1813
1814 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1814 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
@@ -1816,7 +1816,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1816 1816
1817 /* Shutdown chip. Active low */ 1817 /* Shutdown chip. Active low */
1818 if (!AR_SREV_5416(ah) && 1818 if (!AR_SREV_5416(ah) &&
1819 !AR_SREV_9271(ah) && !AR_SREV_9480_10(ah)) { 1819 !AR_SREV_9271(ah) && !AR_SREV_9462_10(ah)) {
1820 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); 1820 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1821 udelay(2); 1821 udelay(2);
1822 } 1822 }
@@ -1854,7 +1854,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1854 * SYS_WAKING and SYS_SLEEPING messages which will make 1854 * SYS_WAKING and SYS_SLEEPING messages which will make
1855 * BT CPU to busy to process. 1855 * BT CPU to busy to process.
1856 */ 1856 */
1857 if (AR_SREV_9480(ah)) { 1857 if (AR_SREV_9462(ah)) {
1858 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & 1858 val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
1859 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; 1859 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK;
1860 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); 1860 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val);
@@ -1866,7 +1866,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1866 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1866 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1867 AR_RTC_FORCE_WAKE_EN); 1867 AR_RTC_FORCE_WAKE_EN);
1868 1868
1869 if (AR_SREV_9480(ah)) 1869 if (AR_SREV_9462(ah))
1870 udelay(30); 1870 udelay(30);
1871 } 1871 }
1872 } 1872 }
@@ -2330,7 +2330,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2330 if (!AR_SREV_9330(ah)) 2330 if (!AR_SREV_9330(ah))
2331 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; 2331 ah->enabled_cals |= TX_IQ_ON_AGC_CAL;
2332 } 2332 }
2333 if (AR_SREV_9480(ah)) 2333 if (AR_SREV_9462(ah))
2334 pCap->hw_caps |= ATH9K_HW_CAP_RTT; 2334 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2335 2335
2336 return 0; 2336 return 0;
@@ -2493,7 +2493,7 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2493 2493
2494 ENABLE_REGWRITE_BUFFER(ah); 2494 ENABLE_REGWRITE_BUFFER(ah);
2495 2495
2496 if (AR_SREV_9480(ah)) 2496 if (AR_SREV_9462(ah))
2497 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; 2497 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2498 2498
2499 REG_WRITE(ah, AR_RX_FILTER, bits); 2499 REG_WRITE(ah, AR_RX_FILTER, bits);
@@ -2785,9 +2785,9 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2785 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2785 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2786 gen_tmr_configuration[timer->index].mode_mask); 2786 gen_tmr_configuration[timer->index].mode_mask);
2787 2787
2788 if (AR_SREV_9480(ah)) { 2788 if (AR_SREV_9462(ah)) {
2789 /* 2789 /*
2790 * Starting from AR9480, each generic timer can select which tsf 2790 * Starting from AR9462, each generic timer can select which tsf
2791 * to use. But we still follow the old rule, 0 - 7 use tsf and 2791 * to use. But we still follow the old rule, 0 - 7 use tsf and
2792 * 8 - 15 use tsf2. 2792 * 8 - 15 use tsf2.
2793 */ 2793 */
@@ -2904,7 +2904,7 @@ static struct {
2904 { AR_SREV_VERSION_9330, "9330" }, 2904 { AR_SREV_VERSION_9330, "9330" },
2905 { AR_SREV_VERSION_9340, "9340" }, 2905 { AR_SREV_VERSION_9340, "9340" },
2906 { AR_SREV_VERSION_9485, "9485" }, 2906 { AR_SREV_VERSION_9485, "9485" },
2907 { AR_SREV_VERSION_9480, "9480" }, 2907 { AR_SREV_VERSION_9462, "9462" },
2908}; 2908};
2909 2909
2910/* For devices with external radios */ 2910/* For devices with external radios */
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 156c57ad4f0c..f389b3c93cf3 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -46,7 +46,7 @@
46#define AR9300_DEVID_AR9340 0x0031 46#define AR9300_DEVID_AR9340 0x0031
47#define AR9300_DEVID_AR9485_PCIE 0x0032 47#define AR9300_DEVID_AR9485_PCIE 0x0032
48#define AR9300_DEVID_AR9580 0x0033 48#define AR9300_DEVID_AR9580 0x0033
49#define AR9300_DEVID_AR9480 0x0034 49#define AR9300_DEVID_AR9462 0x0034
50#define AR9300_DEVID_AR9330 0x0035 50#define AR9300_DEVID_AR9330 0x0035
51 51
52#define AR5416_AR9100_DEVID 0x000b 52#define AR5416_AR9100_DEVID 0x000b
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index d67d6eee3954..edb0b4b3da3a 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -33,7 +33,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
33 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 33 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
34 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ 34 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
35 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ 35 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
36 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9480 */ 36 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */
37 { 0 } 37 { 0 }
38}; 38};
39 39
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 87a1245a68e0..8fcb7e9e8399 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -796,9 +796,9 @@
796#define AR_SREV_VERSION_9340 0x300 796#define AR_SREV_VERSION_9340 0x300
797#define AR_SREV_VERSION_9580 0x1C0 797#define AR_SREV_VERSION_9580 0x1C0
798#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */ 798#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */
799#define AR_SREV_VERSION_9480 0x280 799#define AR_SREV_VERSION_9462 0x280
800#define AR_SREV_REVISION_9480_10 0 800#define AR_SREV_REVISION_9462_10 0
801#define AR_SREV_REVISION_9480_20 2 801#define AR_SREV_REVISION_9462_20 2
802 802
803#define AR_SREV_5416(_ah) \ 803#define AR_SREV_5416(_ah) \
804 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 804 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -895,20 +895,20 @@
895 (AR_SREV_9285_12_OR_LATER(_ah) && \ 895 (AR_SREV_9285_12_OR_LATER(_ah) && \
896 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 896 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
897 897
898#define AR_SREV_9480(_ah) \ 898#define AR_SREV_9462(_ah) \
899 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480)) 899 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462))
900 900
901#define AR_SREV_9480_10(_ah) \ 901#define AR_SREV_9462_10(_ah) \
902 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \ 902 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
903 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9480_10)) 903 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_10))
904 904
905#define AR_SREV_9480_20(_ah) \ 905#define AR_SREV_9462_20(_ah) \
906 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \ 906 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
907 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9480_20)) 907 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_20))
908 908
909#define AR_SREV_9480_20_OR_LATER(_ah) \ 909#define AR_SREV_9462_20_OR_LATER(_ah) \
910 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9480) && \ 910 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \
911 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9480_20)) 911 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20))
912 912
913#define AR_SREV_9580(_ah) \ 913#define AR_SREV_9580(_ah) \
914 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \ 914 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 05:07:16 -0500