diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index cee5d9ceb3b8..c6629bd9430f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -759,22 +759,18 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |||
759 | static void ironlake_edp_panel_on (struct drm_device *dev) | 759 | static void ironlake_edp_panel_on (struct drm_device *dev) |
760 | { | 760 | { |
761 | struct drm_i915_private *dev_priv = dev->dev_private; | 761 | struct drm_i915_private *dev_priv = dev->dev_private; |
762 | unsigned long timeout = jiffies + msecs_to_jiffies(5000); | 762 | u32 pp; |
763 | u32 pp, pp_status; | ||
764 | 763 | ||
765 | pp_status = I915_READ(PCH_PP_STATUS); | 764 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
766 | if (pp_status & PP_ON) | ||
767 | return; | 765 | return; |
768 | 766 | ||
769 | pp = I915_READ(PCH_PP_CONTROL); | 767 | pp = I915_READ(PCH_PP_CONTROL); |
770 | pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; | 768 | pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; |
771 | I915_WRITE(PCH_PP_CONTROL, pp); | 769 | I915_WRITE(PCH_PP_CONTROL, pp); |
772 | do { | ||
773 | pp_status = I915_READ(PCH_PP_STATUS); | ||
774 | } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout)); | ||
775 | 770 | ||
776 | if (time_after(jiffies, timeout)) | 771 | if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000, 10)) |
777 | DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status); | 772 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
773 | I915_READ(PCH_PP_STATUS)); | ||
778 | 774 | ||
779 | pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); | 775 | pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); |
780 | I915_WRITE(PCH_PP_CONTROL, pp); | 776 | I915_WRITE(PCH_PP_CONTROL, pp); |
@@ -783,18 +779,15 @@ static void ironlake_edp_panel_on (struct drm_device *dev) | |||
783 | static void ironlake_edp_panel_off (struct drm_device *dev) | 779 | static void ironlake_edp_panel_off (struct drm_device *dev) |
784 | { | 780 | { |
785 | struct drm_i915_private *dev_priv = dev->dev_private; | 781 | struct drm_i915_private *dev_priv = dev->dev_private; |
786 | unsigned long timeout = jiffies + msecs_to_jiffies(5000); | 782 | u32 pp; |
787 | u32 pp, pp_status; | ||
788 | 783 | ||
789 | pp = I915_READ(PCH_PP_CONTROL); | 784 | pp = I915_READ(PCH_PP_CONTROL); |
790 | pp &= ~POWER_TARGET_ON; | 785 | pp &= ~POWER_TARGET_ON; |
791 | I915_WRITE(PCH_PP_CONTROL, pp); | 786 | I915_WRITE(PCH_PP_CONTROL, pp); |
792 | do { | ||
793 | pp_status = I915_READ(PCH_PP_STATUS); | ||
794 | } while ((pp_status & PP_ON) && !time_after(jiffies, timeout)); | ||
795 | 787 | ||
796 | if (time_after(jiffies, timeout)) | 788 | if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000, 10)) |
797 | DRM_DEBUG_KMS("panel off wait timed out\n"); | 789 | DRM_ERROR("panel off wait timed out: 0x%08x\n", |
790 | I915_READ(PCH_PP_STATUS)); | ||
798 | 791 | ||
799 | /* Make sure VDD is enabled so DP AUX will work */ | 792 | /* Make sure VDD is enabled so DP AUX will work */ |
800 | pp |= EDP_FORCE_VDD; | 793 | pp |= EDP_FORCE_VDD; |