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authorChris Wilson <chris@chris-wilson.co.uk>2010-08-07 06:01:35 -0400
committerEric Anholt <eric@anholt.net>2010-08-09 14:24:35 -0400
commit913d8d110078788c14812dce8bb62c37946821d2 (patch)
tree982a622078194b438bf75d0ee4c77cf1e4f0260e /drivers/gpu/drm/i915/intel_dp.c
parentdd785e35cb3c430c2290d351e67715864f7e5db5 (diff)
drm/i915: Ensure that while(INREG()) are bounded (v2)
Add a new macro, wait_for, to simplify the act of waiting on a register to change state. wait_for() takes three arguments, the condition to inspect on every loop, the maximum amount of time to wait and whether to yield the cpu for a length of time after each check. v2: Upgrade failure messages to DRM_ERROR on the suggestion of Eric Anholt. We do not expect to hit these conditions as they reflect programming errors, so if we do we want to be notified. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c25
1 files changed, 9 insertions, 16 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cee5d9ceb3b8..c6629bd9430f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -759,22 +759,18 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
759static void ironlake_edp_panel_on (struct drm_device *dev) 759static void ironlake_edp_panel_on (struct drm_device *dev)
760{ 760{
761 struct drm_i915_private *dev_priv = dev->dev_private; 761 struct drm_i915_private *dev_priv = dev->dev_private;
762 unsigned long timeout = jiffies + msecs_to_jiffies(5000); 762 u32 pp;
763 u32 pp, pp_status;
764 763
765 pp_status = I915_READ(PCH_PP_STATUS); 764 if (I915_READ(PCH_PP_STATUS) & PP_ON)
766 if (pp_status & PP_ON)
767 return; 765 return;
768 766
769 pp = I915_READ(PCH_PP_CONTROL); 767 pp = I915_READ(PCH_PP_CONTROL);
770 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 768 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
771 I915_WRITE(PCH_PP_CONTROL, pp); 769 I915_WRITE(PCH_PP_CONTROL, pp);
772 do {
773 pp_status = I915_READ(PCH_PP_STATUS);
774 } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
775 770
776 if (time_after(jiffies, timeout)) 771 if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000, 10))
777 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status); 772 DRM_ERROR("panel on wait timed out: 0x%08x\n",
773 I915_READ(PCH_PP_STATUS));
778 774
779 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); 775 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
780 I915_WRITE(PCH_PP_CONTROL, pp); 776 I915_WRITE(PCH_PP_CONTROL, pp);
@@ -783,18 +779,15 @@ static void ironlake_edp_panel_on (struct drm_device *dev)
783static void ironlake_edp_panel_off (struct drm_device *dev) 779static void ironlake_edp_panel_off (struct drm_device *dev)
784{ 780{
785 struct drm_i915_private *dev_priv = dev->dev_private; 781 struct drm_i915_private *dev_priv = dev->dev_private;
786 unsigned long timeout = jiffies + msecs_to_jiffies(5000); 782 u32 pp;
787 u32 pp, pp_status;
788 783
789 pp = I915_READ(PCH_PP_CONTROL); 784 pp = I915_READ(PCH_PP_CONTROL);
790 pp &= ~POWER_TARGET_ON; 785 pp &= ~POWER_TARGET_ON;
791 I915_WRITE(PCH_PP_CONTROL, pp); 786 I915_WRITE(PCH_PP_CONTROL, pp);
792 do {
793 pp_status = I915_READ(PCH_PP_STATUS);
794 } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
795 787
796 if (time_after(jiffies, timeout)) 788 if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000, 10))
797 DRM_DEBUG_KMS("panel off wait timed out\n"); 789 DRM_ERROR("panel off wait timed out: 0x%08x\n",
790 I915_READ(PCH_PP_STATUS));
798 791
799 /* Make sure VDD is enabled so DP AUX will work */ 792 /* Make sure VDD is enabled so DP AUX will work */
800 pp |= EDP_FORCE_VDD; 793 pp |= EDP_FORCE_VDD;