aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/platforms
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/512x/mpc512x_shared.c5
-rw-r--r--arch/powerpc/platforms/82xx/km82xx.c6
-rw-r--r--arch/powerpc/platforms/83xx/km83xx.c161
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig7
-rw-r--r--arch/powerpc/platforms/85xx/Makefile1
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c4
-rw-r--r--arch/powerpc/platforms/85xx/p1022_ds.c40
-rw-r--r--arch/powerpc/platforms/85xx/p1022_rdk.c12
-rw-r--r--arch/powerpc/platforms/85xx/ppa8548.c98
-rw-r--r--arch/powerpc/platforms/85xx/qemu_e500.c7
10 files changed, 198 insertions, 143 deletions
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index 35f14fda108a..c7f47cfa9c29 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -68,10 +68,6 @@ struct fsl_diu_shared_fb {
68 bool in_use; 68 bool in_use;
69}; 69};
70 70
71void mpc512x_set_monitor_port(enum fsl_diu_monitor_port port)
72{
73}
74
75#define DIU_DIV_MASK 0x000000ff 71#define DIU_DIV_MASK 0x000000ff
76void mpc512x_set_pixel_clock(unsigned int pixclock) 72void mpc512x_set_pixel_clock(unsigned int pixclock)
77{ 73{
@@ -303,7 +299,6 @@ void __init mpc512x_setup_diu(void)
303 } 299 }
304 } 300 }
305 301
306 diu_ops.set_monitor_port = mpc512x_set_monitor_port;
307 diu_ops.set_pixel_clock = mpc512x_set_pixel_clock; 302 diu_ops.set_pixel_clock = mpc512x_set_pixel_clock;
308 diu_ops.valid_monitor_port = mpc512x_valid_monitor_port; 303 diu_ops.valid_monitor_port = mpc512x_valid_monitor_port;
309 diu_ops.release_bootmem = mpc512x_release_bootmem; 304 diu_ops.release_bootmem = mpc512x_release_bootmem;
diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c
index cf964e19573a..058cc1895c88 100644
--- a/arch/powerpc/platforms/82xx/km82xx.c
+++ b/arch/powerpc/platforms/82xx/km82xx.c
@@ -18,11 +18,11 @@
18#include <linux/fsl_devices.h> 18#include <linux/fsl_devices.h>
19#include <linux/of_platform.h> 19#include <linux/of_platform.h>
20 20
21#include <asm/io.h> 21#include <linux/io.h>
22#include <asm/cpm2.h> 22#include <asm/cpm2.h>
23#include <asm/udbg.h> 23#include <asm/udbg.h>
24#include <asm/machdep.h> 24#include <asm/machdep.h>
25#include <asm/time.h> 25#include <linux/time.h>
26#include <asm/mpc8260.h> 26#include <asm/mpc8260.h>
27#include <asm/prom.h> 27#include <asm/prom.h>
28 28
@@ -36,7 +36,7 @@ static void __init km82xx_pic_init(void)
36 struct device_node *np = of_find_compatible_node(NULL, NULL, 36 struct device_node *np = of_find_compatible_node(NULL, NULL,
37 "fsl,pq2-pic"); 37 "fsl,pq2-pic");
38 if (!np) { 38 if (!np) {
39 printk(KERN_ERR "PIC init: can not find cpm-pic node\n"); 39 pr_err("PIC init: can not find cpm-pic node\n");
40 return; 40 return;
41 } 41 }
42 42
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index 89923d723349..bf4c4473abb9 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -28,8 +28,8 @@
28#include <linux/of_device.h> 28#include <linux/of_device.h>
29 29
30#include <linux/atomic.h> 30#include <linux/atomic.h>
31#include <asm/time.h> 31#include <linux/time.h>
32#include <asm/io.h> 32#include <linux/io.h>
33#include <asm/machdep.h> 33#include <asm/machdep.h>
34#include <asm/ipic.h> 34#include <asm/ipic.h>
35#include <asm/irq.h> 35#include <asm/irq.h>
@@ -43,6 +43,82 @@
43#include "mpc83xx.h" 43#include "mpc83xx.h"
44 44
45#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ 45#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
46
47static void quirk_mpc8360e_qe_enet10(void)
48{
49 /*
50 * handle mpc8360E Erratum QE_ENET10:
51 * RGMII AC values do not meet the specification
52 */
53 uint svid = mfspr(SPRN_SVR);
54 struct device_node *np_par;
55 struct resource res;
56 void __iomem *base;
57 int ret;
58
59 np_par = of_find_node_by_name(NULL, "par_io");
60 if (np_par == NULL) {
61 pr_warn("%s couldn;t find par_io node\n", __func__);
62 return;
63 }
64 /* Map Parallel I/O ports registers */
65 ret = of_address_to_resource(np_par, 0, &res);
66 if (ret) {
67 pr_warn("%s couldn;t map par_io registers\n", __func__);
68 return;
69 }
70
71 base = ioremap(res.start, res.end - res.start + 1);
72
73 /*
74 * set output delay adjustments to default values according
75 * table 5 in Errata Rev. 5, 9/2011:
76 *
77 * write 0b01 to UCC1 bits 18:19
78 * write 0b01 to UCC2 option 1 bits 4:5
79 * write 0b01 to UCC2 option 2 bits 16:17
80 */
81 clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
82
83 /*
84 * set output delay adjustments to default values according
85 * table 3-13 in Reference Manual Rev.3 05/2010:
86 *
87 * write 0b01 to UCC2 option 2 bits 16:17
88 * write 0b0101 to UCC1 bits 20:23
89 * write 0b0101 to UCC2 option 1 bits 24:27
90 */
91 clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
92
93 if (SVR_REV(svid) == 0x0021) {
94 /*
95 * UCC2 option 1: write 0b1010 to bits 24:27
96 * at address IMMRBAR+0x14AC
97 */
98 clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
99 } else if (SVR_REV(svid) == 0x0020) {
100 /*
101 * UCC1: write 0b11 to bits 18:19
102 * at address IMMRBAR+0x14A8
103 */
104 setbits32((base + 0xa8), 0x00003000);
105
106 /*
107 * UCC2 option 1: write 0b11 to bits 4:5
108 * at address IMMRBAR+0x14A8
109 */
110 setbits32((base + 0xa8), 0x0c000000);
111
112 /*
113 * UCC2 option 2: write 0b11 to bits 16:17
114 * at address IMMRBAR+0x14AC
115 */
116 setbits32((base + 0xac), 0x0000c000);
117 }
118 iounmap(base);
119 of_node_put(np_par);
120}
121
46/* ************************************************************************ 122/* ************************************************************************
47 * 123 *
48 * Setup the architecture 124 * Setup the architecture
@@ -72,84 +148,13 @@ static void __init mpc83xx_km_setup_arch(void)
72 148
73 for_each_node_by_name(np, "ucc") 149 for_each_node_by_name(np, "ucc")
74 par_io_of_config(np); 150 par_io_of_config(np);
75 }
76
77 np = of_find_compatible_node(NULL, "network", "ucc_geth");
78 if (np != NULL) {
79 /*
80 * handle mpc8360E Erratum QE_ENET10:
81 * RGMII AC values do not meet the specification
82 */
83 uint svid = mfspr(SPRN_SVR);
84 struct device_node *np_par;
85 struct resource res;
86 void __iomem *base;
87 int ret;
88
89 np_par = of_find_node_by_name(NULL, "par_io");
90 if (np_par == NULL) {
91 printk(KERN_WARNING "%s couldn;t find par_io node\n",
92 __func__);
93 return;
94 }
95 /* Map Parallel I/O ports registers */
96 ret = of_address_to_resource(np_par, 0, &res);
97 if (ret) {
98 printk(KERN_WARNING "%s couldn;t map par_io registers\n",
99 __func__);
100 return;
101 }
102
103 base = ioremap(res.start, res.end - res.start + 1);
104
105 /*
106 * set output delay adjustments to default values according
107 * table 5 in Errata Rev. 5, 9/2011:
108 *
109 * write 0b01 to UCC1 bits 18:19
110 * write 0b01 to UCC2 option 1 bits 4:5
111 * write 0b01 to UCC2 option 2 bits 16:17
112 */
113 clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
114 151
115 /* 152 /* Only apply this quirk when par_io is available */
116 * set output delay adjustments to default values according 153 np = of_find_compatible_node(NULL, "network", "ucc_geth");
117 * table 3-13 in Reference Manual Rev.3 05/2010: 154 if (np != NULL) {
118 * 155 quirk_mpc8360e_qe_enet10();
119 * write 0b01 to UCC2 option 2 bits 16:17 156 of_node_put(np);
120 * write 0b0101 to UCC1 bits 20:23
121 * write 0b0101 to UCC2 option 1 bits 24:27
122 */
123 clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
124
125 if (SVR_REV(svid) == 0x0021) {
126 /*
127 * UCC2 option 1: write 0b1010 to bits 24:27
128 * at address IMMRBAR+0x14AC
129 */
130 clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
131 } else if (SVR_REV(svid) == 0x0020) {
132 /*
133 * UCC1: write 0b11 to bits 18:19
134 * at address IMMRBAR+0x14A8
135 */
136 setbits32((base + 0xa8), 0x00003000);
137
138 /*
139 * UCC2 option 1: write 0b11 to bits 4:5
140 * at address IMMRBAR+0x14A8
141 */
142 setbits32((base + 0xa8), 0x0c000000);
143
144 /*
145 * UCC2 option 2: write 0b11 to bits 16:17
146 * at address IMMRBAR+0x14AC
147 */
148 setbits32((base + 0xac), 0x0000c000);
149 } 157 }
150 iounmap(base);
151 of_node_put(np_par);
152 of_node_put(np);
153 } 158 }
154#endif /* CONFIG_QUICC_ENGINE */ 159#endif /* CONFIG_QUICC_ENGINE */
155} 160}
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 651788cbc6e6..bcc53aa09bf7 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -191,6 +191,13 @@ config SBC8548
191 help 191 help
192 This option enables support for the Wind River SBC8548 board 192 This option enables support for the Wind River SBC8548 board
193 193
194config PPA8548
195 bool "Prodrive PPA8548"
196 help
197 This option enables support for the Prodrive PPA8548 board.
198 select DEFAULT_UIMAGE
199 select HAS_RAPIDIO
200
194config GE_IMP3A 201config GE_IMP3A
195 bool "GE Intelligent Platforms IMP3A" 202 bool "GE Intelligent Platforms IMP3A"
196 select DEFAULT_UIMAGE 203 select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 9db31dcbd320..07d0dbb141c0 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
25obj-$(CONFIG_STX_GP3) += stx_gp3.o 25obj-$(CONFIG_STX_GP3) += stx_gp3.o
26obj-$(CONFIG_TQM85xx) += tqm85xx.o 26obj-$(CONFIG_TQM85xx) += tqm85xx.o
27obj-$(CONFIG_SBC8548) += sbc8548.o 27obj-$(CONFIG_SBC8548) += sbc8548.o
28obj-$(CONFIG_PPA8548) += ppa8548.o
28obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o 29obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
29obj-$(CONFIG_KSI8560) += ksi8560.o 30obj-$(CONFIG_KSI8560) += ksi8560.o
30obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o 31obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index bd12588fa252..a7b3621a8df5 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -206,9 +206,7 @@ static void __init mpc85xx_mds_reset_ucc_phys(void)
206 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); 206 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
207 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); 207 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
208 208
209 for (np = NULL; (np = of_find_compatible_node(np, 209 for_each_compatible_node(np, "network", "ucc_geth") {
210 "network",
211 "ucc_geth")) != NULL;) {
212 const unsigned int *prop; 210 const unsigned int *prop;
213 int ucc_num; 211 int ucc_num;
214 212
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 7328b8d74129..c3e47144d0e4 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -106,42 +106,6 @@
106 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \ 106 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
107 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT)) 107 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
108 108
109/**
110 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
111 *
112 * The Area Descriptor is a 32-bit value that determine which bits in each
113 * pixel are to be used for each color.
114 */
115static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
116 unsigned int bits_per_pixel)
117{
118 switch (bits_per_pixel) {
119 case 32:
120 /* 0x88883316 */
121 return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
122 case 24:
123 /* 0x88082219 */
124 return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
125 case 16:
126 /* 0x65053118 */
127 return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
128 default:
129 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
130 return 0;
131 }
132}
133
134/**
135 * p1022ds_set_gamma_table: update the gamma table, if necessary
136 *
137 * On some boards, the gamma table for some ports may need to be modified.
138 * This is not the case on the P1022DS, so we do nothing.
139*/
140static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
141 char *gamma_table_base)
142{
143}
144
145struct fsl_law { 109struct fsl_law {
146 u32 lawbar; 110 u32 lawbar;
147 u32 reserved1; 111 u32 reserved1;
@@ -302,7 +266,7 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
302 goto exit; 266 goto exit;
303 } 267 }
304 cs1_addr = lbc_br_to_phys(ecm, num_laws, br1); 268 cs1_addr = lbc_br_to_phys(ecm, num_laws, br1);
305 if (!cs0_addr) { 269 if (!cs1_addr) {
306 pr_err("p1022ds: could not determine physical address for CS1" 270 pr_err("p1022ds: could not determine physical address for CS1"
307 " (BR1=%08x)\n", br1); 271 " (BR1=%08x)\n", br1);
308 goto exit; 272 goto exit;
@@ -510,8 +474,6 @@ static void __init p1022_ds_setup_arch(void)
510 ppc_md.progress("p1022_ds_setup_arch()", 0); 474 ppc_md.progress("p1022_ds_setup_arch()", 0);
511 475
512#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 476#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
513 diu_ops.get_pixel_format = p1022ds_get_pixel_format;
514 diu_ops.set_gamma_table = p1022ds_set_gamma_table;
515 diu_ops.set_monitor_port = p1022ds_set_monitor_port; 477 diu_ops.set_monitor_port = p1022ds_set_monitor_port;
516 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock; 478 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
517 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port; 479 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c
index 55ffa1cc380c..8c9297112b30 100644
--- a/arch/powerpc/platforms/85xx/p1022_rdk.c
+++ b/arch/powerpc/platforms/85xx/p1022_rdk.c
@@ -35,17 +35,6 @@
35#define CLKDVDR_PXCLK_MASK 0x00FF0000 35#define CLKDVDR_PXCLK_MASK 0x00FF0000
36 36
37/** 37/**
38 * p1022rdk_set_monitor_port: switch the output to a different monitor port
39 */
40static void p1022rdk_set_monitor_port(enum fsl_diu_monitor_port port)
41{
42 if (port != FSL_DIU_PORT_DVI) {
43 pr_err("p1022rdk: unsupported monitor port %i\n", port);
44 return;
45 }
46}
47
48/**
49 * p1022rdk_set_pixel_clock: program the DIU's clock 38 * p1022rdk_set_pixel_clock: program the DIU's clock
50 * 39 *
51 * @pixclock: the wavelength, in picoseconds, of the clock 40 * @pixclock: the wavelength, in picoseconds, of the clock
@@ -124,7 +113,6 @@ static void __init p1022_rdk_setup_arch(void)
124 ppc_md.progress("p1022_rdk_setup_arch()", 0); 113 ppc_md.progress("p1022_rdk_setup_arch()", 0);
125 114
126#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 115#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
127 diu_ops.set_monitor_port = p1022rdk_set_monitor_port;
128 diu_ops.set_pixel_clock = p1022rdk_set_pixel_clock; 116 diu_ops.set_pixel_clock = p1022rdk_set_pixel_clock;
129 diu_ops.valid_monitor_port = p1022rdk_valid_monitor_port; 117 diu_ops.valid_monitor_port = p1022rdk_valid_monitor_port;
130#endif 118#endif
diff --git a/arch/powerpc/platforms/85xx/ppa8548.c b/arch/powerpc/platforms/85xx/ppa8548.c
new file mode 100644
index 000000000000..6a7704b92c3b
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/ppa8548.c
@@ -0,0 +1,98 @@
1/*
2 * ppa8548 setup and early boot code.
3 *
4 * Copyright 2009 Prodrive B.V..
5 *
6 * By Stef van Os (see MAINTAINERS for contact information)
7 *
8 * Based on the SBC8548 support - Copyright 2007 Wind River Systems Inc.
9 * Based on the MPC8548CDS support - Copyright 2005 Freescale Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/reboot.h>
21#include <linux/seq_file.h>
22#include <linux/of_platform.h>
23
24#include <asm/machdep.h>
25#include <asm/udbg.h>
26#include <asm/mpic.h>
27
28#include <sysdev/fsl_soc.h>
29
30static void __init ppa8548_pic_init(void)
31{
32 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
33 0, 256, " OpenPIC ");
34 BUG_ON(mpic == NULL);
35 mpic_init(mpic);
36}
37
38/*
39 * Setup the architecture
40 */
41static void __init ppa8548_setup_arch(void)
42{
43 if (ppc_md.progress)
44 ppc_md.progress("ppa8548_setup_arch()", 0);
45}
46
47static void ppa8548_show_cpuinfo(struct seq_file *m)
48{
49 uint32_t svid, phid1;
50
51 svid = mfspr(SPRN_SVR);
52
53 seq_printf(m, "Vendor\t\t: Prodrive B.V.\n");
54 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
55
56 /* Display cpu Pll setting */
57 phid1 = mfspr(SPRN_HID1);
58 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
59}
60
61static struct of_device_id __initdata of_bus_ids[] = {
62 { .name = "soc", },
63 { .type = "soc", },
64 { .compatible = "simple-bus", },
65 { .compatible = "gianfar", },
66 { .compatible = "fsl,srio", },
67 {},
68};
69
70static int __init declare_of_platform_devices(void)
71{
72 of_platform_bus_probe(NULL, of_bus_ids, NULL);
73
74 return 0;
75}
76machine_device_initcall(ppa8548, declare_of_platform_devices);
77
78/*
79 * Called very early, device-tree isn't unflattened
80 */
81static int __init ppa8548_probe(void)
82{
83 unsigned long root = of_get_flat_dt_root();
84
85 return of_flat_dt_is_compatible(root, "ppa8548");
86}
87
88define_machine(ppa8548) {
89 .name = "ppa8548",
90 .probe = ppa8548_probe,
91 .setup_arch = ppa8548_setup_arch,
92 .init_IRQ = ppa8548_pic_init,
93 .show_cpuinfo = ppa8548_show_cpuinfo,
94 .get_irq = mpic_get_irq,
95 .restart = fsl_rstcr_restart,
96 .calibrate_decr = generic_calibrate_decr,
97 .progress = udbg_progress,
98};
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c
index f6ea5618c733..5cefc5a9a144 100644
--- a/arch/powerpc/platforms/85xx/qemu_e500.c
+++ b/arch/powerpc/platforms/85xx/qemu_e500.c
@@ -29,9 +29,10 @@
29void __init qemu_e500_pic_init(void) 29void __init qemu_e500_pic_init(void)
30{ 30{
31 struct mpic *mpic; 31 struct mpic *mpic;
32 unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
33 MPIC_ENABLE_COREINT;
32 34
33 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU, 35 mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC ");
34 0, 256, " OpenPIC ");
35 36
36 BUG_ON(mpic == NULL); 37 BUG_ON(mpic == NULL);
37 mpic_init(mpic); 38 mpic_init(mpic);
@@ -66,7 +67,7 @@ define_machine(qemu_e500) {
66#ifdef CONFIG_PCI 67#ifdef CONFIG_PCI
67 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 68 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
68#endif 69#endif
69 .get_irq = mpic_get_irq, 70 .get_irq = mpic_get_coreint_irq,
70 .restart = fsl_rstcr_restart, 71 .restart = fsl_rstcr_restart,
71 .calibrate_decr = generic_calibrate_decr, 72 .calibrate_decr = generic_calibrate_decr,
72 .progress = udbg_progress, 73 .progress = udbg_progress,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 04:06:57 -0500