Merge remote-tracking branch 'kumar/next' into next

<<
Mostly misc code cleanups in various board ports and adding support for a
new MPC85xx board - ppa8548.
>>

10 files changed, 198 insertions, 143 deletions

diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index 35f14fda108a..c7f47cfa9c29 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -68,10 +68,6 @@ struct fsl_diu_shared_fb {
         bool            in_use;
 };
 
-void mpc512x_set_monitor_port(enum fsl_diu_monitor_port port)
-{
-}
-
 #define DIU_DIV_MASK    0x000000ff
 void mpc512x_set_pixel_clock(unsigned int pixclock)
 {
@@ -303,7 +299,6 @@ void __init mpc512x_setup_diu(void)
                 }
         }
 
-        diu_ops.set_monitor_port        = mpc512x_set_monitor_port;
         diu_ops.set_pixel_clock         = mpc512x_set_pixel_clock;
         diu_ops.valid_monitor_port      = mpc512x_valid_monitor_port;
         diu_ops.release_bootmem         = mpc512x_release_bootmem;
diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c
index cf964e19573a..058cc1895c88 100644
--- a/arch/powerpc/platforms/82xx/km82xx.c
+++ b/arch/powerpc/platforms/82xx/km82xx.c
@@ -18,11 +18,11 @@
 #include <linux/fsl_devices.h>
 #include <linux/of_platform.h>
 
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/cpm2.h>
 #include <asm/udbg.h>
 #include <asm/machdep.h>
-#include <asm/time.h>
+#include <linux/time.h>
 #include <asm/mpc8260.h>
 #include <asm/prom.h>
 
@@ -36,7 +36,7 @@ static void __init km82xx_pic_init(void)
         struct device_node *np = of_find_compatible_node(NULL, NULL,
                                                         "fsl,pq2-pic");
         if (!np) {
-                printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
+                pr_err("PIC init: can not find cpm-pic node\n");
                 return;
         }
 
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index 89923d723349..bf4c4473abb9 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -28,8 +28,8 @@
 #include <linux/of_device.h>
 
 #include <linux/atomic.h>
-#include <asm/time.h>
-#include <asm/io.h>
+#include <linux/time.h>
+#include <linux/io.h>
 #include <asm/machdep.h>
 #include <asm/ipic.h>
 #include <asm/irq.h>
@@ -43,6 +43,82 @@
 #include "mpc83xx.h"
 
 #define SVR_REV(svr)    (((svr) >>  0) & 0xFFFF) /* Revision field */
+
+static void quirk_mpc8360e_qe_enet10(void)
+{
+        /*
+         * handle mpc8360E Erratum QE_ENET10:
+         * RGMII AC values do not meet the specification
+         */
+        uint svid = mfspr(SPRN_SVR);
+        struct  device_node *np_par;
+        struct  resource res;
+        void    __iomem *base;
+        int     ret;
+
+        np_par = of_find_node_by_name(NULL, "par_io");
+        if (np_par == NULL) {
+                pr_warn("%s couldn;t find par_io node\n", __func__);
+                return;
+        }
+        /* Map Parallel I/O ports registers */
+        ret = of_address_to_resource(np_par, 0, &res);
+        if (ret) {
+                pr_warn("%s couldn;t map par_io registers\n", __func__);
+                return;
+        }
+
+        base = ioremap(res.start, res.end - res.start + 1);
+
+        /*
+         * set output delay adjustments to default values according
+         * table 5 in Errata Rev. 5, 9/2011:
+         *
+         * write 0b01 to UCC1 bits 18:19
+         * write 0b01 to UCC2 option 1 bits 4:5
+         * write 0b01 to UCC2 option 2 bits 16:17
+         */
+        clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
+
+        /*
+         * set output delay adjustments to default values according
+         * table 3-13 in Reference Manual Rev.3 05/2010:
+         *
+         * write 0b01 to UCC2 option 2 bits 16:17
+         * write 0b0101 to UCC1 bits 20:23
+         * write 0b0101 to UCC2 option 1 bits 24:27
+         */
+        clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
+
+        if (SVR_REV(svid) == 0x0021) {
+                /*
+                 * UCC2 option 1: write 0b1010 to bits 24:27
+                 * at address IMMRBAR+0x14AC
+                 */
+                clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
+        } else if (SVR_REV(svid) == 0x0020) {
+                /*
+                 * UCC1: write 0b11 to bits 18:19
+                 * at address IMMRBAR+0x14A8
+                 */
+                setbits32((base + 0xa8), 0x00003000);
+
+                /*
+                 * UCC2 option 1: write 0b11 to bits 4:5
+                 * at address IMMRBAR+0x14A8
+                 */
+                setbits32((base + 0xa8), 0x0c000000);
+
+                /*
+                 * UCC2 option 2: write 0b11 to bits 16:17
+                 * at address IMMRBAR+0x14AC
+                 */
+                setbits32((base + 0xac), 0x0000c000);
+        }
+        iounmap(base);
+        of_node_put(np_par);
+}
+
 /* ************************************************************************
  *
  * Setup the architecture
@@ -72,84 +148,13 @@ static void __init mpc83xx_km_setup_arch(void)
 
                 for_each_node_by_name(np, "ucc")
                         par_io_of_config(np);
-        }
-
-        np = of_find_compatible_node(NULL, "network", "ucc_geth");
-        if (np != NULL) {
-                /*
-                 * handle mpc8360E Erratum QE_ENET10:
-                 * RGMII AC values do not meet the specification
-                 */
-                uint svid = mfspr(SPRN_SVR);
-                struct  device_node *np_par;
-                struct  resource res;
-                void    __iomem *base;
-                int     ret;
-
-                np_par = of_find_node_by_name(NULL, "par_io");
-                if (np_par == NULL) {
-                        printk(KERN_WARNING "%s couldn;t find par_io node\n",
-                                __func__);
-                        return;
-                }
-                /* Map Parallel I/O ports registers */
-                ret = of_address_to_resource(np_par, 0, &res);
-                if (ret) {
-                        printk(KERN_WARNING "%s couldn;t map par_io registers\n",
-                                __func__);
-                        return;
-                }
-
-                base = ioremap(res.start, res.end - res.start + 1);
-
-                /*
-                 * set output delay adjustments to default values according
-                 * table 5 in Errata Rev. 5, 9/2011:
-                 *
-                 * write 0b01 to UCC1 bits 18:19
-                 * write 0b01 to UCC2 option 1 bits 4:5
-                 * write 0b01 to UCC2 option 2 bits 16:17
-                 */
-                clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
 
-                /*
-                 * set output delay adjustments to default values according
-                 * table 3-13 in Reference Manual Rev.3 05/2010:
-                 *
-                 * write 0b01 to UCC2 option 2 bits 16:17
-                 * write 0b0101 to UCC1 bits 20:23
-                 * write 0b0101 to UCC2 option 1 bits 24:27
-                 */
-                clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
-
-                if (SVR_REV(svid) == 0x0021) {
-                        /*
-                         * UCC2 option 1: write 0b1010 to bits 24:27
-                         * at address IMMRBAR+0x14AC
-                         */
-                        clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
-                } else if (SVR_REV(svid) == 0x0020) {
-                        /*
-                         * UCC1: write 0b11 to bits 18:19
-                         * at address IMMRBAR+0x14A8
-                         */
-                        setbits32((base + 0xa8), 0x00003000);
-
-                        /*
-                         * UCC2 option 1: write 0b11 to bits 4:5
-                         * at address IMMRBAR+0x14A8
-                         */
-                        setbits32((base + 0xa8), 0x0c000000);
-
-                        /*
-                         * UCC2 option 2: write 0b11 to bits 16:17
-                         * at address IMMRBAR+0x14AC
-                         */
-                        setbits32((base + 0xac), 0x0000c000);
+                /* Only apply this quirk when par_io is available */
+                np = of_find_compatible_node(NULL, "network", "ucc_geth");
+                if (np != NULL) {
+                        quirk_mpc8360e_qe_enet10();
+                        of_node_put(np);
                 }
-                iounmap(base);
-                of_node_put(np_par);
-                of_node_put(np);
         }
 #endif  /* CONFIG_QUICC_ENGINE */
 }
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 651788cbc6e6..bcc53aa09bf7 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -191,6 +191,13 @@ config SBC8548
         help
           This option enables support for the Wind River SBC8548 board
 
+config PPA8548
+        bool "Prodrive PPA8548"
+        help
+          This option enables support for the Prodrive PPA8548 board.
+        select DEFAULT_UIMAGE
+        select HAS_RAPIDIO
+
 config GE_IMP3A
         bool "GE Intelligent Platforms IMP3A"
         select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 9db31dcbd320..07d0dbb141c0 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_P5040_DS)    += p5040_ds.o corenet_ds.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
 obj-$(CONFIG_SBC8548)     += sbc8548.o
+obj-$(CONFIG_PPA8548)     += ppa8548.o
 obj-$(CONFIG_SOCRATES)    += socrates.o socrates_fpga_pic.o
 obj-$(CONFIG_KSI8560)     += ksi8560.o
 obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index bd12588fa252..a7b3621a8df5 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -206,9 +206,7 @@ static void __init mpc85xx_mds_reset_ucc_phys(void)
                 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
                 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
 
-                for (np = NULL; (np = of_find_compatible_node(np,
-                                                "network",
-                                                "ucc_geth")) != NULL;) {
+                for_each_compatible_node(np, "network", "ucc_geth") {
                         const unsigned int *prop;
                         int ucc_num;
 
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 7328b8d74129..c3e47144d0e4 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -106,42 +106,6 @@
         (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
         (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
 
-/**
- * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
- *
- * The Area Descriptor is a 32-bit value that determine which bits in each
- * pixel are to be used for each color.
- */
-static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
-                                    unsigned int bits_per_pixel)
-{
-        switch (bits_per_pixel) {
-        case 32:
-                /* 0x88883316 */
-                return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
-        case 24:
-                /* 0x88082219 */
-                return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
-        case 16:
-                /* 0x65053118 */
-                return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
-        default:
-                pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
-                return 0;
-        }
-}
-
-/**
- * p1022ds_set_gamma_table: update the gamma table, if necessary
- *
- * On some boards, the gamma table for some ports may need to be modified.
- * This is not the case on the P1022DS, so we do nothing.
-*/
-static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
-                                    char *gamma_table_base)
-{
-}
-
 struct fsl_law {
         u32     lawbar;
         u32     reserved1;
@@ -302,7 +266,7 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
                 goto exit;
         }
         cs1_addr = lbc_br_to_phys(ecm, num_laws, br1);
-        if (!cs0_addr) {
+        if (!cs1_addr) {
                 pr_err("p1022ds: could not determine physical address for CS1"
                        " (BR1=%08x)\n", br1);
                 goto exit;
@@ -510,8 +474,6 @@ static void __init p1022_ds_setup_arch(void)
                 ppc_md.progress("p1022_ds_setup_arch()", 0);
 
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
-        diu_ops.get_pixel_format        = p1022ds_get_pixel_format;
-        diu_ops.set_gamma_table         = p1022ds_set_gamma_table;
         diu_ops.set_monitor_port        = p1022ds_set_monitor_port;
         diu_ops.set_pixel_clock         = p1022ds_set_pixel_clock;
         diu_ops.valid_monitor_port      = p1022ds_valid_monitor_port;
diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c
index 55ffa1cc380c..8c9297112b30 100644
--- a/arch/powerpc/platforms/85xx/p1022_rdk.c
+++ b/arch/powerpc/platforms/85xx/p1022_rdk.c
@@ -35,17 +35,6 @@
 #define CLKDVDR_PXCLK_MASK      0x00FF0000
 
 /**
- * p1022rdk_set_monitor_port: switch the output to a different monitor port
- */
-static void p1022rdk_set_monitor_port(enum fsl_diu_monitor_port port)
-{
-        if (port != FSL_DIU_PORT_DVI) {
-                pr_err("p1022rdk: unsupported monitor port %i\n", port);
-                return;
-        }
-}
-
-/**
  * p1022rdk_set_pixel_clock: program the DIU's clock
  *
  * @pixclock: the wavelength, in picoseconds, of the clock
@@ -124,7 +113,6 @@ static void __init p1022_rdk_setup_arch(void)
                 ppc_md.progress("p1022_rdk_setup_arch()", 0);
 
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
-        diu_ops.set_monitor_port        = p1022rdk_set_monitor_port;
         diu_ops.set_pixel_clock         = p1022rdk_set_pixel_clock;
         diu_ops.valid_monitor_port      = p1022rdk_valid_monitor_port;
 #endif
diff --git a/arch/powerpc/platforms/85xx/ppa8548.c b/arch/powerpc/platforms/85xx/ppa8548.c
new file mode 100644
index 000000000000..6a7704b92c3b
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/ppa8548.c
@@ -0,0 +1,98 @@
+/*
+ * ppa8548 setup and early boot code.
+ *
+ * Copyright 2009 Prodrive B.V..
+ *
+ * By Stef van Os (see MAINTAINERS for contact information)
+ *
+ * Based on the SBC8548 support - Copyright 2007 Wind River Systems Inc.
+ * Based on the MPC8548CDS support - Copyright 2005 Freescale Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/reboot.h>
+#include <linux/seq_file.h>
+#include <linux/of_platform.h>
+
+#include <asm/machdep.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+
+static void __init ppa8548_pic_init(void)
+{
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
+                        0, 256, " OpenPIC  ");
+        BUG_ON(mpic == NULL);
+        mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init ppa8548_setup_arch(void)
+{
+        if (ppc_md.progress)
+                ppc_md.progress("ppa8548_setup_arch()", 0);
+}
+
+static void ppa8548_show_cpuinfo(struct seq_file *m)
+{
+        uint32_t svid, phid1;
+
+        svid = mfspr(SPRN_SVR);
+
+        seq_printf(m, "Vendor\t\t: Prodrive B.V.\n");
+        seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+
+        /* Display cpu Pll setting */
+        phid1 = mfspr(SPRN_HID1);
+        seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
+}
+
+static struct of_device_id __initdata of_bus_ids[] = {
+        { .name = "soc", },
+        { .type = "soc", },
+        { .compatible = "simple-bus", },
+        { .compatible = "gianfar", },
+        { .compatible = "fsl,srio", },
+        {},
+};
+
+static int __init declare_of_platform_devices(void)
+{
+        of_platform_bus_probe(NULL, of_bus_ids, NULL);
+
+        return 0;
+}
+machine_device_initcall(ppa8548, declare_of_platform_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init ppa8548_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "ppa8548");
+}
+
+define_machine(ppa8548) {
+        .name           = "ppa8548",
+        .probe          = ppa8548_probe,
+        .setup_arch     = ppa8548_setup_arch,
+        .init_IRQ       = ppa8548_pic_init,
+        .show_cpuinfo   = ppa8548_show_cpuinfo,
+        .get_irq        = mpic_get_irq,
+        .restart        = fsl_rstcr_restart,
+        .calibrate_decr = generic_calibrate_decr,
+        .progress       = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c
index f6ea5618c733..5cefc5a9a144 100644
--- a/arch/powerpc/platforms/85xx/qemu_e500.c
+++ b/arch/powerpc/platforms/85xx/qemu_e500.c
@@ -29,9 +29,10 @@
 void __init qemu_e500_pic_init(void)
 {
         struct mpic *mpic;
+        unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
+                MPIC_ENABLE_COREINT;
 
-        mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU,
-                        0, 256, " OpenPIC  ");
+        mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC  ");
 
         BUG_ON(mpic == NULL);
         mpic_init(mpic);
@@ -66,7 +67,7 @@ define_machine(qemu_e500) {
 #ifdef CONFIG_PCI
         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 #endif
-        .get_irq                = mpic_get_irq,
+        .get_irq                = mpic_get_coreint_irq,
         .restart                = fsl_rstcr_restart,
         .calibrate_decr         = generic_calibrate_decr,
         .progress               = udbg_progress,