diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2014-03-10 02:25:56 -0400 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 09:57:56 -0400 |
| commit | 4cd4b027fa46eabddcfb9f81331bca76932c1ced (patch) | |
| tree | fe81e7f5adf94a16f3ea9963119725d42d270c1d /include/linux/mfd/syscon | |
| parent | e780694aa6cc357f35d9651f158dfdc205815bcf (diff) | |
ENGR00302472-1 ARM: imx6q: Add imx6dl LVDS mux ctrl bit definitions
This patch adds LVDS mux ctrl bit definitions for imx6dl.
The bits LVDS0/1_MUX_CTL are defined in the register IOMUXC_GPR3.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'include/linux/mfd/syscon')
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index bbbebdde44c4..260c55b589e9 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | |||
| @@ -374,6 +374,16 @@ | |||
| 374 | #define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1) | 374 | #define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1) |
| 375 | #define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0) | 375 | #define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0) |
| 376 | 376 | ||
| 377 | /* For imx6dl iomux gpr register field definitions */ | ||
| 378 | #define IMX6DL_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8) | ||
| 379 | #define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8) | ||
| 380 | #define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8) | ||
| 381 | #define IMX6DL_GPR3_LVDS1_MUX_CTL_LCDIF (0x2 << 8) | ||
| 382 | #define IMX6DL_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6) | ||
| 383 | #define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6) | ||
| 384 | #define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6) | ||
| 385 | #define IMX6DL_GPR3_LVDS0_MUX_CTL_LCDIF (0x2 << 6) | ||
| 386 | |||
| 377 | /* For imx6sl iomux gpr register field define */ | 387 | /* For imx6sl iomux gpr register field define */ |
| 378 | #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) | 388 | #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17) |
| 379 | #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) | 389 | #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14) |