ENGR00302472-1 ARM: imx6q: Add imx6dl LVDS mux ctrl bit definitions

This patch adds LVDS mux ctrl bit definitions for imx6dl.
The bits LVDS0/1_MUX_CTL are defined in the register IOMUXC_GPR3.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index bbbebdde44c4..260c55b589e9 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -374,6 +374,16 @@
 #define IMX6Q_GPR13_SATA_MPLL_CLK_EN            BIT(1)
 #define IMX6Q_GPR13_SATA_TX_EDGE_RATE           BIT(0)
 
+/* For imx6dl iomux gpr register field definitions */
+#define IMX6DL_GPR3_LVDS1_MUX_CTL_MASK          (0x3 << 8)
+#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI0      (0x0 << 8)
+#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI1      (0x1 << 8)
+#define IMX6DL_GPR3_LVDS1_MUX_CTL_LCDIF         (0x2 << 8)
+#define IMX6DL_GPR3_LVDS0_MUX_CTL_MASK          (0x3 << 6)
+#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI0      (0x0 << 6)
+#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI1      (0x1 << 6)
+#define IMX6DL_GPR3_LVDS0_MUX_CTL_LCDIF         (0x2 << 6)
+
 /* For imx6sl iomux gpr register field define */
 #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK    (0x3 << 17)
 #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK    (0x1 << 14)