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authorLuis R. Rodriguez <lrodriguez@atheros.com>2010-04-15 17:39:28 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-04-16 15:43:45 -0400
commitb622a720b45def8dce816244a83b82992da4fe20 (patch)
tree0d9c2d852219a1b53e6387848a24dca97552f58e /drivers/net
parent744d402580f959072f6b805a98745837f185c8e0 (diff)
ath9k_hw: move AR9002 mac ops to its own file
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/wireless/ath/ath9k/Makefile1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_mac.c480
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mac.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c461
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.h2
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c1
10 files changed, 486 insertions, 464 deletions
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index b0702fc84651..dd112be218ab 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -30,6 +30,7 @@ ath9k_hw-y:= \
30 ani.o \ 30 ani.o \
31 btcoex.o \ 31 btcoex.o \
32 mac.o \ 32 mac.o \
33 ar9002_mac.o \
33 ar9003_mac.o \ 34 ar9003_mac.o \
34 ar9003_eeprom.o 35 ar9003_eeprom.o
35 36
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
new file mode 100644
index 000000000000..2be20d2070c4
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -0,0 +1,480 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18
19#define AR_BufLen 0x00000fff
20
21static void ar9002_hw_rx_enable(struct ath_hw *ah)
22{
23 REG_WRITE(ah, AR_CR, AR_CR_RXE);
24}
25
26static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
27{
28 ((struct ath_desc*) ds)->ds_link = ds_link;
29}
30
31static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
32{
33 *ds_link = &((struct ath_desc *)ds)->ds_link;
34}
35
36static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
37{
38 u32 isr = 0;
39 u32 mask2 = 0;
40 struct ath9k_hw_capabilities *pCap = &ah->caps;
41 u32 sync_cause = 0;
42 bool fatal_int = false;
43 struct ath_common *common = ath9k_hw_common(ah);
44
45 if (!AR_SREV_9100(ah)) {
46 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
47 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
48 == AR_RTC_STATUS_ON) {
49 isr = REG_READ(ah, AR_ISR);
50 }
51 }
52
53 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
54 AR_INTR_SYNC_DEFAULT;
55
56 *masked = 0;
57
58 if (!isr && !sync_cause)
59 return false;
60 } else {
61 *masked = 0;
62 isr = REG_READ(ah, AR_ISR);
63 }
64
65 if (isr) {
66 if (isr & AR_ISR_BCNMISC) {
67 u32 isr2;
68 isr2 = REG_READ(ah, AR_ISR_S2);
69 if (isr2 & AR_ISR_S2_TIM)
70 mask2 |= ATH9K_INT_TIM;
71 if (isr2 & AR_ISR_S2_DTIM)
72 mask2 |= ATH9K_INT_DTIM;
73 if (isr2 & AR_ISR_S2_DTIMSYNC)
74 mask2 |= ATH9K_INT_DTIMSYNC;
75 if (isr2 & (AR_ISR_S2_CABEND))
76 mask2 |= ATH9K_INT_CABEND;
77 if (isr2 & AR_ISR_S2_GTT)
78 mask2 |= ATH9K_INT_GTT;
79 if (isr2 & AR_ISR_S2_CST)
80 mask2 |= ATH9K_INT_CST;
81 if (isr2 & AR_ISR_S2_TSFOOR)
82 mask2 |= ATH9K_INT_TSFOOR;
83 }
84
85 isr = REG_READ(ah, AR_ISR_RAC);
86 if (isr == 0xffffffff) {
87 *masked = 0;
88 return false;
89 }
90
91 *masked = isr & ATH9K_INT_COMMON;
92
93 if (ah->config.rx_intr_mitigation) {
94 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
95 *masked |= ATH9K_INT_RX;
96 }
97
98 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
99 *masked |= ATH9K_INT_RX;
100 if (isr &
101 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
102 AR_ISR_TXEOL)) {
103 u32 s0_s, s1_s;
104
105 *masked |= ATH9K_INT_TX;
106
107 s0_s = REG_READ(ah, AR_ISR_S0_S);
108 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
109 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
110
111 s1_s = REG_READ(ah, AR_ISR_S1_S);
112 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
113 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
114 }
115
116 if (isr & AR_ISR_RXORN) {
117 ath_print(common, ATH_DBG_INTERRUPT,
118 "receive FIFO overrun interrupt\n");
119 }
120
121 if (!AR_SREV_9100(ah)) {
122 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
123 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
124 if (isr5 & AR_ISR_S5_TIM_TIMER)
125 *masked |= ATH9K_INT_TIM_TIMER;
126 }
127 }
128
129 *masked |= mask2;
130 }
131
132 if (AR_SREV_9100(ah))
133 return true;
134
135 if (isr & AR_ISR_GENTMR) {
136 u32 s5_s;
137
138 s5_s = REG_READ(ah, AR_ISR_S5_S);
139 if (isr & AR_ISR_GENTMR) {
140 ah->intr_gen_timer_trigger =
141 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
142
143 ah->intr_gen_timer_thresh =
144 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
145
146 if (ah->intr_gen_timer_trigger)
147 *masked |= ATH9K_INT_GENTIMER;
148
149 }
150 }
151
152 if (sync_cause) {
153 fatal_int =
154 (sync_cause &
155 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
156 ? true : false;
157
158 if (fatal_int) {
159 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
160 ath_print(common, ATH_DBG_ANY,
161 "received PCI FATAL interrupt\n");
162 }
163 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
164 ath_print(common, ATH_DBG_ANY,
165 "received PCI PERR interrupt\n");
166 }
167 *masked |= ATH9K_INT_FATAL;
168 }
169 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
170 ath_print(common, ATH_DBG_INTERRUPT,
171 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
172 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
173 REG_WRITE(ah, AR_RC, 0);
174 *masked |= ATH9K_INT_FATAL;
175 }
176 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
177 ath_print(common, ATH_DBG_INTERRUPT,
178 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
179 }
180
181 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
182 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
183 }
184
185 return true;
186}
187
188static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
189 bool is_firstseg, bool is_lastseg,
190 const void *ds0, dma_addr_t buf_addr,
191 unsigned int qcu)
192{
193 struct ar5416_desc *ads = AR5416DESC(ds);
194
195 ads->ds_data = buf_addr;
196
197 if (is_firstseg) {
198 ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
199 } else if (is_lastseg) {
200 ads->ds_ctl0 = 0;
201 ads->ds_ctl1 = seglen;
202 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
203 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
204 } else {
205 ads->ds_ctl0 = 0;
206 ads->ds_ctl1 = seglen | AR_TxMore;
207 ads->ds_ctl2 = 0;
208 ads->ds_ctl3 = 0;
209 }
210 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
211 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
212 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
213 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
214 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
215}
216
217static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
218 struct ath_tx_status *ts)
219{
220 struct ar5416_desc *ads = AR5416DESC(ds);
221
222 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
223 return -EINPROGRESS;
224
225 ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
226 ts->ts_tstamp = ads->AR_SendTimestamp;
227 ts->ts_status = 0;
228 ts->ts_flags = 0;
229
230 if (ads->ds_txstatus1 & AR_FrmXmitOK)
231 ts->ts_status |= ATH9K_TX_ACKED;
232 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
233 ts->ts_status |= ATH9K_TXERR_XRETRY;
234 if (ads->ds_txstatus1 & AR_Filtered)
235 ts->ts_status |= ATH9K_TXERR_FILT;
236 if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
237 ts->ts_status |= ATH9K_TXERR_FIFO;
238 ath9k_hw_updatetxtriglevel(ah, true);
239 }
240 if (ads->ds_txstatus9 & AR_TxOpExceeded)
241 ts->ts_status |= ATH9K_TXERR_XTXOP;
242 if (ads->ds_txstatus1 & AR_TxTimerExpired)
243 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
244
245 if (ads->ds_txstatus1 & AR_DescCfgErr)
246 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
247 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
248 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
249 ath9k_hw_updatetxtriglevel(ah, true);
250 }
251 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
252 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
253 ath9k_hw_updatetxtriglevel(ah, true);
254 }
255 if (ads->ds_txstatus0 & AR_TxBaStatus) {
256 ts->ts_flags |= ATH9K_TX_BA;
257 ts->ba_low = ads->AR_BaBitmapLow;
258 ts->ba_high = ads->AR_BaBitmapHigh;
259 }
260
261 ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
262 switch (ts->ts_rateindex) {
263 case 0:
264 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
265 break;
266 case 1:
267 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
268 break;
269 case 2:
270 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
271 break;
272 case 3:
273 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
274 break;
275 }
276
277 ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
278 ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
279 ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
280 ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
281 ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
282 ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
283 ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
284 ts->evm0 = ads->AR_TxEVM0;
285 ts->evm1 = ads->AR_TxEVM1;
286 ts->evm2 = ads->AR_TxEVM2;
287 ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
288 ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
289 ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
290 ts->ts_antenna = 0;
291
292 return 0;
293}
294
295static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
296 u32 pktLen, enum ath9k_pkt_type type,
297 u32 txPower, u32 keyIx,
298 enum ath9k_key_type keyType, u32 flags)
299{
300 struct ar5416_desc *ads = AR5416DESC(ds);
301
302 txPower += ah->txpower_indexoffset;
303 if (txPower > 63)
304 txPower = 63;
305
306 ads->ds_ctl0 = (pktLen & AR_FrameLen)
307 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
308 | SM(txPower, AR_XmitPower)
309 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
310 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
311 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
312 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
313
314 ads->ds_ctl1 =
315 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
316 | SM(type, AR_FrameType)
317 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
318 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
319 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
320
321 ads->ds_ctl6 = SM(keyType, AR_EncrType);
322
323 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
324 ads->ds_ctl8 = 0;
325 ads->ds_ctl9 = 0;
326 ads->ds_ctl10 = 0;
327 ads->ds_ctl11 = 0;
328 }
329}
330
331static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
332 void *lastds,
333 u32 durUpdateEn, u32 rtsctsRate,
334 u32 rtsctsDuration,
335 struct ath9k_11n_rate_series series[],
336 u32 nseries, u32 flags)
337{
338 struct ar5416_desc *ads = AR5416DESC(ds);
339 struct ar5416_desc *last_ads = AR5416DESC(lastds);
340 u32 ds_ctl0;
341
342 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
343 ds_ctl0 = ads->ds_ctl0;
344
345 if (flags & ATH9K_TXDESC_RTSENA) {
346 ds_ctl0 &= ~AR_CTSEnable;
347 ds_ctl0 |= AR_RTSEnable;
348 } else {
349 ds_ctl0 &= ~AR_RTSEnable;
350 ds_ctl0 |= AR_CTSEnable;
351 }
352
353 ads->ds_ctl0 = ds_ctl0;
354 } else {
355 ads->ds_ctl0 =
356 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
357 }
358
359 ads->ds_ctl2 = set11nTries(series, 0)
360 | set11nTries(series, 1)
361 | set11nTries(series, 2)
362 | set11nTries(series, 3)
363 | (durUpdateEn ? AR_DurUpdateEna : 0)
364 | SM(0, AR_BurstDur);
365
366 ads->ds_ctl3 = set11nRate(series, 0)
367 | set11nRate(series, 1)
368 | set11nRate(series, 2)
369 | set11nRate(series, 3);
370
371 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
372 | set11nPktDurRTSCTS(series, 1);
373
374 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
375 | set11nPktDurRTSCTS(series, 3);
376
377 ads->ds_ctl7 = set11nRateFlags(series, 0)
378 | set11nRateFlags(series, 1)
379 | set11nRateFlags(series, 2)
380 | set11nRateFlags(series, 3)
381 | SM(rtsctsRate, AR_RTSCTSRate);
382 last_ads->ds_ctl2 = ads->ds_ctl2;
383 last_ads->ds_ctl3 = ads->ds_ctl3;
384}
385
386static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
387 u32 aggrLen)
388{
389 struct ar5416_desc *ads = AR5416DESC(ds);
390
391 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
392 ads->ds_ctl6 &= ~AR_AggrLen;
393 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
394}
395
396static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
397 u32 numDelims)
398{
399 struct ar5416_desc *ads = AR5416DESC(ds);
400 unsigned int ctl6;
401
402 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
403
404 ctl6 = ads->ds_ctl6;
405 ctl6 &= ~AR_PadDelim;
406 ctl6 |= SM(numDelims, AR_PadDelim);
407 ads->ds_ctl6 = ctl6;
408}
409
410static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
411{
412 struct ar5416_desc *ads = AR5416DESC(ds);
413
414 ads->ds_ctl1 |= AR_IsAggr;
415 ads->ds_ctl1 &= ~AR_MoreAggr;
416 ads->ds_ctl6 &= ~AR_PadDelim;
417}
418
419static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
420{
421 struct ar5416_desc *ads = AR5416DESC(ds);
422
423 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
424}
425
426static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
427 u32 burstDuration)
428{
429 struct ar5416_desc *ads = AR5416DESC(ds);
430
431 ads->ds_ctl2 &= ~AR_BurstDur;
432 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
433}
434
435static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
436 u32 vmf)
437{
438 struct ar5416_desc *ads = AR5416DESC(ds);
439
440 if (vmf)
441 ads->ds_ctl0 |= AR_VirtMoreFrag;
442 else
443 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
444}
445
446void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
447 u32 size, u32 flags)
448{
449 struct ar5416_desc *ads = AR5416DESC(ds);
450 struct ath9k_hw_capabilities *pCap = &ah->caps;
451
452 ads->ds_ctl1 = size & AR_BufLen;
453 if (flags & ATH9K_RXDESC_INTREQ)
454 ads->ds_ctl1 |= AR_RxIntrReq;
455
456 ads->ds_rxstatus8 &= ~AR_RxDone;
457 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
458 memset(&(ads->u), 0, sizeof(ads->u));
459}
460EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
461
462void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
463{
464 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
465
466 ops->rx_enable = ar9002_hw_rx_enable;
467 ops->set_desc_link = ar9002_hw_set_desc_link;
468 ops->get_desc_link = ar9002_hw_get_desc_link;
469 ops->get_isr = ar9002_hw_get_isr;
470 ops->fill_txdesc = ar9002_hw_fill_txdesc;
471 ops->proc_txdesc = ar9002_hw_proc_txdesc;
472 ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
473 ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
474 ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
475 ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
476 ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
477 ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
478 ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
479 ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
480}
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index f32665d9ec0a..b15309caf1da 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "ar9003_mac.h"
18#include "ar9003_initvals.h" 19#include "ar9003_initvals.h"
19 20
20/* General hardware code for the AR9003 hadware family */ 21/* General hardware code for the AR9003 hadware family */
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index 81ad09a7ddff..cb93d2375e8d 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -14,6 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16#include "hw.h" 16#include "hw.h"
17#include "ar9003_mac.h"
17 18
18static void ar9003_hw_rx_enable(struct ath_hw *hw) 19static void ar9003_hw_rx_enable(struct ath_hw *hw)
19{ 20{
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 19e2c3cd1473..1a7cf20d31ea 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -20,6 +20,7 @@
20#include "hw.h" 20#include "hw.h"
21#include "hw-ops.h" 21#include "hw-ops.h"
22#include "rc.h" 22#include "rc.h"
23#include "ar9003_mac.h"
23 24
24#define ATH9K_CLOCK_RATE_CCK 22 25#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 26#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 6dbbab95df59..b711ec212abd 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -28,7 +28,6 @@
28#include "reg.h" 28#include "reg.h"
29#include "phy.h" 29#include "phy.h"
30#include "btcoex.h" 30#include "btcoex.h"
31#include "ar9003_mac.h"
32 31
33#include "../regd.h" 32#include "../regd.h"
34#include "../debug.h" 33#include "../debug.h"
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 22fa5125abff..05159584a544 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -16,451 +16,6 @@
16 16
17#include "hw.h" 17#include "hw.h"
18 18
19static void ar9002_hw_rx_enable(struct ath_hw *ah)
20{
21 REG_WRITE(ah, AR_CR, AR_CR_RXE);
22}
23
24static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
25{
26 ((struct ath_desc *) ds)->ds_link = ds_link;
27}
28
29static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
30{
31 *ds_link = &((struct ath_desc *)ds)->ds_link;
32}
33
34static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
35{
36 u32 isr = 0;
37 u32 mask2 = 0;
38 struct ath9k_hw_capabilities *pCap = &ah->caps;
39 u32 sync_cause = 0;
40 bool fatal_int = false;
41 struct ath_common *common = ath9k_hw_common(ah);
42
43 if (!AR_SREV_9100(ah)) {
44 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
45 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
46 == AR_RTC_STATUS_ON) {
47 isr = REG_READ(ah, AR_ISR);
48 }
49 }
50
51 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
52 AR_INTR_SYNC_DEFAULT;
53
54 *masked = 0;
55
56 if (!isr && !sync_cause)
57 return false;
58 } else {
59 *masked = 0;
60 isr = REG_READ(ah, AR_ISR);
61 }
62
63 if (isr) {
64 if (isr & AR_ISR_BCNMISC) {
65 u32 isr2;
66 isr2 = REG_READ(ah, AR_ISR_S2);
67 if (isr2 & AR_ISR_S2_TIM)
68 mask2 |= ATH9K_INT_TIM;
69 if (isr2 & AR_ISR_S2_DTIM)
70 mask2 |= ATH9K_INT_DTIM;
71 if (isr2 & AR_ISR_S2_DTIMSYNC)
72 mask2 |= ATH9K_INT_DTIMSYNC;
73 if (isr2 & (AR_ISR_S2_CABEND))
74 mask2 |= ATH9K_INT_CABEND;
75 if (isr2 & AR_ISR_S2_GTT)
76 mask2 |= ATH9K_INT_GTT;
77 if (isr2 & AR_ISR_S2_CST)
78 mask2 |= ATH9K_INT_CST;
79 if (isr2 & AR_ISR_S2_TSFOOR)
80 mask2 |= ATH9K_INT_TSFOOR;
81 }
82
83 isr = REG_READ(ah, AR_ISR_RAC);
84 if (isr == 0xffffffff) {
85 *masked = 0;
86 return false;
87 }
88
89 *masked = isr & ATH9K_INT_COMMON;
90
91 if (ah->config.rx_intr_mitigation) {
92 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
93 *masked |= ATH9K_INT_RX;
94 }
95
96 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
97 *masked |= ATH9K_INT_RX;
98 if (isr &
99 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
100 AR_ISR_TXEOL)) {
101 u32 s0_s, s1_s;
102
103 *masked |= ATH9K_INT_TX;
104
105 s0_s = REG_READ(ah, AR_ISR_S0_S);
106 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
107 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
108
109 s1_s = REG_READ(ah, AR_ISR_S1_S);
110 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
111 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
112 }
113
114 if (isr & AR_ISR_RXORN) {
115 ath_print(common, ATH_DBG_INTERRUPT,
116 "receive FIFO overrun interrupt\n");
117 }
118
119 if (!AR_SREV_9100(ah)) {
120 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
121 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
122 if (isr5 & AR_ISR_S5_TIM_TIMER)
123 *masked |= ATH9K_INT_TIM_TIMER;
124 }
125 }
126
127 *masked |= mask2;
128 }
129
130 if (AR_SREV_9100(ah))
131 return true;
132
133 if (isr & AR_ISR_GENTMR) {
134 u32 s5_s;
135
136 s5_s = REG_READ(ah, AR_ISR_S5_S);
137 if (isr & AR_ISR_GENTMR) {
138 ah->intr_gen_timer_trigger =
139 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
140
141 ah->intr_gen_timer_thresh =
142 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
143
144 if (ah->intr_gen_timer_trigger)
145 *masked |= ATH9K_INT_GENTIMER;
146
147 }
148 }
149
150 if (sync_cause) {
151 fatal_int =
152 (sync_cause &
153 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
154 ? true : false;
155
156 if (fatal_int) {
157 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
158 ath_print(common, ATH_DBG_ANY,
159 "received PCI FATAL interrupt\n");
160 }
161 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
162 ath_print(common, ATH_DBG_ANY,
163 "received PCI PERR interrupt\n");
164 }
165 *masked |= ATH9K_INT_FATAL;
166 }
167 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
168 ath_print(common, ATH_DBG_INTERRUPT,
169 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
170 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
171 REG_WRITE(ah, AR_RC, 0);
172 *masked |= ATH9K_INT_FATAL;
173 }
174 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
175 ath_print(common, ATH_DBG_INTERRUPT,
176 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
177 }
178
179 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
180 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
181 }
182
183 return true;
184}
185
186static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
187 bool is_firstseg, bool is_lastseg,
188 const void *ds0, dma_addr_t buf_addr,
189 unsigned int qcu)
190{
191 struct ar5416_desc *ads = AR5416DESC(ds);
192
193 ads->ds_data = buf_addr;
194
195 if (is_firstseg) {
196 ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
197 } else if (is_lastseg) {
198 ads->ds_ctl0 = 0;
199 ads->ds_ctl1 = seglen;
200 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
201 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
202 } else {
203 ads->ds_ctl0 = 0;
204 ads->ds_ctl1 = seglen | AR_TxMore;
205 ads->ds_ctl2 = 0;
206 ads->ds_ctl3 = 0;
207 }
208 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
209 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
210 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
211 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
212 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
213}
214
215static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
216 struct ath_tx_status *ts)
217{
218 struct ar5416_desc *ads = AR5416DESC(ds);
219
220 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
221 return -EINPROGRESS;
222
223 ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
224 ts->ts_tstamp = ads->AR_SendTimestamp;
225 ts->ts_status = 0;
226 ts->ts_flags = 0;
227
228 if (ads->ds_txstatus1 & AR_FrmXmitOK)
229 ts->ts_status |= ATH9K_TX_ACKED;
230 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
231 ts->ts_status |= ATH9K_TXERR_XRETRY;
232 if (ads->ds_txstatus1 & AR_Filtered)
233 ts->ts_status |= ATH9K_TXERR_FILT;
234 if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
235 ts->ts_status |= ATH9K_TXERR_FIFO;
236 ath9k_hw_updatetxtriglevel(ah, true);
237 }
238 if (ads->ds_txstatus9 & AR_TxOpExceeded)
239 ts->ts_status |= ATH9K_TXERR_XTXOP;
240 if (ads->ds_txstatus1 & AR_TxTimerExpired)
241 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
242
243 if (ads->ds_txstatus1 & AR_DescCfgErr)
244 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
245 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
246 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
247 ath9k_hw_updatetxtriglevel(ah, true);
248 }
249 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
250 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
251 ath9k_hw_updatetxtriglevel(ah, true);
252 }
253 if (ads->ds_txstatus0 & AR_TxBaStatus) {
254 ts->ts_flags |= ATH9K_TX_BA;
255 ts->ba_low = ads->AR_BaBitmapLow;
256 ts->ba_high = ads->AR_BaBitmapHigh;
257 }
258
259 ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
260 switch (ts->ts_rateindex) {
261 case 0:
262 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
263 break;
264 case 1:
265 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
266 break;
267 case 2:
268 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
269 break;
270 case 3:
271 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
272 break;
273 }
274
275 ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
276 ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
277 ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
278 ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
279 ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
280 ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
281 ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
282 ts->evm0 = ads->AR_TxEVM0;
283 ts->evm1 = ads->AR_TxEVM1;
284 ts->evm2 = ads->AR_TxEVM2;
285 ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
286 ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
287 ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
288 ts->ts_antenna = 0;
289
290 return 0;
291}
292
293static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
294 u32 pktLen, enum ath9k_pkt_type type,
295 u32 txPower, u32 keyIx,
296 enum ath9k_key_type keyType, u32 flags)
297{
298 struct ar5416_desc *ads = AR5416DESC(ds);
299
300 txPower += ah->txpower_indexoffset;
301 if (txPower > 63)
302 txPower = 63;
303
304 ads->ds_ctl0 = (pktLen & AR_FrameLen)
305 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
306 | SM(txPower, AR_XmitPower)
307 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
308 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
309 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
310 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
311
312 ads->ds_ctl1 =
313 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
314 | SM(type, AR_FrameType)
315 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
316 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
317 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
318
319 ads->ds_ctl6 = SM(keyType, AR_EncrType);
320
321 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
322 ads->ds_ctl8 = 0;
323 ads->ds_ctl9 = 0;
324 ads->ds_ctl10 = 0;
325 ads->ds_ctl11 = 0;
326 }
327}
328
329static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
330 void *lastds,
331 u32 durUpdateEn, u32 rtsctsRate,
332 u32 rtsctsDuration,
333 struct ath9k_11n_rate_series series[],
334 u32 nseries, u32 flags)
335{
336 struct ar5416_desc *ads = AR5416DESC(ds);
337 struct ar5416_desc *last_ads = AR5416DESC(lastds);
338 u32 ds_ctl0;
339
340 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
341 ds_ctl0 = ads->ds_ctl0;
342
343 if (flags & ATH9K_TXDESC_RTSENA) {
344 ds_ctl0 &= ~AR_CTSEnable;
345 ds_ctl0 |= AR_RTSEnable;
346 } else {
347 ds_ctl0 &= ~AR_RTSEnable;
348 ds_ctl0 |= AR_CTSEnable;
349 }
350
351 ads->ds_ctl0 = ds_ctl0;
352 } else {
353 ads->ds_ctl0 =
354 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
355 }
356
357 ads->ds_ctl2 = set11nTries(series, 0)
358 | set11nTries(series, 1)
359 | set11nTries(series, 2)
360 | set11nTries(series, 3)
361 | (durUpdateEn ? AR_DurUpdateEna : 0)
362 | SM(0, AR_BurstDur);
363
364 ads->ds_ctl3 = set11nRate(series, 0)
365 | set11nRate(series, 1)
366 | set11nRate(series, 2)
367 | set11nRate(series, 3);
368
369 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
370 | set11nPktDurRTSCTS(series, 1);
371
372 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
373 | set11nPktDurRTSCTS(series, 3);
374
375 ads->ds_ctl7 = set11nRateFlags(series, 0)
376 | set11nRateFlags(series, 1)
377 | set11nRateFlags(series, 2)
378 | set11nRateFlags(series, 3)
379 | SM(rtsctsRate, AR_RTSCTSRate);
380 last_ads->ds_ctl2 = ads->ds_ctl2;
381 last_ads->ds_ctl3 = ads->ds_ctl3;
382}
383
384static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
385 u32 aggrLen)
386{
387 struct ar5416_desc *ads = AR5416DESC(ds);
388
389 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
390 ads->ds_ctl6 &= ~AR_AggrLen;
391 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
392}
393
394static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
395 u32 numDelims)
396{
397 struct ar5416_desc *ads = AR5416DESC(ds);
398 unsigned int ctl6;
399
400 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
401
402 ctl6 = ads->ds_ctl6;
403 ctl6 &= ~AR_PadDelim;
404 ctl6 |= SM(numDelims, AR_PadDelim);
405 ads->ds_ctl6 = ctl6;
406}
407
408static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
409{
410 struct ar5416_desc *ads = AR5416DESC(ds);
411
412 ads->ds_ctl1 |= AR_IsAggr;
413 ads->ds_ctl1 &= ~AR_MoreAggr;
414 ads->ds_ctl6 &= ~AR_PadDelim;
415}
416
417static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
418{
419 struct ar5416_desc *ads = AR5416DESC(ds);
420
421 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
422}
423
424static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
425 u32 burstDuration)
426{
427 struct ar5416_desc *ads = AR5416DESC(ds);
428
429 ads->ds_ctl2 &= ~AR_BurstDur;
430 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
431}
432
433static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
434 u32 vmf)
435{
436 struct ar5416_desc *ads = AR5416DESC(ds);
437
438 if (vmf)
439 ads->ds_ctl0 |= AR_VirtMoreFrag;
440 else
441 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
442}
443
444void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
445{
446 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
447
448 ops->rx_enable = ar9002_hw_rx_enable;
449 ops->set_desc_link = ar9002_hw_set_desc_link;
450 ops->get_desc_link = ar9002_hw_get_desc_link;
451 ops->get_isr = ar9002_hw_get_isr;
452 ops->fill_txdesc = ar9002_hw_fill_txdesc;
453 ops->proc_txdesc = ar9002_hw_proc_txdesc;
454 ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
455 ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
456 ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
457 ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
458 ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
459 ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
460 ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
461 ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
462}
463
464static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, 19static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
465 struct ath9k_tx_queue_info *qi) 20 struct ath9k_tx_queue_info *qi)
466{ 21{
@@ -1122,22 +677,6 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
1122} 677}
1123EXPORT_SYMBOL(ath9k_hw_rxprocdesc); 678EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
1124 679
1125void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
1126 u32 size, u32 flags)
1127{
1128 struct ar5416_desc *ads = AR5416DESC(ds);
1129 struct ath9k_hw_capabilities *pCap = &ah->caps;
1130
1131 ads->ds_ctl1 = size & AR_BufLen;
1132 if (flags & ATH9K_RXDESC_INTREQ)
1133 ads->ds_ctl1 |= AR_RxIntrReq;
1134
1135 ads->ds_rxstatus8 &= ~AR_RxDone;
1136 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1137 memset(&(ads->u), 0, sizeof(ads->u));
1138}
1139EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
1140
1141/* 680/*
1142 * This can stop or re-enables RX. 681 * This can stop or re-enables RX.
1143 * 682 *
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index 0d492192de94..eb430c471c5c 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -354,7 +354,6 @@ struct ar5416_desc {
354#define AR_DestIdxValid 0x40000000 354#define AR_DestIdxValid 0x40000000
355#define AR_CTSEnable 0x80000000 355#define AR_CTSEnable 0x80000000
356 356
357#define AR_BufLen 0x00000fff
358#define AR_TxMore 0x00001000 357#define AR_TxMore 0x00001000
359#define AR_DestIdx 0x000fe000 358#define AR_DestIdx 0x000fe000
360#define AR_DestIdx_S 13 359#define AR_DestIdx_S 13
@@ -494,7 +493,6 @@ struct ar5416_desc {
494 493
495#define AR_RxCTLRsvd00 0xffffffff 494#define AR_RxCTLRsvd00 0xffffffff
496 495
497#define AR_BufLen 0x00000fff
498#define AR_RxCtlRsvd00 0x00001000 496#define AR_RxCtlRsvd00 0x00001000
499#define AR_RxIntrReq 0x00002000 497#define AR_RxIntrReq 0x00002000
500#define AR_RxCtlRsvd01 0xffffc000 498#define AR_RxCtlRsvd01 0xffffc000
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index ffb599c49185..cb4995ccbc14 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18#include "ar9003_mac.h"
18 19
19#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) 20#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
20 21
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 550253fe61fb..7dae199361bf 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18#include "ar9003_mac.h"
18 19
19#define BITS_PER_BYTE 8 20#define BITS_PER_BYTE 8
20#define OFDM_PLCP_BITS 22 21#define OFDM_PLCP_BITS 22
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 23:02:57 -0500