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-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c461
1 files changed, 0 insertions, 461 deletions
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 22fa5125abff..05159584a544 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -16,451 +16,6 @@
16 16
17#include "hw.h" 17#include "hw.h"
18 18
19static void ar9002_hw_rx_enable(struct ath_hw *ah)
20{
21 REG_WRITE(ah, AR_CR, AR_CR_RXE);
22}
23
24static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
25{
26 ((struct ath_desc *) ds)->ds_link = ds_link;
27}
28
29static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
30{
31 *ds_link = &((struct ath_desc *)ds)->ds_link;
32}
33
34static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
35{
36 u32 isr = 0;
37 u32 mask2 = 0;
38 struct ath9k_hw_capabilities *pCap = &ah->caps;
39 u32 sync_cause = 0;
40 bool fatal_int = false;
41 struct ath_common *common = ath9k_hw_common(ah);
42
43 if (!AR_SREV_9100(ah)) {
44 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
45 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
46 == AR_RTC_STATUS_ON) {
47 isr = REG_READ(ah, AR_ISR);
48 }
49 }
50
51 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
52 AR_INTR_SYNC_DEFAULT;
53
54 *masked = 0;
55
56 if (!isr && !sync_cause)
57 return false;
58 } else {
59 *masked = 0;
60 isr = REG_READ(ah, AR_ISR);
61 }
62
63 if (isr) {
64 if (isr & AR_ISR_BCNMISC) {
65 u32 isr2;
66 isr2 = REG_READ(ah, AR_ISR_S2);
67 if (isr2 & AR_ISR_S2_TIM)
68 mask2 |= ATH9K_INT_TIM;
69 if (isr2 & AR_ISR_S2_DTIM)
70 mask2 |= ATH9K_INT_DTIM;
71 if (isr2 & AR_ISR_S2_DTIMSYNC)
72 mask2 |= ATH9K_INT_DTIMSYNC;
73 if (isr2 & (AR_ISR_S2_CABEND))
74 mask2 |= ATH9K_INT_CABEND;
75 if (isr2 & AR_ISR_S2_GTT)
76 mask2 |= ATH9K_INT_GTT;
77 if (isr2 & AR_ISR_S2_CST)
78 mask2 |= ATH9K_INT_CST;
79 if (isr2 & AR_ISR_S2_TSFOOR)
80 mask2 |= ATH9K_INT_TSFOOR;
81 }
82
83 isr = REG_READ(ah, AR_ISR_RAC);
84 if (isr == 0xffffffff) {
85 *masked = 0;
86 return false;
87 }
88
89 *masked = isr & ATH9K_INT_COMMON;
90
91 if (ah->config.rx_intr_mitigation) {
92 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
93 *masked |= ATH9K_INT_RX;
94 }
95
96 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
97 *masked |= ATH9K_INT_RX;
98 if (isr &
99 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
100 AR_ISR_TXEOL)) {
101 u32 s0_s, s1_s;
102
103 *masked |= ATH9K_INT_TX;
104
105 s0_s = REG_READ(ah, AR_ISR_S0_S);
106 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
107 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
108
109 s1_s = REG_READ(ah, AR_ISR_S1_S);
110 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
111 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
112 }
113
114 if (isr & AR_ISR_RXORN) {
115 ath_print(common, ATH_DBG_INTERRUPT,
116 "receive FIFO overrun interrupt\n");
117 }
118
119 if (!AR_SREV_9100(ah)) {
120 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
121 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
122 if (isr5 & AR_ISR_S5_TIM_TIMER)
123 *masked |= ATH9K_INT_TIM_TIMER;
124 }
125 }
126
127 *masked |= mask2;
128 }
129
130 if (AR_SREV_9100(ah))
131 return true;
132
133 if (isr & AR_ISR_GENTMR) {
134 u32 s5_s;
135
136 s5_s = REG_READ(ah, AR_ISR_S5_S);
137 if (isr & AR_ISR_GENTMR) {
138 ah->intr_gen_timer_trigger =
139 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
140
141 ah->intr_gen_timer_thresh =
142 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
143
144 if (ah->intr_gen_timer_trigger)
145 *masked |= ATH9K_INT_GENTIMER;
146
147 }
148 }
149
150 if (sync_cause) {
151 fatal_int =
152 (sync_cause &
153 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
154 ? true : false;
155
156 if (fatal_int) {
157 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
158 ath_print(common, ATH_DBG_ANY,
159 "received PCI FATAL interrupt\n");
160 }
161 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
162 ath_print(common, ATH_DBG_ANY,
163 "received PCI PERR interrupt\n");
164 }
165 *masked |= ATH9K_INT_FATAL;
166 }
167 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
168 ath_print(common, ATH_DBG_INTERRUPT,
169 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
170 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
171 REG_WRITE(ah, AR_RC, 0);
172 *masked |= ATH9K_INT_FATAL;
173 }
174 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
175 ath_print(common, ATH_DBG_INTERRUPT,
176 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
177 }
178
179 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
180 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
181 }
182
183 return true;
184}
185
186static void ar9002_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
187 bool is_firstseg, bool is_lastseg,
188 const void *ds0, dma_addr_t buf_addr,
189 unsigned int qcu)
190{
191 struct ar5416_desc *ads = AR5416DESC(ds);
192
193 ads->ds_data = buf_addr;
194
195 if (is_firstseg) {
196 ads->ds_ctl1 |= seglen | (is_lastseg ? 0 : AR_TxMore);
197 } else if (is_lastseg) {
198 ads->ds_ctl0 = 0;
199 ads->ds_ctl1 = seglen;
200 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
201 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
202 } else {
203 ads->ds_ctl0 = 0;
204 ads->ds_ctl1 = seglen | AR_TxMore;
205 ads->ds_ctl2 = 0;
206 ads->ds_ctl3 = 0;
207 }
208 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
209 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
210 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
211 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
212 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
213}
214
215static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
216 struct ath_tx_status *ts)
217{
218 struct ar5416_desc *ads = AR5416DESC(ds);
219
220 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
221 return -EINPROGRESS;
222
223 ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
224 ts->ts_tstamp = ads->AR_SendTimestamp;
225 ts->ts_status = 0;
226 ts->ts_flags = 0;
227
228 if (ads->ds_txstatus1 & AR_FrmXmitOK)
229 ts->ts_status |= ATH9K_TX_ACKED;
230 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
231 ts->ts_status |= ATH9K_TXERR_XRETRY;
232 if (ads->ds_txstatus1 & AR_Filtered)
233 ts->ts_status |= ATH9K_TXERR_FILT;
234 if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
235 ts->ts_status |= ATH9K_TXERR_FIFO;
236 ath9k_hw_updatetxtriglevel(ah, true);
237 }
238 if (ads->ds_txstatus9 & AR_TxOpExceeded)
239 ts->ts_status |= ATH9K_TXERR_XTXOP;
240 if (ads->ds_txstatus1 & AR_TxTimerExpired)
241 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
242
243 if (ads->ds_txstatus1 & AR_DescCfgErr)
244 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
245 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
246 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
247 ath9k_hw_updatetxtriglevel(ah, true);
248 }
249 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
250 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
251 ath9k_hw_updatetxtriglevel(ah, true);
252 }
253 if (ads->ds_txstatus0 & AR_TxBaStatus) {
254 ts->ts_flags |= ATH9K_TX_BA;
255 ts->ba_low = ads->AR_BaBitmapLow;
256 ts->ba_high = ads->AR_BaBitmapHigh;
257 }
258
259 ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
260 switch (ts->ts_rateindex) {
261 case 0:
262 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
263 break;
264 case 1:
265 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
266 break;
267 case 2:
268 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
269 break;
270 case 3:
271 ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
272 break;
273 }
274
275 ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
276 ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
277 ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
278 ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
279 ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
280 ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
281 ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
282 ts->evm0 = ads->AR_TxEVM0;
283 ts->evm1 = ads->AR_TxEVM1;
284 ts->evm2 = ads->AR_TxEVM2;
285 ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
286 ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
287 ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
288 ts->ts_antenna = 0;
289
290 return 0;
291}
292
293static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
294 u32 pktLen, enum ath9k_pkt_type type,
295 u32 txPower, u32 keyIx,
296 enum ath9k_key_type keyType, u32 flags)
297{
298 struct ar5416_desc *ads = AR5416DESC(ds);
299
300 txPower += ah->txpower_indexoffset;
301 if (txPower > 63)
302 txPower = 63;
303
304 ads->ds_ctl0 = (pktLen & AR_FrameLen)
305 | (flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
306 | SM(txPower, AR_XmitPower)
307 | (flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
308 | (flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
309 | (flags & ATH9K_TXDESC_INTREQ ? AR_TxIntrReq : 0)
310 | (keyIx != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
311
312 ads->ds_ctl1 =
313 (keyIx != ATH9K_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
314 | SM(type, AR_FrameType)
315 | (flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
316 | (flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
317 | (flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
318
319 ads->ds_ctl6 = SM(keyType, AR_EncrType);
320
321 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
322 ads->ds_ctl8 = 0;
323 ads->ds_ctl9 = 0;
324 ads->ds_ctl10 = 0;
325 ads->ds_ctl11 = 0;
326 }
327}
328
329static void ar9002_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
330 void *lastds,
331 u32 durUpdateEn, u32 rtsctsRate,
332 u32 rtsctsDuration,
333 struct ath9k_11n_rate_series series[],
334 u32 nseries, u32 flags)
335{
336 struct ar5416_desc *ads = AR5416DESC(ds);
337 struct ar5416_desc *last_ads = AR5416DESC(lastds);
338 u32 ds_ctl0;
339
340 if (flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)) {
341 ds_ctl0 = ads->ds_ctl0;
342
343 if (flags & ATH9K_TXDESC_RTSENA) {
344 ds_ctl0 &= ~AR_CTSEnable;
345 ds_ctl0 |= AR_RTSEnable;
346 } else {
347 ds_ctl0 &= ~AR_RTSEnable;
348 ds_ctl0 |= AR_CTSEnable;
349 }
350
351 ads->ds_ctl0 = ds_ctl0;
352 } else {
353 ads->ds_ctl0 =
354 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
355 }
356
357 ads->ds_ctl2 = set11nTries(series, 0)
358 | set11nTries(series, 1)
359 | set11nTries(series, 2)
360 | set11nTries(series, 3)
361 | (durUpdateEn ? AR_DurUpdateEna : 0)
362 | SM(0, AR_BurstDur);
363
364 ads->ds_ctl3 = set11nRate(series, 0)
365 | set11nRate(series, 1)
366 | set11nRate(series, 2)
367 | set11nRate(series, 3);
368
369 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
370 | set11nPktDurRTSCTS(series, 1);
371
372 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
373 | set11nPktDurRTSCTS(series, 3);
374
375 ads->ds_ctl7 = set11nRateFlags(series, 0)
376 | set11nRateFlags(series, 1)
377 | set11nRateFlags(series, 2)
378 | set11nRateFlags(series, 3)
379 | SM(rtsctsRate, AR_RTSCTSRate);
380 last_ads->ds_ctl2 = ads->ds_ctl2;
381 last_ads->ds_ctl3 = ads->ds_ctl3;
382}
383
384static void ar9002_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
385 u32 aggrLen)
386{
387 struct ar5416_desc *ads = AR5416DESC(ds);
388
389 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
390 ads->ds_ctl6 &= ~AR_AggrLen;
391 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
392}
393
394static void ar9002_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
395 u32 numDelims)
396{
397 struct ar5416_desc *ads = AR5416DESC(ds);
398 unsigned int ctl6;
399
400 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
401
402 ctl6 = ads->ds_ctl6;
403 ctl6 &= ~AR_PadDelim;
404 ctl6 |= SM(numDelims, AR_PadDelim);
405 ads->ds_ctl6 = ctl6;
406}
407
408static void ar9002_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
409{
410 struct ar5416_desc *ads = AR5416DESC(ds);
411
412 ads->ds_ctl1 |= AR_IsAggr;
413 ads->ds_ctl1 &= ~AR_MoreAggr;
414 ads->ds_ctl6 &= ~AR_PadDelim;
415}
416
417static void ar9002_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
418{
419 struct ar5416_desc *ads = AR5416DESC(ds);
420
421 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
422}
423
424static void ar9002_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
425 u32 burstDuration)
426{
427 struct ar5416_desc *ads = AR5416DESC(ds);
428
429 ads->ds_ctl2 &= ~AR_BurstDur;
430 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
431}
432
433static void ar9002_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
434 u32 vmf)
435{
436 struct ar5416_desc *ads = AR5416DESC(ds);
437
438 if (vmf)
439 ads->ds_ctl0 |= AR_VirtMoreFrag;
440 else
441 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
442}
443
444void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
445{
446 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
447
448 ops->rx_enable = ar9002_hw_rx_enable;
449 ops->set_desc_link = ar9002_hw_set_desc_link;
450 ops->get_desc_link = ar9002_hw_get_desc_link;
451 ops->get_isr = ar9002_hw_get_isr;
452 ops->fill_txdesc = ar9002_hw_fill_txdesc;
453 ops->proc_txdesc = ar9002_hw_proc_txdesc;
454 ops->set11n_txdesc = ar9002_hw_set11n_txdesc;
455 ops->set11n_ratescenario = ar9002_hw_set11n_ratescenario;
456 ops->set11n_aggr_first = ar9002_hw_set11n_aggr_first;
457 ops->set11n_aggr_middle = ar9002_hw_set11n_aggr_middle;
458 ops->set11n_aggr_last = ar9002_hw_set11n_aggr_last;
459 ops->clr11n_aggr = ar9002_hw_clr11n_aggr;
460 ops->set11n_burstduration = ar9002_hw_set11n_burstduration;
461 ops->set11n_virtualmorefrag = ar9002_hw_set11n_virtualmorefrag;
462}
463
464static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, 19static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
465 struct ath9k_tx_queue_info *qi) 20 struct ath9k_tx_queue_info *qi)
466{ 21{
@@ -1122,22 +677,6 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
1122} 677}
1123EXPORT_SYMBOL(ath9k_hw_rxprocdesc); 678EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
1124 679
1125void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
1126 u32 size, u32 flags)
1127{
1128 struct ar5416_desc *ads = AR5416DESC(ds);
1129 struct ath9k_hw_capabilities *pCap = &ah->caps;
1130
1131 ads->ds_ctl1 = size & AR_BufLen;
1132 if (flags & ATH9K_RXDESC_INTREQ)
1133 ads->ds_ctl1 |= AR_RxIntrReq;
1134
1135 ads->ds_rxstatus8 &= ~AR_RxDone;
1136 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1137 memset(&(ads->u), 0, sizeof(ads->u));
1138}
1139EXPORT_SYMBOL(ath9k_hw_setuprxdesc);
1140
1141/* 680/*
1142 * This can stop or re-enables RX. 681 * This can stop or re-enables RX.
1143 * 682 *
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 01:47:35 -0500