bnx2x: 57712 parity handling

- Added support for a parity error handling for a 57712 chip.
 - Changed the parity recovery scheme from per-chip to per-engine.

Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@conan.davemloft.net>

1 files changed, 96 insertions, 62 deletions

diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h
index 9868cb0270a4..f8436e0c1316 100644
--- a/drivers/net/bnx2x/bnx2x_reg.h
+++ b/drivers/net/bnx2x/bnx2x_reg.h
@@ -804,10 +804,12 @@
 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
 #define DORQ_REG_SHRT_CMHEAD                                     0x170054
 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0                            (0x1<<4)
+#define HC_CONFIG_0_REG_BLOCK_DISABLE_0                          (0x1<<0)
 #define HC_CONFIG_0_REG_INT_LINE_EN_0                            (0x1<<3)
 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0                            (0x1<<7)
 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0                        (0x1<<2)
-#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0                          (0x1<<1)
+#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0                          (0x1<<1)
+#define HC_CONFIG_1_REG_BLOCK_DISABLE_1                          (0x1<<0)
 #define HC_REG_AGG_INT_0                                         0x108050
 #define HC_REG_AGG_INT_1                                         0x108054
 #define HC_REG_ATTN_BIT                                          0x108120
@@ -846,6 +848,7 @@
 #define HC_REG_VQID_0                                            0x108008
 #define HC_REG_VQID_1                                            0x10800c
 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN             (0x1<<1)
+#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE                 (0x1<<0)
 #define IGU_REG_ATTENTION_ACK_BITS                               0x130108
 /* [R 4] Debug: attn_fsm */
 #define IGU_REG_ATTN_FSM                                         0x130054
@@ -1876,11 +1879,21 @@
 /* [R 32] Interrupt register #0 read */
 #define NIG_REG_NIG_INT_STS_0                                    0x103b0
 #define NIG_REG_NIG_INT_STS_1                                    0x103c0
+/* [R 32] Legacy E1 and E1H location for parity error mask register. */
+#define NIG_REG_NIG_PRTY_MASK                                    0x103dc
+/* [RW 32] Parity mask register #0 read/write */
+#define NIG_REG_NIG_PRTY_MASK_0                                  0x183c8
+#define NIG_REG_NIG_PRTY_MASK_1                                  0x183d8
 /* [R 32] Legacy E1 and E1H location for parity error status register. */
 #define NIG_REG_NIG_PRTY_STS                                     0x103d0
 /* [R 32] Parity register #0 read */
 #define NIG_REG_NIG_PRTY_STS_0                                   0x183bc
 #define NIG_REG_NIG_PRTY_STS_1                                   0x183cc
+/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
+#define NIG_REG_NIG_PRTY_STS_CLR                                 0x103d4
+/* [RC 32] Parity register #0 read clear */
+#define NIG_REG_NIG_PRTY_STS_CLR_0                               0x183c0
+#define NIG_REG_NIG_PRTY_STS_CLR_1                               0x183d0
 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
  * Ethernet header. */
 #define NIG_REG_P0_HDRS_AFTER_BASIC                              0x18038
@@ -4322,6 +4335,8 @@
 #define UCM_REG_UCM_INT_MASK                                     0xe01d4
 /* [R 11] Interrupt register #0 read */
 #define UCM_REG_UCM_INT_STS                                      0xe01c8
+/* [RW 27] Parity mask register #0 read/write */
+#define UCM_REG_UCM_PRTY_MASK                                    0xe01e4
 /* [R 27] Parity register #0 read */
 #define UCM_REG_UCM_PRTY_STS                                     0xe01d8
 /* [RC 27] Parity register #0 read clear */
@@ -4843,8 +4858,13 @@
 #define XCM_REG_XCM_INT_MASK                                     0x202b4
 /* [R 14] Interrupt register #0 read */
 #define XCM_REG_XCM_INT_STS                                      0x202a8
+/* [RW 30] Parity mask register #0 read/write */
+#define XCM_REG_XCM_PRTY_MASK                                    0x202c4
 /* [R 30] Parity register #0 read */
 #define XCM_REG_XCM_PRTY_STS                                     0x202b8
+/* [RC 30] Parity register #0 read clear */
+#define XCM_REG_XCM_PRTY_STS_CLR                                 0x202bc
+
 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
    Is used to determine the number of the AG context REG-pairs written back;
@@ -5284,9 +5304,12 @@
 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE           (0x1<<15)
 #define MISC_REGISTERS_RESET_REG_2_RST_GRC                       (0x1<<4)
 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B     (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE      (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU       (0x1<<7)
 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO                      (0x1<<13)
 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE                 (0x1<<11)
+#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO                  (0x1<<13)
 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN                      (0x1<<9)
 #define MISC_REGISTERS_RESET_REG_2_SET                           0x594
 #define MISC_REGISTERS_RESET_REG_3_CLEAR                         0x5a8
@@ -5315,71 +5338,82 @@
 #define HW_LOCK_MAX_RESOURCE_VALUE                               31
 #define HW_LOCK_RESOURCE_GPIO                                    1
 #define HW_LOCK_RESOURCE_MDIO                                    0
-#define HW_LOCK_RESOURCE_PORT0_ATT_MASK                          3
-#define HW_LOCK_RESOURCE_RESERVED_08                             8
+#define HW_LOCK_RESOURCE_PORT0_ATT_MASK                          3
+#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0                       8
+#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1                       9
 #define HW_LOCK_RESOURCE_SPIO                                    2
 #define HW_LOCK_RESOURCE_UNDI                                    5
-#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT                 (0x1<<4)
-#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR                 (0x1<<5)
-#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR                 (1<<18)
-#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT                 (1<<31)
-#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT                 (1<<9)
-#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR                 (1<<8)
-#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT                 (1<<7)
-#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR                 (1<<6)
-#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT                (1<<29)
-#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR                (1<<28)
-#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT               (1<<1)
-#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR               (1<<0)
-#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR               (1<<18)
-#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT                (1<<11)
-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT           (1<<13)
-#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR           (1<<12)
-#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0                 (1<<2)
-#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0                 (1<<5)
-#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1                 (1<<9)
-#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR                 (1<<12)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY           (1<<28)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY         (1<<31)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY        (1<<29)
-#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY        (1<<30)
-#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT                (1<<15)
-#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR                (1<<14)
-#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR              (1<<20)
-#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR            (1<<0)
-#define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT                 (1<<31)
-#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT       (0x1<<2)
-#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR       (0x1<<3)
-#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT                 (1<<3)
-#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR                 (1<<2)
-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT   (1<<5)
-#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR   (1<<4)
-#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT                  (1<<3)
-#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR                  (1<<2)
-#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR            (1<<22)
-#define AEU_INPUTS_ATTN_BITS_SPIO5                            (1<<15)
-#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT                 (1<<27)
-#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT              (1<<5)
-#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT                (1<<25)
-#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR                (1<<24)
-#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT               (1<<29)
-#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR               (1<<28)
-#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT                 (1<<23)
-#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT                 (1<<27)
-#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR                 (1<<26)
-#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT                (1<<21)
-#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR                (1<<20)
-#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT               (1<<25)
-#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR               (1<<24)
-#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR       (1<<16)
-#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT                 (1<<9)
-#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT                (1<<7)
-#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR                (1<<6)
-#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT               (1<<11)
-#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR               (1<<10)
+#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT                    (0x1<<4)
+#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR                    (0x1<<5)
+#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR                    (0x1<<18)
+#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT                    (0x1<<31)
+#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR                    (0x1<<30)
+#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT                    (0x1<<9)
+#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR                    (0x1<<8)
+#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT                    (0x1<<7)
+#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR                    (0x1<<6)
+#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT                   (0x1<<29)
+#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR                   (0x1<<28)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT                  (0x1<<1)
+#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR                  (0x1<<0)
+#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR                  (0x1<<18)
+#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT                   (0x1<<11)
+#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR                   (0x1<<10)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT              (0x1<<13)
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR              (0x1<<12)
+#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0                    (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR                    (0x1<<12)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY              (0x1<<28)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY            (0x1<<31)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY           (0x1<<29)
+#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY           (0x1<<30)
+#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT                   (0x1<<15)
+#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR                   (0x1<<14)
+#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR                    (0x1<<14)
+#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR                 (0x1<<20)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT               (0x1<<31)
+#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR               (0x1<<30)
+#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR                    (0x1<<0)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT                  (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR                  (0x1<<3)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT      (0x1<<5)
+#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR      (0x1<<4)
+#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT                    (0x1<<3)
+#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR                    (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT                     (0x1<<3)
+#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR                     (0x1<<2)
+#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR               (0x1<<22)
+#define AEU_INPUTS_ATTN_BITS_SPIO5                               (0x1<<15)
+#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT                    (0x1<<27)
+#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR                    (0x1<<26)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT                 (0x1<<5)
+#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR                 (0x1<<4)
+#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT                   (0x1<<25)
+#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR                   (0x1<<24)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT                  (0x1<<29)
+#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR                  (0x1<<28)
+#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT                    (0x1<<23)
+#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR                    (0x1<<22)
+#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT                    (0x1<<27)
+#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR                    (0x1<<26)
+#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT                   (0x1<<21)
+#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR                   (0x1<<20)
+#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT                  (0x1<<25)
+#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR                  (0x1<<24)
+#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR          (0x1<<16)
+#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT                    (0x1<<9)
+#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR                    (0x1<<8)
+#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT                   (0x1<<7)
+#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR                   (0x1<<6)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT                  (0x1<<11)
+#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR                  (0x1<<10)
+
+#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0                   (0x1<<5)
+#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1                   (0x1<<9)
+
 #define RESERVED_GENERAL_ATTENTION_BIT_0        0
 
-#define EVEREST_GEN_ATTN_IN_USE_MASK            0x3ffe0
+#define EVEREST_GEN_ATTN_IN_USE_MASK            0x7ffe0
 #define EVEREST_LATCHED_ATTN_IN_USE_MASK        0xffe00000
 
 #define RESERVED_GENERAL_ATTENTION_BIT_6        6