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authorVladislav Zolotarov <vladz@broadcom.com>2011-06-13 21:33:51 -0400
committerDavid S. Miller <davem@conan.davemloft.net>2011-06-15 10:56:55 -0400
commitc9ee92062424375fe6e73c4af5d52df289ccf9eb (patch)
treeacbc3646162c2187c1314a97b288ba07fba7fc5a /drivers
parent619c5cb6885b936c44ae1422ef805b69c6291485 (diff)
bnx2x: 57712 parity handling
- Added support for a parity error handling for a 57712 chip. - Changed the parity recovery scheme from per-chip to per-engine. Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@conan.davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2x/bnx2x.h25
-rw-r--r--drivers/net/bnx2x/bnx2x_cmn.c57
-rw-r--r--drivers/net/bnx2x/bnx2x_cmn.h16
-rw-r--r--drivers/net/bnx2x/bnx2x_ethtool.c3
-rw-r--r--drivers/net/bnx2x/bnx2x_init.h11
-rw-r--r--drivers/net/bnx2x/bnx2x_main.c753
-rw-r--r--drivers/net/bnx2x/bnx2x_reg.h158
7 files changed, 769 insertions, 254 deletions
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index b4b3abe9e7c4..c108e4cf6333 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -733,7 +733,6 @@ struct bnx2x_common {
733 733
734#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 734#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
735#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 735#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
736#define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
737#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 736#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
738 (CHIP_REV_SHIFT + 1)) \ 737 (CHIP_REV_SHIFT + 1)) \
739 << CHIP_REV_SHIFT) 738 << CHIP_REV_SHIFT)
@@ -986,11 +985,13 @@ struct hw_context {
986/* forward */ 985/* forward */
987struct bnx2x_ilt; 986struct bnx2x_ilt;
988 987
989typedef enum { 988
989enum bnx2x_recovery_state {
990 BNX2X_RECOVERY_DONE, 990 BNX2X_RECOVERY_DONE,
991 BNX2X_RECOVERY_INIT, 991 BNX2X_RECOVERY_INIT,
992 BNX2X_RECOVERY_WAIT, 992 BNX2X_RECOVERY_WAIT,
993} bnx2x_recovery_state_t; 993 BNX2X_RECOVERY_FAILED
994};
994 995
995/* 996/*
996 * Event queue (EQ or event ring) MC hsi 997 * Event queue (EQ or event ring) MC hsi
@@ -1076,7 +1077,7 @@ struct bnx2x {
1076 const struct iro *iro_arr; 1077 const struct iro *iro_arr;
1077#define IRO (bp->iro_arr) 1078#define IRO (bp->iro_arr)
1078 1079
1079 bnx2x_recovery_state_t recovery_state; 1080 enum bnx2x_recovery_state recovery_state;
1080 int is_leader; 1081 int is_leader;
1081 struct msix_entry *msix_table; 1082 struct msix_entry *msix_table;
1082 1083
@@ -1800,12 +1801,14 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1800 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 1801 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1801 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 1802 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1802 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 1803 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1803 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) 1804 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1804#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 1805#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1805 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 1806 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1806 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 1807 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1807 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 1808 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1808 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) 1809 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1810 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1811 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1809#define HW_INTERRUT_ASSERT_SET_1 \ 1812#define HW_INTERRUT_ASSERT_SET_1 \
1810 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 1813 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1811 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 1814 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
@@ -1818,17 +1821,22 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1818 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 1821 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1819 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 1822 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1820 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 1823 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1821#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ 1824#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
1822 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 1825 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1826 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
1823 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 1827 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1828 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
1824 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 1829 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1825 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 1830 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1831 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
1826 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 1832 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1827 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 1833 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1828 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 1834 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1835 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
1829 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 1836 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1830 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 1837 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1831 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) 1838 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
1839 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
1832#define HW_INTERRUT_ASSERT_SET_2 \ 1840#define HW_INTERRUT_ASSERT_SET_2 \
1833 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 1841 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1834 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 1842 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
@@ -1840,6 +1848,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1840 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 1848 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1841 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 1849 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1842 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 1850 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1851 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
1843 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 1852 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1844 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 1853 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1845 1854
diff --git a/drivers/net/bnx2x/bnx2x_cmn.c b/drivers/net/bnx2x/bnx2x_cmn.c
index ebd8b1cdd58c..04cacbf5d714 100644
--- a/drivers/net/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/bnx2x/bnx2x_cmn.c
@@ -1918,13 +1918,23 @@ load_error0:
1918int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode) 1918int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
1919{ 1919{
1920 int i; 1920 int i;
1921 1921 bool global = false;
1922 if (bp->state == BNX2X_STATE_CLOSED) { 1922
1923 /* Interface has been removed - nothing to recover */ 1923 if ((bp->state == BNX2X_STATE_CLOSED) ||
1924 (bp->state == BNX2X_STATE_ERROR)) {
1925 /* We can get here if the driver has been unloaded
1926 * during parity error recovery and is either waiting for a
1927 * leader to complete or for other functions to unload and
1928 * then ifdown has been issued. In this case we want to
1929 * unload and let other functions to complete a recovery
1930 * process.
1931 */
1924 bp->recovery_state = BNX2X_RECOVERY_DONE; 1932 bp->recovery_state = BNX2X_RECOVERY_DONE;
1925 bp->is_leader = 0; 1933 bp->is_leader = 0;
1926 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08); 1934 bnx2x_release_leader_lock(bp);
1927 smp_wmb(); 1935 smp_mb();
1936
1937 DP(NETIF_MSG_HW, "Releasing a leadership...\n");
1928 1938
1929 return -EINVAL; 1939 return -EINVAL;
1930 } 1940 }
@@ -1953,11 +1963,27 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
1953 if (unload_mode != UNLOAD_RECOVERY) 1963 if (unload_mode != UNLOAD_RECOVERY)
1954 bnx2x_chip_cleanup(bp, unload_mode); 1964 bnx2x_chip_cleanup(bp, unload_mode);
1955 else { 1965 else {
1956 /* Disable HW interrupts, NAPI and Tx */ 1966 /* Send the UNLOAD_REQUEST to the MCP */
1967 bnx2x_send_unload_req(bp, unload_mode);
1968
1969 /*
1970 * Prevent transactions to host from the functions on the
1971 * engine that doesn't reset global blocks in case of global
1972 * attention once gloabl blocks are reset and gates are opened
1973 * (the engine which leader will perform the recovery
1974 * last).
1975 */
1976 if (!CHIP_IS_E1x(bp))
1977 bnx2x_pf_disable(bp);
1978
1979 /* Disable HW interrupts, NAPI */
1957 bnx2x_netif_stop(bp, 1); 1980 bnx2x_netif_stop(bp, 1);
1958 1981
1959 /* Release IRQs */ 1982 /* Release IRQs */
1960 bnx2x_free_irq(bp); 1983 bnx2x_free_irq(bp);
1984
1985 /* Report UNLOAD_DONE to MCP */
1986 bnx2x_send_unload_done(bp);
1961 } 1987 }
1962 1988
1963 /* 1989 /*
@@ -1977,17 +2003,24 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
1977 2003
1978 bp->state = BNX2X_STATE_CLOSED; 2004 bp->state = BNX2X_STATE_CLOSED;
1979 2005
2006 /* Check if there are pending parity attentions. If there are - set
2007 * RECOVERY_IN_PROGRESS.
2008 */
2009 if (bnx2x_chk_parity_attn(bp, &global, false)) {
2010 bnx2x_set_reset_in_progress(bp);
2011
2012 /* Set RESET_IS_GLOBAL if needed */
2013 if (global)
2014 bnx2x_set_reset_global(bp);
2015 }
2016
2017
1980 /* The last driver must disable a "close the gate" if there is no 2018 /* The last driver must disable a "close the gate" if there is no
1981 * parity attention or "process kill" pending. 2019 * parity attention or "process kill" pending.
1982 */ 2020 */
1983 if ((!bnx2x_dec_load_cnt(bp)) && (!bnx2x_chk_parity_attn(bp)) && 2021 if (!bnx2x_dec_load_cnt(bp) && bnx2x_reset_is_done(bp, BP_PATH(bp)))
1984 bnx2x_reset_is_done(bp))
1985 bnx2x_disable_close_the_gate(bp); 2022 bnx2x_disable_close_the_gate(bp);
1986 2023
1987 /* Reset MCP mail box sequence if there is on going recovery */
1988 if (unload_mode == UNLOAD_RECOVERY)
1989 bp->fw_seq = 0;
1990
1991 return 0; 2024 return 0;
1992} 2025}
1993 2026
diff --git a/drivers/net/bnx2x/bnx2x_cmn.h b/drivers/net/bnx2x/bnx2x_cmn.h
index 944bcaeeba45..c016e20c5c2b 100644
--- a/drivers/net/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/bnx2x/bnx2x_cmn.h
@@ -181,6 +181,9 @@ void bnx2x_drv_pulse(struct bnx2x *bp);
181void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 181void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
182 u16 index, u8 op, u8 update); 182 u16 index, u8 op, u8 update);
183 183
184/* Disable transactions from chip to host */
185void bnx2x_pf_disable(struct bnx2x *bp);
186
184/** 187/**
185 * bnx2x__link_status_update - handles link status change. 188 * bnx2x__link_status_update - handles link status change.
186 * 189 *
@@ -321,6 +324,13 @@ int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
321int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 324int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
322 325
323/** 326/**
327 * bnx2x_release_leader_lock - release recovery leader lock
328 *
329 * @bp: driver handle
330 */
331int bnx2x_release_leader_lock(struct bnx2x *bp);
332
333/**
324 * bnx2x_set_eth_mac - configure eth MAC address in the HW 334 * bnx2x_set_eth_mac - configure eth MAC address in the HW
325 * 335 *
326 * @bp: driver handle 336 * @bp: driver handle
@@ -370,8 +380,10 @@ void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
370/* Parity errors related */ 380/* Parity errors related */
371void bnx2x_inc_load_cnt(struct bnx2x *bp); 381void bnx2x_inc_load_cnt(struct bnx2x *bp);
372u32 bnx2x_dec_load_cnt(struct bnx2x *bp); 382u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
373bool bnx2x_chk_parity_attn(struct bnx2x *bp); 383bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
374bool bnx2x_reset_is_done(struct bnx2x *bp); 384bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
385void bnx2x_set_reset_in_progress(struct bnx2x *bp);
386void bnx2x_set_reset_global(struct bnx2x *bp);
375void bnx2x_disable_close_the_gate(struct bnx2x *bp); 387void bnx2x_disable_close_the_gate(struct bnx2x *bp);
376 388
377/** 389/**
diff --git a/drivers/net/bnx2x/bnx2x_ethtool.c b/drivers/net/bnx2x/bnx2x_ethtool.c
index 1b4fa1d98005..965fb071fbe4 100644
--- a/drivers/net/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/bnx2x/bnx2x_ethtool.c
@@ -634,8 +634,7 @@ static void bnx2x_get_regs(struct net_device *dev,
634 } 634 }
635 /* Re-enable parity attentions */ 635 /* Re-enable parity attentions */
636 bnx2x_clear_blocks_parity(bp); 636 bnx2x_clear_blocks_parity(bp);
637 if (CHIP_PARITY_ENABLED(bp)) 637 bnx2x_enable_blocks_parity(bp);
638 bnx2x_enable_blocks_parity(bp);
639} 638}
640 639
641static void bnx2x_get_drvinfo(struct net_device *dev, 640static void bnx2x_get_drvinfo(struct net_device *dev,
diff --git a/drivers/net/bnx2x/bnx2x_init.h b/drivers/net/bnx2x/bnx2x_init.h
index 8b1d62584436..df9f196dd6e8 100644
--- a/drivers/net/bnx2x/bnx2x_init.h
+++ b/drivers/net/bnx2x/bnx2x_init.h
@@ -377,12 +377,15 @@ static const struct {
377 BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff), 377 BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),
378 BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff), 378 BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff),
379 BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0), 379 BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),
380 BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0),
381 BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff),
382 BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xffff),
380 BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff), 383 BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff),
381 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1), 384 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
382 BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff), 385 BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff),
383 BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3), 386 BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
384 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 387 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
385 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0, 388 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
386 {0xf, 0xf, 0xf}, "UPB"}, 389 {0xf, 0xf, 0xf}, "UPB"},
387 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 390 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
388 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0, 391 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
@@ -394,10 +397,16 @@ static const struct {
394 BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf), 397 BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
395 BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf), 398 BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
396 BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff), 399 BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
400 BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffffff),
401 BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f),
397 BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff), 402 BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
398 BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff), 403 BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
399 BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff), 404 BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
400 BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff), 405 BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
406 BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff),
407 BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff),
408 BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff),
409 BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff),
401 BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff), 410 BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
402 BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f), 411 BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f),
403 BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff), 412 BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index 63c92091586f..7ffb6e651e16 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -1606,6 +1606,34 @@ static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1606 return false; 1606 return false;
1607} 1607}
1608 1608
1609/**
1610 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1611 *
1612 * @bp: driver handle
1613 *
1614 * Returns the recovery leader resource id according to the engine this function
1615 * belongs to. Currently only only 2 engines is supported.
1616 */
1617static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1618{
1619 if (BP_PATH(bp))
1620 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1621 else
1622 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1623}
1624
1625/**
1626 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1627 *
1628 * @bp: driver handle
1629 *
1630 * Tries to aquire a leader lock for cuurent engine.
1631 */
1632static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1633{
1634 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1635}
1636
1609#ifdef BCM_CNIC 1637#ifdef BCM_CNIC
1610static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err); 1638static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1611#endif 1639#endif
@@ -1802,6 +1830,11 @@ int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1802 return -EAGAIN; 1830 return -EAGAIN;
1803} 1831}
1804 1832
1833int bnx2x_release_leader_lock(struct bnx2x *bp)
1834{
1835 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1836}
1837
1805int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) 1838int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1806{ 1839{
1807 u32 lock_status; 1840 u32 lock_status;
@@ -3323,72 +3356,185 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3323 } 3356 }
3324} 3357}
3325 3358
3326#define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1 3359/*
3327#define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */ 3360 * Bits map:
3328#define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1) 3361 * 0-7 - Engine0 load counter.
3329#define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK) 3362 * 8-15 - Engine1 load counter.
3330#define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS 3363 * 16 - Engine0 RESET_IN_PROGRESS bit.
3364 * 17 - Engine1 RESET_IN_PROGRESS bit.
3365 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3366 * on the engine
3367 * 19 - Engine1 ONE_IS_LOADED.
3368 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3369 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3370 * just the one belonging to its engine).
3371 *
3372 */
3373#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3374
3375#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3376#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3377#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3378#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3379#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3380#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3381#define BNX2X_GLOBAL_RESET_BIT 0x00040000
3331 3382
3332/* 3383/*
3384 * Set the GLOBAL_RESET bit.
3385 *
3386 * Should be run under rtnl lock
3387 */
3388void bnx2x_set_reset_global(struct bnx2x *bp)
3389{
3390 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3391
3392 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3393 barrier();
3394 mmiowb();
3395}
3396
3397/*
3398 * Clear the GLOBAL_RESET bit.
3399 *
3400 * Should be run under rtnl lock
3401 */
3402static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3403{
3404 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3405
3406 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3407 barrier();
3408 mmiowb();
3409}
3410
3411/*
3412 * Checks the GLOBAL_RESET bit.
3413 *
3333 * should be run under rtnl lock 3414 * should be run under rtnl lock
3334 */ 3415 */
3416static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3417{
3418 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3419
3420 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3421 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3422}
3423
3424/*
3425 * Clear RESET_IN_PROGRESS bit for the current engine.
3426 *
3427 * Should be run under rtnl lock
3428 */
3335static inline void bnx2x_set_reset_done(struct bnx2x *bp) 3429static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3336{ 3430{
3337 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG); 3431 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3338 val &= ~(1 << RESET_DONE_FLAG_SHIFT); 3432 u32 bit = BP_PATH(bp) ?
3339 REG_WR(bp, BNX2X_MISC_GEN_REG, val); 3433 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3434
3435 /* Clear the bit */
3436 val &= ~bit;
3437 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3340 barrier(); 3438 barrier();
3341 mmiowb(); 3439 mmiowb();
3342} 3440}
3343 3441
3344/* 3442/*
3443 * Set RESET_IN_PROGRESS for the current engine.
3444 *
3345 * should be run under rtnl lock 3445 * should be run under rtnl lock
3346 */ 3446 */
3347static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp) 3447void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3348{ 3448{
3349 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG); 3449 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3350 val |= (1 << 16); 3450 u32 bit = BP_PATH(bp) ?
3351 REG_WR(bp, BNX2X_MISC_GEN_REG, val); 3451 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3452
3453 /* Set the bit */
3454 val |= bit;
3455 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3352 barrier(); 3456 barrier();
3353 mmiowb(); 3457 mmiowb();
3354} 3458}
3355 3459
3356/* 3460/*
3461 * Checks the RESET_IN_PROGRESS bit for the given engine.
3357 * should be run under rtnl lock 3462 * should be run under rtnl lock
3358 */ 3463 */
3359bool bnx2x_reset_is_done(struct bnx2x *bp) 3464bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3360{ 3465{
3361 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG); 3466 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3362 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val); 3467 u32 bit = engine ?
3363 return (val & RESET_DONE_FLAG_MASK) ? false : true; 3468 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3469
3470 /* return false if bit is set */
3471 return (val & bit) ? false : true;
3364} 3472}
3365 3473
3366/* 3474/*
3475 * Increment the load counter for the current engine.
3476 *
3367 * should be run under rtnl lock 3477 * should be run under rtnl lock
3368 */ 3478 */
3369inline void bnx2x_inc_load_cnt(struct bnx2x *bp) 3479void bnx2x_inc_load_cnt(struct bnx2x *bp)
3370{ 3480{
3371 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG); 3481 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3482 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3483 BNX2X_PATH0_LOAD_CNT_MASK;
3484 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3485 BNX2X_PATH0_LOAD_CNT_SHIFT;
3372 3486
3373 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3487 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3374 3488
3375 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK; 3489 /* get the current counter value */
3376 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1); 3490 val1 = (val & mask) >> shift;
3491
3492 /* increment... */
3493 val1++;
3494
3495 /* clear the old value */
3496 val &= ~mask;
3497
3498 /* set the new one */
3499 val |= ((val1 << shift) & mask);
3500
3501 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3377 barrier(); 3502 barrier();
3378 mmiowb(); 3503 mmiowb();
3379} 3504}
3380 3505
3381/* 3506/**
3382 * should be run under rtnl lock 3507 * bnx2x_dec_load_cnt - decrement the load counter
3508 *
3509 * @bp: driver handle
3510 *
3511 * Should be run under rtnl lock.
3512 * Decrements the load counter for the current engine. Returns
3513 * the new counter value.
3383 */ 3514 */
3384u32 bnx2x_dec_load_cnt(struct bnx2x *bp) 3515u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3385{ 3516{
3386 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG); 3517 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3518 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3519 BNX2X_PATH0_LOAD_CNT_MASK;
3520 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3521 BNX2X_PATH0_LOAD_CNT_SHIFT;
3387 3522
3388 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3523 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3389 3524
3390 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK; 3525 /* get the current counter value */
3391 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1); 3526 val1 = (val & mask) >> shift;
3527
3528 /* decrement... */
3529 val1--;
3530
3531 /* clear the old value */
3532 val &= ~mask;
3533
3534 /* set the new one */
3535 val |= ((val1 << shift) & mask);
3536
3537 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3392 barrier(); 3538 barrier();
3393 mmiowb(); 3539 mmiowb();
3394 3540
@@ -3396,17 +3542,39 @@ u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3396} 3542}
3397 3543
3398/* 3544/*
3545 * Read the load counter for the current engine.
3546 *
3399 * should be run under rtnl lock 3547 * should be run under rtnl lock
3400 */ 3548 */
3401static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp) 3549static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3402{ 3550{
3403 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK; 3551 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3552 BNX2X_PATH0_LOAD_CNT_MASK);
3553 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3554 BNX2X_PATH0_LOAD_CNT_SHIFT);
3555 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3556
3557 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3558
3559 val = (val & mask) >> shift;
3560
3561 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3562
3563 return val;
3404} 3564}
3405 3565
3566/*
3567 * Reset the load counter for the current engine.
3568 *
3569 * should be run under rtnl lock
3570 */
3406static inline void bnx2x_clear_load_cnt(struct bnx2x *bp) 3571static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3407{ 3572{
3408 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG); 3573 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3409 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK)); 3574 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3575 BNX2X_PATH0_LOAD_CNT_MASK);
3576
3577 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3410} 3578}
3411 3579
3412static inline void _print_next_block(int idx, const char *blk) 3580static inline void _print_next_block(int idx, const char *blk)
@@ -3416,7 +3584,8 @@ static inline void _print_next_block(int idx, const char *blk)
3416 pr_cont("%s", blk); 3584 pr_cont("%s", blk);
3417} 3585}
3418 3586
3419static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num) 3587static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3588 bool print)
3420{ 3589{
3421 int i = 0; 3590 int i = 0;
3422 u32 cur_bit = 0; 3591 u32 cur_bit = 0;
@@ -3425,19 +3594,33 @@ static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3425 if (sig & cur_bit) { 3594 if (sig & cur_bit) {
3426 switch (cur_bit) { 3595 switch (cur_bit) {
3427 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 3596 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3428 _print_next_block(par_num++, "BRB"); 3597 if (print)
3598 _print_next_block(par_num++, "BRB");
3429 break; 3599 break;
3430 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 3600 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3431 _print_next_block(par_num++, "PARSER"); 3601 if (print)
3602 _print_next_block(par_num++, "PARSER");
3432 break; 3603 break;
3433 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 3604 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3434 _print_next_block(par_num++, "TSDM"); 3605 if (print)
3606 _print_next_block(par_num++, "TSDM");
3435 break; 3607 break;
3436 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 3608 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3437 _print_next_block(par_num++, "SEARCHER"); 3609 if (print)
3610 _print_next_block(par_num++,
3611 "SEARCHER");
3612 break;
3613 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3614 if (print)
3615 _print_next_block(par_num++, "TCM");
3438 break; 3616 break;
3439 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 3617 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3440 _print_next_block(par_num++, "TSEMI"); 3618 if (print)
3619 _print_next_block(par_num++, "TSEMI");
3620 break;
3621 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3622 if (print)
3623 _print_next_block(par_num++, "XPB");
3441 break; 3624 break;
3442 } 3625 }
3443 3626
@@ -3449,7 +3632,8 @@ static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3449 return par_num; 3632 return par_num;
3450} 3633}
3451 3634
3452static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num) 3635static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3636 bool *global, bool print)
3453{ 3637{
3454 int i = 0; 3638 int i = 0;
3455 u32 cur_bit = 0; 3639 u32 cur_bit = 0;
@@ -3457,38 +3641,64 @@ static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3457 cur_bit = ((u32)0x1 << i); 3641 cur_bit = ((u32)0x1 << i);
3458 if (sig & cur_bit) { 3642 if (sig & cur_bit) {
3459 switch (cur_bit) { 3643 switch (cur_bit) {
3460 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 3644 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3461 _print_next_block(par_num++, "PBCLIENT"); 3645 if (print)
3646 _print_next_block(par_num++, "PBF");
3462 break; 3647 break;
3463 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 3648 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3464 _print_next_block(par_num++, "QM"); 3649 if (print)
3650 _print_next_block(par_num++, "QM");
3651 break;
3652 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3653 if (print)
3654 _print_next_block(par_num++, "TM");
3465 break; 3655 break;
3466 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 3656 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3467 _print_next_block(par_num++, "XSDM"); 3657 if (print)
3658 _print_next_block(par_num++, "XSDM");
3659 break;
3660 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3661 if (print)
3662 _print_next_block(par_num++, "XCM");
3468 break; 3663 break;
3469 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 3664 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3470 _print_next_block(par_num++, "XSEMI"); 3665 if (print)
3666 _print_next_block(par_num++, "XSEMI");
3471 break; 3667 break;
3472 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 3668 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3473 _print_next_block(par_num++, "DOORBELLQ"); 3669 if (print)
3670 _print_next_block(par_num++,
3671 "DOORBELLQ");
3672 break;
3673 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3674 if (print)
3675 _print_next_block(par_num++, "NIG");
3474 break; 3676 break;
3475 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 3677 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3476 _print_next_block(par_num++, "VAUX PCI CORE"); 3678 if (print)
3679 _print_next_block(par_num++,
3680 "VAUX PCI CORE");
3681 *global = true;
3477 break; 3682 break;
3478 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 3683 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3479 _print_next_block(par_num++, "DEBUG"); 3684 if (print)
3685 _print_next_block(par_num++, "DEBUG");
3480 break; 3686 break;
3481 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 3687 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3482 _print_next_block(par_num++, "USDM"); 3688 if (print)
3689 _print_next_block(par_num++, "USDM");
3483 break; 3690 break;
3484 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 3691 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3485 _print_next_block(par_num++, "USEMI"); 3692 if (print)
3693 _print_next_block(par_num++, "USEMI");
3486 break; 3694 break;
3487 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 3695 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3488 _print_next_block(par_num++, "UPB"); 3696 if (print)
3697 _print_next_block(par_num++, "UPB");
3489 break; 3698 break;
3490 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 3699 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3491 _print_next_block(par_num++, "CSDM"); 3700 if (print)
3701 _print_next_block(par_num++, "CSDM");
3492 break; 3702 break;
3493 } 3703 }
3494 3704
@@ -3500,7 +3710,8 @@ static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3500 return par_num; 3710 return par_num;
3501} 3711}
3502 3712
3503static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num) 3713static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3714 bool print)
3504{ 3715{
3505 int i = 0; 3716 int i = 0;
3506 u32 cur_bit = 0; 3717 u32 cur_bit = 0;
@@ -3509,26 +3720,37 @@ static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3509 if (sig & cur_bit) { 3720 if (sig & cur_bit) {
3510 switch (cur_bit) { 3721 switch (cur_bit) {
3511 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 3722 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3512 _print_next_block(par_num++, "CSEMI"); 3723 if (print)
3724 _print_next_block(par_num++, "CSEMI");
3513 break; 3725 break;
3514 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 3726 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3515 _print_next_block(par_num++, "PXP"); 3727 if (print)
3728 _print_next_block(par_num++, "PXP");
3516 break; 3729 break;
3517 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 3730 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3518 _print_next_block(par_num++, 3731 if (print)
3732 _print_next_block(par_num++,
3519 "PXPPCICLOCKCLIENT"); 3733 "PXPPCICLOCKCLIENT");
3520 break; 3734 break;
3521 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 3735 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3522 _print_next_block(par_num++, "CFC"); 3736 if (print)
3737 _print_next_block(par_num++, "CFC");
3523 break; 3738 break;
3524 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 3739 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3525 _print_next_block(par_num++, "CDU"); 3740 if (print)
3741 _print_next_block(par_num++, "CDU");
3742 break;
3743 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3744 if (print)
3745 _print_next_block(par_num++, "DMAE");
3526 break; 3746 break;
3527 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 3747 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3528 _print_next_block(par_num++, "IGU"); 3748 if (print)
3749 _print_next_block(par_num++, "IGU");
3529 break; 3750 break;
3530 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 3751 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3531 _print_next_block(par_num++, "MISC"); 3752 if (print)
3753 _print_next_block(par_num++, "MISC");
3532 break; 3754 break;
3533 } 3755 }
3534 3756
@@ -3540,7 +3762,8 @@ static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3540 return par_num; 3762 return par_num;
3541} 3763}
3542 3764
3543static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num) 3765static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3766 bool *global, bool print)
3544{ 3767{
3545 int i = 0; 3768 int i = 0;
3546 u32 cur_bit = 0; 3769 u32 cur_bit = 0;
@@ -3549,16 +3772,27 @@ static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3549 if (sig & cur_bit) { 3772 if (sig & cur_bit) {
3550 switch (cur_bit) { 3773 switch (cur_bit) {
3551 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 3774 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3552 _print_next_block(par_num++, "MCP ROM"); 3775 if (print)
3776 _print_next_block(par_num++, "MCP ROM");
3777 *global = true;
3553 break; 3778 break;
3554 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 3779 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3555 _print_next_block(par_num++, "MCP UMP RX"); 3780 if (print)
3781 _print_next_block(par_num++,
3782 "MCP UMP RX");
3783 *global = true;
3556 break; 3784 break;
3557 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 3785 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3558 _print_next_block(par_num++, "MCP UMP TX"); 3786 if (print)
3787 _print_next_block(par_num++,
3788 "MCP UMP TX");
3789 *global = true;
3559 break; 3790 break;
3560 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 3791 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3561 _print_next_block(par_num++, "MCP SCPAD"); 3792 if (print)
3793 _print_next_block(par_num++,
3794 "MCP SCPAD");
3795 *global = true;
3562 break; 3796 break;
3563 } 3797 }
3564 3798
@@ -3570,8 +3804,8 @@ static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3570 return par_num; 3804 return par_num;
3571} 3805}
3572 3806
3573static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1, 3807static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
3574 u32 sig2, u32 sig3) 3808 u32 sig0, u32 sig1, u32 sig2, u32 sig3)
3575{ 3809{
3576 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) || 3810 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3577 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) { 3811 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
@@ -3583,23 +3817,32 @@ static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3583 sig1 & HW_PRTY_ASSERT_SET_1, 3817 sig1 & HW_PRTY_ASSERT_SET_1,
3584 sig2 & HW_PRTY_ASSERT_SET_2, 3818 sig2 & HW_PRTY_ASSERT_SET_2,
3585 sig3 & HW_PRTY_ASSERT_SET_3); 3819 sig3 & HW_PRTY_ASSERT_SET_3);
3586 printk(KERN_ERR"%s: Parity errors detected in blocks: ", 3820 if (print)
3587 bp->dev->name); 3821 netdev_err(bp->dev,
3588 par_num = bnx2x_print_blocks_with_parity0( 3822 "Parity errors detected in blocks: ");
3589 sig0 & HW_PRTY_ASSERT_SET_0, par_num); 3823 par_num = bnx2x_check_blocks_with_parity0(
3590 par_num = bnx2x_print_blocks_with_parity1( 3824 sig0 & HW_PRTY_ASSERT_SET_0, par_num, print);
3591 sig1 & HW_PRTY_ASSERT_SET_1, par_num); 3825 par_num = bnx2x_check_blocks_with_parity1(
3592 par_num = bnx2x_print_blocks_with_parity2( 3826 sig1 & HW_PRTY_ASSERT_SET_1, par_num, global, print);
3593 sig2 & HW_PRTY_ASSERT_SET_2, par_num); 3827 par_num = bnx2x_check_blocks_with_parity2(
3594 par_num = bnx2x_print_blocks_with_parity3( 3828 sig2 & HW_PRTY_ASSERT_SET_2, par_num, print);
3595 sig3 & HW_PRTY_ASSERT_SET_3, par_num); 3829 par_num = bnx2x_check_blocks_with_parity3(
3596 printk("\n"); 3830 sig3 & HW_PRTY_ASSERT_SET_3, par_num, global, print);
3831 if (print)
3832 pr_cont("\n");
3597 return true; 3833 return true;
3598 } else 3834 } else
3599 return false; 3835 return false;
3600} 3836}
3601 3837
3602bool bnx2x_chk_parity_attn(struct bnx2x *bp) 3838/**
3839 * bnx2x_chk_parity_attn - checks for parity attentions.
3840 *
3841 * @bp: driver handle
3842 * @global: true if there was a global attention
3843 * @print: show parity attention in syslog
3844 */
3845bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
3603{ 3846{
3604 struct attn_route attn; 3847 struct attn_route attn;
3605 int port = BP_PORT(bp); 3848 int port = BP_PORT(bp);
@@ -3617,8 +3860,8 @@ bool bnx2x_chk_parity_attn(struct bnx2x *bp)
3617 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + 3860 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3618 port*4); 3861 port*4);
3619 3862
3620 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2], 3863 return bnx2x_parity_attn(bp, global, print, attn.sig[0], attn.sig[1],
3621 attn.sig[3]); 3864 attn.sig[2], attn.sig[3]);
3622} 3865}
3623 3866
3624 3867
@@ -3697,21 +3940,25 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3697 u32 reg_addr; 3940 u32 reg_addr;
3698 u32 val; 3941 u32 val;
3699 u32 aeu_mask; 3942 u32 aeu_mask;
3943 bool global = false;
3700 3944
3701 /* need to take HW lock because MCP or other port might also 3945 /* need to take HW lock because MCP or other port might also
3702 try to handle this event */ 3946 try to handle this event */
3703 bnx2x_acquire_alr(bp); 3947 bnx2x_acquire_alr(bp);
3704 3948
3705 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) { 3949 if (bnx2x_chk_parity_attn(bp, &global, true)) {
3950#ifndef BNX2X_STOP_ON_ERROR
3706 bp->recovery_state = BNX2X_RECOVERY_INIT; 3951 bp->recovery_state = BNX2X_RECOVERY_INIT;
3707 bnx2x_set_reset_in_progress(bp);
3708 schedule_delayed_work(&bp->reset_task, 0); 3952 schedule_delayed_work(&bp->reset_task, 0);
3709 /* Disable HW interrupts */ 3953 /* Disable HW interrupts */
3710 bnx2x_int_disable(bp); 3954 bnx2x_int_disable(bp);
3711 bnx2x_release_alr(bp);
3712 /* In case of parity errors don't handle attentions so that 3955 /* In case of parity errors don't handle attentions so that
3713 * other function would "see" parity errors. 3956 * other function would "see" parity errors.
3714 */ 3957 */
3958#else
3959 bnx2x_panic();
3960#endif
3961 bnx2x_release_alr(bp);
3715 return; 3962 return;
3716 } 3963 }
3717 3964
@@ -5289,7 +5536,7 @@ static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5289 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num); 5536 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5290} 5537}
5291 5538
5292static void bnx2x_pf_disable(struct bnx2x *bp) 5539void bnx2x_pf_disable(struct bnx2x *bp)
5293{ 5540{
5294 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); 5541 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5295 val &= ~IGU_PF_CONF_FUNC_EN; 5542 val &= ~IGU_PF_CONF_FUNC_EN;
@@ -5733,8 +5980,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
5733 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); 5980 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5734 5981
5735 bnx2x_enable_blocks_attention(bp); 5982 bnx2x_enable_blocks_attention(bp);
5736 if (CHIP_PARITY_ENABLED(bp)) 5983 bnx2x_enable_blocks_parity(bp);
5737 bnx2x_enable_blocks_parity(bp);
5738 5984
5739 if (!BP_NOMCP(bp)) { 5985 if (!BP_NOMCP(bp)) {
5740 if (CHIP_IS_E1x(bp)) 5986 if (CHIP_IS_E1x(bp))
@@ -7165,24 +7411,37 @@ void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7165/* Close gates #2, #3 and #4: */ 7411/* Close gates #2, #3 and #4: */
7166static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) 7412static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7167{ 7413{
7168 u32 val, addr; 7414 u32 val;
7169 7415
7170 /* Gates #2 and #4a are closed/opened for "not E1" only */ 7416 /* Gates #2 and #4a are closed/opened for "not E1" only */
7171 if (!CHIP_IS_E1(bp)) { 7417 if (!CHIP_IS_E1(bp)) {
7172 /* #4 */ 7418 /* #4 */
7173 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS); 7419 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7174 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7175 close ? (val | 0x1) : (val & (~(u32)1)));
7176 /* #2 */ 7420 /* #2 */
7177 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES); 7421 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7178 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7179 close ? (val | 0x1) : (val & (~(u32)1)));
7180 } 7422 }
7181 7423
7182 /* #3 */ 7424 /* #3 */
7183 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 7425 if (CHIP_IS_E1x(bp)) {
7184 val = REG_RD(bp, addr); 7426 /* Prevent interrupts from HC on both ports */
7185 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1))); 7427 val = REG_RD(bp, HC_REG_CONFIG_1);
7428 REG_WR(bp, HC_REG_CONFIG_1,
7429 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7430 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7431
7432 val = REG_RD(bp, HC_REG_CONFIG_0);
7433 REG_WR(bp, HC_REG_CONFIG_0,
7434 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7435 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7436 } else {
7437 /* Prevent incomming interrupts in IGU */
7438 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7439
7440 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7441 (!close) ?
7442 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7443 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7444 }
7186 7445
7187 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 7446 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7188 close ? "closing" : "opening"); 7447 close ? "closing" : "opening");
@@ -7300,7 +7559,6 @@ static void bnx2x_pxp_prep(struct bnx2x *bp)
7300 if (!CHIP_IS_E1(bp)) { 7559 if (!CHIP_IS_E1(bp)) {
7301 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); 7560 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7302 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); 7561 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7303 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7304 mmiowb(); 7562 mmiowb();
7305 } 7563 }
7306} 7564}
@@ -7315,9 +7573,18 @@ static void bnx2x_pxp_prep(struct bnx2x *bp)
7315 * - GRC 7573 * - GRC
7316 * - RBCN, RBCP 7574 * - RBCN, RBCP
7317 */ 7575 */
7318static void bnx2x_process_kill_chip_reset(struct bnx2x *bp) 7576static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
7319{ 7577{
7320 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 7578 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7579 u32 global_bits2;
7580
7581 /*
7582 * Bits that have to be set in reset_mask2 if we want to reset 'global'
7583 * (per chip) blocks.
7584 */
7585 global_bits2 =
7586 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
7587 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
7321 7588
7322 not_reset_mask1 = 7589 not_reset_mask1 =
7323 MISC_REGISTERS_RESET_REG_1_RST_HC | 7590 MISC_REGISTERS_RESET_REG_1_RST_HC |
@@ -7325,7 +7592,7 @@ static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7325 MISC_REGISTERS_RESET_REG_1_RST_PXP; 7592 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7326 7593
7327 not_reset_mask2 = 7594 not_reset_mask2 =
7328 MISC_REGISTERS_RESET_REG_2_RST_MDIO | 7595 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
7329 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 7596 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7330 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 7597 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7331 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 7598 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
@@ -7341,20 +7608,76 @@ static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7341 else 7608 else
7342 reset_mask2 = 0x1ffff; 7609 reset_mask2 = 0x1ffff;
7343 7610
7344 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 7611 if (CHIP_IS_E3(bp)) {
7345 reset_mask1 & (~not_reset_mask1)); 7612 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7613 reset_mask2 |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7614 }
7615
7616 /* Don't reset global blocks unless we need to */
7617 if (!global)
7618 reset_mask2 &= ~global_bits2;
7619
7620 /*
7621 * In case of attention in the QM, we need to reset PXP
7622 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
7623 * because otherwise QM reset would release 'close the gates' shortly
7624 * before resetting the PXP, then the PSWRQ would send a write
7625 * request to PGLUE. Then when PXP is reset, PGLUE would try to
7626 * read the payload data from PSWWR, but PSWWR would not
7627 * respond. The write queue in PGLUE would stuck, dmae commands
7628 * would not return. Therefore it's important to reset the second
7629 * reset register (containing the
7630 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
7631 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
7632 * bit).
7633 */
7346 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 7634 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7347 reset_mask2 & (~not_reset_mask2)); 7635 reset_mask2 & (~not_reset_mask2));
7348 7636
7637 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7638 reset_mask1 & (~not_reset_mask1));
7639
7349 barrier(); 7640 barrier();
7350 mmiowb(); 7641 mmiowb();
7351 7642
7352 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7353 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2); 7643 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7644 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7354 mmiowb(); 7645 mmiowb();
7355} 7646}
7356 7647
7357static int bnx2x_process_kill(struct bnx2x *bp) 7648/**
7649 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
7650 * It should get cleared in no more than 1s.
7651 *
7652 * @bp: driver handle
7653 *
7654 * It should get cleared in no more than 1s. Returns 0 if
7655 * pending writes bit gets cleared.
7656 */
7657static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
7658{
7659 u32 cnt = 1000;
7660 u32 pend_bits = 0;
7661
7662 do {
7663 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
7664
7665 if (pend_bits == 0)
7666 break;
7667
7668 usleep_range(1000, 1000);
7669 } while (cnt-- > 0);
7670
7671 if (cnt <= 0) {
7672 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
7673 pend_bits);
7674 return -EBUSY;
7675 }
7676
7677 return 0;
7678}
7679
7680static int bnx2x_process_kill(struct bnx2x *bp, bool global)
7358{ 7681{
7359 int cnt = 1000; 7682 int cnt = 1000;
7360 u32 val = 0; 7683 u32 val = 0;
@@ -7373,7 +7696,7 @@ static int bnx2x_process_kill(struct bnx2x *bp)
7373 ((port_is_idle_1 & 0x1) == 0x1) && 7696 ((port_is_idle_1 & 0x1) == 0x1) &&
7374 (pgl_exp_rom2 == 0xffffffff)) 7697 (pgl_exp_rom2 == 0xffffffff))
7375 break; 7698 break;
7376 msleep(1); 7699 usleep_range(1000, 1000);
7377 } while (cnt-- > 0); 7700 } while (cnt-- > 0);
7378 7701
7379 if (cnt <= 0) { 7702 if (cnt <= 0) {
@@ -7393,6 +7716,11 @@ static int bnx2x_process_kill(struct bnx2x *bp)
7393 /* Close gates #2, #3 and #4 */ 7716 /* Close gates #2, #3 and #4 */
7394 bnx2x_set_234_gates(bp, true); 7717 bnx2x_set_234_gates(bp, true);
7395 7718
7719 /* Poll for IGU VQs for 57712 and newer chips */
7720 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
7721 return -EAGAIN;
7722
7723
7396 /* TBD: Indicate that "process kill" is in progress to MCP */ 7724 /* TBD: Indicate that "process kill" is in progress to MCP */
7397 7725
7398 /* Clear "unprepared" bit */ 7726 /* Clear "unprepared" bit */
@@ -7405,25 +7733,28 @@ static int bnx2x_process_kill(struct bnx2x *bp)
7405 /* Wait for 1ms to empty GLUE and PCI-E core queues, 7733 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7406 * PSWHST, GRC and PSWRD Tetris buffer. 7734 * PSWHST, GRC and PSWRD Tetris buffer.
7407 */ 7735 */
7408 msleep(1); 7736 usleep_range(1000, 1000);
7409 7737
7410 /* Prepare to chip reset: */ 7738 /* Prepare to chip reset: */
7411 /* MCP */ 7739 /* MCP */
7412 bnx2x_reset_mcp_prep(bp, &val); 7740 if (global)
7741 bnx2x_reset_mcp_prep(bp, &val);
7413 7742
7414 /* PXP */ 7743 /* PXP */
7415 bnx2x_pxp_prep(bp); 7744 bnx2x_pxp_prep(bp);
7416 barrier(); 7745 barrier();
7417 7746
7418 /* reset the chip */ 7747 /* reset the chip */
7419 bnx2x_process_kill_chip_reset(bp); 7748 bnx2x_process_kill_chip_reset(bp, global);
7420 barrier(); 7749 barrier();
7421 7750
7422 /* Recover after reset: */ 7751 /* Recover after reset: */
7423 /* MCP */ 7752 /* MCP */
7424 if (bnx2x_reset_mcp_comp(bp, val)) 7753 if (global && bnx2x_reset_mcp_comp(bp, val))
7425 return -EAGAIN; 7754 return -EAGAIN;
7426 7755
7756 /* TBD: Add resetting the NO_MCP mode DB here */
7757
7427 /* PXP */ 7758 /* PXP */
7428 bnx2x_pxp_prep(bp); 7759 bnx2x_pxp_prep(bp);
7429 7760
@@ -7436,43 +7767,85 @@ static int bnx2x_process_kill(struct bnx2x *bp)
7436 return 0; 7767 return 0;
7437} 7768}
7438 7769
7439static int bnx2x_leader_reset(struct bnx2x *bp) 7770int bnx2x_leader_reset(struct bnx2x *bp)
7440{ 7771{
7441 int rc = 0; 7772 int rc = 0;
7773 bool global = bnx2x_reset_is_global(bp);
7774
7442 /* Try to recover after the failure */ 7775 /* Try to recover after the failure */
7443 if (bnx2x_process_kill(bp)) { 7776 if (bnx2x_process_kill(bp, global)) {
7444 printk(KERN_ERR "%s: Something bad had happen! Aii!\n", 7777 netdev_err(bp->dev, "Something bad had happen on engine %d! "
7445 bp->dev->name); 7778 "Aii!\n", BP_PATH(bp));
7446 rc = -EAGAIN; 7779 rc = -EAGAIN;
7447 goto exit_leader_reset; 7780 goto exit_leader_reset;
7448 } 7781 }
7449 7782
7450 /* Clear "reset is in progress" bit and update the driver state */ 7783 /*
7784 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
7785 * state.
7786 */
7451 bnx2x_set_reset_done(bp); 7787 bnx2x_set_reset_done(bp);
7452 bp->recovery_state = BNX2X_RECOVERY_DONE; 7788 if (global)
7789 bnx2x_clear_reset_global(bp);
7453 7790
7454exit_leader_reset: 7791exit_leader_reset:
7455 bp->is_leader = 0; 7792 bp->is_leader = 0;
7456 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08); 7793 bnx2x_release_leader_lock(bp);
7457 smp_wmb(); 7794 smp_mb();
7458 return rc; 7795 return rc;
7459} 7796}
7460 7797
7461/* Assumption: runs under rtnl lock. This together with the fact 7798static inline void bnx2x_recovery_failed(struct bnx2x *bp)
7799{
7800 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
7801
7802 /* Disconnect this device */
7803 netif_device_detach(bp->dev);
7804
7805 /*
7806 * Block ifup for all function on this engine until "process kill"
7807 * or power cycle.
7808 */
7809 bnx2x_set_reset_in_progress(bp);
7810
7811 /* Shut down the power */
7812 bnx2x_set_power_state(bp, PCI_D3hot);
7813
7814 bp->recovery_state = BNX2X_RECOVERY_FAILED;
7815
7816 smp_mb();
7817}
7818
7819/*
7820 * Assumption: runs under rtnl lock. This together with the fact
7462 * that it's called only from bnx2x_reset_task() ensure that it 7821 * that it's called only from bnx2x_reset_task() ensure that it
7463 * will never be called when netif_running(bp->dev) is false. 7822 * will never be called when netif_running(bp->dev) is false.
7464 */ 7823 */
7465static void bnx2x_parity_recover(struct bnx2x *bp) 7824static void bnx2x_parity_recover(struct bnx2x *bp)
7466{ 7825{
7826 bool global = false;
7827
7467 DP(NETIF_MSG_HW, "Handling parity\n"); 7828 DP(NETIF_MSG_HW, "Handling parity\n");
7468 while (1) { 7829 while (1) {
7469 switch (bp->recovery_state) { 7830 switch (bp->recovery_state) {
7470 case BNX2X_RECOVERY_INIT: 7831 case BNX2X_RECOVERY_INIT:
7471 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n"); 7832 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7833 bnx2x_chk_parity_attn(bp, &global, false);
7834
7472 /* Try to get a LEADER_LOCK HW lock */ 7835 /* Try to get a LEADER_LOCK HW lock */
7473 if (bnx2x_trylock_hw_lock(bp, 7836 if (bnx2x_trylock_leader_lock(bp)) {
7474 HW_LOCK_RESOURCE_RESERVED_08)) 7837 bnx2x_set_reset_in_progress(bp);
7838 /*
7839 * Check if there is a global attention and if
7840 * there was a global attention, set the global
7841 * reset bit.
7842 */
7843
7844 if (global)
7845 bnx2x_set_reset_global(bp);
7846
7475 bp->is_leader = 1; 7847 bp->is_leader = 1;
7848 }
7476 7849
7477 /* Stop the driver */ 7850 /* Stop the driver */
7478 /* If interface has been removed - break */ 7851 /* If interface has been removed - break */
@@ -7480,17 +7853,43 @@ static void bnx2x_parity_recover(struct bnx2x *bp)
7480 return; 7853 return;
7481 7854
7482 bp->recovery_state = BNX2X_RECOVERY_WAIT; 7855 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7483 /* Ensure "is_leader" and "recovery_state" 7856
7484 * update values are seen on other CPUs 7857 /*
7858 * Reset MCP command sequence number and MCP mail box
7859 * sequence as we are going to reset the MCP.
7860 */
7861 if (global) {
7862 bp->fw_seq = 0;
7863 bp->fw_drv_pulse_wr_seq = 0;
7864 }
7865
7866 /* Ensure "is_leader", MCP command sequence and
7867 * "recovery_state" update values are seen on other
7868 * CPUs.
7485 */ 7869 */
7486 smp_wmb(); 7870 smp_mb();
7487 break; 7871 break;
7488 7872
7489 case BNX2X_RECOVERY_WAIT: 7873 case BNX2X_RECOVERY_WAIT:
7490 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n"); 7874 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7491 if (bp->is_leader) { 7875 if (bp->is_leader) {
7492 u32 load_counter = bnx2x_get_load_cnt(bp); 7876 int other_engine = BP_PATH(bp) ? 0 : 1;
7493 if (load_counter) { 7877 u32 other_load_counter =
7878 bnx2x_get_load_cnt(bp, other_engine);
7879 u32 load_counter =
7880 bnx2x_get_load_cnt(bp, BP_PATH(bp));
7881 global = bnx2x_reset_is_global(bp);
7882
7883 /*
7884 * In case of a parity in a global block, let
7885 * the first leader that performs a
7886 * leader_reset() reset the global blocks in
7887 * order to clear global attentions. Otherwise
7888 * the the gates will remain closed for that
7889 * engine.
7890 */
7891 if (load_counter ||
7892 (global && other_load_counter)) {
7494 /* Wait until all other functions get 7893 /* Wait until all other functions get
7495 * down. 7894 * down.
7496 */ 7895 */
@@ -7503,37 +7902,27 @@ static void bnx2x_parity_recover(struct bnx2x *bp)
7503 * normal. In any case it's an exit 7902 * normal. In any case it's an exit
7504 * point for a leader. 7903 * point for a leader.
7505 */ 7904 */
7506 if (bnx2x_leader_reset(bp) || 7905 if (bnx2x_leader_reset(bp)) {
7507 bnx2x_nic_load(bp, LOAD_NORMAL)) { 7906 bnx2x_recovery_failed(bp);
7508 printk(KERN_ERR"%s: Recovery "
7509 "has failed. Power cycle is "
7510 "needed.\n", bp->dev->name);
7511 /* Disconnect this device */
7512 netif_device_detach(bp->dev);
7513 /* Block ifup for all function
7514 * of this ASIC until
7515 * "process kill" or power
7516 * cycle.
7517 */
7518 bnx2x_set_reset_in_progress(bp);
7519 /* Shut down the power */
7520 bnx2x_set_power_state(bp,
7521 PCI_D3hot);
7522 return; 7907 return;
7523 } 7908 }
7524 7909
7525 return; 7910 /* If we are here, means that the
7911 * leader has succeeded and doesn't
7912 * want to be a leader any more. Try
7913 * to continue as a none-leader.
7914 */
7915 break;
7526 } 7916 }
7527 } else { /* non-leader */ 7917 } else { /* non-leader */
7528 if (!bnx2x_reset_is_done(bp)) { 7918 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
7529 /* Try to get a LEADER_LOCK HW lock as 7919 /* Try to get a LEADER_LOCK HW lock as
7530 * long as a former leader may have 7920 * long as a former leader may have
7531 * been unloaded by the user or 7921 * been unloaded by the user or
7532 * released a leadership by another 7922 * released a leadership by another
7533 * reason. 7923 * reason.
7534 */ 7924 */
7535 if (bnx2x_trylock_hw_lock(bp, 7925 if (bnx2x_trylock_leader_lock(bp)) {
7536 HW_LOCK_RESOURCE_RESERVED_08)) {
7537 /* I'm a leader now! Restart a 7926 /* I'm a leader now! Restart a
7538 * switch case. 7927 * switch case.
7539 */ 7928 */
@@ -7545,14 +7934,25 @@ static void bnx2x_parity_recover(struct bnx2x *bp)
7545 HZ/10); 7934 HZ/10);
7546 return; 7935 return;
7547 7936
7548 } else { /* A leader has completed 7937 } else {
7549 * the "process kill". It's an exit 7938 /*
7550 * point for a non-leader. 7939 * If there was a global attention, wait
7551 */ 7940 * for it to be cleared.
7552 bnx2x_nic_load(bp, LOAD_NORMAL); 7941 */
7553 bp->recovery_state = 7942 if (bnx2x_reset_is_global(bp)) {
7554 BNX2X_RECOVERY_DONE; 7943 schedule_delayed_work(
7555 smp_wmb(); 7944 &bp->reset_task, HZ/10);
7945 return;
7946 }
7947
7948 if (bnx2x_nic_load(bp, LOAD_NORMAL))
7949 bnx2x_recovery_failed(bp);
7950 else {
7951 bp->recovery_state =
7952 BNX2X_RECOVERY_DONE;
7953 smp_mb();
7954 }
7955
7556 return; 7956 return;
7557 } 7957 }
7558 } 7958 }
@@ -8871,45 +9271,62 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8871static int bnx2x_open(struct net_device *dev) 9271static int bnx2x_open(struct net_device *dev)
8872{ 9272{
8873 struct bnx2x *bp = netdev_priv(dev); 9273 struct bnx2x *bp = netdev_priv(dev);
9274 bool global = false;
9275 int other_engine = BP_PATH(bp) ? 0 : 1;
9276 u32 other_load_counter, load_counter;
8874 9277
8875 netif_carrier_off(dev); 9278 netif_carrier_off(dev);
8876 9279
8877 bnx2x_set_power_state(bp, PCI_D0); 9280 bnx2x_set_power_state(bp, PCI_D0);
8878 9281
8879 if (!bnx2x_reset_is_done(bp)) { 9282 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9283 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9284
9285 /*
9286 * If parity had happen during the unload, then attentions
9287 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9288 * want the first function loaded on the current engine to
9289 * complete the recovery.
9290 */
9291 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9292 bnx2x_chk_parity_attn(bp, &global, true))
8880 do { 9293 do {
8881 /* Reset MCP mail box sequence if there is on going 9294 /*
8882 * recovery 9295 * If there are attentions and they are in a global
9296 * blocks, set the GLOBAL_RESET bit regardless whether
9297 * it will be this function that will complete the
9298 * recovery or not.
8883 */ 9299 */
8884 bp->fw_seq = 0; 9300 if (global)
9301 bnx2x_set_reset_global(bp);
8885 9302
8886 /* If it's the first function to load and reset done 9303 /*
8887 * is still not cleared it may mean that. We don't 9304 * Only the first function on the current engine should
8888 * check the attention state here because it may have 9305 * try to recover in open. In case of attentions in
8889 * already been cleared by a "common" reset but we 9306 * global blocks only the first in the chip should try
8890 * shell proceed with "process kill" anyway. 9307 * to recover.
8891 */ 9308 */
8892 if ((bnx2x_get_load_cnt(bp) == 0) && 9309 if ((!load_counter &&
8893 bnx2x_trylock_hw_lock(bp, 9310 (!global || !other_load_counter)) &&
8894 HW_LOCK_RESOURCE_RESERVED_08) && 9311 bnx2x_trylock_leader_lock(bp) &&
8895 (!bnx2x_leader_reset(bp))) { 9312 !bnx2x_leader_reset(bp)) {
8896 DP(NETIF_MSG_HW, "Recovered in open\n"); 9313 netdev_info(bp->dev, "Recovered in open\n");
8897 break; 9314 break;
8898 } 9315 }
8899 9316
9317 /* recovery has failed... */
8900 bnx2x_set_power_state(bp, PCI_D3hot); 9318 bnx2x_set_power_state(bp, PCI_D3hot);
9319 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8901 9320
8902 printk(KERN_ERR"%s: Recovery flow hasn't been properly" 9321 netdev_err(bp->dev, "Recovery flow hasn't been properly"
8903 " completed yet. Try again later. If u still see this" 9322 " completed yet. Try again later. If u still see this"
8904 " message after a few retries then power cycle is" 9323 " message after a few retries then power cycle is"
8905 " required.\n", bp->dev->name); 9324 " required.\n");
8906 9325
8907 return -EAGAIN; 9326 return -EAGAIN;
8908 } while (0); 9327 } while (0);
8909 }
8910 9328
8911 bp->recovery_state = BNX2X_RECOVERY_DONE; 9329 bp->recovery_state = BNX2X_RECOVERY_DONE;
8912
8913 return bnx2x_nic_load(bp, LOAD_OPEN); 9330 return bnx2x_nic_load(bp, LOAD_OPEN);
8914} 9331}
8915 9332
@@ -8920,6 +9337,8 @@ static int bnx2x_close(struct net_device *dev)
8920 9337
8921 /* Unload the driver, release IRQs */ 9338 /* Unload the driver, release IRQs */
8922 bnx2x_nic_unload(bp, UNLOAD_CLOSE); 9339 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9340
9341 /* Power off */
8923 bnx2x_set_power_state(bp, PCI_D3hot); 9342 bnx2x_set_power_state(bp, PCI_D3hot);
8924 9343
8925 return 0; 9344 return 0;
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h
index 9868cb0270a4..f8436e0c1316 100644
--- a/drivers/net/bnx2x/bnx2x_reg.h
+++ b/drivers/net/bnx2x/bnx2x_reg.h
@@ -804,10 +804,12 @@
804/* [RW 28] TCM Header when both ULP and TCP context is loaded. */ 804/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
805#define DORQ_REG_SHRT_CMHEAD 0x170054 805#define DORQ_REG_SHRT_CMHEAD 0x170054
806#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) 806#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
807#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
807#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) 808#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
808#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7) 809#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
809#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) 810#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
810#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 811#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
812#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
811#define HC_REG_AGG_INT_0 0x108050 813#define HC_REG_AGG_INT_0 0x108050
812#define HC_REG_AGG_INT_1 0x108054 814#define HC_REG_AGG_INT_1 0x108054
813#define HC_REG_ATTN_BIT 0x108120 815#define HC_REG_ATTN_BIT 0x108120
@@ -846,6 +848,7 @@
846#define HC_REG_VQID_0 0x108008 848#define HC_REG_VQID_0 0x108008
847#define HC_REG_VQID_1 0x10800c 849#define HC_REG_VQID_1 0x10800c
848#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1) 850#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
851#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
849#define IGU_REG_ATTENTION_ACK_BITS 0x130108 852#define IGU_REG_ATTENTION_ACK_BITS 0x130108
850/* [R 4] Debug: attn_fsm */ 853/* [R 4] Debug: attn_fsm */
851#define IGU_REG_ATTN_FSM 0x130054 854#define IGU_REG_ATTN_FSM 0x130054
@@ -1876,11 +1879,21 @@
1876/* [R 32] Interrupt register #0 read */ 1879/* [R 32] Interrupt register #0 read */
1877#define NIG_REG_NIG_INT_STS_0 0x103b0 1880#define NIG_REG_NIG_INT_STS_0 0x103b0
1878#define NIG_REG_NIG_INT_STS_1 0x103c0 1881#define NIG_REG_NIG_INT_STS_1 0x103c0
1882/* [R 32] Legacy E1 and E1H location for parity error mask register. */
1883#define NIG_REG_NIG_PRTY_MASK 0x103dc
1884/* [RW 32] Parity mask register #0 read/write */
1885#define NIG_REG_NIG_PRTY_MASK_0 0x183c8
1886#define NIG_REG_NIG_PRTY_MASK_1 0x183d8
1879/* [R 32] Legacy E1 and E1H location for parity error status register. */ 1887/* [R 32] Legacy E1 and E1H location for parity error status register. */
1880#define NIG_REG_NIG_PRTY_STS 0x103d0 1888#define NIG_REG_NIG_PRTY_STS 0x103d0
1881/* [R 32] Parity register #0 read */ 1889/* [R 32] Parity register #0 read */
1882#define NIG_REG_NIG_PRTY_STS_0 0x183bc 1890#define NIG_REG_NIG_PRTY_STS_0 0x183bc
1883#define NIG_REG_NIG_PRTY_STS_1 0x183cc 1891#define NIG_REG_NIG_PRTY_STS_1 0x183cc
1892/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
1893#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
1894/* [RC 32] Parity register #0 read clear */
1895#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
1896#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
1884/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 1897/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
1885 * Ethernet header. */ 1898 * Ethernet header. */
1886#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038 1899#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
@@ -4322,6 +4335,8 @@
4322#define UCM_REG_UCM_INT_MASK 0xe01d4 4335#define UCM_REG_UCM_INT_MASK 0xe01d4
4323/* [R 11] Interrupt register #0 read */ 4336/* [R 11] Interrupt register #0 read */
4324#define UCM_REG_UCM_INT_STS 0xe01c8 4337#define UCM_REG_UCM_INT_STS 0xe01c8
4338/* [RW 27] Parity mask register #0 read/write */
4339#define UCM_REG_UCM_PRTY_MASK 0xe01e4
4325/* [R 27] Parity register #0 read */ 4340/* [R 27] Parity register #0 read */
4326#define UCM_REG_UCM_PRTY_STS 0xe01d8 4341#define UCM_REG_UCM_PRTY_STS 0xe01d8
4327/* [RC 27] Parity register #0 read clear */ 4342/* [RC 27] Parity register #0 read clear */
@@ -4843,8 +4858,13 @@
4843#define XCM_REG_XCM_INT_MASK 0x202b4 4858#define XCM_REG_XCM_INT_MASK 0x202b4
4844/* [R 14] Interrupt register #0 read */ 4859/* [R 14] Interrupt register #0 read */
4845#define XCM_REG_XCM_INT_STS 0x202a8 4860#define XCM_REG_XCM_INT_STS 0x202a8
4861/* [RW 30] Parity mask register #0 read/write */
4862#define XCM_REG_XCM_PRTY_MASK 0x202c4
4846/* [R 30] Parity register #0 read */ 4863/* [R 30] Parity register #0 read */
4847#define XCM_REG_XCM_PRTY_STS 0x202b8 4864#define XCM_REG_XCM_PRTY_STS 0x202b8
4865/* [RC 30] Parity register #0 read clear */
4866#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
4867
4848/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS 4868/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4849 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4869 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4850 Is used to determine the number of the AG context REG-pairs written back; 4870 Is used to determine the number of the AG context REG-pairs written back;
@@ -5284,9 +5304,12 @@
5284#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15) 5304#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
5285#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) 5305#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
5286#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) 5306#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
5307#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
5308#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
5287#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) 5309#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5288#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13) 5310#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
5289#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11) 5311#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
5312#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
5290#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 5313#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
5291#define MISC_REGISTERS_RESET_REG_2_SET 0x594 5314#define MISC_REGISTERS_RESET_REG_2_SET 0x594
5292#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 5315#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
@@ -5315,71 +5338,82 @@
5315#define HW_LOCK_MAX_RESOURCE_VALUE 31 5338#define HW_LOCK_MAX_RESOURCE_VALUE 31
5316#define HW_LOCK_RESOURCE_GPIO 1 5339#define HW_LOCK_RESOURCE_GPIO 1
5317#define HW_LOCK_RESOURCE_MDIO 0 5340#define HW_LOCK_RESOURCE_MDIO 0
5318#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 5341#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5319#define HW_LOCK_RESOURCE_RESERVED_08 8 5342#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8
5343#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9
5320#define HW_LOCK_RESOURCE_SPIO 2 5344#define HW_LOCK_RESOURCE_SPIO 2
5321#define HW_LOCK_RESOURCE_UNDI 5 5345#define HW_LOCK_RESOURCE_UNDI 5
5322#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) 5346#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
5323#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) 5347#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
5324#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) 5348#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
5325#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) 5349#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
5326#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) 5350#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
5327#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8) 5351#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
5328#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7) 5352#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
5329#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6) 5353#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
5330#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29) 5354#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
5331#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28) 5355#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
5332#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1) 5356#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
5333#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0) 5357#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
5334#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18) 5358#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
5335#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11) 5359#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
5336#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13) 5360#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
5337#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12) 5361#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
5338#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (1<<2) 5362#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
5339#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5) 5363#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
5340#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9) 5364#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
5341#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12) 5365#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
5342#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (1<<28) 5366#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
5343#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (1<<31) 5367#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31)
5344#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (1<<29) 5368#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
5345#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (1<<30) 5369#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
5346#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15) 5370#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
5347#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14) 5371#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
5348#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20) 5372#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
5349#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0) 5373#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
5350#define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31) 5374#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
5351#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2) 5375#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
5352#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3) 5376#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
5353#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3) 5377#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
5354#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2) 5378#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
5355#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5) 5379#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
5356#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4) 5380#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
5357#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3) 5381#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
5358#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2) 5382#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
5359#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22) 5383#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
5360#define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15) 5384#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
5361#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27) 5385#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
5362#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5) 5386#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
5363#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25) 5387#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
5364#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24) 5388#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
5365#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29) 5389#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
5366#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28) 5390#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
5367#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23) 5391#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
5368#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27) 5392#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
5369#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26) 5393#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
5370#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21) 5394#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
5371#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20) 5395#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
5372#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25) 5396#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
5373#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24) 5397#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
5374#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16) 5398#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
5375#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9) 5399#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
5376#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7) 5400#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
5377#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6) 5401#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
5378#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11) 5402#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
5379#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10) 5403#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
5404#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
5405#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
5406#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
5407#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
5408#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
5409#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
5410
5411#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)
5412#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)
5413
5380#define RESERVED_GENERAL_ATTENTION_BIT_0 0 5414#define RESERVED_GENERAL_ATTENTION_BIT_0 0
5381 5415
5382#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0 5416#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
5383#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 5417#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5384 5418
5385#define RESERVED_GENERAL_ATTENTION_BIT_6 6 5419#define RESERVED_GENERAL_ATTENTION_BIT_6 6
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 14:54:16 -0500