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authorAlex Deucher <alexander.deucher@amd.com>2012-08-10 13:26:24 -0400
committerAlex Deucher <alexander.deucher@amd.com>2012-09-20 13:10:33 -0400
commitee93b86be118dcdec1a8e29983ed1d010c71bfee (patch)
tree4f662dde9f72811d6c97c624a285da6943f77070 /drivers/gpu/drm/radeon/r100.c
parent95f5a3acfaf6f5672420398e01ca32220b36bb90 (diff)
drm/radeon: remove gui_idle interrupt infrastructure
It was only used for dynpm, but has been replaced with a better implementation using fences. Remove it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c19
1 files changed, 0 insertions, 19 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 163c33e1a1d6..ff3a444836d4 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -700,9 +700,6 @@ int r100_irq_set(struct radeon_device *rdev)
700 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 700 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
701 tmp |= RADEON_SW_INT_ENABLE; 701 tmp |= RADEON_SW_INT_ENABLE;
702 } 702 }
703 if (rdev->irq.gui_idle) {
704 tmp |= RADEON_GUI_IDLE_MASK;
705 }
706 if (rdev->irq.crtc_vblank_int[0] || 703 if (rdev->irq.crtc_vblank_int[0] ||
707 atomic_read(&rdev->irq.pflip[0])) { 704 atomic_read(&rdev->irq.pflip[0])) {
708 tmp |= RADEON_CRTC_VBLANK_MASK; 705 tmp |= RADEON_CRTC_VBLANK_MASK;
@@ -739,12 +736,6 @@ static uint32_t r100_irq_ack(struct radeon_device *rdev)
739 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 736 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
740 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 737 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
741 738
742 /* the interrupt works, but the status bit is permanently asserted */
743 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
744 if (!rdev->irq.gui_idle_acked)
745 irq_mask |= RADEON_GUI_IDLE_STAT;
746 }
747
748 if (irqs) { 739 if (irqs) {
749 WREG32(RADEON_GEN_INT_STATUS, irqs); 740 WREG32(RADEON_GEN_INT_STATUS, irqs);
750 } 741 }
@@ -756,9 +747,6 @@ int r100_irq_process(struct radeon_device *rdev)
756 uint32_t status, msi_rearm; 747 uint32_t status, msi_rearm;
757 bool queue_hotplug = false; 748 bool queue_hotplug = false;
758 749
759 /* reset gui idle ack. the status bit is broken */
760 rdev->irq.gui_idle_acked = false;
761
762 status = r100_irq_ack(rdev); 750 status = r100_irq_ack(rdev);
763 if (!status) { 751 if (!status) {
764 return IRQ_NONE; 752 return IRQ_NONE;
@@ -771,11 +759,6 @@ int r100_irq_process(struct radeon_device *rdev)
771 if (status & RADEON_SW_INT_TEST) { 759 if (status & RADEON_SW_INT_TEST) {
772 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 760 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
773 } 761 }
774 /* gui idle interrupt */
775 if (status & RADEON_GUI_IDLE_STAT) {
776 rdev->irq.gui_idle_acked = true;
777 wake_up(&rdev->irq.idle_queue);
778 }
779 /* Vertical blank interrupts */ 762 /* Vertical blank interrupts */
780 if (status & RADEON_CRTC_VBLANK_STAT) { 763 if (status & RADEON_CRTC_VBLANK_STAT) {
781 if (rdev->irq.crtc_vblank_int[0]) { 764 if (rdev->irq.crtc_vblank_int[0]) {
@@ -805,8 +788,6 @@ int r100_irq_process(struct radeon_device *rdev)
805 } 788 }
806 status = r100_irq_ack(rdev); 789 status = r100_irq_ack(rdev);
807 } 790 }
808 /* reset gui idle ack. the status bit is broken */
809 rdev->irq.gui_idle_acked = false;
810 if (queue_hotplug) 791 if (queue_hotplug)
811 schedule_work(&rdev->hotplug_work); 792 schedule_work(&rdev->hotplug_work);
812 if (rdev->msi_enabled) { 793 if (rdev->msi_enabled) {