Merge branch 'linus' into idle-test

1484 files changed, 75437 insertions, 39219 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 8bf0fa652eb6..f78c2be4242b 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -175,4 +175,7 @@ config HAVE_PERF_EVENTS_NMI
 config HAVE_ARCH_JUMP_LABEL
         bool
 
+config HAVE_ARCH_MUTEX_CPU_RELAX
+        bool
+
 source "kernel/gcov/Kconfig"
diff --git a/arch/alpha/include/asm/ioctls.h b/arch/alpha/include/asm/ioctls.h
index 59617c3c2be6..034b6cf5d9f3 100644
--- a/arch/alpha/include/asm/ioctls.h
+++ b/arch/alpha/include/asm/ioctls.h
@@ -92,6 +92,7 @@
 #define TIOCGSID        0x5429  /* Return the session ID of FD */
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+#define TIOCGDEV        _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
 #define TIOCSIG         _IOW('T',0x36, int)  /* Generate signal on Pty slave */
 
 #define TIOCSERCONFIG   0x5453
diff --git a/arch/alpha/include/asm/perf_event.h b/arch/alpha/include/asm/perf_event.h
index fe792ca818f6..5996e7a6757e 100644
--- a/arch/alpha/include/asm/perf_event.h
+++ b/arch/alpha/include/asm/perf_event.h
@@ -1,10 +1,4 @@
 #ifndef __ASM_ALPHA_PERF_EVENT_H
 #define __ASM_ALPHA_PERF_EVENT_H
 
-#ifdef CONFIG_PERF_EVENTS
-extern void init_hw_perf_events(void);
-#else
-static inline void init_hw_perf_events(void)    { }
-#endif
-
 #endif /* __ASM_ALPHA_PERF_EVENT_H */
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c
index 5f77afb88e89..4c8bb374eb0a 100644
--- a/arch/alpha/kernel/irq_alpha.c
+++ b/arch/alpha/kernel/irq_alpha.c
@@ -112,8 +112,6 @@ init_IRQ(void)
         wrent(entInt, 0);
 
         alpha_mv.init_irq();
-
-        init_hw_perf_events();
 }
 
 /*
diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c
index 1cc49683fb69..90561c45e7d8 100644
--- a/arch/alpha/kernel/perf_event.c
+++ b/arch/alpha/kernel/perf_event.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/kdebug.h>
 #include <linux/mutex.h>
+#include <linux/init.h>
 
 #include <asm/hwrpb.h>
 #include <asm/atomic.h>
@@ -863,13 +864,13 @@ static void alpha_perf_event_irq_handler(unsigned long la_ptr,
 /*
  * Init call to initialise performance events at kernel startup.
  */
-void __init init_hw_perf_events(void)
+int __init init_hw_perf_events(void)
 {
         pr_info("Performance events: ");
 
         if (!supported_cpu()) {
                 pr_cont("No support for your CPU.\n");
-                return;
+                return 0;
         }
 
         pr_cont("Supported CPU type!\n");
@@ -881,6 +882,8 @@ void __init init_hw_perf_events(void)
         /* And set up PMU specification */
         alpha_pmu = &ev67_pmu;
 
-        perf_pmu_register(&pmu);
-}
+        perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
 
+        return 0;
+}
+early_initcall(init_hw_perf_events);
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d56d21c0573b..e2f801167593 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2,6 +2,7 @@ config ARM
         bool
         default y
         select HAVE_AOUT
+        select HAVE_DMA_API_DEBUG
         select HAVE_IDE
         select HAVE_MEMBLOCK
         select RTC_LIB
@@ -14,6 +15,7 @@ config ARM
         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
+        select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_LZO
@@ -23,6 +25,7 @@ config ARM
         select PERF_USE_VMALLOC
         select HAVE_REGS_AND_STACK_ACCESS_API
         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
+        select HAVE_C_RECORDMCOUNT
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -34,9 +37,15 @@ config ARM
 config HAVE_PWM
         bool
 
+config MIGHT_HAVE_PCI
+        bool
+
 config SYS_SUPPORTS_APM_EMULATION
         bool
 
+config HAVE_SCHED_CLOCK
+        bool
+
 config GENERIC_GPIO
         bool
 
@@ -221,7 +230,7 @@ config ARCH_INTEGRATOR
         bool "ARM Ltd. Integrator family"
         select ARM_AMBA
         select ARCH_HAS_CPUFREQ
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select ICST
         select GENERIC_CLOCKEVENTS
         select PLAT_VERSATILE
@@ -231,7 +240,8 @@ config ARCH_INTEGRATOR
 config ARCH_REALVIEW
         bool "ARM Ltd. RealView family"
         select ARM_AMBA
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
+        select HAVE_SCHED_CLOCK
         select ICST
         select GENERIC_CLOCKEVENTS
         select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -245,7 +255,8 @@ config ARCH_VERSATILE
         bool "ARM Ltd. Versatile family"
         select ARM_AMBA
         select ARM_VIC
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
+        select HAVE_SCHED_CLOCK
         select ICST
         select GENERIC_CLOCKEVENTS
         select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -259,9 +270,10 @@ config ARCH_VEXPRESS
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_AMBA
         select ARM_TIMER_SP804
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
+        select HAVE_SCHED_CLOCK
         select ICST
         select PLAT_VERSATILE
         help
@@ -280,7 +292,7 @@ config ARCH_BCMRING
         depends on MMU
         select CPU_V6
         select ARM_AMBA
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         select ARCH_WANT_OPTIONAL_GPIOLIB
         help
@@ -298,6 +310,7 @@ config ARCH_CNS3XXX
         select CPU_V6
         select GENERIC_CLOCKEVENTS
         select ARM_GIC
+        select MIGHT_HAVE_PCI
         select PCI_DOMAINS if PCI
         help
           Support for Cavium Networks CNS3XXX platform.
@@ -327,7 +340,7 @@ config ARCH_EP93XX
         select CPU_ARM920T
         select ARM_AMBA
         select ARM_VIC
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select ARCH_REQUIRE_GPIOLIB
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_USES_GETTIMEOFFSET
@@ -347,14 +360,22 @@ config ARCH_MXC
         bool "Freescale MXC/iMX-based"
         select GENERIC_CLOCKEVENTS
         select ARCH_REQUIRE_GPIOLIB
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         help
           Support for Freescale MXC/iMX-based family of processors
 
+config ARCH_MXS
+        bool "Freescale MXS-based"
+        select GENERIC_CLOCKEVENTS
+        select ARCH_REQUIRE_GPIOLIB
+        select COMMON_CLKDEV
+        help
+          Support for Freescale MXS-based family of processors
+
 config ARCH_STMP3XXX
         bool "Freescale STMP3xxx"
         select CPU_ARM926T
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
         select USB_ARCH_HAS_EHCI
@@ -433,6 +454,8 @@ config ARCH_IXP4XX
         select CPU_XSCALE
         select GENERIC_GPIO
         select GENERIC_CLOCKEVENTS
+        select HAVE_SCHED_CLOCK
+        select MIGHT_HAVE_PCI
         select DMABOUNCE if PCI
         help
           Support for Intel's IXP4XX (XScale) family of processors.
@@ -472,7 +495,7 @@ config ARCH_LPC32XX
         select HAVE_IDE
         select ARM_AMBA
         select USB_ARCH_HAS_OHCI
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         help
@@ -506,8 +529,9 @@ config ARCH_MMP
         bool "Marvell PXA168/910/MMP2"
         depends on MMU
         select ARCH_REQUIRE_GPIOLIB
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
+        select HAVE_SCHED_CLOCK
         select TICK_ONESHOT
         select PLAT_PXA
         select SPARSE_IRQ
@@ -539,7 +563,7 @@ config ARCH_W90X900
         bool "Nuvoton W90X900 CPU"
         select CPU_ARM926T
         select ARCH_REQUIRE_GPIOLIB
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         help
           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
@@ -553,18 +577,19 @@ config ARCH_W90X900
 config ARCH_NUC93X
         bool "Nuvoton NUC93X CPU"
         select CPU_ARM926T
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         help
           Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
           low-power and high performance MPEG-4/JPEG multimedia controller chip.
 
 config ARCH_TEGRA
         bool "NVIDIA Tegra"
+        select CLKDEV_LOOKUP
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         select GENERIC_GPIO
         select HAVE_CLK
-        select COMMON_CLKDEV
+        select HAVE_SCHED_CLOCK
         select ARCH_HAS_BARRIERS if CACHE_L2X0
         select ARCH_HAS_CPUFREQ
         help
@@ -574,7 +599,7 @@ config ARCH_TEGRA
 config ARCH_PNX4008
         bool "Philips Nexperia PNX4008 Mobile"
         select CPU_ARM926T
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select ARCH_USES_GETTIMEOFFSET
         help
           This enables support for Philips PNX4008 mobile platform.
@@ -584,9 +609,10 @@ config ARCH_PXA
         depends on MMU
         select ARCH_MTD_XIP
         select ARCH_HAS_CPUFREQ
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
+        select HAVE_SCHED_CLOCK
         select TICK_ONESHOT
         select PLAT_PXA
         select SPARSE_IRQ
@@ -606,9 +632,15 @@ config ARCH_MSM
           (clock and power control, etc).
 
 config ARCH_SHMOBILE
-        bool "Renesas SH-Mobile"
+        bool "Renesas SH-Mobile / R-Mobile"
+        select HAVE_CLK
+        select CLKDEV_LOOKUP
+        select GENERIC_CLOCKEVENTS
+        select NO_IOPORT
+        select SPARSE_IRQ
+        select MULTI_IRQ_HANDLER
         help
-          Support for Renesas's SH-Mobile ARM platforms
+          Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
 
 config ARCH_RPC
         bool "RiscPC"
@@ -635,6 +667,7 @@ config ARCH_SA1100
         select CPU_FREQ
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
+        select HAVE_SCHED_CLOCK
         select TICK_ONESHOT
         select ARCH_REQUIRE_GPIOLIB
         help
@@ -761,7 +794,7 @@ config ARCH_TCC_926
         bool "Telechips TCC ARM926-based systems"
         select CPU_ARM926T
         select HAVE_CLK
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         help
           Support for Telechips TCC ARM926-based systems.
@@ -781,11 +814,12 @@ config ARCH_U300
         bool "ST-Ericsson U300 Series"
         depends on MMU
         select CPU_ARM926T
+        select HAVE_SCHED_CLOCK
         select HAVE_TCM
         select ARM_AMBA
         select ARM_VIC
         select GENERIC_CLOCKEVENTS
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select GENERIC_GPIO
         help
           Support for ST-Ericsson U300 series mobile platforms.
@@ -795,8 +829,9 @@ config ARCH_U8500
         select CPU_V7
         select ARM_AMBA
         select GENERIC_CLOCKEVENTS
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select ARCH_REQUIRE_GPIOLIB
+        select ARCH_HAS_CPUFREQ
         help
           Support for ST-Ericsson's Ux500 architecture
 
@@ -805,7 +840,7 @@ config ARCH_NOMADIK
         select ARM_AMBA
         select ARM_VIC
         select CPU_ARM926T
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         select ARCH_REQUIRE_GPIOLIB
         help
@@ -817,7 +852,7 @@ config ARCH_DAVINCI
         select ARCH_REQUIRE_GPIOLIB
         select ZONE_DMA
         select HAVE_IDE
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select GENERIC_ALLOCATOR
         select ARCH_HAS_HOLES_MEMORYMODEL
         help
@@ -829,6 +864,7 @@ config ARCH_OMAP
         select ARCH_REQUIRE_GPIOLIB
         select ARCH_HAS_CPUFREQ
         select GENERIC_CLOCKEVENTS
+        select HAVE_SCHED_CLOCK
         select ARCH_HAS_HOLES_MEMORYMODEL
         help
           Support for TI's OMAP platform (OMAP1/2/3/4).
@@ -837,7 +873,7 @@ config PLAT_SPEAR
         bool "ST SPEAr"
         select ARM_AMBA
         select ARCH_REQUIRE_GPIOLIB
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         help
@@ -902,6 +938,8 @@ source "arch/arm/mach-mv78xx0/Kconfig"
 
 source "arch/arm/plat-mxc/Kconfig"
 
+source "arch/arm/mach-mxs/Kconfig"
+
 source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-nomadik/Kconfig"
@@ -982,9 +1020,11 @@ config ARCH_ACORN
 config PLAT_IOP
         bool
         select GENERIC_CLOCKEVENTS
+        select HAVE_SCHED_CLOCK
 
 config PLAT_ORION
         bool
+        select HAVE_SCHED_CLOCK
 
 config PLAT_PXA
         bool
@@ -999,8 +1039,8 @@ source arch/arm/mm/Kconfig
 
 config IWMMXT
         bool "Enable iWMMXt support"
-        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
-        default y if PXA27x || PXA3xx || ARCH_MMP
+        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
+        default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
         help
           Enable support for iWMMXt context switching at run time if
           running on a CPU that supports it.
@@ -1017,6 +1057,11 @@ config CPU_HAS_PMU
         default y
         bool
 
+config MULTI_IRQ_HANDLER
+        bool
+        help
+          Allow each machine to specify it's own IRQ handler at run time.
+
 if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
@@ -1164,7 +1209,7 @@ config ISA_DMA_API
         bool
 
 config PCI
-        bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
+        bool "PCI support" if MIGHT_HAVE_PCI
         help
           Find out whether you have a PCI motherboard. PCI is the name of a
           bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1175,6 +1220,12 @@ config PCI_DOMAINS
         bool
         depends on PCI
 
+config PCI_NANOENGINE
+        bool "BSE nanoEngine PCI support"
+        depends on SA1100_NANOENGINE
+        help
+          Enable PCI on the BSE nanoEngine board.
+
 config PCI_SYSCALL
         def_bool PCI
 
@@ -1205,10 +1256,11 @@ config SMP
         depends on EXPERIMENTAL
         depends on GENERIC_CLOCKEVENTS
         depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
-                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
-                 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+                 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+                 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
         select USE_GENERIC_SMP_HELPERS
-        select HAVE_ARM_SCU
+        select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
         help
           This enables support for systems with more than one CPU. If you have
           a system with only one CPU, like most personal computers, say N. If
@@ -1229,7 +1281,7 @@ config SMP
 config SMP_ON_UP
         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
         depends on EXPERIMENTAL
-        depends on SMP && !XIP && !THUMB2_KERNEL
+        depends on SMP && !XIP
         default y
         help
           SMP kernels contain instructions which fail on non-SMP processors.
@@ -1248,6 +1300,7 @@ config HAVE_ARM_SCU
 config HAVE_ARM_TWD
         bool
         depends on SMP
+        select TICK_ONESHOT
         help
           This options enables support for the ARM timer and watchdog unit
 
@@ -1283,6 +1336,7 @@ config NR_CPUS
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
         depends on SMP && HOTPLUG && EXPERIMENTAL
+        depends on !ARCH_MSM
         help
           Say Y here to experiment with turning CPUs off and on.  CPUs
           can be controlled through /sys/devices/system/cpu.
@@ -1291,7 +1345,7 @@ config LOCAL_TIMERS
         bool "Use local timer interrupts"
         depends on SMP
         default y
-        select HAVE_ARM_TWD
+        select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
@@ -1310,7 +1364,7 @@ config HZ
         default 100
 
 config THUMB2_KERNEL
-        bool "Compile the kernel in Thumb-2 mode"
+        bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
         depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
         select AEABI
         select ARM_ASM_UNIFIED
@@ -1524,6 +1578,7 @@ config SECCOMP
 
 config CC_STACKPROTECTOR
         bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
         help
           This option turns on the -fstack-protector GCC feature. This
           feature puts, at the beginning of functions, a canary value on
@@ -1650,6 +1705,19 @@ config ATAGS_PROC
           Should the atags used to boot the kernel be exported in an "atags"
           file in procfs. Useful with kexec.
 
+config CRASH_DUMP
+        bool "Build kdump crash kernel (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        help
+          Generate crash dump after being started by kexec. This should
+          be normally only set in special crash dump kernels which are
+          loaded in the main kernel with kexec-tools into a specially
+          reserved region and then later executed after a crash by
+          kdump/kexec. The crash dump kernel must be compiled to a
+          memory address not used by the main kernel
+
+          For more details see Documentation/kdump/kdump.txt
+
 config AUTO_ZRELADDR
         bool "Auto calculation of the decompressed kernel image address"
         depends on !ZBOOT_ROM && !ARCH_U300
@@ -1707,7 +1775,7 @@ config CPU_FREQ_S3C
           Internal configuration node for common cpufreq on Samsung SoC
 
 config CPU_FREQ_S3C24XX
-        bool "CPUfreq driver for Samsung S3C24XX series CPUs"
+        bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
         depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
         select CPU_FREQ_S3C
         help
@@ -1719,7 +1787,7 @@ config CPU_FREQ_S3C24XX
           If in doubt, say N.
 
 config CPU_FREQ_S3C24XX_PLL
-        bool "Support CPUfreq changing of PLL frequency"
+        bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
         depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
         help
           Compile in support for changing the PLL frequency from the
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 2fd0b99afc4b..494224a9b459 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -23,7 +23,7 @@ config STRICT_DEVMEM
 config FRAME_POINTER
         bool
         depends on !THUMB2_KERNEL
-        default y if !ARM_UNWIND
+        default y if !ARM_UNWIND || FUNCTION_GRAPH_TRACER
         help
           If you say N here, the resulting kernel will be slightly smaller and
           faster. However, if neither FRAME_POINTER nor ARM_UNWIND are enabled,
@@ -31,7 +31,7 @@ config FRAME_POINTER
           reported is severely limited.
 
 config ARM_UNWIND
-        bool "Enable stack unwinding support"
+        bool "Enable stack unwinding support (EXPERIMENTAL)"
         depends on AEABI && EXPERIMENTAL
         default y
         help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b87aed028eef..c22c1adfedd6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -154,10 +154,11 @@ machine-$(CONFIG_ARCH_MSM)		:= msm
 machine-$(CONFIG_ARCH_MV78XX0)          := mv78xx0
 machine-$(CONFIG_ARCH_MX1)              := imx
 machine-$(CONFIG_ARCH_MX2)              := imx
-machine-$(CONFIG_ARCH_MX25)             := mx25
+machine-$(CONFIG_ARCH_MX25)             := imx
 machine-$(CONFIG_ARCH_MX3)              := mx3
 machine-$(CONFIG_ARCH_MX5)              := mx5
 machine-$(CONFIG_ARCH_MXC91231)         := mxc91231
+machine-$(CONFIG_ARCH_MXS)              := mxs
 machine-$(CONFIG_ARCH_NETX)             := netx
 machine-$(CONFIG_ARCH_NOMADIK)          := nomadik
 machine-$(CONFIG_ARCH_NS9XXX)           := ns9xxx
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 65a7c1c588a9..0a8f748e506a 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -45,6 +45,10 @@ else
 endif
 endif
 
+ifeq ($(CONFIG_ARCH_SHMOBILE),y)
+OBJS            += head-shmobile.o
+endif
+
 #
 # We now have a PIC decompressor implementation.  Decompressors running
 # from RAM should not define ZTEXTADDR.  Decompressors running directly
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
new file mode 100644
index 000000000000..30973b76e6ae
--- /dev/null
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -0,0 +1,53 @@
+/*
+ * The head-file for SH-Mobile ARM platforms
+ *
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ * Simon Horman <horms@verge.net.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifdef CONFIG_ZBOOT_ROM
+
+        .section        ".start", "ax"
+
+        /* load board-specific initialization code */
+#include <mach/zboot.h>
+
+        b       1f
+__atags:@ tag #1
+        .long   12                      @ tag->hdr.size = tag_size(tag_core);
+        .long   0x54410001              @ tag->hdr.tag = ATAG_CORE;
+        .long   0                       @ tag->u.core.flags = 0;
+        .long   0                       @ tag->u.core.pagesize = 0;
+        .long   0                       @ tag->u.core.rootdev = 0;
+        @ tag #2
+        .long   8                       @ tag->hdr.size = tag_size(tag_mem32);
+        .long   0x54410002              @ tag->hdr.tag = ATAG_MEM;
+        .long   CONFIG_MEMORY_SIZE      @ tag->u.mem.size = CONFIG_MEMORY_SIZE;
+        .long   CONFIG_MEMORY_START     @ @ tag->u.mem.start = CONFIG_MEMORY_START;
+        @ tag #3
+        .long   0                       @ tag->hdr.size = 0
+        .long   0                       @ tag->hdr.tag = ATAG_NONE;
+1:
+
+        /* Set board ID necessary for boot */
+        ldr     r7, 1f                          @ Set machine type register
+        adr     r8, __atags                     @ Set atag register
+        b       2f
+
+1 :     .long MACH_TYPE
+2 :
+
+#endif /* CONFIG_ZBOOT_ROM */
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 0a34c8186924..778655f0257a 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -37,7 +37,3 @@ config SHARP_PARAM
 
 config SHARP_SCOOP
         bool
-
-config COMMON_CLKDEV
-        bool
-        select HAVE_CLK
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e6e8664a9413..e7521bca2c35 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_ARCH_IXP2000)	+= uengine.o
 obj-$(CONFIG_ARCH_IXP23XX)      += uengine.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_COMMON_CLKDEV)     += clkdev.o
+obj-$(CONFIG_ARM_TIMER_SP804)   += timer-sp.o
diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c
deleted file mode 100644
index e2b2bb66e094..000000000000
--- a/arch/arm/common/clkdev.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- *  arch/arm/common/clkdev.c
- *
- *  Copyright (C) 2008 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Helper for the clk API to assist looking up a struct clk.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/mutex.h>
-#include <linux/clk.h>
-#include <linux/slab.h>
-
-#include <asm/clkdev.h>
-#include <mach/clkdev.h>
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-/*
- * Find the correct struct clk for the device and connection ID.
- * We do slightly fuzzy matching here:
- *  An entry with a NULL ID is assumed to be a wildcard.
- *  If an entry has a device ID, it must match
- *  If an entry has a connection ID, it must match
- * Then we take the most specific entry - with the following
- * order of precedence: dev+con > dev only > con only.
- */
-static struct clk *clk_find(const char *dev_id, const char *con_id)
-{
-        struct clk_lookup *p;
-        struct clk *clk = NULL;
-        int match, best = 0;
-
-        list_for_each_entry(p, &clocks, node) {
-                match = 0;
-                if (p->dev_id) {
-                        if (!dev_id || strcmp(p->dev_id, dev_id))
-                                continue;
-                        match += 2;
-                }
-                if (p->con_id) {
-                        if (!con_id || strcmp(p->con_id, con_id))
-                                continue;
-                        match += 1;
-                }
-
-                if (match > best) {
-                        clk = p->clk;
-                        if (match != 3)
-                                best = match;
-                        else
-                                break;
-                }
-        }
-        return clk;
-}
-
-struct clk *clk_get_sys(const char *dev_id, const char *con_id)
-{
-        struct clk *clk;
-
-        mutex_lock(&clocks_mutex);
-        clk = clk_find(dev_id, con_id);
-        if (clk && !__clk_get(clk))
-                clk = NULL;
-        mutex_unlock(&clocks_mutex);
-
-        return clk ? clk : ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get_sys);
-
-struct clk *clk_get(struct device *dev, const char *con_id)
-{
-        const char *dev_id = dev ? dev_name(dev) : NULL;
-
-        return clk_get_sys(dev_id, con_id);
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-        __clk_put(clk);
-}
-EXPORT_SYMBOL(clk_put);
-
-void clkdev_add(struct clk_lookup *cl)
-{
-        mutex_lock(&clocks_mutex);
-        list_add_tail(&cl->node, &clocks);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clkdev_add);
-
-void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
-{
-        mutex_lock(&clocks_mutex);
-        while (num--) {
-                list_add_tail(&cl->node, &clocks);
-                cl++;
-        }
-        mutex_unlock(&clocks_mutex);
-}
-
-#define MAX_DEV_ID      20
-#define MAX_CON_ID      16
-
-struct clk_lookup_alloc {
-        struct clk_lookup cl;
-        char    dev_id[MAX_DEV_ID];
-        char    con_id[MAX_CON_ID];
-};
-
-struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
-        const char *dev_fmt, ...)
-{
-        struct clk_lookup_alloc *cla;
-
-        cla = kzalloc(sizeof(*cla), GFP_KERNEL);
-        if (!cla)
-                return NULL;
-
-        cla->cl.clk = clk;
-        if (con_id) {
-                strlcpy(cla->con_id, con_id, sizeof(cla->con_id));
-                cla->cl.con_id = cla->con_id;
-        }
-
-        if (dev_fmt) {
-                va_list ap;
-
-                va_start(ap, dev_fmt);
-                vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
-                cla->cl.dev_id = cla->dev_id;
-                va_end(ap);
-        }
-
-        return &cla->cl;
-}
-EXPORT_SYMBOL(clkdev_alloc);
-
-int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
-        struct device *dev)
-{
-        struct clk *r = clk_get(dev, id);
-        struct clk_lookup *l;
-
-        if (IS_ERR(r))
-                return PTR_ERR(r);
-
-        l = clkdev_alloc(r, alias, alias_dev_name);
-        clk_put(r);
-        if (!l)
-                return -ENODEV;
-        clkdev_add(l);
-        return 0;
-}
-EXPORT_SYMBOL(clk_add_alias);
-
-/*
- * clkdev_drop - remove a clock dynamically allocated
- */
-void clkdev_drop(struct clk_lookup *cl)
-{
-        mutex_lock(&clocks_mutex);
-        list_del(&cl->node);
-        mutex_unlock(&clocks_mutex);
-        kfree(cl);
-}
-EXPORT_SYMBOL(clkdev_drop);
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index cc0a932bbea9..e5681636626f 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -328,7 +328,7 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
  * substitute the safe buffer for the unsafe one.
  * (basically move the buffer from an unsafe area to a safe one)
  */
-dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
+dma_addr_t __dma_map_single(struct device *dev, void *ptr, size_t size,
                 enum dma_data_direction dir)
 {
         dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n",
@@ -338,7 +338,7 @@ dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
 
         return map_single(dev, ptr, size, dir);
 }
-EXPORT_SYMBOL(dma_map_single);
+EXPORT_SYMBOL(__dma_map_single);
 
 /*
  * see if a mapped address was really a "safe" buffer and if so, copy
@@ -346,7 +346,7 @@ EXPORT_SYMBOL(dma_map_single);
  * the safe buffer.  (basically return things back to the way they
  * should be)
  */
-void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+void __dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
                 enum dma_data_direction dir)
 {
         dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n",
@@ -354,9 +354,9 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
 
         unmap_single(dev, dma_addr, size, dir);
 }
-EXPORT_SYMBOL(dma_unmap_single);
+EXPORT_SYMBOL(__dma_unmap_single);
 
-dma_addr_t dma_map_page(struct device *dev, struct page *page,
+dma_addr_t __dma_map_page(struct device *dev, struct page *page,
                 unsigned long offset, size_t size, enum dma_data_direction dir)
 {
         dev_dbg(dev, "%s(page=%p,off=%#lx,size=%zx,dir=%x)\n",
@@ -372,7 +372,7 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page,
 
         return map_single(dev, page_address(page) + offset, size, dir);
 }
-EXPORT_SYMBOL(dma_map_page);
+EXPORT_SYMBOL(__dma_map_page);
 
 /*
  * see if a mapped address was really a "safe" buffer and if so, copy
@@ -380,7 +380,7 @@ EXPORT_SYMBOL(dma_map_page);
  * the safe buffer.  (basically return things back to the way they
  * should be)
  */
-void dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
+void __dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
                 enum dma_data_direction dir)
 {
         dev_dbg(dev, "%s(ptr=%p,size=%d,dir=%x)\n",
@@ -388,7 +388,7 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
 
         unmap_single(dev, dma_addr, size, dir);
 }
-EXPORT_SYMBOL(dma_unmap_page);
+EXPORT_SYMBOL(__dma_unmap_page);
 
 int dmabounce_sync_for_cpu(struct device *dev, dma_addr_t addr,
                 unsigned long off, size_t sz, enum dma_data_direction dir)
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index e6388dcd8cfa..0b89ef001330 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -35,6 +35,9 @@
 
 static DEFINE_SPINLOCK(irq_controller_lock);
 
+/* Address of GIC 0 CPU interface */
+void __iomem *gic_cpu_base_addr __read_mostly;
+
 struct gic_chip_data {
         unsigned int irq_offset;
         void __iomem *dist_base;
@@ -45,7 +48,7 @@ struct gic_chip_data {
 #define MAX_GIC_NR      1
 #endif
 
-static struct gic_chip_data gic_data[MAX_GIC_NR];
+static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
 
 static inline void __iomem *gic_dist_base(unsigned int irq)
 {
@@ -213,21 +216,16 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
         set_irq_chained_handler(irq, gic_handle_cascade_irq);
 }
 
-void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
-                          unsigned int irq_start)
+static void __init gic_dist_init(struct gic_chip_data *gic,
+        unsigned int irq_start)
 {
         unsigned int gic_irqs, irq_limit, i;
+        void __iomem *base = gic->dist_base;
         u32 cpumask = 1 << smp_processor_id();
 
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
-
         cpumask |= cpumask << 8;
         cpumask |= cpumask << 16;
 
-        gic_data[gic_nr].dist_base = base;
-        gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
-
         writel(0, base + GIC_DIST_CTRL);
 
         /*
@@ -267,7 +265,7 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
         /*
          * Limit number of interrupts registered to the platform maximum
          */
-        irq_limit = gic_data[gic_nr].irq_offset + gic_irqs;
+        irq_limit = gic->irq_offset + gic_irqs;
         if (WARN_ON(irq_limit > NR_IRQS))
                 irq_limit = NR_IRQS;
 
@@ -276,7 +274,7 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
          */
         for (i = irq_start; i < irq_limit; i++) {
                 set_irq_chip(i, &gic_chip);
-                set_irq_chip_data(i, &gic_data[gic_nr]);
+                set_irq_chip_data(i, gic);
                 set_irq_handler(i, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
@@ -284,19 +282,12 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
         writel(1, base + GIC_DIST_CTRL);
 }
 
-void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
+static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
 {
-        void __iomem *dist_base;
+        void __iomem *dist_base = gic->dist_base;
+        void __iomem *base = gic->cpu_base;
         int i;
 
-        if (gic_nr >= MAX_GIC_NR)
-                BUG();
-
-        dist_base = gic_data[gic_nr].dist_base;
-        BUG_ON(!dist_base);
-
-        gic_data[gic_nr].cpu_base = base;
-
         /*
          * Deal with the banked PPI and SGI interrupts - disable all
          * PPI interrupts, ensure all SGI interrupts are enabled.
@@ -314,6 +305,42 @@ void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
         writel(1, base + GIC_CPU_CTRL);
 }
 
+void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
+        void __iomem *dist_base, void __iomem *cpu_base)
+{
+        struct gic_chip_data *gic;
+
+        BUG_ON(gic_nr >= MAX_GIC_NR);
+
+        gic = &gic_data[gic_nr];
+        gic->dist_base = dist_base;
+        gic->cpu_base = cpu_base;
+        gic->irq_offset = (irq_start - 1) & ~31;
+
+        if (gic_nr == 0)
+                gic_cpu_base_addr = cpu_base;
+
+        gic_dist_init(gic, irq_start);
+        gic_cpu_init(gic);
+}
+
+void __cpuinit gic_secondary_init(unsigned int gic_nr)
+{
+        BUG_ON(gic_nr >= MAX_GIC_NR);
+
+        gic_cpu_init(&gic_data[gic_nr]);
+}
+
+void __cpuinit gic_enable_ppi(unsigned int irq)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        irq_to_desc(irq)->status |= IRQ_NOPROBE;
+        gic_unmask_irq(irq);
+        local_irq_restore(flags);
+}
+
 #ifdef CONFIG_SMP
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 {
diff --git a/arch/arm/plat-versatile/timer-sp.c b/arch/arm/common/timer-sp.c
index fb0d1c299718..6ef3342153b9 100644
--- a/arch/arm/plat-versatile/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/plat-versatile/timer-sp.c
+ *  linux/arch/arm/common/timer-sp.c
  *
  *  Copyright (C) 1999 - 2003 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd
@@ -26,8 +26,6 @@
 
 #include <asm/hardware/arm_timer.h>
 
-#include <plat/timer-sp.h>
-
 /*
  * These timers are currently always setup to be clocked at 1MHz.
  */
@@ -46,7 +44,6 @@ static struct clocksource clocksource_sp804 = {
         .rating         = 200,
         .read           = sp804_read,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -63,8 +60,7 @@ void __init sp804_clocksource_init(void __iomem *base)
         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
                 clksrc_base + TIMER_CTRL);
 
-        cs->mult = clocksource_khz2mult(TIMER_FREQ_KHZ, cs->shift);
-        clocksource_register(cs);
+        clocksource_register_khz(cs, TIMER_FREQ_KHZ);
 }
 
 
diff --git a/arch/arm/configs/ag5evm_defconfig b/arch/arm/configs/ag5evm_defconfig
new file mode 100644
index 000000000000..2b9cf56db363
--- /dev/null
+++ b/arch/arm/configs/ag5evm_defconfig
@@ -0,0 +1,83 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SH73A0=y
+CONFIG_MACH_AG5EVM=y
+CONFIG_MEMORY_SIZE=0x10000000
+CONFIG_CPU_BPREDICT_DISABLE=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_458693=y
+CONFIG_NO_HZ=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=tty0 console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM=y
+# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMSC911X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_SPARSEKMAP=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=9
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_SH_MOBILE=y
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+CONFIG_FB=y
+CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/ams_delta_defconfig b/arch/arm/configs/ams_delta_defconfig
deleted file mode 100644
index 75de45e949b9..000000000000
--- a/arch/arm/configs/ams_delta_defconfig
+++ /dev/null
@@ -1,121 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_TREE_PREEMPT_RCU=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_KALLSYMS is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_LBDAF is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_MBOX_FWK=m
-CONFIG_MACH_AMS_DELTA=y
-CONFIG_OMAP_ARM_150MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=/dev/ram0 initrd=0x11c00000,4M"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-# CONFIG_SUSPEND is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IPV6=y
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_AMS_DELTA=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_CATC=y
-CONFIG_USB_KAWETH=y
-CONFIG_USB_PEGASUS=y
-CONFIG_USB_RTL8150=y
-CONFIG_USB_USBNET=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_OMAP=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_6x11=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_OMAP_SOC=y
-CONFIG_SND_OMAP_SOC_AMS_DELTA=y
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_AMS_DELTA=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_NFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/arm/configs/htcherald_defconfig b/arch/arm/configs/htcherald_defconfig
deleted file mode 100644
index edfa1c0daab0..000000000000
--- a/arch/arm/configs/htcherald_defconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_ARCH_OMAP850=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_MACH_HERALD=y
-CONFIG_OMAP_ARM_195MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-CONFIG_CPU_ARM925T=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200 ip=dhcp"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=m
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_ZLIB=y
-CONFIG_CRYPTO_LZO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
new file mode 100644
index 000000000000..306a2e2d3622
--- /dev/null
+++ b/arch/arm/configs/mackerel_defconfig
@@ -0,0 +1,138 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_SH7372=y
+CONFIG_MACH_MACKEREL=y
+CONFIG_MEMORY_SIZE=0x10000000
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_FORCE_MAX_ZONEORDER=15
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp memchunk.vpu=64m memchunk.veu0=8m memchunk.spu0=2m mem=240m"
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_ARM_INTEGRATOR=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMSC911X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=8
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+CONFIG_FB=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_CLUT224 is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
index f0c339fd5d21..e648ea3429be 100644
--- a/arch/arm/configs/mx3_defconfig
+++ b/arch/arm/configs/mx3_defconfig
@@ -84,6 +84,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_IMX=y
+CONFIG_SPI=y
 CONFIG_W1=y
 CONFIG_W1_MASTER_MXC=y
 CONFIG_W1_SLAVE_THERM=y
diff --git a/arch/arm/configs/n770_defconfig b/arch/arm/configs/n770_defconfig
deleted file mode 100644
index 993e94df5d0e..000000000000
--- a/arch/arm/configs/n770_defconfig
+++ /dev/null
@@ -1,138 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_RESET_CLOCKS=y
-# CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_MBOX_FWK=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_NOKIA770=y
-CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
-CONFIG_OMAP_ARM_216MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=1f03 rootfstype=jffs2 time"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_HIDP=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_CONNECTOR=y
-# CONFIG_PROC_EVENTS is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_SCSI=y
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_TUN=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_USBNET=y
-# CONFIG_USB_NET_AX8817X is not set
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_PPP=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP_UWIRE=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_OMAP_WATCHDOG=y
-CONFIG_FB=y
-CONFIG_FB_OMAP=y
-CONFIG_FB_OMAP_LCDC_EXTERNAL=y
-CONFIG_FB_OMAP_LCDC_HWA742=y
-CONFIG_FB_OMAP_MANUAL_UPDATE=y
-CONFIG_FB_OMAP_LCD_MIPID=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-CONFIG_SND_DUMMY=y
-CONFIG_SND_USB_AUDIO=y
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_SUSPEND=y
-CONFIG_USB_OTG=y
-# CONFIG_USB_OTG_WHITELIST is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_CONSOLE=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_FILE_STORAGE_TEST=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_SECURITY=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
new file mode 100644
index 000000000000..a350cc6bfe6a
--- /dev/null
+++ b/arch/arm/configs/omap1_defconfig
@@ -0,0 +1,286 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_IKCONFIG=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_ELF_CORE is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_SHMEM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLOB=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP1=y
+CONFIG_OMAP_RESET_CLOCKS=y
+# CONFIG_OMAP_MUX is not set
+CONFIG_OMAP_MBOX_FWK=y
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_ARCH_OMAP730=y
+CONFIG_ARCH_OMAP850=y
+CONFIG_ARCH_OMAP16XX=y
+CONFIG_MACH_OMAP_INNOVATOR=y
+CONFIG_MACH_OMAP_H2=y
+CONFIG_MACH_OMAP_H3=y
+CONFIG_MACH_OMAP_HTCWIZARD=y
+CONFIG_MACH_HERALD=y
+CONFIG_MACH_OMAP_OSK=y
+CONFIG_MACH_OMAP_PERSEUS2=y
+CONFIG_MACH_OMAP_FSAMPLE=y
+CONFIG_MACH_VOICEBLUE=y
+CONFIG_MACH_OMAP_PALMTE=y
+CONFIG_MACH_OMAP_PALMZ71=y
+CONFIG_MACH_OMAP_PALMTT=y
+CONFIG_MACH_SX1=y
+CONFIG_MACH_NOKIA770=y
+CONFIG_MACH_AMS_DELTA=y
+CONFIG_MACH_OMAP_GENERIC=y
+CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
+CONFIG_OMAP_ARM_216MHZ=y
+CONFIG_OMAP_ARM_195MHZ=y
+CONFIG_OMAP_ARM_192MHZ=y
+CONFIG_OMAP_ARM_182MHZ=y
+CONFIG_OMAP_ARM_168MHZ=y
+# CONFIG_OMAP_ARM_60MHZ is not set
+# CONFIG_ARM_THUMB is not set
+CONFIG_PCCARD=y
+CONFIG_OMAP_CF=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_LEDS=y
+CONFIG_LEDS_CPU=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=1f03 rootfstype=jffs2"
+CONFIG_FPE_NWFPE=y
+CONFIG_BINFMT_MISC=y
+CONFIG_PM=y
+# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+CONFIG_NETFILTER=y
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_HIDP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_CONNECTOR=y
+# CONFIG_PROC_EVENTS is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=3
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_NAND=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_IDE=m
+CONFIG_BLK_DEV_IDECS=m
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_PHYLIB=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMC91X=y
+CONFIG_USB_CATC=y
+CONFIG_USB_KAWETH=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_RTL8150=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+CONFIG_PPP=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_SLIP=y
+CONFIG_SLIP_COMPRESSED=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_OMAP_UWIRE=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_OMAP_WATCHDOG=y
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_VIRTUAL=y
+CONFIG_FB_OMAP=y
+CONFIG_FB_OMAP_LCDC_EXTERNAL=y
+CONFIG_FB_OMAP_LCDC_HWA742=y
+CONFIG_FB_OMAP_MANUAL_UPDATE=y
+CONFIG_FB_OMAP_LCD_MIPID=y
+CONFIG_FB_OMAP_BOOTLOADER_INIT=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_6x11=y
+CONFIG_FONT_MINI_4x6=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+CONFIG_SND_DUMMY=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_SND_OMAP_SOC=y
+# CONFIG_USB_HID is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_TEST=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETH=m
+# CONFIG_USB_ETH_RNDIS is not set
+CONFIG_USB_FILE_STORAGE=m
+CONFIG_USB_FILE_STORAGE_TEST=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_OMAP=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_OMAP=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=866
+CONFIG_FAT_DEFAULT_IOCHARSET="koi8-r"
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_CRAMFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_UTF8=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+CONFIG_SECURITY=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_ZLIB=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/omap_generic_1510_defconfig b/arch/arm/configs/omap_generic_1510_defconfig
deleted file mode 100644
index 0e42ba4ede9d..000000000000
--- a/arch/arm/configs/omap_generic_1510_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_OMAP_ARM_168MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS2,115200 root=0803 ro init=/bin/sh"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_RTL8150=y
-CONFIG_USB_USBNET=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/arm/configs/omap_generic_1610_defconfig b/arch/arm/configs/omap_generic_1610_defconfig
deleted file mode 100644
index 5e536cf0f9f7..000000000000
--- a/arch/arm/configs/omap_generic_1610_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_OMAP_ARM_192MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS2,115200 root=0803 ro init=/bin/sh"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_RTL8150=y
-CONFIG_USB_USBNET=y
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/arm/configs/omap_generic_1710_defconfig b/arch/arm/configs/omap_generic_1710_defconfig
deleted file mode 100644
index c0867b1d9815..000000000000
--- a/arch/arm/configs/omap_generic_1710_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-# CONFIG_OMAP_MUX is not set
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_OMAP_ARM_192MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=tty0 console=ttyS2,115200 root=0801"
-CONFIG_FPE_NWFPE=y
-CONFIG_ARTHUR=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_USBNET=y
-CONFIG_USB_ALI_M5632=y
-# CONFIG_USB_BELKIN is not set
-# CONFIG_USB_ARMLINUX is not set
-CONFIG_PPP=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_VIDEO_OUTPUT_CONTROL=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_PCBC=y
diff --git a/arch/arm/configs/omap_h2_1610_defconfig b/arch/arm/configs/omap_h2_1610_defconfig
deleted file mode 100644
index e2de2aa17e62..000000000000
--- a/arch/arm/configs/omap_h2_1610_defconfig
+++ /dev/null
@@ -1,109 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_MUX_DEBUG=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_OMAP_DM_TIMER=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_H2=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200n8 root=/dev/ram0 rw initrd=0x10600000,8M ramdisk_size=8192"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_PM_RUNTIME=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEBUG_DRIVER=y
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=3
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_PPP=y
-CONFIG_SLIP=y
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_EVBUG=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_I2C_OMAP=y
-CONFIG_SPI=y
-CONFIG_SPI_OMAP_UWIRE=y
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_SUSPEND=y
-CONFIG_USB_OTG=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_TEST=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
diff --git a/arch/arm/configs/omap_innovator_1510_defconfig b/arch/arm/configs/omap_innovator_1510_defconfig
deleted file mode 100644
index 265af2669ede..000000000000
--- a/arch/arm/configs/omap_innovator_1510_defconfig
+++ /dev/null
@@ -1,102 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_MACH_OMAP_INNOVATOR=y
-CONFIG_OMAP_ARM_168MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-CONFIG_PREEMPT=y
-CONFIG_LEDS=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200n8 root=/dev/nfs ip=bootp noinitrd"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_ST=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_USB_RTL8150=y
-CONFIG_USB_USBNET=y
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_ASYNC=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_I2C=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
diff --git a/arch/arm/configs/omap_innovator_1610_defconfig b/arch/arm/configs/omap_innovator_1610_defconfig
deleted file mode 100644
index cc7fbf84ddd9..000000000000
--- a/arch/arm/configs/omap_innovator_1610_defconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_INNOVATOR=y
-CONFIG_OMAP_ARM_192MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_CPU_DCACHE_WRITETHROUGH=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=tty0 console=ttyS0,115200 initrd=0x10200000,8M root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
diff --git a/arch/arm/configs/omap_osk_5912_defconfig b/arch/arm/configs/omap_osk_5912_defconfig
deleted file mode 100644
index 9105de7661f9..000000000000
--- a/arch/arm/configs/omap_osk_5912_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_RESET_CLOCKS=y
-CONFIG_OMAP_32K_TIMER=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_ARCH_OMAP16XX=y
-CONFIG_MACH_OMAP_OSK=y
-CONFIG_OMAP_ARM_192MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_PCCARD=y
-CONFIG_OMAP_CF=y
-CONFIG_NO_HZ=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x10400000,8M root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_IDE=m
-CONFIG_BLK_DEV_IDECS=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-CONFIG_PPP=y
-CONFIG_PPP_MULTILINK=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_ISO8859_1=m
diff --git a/arch/arm/configs/omap_perseus2_730_defconfig b/arch/arm/configs/omap_perseus2_730_defconfig
deleted file mode 100644
index aa777e624e23..000000000000
--- a/arch/arm/configs/omap_perseus2_730_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_ARCH_OMAP730=y
-# CONFIG_ARCH_OMAP15XX is not set
-CONFIG_MACH_OMAP_PERSEUS2=y
-CONFIG_OMAP_ARM_182MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_PREEMPT=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=ttyS0,115200 ip=dhcp"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_NAND=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMC91X=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=m
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_VIRTUAL=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
diff --git a/arch/arm/configs/palmte_defconfig b/arch/arm/configs/palmte_defconfig
deleted file mode 100644
index 828d7cb9e667..000000000000
--- a/arch/arm/configs/palmte_defconfig
+++ /dev/null
@@ -1,48 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_MACH_OMAP_PALMTE=y
-CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_OMAP=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_USB_GADGET=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=850
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/palmtt_defconfig b/arch/arm/configs/palmtt_defconfig
deleted file mode 100644
index 31d02c48a3d9..000000000000
--- a/arch/arm/configs/palmtt_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_MACH_OMAP_PALMTT=y
-CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/mmcblk0p2 rw init=/init"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SPI=y
-CONFIG_SPI_OMAP_UWIRE=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_OMAP=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/palmz71_defconfig b/arch/arm/configs/palmz71_defconfig
deleted file mode 100644
index c478db6f5192..000000000000
--- a/arch/arm/configs/palmz71_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="-z71"
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_SLAB=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_MACH_OMAP_PALMZ71=y
-CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_ARM_THUMB is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=16
-CONFIG_SPI=y
-CONFIG_SPI_OMAP_UWIRE=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-CONFIG_FB_OMAP=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/sx1_defconfig b/arch/arm/configs/sx1_defconfig
deleted file mode 100644
index 20a861877a33..000000000000
--- a/arch/arm/configs/sx1_defconfig
+++ /dev/null
@@ -1,110 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EMBEDDED=y
-# CONFIG_KALLSYMS is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_BASE_FULL is not set
-# CONFIG_SHMEM is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_SLOB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP1=y
-CONFIG_OMAP_MBOX_FWK=y
-CONFIG_MACH_SX1=y
-CONFIG_OMAP_ARM_168MHZ=y
-# CONFIG_OMAP_ARM_60MHZ is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_CONNECTOR=y
-# CONFIG_PROC_EVENTS is not set
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_RAM=m
-CONFIG_BLK_DEV_RAM_COUNT=2
-CONFIG_NETDEVICES=y
-CONFIG_PHYLIB=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_OMAP=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_OMAP=y
-CONFIG_FB_OMAP_BOOTLOADER_INIT=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_MMC=y
-CONFIG_MMC_OMAP=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=866
-CONFIG_FAT_DEFAULT_IOCHARSET="koi8-r"
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_CODEPAGE_1251=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_5=y
-CONFIG_NLS_KOI8_R=y
-CONFIG_NLS_UTF8=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index be80f037f85a..52d86c4485bf 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -9,6 +9,10 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_U8500=y
+CONFIG_UX500_SOC_DB5500=y
+CONFIG_UX500_SOC_DB8500=y
+CONFIG_MACH_U8500=y
+CONFIG_MACH_U5500=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
 CONFIG_PREEMPT=y
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 749bb6622404..bc2d2d75f706 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -18,6 +18,7 @@
 #endif
 
 #include <asm/ptrace.h>
+#include <asm/domain.h>
 
 /*
  * Endian independent macros for shifting bytes within registers.
@@ -157,16 +158,24 @@
 #ifdef CONFIG_SMP
 #define ALT_SMP(instr...)                                       \
 9998:   instr
+/*
+ * Note: if you get assembler errors from ALT_UP() when building with
+ * CONFIG_THUMB2_KERNEL, you almost certainly need to use
+ * ALT_SMP( W(instr) ... )
+ */
 #define ALT_UP(instr...)                                        \
         .pushsection ".alt.smp.init", "a"                       ;\
         .long   9998b                                           ;\
-        instr                                                   ;\
+9997:   instr                                                   ;\
+        .if . - 9997b != 4                                      ;\
+                .error "ALT_UP() content must assemble to exactly 4 bytes";\
+        .endif                                                  ;\
         .popsection
 #define ALT_UP_B(label)                                 \
         .equ    up_b_offset, label - 9998b                      ;\
         .pushsection ".alt.smp.init", "a"                       ;\
         .long   9998b                                           ;\
-        b       . + up_b_offset                                 ;\
+        W(b)    . + up_b_offset                                 ;\
         .popsection
 #else
 #define ALT_SMP(instr...)
@@ -177,16 +186,24 @@
 /*
  * SMP data memory barrier
  */
-        .macro  smp_dmb
+        .macro  smp_dmb mode
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
+        .ifeqs "\mode","arm"
         ALT_SMP(dmb)
+        .else
+        ALT_SMP(W(dmb))
+        .endif
 #elif __LINUX_ARM_ARCH__ == 6
         ALT_SMP(mcr     p15, 0, r0, c7, c10, 5) @ dmb
 #else
 #error Incompatible SMP platform
 #endif
+        .ifeqs "\mode","arm"
         ALT_UP(nop)
+        .else
+        ALT_UP(W(nop))
+        .endif
 #endif
         .endm
 
@@ -206,12 +223,12 @@
  */
 #ifdef CONFIG_THUMB2_KERNEL
 
-        .macro  usraccoff, instr, reg, ptr, inc, off, cond, abort
+        .macro  usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()
 9999:
         .if     \inc == 1
-        \instr\cond\()bt \reg, [\ptr, #\off]
+        \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
         .elseif \inc == 4
-        \instr\cond\()t \reg, [\ptr, #\off]
+        \instr\cond\()\t\().w \reg, [\ptr, #\off]
         .else
         .error  "Unsupported inc macro argument"
         .endif
@@ -246,13 +263,13 @@
 
 #else   /* !CONFIG_THUMB2_KERNEL */
 
-        .macro  usracc, instr, reg, ptr, inc, cond, rept, abort
+        .macro  usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()
         .rept   \rept
 9999:
         .if     \inc == 1
-        \instr\cond\()bt \reg, [\ptr], #\inc
+        \instr\cond\()b\()\t \reg, [\ptr], #\inc
         .elseif \inc == 4
-        \instr\cond\()t \reg, [\ptr], #\inc
+        \instr\cond\()\t \reg, [\ptr], #\inc
         .else
         .error  "Unsupported inc macro argument"
         .endif
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 9d6122096fbe..75fe66bc02b4 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -23,4 +23,6 @@
 #define ARCH_SLAB_MINALIGN 8
 #endif
 
+#define __read_mostly __attribute__((__section__(".data..read_mostly")))
+
 #endif
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h
index b56c1389b6fa..765d33222369 100644
--- a/arch/arm/include/asm/clkdev.h
+++ b/arch/arm/include/asm/clkdev.h
@@ -12,23 +12,13 @@
 #ifndef __ASM_CLKDEV_H
 #define __ASM_CLKDEV_H
 
-struct clk;
-struct device;
+#include <linux/slab.h>
 
-struct clk_lookup {
-        struct list_head        node;
-        const char              *dev_id;
-        const char              *con_id;
-        struct clk              *clk;
-};
+#include <mach/clkdev.h>
 
-struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
-        const char *dev_fmt, ...);
-
-void clkdev_add(struct clk_lookup *cl);
-void clkdev_drop(struct clk_lookup *cl);
-
-void clkdev_add_table(struct clk_lookup *, size_t);
-int clk_add_alias(const char *, const char *, char *, struct device *);
+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
+{
+        return kzalloc(size, GFP_KERNEL);
+}
 
 #endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index c568da7dcae4..4fff837363ed 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -5,24 +5,29 @@
 
 #include <linux/mm_types.h>
 #include <linux/scatterlist.h>
+#include <linux/dma-debug.h>
 
 #include <asm-generic/dma-coherent.h>
 #include <asm/memory.h>
 
+#ifdef __arch_page_to_dma
+#error Please update to __arch_pfn_to_dma
+#endif
+
 /*
- * page_to_dma/dma_to_virt/virt_to_dma are architecture private functions
- * used internally by the DMA-mapping API to provide DMA addresses. They
- * must not be used by drivers.
+ * dma_to_pfn/pfn_to_dma/dma_to_virt/virt_to_dma are architecture private
+ * functions used internally by the DMA-mapping API to provide DMA
+ * addresses. They must not be used by drivers.
  */
-#ifndef __arch_page_to_dma
-static inline dma_addr_t page_to_dma(struct device *dev, struct page *page)
+#ifndef __arch_pfn_to_dma
+static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
 {
-        return (dma_addr_t)__pfn_to_bus(page_to_pfn(page));
+        return (dma_addr_t)__pfn_to_bus(pfn);
 }
 
-static inline struct page *dma_to_page(struct device *dev, dma_addr_t addr)
+static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
 {
-        return pfn_to_page(__bus_to_pfn(addr));
+        return __bus_to_pfn(addr);
 }
 
 static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
@@ -35,14 +40,14 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
         return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
 }
 #else
-static inline dma_addr_t page_to_dma(struct device *dev, struct page *page)
+static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
 {
-        return __arch_page_to_dma(dev, page);
+        return __arch_pfn_to_dma(dev, pfn);
 }
 
-static inline struct page *dma_to_page(struct device *dev, dma_addr_t addr)
+static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
 {
-        return __arch_dma_to_page(dev, addr);
+        return __arch_dma_to_pfn(dev, addr);
 }
 
 static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
@@ -293,13 +298,13 @@ extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
 /*
  * The DMA API, implemented by dmabounce.c.  See below for descriptions.
  */
-extern dma_addr_t dma_map_single(struct device *, void *, size_t,
+extern dma_addr_t __dma_map_single(struct device *, void *, size_t,
                 enum dma_data_direction);
-extern void dma_unmap_single(struct device *, dma_addr_t, size_t,
+extern void __dma_unmap_single(struct device *, dma_addr_t, size_t,
                 enum dma_data_direction);
-extern dma_addr_t dma_map_page(struct device *, struct page *,
+extern dma_addr_t __dma_map_page(struct device *, struct page *,
                 unsigned long, size_t, enum dma_data_direction);
-extern void dma_unmap_page(struct device *, dma_addr_t, size_t,
+extern void __dma_unmap_page(struct device *, dma_addr_t, size_t,
                 enum dma_data_direction);
 
 /*
@@ -323,6 +328,34 @@ static inline int dmabounce_sync_for_device(struct device *d, dma_addr_t addr,
 }
 
 
+static inline dma_addr_t __dma_map_single(struct device *dev, void *cpu_addr,
+                size_t size, enum dma_data_direction dir)
+{
+        __dma_single_cpu_to_dev(cpu_addr, size, dir);
+        return virt_to_dma(dev, cpu_addr);
+}
+
+static inline dma_addr_t __dma_map_page(struct device *dev, struct page *page,
+             unsigned long offset, size_t size, enum dma_data_direction dir)
+{
+        __dma_page_cpu_to_dev(page, offset, size, dir);
+        return pfn_to_dma(dev, page_to_pfn(page)) + offset;
+}
+
+static inline void __dma_unmap_single(struct device *dev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir)
+{
+        __dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir);
+}
+
+static inline void __dma_unmap_page(struct device *dev, dma_addr_t handle,
+                size_t size, enum dma_data_direction dir)
+{
+        __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
+                handle & ~PAGE_MASK, size, dir);
+}
+#endif /* CONFIG_DMABOUNCE */
+
 /**
  * dma_map_single - map a single buffer for streaming DMA
  * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
@@ -340,11 +373,16 @@ static inline int dmabounce_sync_for_device(struct device *d, dma_addr_t addr,
 static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
                 size_t size, enum dma_data_direction dir)
 {
+        dma_addr_t addr;
+
         BUG_ON(!valid_dma_direction(dir));
 
-        __dma_single_cpu_to_dev(cpu_addr, size, dir);
+        addr = __dma_map_single(dev, cpu_addr, size, dir);
+        debug_dma_map_page(dev, virt_to_page(cpu_addr),
+                        (unsigned long)cpu_addr & ~PAGE_MASK, size,
+                        dir, addr, true);
 
-        return virt_to_dma(dev, cpu_addr);
+        return addr;
 }
 
 /**
@@ -364,11 +402,14 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
 static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
              unsigned long offset, size_t size, enum dma_data_direction dir)
 {
+        dma_addr_t addr;
+
         BUG_ON(!valid_dma_direction(dir));
 
-        __dma_page_cpu_to_dev(page, offset, size, dir);
+        addr = __dma_map_page(dev, page, offset, size, dir);
+        debug_dma_map_page(dev, page, offset, size, dir, addr, false);
 
-        return page_to_dma(dev, page) + offset;
+        return addr;
 }
 
 /**
@@ -388,7 +429,8 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
 static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
                 size_t size, enum dma_data_direction dir)
 {
-        __dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir);
+        debug_dma_unmap_page(dev, handle, size, dir, true);
+        __dma_unmap_single(dev, handle, size, dir);
 }
 
 /**
@@ -408,10 +450,9 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
 static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
                 size_t size, enum dma_data_direction dir)
 {
-        __dma_page_dev_to_cpu(dma_to_page(dev, handle), handle & ~PAGE_MASK,
-                size, dir);
+        debug_dma_unmap_page(dev, handle, size, dir, false);
+        __dma_unmap_page(dev, handle, size, dir);
 }
-#endif /* CONFIG_DMABOUNCE */
 
 /**
  * dma_sync_single_range_for_cpu
@@ -437,6 +478,8 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev,
 {
         BUG_ON(!valid_dma_direction(dir));
 
+        debug_dma_sync_single_for_cpu(dev, handle + offset, size, dir);
+
         if (!dmabounce_sync_for_cpu(dev, handle, offset, size, dir))
                 return;
 
@@ -449,6 +492,8 @@ static inline void dma_sync_single_range_for_device(struct device *dev,
 {
         BUG_ON(!valid_dma_direction(dir));
 
+        debug_dma_sync_single_for_device(dev, handle + offset, size, dir);
+
         if (!dmabounce_sync_for_device(dev, handle, offset, size, dir))
                 return;
 
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index cc7ef4080711..af18ceaacf5d 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -45,13 +45,17 @@
  */
 #define DOMAIN_NOACCESS 0
 #define DOMAIN_CLIENT   1
+#ifdef CONFIG_CPU_USE_DOMAINS
 #define DOMAIN_MANAGER  3
+#else
+#define DOMAIN_MANAGER  1
+#endif
 
 #define domain_val(dom,type)    ((type) << (2*(dom)))
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
 #define set_domain(x)                                   \
         do {                                            \
         __asm__ __volatile__(                           \
@@ -74,5 +78,28 @@
 #define modify_domain(dom,type) do { } while (0)
 #endif
 
+/*
+ * Generate the T (user) versions of the LDR/STR and related
+ * instructions (inline assembly)
+ */
+#ifdef CONFIG_CPU_USE_DOMAINS
+#define T(instr)        #instr "t"
+#else
+#define T(instr)        #instr
 #endif
-#endif /* !__ASSEMBLY__ */
+
+#else /* __ASSEMBLY__ */
+
+/*
+ * Generate the T (user) versions of the LDR/STR and related
+ * instructions
+ */
+#ifdef CONFIG_CPU_USE_DOMAINS
+#define T(instr)        instr ## t
+#else
+#define T(instr)        instr
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* !__ASM_PROC_DOMAIN_H */
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 8bb66bca2e3e..c3cd8755e648 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -99,6 +99,8 @@ struct elf32_hdr;
 extern int elf_check_arch(const struct elf32_hdr *);
 #define elf_check_arch elf_check_arch
 
+#define vmcore_elf64_check_arch(x) (0)
+
 extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int);
 #define elf_read_implies_exec(ex,stk) arm_elf_read_implies_exec(&(ex), stk)
 
diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S
new file mode 100644
index 000000000000..ec0bbf79c71f
--- /dev/null
+++ b/arch/arm/include/asm/entry-macro-multi.S
@@ -0,0 +1,44 @@
+/*
+ * Interrupt handling.  Preserves r7, r8, r9
+ */
+        .macro  arch_irq_handler_default
+        get_irqnr_preamble r5, lr
+1:      get_irqnr_and_base r0, r6, r5, lr
+        movne   r1, sp
+        @
+        @ routine called with r0 = irq number, r1 = struct pt_regs *
+        @
+        adrne   lr, BSYM(1b)
+        bne     asm_do_IRQ
+
+#ifdef CONFIG_SMP
+        /*
+         * XXX
+         *
+         * this macro assumes that irqstat (r6) and base (r5) are
+         * preserved from get_irqnr_and_base above
+         */
+        ALT_SMP(test_for_ipi r0, r6, r5, lr)
+        ALT_UP_B(9997f)
+        movne   r1, sp
+        adrne   lr, BSYM(1b)
+        bne     do_IPI
+
+#ifdef CONFIG_LOCAL_TIMERS
+        test_for_ltirq r0, r6, r5, lr
+        movne   r0, sp
+        adrne   lr, BSYM(1b)
+        bne     do_local_timer
+#endif
+#endif
+9997:
+        .endm
+
+        .macro  arch_irq_handler, symbol_name
+        .align  5
+        .global \symbol_name
+\symbol_name:
+        mov     r4, lr
+        arch_irq_handler_default
+        mov     pc, r4
+        .endm
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 540a044153a5..b33fe7065b38 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -13,12 +13,13 @@
 #include <linux/preempt.h>
 #include <linux/uaccess.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)      \
         __asm__ __volatile__(                                   \
-        "1:     ldrt    %1, [%2]\n"                             \
+        "1:     " T(ldr) "      %1, [%2]\n"                     \
         "       " insn "\n"                                     \
-        "2:     strt    %0, [%2]\n"                             \
+        "2:     " T(str) "      %0, [%2]\n"                     \
         "       mov     %0, #0\n"                               \
         "3:\n"                                                  \
         "       .pushsection __ex_table,\"a\"\n"                \
@@ -97,10 +98,10 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
         pagefault_disable();    /* implies preempt_disable() */
 
         __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
-        "1:     ldrt    %0, [%3]\n"
+        "1:     " T(ldr) "      %0, [%3]\n"
         "       teq     %0, %1\n"
         "       it      eq      @ explicit IT needed for the 2b label\n"
-        "2:     streqt  %2, [%3]\n"
+        "2:     " T(streq) "    %2, [%3]\n"
         "3:\n"
         "       .pushsection __ex_table,\"a\"\n"
         "       .align  3\n"
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 6d7485aff955..89ad1805e579 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -5,13 +5,31 @@
 #include <linux/threads.h>
 #include <asm/irq.h>
 
+#define NR_IPI  5
+
 typedef struct {
         unsigned int __softirq_pending;
+#ifdef CONFIG_LOCAL_TIMERS
         unsigned int local_timer_irqs;
+#endif
+#ifdef CONFIG_SMP
+        unsigned int ipi_irqs[NR_IPI];
+#endif
 } ____cacheline_aligned irq_cpustat_t;
 
 #include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
 
+#define __inc_irq_stat(cpu, member)     __IRQ_STAT(cpu, member)++
+#define __get_irq_stat(cpu, member)     __IRQ_STAT(cpu, member)
+
+#ifdef CONFIG_SMP
+u64 smp_irq_stat_cpu(unsigned int cpu);
+#else
+#define smp_irq_stat_cpu(cpu)   0
+#endif
+
+#define arch_irq_stat_cpu       smp_irq_stat_cpu
+
 #if NR_IRQS > 512
 #define HARDIRQ_BITS    10
 #elif NR_IRQS > 256
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index cc42d5fdee17..5aeec1e1735c 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -59,7 +59,17 @@
 #define L2X0_CACHE_ID_PART_MASK         (0xf << 6)
 #define L2X0_CACHE_ID_PART_L210         (1 << 6)
 #define L2X0_CACHE_ID_PART_L310         (3 << 6)
-#define L2X0_AUX_CTRL_WAY_SIZE_MASK     (0x3 << 17)
+
+#define L2X0_AUX_CTRL_MASK                      0xc0000fff
+#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT       16
+#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT            17
+#define L2X0_AUX_CTRL_WAY_SIZE_MASK             (0x3 << 17)
+#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT      22
+#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT         26
+#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT         27
+#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT       28
+#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT      29
+#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT         30
 
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
new file mode 100644
index 000000000000..c115b82fe80a
--- /dev/null
+++ b/arch/arm/include/asm/hardware/entry-macro-gic.S
@@ -0,0 +1,75 @@
+/*
+ * arch/arm/include/asm/hardware/entry-macro-gic.S
+ *
+ * Low-level IRQ helper macros for GIC
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/hardware/gic.h>
+
+#ifndef HAVE_GET_IRQNR_PREAMBLE
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =gic_cpu_base_addr
+        ldr     \base, [\base]
+        .endm
+#endif
+
+/*
+ * The interrupt numbering scheme is defined in the
+ * interrupt controller spec.  To wit:
+ *
+ * Interrupts 0-15 are IPI
+ * 16-28 are reserved
+ * 29-31 are local.  We allow 30 to be used for the watchdog.
+ * 32-1020 are global
+ * 1021-1022 are reserved
+ * 1023 is "spurious" (no interrupt)
+ *
+ * For now, we ignore all local interrupts so only return an interrupt if it's
+ * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+ *
+ * A simple read from the controller will tell us the number of the highest
+ * priority enabled interrupt.  We then just need to check whether it is in the
+ * valid range for an IRQ (30-1020 inclusive).
+ */
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+        ldr     \irqstat, [\base, #GIC_CPU_INTACK]
+        /* bits 12-10 = src CPU, 9-0 = int # */
+
+        ldr     \tmp, =1021
+        bic     \irqnr, \irqstat, #0x1c00
+        cmp     \irqnr, #29
+        cmpcc   \irqnr, \irqnr
+        cmpne   \irqnr, \tmp
+        cmpcs   \irqnr, \irqnr
+        .endm
+
+/* We assume that irqstat (the raw value of the IRQ acknowledge
+ * register) is preserved from the macro above.
+ * If there is an IPI, we immediately signal end of interrupt on the
+ * controller, since this requires the original irqstat value which
+ * we won't easily be able to recreate later.
+ */
+
+        .macro test_for_ipi, irqnr, irqstat, base, tmp
+        bic     \irqnr, \irqstat, #0x1c00
+        cmp     \irqnr, #16
+        strcc   \irqstat, [\base, #GIC_CPU_EOI]
+        cmpcs   \irqnr, \irqnr
+        .endm
+
+/* As above, this assumes that irqstat and base are preserved.. */
+
+        .macro test_for_ltirq, irqnr, irqstat, base, tmp
+        bic     \irqnr, \irqstat, #0x1c00
+        mov     \tmp, #0
+        cmp     \irqnr, #29
+        moveq   \tmp, #1
+        streq   \irqstat, [\base, #GIC_CPU_EOI]
+        cmp     \tmp, #0
+        .endm
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 7f34333bb545..84557d321001 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -33,10 +33,13 @@
 #define GIC_DIST_SOFTINT                0xf00
 
 #ifndef __ASSEMBLY__
-void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start);
-void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
+extern void __iomem *gic_cpu_base_addr;
+
+void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
+void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
+void gic_enable_ppi(unsigned int);
 #endif
 
 #endif
diff --git a/arch/arm/plat-versatile/include/plat/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
index 21e75e30d497..21e75e30d497 100644
--- a/arch/arm/plat-versatile/include/plat/timer-sp.h
+++ b/arch/arm/include/asm/hardware/timer-sp.h
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index 4d8ae9d67abe..f389b2704d82 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -20,8 +20,8 @@ struct arch_hw_breakpoint_ctrl {
 struct arch_hw_breakpoint {
         u32     address;
         u32     trigger;
-        struct perf_event *suspended_wp;
-        struct arch_hw_breakpoint_ctrl ctrl;
+        struct  arch_hw_breakpoint_ctrl step_ctrl;
+        struct  arch_hw_breakpoint_ctrl ctrl;
 };
 
 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 815efa2d4e07..20e0f7c9e03e 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -241,18 +241,15 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  *
  */
 #ifndef __arch_ioremap
-#define ioremap(cookie,size)            __arm_ioremap(cookie, size, MT_DEVICE)
-#define ioremap_nocache(cookie,size)    __arm_ioremap(cookie, size, MT_DEVICE)
-#define ioremap_cached(cookie,size)     __arm_ioremap(cookie, size, MT_DEVICE_CACHED)
-#define ioremap_wc(cookie,size)         __arm_ioremap(cookie, size, MT_DEVICE_WC)
-#define iounmap(cookie)                 __iounmap(cookie)
-#else
+#define __arch_ioremap                  __arm_ioremap
+#define __arch_iounmap                  __iounmap
+#endif
+
 #define ioremap(cookie,size)            __arch_ioremap((cookie), (size), MT_DEVICE)
 #define ioremap_nocache(cookie,size)    __arch_ioremap((cookie), (size), MT_DEVICE)
 #define ioremap_cached(cookie,size)     __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
 #define ioremap_wc(cookie,size)         __arch_ioremap((cookie), (size), MT_DEVICE_WC)
-#define iounmap(cookie)                 __arch_iounmap(cookie)
-#endif
+#define iounmap                         __arch_iounmap
 
 /*
  * io{read,write}{8,16,32} macros
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index 8ec9ef5c3c7b..c0094d8edae4 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -33,10 +33,20 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
         if (oldregs) {
                 memcpy(newregs, oldregs, sizeof(*newregs));
         } else {
-                __asm__ __volatile__ ("stmia %0, {r0 - r15}"
-                                      : : "r" (&newregs->ARM_r0));
-                __asm__ __volatile__ ("mrs %0, cpsr"
-                                      : "=r" (newregs->ARM_cpsr));
+                __asm__ __volatile__ (
+                        "stmia  %[regs_base], {r0-r12}\n\t"
+                        "mov    %[_ARM_sp], sp\n\t"
+                        "str    lr, %[_ARM_lr]\n\t"
+                        "adr    %[_ARM_pc], 1f\n\t"
+                        "mrs    %[_ARM_cpsr], cpsr\n\t"
+                "1:"
+                        : [_ARM_pc] "=r" (newregs->ARM_pc),
+                          [_ARM_cpsr] "=r" (newregs->ARM_cpsr),
+                          [_ARM_sp] "=r" (newregs->ARM_sp),
+                          [_ARM_lr] "=o" (newregs->ARM_lr)
+                        : [regs_base] "r" (&newregs->ARM_r0)
+                        : "memory"
+                );
         }
 }
 
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index 50c7e7cfd670..6bc63ab498ce 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -30,7 +30,6 @@ asmlinkage void do_local_timer(struct pt_regs *);
 #include "smp_twd.h"
 
 #define local_timer_ack()       twd_timer_ack()
-#define local_timer_stop()      twd_timer_stop()
 
 #else
 
@@ -40,11 +39,6 @@ asmlinkage void do_local_timer(struct pt_regs *);
  */
 int local_timer_ack(void);
 
-/*
- * Stop a local timer interrupt.
- */
-void local_timer_stop(void);
-
 #endif
 
 /*
@@ -52,12 +46,6 @@ void local_timer_stop(void);
  */
 void local_timer_setup(struct clock_event_device *);
 
-#else
-
-static inline void local_timer_stop(void)
-{
-}
-
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index d97a964207fa..3a0893a76a3b 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -37,12 +37,21 @@ struct machine_desc {
                                          struct meminfo *);
         void                    (*reserve)(void);/* reserve mem blocks  */
         void                    (*map_io)(void);/* IO mapping function  */
+        void                    (*init_early)(void);
         void                    (*init_irq)(void);
         struct sys_timer        *timer;         /* system tick timer    */
         void                    (*init_machine)(void);
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+        void                    (*handle_irq)(struct pt_regs *);
+#endif
 };
 
 /*
+ * Current machine - only accessible during boot.
+ */
+extern struct machine_desc *machine_desc;
+
+/*
  * Set of macros to define architecture features.  This is built into
  * a table by the linker.
  */
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index ce3eee9fe26c..22ac140edd9e 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -17,10 +17,12 @@ struct seq_file;
 /*
  * This is internal.  Do not use it.
  */
-extern unsigned int arch_nr_irqs;
-extern void (*init_arch_irq)(void);
 extern void init_FIQ(void);
-extern int show_fiq_list(struct seq_file *, void *);
+extern int show_fiq_list(struct seq_file *, int);
+
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+extern void (*handle_arch_irq)(struct pt_regs *);
+#endif
 
 /*
  * This is for easy migration, but should be changed in the source
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h
index 35d408f6dccf..883f6be5117a 100644
--- a/arch/arm/include/asm/mach/time.h
+++ b/arch/arm/include/asm/mach/time.h
@@ -43,7 +43,6 @@ struct sys_timer {
 #endif
 };
 
-extern struct sys_timer *system_timer;
 extern void timer_tick(void);
 
 #endif
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index cbb0bc295d2b..12c8e680cbff 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -8,11 +8,6 @@
 struct unwind_table;
 
 #ifdef CONFIG_ARM_UNWIND
-struct arm_unwind_mapping {
-        Elf_Shdr *unw_sec;
-        Elf_Shdr *sec_text;
-        struct unwind_table *unwind;
-};
 enum {
         ARM_SEC_INIT,
         ARM_SEC_DEVINIT,
@@ -21,13 +16,13 @@ enum {
         ARM_SEC_DEVEXIT,
         ARM_SEC_MAX,
 };
+#endif
+
 struct mod_arch_specific {
-        struct arm_unwind_mapping map[ARM_SEC_MAX];
-};
-#else
-struct mod_arch_specific {
-};
+#ifdef CONFIG_ARM_UNWIND
+        struct unwind_table *unwind[ARM_SEC_MAX];
 #endif
+};
 
 /*
  * Include the ARM architecture version.
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index a485ac3c8696..f51a69595f6e 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -151,13 +151,15 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
 #define clear_page(page)        memset((void *)(page), 0, PAGE_SIZE)
 extern void copy_page(void *to, const void *from);
 
+typedef unsigned long pteval_t;
+
 #undef STRICT_MM_TYPECHECKS
 
 #ifdef STRICT_MM_TYPECHECKS
 /*
  * These are used to make use of C type-checking..
  */
-typedef struct { unsigned long pte; } pte_t;
+typedef struct { pteval_t pte; } pte_t;
 typedef struct { unsigned long pmd; } pmd_t;
 typedef struct { unsigned long pgd[2]; } pgd_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
@@ -175,7 +177,7 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 /*
  * .. while these make it easier on the compiler
  */
-typedef unsigned long pte_t;
+typedef pteval_t pte_t;
 typedef unsigned long pmd_t;
 typedef unsigned long pgd_t[2];
 typedef unsigned long pgprot_t;
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h
index b12cc98bbe04..9763be04f77e 100644
--- a/arch/arm/include/asm/pgalloc.h
+++ b/arch/arm/include/asm/pgalloc.h
@@ -30,14 +30,16 @@
 #define pmd_free(mm, pmd)               do { } while (0)
 #define pgd_populate(mm,pmd,pte)        BUG()
 
-extern pgd_t *get_pgd_slow(struct mm_struct *mm);
-extern void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd);
-
-#define pgd_alloc(mm)                   get_pgd_slow(mm)
-#define pgd_free(mm, pgd)               free_pgd_slow(mm, pgd)
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
 
 #define PGALLOC_GFP     (GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO)
 
+static inline void clean_pte_table(pte_t *pte)
+{
+        clean_dcache_area(pte + PTE_HWTABLE_PTRS, PTE_HWTABLE_SIZE);
+}
+
 /*
  * Allocate one PTE table.
  *
@@ -45,14 +47,14 @@ extern void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd);
  * into one table thus:
  *
  *  +------------+
- *  |  h/w pt 0  |
- *  +------------+
- *  |  h/w pt 1  |
- *  +------------+
  *  | Linux pt 0 |
  *  +------------+
  *  | Linux pt 1 |
  *  +------------+
+ *  |  h/w pt 0  |
+ *  +------------+
+ *  |  h/w pt 1  |
+ *  +------------+
  */
 static inline pte_t *
 pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
@@ -60,10 +62,8 @@ pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
         pte_t *pte;
 
         pte = (pte_t *)__get_free_page(PGALLOC_GFP);
-        if (pte) {
-                clean_dcache_area(pte, sizeof(pte_t) * PTRS_PER_PTE);
-                pte += PTRS_PER_PTE;
-        }
+        if (pte)
+                clean_pte_table(pte);
 
         return pte;
 }
@@ -79,10 +79,8 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr)
         pte = alloc_pages(PGALLOC_GFP, 0);
 #endif
         if (pte) {
-                if (!PageHighMem(pte)) {
-                        void *page = page_address(pte);
-                        clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE);
-                }
+                if (!PageHighMem(pte))
+                        clean_pte_table(page_address(pte));
                 pgtable_page_ctor(pte);
         }
 
@@ -94,10 +92,8 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr)
  */
 static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
 {
-        if (pte) {
-                pte -= PTRS_PER_PTE;
+        if (pte)
                 free_page((unsigned long)pte);
-        }
 }
 
 static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
@@ -106,8 +102,10 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
         __free_page(pte);
 }
 
-static inline void __pmd_populate(pmd_t *pmdp, unsigned long pmdval)
+static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte,
+        unsigned long prot)
 {
+        unsigned long pmdval = (pte + PTE_HWTABLE_OFF) | prot;
         pmdp[0] = __pmd(pmdval);
         pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
         flush_pmd_entry(pmdp);
@@ -122,20 +120,16 @@ static inline void __pmd_populate(pmd_t *pmdp, unsigned long pmdval)
 static inline void
 pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
 {
-        unsigned long pte_ptr = (unsigned long)ptep;
-
         /*
-         * The pmd must be loaded with the physical
-         * address of the PTE table
+         * The pmd must be loaded with the physical address of the PTE table
          */
-        pte_ptr -= PTRS_PER_PTE * sizeof(void *);
-        __pmd_populate(pmdp, __pa(pte_ptr) | _PAGE_KERNEL_TABLE);
+        __pmd_populate(pmdp, __pa(ptep), _PAGE_KERNEL_TABLE);
 }
 
 static inline void
 pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep)
 {
-        __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE);
+        __pmd_populate(pmdp, page_to_phys(ptep), _PAGE_USER_TABLE);
 }
 #define pmd_pgtable(pmd) pmd_page(pmd)
 
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 53d1d5deb111..ebcb6432f45f 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -10,6 +10,7 @@
 #ifndef _ASMARM_PGTABLE_H
 #define _ASMARM_PGTABLE_H
 
+#include <linux/const.h>
 #include <asm-generic/4level-fixup.h>
 #include <asm/proc-fns.h>
 
@@ -54,7 +55,7 @@
  * Therefore, we tweak the implementation slightly - we tell Linux that we
  * have 2048 entries in the first level, each of which is 8 bytes (iow, two
  * hardware pointers to the second level.)  The second level contains two
- * hardware PTE tables arranged contiguously, followed by Linux versions
+ * hardware PTE tables arranged contiguously, preceded by Linux versions
  * which contain the state information Linux needs.  We, therefore, end up
  * with 512 entries in the "PTE" level.
  *
@@ -62,15 +63,15 @@
  *
  *    pgd             pte
  * |        |
- * +--------+ +0
- * |        |-----> +------------+ +0
+ * +--------+
+ * |        |       +------------+ +0
+ * +- - - - +       | Linux pt 0 |
+ * |        |       +------------+ +1024
+ * +--------+ +0    | Linux pt 1 |
+ * |        |-----> +------------+ +2048
  * +- - - - + +4    |  h/w pt 0  |
- * |        |-----> +------------+ +1024
+ * |        |-----> +------------+ +3072
  * +--------+ +8    |  h/w pt 1  |
- * |        |       +------------+ +2048
- * +- - - - +       | Linux pt 0 |
- * |        |       +------------+ +3072
- * +--------+       | Linux pt 1 |
  * |        |       +------------+ +4096
  *
  * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
@@ -102,6 +103,10 @@
 #define PTRS_PER_PMD            1
 #define PTRS_PER_PGD            2048
 
+#define PTE_HWTABLE_PTRS        (PTRS_PER_PTE)
+#define PTE_HWTABLE_OFF         (PTE_HWTABLE_PTRS * sizeof(pte_t))
+#define PTE_HWTABLE_SIZE        (PTRS_PER_PTE * sizeof(u32))
+
 /*
  * PMD_SHIFT determines the size of the area a second-level page table can map
  * PGDIR_SHIFT determines what a third-level page table entry can map
@@ -112,13 +117,13 @@
 #define LIBRARY_TEXT_START      0x0c000000
 
 #ifndef __ASSEMBLY__
-extern void __pte_error(const char *file, int line, unsigned long val);
-extern void __pmd_error(const char *file, int line, unsigned long val);
-extern void __pgd_error(const char *file, int line, unsigned long val);
+extern void __pte_error(const char *file, int line, pte_t);
+extern void __pmd_error(const char *file, int line, pmd_t);
+extern void __pgd_error(const char *file, int line, pgd_t);
 
-#define pte_ERROR(pte)          __pte_error(__FILE__, __LINE__, pte_val(pte))
-#define pmd_ERROR(pmd)          __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
-#define pgd_ERROR(pgd)          __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
+#define pte_ERROR(pte)          __pte_error(__FILE__, __LINE__, pte)
+#define pmd_ERROR(pmd)          __pmd_error(__FILE__, __LINE__, pmd)
+#define pgd_ERROR(pgd)          __pgd_error(__FILE__, __LINE__, pgd)
 #endif /* !__ASSEMBLY__ */
 
 #define PMD_SIZE                (1UL << PMD_SHIFT)
@@ -133,8 +138,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
  */
 #define FIRST_USER_ADDRESS      PAGE_SIZE
 
-#define FIRST_USER_PGD_NR       1
-#define USER_PTRS_PER_PGD       ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)
+#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
 
 /*
  * section address mask and size definitions.
@@ -161,30 +165,30 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
  * The PTE table pointer refers to the hardware entries; the "Linux"
  * entries are stored 1024 bytes below.
  */
-#define L_PTE_PRESENT           (1 << 0)
-#define L_PTE_YOUNG             (1 << 1)
-#define L_PTE_FILE              (1 << 2)        /* only when !PRESENT */
-#define L_PTE_DIRTY             (1 << 6)
-#define L_PTE_WRITE             (1 << 7)
-#define L_PTE_USER              (1 << 8)
-#define L_PTE_EXEC              (1 << 9)
-#define L_PTE_SHARED            (1 << 10)       /* shared(v6), coherent(xsc3) */
+#define L_PTE_PRESENT           (_AT(pteval_t, 1) << 0)
+#define L_PTE_YOUNG             (_AT(pteval_t, 1) << 1)
+#define L_PTE_FILE              (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
+#define L_PTE_DIRTY             (_AT(pteval_t, 1) << 6)
+#define L_PTE_RDONLY            (_AT(pteval_t, 1) << 7)
+#define L_PTE_USER              (_AT(pteval_t, 1) << 8)
+#define L_PTE_XN                (_AT(pteval_t, 1) << 9)
+#define L_PTE_SHARED            (_AT(pteval_t, 1) << 10)        /* shared(v6), coherent(xsc3) */
 
 /*
  * These are the memory types, defined to be compatible with
  * pre-ARMv6 CPUs cacheable and bufferable bits:   XXCB
  */
-#define L_PTE_MT_UNCACHED       (0x00 << 2)     /* 0000 */
-#define L_PTE_MT_BUFFERABLE     (0x01 << 2)     /* 0001 */
-#define L_PTE_MT_WRITETHROUGH   (0x02 << 2)     /* 0010 */
-#define L_PTE_MT_WRITEBACK      (0x03 << 2)     /* 0011 */
-#define L_PTE_MT_MINICACHE      (0x06 << 2)     /* 0110 (sa1100, xscale) */
-#define L_PTE_MT_WRITEALLOC     (0x07 << 2)     /* 0111 */
-#define L_PTE_MT_DEV_SHARED     (0x04 << 2)     /* 0100 */
-#define L_PTE_MT_DEV_NONSHARED  (0x0c << 2)     /* 1100 */
-#define L_PTE_MT_DEV_WC         (0x09 << 2)     /* 1001 */
-#define L_PTE_MT_DEV_CACHED     (0x0b << 2)     /* 1011 */
-#define L_PTE_MT_MASK           (0x0f << 2)
+#define L_PTE_MT_UNCACHED       (_AT(pteval_t, 0x00) << 2)      /* 0000 */
+#define L_PTE_MT_BUFFERABLE     (_AT(pteval_t, 0x01) << 2)      /* 0001 */
+#define L_PTE_MT_WRITETHROUGH   (_AT(pteval_t, 0x02) << 2)      /* 0010 */
+#define L_PTE_MT_WRITEBACK      (_AT(pteval_t, 0x03) << 2)      /* 0011 */
+#define L_PTE_MT_MINICACHE      (_AT(pteval_t, 0x06) << 2)      /* 0110 (sa1100, xscale) */
+#define L_PTE_MT_WRITEALLOC     (_AT(pteval_t, 0x07) << 2)      /* 0111 */
+#define L_PTE_MT_DEV_SHARED     (_AT(pteval_t, 0x04) << 2)      /* 0100 */
+#define L_PTE_MT_DEV_NONSHARED  (_AT(pteval_t, 0x0c) << 2)      /* 1100 */
+#define L_PTE_MT_DEV_WC         (_AT(pteval_t, 0x09) << 2)      /* 1001 */
+#define L_PTE_MT_DEV_CACHED     (_AT(pteval_t, 0x0b) << 2)      /* 1011 */
+#define L_PTE_MT_MASK           (_AT(pteval_t, 0x0f) << 2)
 
 #ifndef __ASSEMBLY__
 
@@ -201,23 +205,44 @@ extern pgprot_t		pgprot_kernel;
 
 #define _MOD_PROT(p, b) __pgprot(pgprot_val(p) | (b))
 
-#define PAGE_NONE               pgprot_user
-#define PAGE_SHARED             _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE)
-#define PAGE_SHARED_EXEC        _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC)
-#define PAGE_COPY               _MOD_PROT(pgprot_user, L_PTE_USER)
-#define PAGE_COPY_EXEC          _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC)
-#define PAGE_READONLY           _MOD_PROT(pgprot_user, L_PTE_USER)
-#define PAGE_READONLY_EXEC      _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC)
-#define PAGE_KERNEL             pgprot_kernel
-#define PAGE_KERNEL_EXEC        _MOD_PROT(pgprot_kernel, L_PTE_EXEC)
-
-#define __PAGE_NONE             __pgprot(_L_PTE_DEFAULT)
-#define __PAGE_SHARED           __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE)
-#define __PAGE_SHARED_EXEC      __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC)
-#define __PAGE_COPY             __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
-#define __PAGE_COPY_EXEC        __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC)
-#define __PAGE_READONLY         __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
-#define __PAGE_READONLY_EXEC    __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC)
+#define PAGE_NONE               _MOD_PROT(pgprot_user, L_PTE_XN | L_PTE_RDONLY)
+#define PAGE_SHARED             _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_XN)
+#define PAGE_SHARED_EXEC        _MOD_PROT(pgprot_user, L_PTE_USER)
+#define PAGE_COPY               _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
+#define PAGE_COPY_EXEC          _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
+#define PAGE_READONLY           _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
+#define PAGE_READONLY_EXEC      _MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_RDONLY)
+#define PAGE_KERNEL             _MOD_PROT(pgprot_kernel, L_PTE_XN)
+#define PAGE_KERNEL_EXEC        pgprot_kernel
+
+#define __PAGE_NONE             __pgprot(_L_PTE_DEFAULT | L_PTE_RDONLY | L_PTE_XN)
+#define __PAGE_SHARED           __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_XN)
+#define __PAGE_SHARED_EXEC      __pgprot(_L_PTE_DEFAULT | L_PTE_USER)
+#define __PAGE_COPY             __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
+#define __PAGE_COPY_EXEC        __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
+#define __PAGE_READONLY         __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY | L_PTE_XN)
+#define __PAGE_READONLY_EXEC    __pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_RDONLY)
+
+#define __pgprot_modify(prot,mask,bits)         \
+        __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
+
+#define pgprot_noncached(prot) \
+        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
+
+#define pgprot_writecombine(prot) \
+        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
+
+#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
+#define pgprot_dmacoherent(prot) \
+        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                                     unsigned long size, pgprot_t vma_prot);
+#else
+#define pgprot_dmacoherent(prot) \
+        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
+#endif
 
 #endif /* __ASSEMBLY__ */
 
@@ -255,26 +280,84 @@ extern pgprot_t		pgprot_kernel;
 extern struct page *empty_zero_page;
 #define ZERO_PAGE(vaddr)        (empty_zero_page)
 
-#define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
-#define pfn_pte(pfn,prot)       (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
 
-#define pte_none(pte)           (!pte_val(pte))
-#define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
-#define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
-#define pte_offset_kernel(dir,addr)     (pmd_page_vaddr(*(dir)) + __pte_index(addr))
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+
+/* to find an entry in a page-table-directory */
+#define pgd_index(addr)         ((addr) >> PGDIR_SHIFT)
+
+#define pgd_offset(mm, addr)    ((mm)->pgd + pgd_index(addr))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(addr)      pgd_offset(&init_mm, addr)
+
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+#define pgd_none(pgd)           (0)
+#define pgd_bad(pgd)            (0)
+#define pgd_present(pgd)        (1)
+#define pgd_clear(pgdp)         do { } while (0)
+#define set_pgd(pgd,pgdp)       do { } while (0)
+
+
+/* Find an entry in the second-level page table.. */
+#define pmd_offset(dir, addr)   ((pmd_t *)(dir))
+
+#define pmd_none(pmd)           (!pmd_val(pmd))
+#define pmd_present(pmd)        (pmd_val(pmd))
+#define pmd_bad(pmd)            (pmd_val(pmd) & 2)
+
+#define copy_pmd(pmdpd,pmdps)           \
+        do {                            \
+                pmdpd[0] = pmdps[0];    \
+                pmdpd[1] = pmdps[1];    \
+                flush_pmd_entry(pmdpd); \
+        } while (0)
+
+#define pmd_clear(pmdp)                 \
+        do {                            \
+                pmdp[0] = __pmd(0);     \
+                pmdp[1] = __pmd(0);     \
+                clean_pmd_entry(pmdp);  \
+        } while (0)
+
+static inline pte_t *pmd_page_vaddr(pmd_t pmd)
+{
+        return __va(pmd_val(pmd) & PAGE_MASK);
+}
+
+#define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd)))
+
+/* we don't need complex calculations here as the pmd is folded into the pgd */
+#define pmd_addr_end(addr,end)  (end)
 
-#define pte_offset_map(dir,addr)        (__pte_map(dir) + __pte_index(addr))
-#define pte_unmap(pte)                  __pte_unmap(pte)
 
 #ifndef CONFIG_HIGHPTE
-#define __pte_map(dir)          pmd_page_vaddr(*(dir))
+#define __pte_map(pmd)          pmd_page_vaddr(*(pmd))
 #define __pte_unmap(pte)        do { } while (0)
 #else
-#define __pte_map(dir)          ((pte_t *)kmap_atomic(pmd_page(*(dir))) + PTRS_PER_PTE)
-#define __pte_unmap(pte)        kunmap_atomic((pte - PTRS_PER_PTE))
+#define __pte_map(pmd)          (pte_t *)kmap_atomic(pmd_page(*(pmd)))
+#define __pte_unmap(pte)        kunmap_atomic(pte)
 #endif
 
+#define pte_index(addr)         (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+
+#define pte_offset_kernel(pmd,addr)     (pmd_page_vaddr(*(pmd)) + pte_index(addr))
+
+#define pte_offset_map(pmd,addr)        (__pte_map(pmd) + pte_index(addr))
+#define pte_unmap(pte)                  __pte_unmap(pte)
+
+#define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
+#define pfn_pte(pfn,prot)       __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+
+#define pte_page(pte)           pfn_to_page(pte_pfn(pte))
+#define mk_pte(page,prot)       pfn_pte(page_to_pfn(page), prot)
+
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
+#define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
 
 #if __LINUX_ARM_ARCH__ < 6
 static inline void __sync_icache_dcache(pte_t pteval)
@@ -295,15 +378,12 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
         }
 }
 
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
+#define pte_none(pte)           (!pte_val(pte))
 #define pte_present(pte)        (pte_val(pte) & L_PTE_PRESENT)
-#define pte_write(pte)          (pte_val(pte) & L_PTE_WRITE)
+#define pte_write(pte)          (!(pte_val(pte) & L_PTE_RDONLY))
 #define pte_dirty(pte)          (pte_val(pte) & L_PTE_DIRTY)
 #define pte_young(pte)          (pte_val(pte) & L_PTE_YOUNG)
-#define pte_exec(pte)           (pte_val(pte) & L_PTE_EXEC)
+#define pte_exec(pte)           (!(pte_val(pte) & L_PTE_XN))
 #define pte_special(pte)        (0)
 
 #define pte_present_user(pte) \
@@ -313,8 +393,8 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 #define PTE_BIT_FUNC(fn,op) \
 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
 
-PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE);
-PTE_BIT_FUNC(mkwrite,   |= L_PTE_WRITE);
+PTE_BIT_FUNC(wrprotect, |= L_PTE_RDONLY);
+PTE_BIT_FUNC(mkwrite,   &= ~L_PTE_RDONLY);
 PTE_BIT_FUNC(mkclean,   &= ~L_PTE_DIRTY);
 PTE_BIT_FUNC(mkdirty,   |= L_PTE_DIRTY);
 PTE_BIT_FUNC(mkold,     &= ~L_PTE_YOUNG);
@@ -322,101 +402,13 @@ PTE_BIT_FUNC(mkyoung,   |= L_PTE_YOUNG);
 
 static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 
-#define __pgprot_modify(prot,mask,bits)         \
-        __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
-
-/*
- * Mark the prot value as uncacheable and unbufferable.
- */
-#define pgprot_noncached(prot) \
-        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
-#define pgprot_writecombine(prot) \
-        __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
-#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
-#define pgprot_dmacoherent(prot) \
-        __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE)
-#define __HAVE_PHYS_MEM_ACCESS_PROT
-struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
-                                     unsigned long size, pgprot_t vma_prot);
-#else
-#define pgprot_dmacoherent(prot) \
-        __pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED)
-#endif
-
-#define pmd_none(pmd)           (!pmd_val(pmd))
-#define pmd_present(pmd)        (pmd_val(pmd))
-#define pmd_bad(pmd)            (pmd_val(pmd) & 2)
-
-#define copy_pmd(pmdpd,pmdps)           \
-        do {                            \
-                pmdpd[0] = pmdps[0];    \
-                pmdpd[1] = pmdps[1];    \
-                flush_pmd_entry(pmdpd); \
-        } while (0)
-
-#define pmd_clear(pmdp)                 \
-        do {                            \
-                pmdp[0] = __pmd(0);     \
-                pmdp[1] = __pmd(0);     \
-                clean_pmd_entry(pmdp);  \
-        } while (0)
-
-static inline pte_t *pmd_page_vaddr(pmd_t pmd)
-{
-        unsigned long ptr;
-
-        ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1);
-        ptr += PTRS_PER_PTE * sizeof(void *);
-
-        return __va(ptr);
-}
-
-#define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd)))
-
-/* we don't need complex calculations here as the pmd is folded into the pgd */
-#define pmd_addr_end(addr,end)  (end)
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-#define mk_pte(page,prot)       pfn_pte(page_to_pfn(page),prot)
-
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-#define pgd_none(pgd)           (0)
-#define pgd_bad(pgd)            (0)
-#define pgd_present(pgd)        (1)
-#define pgd_clear(pgdp)         do { } while (0)
-#define set_pgd(pgd,pgdp)       do { } while (0)
-
-/* to find an entry in a page-table-directory */
-#define pgd_index(addr)         ((addr) >> PGDIR_SHIFT)
-
-#define pgd_offset(mm, addr)    ((mm)->pgd+pgd_index(addr))
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(addr)      pgd_offset(&init_mm, addr)
-
-/* Find an entry in the second-level page table.. */
-#define pmd_offset(dir, addr)   ((pmd_t *)(dir))
-
-/* Find an entry in the third-level page table.. */
-#define __pte_index(addr)       (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-        const unsigned long mask = L_PTE_EXEC | L_PTE_WRITE | L_PTE_USER;
+        const pteval_t mask = L_PTE_XN | L_PTE_RDONLY | L_PTE_USER;
         pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
         return pte;
 }
 
-extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
-
 /*
  * Encode and decode a swap entry.  Swap entries are stored in the Linux
  * page tables as follows:
@@ -481,6 +473,9 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 
 #define pgtable_cache_init() do { } while (0)
 
+void identity_mapping_add(pgd_t *, unsigned long, unsigned long);
+void identity_mapping_del(pgd_t *, unsigned long, unsigned long);
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* CONFIG_MMU */
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h
new file mode 100644
index 000000000000..a84628be1a7b
--- /dev/null
+++ b/arch/arm/include/asm/sched_clock.h
@@ -0,0 +1,118 @@
+/*
+ * sched_clock.h: support for extending counters to full 64-bit ns counter
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASM_SCHED_CLOCK
+#define ASM_SCHED_CLOCK
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct clock_data {
+        u64 epoch_ns;
+        u32 epoch_cyc;
+        u32 epoch_cyc_copy;
+        u32 mult;
+        u32 shift;
+};
+
+#define DEFINE_CLOCK_DATA(name) struct clock_data name
+
+static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
+{
+        return (cyc * mult) >> shift;
+}
+
+/*
+ * Atomically update the sched_clock epoch.  Your update callback will
+ * be called from a timer before the counter wraps - read the current
+ * counter value, and call this function to safely move the epochs
+ * forward.  Only use this from the update callback.
+ */
+static inline void update_sched_clock(struct clock_data *cd, u32 cyc, u32 mask)
+{
+        unsigned long flags;
+        u64 ns = cd->epoch_ns +
+                cyc_to_ns((cyc - cd->epoch_cyc) & mask, cd->mult, cd->shift);
+
+        /*
+         * Write epoch_cyc and epoch_ns in a way that the update is
+         * detectable in cyc_to_fixed_sched_clock().
+         */
+        raw_local_irq_save(flags);
+        cd->epoch_cyc = cyc;
+        smp_wmb();
+        cd->epoch_ns = ns;
+        smp_wmb();
+        cd->epoch_cyc_copy = cyc;
+        raw_local_irq_restore(flags);
+}
+
+/*
+ * If your clock rate is known at compile time, using this will allow
+ * you to optimize the mult/shift loads away.  This is paired with
+ * init_fixed_sched_clock() to ensure that your mult/shift are correct.
+ */
+static inline unsigned long long cyc_to_fixed_sched_clock(struct clock_data *cd,
+        u32 cyc, u32 mask, u32 mult, u32 shift)
+{
+        u64 epoch_ns;
+        u32 epoch_cyc;
+
+        /*
+         * Load the epoch_cyc and epoch_ns atomically.  We do this by
+         * ensuring that we always write epoch_cyc, epoch_ns and
+         * epoch_cyc_copy in strict order, and read them in strict order.
+         * If epoch_cyc and epoch_cyc_copy are not equal, then we're in
+         * the middle of an update, and we should repeat the load.
+         */
+        do {
+                epoch_cyc = cd->epoch_cyc;
+                smp_rmb();
+                epoch_ns = cd->epoch_ns;
+                smp_rmb();
+        } while (epoch_cyc != cd->epoch_cyc_copy);
+
+        return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, mult, shift);
+}
+
+/*
+ * Otherwise, you need to use this, which will obtain the mult/shift
+ * from the clock_data structure.  Use init_sched_clock() with this.
+ */
+static inline unsigned long long cyc_to_sched_clock(struct clock_data *cd,
+        u32 cyc, u32 mask)
+{
+        return cyc_to_fixed_sched_clock(cd, cyc, mask, cd->mult, cd->shift);
+}
+
+/*
+ * Initialize the clock data - calculate the appropriate multiplier
+ * and shift.  Also setup a timer to ensure that the epoch is refreshed
+ * at the appropriate time interval, which will call your update
+ * handler.
+ */
+void init_sched_clock(struct clock_data *, void (*)(void),
+        unsigned int, unsigned long);
+
+/*
+ * Use this initialization function rather than init_sched_clock() if
+ * you're using cyc_to_fixed_sched_clock, which will warn if your
+ * constants are incorrect.
+ */
+static inline void init_fixed_sched_clock(struct clock_data *cd,
+        void (*update)(void), unsigned int bits, unsigned long rate,
+        u32 mult, u32 shift)
+{
+        init_sched_clock(cd, update, bits, rate);
+        if (cd->mult != mult || cd->shift != shift) {
+                pr_crit("sched_clock: wrong multiply/shift: %u>>%u vs calculated %u>>%u\n"
+                        "sched_clock: fix multiply/shift to avoid scheduler hiccups\n",
+                        mult, shift, cd->mult, cd->shift);
+        }
+}
+
+#endif
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 3d05190797cb..96ed521f2408 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -33,27 +33,23 @@ struct seq_file;
 /*
  * generate IPI list text
  */
-extern void show_ipi_list(struct seq_file *p);
+extern void show_ipi_list(struct seq_file *, int);
 
 /*
  * Called from assembly code, this handles an IPI.
  */
-asmlinkage void do_IPI(struct pt_regs *regs);
+asmlinkage void do_IPI(int ipinr, struct pt_regs *regs);
 
 /*
  * Setup the set of possible CPUs (via set_cpu_possible)
  */
 extern void smp_init_cpus(void);
 
-/*
- * Move global data into per-processor storage.
- */
-extern void smp_store_cpu_info(unsigned int cpuid);
 
 /*
  * Raise an IPI cross call on CPUs in callmap.
  */
-extern void smp_cross_call(const struct cpumask *mask);
+extern void smp_cross_call(const struct cpumask *mask, int ipi);
 
 /*
  * Boot a secondary CPU, and assign it the specified idle task.
@@ -73,6 +69,11 @@ asmlinkage void secondary_start_kernel(void);
 extern void platform_secondary_init(unsigned int cpu);
 
 /*
+ * Initialize cpu_possible map, and enable coherency
+ */
+extern void platform_smp_prepare_cpus(unsigned int);
+
+/*
  * Initial data for bringing up a secondary CPU.
  */
 struct secondary_data {
@@ -97,6 +98,6 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 /*
  * show local interrupt info
  */
-extern void show_local_irqs(struct seq_file *);
+extern void show_local_irqs(struct seq_file *, int);
 
 #endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/include/asm/smp_mpidr.h b/arch/arm/include/asm/smp_mpidr.h
deleted file mode 100644
index 6a9307d64900..000000000000
--- a/arch/arm/include/asm/smp_mpidr.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef ASMARM_SMP_MIDR_H
-#define ASMARM_SMP_MIDR_H
-
-#define hard_smp_processor_id()                                         \
-        ({                                                              \
-                unsigned int cpunum;                                    \
-                __asm__("\n"                                            \
-                        "1:     mrc p15, 0, %0, c0, c0, 5\n"            \
-                        "       .pushsection \".alt.smp.init\", \"a\"\n"\
-                        "       .long   1b\n"                           \
-                        "       mov     %0, #0\n"                       \
-                        "       .popsection"                            \
-                        : "=r" (cpunum));                               \
-                cpunum &= 0x0F;                                         \
-        })
-
-#endif
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index 634f357be6bb..fed9981fba08 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -22,7 +22,6 @@ struct clock_event_device;
 
 extern void __iomem *twd_base;
 
-void twd_timer_stop(void);
 int twd_timer_ack(void);
 void twd_timer_setup(struct clock_event_device *);
 
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 80025948b8ad..97f6d60297d5 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -63,6 +63,11 @@
 #include <asm/outercache.h>
 
 #define __exception     __attribute__((section(".exception.text")))
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#define __exception_irq_entry   __irq_entry
+#else
+#define __exception_irq_entry   __exception
+#endif
 
 struct thread_info;
 struct task_struct;
@@ -119,6 +124,13 @@ extern unsigned int user_debug;
 #define vectors_high()  (0)
 #endif
 
+#if __LINUX_ARM_ARCH__ >= 7 ||          \
+        (__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
+#define sev()   __asm__ __volatile__ ("sev" : : : "memory")
+#define wfe()   __asm__ __volatile__ ("wfe" : : : "memory")
+#define wfi()   __asm__ __volatile__ ("wfi" : : : "memory")
+#endif
+
 #if __LINUX_ARM_ARCH__ >= 7
 #define isb() __asm__ __volatile__ ("isb" : : : "memory")
 #define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h
index 491960bf4260..1b960d5ef6a5 100644
--- a/arch/arm/include/asm/traps.h
+++ b/arch/arm/include/asm/traps.h
@@ -15,16 +15,37 @@ struct undef_hook {
 void register_undef_hook(struct undef_hook *hook);
 void unregister_undef_hook(struct undef_hook *hook);
 
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+static inline int __in_irqentry_text(unsigned long ptr)
+{
+        extern char __irqentry_text_start[];
+        extern char __irqentry_text_end[];
+
+        return ptr >= (unsigned long)&__irqentry_text_start &&
+               ptr < (unsigned long)&__irqentry_text_end;
+}
+#else
+static inline int __in_irqentry_text(unsigned long ptr)
+{
+        return 0;
+}
+#endif
+
 static inline int in_exception_text(unsigned long ptr)
 {
         extern char __exception_text_start[];
         extern char __exception_text_end[];
+        int in;
 
-        return ptr >= (unsigned long)&__exception_text_start &&
-               ptr < (unsigned long)&__exception_text_end;
+        in = ptr >= (unsigned long)&__exception_text_start &&
+             ptr < (unsigned long)&__exception_text_end;
+
+        return in ? : __in_irqentry_text(ptr);
 }
 
 extern void __init early_trap_init(void);
 extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame);
 
+extern void *vectors_page;
+
 #endif
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 33e4a48fe103..b293616a1a1a 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -227,7 +227,7 @@ do {									\
 
 #define __get_user_asm_byte(x,addr,err)                         \
         __asm__ __volatile__(                                   \
-        "1:     ldrbt   %1,[%2]\n"                              \
+        "1:     " T(ldrb) "     %1,[%2],#0\n"                   \
         "2:\n"                                                  \
         "       .pushsection .fixup,\"ax\"\n"                   \
         "       .align  2\n"                                    \
@@ -263,7 +263,7 @@ do {									\
 
 #define __get_user_asm_word(x,addr,err)                         \
         __asm__ __volatile__(                                   \
-        "1:     ldrt    %1,[%2]\n"                              \
+        "1:     " T(ldr) "      %1,[%2],#0\n"                   \
         "2:\n"                                                  \
         "       .pushsection .fixup,\"ax\"\n"                   \
         "       .align  2\n"                                    \
@@ -308,7 +308,7 @@ do {									\
 
 #define __put_user_asm_byte(x,__pu_addr,err)                    \
         __asm__ __volatile__(                                   \
-        "1:     strbt   %1,[%2]\n"                              \
+        "1:     " T(strb) "     %1,[%2],#0\n"                   \
         "2:\n"                                                  \
         "       .pushsection .fixup,\"ax\"\n"                   \
         "       .align  2\n"                                    \
@@ -341,7 +341,7 @@ do {									\
 
 #define __put_user_asm_word(x,__pu_addr,err)                    \
         __asm__ __volatile__(                                   \
-        "1:     strt    %1,[%2]\n"                              \
+        "1:     " T(str) "      %1,[%2],#0\n"                   \
         "2:\n"                                                  \
         "       .pushsection .fixup,\"ax\"\n"                   \
         "       .align  2\n"                                    \
@@ -366,10 +366,10 @@ do {									\
 
 #define __put_user_asm_dword(x,__pu_addr,err)                   \
         __asm__ __volatile__(                                   \
- ARM(   "1:     strt    " __reg_oper1 ", [%1], #4\n"    )       \
- ARM(   "2:     strt    " __reg_oper0 ", [%1]\n"        )       \
- THUMB( "1:     strt    " __reg_oper1 ", [%1]\n"        )       \
- THUMB( "2:     strt    " __reg_oper0 ", [%1, #4]\n"    )       \
+ ARM(   "1:     " T(str) "      " __reg_oper1 ", [%1], #4\n"    )       \
+ ARM(   "2:     " T(str) "      " __reg_oper0 ", [%1]\n"        )       \
+ THUMB( "1:     " T(str) "      " __reg_oper1 ", [%1]\n"        )       \
+ THUMB( "2:     " T(str) "      " __reg_oper0 ", [%1, #4]\n"    )       \
         "3:\n"                                                  \
         "       .pushsection .fixup,\"ax\"\n"                   \
         "       .align  2\n"                                    \
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5b9b268f4fbb..185ee822c935 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -5,7 +5,7 @@
 CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET)
 AFLAGS_head.o        := -DTEXT_OFFSET=$(TEXT_OFFSET)
 
-ifdef CONFIG_DYNAMIC_FTRACE
+ifdef CONFIG_FUNCTION_TRACER
 CFLAGS_REMOVE_ftrace.o = -pg
 endif
 
@@ -29,10 +29,12 @@ obj-$(CONFIG_MODULES)		+= armksyms.o module.o
 obj-$(CONFIG_ARTHUR)            += arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
 obj-$(CONFIG_PCI)               += bios32.o isa.o
-obj-$(CONFIG_SMP)               += smp.o
+obj-$(CONFIG_HAVE_SCHED_CLOCK)  += sched_clock.o
+obj-$(CONFIG_SMP)               += smp.o smp_tlb.o
 obj-$(CONFIG_HAVE_ARM_SCU)      += smp_scu.o
 obj-$(CONFIG_HAVE_ARM_TWD)      += smp_twd.o
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
+obj-$(CONFIG_FUNCTION_GRAPH_TRACER)     += ftrace.o
 obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_KPROBES)           += kprobes.o kprobes-decode.o
 obj-$(CONFIG_ATAGS_PROC)        += atags.o
@@ -42,6 +44,8 @@ obj-$(CONFIG_KGDB)		+= kgdb.o
 obj-$(CONFIG_ARM_UNWIND)        += unwind.o
 obj-$(CONFIG_HAVE_TCM)          += tcm.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
+obj-$(CONFIG_SWP_EMULATE)       += swp_emulate.o
+CFLAGS_swp_emulate.o            := -Wa,-march=armv7-a
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += hw_breakpoint.o
 
 obj-$(CONFIG_CRUNCH)            += crunch.o crunch-bits.o
@@ -50,6 +54,7 @@ AFLAGS_crunch-bits.o		:= -Wa,-mcpu=ep9312
 obj-$(CONFIG_CPU_XSCALE)        += xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)          += xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)        += xscale-cp0.o
+obj-$(CONFIG_CPU_PJ4)           += pj4-cp0.o
 obj-$(CONFIG_IWMMXT)            += iwmmxt.o
 obj-$(CONFIG_CPU_HAS_PMU)       += pmu.o
 obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb96a7d4bbf5..2b46fea36c9f 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -25,42 +25,22 @@
 #include <asm/tls.h>
 
 #include "entry-header.S"
+#include <asm/entry-macro-multi.S>
 
 /*
  * Interrupt handling.  Preserves r7, r8, r9
  */
         .macro  irq_handler
-        get_irqnr_preamble r5, lr
-1:      get_irqnr_and_base r0, r6, r5, lr
-        movne   r1, sp
-        @
-        @ routine called with r0 = irq number, r1 = struct pt_regs *
-        @
-        adrne   lr, BSYM(1b)
-        bne     asm_do_IRQ
-
-#ifdef CONFIG_SMP
-        /*
-         * XXX
-         *
-         * this macro assumes that irqstat (r6) and base (r5) are
-         * preserved from get_irqnr_and_base above
-         */
-        ALT_SMP(test_for_ipi r0, r6, r5, lr)
-        ALT_UP_B(9997f)
-        movne   r0, sp
-        adrne   lr, BSYM(1b)
-        bne     do_IPI
-
-#ifdef CONFIG_LOCAL_TIMERS
-        test_for_ltirq r0, r6, r5, lr
-        movne   r0, sp
-        adrne   lr, BSYM(1b)
-        bne     do_local_timer
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+        ldr     r5, =handle_arch_irq
+        mov     r0, sp
+        ldr     r5, [r5]
+        adr     lr, BSYM(9997f)
+        teq     r5, #0
+        movne   pc, r5
 #endif
+        arch_irq_handler_default
 9997:
-#endif
-
         .endm
 
 #ifdef CONFIG_KPROBES
@@ -198,6 +178,7 @@ __dabt_svc:
         @
         @ set desired IRQ state, then call main handler
         @
+        debug_entry r1
         msr     cpsr_c, r9
         mov     r2, sp
         bl      do_DataAbort
@@ -324,6 +305,7 @@ __pabt_svc:
 #else
         bl      CPU_PABORT_HANDLER
 #endif
+        debug_entry r1
         msr     cpsr_c, r9                      @ Maybe enable interrupts
         mov     r2, sp                          @ regs
         bl      do_PrefetchAbort                @ call abort handler
@@ -439,6 +421,7 @@ __dabt_usr:
         @
         @ IRQs on, then call the main handler
         @
+        debug_entry r1
         enable_irq
         mov     r2, sp
         adr     lr, BSYM(ret_from_exception)
@@ -703,6 +686,7 @@ __pabt_usr:
 #else
         bl      CPU_PABORT_HANDLER
 #endif
+        debug_entry r1
         enable_irq                              @ Enable interrupts
         mov     r2, sp                          @ regs
         bl      do_PrefetchAbort                @ call abort handler
@@ -735,7 +719,7 @@ ENTRY(__switch_to)
  THUMB( stmia   ip!, {r4 - sl, fp}         )    @ Store most regs on stack
  THUMB( str     sp, [ip], #4               )
  THUMB( str     lr, [ip], #4               )
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
         ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
         set_tls r3, r4, r5
@@ -744,7 +728,7 @@ ENTRY(__switch_to)
         ldr     r8, =__stack_chk_guard
         ldr     r7, [r7, #TSK_STACK_CANARY]
 #endif
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
         mcr     p15, 0, r6, c3, c0, 0           @ Set domain register
 #endif
         mov     r5, r0
@@ -842,7 +826,7 @@ __kuser_helper_start:
  */
 
 __kuser_memory_barrier:                         @ 0xffff0fa0
-        smp_dmb
+        smp_dmb arm
         usr_ret lr
 
         .align  5
@@ -959,7 +943,7 @@ kuser_cmpxchg_fixup:
 
 #else
 
-        smp_dmb
+        smp_dmb arm
 1:      ldrex   r3, [r2]
         subs    r3, r3, r0
         strexeq r3, r1, [r2]
@@ -1245,3 +1229,9 @@ cr_alignment:
         .space  4
 cr_no_alignment:
         .space  4
+
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+        .globl  handle_arch_irq
+handle_arch_irq:
+        .space  4
+#endif
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 80bf8cd88d7c..1e7b04a40a31 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -147,98 +147,170 @@ ENDPROC(ret_from_fork)
 #endif
 #endif
 
-#ifdef CONFIG_DYNAMIC_FTRACE
-ENTRY(__gnu_mcount_nc)
-        mov     ip, lr
-        ldmia   sp!, {lr}
-        mov     pc, ip
-ENDPROC(__gnu_mcount_nc)
+.macro __mcount suffix
+        mcount_enter
+        ldr     r0, =ftrace_trace_function
+        ldr     r2, [r0]
+        adr     r0, .Lftrace_stub
+        cmp     r0, r2
+        bne     1f
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+        ldr     r1, =ftrace_graph_return
+        ldr     r2, [r1]
+        cmp     r0, r2
+        bne     ftrace_graph_caller\suffix
+
+        ldr     r1, =ftrace_graph_entry
+        ldr     r2, [r1]
+        ldr     r0, =ftrace_graph_entry_stub
+        cmp     r0, r2
+        bne     ftrace_graph_caller\suffix
+#endif
 
-ENTRY(ftrace_caller)
-        stmdb   sp!, {r0-r3, lr}
-        mov     r0, lr
+        mcount_exit
+
+1:      mcount_get_lr   r1                      @ lr of instrumented func
+        mov     r0, lr                          @ instrumented function
+        sub     r0, r0, #MCOUNT_INSN_SIZE
+        adr     lr, BSYM(2f)
+        mov     pc, r2
+2:      mcount_exit
+.endm
+
+.macro __ftrace_caller suffix
+        mcount_enter
+
+        mcount_get_lr   r1                      @ lr of instrumented func
+        mov     r0, lr                          @ instrumented function
         sub     r0, r0, #MCOUNT_INSN_SIZE
-        ldr     r1, [sp, #20]
 
-        .global ftrace_call
-ftrace_call:
+        .globl ftrace_call\suffix
+ftrace_call\suffix:
         bl      ftrace_stub
-        ldmia   sp!, {r0-r3, ip, lr}
-        mov     pc, ip
-ENDPROC(ftrace_caller)
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+        .globl ftrace_graph_call\suffix
+ftrace_graph_call\suffix:
+        mov     r0, r0
+#endif
+
+        mcount_exit
+.endm
+
+.macro __ftrace_graph_caller
+        sub     r0, fp, #4              @ &lr of instrumented routine (&parent)
+#ifdef CONFIG_DYNAMIC_FTRACE
+        @ called from __ftrace_caller, saved in mcount_enter
+        ldr     r1, [sp, #16]           @ instrumented routine (func)
+#else
+        @ called from __mcount, untouched in lr
+        mov     r1, lr                  @ instrumented routine (func)
+#endif
+        sub     r1, r1, #MCOUNT_INSN_SIZE
+        mov     r2, fp                  @ frame pointer
+        bl      prepare_ftrace_return
+        mcount_exit
+.endm
 
 #ifdef CONFIG_OLD_MCOUNT
+/*
+ * mcount
+ */
+
+.macro mcount_enter
+        stmdb   sp!, {r0-r3, lr}
+.endm
+
+.macro mcount_get_lr reg
+        ldr     \reg, [fp, #-4]
+.endm
+
+.macro mcount_exit
+        ldr     lr, [fp, #-4]
+        ldmia   sp!, {r0-r3, pc}
+.endm
+
 ENTRY(mcount)
+#ifdef CONFIG_DYNAMIC_FTRACE
         stmdb   sp!, {lr}
         ldr     lr, [fp, #-4]
         ldmia   sp!, {pc}
+#else
+        __mcount _old
+#endif
 ENDPROC(mcount)
 
+#ifdef CONFIG_DYNAMIC_FTRACE
 ENTRY(ftrace_caller_old)
-        stmdb   sp!, {r0-r3, lr}
-        ldr     r1, [fp, #-4]
-        mov     r0, lr
-        sub     r0, r0, #MCOUNT_INSN_SIZE
-
-        .globl ftrace_call_old
-ftrace_call_old:
-        bl      ftrace_stub
-        ldr     lr, [fp, #-4]                   @ restore lr
-        ldmia   sp!, {r0-r3, pc}
+        __ftrace_caller _old
 ENDPROC(ftrace_caller_old)
 #endif
 
-#else
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+ENTRY(ftrace_graph_caller_old)
+        __ftrace_graph_caller
+ENDPROC(ftrace_graph_caller_old)
+#endif
 
-ENTRY(__gnu_mcount_nc)
+.purgem mcount_enter
+.purgem mcount_get_lr
+.purgem mcount_exit
+#endif
+
+/*
+ * __gnu_mcount_nc
+ */
+
+.macro mcount_enter
         stmdb   sp!, {r0-r3, lr}
-        ldr     r0, =ftrace_trace_function
-        ldr     r2, [r0]
-        adr     r0, .Lftrace_stub
-        cmp     r0, r2
-        bne     gnu_trace
+.endm
+
+.macro mcount_get_lr reg
+        ldr     \reg, [sp, #20]
+.endm
+
+.macro mcount_exit
         ldmia   sp!, {r0-r3, ip, lr}
         mov     pc, ip
+.endm
 
-gnu_trace:
-        ldr     r1, [sp, #20]                   @ lr of instrumented routine
-        mov     r0, lr
-        sub     r0, r0, #MCOUNT_INSN_SIZE
-        adr     lr, BSYM(1f)
-        mov     pc, r2
-1:
-        ldmia   sp!, {r0-r3, ip, lr}
+ENTRY(__gnu_mcount_nc)
+#ifdef CONFIG_DYNAMIC_FTRACE
+        mov     ip, lr
+        ldmia   sp!, {lr}
         mov     pc, ip
+#else
+        __mcount
+#endif
 ENDPROC(__gnu_mcount_nc)
 
-#ifdef CONFIG_OLD_MCOUNT
-/*
- * This is under an ifdef in order to force link-time errors for people trying
- * to build with !FRAME_POINTER with a GCC which doesn't use the new-style
- * mcount.
- */
-ENTRY(mcount)
-        stmdb   sp!, {r0-r3, lr}
-        ldr     r0, =ftrace_trace_function
-        ldr     r2, [r0]
-        adr     r0, ftrace_stub
-        cmp     r0, r2
-        bne     trace
-        ldr     lr, [fp, #-4]                   @ restore lr
-        ldmia   sp!, {r0-r3, pc}
+#ifdef CONFIG_DYNAMIC_FTRACE
+ENTRY(ftrace_caller)
+        __ftrace_caller
+ENDPROC(ftrace_caller)
+#endif
 
-trace:
-        ldr     r1, [fp, #-4]                   @ lr of instrumented routine
-        mov     r0, lr
-        sub     r0, r0, #MCOUNT_INSN_SIZE
-        mov     lr, pc
-        mov     pc, r2
-        ldr     lr, [fp, #-4]                   @ restore lr
-        ldmia   sp!, {r0-r3, pc}
-ENDPROC(mcount)
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+ENTRY(ftrace_graph_caller)
+        __ftrace_graph_caller
+ENDPROC(ftrace_graph_caller)
 #endif
 
-#endif /* CONFIG_DYNAMIC_FTRACE */
+.purgem mcount_enter
+.purgem mcount_get_lr
+.purgem mcount_exit
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+        .globl return_to_handler
+return_to_handler:
+        stmdb   sp!, {r0-r3}
+        mov     r0, fp                  @ frame pointer
+        bl      ftrace_return_to_handler
+        mov     lr, r0                  @ r0 has real ret addr
+        ldmia   sp!, {r0-r3}
+        mov     pc, lr
+#endif
 
 ENTRY(ftrace_stub)
 .Lftrace_stub:
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index d93f976fb389..ae9464900168 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -165,6 +165,25 @@
         .endm
 #endif  /* !CONFIG_THUMB2_KERNEL */
 
+        @
+        @ Debug exceptions are taken as prefetch or data aborts.
+        @ We must disable preemption during the handler so that
+        @ we can access the debug registers safely.
+        @
+        .macro  debug_entry, fsr
+#if defined(CONFIG_HAVE_HW_BREAKPOINT) && defined(CONFIG_PREEMPT)
+        ldr     r4, =0x40f              @ mask out fsr.fs
+        and     r5, r4, \fsr
+        cmp     r5, #2                  @ debug exception
+        bne     1f
+        get_thread_info r10
+        ldr     r6, [r10, #TI_PREEMPT]  @ get preempt count
+        add     r11, r6, #1             @ increment it
+        str     r11, [r10, #TI_PREEMPT]
+1:
+#endif
+        .endm
+
 /*
  * These are the registers used in the syscall handler, and allow us to
  * have in theory up to 7 arguments to a function - r0 to r6.
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 6ff7919613d7..e72dc34eea1c 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -45,6 +45,7 @@
 #include <asm/fiq.h>
 #include <asm/irq.h>
 #include <asm/system.h>
+#include <asm/traps.h>
 
 static unsigned long no_fiq_insn;
 
@@ -67,17 +68,22 @@ static struct fiq_handler default_owner = {
 
 static struct fiq_handler *current_fiq = &default_owner;
 
-int show_fiq_list(struct seq_file *p, void *v)
+int show_fiq_list(struct seq_file *p, int prec)
 {
         if (current_fiq != &default_owner)
-                seq_printf(p, "FIQ:              %s\n", current_fiq->name);
+                seq_printf(p, "%*s:              %s\n", prec, "FIQ",
+                        current_fiq->name);
 
         return 0;
 }
 
 void set_fiq_handler(void *start, unsigned int length)
 {
+#if defined(CONFIG_CPU_USE_DOMAINS)
         memcpy((void *)0xffff001c, start, length);
+#else
+        memcpy(vectors_page + 0x1c, start, length);
+#endif
         flush_icache_range(0xffff001c, 0xffff001c + length);
         if (!vectors_high())
                 flush_icache_range(0x1c, 0x1c + length);
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
index 971ac8c36ea7..c0062ad1e847 100644
--- a/arch/arm/kernel/ftrace.c
+++ b/arch/arm/kernel/ftrace.c
@@ -24,6 +24,7 @@
 #define NOP             0xe8bd4000      /* pop {lr} */
 #endif
 
+#ifdef CONFIG_DYNAMIC_FTRACE
 #ifdef CONFIG_OLD_MCOUNT
 #define OLD_MCOUNT_ADDR ((unsigned long) mcount)
 #define OLD_FTRACE_ADDR ((unsigned long) ftrace_caller_old)
@@ -59,9 +60,9 @@ static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr)
 }
 #endif
 
-/* construct a branch (BL) instruction to addr */
 #ifdef CONFIG_THUMB2_KERNEL
-static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
+static unsigned long ftrace_gen_branch(unsigned long pc, unsigned long addr,
+                                       bool link)
 {
         unsigned long s, j1, j2, i1, i2, imm10, imm11;
         unsigned long first, second;
@@ -83,15 +84,22 @@ static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
         j2 = (!i2) ^ s;
 
         first = 0xf000 | (s << 10) | imm10;
-        second = 0xd000 | (j1 << 13) | (j2 << 11) | imm11;
+        second = 0x9000 | (j1 << 13) | (j2 << 11) | imm11;
+        if (link)
+                second |= 1 << 14;
 
         return (second << 16) | first;
 }
 #else
-static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
+static unsigned long ftrace_gen_branch(unsigned long pc, unsigned long addr,
+                                       bool link)
 {
+        unsigned long opcode = 0xea000000;
         long offset;
 
+        if (link)
+                opcode |= 1 << 24;
+
         offset = (long)addr - (long)(pc + 8);
         if (unlikely(offset < -33554432 || offset > 33554428)) {
                 /* Can't generate branches that far (from ARM ARM). Ftrace
@@ -103,10 +111,15 @@ static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
 
         offset = (offset >> 2) & 0x00ffffff;
 
-        return 0xeb000000 | offset;
+        return opcode | offset;
 }
 #endif
 
+static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
+{
+        return ftrace_gen_branch(pc, addr, true);
+}
+
 static int ftrace_modify_code(unsigned long pc, unsigned long old,
                               unsigned long new)
 {
@@ -193,3 +206,83 @@ int __init ftrace_dyn_arch_init(void *data)
 
         return 0;
 }
+#endif /* CONFIG_DYNAMIC_FTRACE */
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
+                           unsigned long frame_pointer)
+{
+        unsigned long return_hooker = (unsigned long) &return_to_handler;
+        struct ftrace_graph_ent trace;
+        unsigned long old;
+        int err;
+
+        if (unlikely(atomic_read(&current->tracing_graph_pause)))
+                return;
+
+        old = *parent;
+        *parent = return_hooker;
+
+        err = ftrace_push_return_trace(old, self_addr, &trace.depth,
+                                       frame_pointer);
+        if (err == -EBUSY) {
+                *parent = old;
+                return;
+        }
+
+        trace.func = self_addr;
+
+        /* Only trace if the calling function expects to */
+        if (!ftrace_graph_entry(&trace)) {
+                current->curr_ret_stack--;
+                *parent = old;
+        }
+}
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+extern unsigned long ftrace_graph_call;
+extern unsigned long ftrace_graph_call_old;
+extern void ftrace_graph_caller_old(void);
+
+static int __ftrace_modify_caller(unsigned long *callsite,
+                                  void (*func) (void), bool enable)
+{
+        unsigned long caller_fn = (unsigned long) func;
+        unsigned long pc = (unsigned long) callsite;
+        unsigned long branch = ftrace_gen_branch(pc, caller_fn, false);
+        unsigned long nop = 0xe1a00000; /* mov r0, r0 */
+        unsigned long old = enable ? nop : branch;
+        unsigned long new = enable ? branch : nop;
+
+        return ftrace_modify_code(pc, old, new);
+}
+
+static int ftrace_modify_graph_caller(bool enable)
+{
+        int ret;
+
+        ret = __ftrace_modify_caller(&ftrace_graph_call,
+                                     ftrace_graph_caller,
+                                     enable);
+
+#ifdef CONFIG_OLD_MCOUNT
+        if (!ret)
+                ret = __ftrace_modify_caller(&ftrace_graph_call_old,
+                                             ftrace_graph_caller_old,
+                                             enable);
+#endif
+
+        return ret;
+}
+
+int ftrace_enable_ftrace_graph_caller(void)
+{
+        return ftrace_modify_graph_caller(true);
+}
+
+int ftrace_disable_ftrace_graph_caller(void)
+{
+        return ftrace_modify_graph_caller(false);
+}
+#endif /* CONFIG_DYNAMIC_FTRACE */
+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 6bd82d25683c..f17d9a09e8fb 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -91,6 +91,11 @@ ENTRY(stext)
         movs    r8, r5                          @ invalid machine (r5=0)?
  THUMB( it      eq )            @ force fixup-able long branch encoding
         beq     __error_a                       @ yes, error 'a'
+
+        /*
+         * r1 = machine no, r2 = atags,
+         * r8 = machinfo, r9 = cpuid, r10 = procinfo
+         */
         bl      __vet_atags
 #ifdef CONFIG_SMP_ON_UP
         bl      __fixup_smp
@@ -387,19 +392,19 @@ ENDPROC(__turn_mmu_on)
 
 #ifdef CONFIG_SMP_ON_UP
 __fixup_smp:
-        mov     r7, #0x00070000
-        orr     r6, r7, #0xff000000     @ mask 0xff070000
-        orr     r7, r7, #0x41000000     @ val 0x41070000
-        and     r0, r9, r6
-        teq     r0, r7                  @ ARM CPU and ARMv6/v7?
+        mov     r4, #0x00070000
+        orr     r3, r4, #0xff000000     @ mask 0xff070000
+        orr     r4, r4, #0x41000000     @ val 0x41070000
+        and     r0, r9, r3
+        teq     r0, r4                  @ ARM CPU and ARMv6/v7?
         bne     __fixup_smp_on_up       @ no, assume UP
 
-        orr     r6, r6, #0x0000ff00
-        orr     r6, r6, #0x000000f0     @ mask 0xff07fff0
-        orr     r7, r7, #0x0000b000
-        orr     r7, r7, #0x00000020     @ val 0x4107b020
-        and     r0, r9, r6
-        teq     r0, r7                  @ ARM 11MPCore?
+        orr     r3, r3, #0x0000ff00
+        orr     r3, r3, #0x000000f0     @ mask 0xff07fff0
+        orr     r4, r4, #0x0000b000
+        orr     r4, r4, #0x00000020     @ val 0x4107b020
+        and     r0, r9, r3
+        teq     r0, r4                  @ ARM 11MPCore?
         moveq   pc, lr                  @ yes, assume SMP
 
         mrc     p15, 0, r0, c0, c0, 5   @ read MPIDR
@@ -408,15 +413,22 @@ __fixup_smp:
 
 __fixup_smp_on_up:
         adr     r0, 1f
-        ldmia   r0, {r3, r6, r7}
+        ldmia   r0, {r3 - r5}
         sub     r3, r0, r3
-        add     r6, r6, r3
-        add     r7, r7, r3
-2:      cmp     r6, r7
-        ldmia   r6!, {r0, r4}
-        strlo   r4, [r0, r3]
-        blo     2b
-        mov     pc, lr
+        add     r4, r4, r3
+        add     r5, r5, r3
+2:      cmp     r4, r5
+        movhs   pc, lr
+        ldmia   r4!, {r0, r6}
+ ARM(   str     r6, [r0, r3]    )
+ THUMB( add     r0, r0, r3      )
+#ifdef __ARMEB__
+ THUMB( mov     r6, r6, ror #16 )       @ Convert word order for big-endian.
+#endif
+ THUMB( strh    r6, [r0], #2    )       @ For Thumb-2, store as two halfwords
+ THUMB( mov     r6, r6, lsr #16 )       @ to be robust against misaligned r3.
+ THUMB( strh    r6, [r0]        )
+        b       2b
 ENDPROC(__fixup_smp)
 
         .align
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 21e3a4ab3b8c..c9f3f0467570 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -24,6 +24,7 @@
 #define pr_fmt(fmt) "hw-breakpoint: " fmt
 
 #include <linux/errno.h>
+#include <linux/hardirq.h>
 #include <linux/perf_event.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/smp.h>
@@ -44,6 +45,7 @@ static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
 
 /* Number of BRP/WRP registers on this CPU. */
 static int core_num_brps;
+static int core_num_reserved_brps;
 static int core_num_wrps;
 
 /* Debug architecture version. */
@@ -52,87 +54,6 @@ static u8 debug_arch;
 /* Maximum supported watchpoint length. */
 static u8 max_watchpoint_len;
 
-/* Determine number of BRP registers available. */
-static int get_num_brps(void)
-{
-        u32 didr;
-        ARM_DBG_READ(c0, 0, didr);
-        return ((didr >> 24) & 0xf) + 1;
-}
-
-/* Determine number of WRP registers available. */
-static int get_num_wrps(void)
-{
-        /*
-         * FIXME: When a watchpoint fires, the only way to work out which
-         * watchpoint it was is by disassembling the faulting instruction
-         * and working out the address of the memory access.
-         *
-         * Furthermore, we can only do this if the watchpoint was precise
-         * since imprecise watchpoints prevent us from calculating register
-         * based addresses.
-         *
-         * For the time being, we only report 1 watchpoint register so we
-         * always know which watchpoint fired. In the future we can either
-         * add a disassembler and address generation emulator, or we can
-         * insert a check to see if the DFAR is set on watchpoint exception
-         * entry [the ARM ARM states that the DFAR is UNKNOWN, but
-         * experience shows that it is set on some implementations].
-         */
-
-#if 0
-        u32 didr, wrps;
-        ARM_DBG_READ(c0, 0, didr);
-        return ((didr >> 28) & 0xf) + 1;
-#endif
-
-        return 1;
-}
-
-int hw_breakpoint_slots(int type)
-{
-        /*
-         * We can be called early, so don't rely on
-         * our static variables being initialised.
-         */
-        switch (type) {
-        case TYPE_INST:
-                return get_num_brps();
-        case TYPE_DATA:
-                return get_num_wrps();
-        default:
-                pr_warning("unknown slot type: %d\n", type);
-                return 0;
-        }
-}
-
-/* Determine debug architecture. */
-static u8 get_debug_arch(void)
-{
-        u32 didr;
-
-        /* Do we implement the extended CPUID interface? */
-        if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
-                pr_warning("CPUID feature registers not supported. "
-                                "Assuming v6 debug is present.\n");
-                return ARM_DEBUG_ARCH_V6;
-        }
-
-        ARM_DBG_READ(c0, 0, didr);
-        return (didr >> 16) & 0xf;
-}
-
-/* Does this core support mismatch breakpoints? */
-static int core_has_mismatch_bps(void)
-{
-        return debug_arch >= ARM_DEBUG_ARCH_V7_ECP14 && core_num_brps > 1;
-}
-
-u8 arch_get_debug_arch(void)
-{
-        return debug_arch;
-}
-
 #define READ_WB_REG_CASE(OP2, M, VAL)           \
         case ((OP2 << 4) + M):                  \
                 ARM_DBG_READ(c ## M, OP2, VAL); \
@@ -210,6 +131,94 @@ static void write_wb_reg(int n, u32 val)
         isb();
 }
 
+/* Determine debug architecture. */
+static u8 get_debug_arch(void)
+{
+        u32 didr;
+
+        /* Do we implement the extended CPUID interface? */
+        if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
+                pr_warning("CPUID feature registers not supported. "
+                                "Assuming v6 debug is present.\n");
+                return ARM_DEBUG_ARCH_V6;
+        }
+
+        ARM_DBG_READ(c0, 0, didr);
+        return (didr >> 16) & 0xf;
+}
+
+u8 arch_get_debug_arch(void)
+{
+        return debug_arch;
+}
+
+/* Determine number of BRP register available. */
+static int get_num_brp_resources(void)
+{
+        u32 didr;
+        ARM_DBG_READ(c0, 0, didr);
+        return ((didr >> 24) & 0xf) + 1;
+}
+
+/* Does this core support mismatch breakpoints? */
+static int core_has_mismatch_brps(void)
+{
+        return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
+                get_num_brp_resources() > 1);
+}
+
+/* Determine number of usable WRPs available. */
+static int get_num_wrps(void)
+{
+        /*
+         * FIXME: When a watchpoint fires, the only way to work out which
+         * watchpoint it was is by disassembling the faulting instruction
+         * and working out the address of the memory access.
+         *
+         * Furthermore, we can only do this if the watchpoint was precise
+         * since imprecise watchpoints prevent us from calculating register
+         * based addresses.
+         *
+         * Providing we have more than 1 breakpoint register, we only report
+         * a single watchpoint register for the time being. This way, we always
+         * know which watchpoint fired. In the future we can either add a
+         * disassembler and address generation emulator, or we can insert a
+         * check to see if the DFAR is set on watchpoint exception entry
+         * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
+         * that it is set on some implementations].
+         */
+
+#if 0
+        int wrps;
+        u32 didr;
+        ARM_DBG_READ(c0, 0, didr);
+        wrps = ((didr >> 28) & 0xf) + 1;
+#endif
+        int wrps = 1;
+
+        if (core_has_mismatch_brps() && wrps >= get_num_brp_resources())
+                wrps = get_num_brp_resources() - 1;
+
+        return wrps;
+}
+
+/* We reserve one breakpoint for each watchpoint. */
+static int get_num_reserved_brps(void)
+{
+        if (core_has_mismatch_brps())
+                return get_num_wrps();
+        return 0;
+}
+
+/* Determine number of usable BRPs available. */
+static int get_num_brps(void)
+{
+        int brps = get_num_brp_resources();
+        if (core_has_mismatch_brps())
+                brps -= get_num_reserved_brps();
+        return brps;
+}
+
 /*
  * In order to access the breakpoint/watchpoint control registers,
  * we must be running in debug monitor mode. Unfortunately, we can
@@ -230,8 +239,12 @@ static int enable_monitor_mode(void)
                 goto out;
         }
 
+        /* If monitor mode is already enabled, just return. */
+        if (dscr & ARM_DSCR_MDBGEN)
+                goto out;
+
         /* Write to the corresponding DSCR. */
-        switch (debug_arch) {
+        switch (get_debug_arch()) {
         case ARM_DEBUG_ARCH_V6:
         case ARM_DEBUG_ARCH_V6_1:
                 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
@@ -246,15 +259,30 @@ static int enable_monitor_mode(void)
 
         /* Check that the write made it through. */
         ARM_DBG_READ(c1, 0, dscr);
-        if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN),
-                                "failed to enable monitor mode.")) {
+        if (!(dscr & ARM_DSCR_MDBGEN))
                 ret = -EPERM;
-        }
 
 out:
         return ret;
 }
 
+int hw_breakpoint_slots(int type)
+{
+        /*
+         * We can be called early, so don't rely on
+         * our static variables being initialised.
+         */
+        switch (type) {
+        case TYPE_INST:
+                return get_num_brps();
+        case TYPE_DATA:
+                return get_num_wrps();
+        default:
+                pr_warning("unknown slot type: %d\n", type);
+                return 0;
+        }
+}
+
 /*
  * Check if 8-bit byte-address select is available.
  * This clobbers WRP 0.
@@ -268,9 +296,6 @@ static u8 get_max_wp_len(void)
         if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
                 goto out;
 
-        if (enable_monitor_mode())
-                goto out;
-
         memset(&ctrl, 0, sizeof(ctrl));
         ctrl.len = ARM_BREAKPOINT_LEN_8;
         ctrl_reg = encode_ctrl_reg(ctrl);
@@ -290,23 +315,6 @@ u8 arch_get_max_wp_len(void)
 }
 
 /*
- * Handler for reactivating a suspended watchpoint when the single
- * step `mismatch' breakpoint is triggered.
- */
-static void wp_single_step_handler(struct perf_event *bp, int unused,
-                                   struct perf_sample_data *data,
-                                   struct pt_regs *regs)
-{
-        perf_event_enable(counter_arch_bp(bp)->suspended_wp);
-        unregister_hw_breakpoint(bp);
-}
-
-static int bp_is_single_step(struct perf_event *bp)
-{
-        return bp->overflow_handler == wp_single_step_handler;
-}
-
-/*
  * Install a perf counter breakpoint.
  */
 int arch_install_hw_breakpoint(struct perf_event *bp)
@@ -314,30 +322,41 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
         struct perf_event **slot, **slots;
         int i, max_slots, ctrl_base, val_base, ret = 0;
+        u32 addr, ctrl;
 
         /* Ensure that we are in monitor mode and halting mode is disabled. */
         ret = enable_monitor_mode();
         if (ret)
                 goto out;
 
+        addr = info->address;
+        ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
+
         if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
                 /* Breakpoint */
                 ctrl_base = ARM_BASE_BCR;
                 val_base = ARM_BASE_BVR;
-                slots = __get_cpu_var(bp_on_reg);
-                max_slots = core_num_brps - 1;
-
-                if (bp_is_single_step(bp)) {
-                        info->ctrl.mismatch = 1;
-                        i = max_slots;
-                        slots[i] = bp;
-                        goto setup;
+                slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
+                max_slots = core_num_brps;
+                if (info->step_ctrl.enabled) {
+                        /* Override the breakpoint data with the step data. */
+                        addr = info->trigger & ~0x3;
+                        ctrl = encode_ctrl_reg(info->step_ctrl);
                 }
         } else {
                 /* Watchpoint */
-                ctrl_base = ARM_BASE_WCR;
-                val_base = ARM_BASE_WVR;
-                slots = __get_cpu_var(wp_on_reg);
+                if (info->step_ctrl.enabled) {
+                        /* Install into the reserved breakpoint region. */
+                        ctrl_base = ARM_BASE_BCR + core_num_brps;
+                        val_base = ARM_BASE_BVR + core_num_brps;
+                        /* Override the watchpoint data with the step data. */
+                        addr = info->trigger & ~0x3;
+                        ctrl = encode_ctrl_reg(info->step_ctrl);
+                } else {
+                        ctrl_base = ARM_BASE_WCR;
+                        val_base = ARM_BASE_WVR;
+                }
+                slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
                 max_slots = core_num_wrps;
         }
 
@@ -355,12 +374,11 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
                 goto out;
         }
 
-setup:
         /* Setup the address register. */
-        write_wb_reg(val_base + i, info->address);
+        write_wb_reg(val_base + i, addr);
 
         /* Setup the control register. */
-        write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl) | 0x1);
+        write_wb_reg(ctrl_base + i, ctrl);
 
 out:
         return ret;
@@ -375,18 +393,15 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
         if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
                 /* Breakpoint */
                 base = ARM_BASE_BCR;
-                slots = __get_cpu_var(bp_on_reg);
-                max_slots = core_num_brps - 1;
-
-                if (bp_is_single_step(bp)) {
-                        i = max_slots;
-                        slots[i] = NULL;
-                        goto reset;
-                }
+                slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
+                max_slots = core_num_brps;
         } else {
                 /* Watchpoint */
-                base = ARM_BASE_WCR;
-                slots = __get_cpu_var(wp_on_reg);
+                if (info->step_ctrl.enabled)
+                        base = ARM_BASE_BCR + core_num_brps;
+                else
+                        base = ARM_BASE_WCR;
+                slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
                 max_slots = core_num_wrps;
         }
 
@@ -403,7 +418,6 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
         if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
                 return;
 
-reset:
         /* Reset the control register. */
         write_wb_reg(base + i, 0);
 }
@@ -537,12 +551,23 @@ static int arch_build_bp_info(struct perf_event *bp)
                 return -EINVAL;
         }
 
+        /*
+         * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
+         * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
+         * by the hardware and must be aligned to the appropriate number of
+         * bytes.
+         */
+        if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
+            info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
+            info->ctrl.len != ARM_BREAKPOINT_LEN_4)
+                return -EINVAL;
+
         /* Address */
         info->address = bp->attr.bp_addr;
 
         /* Privilege */
         info->ctrl.privilege = ARM_BREAKPOINT_USER;
-        if (arch_check_bp_in_kernelspace(bp) && !bp_is_single_step(bp))
+        if (arch_check_bp_in_kernelspace(bp))
                 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
 
         /* Enabled? */
@@ -561,7 +586,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
 {
         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
         int ret = 0;
-        u32 bytelen, max_len, offset, alignment_mask = 0x3;
+        u32 offset, alignment_mask = 0x3;
 
         /* Build the arch_hw_breakpoint. */
         ret = arch_build_bp_info(bp);
@@ -571,84 +596,85 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
         /* Check address alignment. */
         if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
                 alignment_mask = 0x7;
-        if (info->address & alignment_mask) {
-                /*
-                 * Try to fix the alignment. This may result in a length
-                 * that is too large, so we must check for that.
-                 */
-                bytelen = get_hbp_len(info->ctrl.len);
-                max_len = info->ctrl.type == ARM_BREAKPOINT_EXECUTE ? 4 :
-                                max_watchpoint_len;
-
-                if (max_len >= 8)
-                        offset = info->address & 0x7;
-                else
-                        offset = info->address & 0x3;
-
-                if (bytelen > (1 << ((max_len - (offset + 1)) >> 1))) {
-                        ret = -EFBIG;
-                        goto out;
-                }
-
-                info->ctrl.len <<= offset;
-                info->address &= ~offset;
-
-                pr_debug("breakpoint alignment fixup: length = 0x%x, "
-                        "address = 0x%x\n", info->ctrl.len, info->address);
+        offset = info->address & alignment_mask;
+        switch (offset) {
+        case 0:
+                /* Aligned */
+                break;
+        case 1:
+                /* Allow single byte watchpoint. */
+                if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
+                        break;
+        case 2:
+                /* Allow halfword watchpoints and breakpoints. */
+                if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
+                        break;
+        default:
+                ret = -EINVAL;
+                goto out;
         }
 
+        info->address &= ~alignment_mask;
+        info->ctrl.len <<= offset;
+
         /*
          * Currently we rely on an overflow handler to take
          * care of single-stepping the breakpoint when it fires.
          * In the case of userspace breakpoints on a core with V7 debug,
-         * we can use the mismatch feature as a poor-man's hardware single-step.
+         * we can use the mismatch feature as a poor-man's hardware
+         * single-step, but this only works for per-task breakpoints.
          */
         if (WARN_ONCE(!bp->overflow_handler &&
-                (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_bps()),
+                (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps()
+                 || !bp->hw.bp_target),
                         "overflow handler required but none found")) {
                 ret = -EINVAL;
-                goto out;
         }
 out:
         return ret;
 }
 
-static void update_mismatch_flag(int idx, int flag)
+/*
+ * Enable/disable single-stepping over the breakpoint bp at address addr.
+ */
+static void enable_single_step(struct perf_event *bp, u32 addr)
 {
-        struct perf_event *bp = __get_cpu_var(bp_on_reg[idx]);
-        struct arch_hw_breakpoint *info;
-
-        if (bp == NULL)
-                return;
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 
-        info = counter_arch_bp(bp);
+        arch_uninstall_hw_breakpoint(bp);
+        info->step_ctrl.mismatch  = 1;
+        info->step_ctrl.len       = ARM_BREAKPOINT_LEN_4;
+        info->step_ctrl.type      = ARM_BREAKPOINT_EXECUTE;
+        info->step_ctrl.privilege = info->ctrl.privilege;
+        info->step_ctrl.enabled   = 1;
+        info->trigger             = addr;
+        arch_install_hw_breakpoint(bp);
+}
 
-        /* Update the mismatch field to enter/exit `single-step' mode */
-        if (!bp->overflow_handler && info->ctrl.mismatch != flag) {
-                info->ctrl.mismatch = flag;
-                write_wb_reg(ARM_BASE_BCR + idx, encode_ctrl_reg(info->ctrl) | 0x1);
-        }
+static void disable_single_step(struct perf_event *bp)
+{
+        arch_uninstall_hw_breakpoint(bp);
+        counter_arch_bp(bp)->step_ctrl.enabled = 0;
+        arch_install_hw_breakpoint(bp);
 }
 
 static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
 {
         int i;
-        struct perf_event *bp, **slots = __get_cpu_var(wp_on_reg);
+        struct perf_event *wp, **slots;
         struct arch_hw_breakpoint *info;
-        struct perf_event_attr attr;
+
+        slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
 
         /* Without a disassembler, we can only handle 1 watchpoint. */
         BUG_ON(core_num_wrps > 1);
 
-        hw_breakpoint_init(&attr);
-        attr.bp_addr    = regs->ARM_pc & ~0x3;
-        attr.bp_len     = HW_BREAKPOINT_LEN_4;
-        attr.bp_type    = HW_BREAKPOINT_X;
-
         for (i = 0; i < core_num_wrps; ++i) {
                 rcu_read_lock();
 
-                if (slots[i] == NULL) {
+                wp = slots[i];
+
+                if (wp == NULL) {
                         rcu_read_unlock();
                         continue;
                 }
@@ -658,24 +684,51 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
                  * single watchpoint, we can set the trigger to the lowest
                  * possible faulting address.
                  */
-                info = counter_arch_bp(slots[i]);
-                info->trigger = slots[i]->attr.bp_addr;
+                info = counter_arch_bp(wp);
+                info->trigger = wp->attr.bp_addr;
                 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
-                perf_bp_event(slots[i], regs);
+                perf_bp_event(wp, regs);
 
                 /*
                  * If no overflow handler is present, insert a temporary
                  * mismatch breakpoint so we can single-step over the
                  * watchpoint trigger.
                  */
-                if (!slots[i]->overflow_handler) {
-                        bp = register_user_hw_breakpoint(&attr,
-                                                         wp_single_step_handler,
-                                                         current);
-                        counter_arch_bp(bp)->suspended_wp = slots[i];
-                        perf_event_disable(slots[i]);
-                }
+                if (!wp->overflow_handler)
+                        enable_single_step(wp, instruction_pointer(regs));
+
+                rcu_read_unlock();
+        }
+}
 
+static void watchpoint_single_step_handler(unsigned long pc)
+{
+        int i;
+        struct perf_event *wp, **slots;
+        struct arch_hw_breakpoint *info;
+
+        slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
+
+        for (i = 0; i < core_num_reserved_brps; ++i) {
+                rcu_read_lock();
+
+                wp = slots[i];
+
+                if (wp == NULL)
+                        goto unlock;
+
+                info = counter_arch_bp(wp);
+                if (!info->step_ctrl.enabled)
+                        goto unlock;
+
+                /*
+                 * Restore the original watchpoint if we've completed the
+                 * single-step.
+                 */
+                if (info->trigger != pc)
+                        disable_single_step(wp);
+
+unlock:
                 rcu_read_unlock();
         }
 }
@@ -683,62 +736,69 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
 static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
 {
         int i;
-        int mismatch;
         u32 ctrl_reg, val, addr;
-        struct perf_event *bp, **slots = __get_cpu_var(bp_on_reg);
+        struct perf_event *bp, **slots;
         struct arch_hw_breakpoint *info;
         struct arch_hw_breakpoint_ctrl ctrl;
 
+        slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
+
         /* The exception entry code places the amended lr in the PC. */
         addr = regs->ARM_pc;
 
+        /* Check the currently installed breakpoints first. */
         for (i = 0; i < core_num_brps; ++i) {
                 rcu_read_lock();
 
                 bp = slots[i];
 
-                if (bp == NULL) {
-                        rcu_read_unlock();
-                        continue;
-                }
+                if (bp == NULL)
+                        goto unlock;
 
-                mismatch = 0;
+                info = counter_arch_bp(bp);
 
                 /* Check if the breakpoint value matches. */
                 val = read_wb_reg(ARM_BASE_BVR + i);
                 if (val != (addr & ~0x3))
-                        goto unlock;
+                        goto mismatch;
 
                 /* Possible match, check the byte address select to confirm. */
                 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
                 decode_ctrl_reg(ctrl_reg, &ctrl);
                 if ((1 << (addr & 0x3)) & ctrl.len) {
-                        mismatch = 1;
-                        info = counter_arch_bp(bp);
                         info->trigger = addr;
-                }
-
-unlock:
-                if ((mismatch && !info->ctrl.mismatch) || bp_is_single_step(bp)) {
                         pr_debug("breakpoint fired: address = 0x%x\n", addr);
                         perf_bp_event(bp, regs);
+                        if (!bp->overflow_handler)
+                                enable_single_step(bp, addr);
+                        goto unlock;
                 }
 
-                update_mismatch_flag(i, mismatch);
+mismatch:
+                /* If we're stepping a breakpoint, it can now be restored. */
+                if (info->step_ctrl.enabled)
+                        disable_single_step(bp);
+unlock:
                 rcu_read_unlock();
         }
+
+        /* Handle any pending watchpoint single-step breakpoints. */
+        watchpoint_single_step_handler(addr);
 }
 
 /*
  * Called from either the Data Abort Handler [watchpoint] or the
- * Prefetch Abort Handler [breakpoint].
+ * Prefetch Abort Handler [breakpoint] with preemption disabled.
  */
 static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
                                  struct pt_regs *regs)
 {
-        int ret = 1; /* Unhandled fault. */
+        int ret = 0;
         u32 dscr;
 
+        /* We must be called with preemption disabled. */
+        WARN_ON(preemptible());
+
         /* We only handle watchpoints and hardware breakpoints. */
         ARM_DBG_READ(c1, 0, dscr);
 
@@ -753,25 +813,47 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
                 watchpoint_handler(addr, regs);
                 break;
         default:
-                goto out;
+                ret = 1; /* Unhandled fault. */
         }
 
-        ret = 0;
-out:
+        /*
+         * Re-enable preemption after it was disabled in the
+         * low-level exception handling code.
+         */
+        preempt_enable();
+
         return ret;
 }
 
 /*
  * One-time initialisation.
  */
-static void __init reset_ctrl_regs(void *unused)
+static void reset_ctrl_regs(void *unused)
 {
         int i;
 
+        /*
+         * v7 debug contains save and restore registers so that debug state
+         * can be maintained across low-power modes without leaving
+         * the debug logic powered up. It is IMPLEMENTATION DEFINED whether
+         * we can write to the debug registers out of reset, so we must
+         * unlock the OS Lock Access Register to avoid taking undefined
+         * instruction exceptions later on.
+         */
+        if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
+                /*
+                 * Unconditionally clear the lock by writing a value
+                 * other than 0xC5ACCE55 to the access register.
+                 */
+                asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
+                isb();
+        }
+
         if (enable_monitor_mode())
                 return;
 
-        for (i = 0; i < core_num_brps; ++i) {
+        /* We must also reset any reserved registers. */
+        for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) {
                 write_wb_reg(ARM_BASE_BCR + i, 0UL);
                 write_wb_reg(ARM_BASE_BVR + i, 0UL);
         }
@@ -782,45 +864,57 @@ static void __init reset_ctrl_regs(void *unused)
         }
 }
 
+static int __cpuinit dbg_reset_notify(struct notifier_block *self,
+                                      unsigned long action, void *cpu)
+{
+        if (action == CPU_ONLINE)
+                smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
+        return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata dbg_reset_nb = {
+        .notifier_call = dbg_reset_notify,
+};
+
 static int __init arch_hw_breakpoint_init(void)
 {
-        int ret = 0;
         u32 dscr;
 
         debug_arch = get_debug_arch();
 
         if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) {
                 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
-                ret = -ENODEV;
-                goto out;
+                return 0;
         }
 
         /* Determine how many BRPs/WRPs are available. */
         core_num_brps = get_num_brps();
+        core_num_reserved_brps = get_num_reserved_brps();
         core_num_wrps = get_num_wrps();
 
         pr_info("found %d breakpoint and %d watchpoint registers.\n",
-                        core_num_brps, core_num_wrps);
+                core_num_brps + core_num_reserved_brps, core_num_wrps);
 
-        if (core_has_mismatch_bps())
-                pr_info("1 breakpoint reserved for watchpoint single-step.\n");
+        if (core_num_reserved_brps)
+                pr_info("%d breakpoint(s) reserved for watchpoint "
+                                "single-step.\n", core_num_reserved_brps);
 
         ARM_DBG_READ(c1, 0, dscr);
         if (dscr & ARM_DSCR_HDBGEN) {
                 pr_warning("halting debug mode enabled. Assuming maximum "
                                 "watchpoint size of 4 bytes.");
         } else {
-                /* Work out the maximum supported watchpoint length. */
-                max_watchpoint_len = get_max_wp_len();
-                pr_info("maximum watchpoint size is %u bytes.\n",
-                                max_watchpoint_len);
-
                 /*
                  * Reset the breakpoint resources. We assume that a halting
                  * debugger will leave the world in a nice state for us.
                  */
                 smp_call_function(reset_ctrl_regs, NULL, 1);
                 reset_ctrl_regs(NULL);
+
+                /* Work out the maximum supported watchpoint length. */
+                max_watchpoint_len = get_max_wp_len();
+                pr_info("maximum watchpoint size is %u bytes.\n",
+                                max_watchpoint_len);
         }
 
         /* Register debug fault handler. */
@@ -829,8 +923,9 @@ static int __init arch_hw_breakpoint_init(void)
         hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
                         "breakpoint debug exception");
 
-out:
-        return ret;
+        /* Register hotplug notifier. */
+        register_cpu_notifier(&dbg_reset_nb);
+        return 0;
 }
 arch_initcall(arch_hw_breakpoint_init);
 
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 36ad3be4692a..8135438b8818 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -35,8 +35,10 @@
 #include <linux/list.h>
 #include <linux/kallsyms.h>
 #include <linux/proc_fs.h>
+#include <linux/ftrace.h>
 
 #include <asm/system.h>
+#include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 
@@ -47,8 +49,6 @@
 #define irq_finish(irq) do { } while (0)
 #endif
 
-unsigned int arch_nr_irqs;
-void (*init_arch_irq)(void) __initdata = NULL;
 unsigned long irq_err_count;
 
 int show_interrupts(struct seq_file *p, void *v)
@@ -57,11 +57,20 @@ int show_interrupts(struct seq_file *p, void *v)
         struct irq_desc *desc;
         struct irqaction * action;
         unsigned long flags;
+        int prec, n;
+
+        for (prec = 3, n = 1000; prec < 10 && n <= nr_irqs; prec++)
+                n *= 10;
+
+#ifdef CONFIG_SMP
+        if (prec < 4)
+                prec = 4;
+#endif
 
         if (i == 0) {
                 char cpuname[12];
 
-                seq_printf(p, "    ");
+                seq_printf(p, "%*s ", prec, "");
                 for_each_present_cpu(cpu) {
                         sprintf(cpuname, "CPU%d", cpu);
                         seq_printf(p, " %10s", cpuname);
@@ -76,7 +85,7 @@ int show_interrupts(struct seq_file *p, void *v)
                 if (!action)
                         goto unlock;
 
-                seq_printf(p, "%3d: ", i);
+                seq_printf(p, "%*d: ", prec, i);
                 for_each_present_cpu(cpu)
                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
                 seq_printf(p, " %10s", desc->chip->name ? : "-");
@@ -89,13 +98,15 @@ unlock:
                 raw_spin_unlock_irqrestore(&desc->lock, flags);
         } else if (i == nr_irqs) {
 #ifdef CONFIG_FIQ
-                show_fiq_list(p, v);
+                show_fiq_list(p, prec);
 #endif
 #ifdef CONFIG_SMP
-                show_ipi_list(p);
-                show_local_irqs(p);
+                show_ipi_list(p, prec);
+#endif
+#ifdef CONFIG_LOCAL_TIMERS
+                show_local_irqs(p, prec);
 #endif
-                seq_printf(p, "Err: %10lu\n", irq_err_count);
+                seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
         }
         return 0;
 }
@@ -105,7 +116,8 @@ unlock:
  * come via this function.  Instead, they should provide their
  * own 'handler'
  */
-asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
+asmlinkage void __exception_irq_entry
+asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
 {
         struct pt_regs *old_regs = set_irq_regs(regs);
 
@@ -154,13 +166,13 @@ void set_irq_flags(unsigned int irq, unsigned int iflags)
 
 void __init init_IRQ(void)
 {
-        init_arch_irq();
+        machine_desc->init_irq();
 }
 
 #ifdef CONFIG_SPARSE_IRQ
 int __init arch_probe_nr_irqs(void)
 {
-        nr_irqs = arch_nr_irqs ? arch_nr_irqs : NR_IRQS;
+        nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs : NR_IRQS;
         return nr_irqs;
 }
 #endif
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index b63b528f22a6..7fa3bb0d2397 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -19,6 +19,14 @@
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
 
+#if defined(CONFIG_CPU_PJ4)
+#define PJ4(code...)            code
+#define XSC(code...)
+#else
+#define PJ4(code...)
+#define XSC(code...)            code
+#endif
+
 #define MMX_WR0                 (0x00)
 #define MMX_WR1                 (0x08)
 #define MMX_WR2                 (0x10)
@@ -58,11 +66,17 @@
 
 ENTRY(iwmmxt_task_enable)
 
-        mrc     p15, 0, r2, c15, c1, 0
-        tst     r2, #0x3                        @ CP0 and CP1 accessible?
+        XSC(mrc p15, 0, r2, c15, c1, 0)
+        PJ4(mrc p15, 0, r2, c1, c0, 2)
+        @ CP0 and CP1 accessible?
+        XSC(tst r2, #0x3)
+        PJ4(tst r2, #0xf)
         movne   pc, lr                          @ if so no business here
-        orr     r2, r2, #0x3                    @ enable access to CP0 and CP1
-        mcr     p15, 0, r2, c15, c1, 0
+        @ enable access to CP0 and CP1
+        XSC(orr r2, r2, #0x3)
+        XSC(mcr p15, 0, r2, c15, c1, 0)
+        PJ4(orr r2, r2, #0xf)
+        PJ4(mcr p15, 0, r2, c1, c0, 2)
 
         ldr     r3, =concan_owner
         add     r0, r10, #TI_IWMMXT_STATE       @ get task Concan save area
@@ -179,17 +193,26 @@ ENTRY(iwmmxt_task_disable)
         teqne   r1, r2                          @ or specified one?
         bne     1f                              @ no: quit
 
-        mrc     p15, 0, r4, c15, c1, 0
-        orr     r4, r4, #0x3                    @ enable access to CP0 and CP1
-        mcr     p15, 0, r4, c15, c1, 0
+        @ enable access to CP0 and CP1
+        XSC(mrc p15, 0, r4, c15, c1, 0)
+        XSC(orr r4, r4, #0xf)
+        XSC(mcr p15, 0, r4, c15, c1, 0)
+        PJ4(mrc p15, 0, r4, c1, c0, 2)
+        PJ4(orr r4, r4, #0x3)
+        PJ4(mcr p15, 0, r4, c1, c0, 2)
+
         mov     r0, #0                          @ nothing to load
         str     r0, [r3]                        @ no more current owner
         mrc     p15, 0, r2, c2, c0, 0
         mov     r2, r2                          @ cpwait
         bl      concan_save
 
-        bic     r4, r4, #0x3                    @ disable access to CP0 and CP1
-        mcr     p15, 0, r4, c15, c1, 0
+        @ disable access to CP0 and CP1
+        XSC(bic r4, r4, #0x3)
+        XSC(mcr p15, 0, r4, c15, c1, 0)
+        PJ4(bic r4, r4, #0xf)
+        PJ4(mcr p15, 0, r4, c1, c0, 2)
+
         mrc     p15, 0, r2, c2, c0, 0
         mov     r2, r2                          @ cpwait
 
@@ -277,8 +300,11 @@ ENTRY(iwmmxt_task_restore)
  */
 ENTRY(iwmmxt_task_switch)
 
-        mrc     p15, 0, r1, c15, c1, 0
-        tst     r1, #0x3                        @ CP0 and CP1 accessible?
+        XSC(mrc p15, 0, r1, c15, c1, 0)
+        PJ4(mrc p15, 0, r1, c1, c0, 2)
+        @ CP0 and CP1 accessible?
+        XSC(tst r1, #0x3)
+        PJ4(tst r1, #0xf)
         bne     1f                              @ yes: block them for next task
 
         ldr     r2, =concan_owner
@@ -287,8 +313,11 @@ ENTRY(iwmmxt_task_switch)
         teq     r2, r3                          @ next task owns it?
         movne   pc, lr                          @ no: leave Concan disabled
 
-1:      eor     r1, r1, #3                      @ flip Concan access
-        mcr     p15, 0, r1, c15, c1, 0
+1:      @ flip Conan access
+        XSC(eor r1, r1, #0x3)
+        XSC(mcr p15, 0, r1, c15, c1, 0)
+        PJ4(eor r1, r1, #0xf)
+        PJ4(mcr p15, 0, r1, c1, c0, 2)
 
         mrc     p15, 0, r1, c2, c0, 0
         sub     pc, lr, r1, lsr #32             @ cpwait and return
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 3a8fd5140d7a..30ead135ff5f 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -23,6 +23,8 @@ extern unsigned long kexec_indirection_page;
 extern unsigned long kexec_mach_type;
 extern unsigned long kexec_boot_atags;
 
+static atomic_t waiting_for_crash_ipi;
+
 /*
  * Provide a dummy crash_notes definition while crash dump arrives to arm.
  * This prevents breakage of crash_notes attribute in kernel/ksysfs.c.
@@ -37,9 +39,37 @@ void machine_kexec_cleanup(struct kimage *image)
 {
 }
 
+void machine_crash_nonpanic_core(void *unused)
+{
+        struct pt_regs regs;
+
+        crash_setup_regs(&regs, NULL);
+        printk(KERN_DEBUG "CPU %u will stop doing anything useful since another CPU has crashed\n",
+               smp_processor_id());
+        crash_save_cpu(&regs, smp_processor_id());
+        flush_cache_all();
+
+        atomic_dec(&waiting_for_crash_ipi);
+        while (1)
+                cpu_relax();
+}
+
 void machine_crash_shutdown(struct pt_regs *regs)
 {
+        unsigned long msecs;
+
         local_irq_disable();
+
+        atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1);
+        smp_call_function(machine_crash_nonpanic_core, NULL, false);
+        msecs = 1000; /* Wait at most a second for the other cpus to stop */
+        while ((atomic_read(&waiting_for_crash_ipi) > 0) && msecs) {
+                mdelay(1);
+                msecs--;
+        }
+        if (atomic_read(&waiting_for_crash_ipi) > 0)
+                printk(KERN_WARNING "Non-crashing CPUs did not react to IPI\n");
+
         crash_save_cpu(regs, smp_processor_id());
 
         printk(KERN_INFO "Loading crashdump kernel...\n");
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index d9bd786ce23d..0c1bb68ff4a8 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -67,35 +67,6 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
                               char *secstrings,
                               struct module *mod)
 {
-#ifdef CONFIG_ARM_UNWIND
-        Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
-        struct arm_unwind_mapping *maps = mod->arch.map;
-
-        for (s = sechdrs; s < sechdrs_end; s++) {
-                char const *secname = secstrings + s->sh_name;
-
-                if (strcmp(".ARM.exidx.init.text", secname) == 0)
-                        maps[ARM_SEC_INIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
-                        maps[ARM_SEC_DEVINIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx", secname) == 0)
-                        maps[ARM_SEC_CORE].unw_sec = s;
-                else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
-                        maps[ARM_SEC_EXIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
-                        maps[ARM_SEC_DEVEXIT].unw_sec = s;
-                else if (strcmp(".init.text", secname) == 0)
-                        maps[ARM_SEC_INIT].sec_text = s;
-                else if (strcmp(".devinit.text", secname) == 0)
-                        maps[ARM_SEC_DEVINIT].sec_text = s;
-                else if (strcmp(".text", secname) == 0)
-                        maps[ARM_SEC_CORE].sec_text = s;
-                else if (strcmp(".exit.text", secname) == 0)
-                        maps[ARM_SEC_EXIT].sec_text = s;
-                else if (strcmp(".devexit.text", secname) == 0)
-                        maps[ARM_SEC_DEVEXIT].sec_text = s;
-        }
-#endif
         return 0;
 }
 
@@ -300,41 +271,69 @@ apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab,
         return -ENOEXEC;
 }
 
-#ifdef CONFIG_ARM_UNWIND
-static void register_unwind_tables(struct module *mod)
+struct mod_unwind_map {
+        const Elf_Shdr *unw_sec;
+        const Elf_Shdr *txt_sec;
+};
+
+int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
+                    struct module *mod)
 {
+#ifdef CONFIG_ARM_UNWIND
+        const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
+        const Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
+        struct mod_unwind_map maps[ARM_SEC_MAX];
         int i;
-        for (i = 0; i < ARM_SEC_MAX; ++i) {
-                struct arm_unwind_mapping *map = &mod->arch.map[i];
-                if (map->unw_sec && map->sec_text)
-                        map->unwind = unwind_table_add(map->unw_sec->sh_addr,
-                                                       map->unw_sec->sh_size,
-                                                       map->sec_text->sh_addr,
-                                                       map->sec_text->sh_size);
+
+        memset(maps, 0, sizeof(maps));
+
+        for (s = sechdrs; s < sechdrs_end; s++) {
+                const char *secname = secstrs + s->sh_name;
+
+                if (!(s->sh_flags & SHF_ALLOC))
+                        continue;
+
+                if (strcmp(".ARM.exidx.init.text", secname) == 0)
+                        maps[ARM_SEC_INIT].unw_sec = s;
+                else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
+                        maps[ARM_SEC_DEVINIT].unw_sec = s;
+                else if (strcmp(".ARM.exidx", secname) == 0)
+                        maps[ARM_SEC_CORE].unw_sec = s;
+                else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
+                        maps[ARM_SEC_EXIT].unw_sec = s;
+                else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
+                        maps[ARM_SEC_DEVEXIT].unw_sec = s;
+                else if (strcmp(".init.text", secname) == 0)
+                        maps[ARM_SEC_INIT].txt_sec = s;
+                else if (strcmp(".devinit.text", secname) == 0)
+                        maps[ARM_SEC_DEVINIT].txt_sec = s;
+                else if (strcmp(".text", secname) == 0)
+                        maps[ARM_SEC_CORE].txt_sec = s;
+                else if (strcmp(".exit.text", secname) == 0)
+                        maps[ARM_SEC_EXIT].txt_sec = s;
+                else if (strcmp(".devexit.text", secname) == 0)
+                        maps[ARM_SEC_DEVEXIT].txt_sec = s;
         }
-}
 
-static void unregister_unwind_tables(struct module *mod)
-{
-        int i = ARM_SEC_MAX;
-        while (--i >= 0)
-                unwind_table_del(mod->arch.map[i].unwind);
-}
-#else
-static inline void register_unwind_tables(struct module *mod) { }
-static inline void unregister_unwind_tables(struct module *mod) { }
+        for (i = 0; i < ARM_SEC_MAX; i++)
+                if (maps[i].unw_sec && maps[i].txt_sec)
+                        mod->arch.unwind[i] =
+                                unwind_table_add(maps[i].unw_sec->sh_addr,
+                                                 maps[i].unw_sec->sh_size,
+                                                 maps[i].txt_sec->sh_addr,
+                                                 maps[i].txt_sec->sh_size);
 #endif
-
-int
-module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
-                struct module *module)
-{
-        register_unwind_tables(module);
         return 0;
 }
 
 void
 module_arch_cleanup(struct module *mod)
 {
-        unregister_unwind_tables(mod);
+#ifdef CONFIG_ARM_UNWIND
+        int i;
+
+        for (i = 0; i < ARM_SEC_MAX; i++)
+                if (mod->arch.unwind[i])
+                        unwind_table_del(mod->arch.unwind[i]);
+#endif
 }
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 07a50357492a..5efa2647a2fb 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -4,9 +4,7 @@
  * ARM performance counter support.
  *
  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
- *
- * ARMv7 support: Jean Pihet <jpihet@mvista.com>
- * 2010 (c) MontaVista Software, LLC.
+ * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
  *
  * This code is based on the sparc64 perf event code, which is in turn based
  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
@@ -34,7 +32,7 @@ static struct platform_device *pmu_device;
  * Hardware lock to serialize accesses to PMU registers. Needed for the
  * read/modify/write sequences.
  */
-DEFINE_SPINLOCK(pmu_lock);
+static DEFINE_RAW_SPINLOCK(pmu_lock);
 
 /*
  * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
@@ -67,31 +65,25 @@ struct cpu_hw_events {
          */
         unsigned long           active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
 };
-DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
-
-/* PMU names. */
-static const char *arm_pmu_names[] = {
-        [ARM_PERF_PMU_ID_XSCALE1] = "xscale1",
-        [ARM_PERF_PMU_ID_XSCALE2] = "xscale2",
-        [ARM_PERF_PMU_ID_V6]      = "v6",
-        [ARM_PERF_PMU_ID_V6MP]    = "v6mpcore",
-        [ARM_PERF_PMU_ID_CA8]     = "ARMv7 Cortex-A8",
-        [ARM_PERF_PMU_ID_CA9]     = "ARMv7 Cortex-A9",
-};
+static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
 
 struct arm_pmu {
         enum arm_perf_pmu_ids id;
+        const char      *name;
         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
         void            (*enable)(struct hw_perf_event *evt, int idx);
         void            (*disable)(struct hw_perf_event *evt, int idx);
-        int             (*event_map)(int evt);
-        u64             (*raw_event)(u64);
         int             (*get_event_idx)(struct cpu_hw_events *cpuc,
                                          struct hw_perf_event *hwc);
         u32             (*read_counter)(int idx);
         void            (*write_counter)(int idx, u32 val);
         void            (*start)(void);
         void            (*stop)(void);
+        const unsigned  (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
+                                    [PERF_COUNT_HW_CACHE_OP_MAX]
+                                    [PERF_COUNT_HW_CACHE_RESULT_MAX];
+        const unsigned  (*event_map)[PERF_COUNT_HW_MAX];
+        u32             raw_event_mask;
         int             num_events;
         u64             max_period;
 };
@@ -136,10 +128,6 @@ EXPORT_SYMBOL_GPL(perf_num_counters);
 
 #define CACHE_OP_UNSUPPORTED            0xFFFF
 
-static unsigned armpmu_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                     [PERF_COUNT_HW_CACHE_OP_MAX]
-                                     [PERF_COUNT_HW_CACHE_RESULT_MAX];
-
 static int
 armpmu_map_cache_event(u64 config)
 {
@@ -157,7 +145,7 @@ armpmu_map_cache_event(u64 config)
         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
                 return -EINVAL;
 
-        ret = (int)armpmu_perf_cache_map[cache_type][cache_op][cache_result];
+        ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result];
 
         if (ret == CACHE_OP_UNSUPPORTED)
                 return -ENOENT;
@@ -166,6 +154,19 @@ armpmu_map_cache_event(u64 config)
 }
 
 static int
+armpmu_map_event(u64 config)
+{
+        int mapping = (*armpmu->event_map)[config];
+        return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping;
+}
+
+static int
+armpmu_map_raw_event(u64 config)
+{
+        return (int)(config & armpmu->raw_event_mask);
+}
+
+static int
 armpmu_event_set_period(struct perf_event *event,
                         struct hw_perf_event *hwc,
                         int idx)
@@ -458,11 +459,11 @@ __hw_perf_event_init(struct perf_event *event)
 
         /* Decode the generic type into an ARM event identifier. */
         if (PERF_TYPE_HARDWARE == event->attr.type) {
-                mapping = armpmu->event_map(event->attr.config);
+                mapping = armpmu_map_event(event->attr.config);
         } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
                 mapping = armpmu_map_cache_event(event->attr.config);
         } else if (PERF_TYPE_RAW == event->attr.type) {
-                mapping = armpmu->raw_event(event->attr.config);
+                mapping = armpmu_map_raw_event(event->attr.config);
         } else {
                 pr_debug("event type %x not supported\n", event->attr.type);
                 return -EOPNOTSUPP;
@@ -603,2366 +604,10 @@ static struct pmu pmu = {
         .read           = armpmu_read,
 };
 
-/*
- * ARMv6 Performance counter handling code.
- *
- * ARMv6 has 2 configurable performance counters and a single cycle counter.
- * They all share a single reset bit but can be written to zero so we can use
- * that for a reset.
- *
- * The counters can't be individually enabled or disabled so when we remove
- * one event and replace it with another we could get spurious counts from the
- * wrong event. However, we can take advantage of the fact that the
- * performance counters can export events to the event bus, and the event bus
- * itself can be monitored. This requires that we *don't* export the events to
- * the event bus. The procedure for disabling a configurable counter is:
- *      - change the counter to count the ETMEXTOUT[0] signal (0x20). This
- *        effectively stops the counter from counting.
- *      - disable the counter's interrupt generation (each counter has it's
- *        own interrupt enable bit).
- * Once stopped, the counter value can be written as 0 to reset.
- *
- * To enable a counter:
- *      - enable the counter's interrupt generation.
- *      - set the new event type.
- *
- * Note: the dedicated cycle counter only counts cycles and can't be
- * enabled/disabled independently of the others. When we want to disable the
- * cycle counter, we have to just disable the interrupt reporting and start
- * ignoring that counter. When re-enabling, we have to reset the value and
- * enable the interrupt.
- */
-
-enum armv6_perf_types {
-        ARMV6_PERFCTR_ICACHE_MISS           = 0x0,
-        ARMV6_PERFCTR_IBUF_STALL            = 0x1,
-        ARMV6_PERFCTR_DDEP_STALL            = 0x2,
-        ARMV6_PERFCTR_ITLB_MISS             = 0x3,
-        ARMV6_PERFCTR_DTLB_MISS             = 0x4,
-        ARMV6_PERFCTR_BR_EXEC               = 0x5,
-        ARMV6_PERFCTR_BR_MISPREDICT         = 0x6,
-        ARMV6_PERFCTR_INSTR_EXEC            = 0x7,
-        ARMV6_PERFCTR_DCACHE_HIT            = 0x9,
-        ARMV6_PERFCTR_DCACHE_ACCESS         = 0xA,
-        ARMV6_PERFCTR_DCACHE_MISS           = 0xB,
-        ARMV6_PERFCTR_DCACHE_WBACK          = 0xC,
-        ARMV6_PERFCTR_SW_PC_CHANGE          = 0xD,
-        ARMV6_PERFCTR_MAIN_TLB_MISS         = 0xF,
-        ARMV6_PERFCTR_EXPL_D_ACCESS         = 0x10,
-        ARMV6_PERFCTR_LSU_FULL_STALL        = 0x11,
-        ARMV6_PERFCTR_WBUF_DRAINED          = 0x12,
-        ARMV6_PERFCTR_CPU_CYCLES            = 0xFF,
-        ARMV6_PERFCTR_NOP                   = 0x20,
-};
-
-enum armv6_counters {
-        ARMV6_CYCLE_COUNTER = 1,
-        ARMV6_COUNTER0,
-        ARMV6_COUNTER1,
-};
-
-/*
- * The hardware events that we support. We do support cache operations but
- * we have harvard caches and no way to combine instruction and data
- * accesses/misses in hardware.
- */
-static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6_PERFCTR_INSTR_EXEC,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6_PERFCTR_BR_MISPREDICT,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
-};
-
-static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                          [PERF_COUNT_HW_CACHE_OP_MAX]
-                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-        [C(L1D)] = {
-                /*
-                 * The performance counters don't differentiate between read
-                 * and write accesses/misses so this isn't strictly correct,
-                 * but it's the best we can do. Writes and reads get
-                 * combined.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(L1I)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(LL)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(DTLB)] = {
-                /*
-                 * The ARM performance counters can count micro DTLB misses,
-                 * micro ITLB misses and main TLB misses. There isn't an event
-                 * for TLB misses, so use the micro misses here and if users
-                 * want the main TLB misses they can use a raw counter.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(ITLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(BPU)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-};
-
-enum armv6mpcore_perf_types {
-        ARMV6MPCORE_PERFCTR_ICACHE_MISS     = 0x0,
-        ARMV6MPCORE_PERFCTR_IBUF_STALL      = 0x1,
-        ARMV6MPCORE_PERFCTR_DDEP_STALL      = 0x2,
-        ARMV6MPCORE_PERFCTR_ITLB_MISS       = 0x3,
-        ARMV6MPCORE_PERFCTR_DTLB_MISS       = 0x4,
-        ARMV6MPCORE_PERFCTR_BR_EXEC         = 0x5,
-        ARMV6MPCORE_PERFCTR_BR_NOTPREDICT   = 0x6,
-        ARMV6MPCORE_PERFCTR_BR_MISPREDICT   = 0x7,
-        ARMV6MPCORE_PERFCTR_INSTR_EXEC      = 0x8,
-        ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
-        ARMV6MPCORE_PERFCTR_DCACHE_RDMISS   = 0xB,
-        ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
-        ARMV6MPCORE_PERFCTR_DCACHE_WRMISS   = 0xD,
-        ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
-        ARMV6MPCORE_PERFCTR_SW_PC_CHANGE    = 0xF,
-        ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS   = 0x10,
-        ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
-        ARMV6MPCORE_PERFCTR_LSU_FULL_STALL  = 0x12,
-        ARMV6MPCORE_PERFCTR_WBUF_DRAINED    = 0x13,
-        ARMV6MPCORE_PERFCTR_CPU_CYCLES      = 0xFF,
-};
-
-/*
- * The hardware events that we support. We do support cache operations but
- * we have harvard caches and no way to combine instruction and data
- * accesses/misses in hardware.
- */
-static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
-};
-
-static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                        [PERF_COUNT_HW_CACHE_OP_MAX]
-                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-        [C(L1D)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  =
-                                ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
-                        [C(RESULT_MISS)]    =
-                                ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  =
-                                ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
-                        [C(RESULT_MISS)]    =
-                                ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(L1I)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(LL)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(DTLB)] = {
-                /*
-                 * The ARM performance counters can count micro DTLB misses,
-                 * micro ITLB misses and main TLB misses. There isn't an event
-                 * for TLB misses, so use the micro misses here and if users
-                 * want the main TLB misses they can use a raw counter.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(ITLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(BPU)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-};
-
-static inline unsigned long
-armv6_pmcr_read(void)
-{
-        u32 val;
-        asm volatile("mrc   p15, 0, %0, c15, c12, 0" : "=r"(val));
-        return val;
-}
-
-static inline void
-armv6_pmcr_write(unsigned long val)
-{
-        asm volatile("mcr   p15, 0, %0, c15, c12, 0" : : "r"(val));
-}
-
-#define ARMV6_PMCR_ENABLE               (1 << 0)
-#define ARMV6_PMCR_CTR01_RESET          (1 << 1)
-#define ARMV6_PMCR_CCOUNT_RESET         (1 << 2)
-#define ARMV6_PMCR_CCOUNT_DIV           (1 << 3)
-#define ARMV6_PMCR_COUNT0_IEN           (1 << 4)
-#define ARMV6_PMCR_COUNT1_IEN           (1 << 5)
-#define ARMV6_PMCR_CCOUNT_IEN           (1 << 6)
-#define ARMV6_PMCR_COUNT0_OVERFLOW      (1 << 8)
-#define ARMV6_PMCR_COUNT1_OVERFLOW      (1 << 9)
-#define ARMV6_PMCR_CCOUNT_OVERFLOW      (1 << 10)
-#define ARMV6_PMCR_EVT_COUNT0_SHIFT     20
-#define ARMV6_PMCR_EVT_COUNT0_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
-#define ARMV6_PMCR_EVT_COUNT1_SHIFT     12
-#define ARMV6_PMCR_EVT_COUNT1_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
-
-#define ARMV6_PMCR_OVERFLOWED_MASK \
-        (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
-         ARMV6_PMCR_CCOUNT_OVERFLOW)
-
-static inline int
-armv6_pmcr_has_overflowed(unsigned long pmcr)
-{
-        return (pmcr & ARMV6_PMCR_OVERFLOWED_MASK);
-}
-
-static inline int
-armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
-                                  enum armv6_counters counter)
-{
-        int ret = 0;
-
-        if (ARMV6_CYCLE_COUNTER == counter)
-                ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
-        else if (ARMV6_COUNTER0 == counter)
-                ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
-        else if (ARMV6_COUNTER1 == counter)
-                ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
-        else
-                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
-
-        return ret;
-}
-
-static inline u32
-armv6pmu_read_counter(int counter)
-{
-        unsigned long value = 0;
-
-        if (ARMV6_CYCLE_COUNTER == counter)
-                asm volatile("mrc   p15, 0, %0, c15, c12, 1" : "=r"(value));
-        else if (ARMV6_COUNTER0 == counter)
-                asm volatile("mrc   p15, 0, %0, c15, c12, 2" : "=r"(value));
-        else if (ARMV6_COUNTER1 == counter)
-                asm volatile("mrc   p15, 0, %0, c15, c12, 3" : "=r"(value));
-        else
-                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
-
-        return value;
-}
-
-static inline void
-armv6pmu_write_counter(int counter,
-                       u32 value)
-{
-        if (ARMV6_CYCLE_COUNTER == counter)
-                asm volatile("mcr   p15, 0, %0, c15, c12, 1" : : "r"(value));
-        else if (ARMV6_COUNTER0 == counter)
-                asm volatile("mcr   p15, 0, %0, c15, c12, 2" : : "r"(value));
-        else if (ARMV6_COUNTER1 == counter)
-                asm volatile("mcr   p15, 0, %0, c15, c12, 3" : : "r"(value));
-        else
-                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
-}
-
-void
-armv6pmu_enable_event(struct hw_perf_event *hwc,
-                      int idx)
-{
-        unsigned long val, mask, evt, flags;
-
-        if (ARMV6_CYCLE_COUNTER == idx) {
-                mask    = 0;
-                evt     = ARMV6_PMCR_CCOUNT_IEN;
-        } else if (ARMV6_COUNTER0 == idx) {
-                mask    = ARMV6_PMCR_EVT_COUNT0_MASK;
-                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
-                          ARMV6_PMCR_COUNT0_IEN;
-        } else if (ARMV6_COUNTER1 == idx) {
-                mask    = ARMV6_PMCR_EVT_COUNT1_MASK;
-                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
-                          ARMV6_PMCR_COUNT1_IEN;
-        } else {
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        /*
-         * Mask out the current event and set the counter to count the event
-         * that we're interested in.
-         */
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = armv6_pmcr_read();
-        val &= ~mask;
-        val |= evt;
-        armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static irqreturn_t
-armv6pmu_handle_irq(int irq_num,
-                    void *dev)
-{
-        unsigned long pmcr = armv6_pmcr_read();
-        struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
-        struct pt_regs *regs;
-        int idx;
-
-        if (!armv6_pmcr_has_overflowed(pmcr))
-                return IRQ_NONE;
-
-        regs = get_irq_regs();
-
-        /*
-         * The interrupts are cleared by writing the overflow flags back to
-         * the control register. All of the other bits don't have any effect
-         * if they are rewritten, so write the whole value back.
-         */
-        armv6_pmcr_write(pmcr);
-
-        perf_sample_data_init(&data, 0);
-
-        cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
-                struct perf_event *event = cpuc->events[idx];
-                struct hw_perf_event *hwc;
-
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
-                /*
-                 * We have a single interrupt for all counters. Check that
-                 * each counter has overflowed before we process it.
-                 */
-                if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
-                        continue;
-
-                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
-                if (!armpmu_event_set_period(event, hwc, idx))
-                        continue;
-
-                if (perf_event_overflow(event, 0, &data, regs))
-                        armpmu->disable(hwc, idx);
-        }
-
-        /*
-         * Handle the pending perf events.
-         *
-         * Note: this call *must* be run with interrupts disabled. For
-         * platforms that can have the PMU interrupts raised as an NMI, this
-         * will not work.
-         */
-        irq_work_run();
-
-        return IRQ_HANDLED;
-}
-
-static void
-armv6pmu_start(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = armv6_pmcr_read();
-        val |= ARMV6_PMCR_ENABLE;
-        armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-void
-armv6pmu_stop(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = armv6_pmcr_read();
-        val &= ~ARMV6_PMCR_ENABLE;
-        armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static inline int
-armv6pmu_event_map(int config)
-{
-        int mapping = armv6_perf_map[config];
-        if (HW_OP_UNSUPPORTED == mapping)
-                mapping = -EOPNOTSUPP;
-        return mapping;
-}
-
-static inline int
-armv6mpcore_pmu_event_map(int config)
-{
-        int mapping = armv6mpcore_perf_map[config];
-        if (HW_OP_UNSUPPORTED == mapping)
-                mapping = -EOPNOTSUPP;
-        return mapping;
-}
-
-static u64
-armv6pmu_raw_event(u64 config)
-{
-        return config & 0xff;
-}
-
-static int
-armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
-                       struct hw_perf_event *event)
-{
-        /* Always place a cycle counter into the cycle counter. */
-        if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
-                if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
-                        return -EAGAIN;
-
-                return ARMV6_CYCLE_COUNTER;
-        } else {
-                /*
-                 * For anything other than a cycle counter, try and use
-                 * counter0 and counter1.
-                 */
-                if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) {
-                        return ARMV6_COUNTER1;
-                }
-
-                if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) {
-                        return ARMV6_COUNTER0;
-                }
-
-                /* The counters are all in use. */
-                return -EAGAIN;
-        }
-}
-
-static void
-armv6pmu_disable_event(struct hw_perf_event *hwc,
-                       int idx)
-{
-        unsigned long val, mask, evt, flags;
-
-        if (ARMV6_CYCLE_COUNTER == idx) {
-                mask    = ARMV6_PMCR_CCOUNT_IEN;
-                evt     = 0;
-        } else if (ARMV6_COUNTER0 == idx) {
-                mask    = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
-                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
-        } else if (ARMV6_COUNTER1 == idx) {
-                mask    = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
-                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
-        } else {
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        /*
-         * Mask out the current event and set the counter to count the number
-         * of ETM bus signal assertion cycles. The external reporting should
-         * be disabled and so this should never increment.
-         */
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = armv6_pmcr_read();
-        val &= ~mask;
-        val |= evt;
-        armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void
-armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
-                              int idx)
-{
-        unsigned long val, mask, flags, evt = 0;
-
-        if (ARMV6_CYCLE_COUNTER == idx) {
-                mask    = ARMV6_PMCR_CCOUNT_IEN;
-        } else if (ARMV6_COUNTER0 == idx) {
-                mask    = ARMV6_PMCR_COUNT0_IEN;
-        } else if (ARMV6_COUNTER1 == idx) {
-                mask    = ARMV6_PMCR_COUNT1_IEN;
-        } else {
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        /*
-         * Unlike UP ARMv6, we don't have a way of stopping the counters. We
-         * simply disable the interrupt reporting.
-         */
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = armv6_pmcr_read();
-        val &= ~mask;
-        val |= evt;
-        armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static const struct arm_pmu armv6pmu = {
-        .id                     = ARM_PERF_PMU_ID_V6,
-        .handle_irq             = armv6pmu_handle_irq,
-        .enable                 = armv6pmu_enable_event,
-        .disable                = armv6pmu_disable_event,
-        .event_map              = armv6pmu_event_map,
-        .raw_event              = armv6pmu_raw_event,
-        .read_counter           = armv6pmu_read_counter,
-        .write_counter          = armv6pmu_write_counter,
-        .get_event_idx          = armv6pmu_get_event_idx,
-        .start                  = armv6pmu_start,
-        .stop                   = armv6pmu_stop,
-        .num_events             = 3,
-        .max_period             = (1LLU << 32) - 1,
-};
-
-/*
- * ARMv6mpcore is almost identical to single core ARMv6 with the exception
- * that some of the events have different enumerations and that there is no
- * *hack* to stop the programmable counters. To stop the counters we simply
- * disable the interrupt reporting and update the event. When unthrottling we
- * reset the period and enable the interrupt reporting.
- */
-static const struct arm_pmu armv6mpcore_pmu = {
-        .id                     = ARM_PERF_PMU_ID_V6MP,
-        .handle_irq             = armv6pmu_handle_irq,
-        .enable                 = armv6pmu_enable_event,
-        .disable                = armv6mpcore_pmu_disable_event,
-        .event_map              = armv6mpcore_pmu_event_map,
-        .raw_event              = armv6pmu_raw_event,
-        .read_counter           = armv6pmu_read_counter,
-        .write_counter          = armv6pmu_write_counter,
-        .get_event_idx          = armv6pmu_get_event_idx,
-        .start                  = armv6pmu_start,
-        .stop                   = armv6pmu_stop,
-        .num_events             = 3,
-        .max_period             = (1LLU << 32) - 1,
-};
-
-/*
- * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
- *
- * Copied from ARMv6 code, with the low level code inspired
- *  by the ARMv7 Oprofile code.
- *
- * Cortex-A8 has up to 4 configurable performance counters and
- *  a single cycle counter.
- * Cortex-A9 has up to 31 configurable performance counters and
- *  a single cycle counter.
- *
- * All counters can be enabled/disabled and IRQ masked separately. The cycle
- *  counter and all 4 performance counters together can be reset separately.
- */
-
-/* Common ARMv7 event types */
-enum armv7_perf_types {
-        ARMV7_PERFCTR_PMNC_SW_INCR              = 0x00,
-        ARMV7_PERFCTR_IFETCH_MISS               = 0x01,
-        ARMV7_PERFCTR_ITLB_MISS                 = 0x02,
-        ARMV7_PERFCTR_DCACHE_REFILL             = 0x03,
-        ARMV7_PERFCTR_DCACHE_ACCESS             = 0x04,
-        ARMV7_PERFCTR_DTLB_REFILL               = 0x05,
-        ARMV7_PERFCTR_DREAD                     = 0x06,
-        ARMV7_PERFCTR_DWRITE                    = 0x07,
-
-        ARMV7_PERFCTR_EXC_TAKEN                 = 0x09,
-        ARMV7_PERFCTR_EXC_EXECUTED              = 0x0A,
-        ARMV7_PERFCTR_CID_WRITE                 = 0x0B,
-        /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
-         * It counts:
-         *  - all branch instructions,
-         *  - instructions that explicitly write the PC,
-         *  - exception generating instructions.
-         */
-        ARMV7_PERFCTR_PC_WRITE                  = 0x0C,
-        ARMV7_PERFCTR_PC_IMM_BRANCH             = 0x0D,
-        ARMV7_PERFCTR_UNALIGNED_ACCESS          = 0x0F,
-        ARMV7_PERFCTR_PC_BRANCH_MIS_PRED        = 0x10,
-        ARMV7_PERFCTR_CLOCK_CYCLES              = 0x11,
-
-        ARMV7_PERFCTR_PC_BRANCH_MIS_USED        = 0x12,
-
-        ARMV7_PERFCTR_CPU_CYCLES                = 0xFF
-};
-
-/* ARMv7 Cortex-A8 specific event types */
-enum armv7_a8_perf_types {
-        ARMV7_PERFCTR_INSTR_EXECUTED            = 0x08,
-
-        ARMV7_PERFCTR_PC_PROC_RETURN            = 0x0E,
-
-        ARMV7_PERFCTR_WRITE_BUFFER_FULL         = 0x40,
-        ARMV7_PERFCTR_L2_STORE_MERGED           = 0x41,
-        ARMV7_PERFCTR_L2_STORE_BUFF             = 0x42,
-        ARMV7_PERFCTR_L2_ACCESS                 = 0x43,
-        ARMV7_PERFCTR_L2_CACH_MISS              = 0x44,
-        ARMV7_PERFCTR_AXI_READ_CYCLES           = 0x45,
-        ARMV7_PERFCTR_AXI_WRITE_CYCLES          = 0x46,
-        ARMV7_PERFCTR_MEMORY_REPLAY             = 0x47,
-        ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY   = 0x48,
-        ARMV7_PERFCTR_L1_DATA_MISS              = 0x49,
-        ARMV7_PERFCTR_L1_INST_MISS              = 0x4A,
-        ARMV7_PERFCTR_L1_DATA_COLORING          = 0x4B,
-        ARMV7_PERFCTR_L1_NEON_DATA              = 0x4C,
-        ARMV7_PERFCTR_L1_NEON_CACH_DATA         = 0x4D,
-        ARMV7_PERFCTR_L2_NEON                   = 0x4E,
-        ARMV7_PERFCTR_L2_NEON_HIT               = 0x4F,
-        ARMV7_PERFCTR_L1_INST                   = 0x50,
-        ARMV7_PERFCTR_PC_RETURN_MIS_PRED        = 0x51,
-        ARMV7_PERFCTR_PC_BRANCH_FAILED          = 0x52,
-        ARMV7_PERFCTR_PC_BRANCH_TAKEN           = 0x53,
-        ARMV7_PERFCTR_PC_BRANCH_EXECUTED        = 0x54,
-        ARMV7_PERFCTR_OP_EXECUTED               = 0x55,
-        ARMV7_PERFCTR_CYCLES_INST_STALL         = 0x56,
-        ARMV7_PERFCTR_CYCLES_INST               = 0x57,
-        ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL    = 0x58,
-        ARMV7_PERFCTR_CYCLES_NEON_INST_STALL    = 0x59,
-        ARMV7_PERFCTR_NEON_CYCLES               = 0x5A,
-
-        ARMV7_PERFCTR_PMU0_EVENTS               = 0x70,
-        ARMV7_PERFCTR_PMU1_EVENTS               = 0x71,
-        ARMV7_PERFCTR_PMU_EVENTS                = 0x72,
-};
-
-/* ARMv7 Cortex-A9 specific event types */
-enum armv7_a9_perf_types {
-        ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC     = 0x40,
-        ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC     = 0x41,
-        ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC       = 0x42,
-
-        ARMV7_PERFCTR_COHERENT_LINE_MISS        = 0x50,
-        ARMV7_PERFCTR_COHERENT_LINE_HIT         = 0x51,
-
-        ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES   = 0x60,
-        ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES   = 0x61,
-        ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
-        ARMV7_PERFCTR_STREX_EXECUTED_PASSED     = 0x63,
-        ARMV7_PERFCTR_STREX_EXECUTED_FAILED     = 0x64,
-        ARMV7_PERFCTR_DATA_EVICTION             = 0x65,
-        ARMV7_PERFCTR_ISSUE_STAGE_NO_INST       = 0x66,
-        ARMV7_PERFCTR_ISSUE_STAGE_EMPTY         = 0x67,
-        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE  = 0x68,
-
-        ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
-
-        ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST   = 0x70,
-        ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
-        ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST  = 0x72,
-        ARMV7_PERFCTR_FP_EXECUTED_INST          = 0x73,
-        ARMV7_PERFCTR_NEON_EXECUTED_INST        = 0x74,
-
-        ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
-        ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES  = 0x81,
-        ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
-        ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
-        ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
-        ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
-        ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES      = 0x86,
-
-        ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
-        ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
-
-        ARMV7_PERFCTR_ISB_INST                  = 0x90,
-        ARMV7_PERFCTR_DSB_INST                  = 0x91,
-        ARMV7_PERFCTR_DMB_INST                  = 0x92,
-        ARMV7_PERFCTR_EXT_INTERRUPTS            = 0x93,
-
-        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
-        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
-        ARMV7_PERFCTR_PLE_FIFO_FLUSH            = 0xA2,
-        ARMV7_PERFCTR_PLE_RQST_COMPLETED        = 0xA3,
-        ARMV7_PERFCTR_PLE_FIFO_OVERFLOW         = 0xA4,
-        ARMV7_PERFCTR_PLE_RQST_PROG             = 0xA5
-};
-
-/*
- * Cortex-A8 HW events mapping
- *
- * The hardware events that we support. We do support cache operations but
- * we have harvard caches and no way to combine instruction and data
- * accesses/misses in hardware.
- */
-static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
-};
-
-static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                          [PERF_COUNT_HW_CACHE_OP_MAX]
-                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-        [C(L1D)] = {
-                /*
-                 * The performance counters don't differentiate between read
-                 * and write accesses/misses so this isn't strictly correct,
-                 * but it's the best we can do. Writes and reads get
-                 * combined.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(L1I)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(LL)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(DTLB)] = {
-                /*
-                 * Only ITLB misses and DTLB refills are supported.
-                 * If users want the DTLB refills misses a raw counter
-                 * must be used.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(ITLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(BPU)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-};
-
-/*
- * Cortex-A9 HW events mapping
- */
-static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        =
-                                        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_COHERENT_LINE_HIT,
-        [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_COHERENT_LINE_MISS,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
-};
-
-static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                          [PERF_COUNT_HW_CACHE_OP_MAX]
-                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-        [C(L1D)] = {
-                /*
-                 * The performance counters don't differentiate between read
-                 * and write accesses/misses so this isn't strictly correct,
-                 * but it's the best we can do. Writes and reads get
-                 * combined.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(L1I)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(LL)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(DTLB)] = {
-                /*
-                 * Only ITLB misses and DTLB refills are supported.
-                 * If users want the DTLB refills misses a raw counter
-                 * must be used.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(ITLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(BPU)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-};
-
-/*
- * Perf Events counters
- */
-enum armv7_counters {
-        ARMV7_CYCLE_COUNTER             = 1,    /* Cycle counter */
-        ARMV7_COUNTER0                  = 2,    /* First event counter */
-};
-
-/*
- * The cycle counter is ARMV7_CYCLE_COUNTER.
- * The first event counter is ARMV7_COUNTER0.
- * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
- */
-#define ARMV7_COUNTER_LAST      (ARMV7_COUNTER0 + armpmu->num_events - 1)
-
-/*
- * ARMv7 low level PMNC access
- */
-
-/*
- * Per-CPU PMNC: config reg
- */
-#define ARMV7_PMNC_E            (1 << 0) /* Enable all counters */
-#define ARMV7_PMNC_P            (1 << 1) /* Reset all counters */
-#define ARMV7_PMNC_C            (1 << 2) /* Cycle counter reset */
-#define ARMV7_PMNC_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
-#define ARMV7_PMNC_X            (1 << 4) /* Export to ETM */
-#define ARMV7_PMNC_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
-#define ARMV7_PMNC_N_SHIFT      11       /* Number of counters supported */
-#define ARMV7_PMNC_N_MASK       0x1f
-#define ARMV7_PMNC_MASK         0x3f     /* Mask for writable bits */
-
-/*
- * Available counters
- */
-#define ARMV7_CNT0              0       /* First event counter */
-#define ARMV7_CCNT              31      /* Cycle counter */
-
-/* Perf Event to low level counters mapping */
-#define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
-
-/*
- * CNTENS: counters enable reg
- */
-#define ARMV7_CNTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_CNTENS_C          (1 << ARMV7_CCNT)
-
-/*
- * CNTENC: counters disable reg
- */
-#define ARMV7_CNTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_CNTENC_C          (1 << ARMV7_CCNT)
-
-/*
- * INTENS: counters overflow interrupt enable reg
- */
-#define ARMV7_INTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_INTENS_C          (1 << ARMV7_CCNT)
-
-/*
- * INTENC: counters overflow interrupt disable reg
- */
-#define ARMV7_INTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_INTENC_C          (1 << ARMV7_CCNT)
-
-/*
- * EVTSEL: Event selection reg
- */
-#define ARMV7_EVTSEL_MASK       0xff            /* Mask for writable bits */
-
-/*
- * SELECT: Counter selection reg
- */
-#define ARMV7_SELECT_MASK       0x1f            /* Mask for writable bits */
-
-/*
- * FLAG: counters overflow flag status reg
- */
-#define ARMV7_FLAG_P(idx)       (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_FLAG_C            (1 << ARMV7_CCNT)
-#define ARMV7_FLAG_MASK         0xffffffff      /* Mask for writable bits */
-#define ARMV7_OVERFLOWED_MASK   ARMV7_FLAG_MASK
-
-static inline unsigned long armv7_pmnc_read(void)
-{
-        u32 val;
-        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
-        return val;
-}
-
-static inline void armv7_pmnc_write(unsigned long val)
-{
-        val &= ARMV7_PMNC_MASK;
-        asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
-}
-
-static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
-{
-        return pmnc & ARMV7_OVERFLOWED_MASK;
-}
-
-static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
-                                        enum armv7_counters counter)
-{
-        int ret = 0;
-
-        if (counter == ARMV7_CYCLE_COUNTER)
-                ret = pmnc & ARMV7_FLAG_C;
-        else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
-                ret = pmnc & ARMV7_FLAG_P(counter);
-        else
-                pr_err("CPU%u checking wrong counter %d overflow status\n",
-                        smp_processor_id(), counter);
-
-        return ret;
-}
-
-static inline int armv7_pmnc_select_counter(unsigned int idx)
-{
-        u32 val;
-
-        if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
-                pr_err("CPU%u selecting wrong PMNC counter"
-                        " %d\n", smp_processor_id(), idx);
-                return -1;
-        }
-
-        val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
-        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
-
-        return idx;
-}
-
-static inline u32 armv7pmu_read_counter(int idx)
-{
-        unsigned long value = 0;
-
-        if (idx == ARMV7_CYCLE_COUNTER)
-                asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
-        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
-                if (armv7_pmnc_select_counter(idx) == idx)
-                        asm volatile("mrc p15, 0, %0, c9, c13, 2"
-                                     : "=r" (value));
-        } else
-                pr_err("CPU%u reading wrong counter %d\n",
-                        smp_processor_id(), idx);
-
-        return value;
-}
-
-static inline void armv7pmu_write_counter(int idx, u32 value)
-{
-        if (idx == ARMV7_CYCLE_COUNTER)
-                asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
-        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
-                if (armv7_pmnc_select_counter(idx) == idx)
-                        asm volatile("mcr p15, 0, %0, c9, c13, 2"
-                                     : : "r" (value));
-        } else
-                pr_err("CPU%u writing wrong counter %d\n",
-                        smp_processor_id(), idx);
-}
-
-static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
-{
-        if (armv7_pmnc_select_counter(idx) == idx) {
-                val &= ARMV7_EVTSEL_MASK;
-                asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
-        }
-}
-
-static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
-{
-        u32 val;
-
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u enabling wrong PMNC counter"
-                        " %d\n", smp_processor_id(), idx);
-                return -1;
-        }
-
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_CNTENS_C;
-        else
-                val = ARMV7_CNTENS_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
-
-        return idx;
-}
-
-static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
-{
-        u32 val;
-
-
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u disabling wrong PMNC counter"
-                        " %d\n", smp_processor_id(), idx);
-                return -1;
-        }
-
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_CNTENC_C;
-        else
-                val = ARMV7_CNTENC_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
-
-        return idx;
-}
-
-static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
-{
-        u32 val;
-
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u enabling wrong PMNC counter"
-                        " interrupt enable %d\n", smp_processor_id(), idx);
-                return -1;
-        }
-
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_INTENS_C;
-        else
-                val = ARMV7_INTENS_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
-
-        return idx;
-}
-
-static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
-{
-        u32 val;
-
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u disabling wrong PMNC counter"
-                        " interrupt enable %d\n", smp_processor_id(), idx);
-                return -1;
-        }
-
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_INTENC_C;
-        else
-                val = ARMV7_INTENC_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
-
-        return idx;
-}
-
-static inline u32 armv7_pmnc_getreset_flags(void)
-{
-        u32 val;
-
-        /* Read */
-        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
-
-        /* Write to clear flags */
-        val &= ARMV7_FLAG_MASK;
-        asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
-
-        return val;
-}
-
-#ifdef DEBUG
-static void armv7_pmnc_dump_regs(void)
-{
-        u32 val;
-        unsigned int cnt;
-
-        printk(KERN_INFO "PMNC registers dump:\n");
-
-        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
-        printk(KERN_INFO "PMNC  =0x%08x\n", val);
-
-        asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
-        printk(KERN_INFO "CNTENS=0x%08x\n", val);
-
-        asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
-        printk(KERN_INFO "INTENS=0x%08x\n", val);
-
-        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
-        printk(KERN_INFO "FLAGS =0x%08x\n", val);
-
-        asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
-        printk(KERN_INFO "SELECT=0x%08x\n", val);
-
-        asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
-        printk(KERN_INFO "CCNT  =0x%08x\n", val);
-
-        for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
-                armv7_pmnc_select_counter(cnt);
-                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
-                printk(KERN_INFO "CNT[%d] count =0x%08x\n",
-                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
-                asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
-                printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
-                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
-        }
-}
-#endif
-
-void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long flags;
-
-        /*
-         * Enable counter and interrupt, and set the counter to count
-         * the event that we're interested in.
-         */
-        spin_lock_irqsave(&pmu_lock, flags);
-
-        /*
-         * Disable counter
-         */
-        armv7_pmnc_disable_counter(idx);
-
-        /*
-         * Set event (if destined for PMNx counters)
-         * We don't need to set the event if it's a cycle count
-         */
-        if (idx != ARMV7_CYCLE_COUNTER)
-                armv7_pmnc_write_evtsel(idx, hwc->config_base);
-
-        /*
-         * Enable interrupt for this counter
-         */
-        armv7_pmnc_enable_intens(idx);
-
-        /*
-         * Enable counter
-         */
-        armv7_pmnc_enable_counter(idx);
-
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long flags;
-
-        /*
-         * Disable counter and interrupt
-         */
-        spin_lock_irqsave(&pmu_lock, flags);
-
-        /*
-         * Disable counter
-         */
-        armv7_pmnc_disable_counter(idx);
-
-        /*
-         * Disable interrupt for this counter
-         */
-        armv7_pmnc_disable_intens(idx);
-
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
-{
-        unsigned long pmnc;
-        struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
-        struct pt_regs *regs;
-        int idx;
-
-        /*
-         * Get and reset the IRQ flags
-         */
-        pmnc = armv7_pmnc_getreset_flags();
-
-        /*
-         * Did an overflow occur?
-         */
-        if (!armv7_pmnc_has_overflowed(pmnc))
-                return IRQ_NONE;
-
-        /*
-         * Handle the counter(s) overflow(s)
-         */
-        regs = get_irq_regs();
-
-        perf_sample_data_init(&data, 0);
-
-        cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
-                struct perf_event *event = cpuc->events[idx];
-                struct hw_perf_event *hwc;
-
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
-                /*
-                 * We have a single interrupt for all counters. Check that
-                 * each counter has overflowed before we process it.
-                 */
-                if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
-                        continue;
-
-                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
-                if (!armpmu_event_set_period(event, hwc, idx))
-                        continue;
-
-                if (perf_event_overflow(event, 0, &data, regs))
-                        armpmu->disable(hwc, idx);
-        }
-
-        /*
-         * Handle the pending perf events.
-         *
-         * Note: this call *must* be run with interrupts disabled. For
-         * platforms that can have the PMU interrupts raised as an NMI, this
-         * will not work.
-         */
-        irq_work_run();
-
-        return IRQ_HANDLED;
-}
-
-static void armv7pmu_start(void)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        /* Enable all counters */
-        armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void armv7pmu_stop(void)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        /* Disable all counters */
-        armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static inline int armv7_a8_pmu_event_map(int config)
-{
-        int mapping = armv7_a8_perf_map[config];
-        if (HW_OP_UNSUPPORTED == mapping)
-                mapping = -EOPNOTSUPP;
-        return mapping;
-}
-
-static inline int armv7_a9_pmu_event_map(int config)
-{
-        int mapping = armv7_a9_perf_map[config];
-        if (HW_OP_UNSUPPORTED == mapping)
-                mapping = -EOPNOTSUPP;
-        return mapping;
-}
-
-static u64 armv7pmu_raw_event(u64 config)
-{
-        return config & 0xff;
-}
-
-static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
-                                  struct hw_perf_event *event)
-{
-        int idx;
-
-        /* Always place a cycle counter into the cycle counter. */
-        if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
-                if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
-                        return -EAGAIN;
-
-                return ARMV7_CYCLE_COUNTER;
-        } else {
-                /*
-                 * For anything other than a cycle counter, try and use
-                 * the events counters
-                 */
-                for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
-                        if (!test_and_set_bit(idx, cpuc->used_mask))
-                                return idx;
-                }
-
-                /* The counters are all in use. */
-                return -EAGAIN;
-        }
-}
-
-static struct arm_pmu armv7pmu = {
-        .handle_irq             = armv7pmu_handle_irq,
-        .enable                 = armv7pmu_enable_event,
-        .disable                = armv7pmu_disable_event,
-        .raw_event              = armv7pmu_raw_event,
-        .read_counter           = armv7pmu_read_counter,
-        .write_counter          = armv7pmu_write_counter,
-        .get_event_idx          = armv7pmu_get_event_idx,
-        .start                  = armv7pmu_start,
-        .stop                   = armv7pmu_stop,
-        .max_period             = (1LLU << 32) - 1,
-};
-
-static u32 __init armv7_reset_read_pmnc(void)
-{
-        u32 nb_cnt;
-
-        /* Initialize & Reset PMNC: C and P bits */
-        armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
-
-        /* Read the nb of CNTx counters supported from PMNC */
-        nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
-
-        /* Add the CPU cycles counter and return */
-        return nb_cnt + 1;
-}
-
-/*
- * ARMv5 [xscale] Performance counter handling code.
- *
- * Based on xscale OProfile code.
- *
- * There are two variants of the xscale PMU that we support:
- *      - xscale1pmu: 2 event counters and a cycle counter
- *      - xscale2pmu: 4 event counters and a cycle counter
- * The two variants share event definitions, but have different
- * PMU structures.
- */
-
-enum xscale_perf_types {
-        XSCALE_PERFCTR_ICACHE_MISS              = 0x00,
-        XSCALE_PERFCTR_ICACHE_NO_DELIVER        = 0x01,
-        XSCALE_PERFCTR_DATA_STALL               = 0x02,
-        XSCALE_PERFCTR_ITLB_MISS                = 0x03,
-        XSCALE_PERFCTR_DTLB_MISS                = 0x04,
-        XSCALE_PERFCTR_BRANCH                   = 0x05,
-        XSCALE_PERFCTR_BRANCH_MISS              = 0x06,
-        XSCALE_PERFCTR_INSTRUCTION              = 0x07,
-        XSCALE_PERFCTR_DCACHE_FULL_STALL        = 0x08,
-        XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
-        XSCALE_PERFCTR_DCACHE_ACCESS            = 0x0A,
-        XSCALE_PERFCTR_DCACHE_MISS              = 0x0B,
-        XSCALE_PERFCTR_DCACHE_WRITE_BACK        = 0x0C,
-        XSCALE_PERFCTR_PC_CHANGED               = 0x0D,
-        XSCALE_PERFCTR_BCU_REQUEST              = 0x10,
-        XSCALE_PERFCTR_BCU_FULL                 = 0x11,
-        XSCALE_PERFCTR_BCU_DRAIN                = 0x12,
-        XSCALE_PERFCTR_BCU_ECC_NO_ELOG          = 0x14,
-        XSCALE_PERFCTR_BCU_1_BIT_ERR            = 0x15,
-        XSCALE_PERFCTR_RMW                      = 0x16,
-        /* XSCALE_PERFCTR_CCNT is not hardware defined */
-        XSCALE_PERFCTR_CCNT                     = 0xFE,
-        XSCALE_PERFCTR_UNUSED                   = 0xFF,
-};
-
-enum xscale_counters {
-        XSCALE_CYCLE_COUNTER    = 1,
-        XSCALE_COUNTER0,
-        XSCALE_COUNTER1,
-        XSCALE_COUNTER2,
-        XSCALE_COUNTER3,
-};
-
-static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = XSCALE_PERFCTR_CCNT,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = XSCALE_PERFCTR_INSTRUCTION,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = XSCALE_PERFCTR_BRANCH_MISS,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
-};
-
-static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                           [PERF_COUNT_HW_CACHE_OP_MAX]
-                                           [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-        [C(L1D)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = XSCALE_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DCACHE_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = XSCALE_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DCACHE_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(L1I)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(LL)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(DTLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(ITLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(BPU)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-};
-
-#define XSCALE_PMU_ENABLE       0x001
-#define XSCALE_PMN_RESET        0x002
-#define XSCALE_CCNT_RESET       0x004
-#define XSCALE_PMU_RESET        (CCNT_RESET | PMN_RESET)
-#define XSCALE_PMU_CNT64        0x008
-
-static inline int
-xscalepmu_event_map(int config)
-{
-        int mapping = xscale_perf_map[config];
-        if (HW_OP_UNSUPPORTED == mapping)
-                mapping = -EOPNOTSUPP;
-        return mapping;
-}
-
-static u64
-xscalepmu_raw_event(u64 config)
-{
-        return config & 0xff;
-}
-
-#define XSCALE1_OVERFLOWED_MASK 0x700
-#define XSCALE1_CCOUNT_OVERFLOW 0x400
-#define XSCALE1_COUNT0_OVERFLOW 0x100
-#define XSCALE1_COUNT1_OVERFLOW 0x200
-#define XSCALE1_CCOUNT_INT_EN   0x040
-#define XSCALE1_COUNT0_INT_EN   0x010
-#define XSCALE1_COUNT1_INT_EN   0x020
-#define XSCALE1_COUNT0_EVT_SHFT 12
-#define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
-#define XSCALE1_COUNT1_EVT_SHFT 20
-#define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
-
-static inline u32
-xscale1pmu_read_pmnc(void)
-{
-        u32 val;
-        asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
-        return val;
-}
-
-static inline void
-xscale1pmu_write_pmnc(u32 val)
-{
-        /* upper 4bits and 7, 11 are write-as-0 */
-        val &= 0xffff77f;
-        asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
-}
-
-static inline int
-xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
-                                        enum xscale_counters counter)
-{
-        int ret = 0;
-
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
-                break;
-        case XSCALE_COUNTER0:
-                ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
-                break;
-        case XSCALE_COUNTER1:
-                ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
-        }
-
-        return ret;
-}
-
-static irqreturn_t
-xscale1pmu_handle_irq(int irq_num, void *dev)
-{
-        unsigned long pmnc;
-        struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
-        struct pt_regs *regs;
-        int idx;
-
-        /*
-         * NOTE: there's an A stepping erratum that states if an overflow
-         *       bit already exists and another occurs, the previous
-         *       Overflow bit gets cleared. There's no workaround.
-         *       Fixed in B stepping or later.
-         */
-        pmnc = xscale1pmu_read_pmnc();
-
-        /*
-         * Write the value back to clear the overflow flags. Overflow
-         * flags remain in pmnc for use below. We also disable the PMU
-         * while we process the interrupt.
-         */
-        xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
-
-        if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
-                return IRQ_NONE;
-
-        regs = get_irq_regs();
-
-        perf_sample_data_init(&data, 0);
-
-        cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
-                struct perf_event *event = cpuc->events[idx];
-                struct hw_perf_event *hwc;
-
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
-                if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
-                        continue;
-
-                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
-                if (!armpmu_event_set_period(event, hwc, idx))
-                        continue;
-
-                if (perf_event_overflow(event, 0, &data, regs))
-                        armpmu->disable(hwc, idx);
-        }
-
-        irq_work_run();
-
-        /*
-         * Re-enable the PMU.
-         */
-        pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
-        xscale1pmu_write_pmnc(pmnc);
-
-        return IRQ_HANDLED;
-}
-
-static void
-xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long val, mask, evt, flags;
-
-        switch (idx) {
-        case XSCALE_CYCLE_COUNTER:
-                mask = 0;
-                evt = XSCALE1_CCOUNT_INT_EN;
-                break;
-        case XSCALE_COUNTER0:
-                mask = XSCALE1_COUNT0_EVT_MASK;
-                evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
-                        XSCALE1_COUNT0_INT_EN;
-                break;
-        case XSCALE_COUNTER1:
-                mask = XSCALE1_COUNT1_EVT_MASK;
-                evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
-                        XSCALE1_COUNT1_INT_EN;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale1pmu_read_pmnc();
-        val &= ~mask;
-        val |= evt;
-        xscale1pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void
-xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long val, mask, evt, flags;
-
-        switch (idx) {
-        case XSCALE_CYCLE_COUNTER:
-                mask = XSCALE1_CCOUNT_INT_EN;
-                evt = 0;
-                break;
-        case XSCALE_COUNTER0:
-                mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
-                evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER1:
-                mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
-                evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale1pmu_read_pmnc();
-        val &= ~mask;
-        val |= evt;
-        xscale1pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static int
-xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc,
-                        struct hw_perf_event *event)
-{
-        if (XSCALE_PERFCTR_CCNT == event->config_base) {
-                if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
-                        return -EAGAIN;
-
-                return XSCALE_CYCLE_COUNTER;
-        } else {
-                if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) {
-                        return XSCALE_COUNTER1;
-                }
-
-                if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) {
-                        return XSCALE_COUNTER0;
-                }
-
-                return -EAGAIN;
-        }
-}
-
-static void
-xscale1pmu_start(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale1pmu_read_pmnc();
-        val |= XSCALE_PMU_ENABLE;
-        xscale1pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void
-xscale1pmu_stop(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale1pmu_read_pmnc();
-        val &= ~XSCALE_PMU_ENABLE;
-        xscale1pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static inline u32
-xscale1pmu_read_counter(int counter)
-{
-        u32 val = 0;
-
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER0:
-                asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER1:
-                asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
-                break;
-        }
-
-        return val;
-}
-
-static inline void
-xscale1pmu_write_counter(int counter, u32 val)
-{
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER0:
-                asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER1:
-                asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
-                break;
-        }
-}
-
-static const struct arm_pmu xscale1pmu = {
-        .id             = ARM_PERF_PMU_ID_XSCALE1,
-        .handle_irq     = xscale1pmu_handle_irq,
-        .enable         = xscale1pmu_enable_event,
-        .disable        = xscale1pmu_disable_event,
-        .event_map      = xscalepmu_event_map,
-        .raw_event      = xscalepmu_raw_event,
-        .read_counter   = xscale1pmu_read_counter,
-        .write_counter  = xscale1pmu_write_counter,
-        .get_event_idx  = xscale1pmu_get_event_idx,
-        .start          = xscale1pmu_start,
-        .stop           = xscale1pmu_stop,
-        .num_events     = 3,
-        .max_period     = (1LLU << 32) - 1,
-};
-
-#define XSCALE2_OVERFLOWED_MASK 0x01f
-#define XSCALE2_CCOUNT_OVERFLOW 0x001
-#define XSCALE2_COUNT0_OVERFLOW 0x002
-#define XSCALE2_COUNT1_OVERFLOW 0x004
-#define XSCALE2_COUNT2_OVERFLOW 0x008
-#define XSCALE2_COUNT3_OVERFLOW 0x010
-#define XSCALE2_CCOUNT_INT_EN   0x001
-#define XSCALE2_COUNT0_INT_EN   0x002
-#define XSCALE2_COUNT1_INT_EN   0x004
-#define XSCALE2_COUNT2_INT_EN   0x008
-#define XSCALE2_COUNT3_INT_EN   0x010
-#define XSCALE2_COUNT0_EVT_SHFT 0
-#define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
-#define XSCALE2_COUNT1_EVT_SHFT 8
-#define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
-#define XSCALE2_COUNT2_EVT_SHFT 16
-#define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
-#define XSCALE2_COUNT3_EVT_SHFT 24
-#define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
-
-static inline u32
-xscale2pmu_read_pmnc(void)
-{
-        u32 val;
-        asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
-        /* bits 1-2 and 4-23 are read-unpredictable */
-        return val & 0xff000009;
-}
-
-static inline void
-xscale2pmu_write_pmnc(u32 val)
-{
-        /* bits 4-23 are write-as-0, 24-31 are write ignored */
-        val &= 0xf;
-        asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
-}
-
-static inline u32
-xscale2pmu_read_overflow_flags(void)
-{
-        u32 val;
-        asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
-        return val;
-}
-
-static inline void
-xscale2pmu_write_overflow_flags(u32 val)
-{
-        asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
-}
-
-static inline u32
-xscale2pmu_read_event_select(void)
-{
-        u32 val;
-        asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
-        return val;
-}
-
-static inline void
-xscale2pmu_write_event_select(u32 val)
-{
-        asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
-}
-
-static inline u32
-xscale2pmu_read_int_enable(void)
-{
-        u32 val;
-        asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
-        return val;
-}
-
-static void
-xscale2pmu_write_int_enable(u32 val)
-{
-        asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
-}
-
-static inline int
-xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
-                                        enum xscale_counters counter)
-{
-        int ret = 0;
-
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
-                break;
-        case XSCALE_COUNTER0:
-                ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
-                break;
-        case XSCALE_COUNTER1:
-                ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
-                break;
-        case XSCALE_COUNTER2:
-                ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
-                break;
-        case XSCALE_COUNTER3:
-                ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
-        }
-
-        return ret;
-}
-
-static irqreturn_t
-xscale2pmu_handle_irq(int irq_num, void *dev)
-{
-        unsigned long pmnc, of_flags;
-        struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
-        struct pt_regs *regs;
-        int idx;
-
-        /* Disable the PMU. */
-        pmnc = xscale2pmu_read_pmnc();
-        xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
-
-        /* Check the overflow flag register. */
-        of_flags = xscale2pmu_read_overflow_flags();
-        if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
-                return IRQ_NONE;
-
-        /* Clear the overflow bits. */
-        xscale2pmu_write_overflow_flags(of_flags);
-
-        regs = get_irq_regs();
-
-        perf_sample_data_init(&data, 0);
-
-        cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
-                struct perf_event *event = cpuc->events[idx];
-                struct hw_perf_event *hwc;
-
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
-                if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
-                        continue;
-
-                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
-                if (!armpmu_event_set_period(event, hwc, idx))
-                        continue;
-
-                if (perf_event_overflow(event, 0, &data, regs))
-                        armpmu->disable(hwc, idx);
-        }
-
-        irq_work_run();
-
-        /*
-         * Re-enable the PMU.
-         */
-        pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
-        xscale2pmu_write_pmnc(pmnc);
-
-        return IRQ_HANDLED;
-}
-
-static void
-xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long flags, ien, evtsel;
-
-        ien = xscale2pmu_read_int_enable();
-        evtsel = xscale2pmu_read_event_select();
-
-        switch (idx) {
-        case XSCALE_CYCLE_COUNTER:
-                ien |= XSCALE2_CCOUNT_INT_EN;
-                break;
-        case XSCALE_COUNTER0:
-                ien |= XSCALE2_COUNT0_INT_EN;
-                evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
-                evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER1:
-                ien |= XSCALE2_COUNT1_INT_EN;
-                evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
-                evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER2:
-                ien |= XSCALE2_COUNT2_INT_EN;
-                evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
-                evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER3:
-                ien |= XSCALE2_COUNT3_INT_EN;
-                evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
-                evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        xscale2pmu_write_event_select(evtsel);
-        xscale2pmu_write_int_enable(ien);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void
-xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long flags, ien, evtsel;
-
-        ien = xscale2pmu_read_int_enable();
-        evtsel = xscale2pmu_read_event_select();
-
-        switch (idx) {
-        case XSCALE_CYCLE_COUNTER:
-                ien &= ~XSCALE2_CCOUNT_INT_EN;
-                break;
-        case XSCALE_COUNTER0:
-                ien &= ~XSCALE2_COUNT0_INT_EN;
-                evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
-                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER1:
-                ien &= ~XSCALE2_COUNT1_INT_EN;
-                evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
-                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER2:
-                ien &= ~XSCALE2_COUNT2_INT_EN;
-                evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
-                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER3:
-                ien &= ~XSCALE2_COUNT3_INT_EN;
-                evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
-                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        xscale2pmu_write_event_select(evtsel);
-        xscale2pmu_write_int_enable(ien);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static int
-xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc,
-                        struct hw_perf_event *event)
-{
-        int idx = xscale1pmu_get_event_idx(cpuc, event);
-        if (idx >= 0)
-                goto out;
-
-        if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
-                idx = XSCALE_COUNTER3;
-        else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
-                idx = XSCALE_COUNTER2;
-out:
-        return idx;
-}
-
-static void
-xscale2pmu_start(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
-        val |= XSCALE_PMU_ENABLE;
-        xscale2pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void
-xscale2pmu_stop(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale2pmu_read_pmnc();
-        val &= ~XSCALE_PMU_ENABLE;
-        xscale2pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static inline u32
-xscale2pmu_read_counter(int counter)
-{
-        u32 val = 0;
-
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER0:
-                asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER1:
-                asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER2:
-                asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER3:
-                asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
-                break;
-        }
-
-        return val;
-}
-
-static inline void
-xscale2pmu_write_counter(int counter, u32 val)
-{
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER0:
-                asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER1:
-                asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER2:
-                asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER3:
-                asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
-                break;
-        }
-}
-
-static const struct arm_pmu xscale2pmu = {
-        .id             = ARM_PERF_PMU_ID_XSCALE2,
-        .handle_irq     = xscale2pmu_handle_irq,
-        .enable         = xscale2pmu_enable_event,
-        .disable        = xscale2pmu_disable_event,
-        .event_map      = xscalepmu_event_map,
-        .raw_event      = xscalepmu_raw_event,
-        .read_counter   = xscale2pmu_read_counter,
-        .write_counter  = xscale2pmu_write_counter,
-        .get_event_idx  = xscale2pmu_get_event_idx,
-        .start          = xscale2pmu_start,
-        .stop           = xscale2pmu_stop,
-        .num_events     = 5,
-        .max_period     = (1LLU << 32) - 1,
-};
+/* Include the PMU-specific implementations. */
+#include "perf_event_xscale.c"
+#include "perf_event_v6.c"
+#include "perf_event_v7.c"
 
 static int __init
 init_hw_perf_events(void)
@@ -2977,37 +622,16 @@ init_hw_perf_events(void)
                 case 0xB360:    /* ARM1136 */
                 case 0xB560:    /* ARM1156 */
                 case 0xB760:    /* ARM1176 */
-                        armpmu = &armv6pmu;
-                        memcpy(armpmu_perf_cache_map, armv6_perf_cache_map,
-                                        sizeof(armv6_perf_cache_map));
+                        armpmu = armv6pmu_init();
                         break;
                 case 0xB020:    /* ARM11mpcore */
-                        armpmu = &armv6mpcore_pmu;
-                        memcpy(armpmu_perf_cache_map,
-                               armv6mpcore_perf_cache_map,
-                               sizeof(armv6mpcore_perf_cache_map));
+                        armpmu = armv6mpcore_pmu_init();
                         break;
                 case 0xC080:    /* Cortex-A8 */
-                        armv7pmu.id = ARM_PERF_PMU_ID_CA8;
-                        memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map,
-                                sizeof(armv7_a8_perf_cache_map));
-                        armv7pmu.event_map = armv7_a8_pmu_event_map;
-                        armpmu = &armv7pmu;
-
-                        /* Reset PMNC and read the nb of CNTx counters
-                            supported */
-                        armv7pmu.num_events = armv7_reset_read_pmnc();
+                        armpmu = armv7_a8_pmu_init();
                         break;
                 case 0xC090:    /* Cortex-A9 */
-                        armv7pmu.id = ARM_PERF_PMU_ID_CA9;
-                        memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map,
-                                sizeof(armv7_a9_perf_cache_map));
-                        armv7pmu.event_map = armv7_a9_pmu_event_map;
-                        armpmu = &armv7pmu;
-
-                        /* Reset PMNC and read the nb of CNTx counters
-                            supported */
-                        armv7pmu.num_events = armv7_reset_read_pmnc();
+                        armpmu = armv7_a9_pmu_init();
                         break;
                 }
         /* Intel CPUs [xscale]. */
@@ -3015,30 +639,26 @@ init_hw_perf_events(void)
                 part_number = (cpuid >> 13) & 0x7;
                 switch (part_number) {
                 case 1:
-                        armpmu = &xscale1pmu;
-                        memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
-                                        sizeof(xscale_perf_cache_map));
+                        armpmu = xscale1pmu_init();
                         break;
                 case 2:
-                        armpmu = &xscale2pmu;
-                        memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
-                                        sizeof(xscale_perf_cache_map));
+                        armpmu = xscale2pmu_init();
                         break;
                 }
         }
 
         if (armpmu) {
                 pr_info("enabled with %s PMU driver, %d counters available\n",
-                                arm_pmu_names[armpmu->id], armpmu->num_events);
+                        armpmu->name, armpmu->num_events);
         } else {
                 pr_info("no hardware support available\n");
         }
 
-        perf_pmu_register(&pmu);
+        perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
 
         return 0;
 }
-arch_initcall(init_hw_perf_events);
+early_initcall(init_hw_perf_events);
 
 /*
  * Callchain handling code.
@@ -3053,17 +673,17 @@ arch_initcall(init_hw_perf_events);
  * This code has been adapted from the ARM OProfile support.
  */
 struct frame_tail {
-        struct frame_tail   *fp;
-        unsigned long       sp;
-        unsigned long       lr;
+        struct frame_tail __user *fp;
+        unsigned long sp;
+        unsigned long lr;
 } __attribute__((packed));
 
 /*
  * Get the return address for a single stackframe and return a pointer to the
  * next frame tail.
  */
-static struct frame_tail *
-user_backtrace(struct frame_tail *tail,
+static struct frame_tail __user *
+user_backtrace(struct frame_tail __user *tail,
                struct perf_callchain_entry *entry)
 {
         struct frame_tail buftail;
@@ -3089,10 +709,10 @@ user_backtrace(struct frame_tail *tail,
 void
 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 {
-        struct frame_tail *tail;
+        struct frame_tail __user *tail;
 
 
-        tail = (struct frame_tail *)regs->ARM_fp - 1;
+        tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 
         while (tail && !((unsigned long)tail & 0x3))
                 tail = user_backtrace(tail, entry);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
new file mode 100644
index 000000000000..c058bfc8532b
--- /dev/null
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -0,0 +1,672 @@
+/*
+ * ARMv6 Performance counter handling code.
+ *
+ * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
+ *
+ * ARMv6 has 2 configurable performance counters and a single cycle counter.
+ * They all share a single reset bit but can be written to zero so we can use
+ * that for a reset.
+ *
+ * The counters can't be individually enabled or disabled so when we remove
+ * one event and replace it with another we could get spurious counts from the
+ * wrong event. However, we can take advantage of the fact that the
+ * performance counters can export events to the event bus, and the event bus
+ * itself can be monitored. This requires that we *don't* export the events to
+ * the event bus. The procedure for disabling a configurable counter is:
+ *      - change the counter to count the ETMEXTOUT[0] signal (0x20). This
+ *        effectively stops the counter from counting.
+ *      - disable the counter's interrupt generation (each counter has it's
+ *        own interrupt enable bit).
+ * Once stopped, the counter value can be written as 0 to reset.
+ *
+ * To enable a counter:
+ *      - enable the counter's interrupt generation.
+ *      - set the new event type.
+ *
+ * Note: the dedicated cycle counter only counts cycles and can't be
+ * enabled/disabled independently of the others. When we want to disable the
+ * cycle counter, we have to just disable the interrupt reporting and start
+ * ignoring that counter. When re-enabling, we have to reset the value and
+ * enable the interrupt.
+ */
+
+#ifdef CONFIG_CPU_V6
+enum armv6_perf_types {
+        ARMV6_PERFCTR_ICACHE_MISS           = 0x0,
+        ARMV6_PERFCTR_IBUF_STALL            = 0x1,
+        ARMV6_PERFCTR_DDEP_STALL            = 0x2,
+        ARMV6_PERFCTR_ITLB_MISS             = 0x3,
+        ARMV6_PERFCTR_DTLB_MISS             = 0x4,
+        ARMV6_PERFCTR_BR_EXEC               = 0x5,
+        ARMV6_PERFCTR_BR_MISPREDICT         = 0x6,
+        ARMV6_PERFCTR_INSTR_EXEC            = 0x7,
+        ARMV6_PERFCTR_DCACHE_HIT            = 0x9,
+        ARMV6_PERFCTR_DCACHE_ACCESS         = 0xA,
+        ARMV6_PERFCTR_DCACHE_MISS           = 0xB,
+        ARMV6_PERFCTR_DCACHE_WBACK          = 0xC,
+        ARMV6_PERFCTR_SW_PC_CHANGE          = 0xD,
+        ARMV6_PERFCTR_MAIN_TLB_MISS         = 0xF,
+        ARMV6_PERFCTR_EXPL_D_ACCESS         = 0x10,
+        ARMV6_PERFCTR_LSU_FULL_STALL        = 0x11,
+        ARMV6_PERFCTR_WBUF_DRAINED          = 0x12,
+        ARMV6_PERFCTR_CPU_CYCLES            = 0xFF,
+        ARMV6_PERFCTR_NOP                   = 0x20,
+};
+
+enum armv6_counters {
+        ARMV6_CYCLE_COUNTER = 1,
+        ARMV6_COUNTER0,
+        ARMV6_COUNTER1,
+};
+
+/*
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * The ARM performance counters can count micro DTLB misses,
+                 * micro ITLB misses and main TLB misses. There isn't an event
+                 * for TLB misses, so use the micro misses here and if users
+                 * want the main TLB misses they can use a raw counter.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+enum armv6mpcore_perf_types {
+        ARMV6MPCORE_PERFCTR_ICACHE_MISS     = 0x0,
+        ARMV6MPCORE_PERFCTR_IBUF_STALL      = 0x1,
+        ARMV6MPCORE_PERFCTR_DDEP_STALL      = 0x2,
+        ARMV6MPCORE_PERFCTR_ITLB_MISS       = 0x3,
+        ARMV6MPCORE_PERFCTR_DTLB_MISS       = 0x4,
+        ARMV6MPCORE_PERFCTR_BR_EXEC         = 0x5,
+        ARMV6MPCORE_PERFCTR_BR_NOTPREDICT   = 0x6,
+        ARMV6MPCORE_PERFCTR_BR_MISPREDICT   = 0x7,
+        ARMV6MPCORE_PERFCTR_INSTR_EXEC      = 0x8,
+        ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
+        ARMV6MPCORE_PERFCTR_DCACHE_RDMISS   = 0xB,
+        ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
+        ARMV6MPCORE_PERFCTR_DCACHE_WRMISS   = 0xD,
+        ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
+        ARMV6MPCORE_PERFCTR_SW_PC_CHANGE    = 0xF,
+        ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS   = 0x10,
+        ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
+        ARMV6MPCORE_PERFCTR_LSU_FULL_STALL  = 0x12,
+        ARMV6MPCORE_PERFCTR_WBUF_DRAINED    = 0x13,
+        ARMV6MPCORE_PERFCTR_CPU_CYCLES      = 0xFF,
+};
+
+/*
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                        [PERF_COUNT_HW_CACHE_OP_MAX]
+                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  =
+                                ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
+                        [C(RESULT_MISS)]    =
+                                ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  =
+                                ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
+                        [C(RESULT_MISS)]    =
+                                ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * The ARM performance counters can count micro DTLB misses,
+                 * micro ITLB misses and main TLB misses. There isn't an event
+                 * for TLB misses, so use the micro misses here and if users
+                 * want the main TLB misses they can use a raw counter.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+static inline unsigned long
+armv6_pmcr_read(void)
+{
+        u32 val;
+        asm volatile("mrc   p15, 0, %0, c15, c12, 0" : "=r"(val));
+        return val;
+}
+
+static inline void
+armv6_pmcr_write(unsigned long val)
+{
+        asm volatile("mcr   p15, 0, %0, c15, c12, 0" : : "r"(val));
+}
+
+#define ARMV6_PMCR_ENABLE               (1 << 0)
+#define ARMV6_PMCR_CTR01_RESET          (1 << 1)
+#define ARMV6_PMCR_CCOUNT_RESET         (1 << 2)
+#define ARMV6_PMCR_CCOUNT_DIV           (1 << 3)
+#define ARMV6_PMCR_COUNT0_IEN           (1 << 4)
+#define ARMV6_PMCR_COUNT1_IEN           (1 << 5)
+#define ARMV6_PMCR_CCOUNT_IEN           (1 << 6)
+#define ARMV6_PMCR_COUNT0_OVERFLOW      (1 << 8)
+#define ARMV6_PMCR_COUNT1_OVERFLOW      (1 << 9)
+#define ARMV6_PMCR_CCOUNT_OVERFLOW      (1 << 10)
+#define ARMV6_PMCR_EVT_COUNT0_SHIFT     20
+#define ARMV6_PMCR_EVT_COUNT0_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
+#define ARMV6_PMCR_EVT_COUNT1_SHIFT     12
+#define ARMV6_PMCR_EVT_COUNT1_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
+
+#define ARMV6_PMCR_OVERFLOWED_MASK \
+        (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
+         ARMV6_PMCR_CCOUNT_OVERFLOW)
+
+static inline int
+armv6_pmcr_has_overflowed(unsigned long pmcr)
+{
+        return pmcr & ARMV6_PMCR_OVERFLOWED_MASK;
+}
+
+static inline int
+armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
+                                  enum armv6_counters counter)
+{
+        int ret = 0;
+
+        if (ARMV6_CYCLE_COUNTER == counter)
+                ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
+        else if (ARMV6_COUNTER0 == counter)
+                ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
+        else if (ARMV6_COUNTER1 == counter)
+                ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+
+        return ret;
+}
+
+static inline u32
+armv6pmu_read_counter(int counter)
+{
+        unsigned long value = 0;
+
+        if (ARMV6_CYCLE_COUNTER == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 1" : "=r"(value));
+        else if (ARMV6_COUNTER0 == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 2" : "=r"(value));
+        else if (ARMV6_COUNTER1 == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 3" : "=r"(value));
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+
+        return value;
+}
+
+static inline void
+armv6pmu_write_counter(int counter,
+                       u32 value)
+{
+        if (ARMV6_CYCLE_COUNTER == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 1" : : "r"(value));
+        else if (ARMV6_COUNTER0 == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 2" : : "r"(value));
+        else if (ARMV6_COUNTER1 == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 3" : : "r"(value));
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+}
+
+static void
+armv6pmu_enable_event(struct hw_perf_event *hwc,
+                      int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = 0;
+                evt     = ARMV6_PMCR_CCOUNT_IEN;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_EVT_COUNT0_MASK;
+                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
+                          ARMV6_PMCR_COUNT0_IEN;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_EVT_COUNT1_MASK;
+                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
+                          ARMV6_PMCR_COUNT1_IEN;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Mask out the current event and set the counter to count the event
+         * that we're interested in.
+         */
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static irqreturn_t
+armv6pmu_handle_irq(int irq_num,
+                    void *dev)
+{
+        unsigned long pmcr = armv6_pmcr_read();
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        if (!armv6_pmcr_has_overflowed(pmcr))
+                return IRQ_NONE;
+
+        regs = get_irq_regs();
+
+        /*
+         * The interrupts are cleared by writing the overflow flags back to
+         * the control register. All of the other bits don't have any effect
+         * if they are rewritten, so write the whole value back.
+         */
+        armv6_pmcr_write(pmcr);
+
+        perf_sample_data_init(&data, 0);
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                /*
+                 * We have a single interrupt for all counters. Check that
+                 * each counter has overflowed before we process it.
+                 */
+                if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        /*
+         * Handle the pending perf events.
+         *
+         * Note: this call *must* be run with interrupts disabled. For
+         * platforms that can have the PMU interrupts raised as an NMI, this
+         * will not work.
+         */
+        irq_work_run();
+
+        return IRQ_HANDLED;
+}
+
+static void
+armv6pmu_start(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val |= ARMV6_PMCR_ENABLE;
+        armv6_pmcr_write(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+armv6pmu_stop(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~ARMV6_PMCR_ENABLE;
+        armv6_pmcr_write(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static int
+armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                       struct hw_perf_event *event)
+{
+        /* Always place a cycle counter into the cycle counter. */
+        if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
+                if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
+                        return -EAGAIN;
+
+                return ARMV6_CYCLE_COUNTER;
+        } else {
+                /*
+                 * For anything other than a cycle counter, try and use
+                 * counter0 and counter1.
+                 */
+                if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask))
+                        return ARMV6_COUNTER1;
+
+                if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask))
+                        return ARMV6_COUNTER0;
+
+                /* The counters are all in use. */
+                return -EAGAIN;
+        }
+}
+
+static void
+armv6pmu_disable_event(struct hw_perf_event *hwc,
+                       int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = ARMV6_PMCR_CCOUNT_IEN;
+                evt     = 0;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
+                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
+                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Mask out the current event and set the counter to count the number
+         * of ETM bus signal assertion cycles. The external reporting should
+         * be disabled and so this should never increment.
+         */
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
+                              int idx)
+{
+        unsigned long val, mask, flags, evt = 0;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = ARMV6_PMCR_CCOUNT_IEN;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_COUNT0_IEN;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_COUNT1_IEN;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Unlike UP ARMv6, we don't have a way of stopping the counters. We
+         * simply disable the interrupt reporting.
+         */
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static const struct arm_pmu armv6pmu = {
+        .id                     = ARM_PERF_PMU_ID_V6,
+        .name                   = "v6",
+        .handle_irq             = armv6pmu_handle_irq,
+        .enable                 = armv6pmu_enable_event,
+        .disable                = armv6pmu_disable_event,
+        .read_counter           = armv6pmu_read_counter,
+        .write_counter          = armv6pmu_write_counter,
+        .get_event_idx          = armv6pmu_get_event_idx,
+        .start                  = armv6pmu_start,
+        .stop                   = armv6pmu_stop,
+        .cache_map              = &armv6_perf_cache_map,
+        .event_map              = &armv6_perf_map,
+        .raw_event_mask         = 0xFF,
+        .num_events             = 3,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+static const struct arm_pmu *__init armv6pmu_init(void)
+{
+        return &armv6pmu;
+}
+
+/*
+ * ARMv6mpcore is almost identical to single core ARMv6 with the exception
+ * that some of the events have different enumerations and that there is no
+ * *hack* to stop the programmable counters. To stop the counters we simply
+ * disable the interrupt reporting and update the event. When unthrottling we
+ * reset the period and enable the interrupt reporting.
+ */
+static const struct arm_pmu armv6mpcore_pmu = {
+        .id                     = ARM_PERF_PMU_ID_V6MP,
+        .name                   = "v6mpcore",
+        .handle_irq             = armv6pmu_handle_irq,
+        .enable                 = armv6pmu_enable_event,
+        .disable                = armv6mpcore_pmu_disable_event,
+        .read_counter           = armv6pmu_read_counter,
+        .write_counter          = armv6pmu_write_counter,
+        .get_event_idx          = armv6pmu_get_event_idx,
+        .start                  = armv6pmu_start,
+        .stop                   = armv6pmu_stop,
+        .cache_map              = &armv6mpcore_perf_cache_map,
+        .event_map              = &armv6mpcore_perf_map,
+        .raw_event_mask         = 0xFF,
+        .num_events             = 3,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
+{
+        return &armv6mpcore_pmu;
+}
+#else
+static const struct arm_pmu *__init armv6pmu_init(void)
+{
+        return NULL;
+}
+
+static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
+{
+        return NULL;
+}
+#endif  /* CONFIG_CPU_V6 */
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
new file mode 100644
index 000000000000..2e1402556fa0
--- /dev/null
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -0,0 +1,906 @@
+/*
+ * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
+ *
+ * ARMv7 support: Jean Pihet <jpihet@mvista.com>
+ * 2010 (c) MontaVista Software, LLC.
+ *
+ * Copied from ARMv6 code, with the low level code inspired
+ *  by the ARMv7 Oprofile code.
+ *
+ * Cortex-A8 has up to 4 configurable performance counters and
+ *  a single cycle counter.
+ * Cortex-A9 has up to 31 configurable performance counters and
+ *  a single cycle counter.
+ *
+ * All counters can be enabled/disabled and IRQ masked separately. The cycle
+ *  counter and all 4 performance counters together can be reset separately.
+ */
+
+#ifdef CONFIG_CPU_V7
+/* Common ARMv7 event types */
+enum armv7_perf_types {
+        ARMV7_PERFCTR_PMNC_SW_INCR              = 0x00,
+        ARMV7_PERFCTR_IFETCH_MISS               = 0x01,
+        ARMV7_PERFCTR_ITLB_MISS                 = 0x02,
+        ARMV7_PERFCTR_DCACHE_REFILL             = 0x03,
+        ARMV7_PERFCTR_DCACHE_ACCESS             = 0x04,
+        ARMV7_PERFCTR_DTLB_REFILL               = 0x05,
+        ARMV7_PERFCTR_DREAD                     = 0x06,
+        ARMV7_PERFCTR_DWRITE                    = 0x07,
+
+        ARMV7_PERFCTR_EXC_TAKEN                 = 0x09,
+        ARMV7_PERFCTR_EXC_EXECUTED              = 0x0A,
+        ARMV7_PERFCTR_CID_WRITE                 = 0x0B,
+        /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
+         * It counts:
+         *  - all branch instructions,
+         *  - instructions that explicitly write the PC,
+         *  - exception generating instructions.
+         */
+        ARMV7_PERFCTR_PC_WRITE                  = 0x0C,
+        ARMV7_PERFCTR_PC_IMM_BRANCH             = 0x0D,
+        ARMV7_PERFCTR_UNALIGNED_ACCESS          = 0x0F,
+        ARMV7_PERFCTR_PC_BRANCH_MIS_PRED        = 0x10,
+        ARMV7_PERFCTR_CLOCK_CYCLES              = 0x11,
+
+        ARMV7_PERFCTR_PC_BRANCH_MIS_USED        = 0x12,
+
+        ARMV7_PERFCTR_CPU_CYCLES                = 0xFF
+};
+
+/* ARMv7 Cortex-A8 specific event types */
+enum armv7_a8_perf_types {
+        ARMV7_PERFCTR_INSTR_EXECUTED            = 0x08,
+
+        ARMV7_PERFCTR_PC_PROC_RETURN            = 0x0E,
+
+        ARMV7_PERFCTR_WRITE_BUFFER_FULL         = 0x40,
+        ARMV7_PERFCTR_L2_STORE_MERGED           = 0x41,
+        ARMV7_PERFCTR_L2_STORE_BUFF             = 0x42,
+        ARMV7_PERFCTR_L2_ACCESS                 = 0x43,
+        ARMV7_PERFCTR_L2_CACH_MISS              = 0x44,
+        ARMV7_PERFCTR_AXI_READ_CYCLES           = 0x45,
+        ARMV7_PERFCTR_AXI_WRITE_CYCLES          = 0x46,
+        ARMV7_PERFCTR_MEMORY_REPLAY             = 0x47,
+        ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY   = 0x48,
+        ARMV7_PERFCTR_L1_DATA_MISS              = 0x49,
+        ARMV7_PERFCTR_L1_INST_MISS              = 0x4A,
+        ARMV7_PERFCTR_L1_DATA_COLORING          = 0x4B,
+        ARMV7_PERFCTR_L1_NEON_DATA              = 0x4C,
+        ARMV7_PERFCTR_L1_NEON_CACH_DATA         = 0x4D,
+        ARMV7_PERFCTR_L2_NEON                   = 0x4E,
+        ARMV7_PERFCTR_L2_NEON_HIT               = 0x4F,
+        ARMV7_PERFCTR_L1_INST                   = 0x50,
+        ARMV7_PERFCTR_PC_RETURN_MIS_PRED        = 0x51,
+        ARMV7_PERFCTR_PC_BRANCH_FAILED          = 0x52,
+        ARMV7_PERFCTR_PC_BRANCH_TAKEN           = 0x53,
+        ARMV7_PERFCTR_PC_BRANCH_EXECUTED        = 0x54,
+        ARMV7_PERFCTR_OP_EXECUTED               = 0x55,
+        ARMV7_PERFCTR_CYCLES_INST_STALL         = 0x56,
+        ARMV7_PERFCTR_CYCLES_INST               = 0x57,
+        ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL    = 0x58,
+        ARMV7_PERFCTR_CYCLES_NEON_INST_STALL    = 0x59,
+        ARMV7_PERFCTR_NEON_CYCLES               = 0x5A,
+
+        ARMV7_PERFCTR_PMU0_EVENTS               = 0x70,
+        ARMV7_PERFCTR_PMU1_EVENTS               = 0x71,
+        ARMV7_PERFCTR_PMU_EVENTS                = 0x72,
+};
+
+/* ARMv7 Cortex-A9 specific event types */
+enum armv7_a9_perf_types {
+        ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC     = 0x40,
+        ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC     = 0x41,
+        ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC       = 0x42,
+
+        ARMV7_PERFCTR_COHERENT_LINE_MISS        = 0x50,
+        ARMV7_PERFCTR_COHERENT_LINE_HIT         = 0x51,
+
+        ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES   = 0x60,
+        ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES   = 0x61,
+        ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
+        ARMV7_PERFCTR_STREX_EXECUTED_PASSED     = 0x63,
+        ARMV7_PERFCTR_STREX_EXECUTED_FAILED     = 0x64,
+        ARMV7_PERFCTR_DATA_EVICTION             = 0x65,
+        ARMV7_PERFCTR_ISSUE_STAGE_NO_INST       = 0x66,
+        ARMV7_PERFCTR_ISSUE_STAGE_EMPTY         = 0x67,
+        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE  = 0x68,
+
+        ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
+
+        ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST   = 0x70,
+        ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
+        ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST  = 0x72,
+        ARMV7_PERFCTR_FP_EXECUTED_INST          = 0x73,
+        ARMV7_PERFCTR_NEON_EXECUTED_INST        = 0x74,
+
+        ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
+        ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES  = 0x81,
+        ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
+        ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
+        ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
+        ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
+        ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES      = 0x86,
+
+        ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
+        ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
+
+        ARMV7_PERFCTR_ISB_INST                  = 0x90,
+        ARMV7_PERFCTR_DSB_INST                  = 0x91,
+        ARMV7_PERFCTR_DMB_INST                  = 0x92,
+        ARMV7_PERFCTR_EXT_INTERRUPTS            = 0x93,
+
+        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
+        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
+        ARMV7_PERFCTR_PLE_FIFO_FLUSH            = 0xA2,
+        ARMV7_PERFCTR_PLE_RQST_COMPLETED        = 0xA3,
+        ARMV7_PERFCTR_PLE_FIFO_OVERFLOW         = 0xA4,
+        ARMV7_PERFCTR_PLE_RQST_PROG             = 0xA5
+};
+
+/*
+ * Cortex-A8 HW events mapping
+ *
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+
+static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * Only ITLB misses and DTLB refills are supported.
+                 * If users want the DTLB refills misses a raw counter
+                 * must be used.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+/*
+ * Cortex-A9 HW events mapping
+ */
+static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        =
+                                        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_COHERENT_LINE_HIT,
+        [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_COHERENT_LINE_MISS,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+
+static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * Only ITLB misses and DTLB refills are supported.
+                 * If users want the DTLB refills misses a raw counter
+                 * must be used.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+/*
+ * Perf Events counters
+ */
+enum armv7_counters {
+        ARMV7_CYCLE_COUNTER             = 1,    /* Cycle counter */
+        ARMV7_COUNTER0                  = 2,    /* First event counter */
+};
+
+/*
+ * The cycle counter is ARMV7_CYCLE_COUNTER.
+ * The first event counter is ARMV7_COUNTER0.
+ * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
+ */
+#define ARMV7_COUNTER_LAST      (ARMV7_COUNTER0 + armpmu->num_events - 1)
+
+/*
+ * ARMv7 low level PMNC access
+ */
+
+/*
+ * Per-CPU PMNC: config reg
+ */
+#define ARMV7_PMNC_E            (1 << 0) /* Enable all counters */
+#define ARMV7_PMNC_P            (1 << 1) /* Reset all counters */
+#define ARMV7_PMNC_C            (1 << 2) /* Cycle counter reset */
+#define ARMV7_PMNC_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
+#define ARMV7_PMNC_X            (1 << 4) /* Export to ETM */
+#define ARMV7_PMNC_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
+#define ARMV7_PMNC_N_SHIFT      11       /* Number of counters supported */
+#define ARMV7_PMNC_N_MASK       0x1f
+#define ARMV7_PMNC_MASK         0x3f     /* Mask for writable bits */
+
+/*
+ * Available counters
+ */
+#define ARMV7_CNT0              0       /* First event counter */
+#define ARMV7_CCNT              31      /* Cycle counter */
+
+/* Perf Event to low level counters mapping */
+#define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
+
+/*
+ * CNTENS: counters enable reg
+ */
+#define ARMV7_CNTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_CNTENS_C          (1 << ARMV7_CCNT)
+
+/*
+ * CNTENC: counters disable reg
+ */
+#define ARMV7_CNTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_CNTENC_C          (1 << ARMV7_CCNT)
+
+/*
+ * INTENS: counters overflow interrupt enable reg
+ */
+#define ARMV7_INTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_INTENS_C          (1 << ARMV7_CCNT)
+
+/*
+ * INTENC: counters overflow interrupt disable reg
+ */
+#define ARMV7_INTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_INTENC_C          (1 << ARMV7_CCNT)
+
+/*
+ * EVTSEL: Event selection reg
+ */
+#define ARMV7_EVTSEL_MASK       0xff            /* Mask for writable bits */
+
+/*
+ * SELECT: Counter selection reg
+ */
+#define ARMV7_SELECT_MASK       0x1f            /* Mask for writable bits */
+
+/*
+ * FLAG: counters overflow flag status reg
+ */
+#define ARMV7_FLAG_P(idx)       (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_FLAG_C            (1 << ARMV7_CCNT)
+#define ARMV7_FLAG_MASK         0xffffffff      /* Mask for writable bits */
+#define ARMV7_OVERFLOWED_MASK   ARMV7_FLAG_MASK
+
+static inline unsigned long armv7_pmnc_read(void)
+{
+        u32 val;
+        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
+        return val;
+}
+
+static inline void armv7_pmnc_write(unsigned long val)
+{
+        val &= ARMV7_PMNC_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
+}
+
+static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
+{
+        return pmnc & ARMV7_OVERFLOWED_MASK;
+}
+
+static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
+                                        enum armv7_counters counter)
+{
+        int ret = 0;
+
+        if (counter == ARMV7_CYCLE_COUNTER)
+                ret = pmnc & ARMV7_FLAG_C;
+        else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
+                ret = pmnc & ARMV7_FLAG_P(counter);
+        else
+                pr_err("CPU%u checking wrong counter %d overflow status\n",
+                        smp_processor_id(), counter);
+
+        return ret;
+}
+
+static inline int armv7_pmnc_select_counter(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
+                pr_err("CPU%u selecting wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7pmu_read_counter(int idx)
+{
+        unsigned long value = 0;
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
+        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
+                if (armv7_pmnc_select_counter(idx) == idx)
+                        asm volatile("mrc p15, 0, %0, c9, c13, 2"
+                                     : "=r" (value));
+        } else
+                pr_err("CPU%u reading wrong counter %d\n",
+                        smp_processor_id(), idx);
+
+        return value;
+}
+
+static inline void armv7pmu_write_counter(int idx, u32 value)
+{
+        if (idx == ARMV7_CYCLE_COUNTER)
+                asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
+        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
+                if (armv7_pmnc_select_counter(idx) == idx)
+                        asm volatile("mcr p15, 0, %0, c9, c13, 2"
+                                     : : "r" (value));
+        } else
+                pr_err("CPU%u writing wrong counter %d\n",
+                        smp_processor_id(), idx);
+}
+
+static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
+{
+        if (armv7_pmnc_select_counter(idx) == idx) {
+                val &= ARMV7_EVTSEL_MASK;
+                asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
+        }
+}
+
+static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u enabling wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_CNTENS_C;
+        else
+                val = ARMV7_CNTENS_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
+{
+        u32 val;
+
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u disabling wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_CNTENC_C;
+        else
+                val = ARMV7_CNTENC_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u enabling wrong PMNC counter"
+                        " interrupt enable %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_INTENS_C;
+        else
+                val = ARMV7_INTENS_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u disabling wrong PMNC counter"
+                        " interrupt enable %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_INTENC_C;
+        else
+                val = ARMV7_INTENC_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_getreset_flags(void)
+{
+        u32 val;
+
+        /* Read */
+        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+
+        /* Write to clear flags */
+        val &= ARMV7_FLAG_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
+
+        return val;
+}
+
+#ifdef DEBUG
+static void armv7_pmnc_dump_regs(void)
+{
+        u32 val;
+        unsigned int cnt;
+
+        printk(KERN_INFO "PMNC registers dump:\n");
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
+        printk(KERN_INFO "PMNC  =0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
+        printk(KERN_INFO "CNTENS=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
+        printk(KERN_INFO "INTENS=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+        printk(KERN_INFO "FLAGS =0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
+        printk(KERN_INFO "SELECT=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
+        printk(KERN_INFO "CCNT  =0x%08x\n", val);
+
+        for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
+                armv7_pmnc_select_counter(cnt);
+                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
+                printk(KERN_INFO "CNT[%d] count =0x%08x\n",
+                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
+                asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
+                printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
+                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
+        }
+}
+#endif
+
+static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags;
+
+        /*
+         * Enable counter and interrupt, and set the counter to count
+         * the event that we're interested in.
+         */
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+
+        /*
+         * Disable counter
+         */
+        armv7_pmnc_disable_counter(idx);
+
+        /*
+         * Set event (if destined for PMNx counters)
+         * We don't need to set the event if it's a cycle count
+         */
+        if (idx != ARMV7_CYCLE_COUNTER)
+                armv7_pmnc_write_evtsel(idx, hwc->config_base);
+
+        /*
+         * Enable interrupt for this counter
+         */
+        armv7_pmnc_enable_intens(idx);
+
+        /*
+         * Enable counter
+         */
+        armv7_pmnc_enable_counter(idx);
+
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags;
+
+        /*
+         * Disable counter and interrupt
+         */
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+
+        /*
+         * Disable counter
+         */
+        armv7_pmnc_disable_counter(idx);
+
+        /*
+         * Disable interrupt for this counter
+         */
+        armv7_pmnc_disable_intens(idx);
+
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
+{
+        unsigned long pmnc;
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        /*
+         * Get and reset the IRQ flags
+         */
+        pmnc = armv7_pmnc_getreset_flags();
+
+        /*
+         * Did an overflow occur?
+         */
+        if (!armv7_pmnc_has_overflowed(pmnc))
+                return IRQ_NONE;
+
+        /*
+         * Handle the counter(s) overflow(s)
+         */
+        regs = get_irq_regs();
+
+        perf_sample_data_init(&data, 0);
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                /*
+                 * We have a single interrupt for all counters. Check that
+                 * each counter has overflowed before we process it.
+                 */
+                if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        /*
+         * Handle the pending perf events.
+         *
+         * Note: this call *must* be run with interrupts disabled. For
+         * platforms that can have the PMU interrupts raised as an NMI, this
+         * will not work.
+         */
+        irq_work_run();
+
+        return IRQ_HANDLED;
+}
+
+static void armv7pmu_start(void)
+{
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        /* Enable all counters */
+        armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void armv7pmu_stop(void)
+{
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        /* Disable all counters */
+        armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                                  struct hw_perf_event *event)
+{
+        int idx;
+
+        /* Always place a cycle counter into the cycle counter. */
+        if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
+                if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
+                        return -EAGAIN;
+
+                return ARMV7_CYCLE_COUNTER;
+        } else {
+                /*
+                 * For anything other than a cycle counter, try and use
+                 * the events counters
+                 */
+                for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
+                        if (!test_and_set_bit(idx, cpuc->used_mask))
+                                return idx;
+                }
+
+                /* The counters are all in use. */
+                return -EAGAIN;
+        }
+}
+
+static struct arm_pmu armv7pmu = {
+        .handle_irq             = armv7pmu_handle_irq,
+        .enable                 = armv7pmu_enable_event,
+        .disable                = armv7pmu_disable_event,
+        .read_counter           = armv7pmu_read_counter,
+        .write_counter          = armv7pmu_write_counter,
+        .get_event_idx          = armv7pmu_get_event_idx,
+        .start                  = armv7pmu_start,
+        .stop                   = armv7pmu_stop,
+        .raw_event_mask         = 0xFF,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+static u32 __init armv7_reset_read_pmnc(void)
+{
+        u32 nb_cnt;
+
+        /* Initialize & Reset PMNC: C and P bits */
+        armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
+
+        /* Read the nb of CNTx counters supported from PMNC */
+        nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
+
+        /* Add the CPU cycles counter and return */
+        return nb_cnt + 1;
+}
+
+static const struct arm_pmu *__init armv7_a8_pmu_init(void)
+{
+        armv7pmu.id             = ARM_PERF_PMU_ID_CA8;
+        armv7pmu.name           = "ARMv7 Cortex-A8";
+        armv7pmu.cache_map      = &armv7_a8_perf_cache_map;
+        armv7pmu.event_map      = &armv7_a8_perf_map;
+        armv7pmu.num_events     = armv7_reset_read_pmnc();
+        return &armv7pmu;
+}
+
+static const struct arm_pmu *__init armv7_a9_pmu_init(void)
+{
+        armv7pmu.id             = ARM_PERF_PMU_ID_CA9;
+        armv7pmu.name           = "ARMv7 Cortex-A9";
+        armv7pmu.cache_map      = &armv7_a9_perf_cache_map;
+        armv7pmu.event_map      = &armv7_a9_perf_map;
+        armv7pmu.num_events     = armv7_reset_read_pmnc();
+        return &armv7pmu;
+}
+#else
+static const struct arm_pmu *__init armv7_a8_pmu_init(void)
+{
+        return NULL;
+}
+
+static const struct arm_pmu *__init armv7_a9_pmu_init(void)
+{
+        return NULL;
+}
+#endif  /* CONFIG_CPU_V7 */
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
new file mode 100644
index 000000000000..28cd3b025bc3
--- /dev/null
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -0,0 +1,807 @@
+/*
+ * ARMv5 [xscale] Performance counter handling code.
+ *
+ * Copyright (C) 2010, ARM Ltd., Will Deacon <will.deacon@arm.com>
+ *
+ * Based on the previous xscale OProfile code.
+ *
+ * There are two variants of the xscale PMU that we support:
+ *      - xscale1pmu: 2 event counters and a cycle counter
+ *      - xscale2pmu: 4 event counters and a cycle counter
+ * The two variants share event definitions, but have different
+ * PMU structures.
+ */
+
+#ifdef CONFIG_CPU_XSCALE
+enum xscale_perf_types {
+        XSCALE_PERFCTR_ICACHE_MISS              = 0x00,
+        XSCALE_PERFCTR_ICACHE_NO_DELIVER        = 0x01,
+        XSCALE_PERFCTR_DATA_STALL               = 0x02,
+        XSCALE_PERFCTR_ITLB_MISS                = 0x03,
+        XSCALE_PERFCTR_DTLB_MISS                = 0x04,
+        XSCALE_PERFCTR_BRANCH                   = 0x05,
+        XSCALE_PERFCTR_BRANCH_MISS              = 0x06,
+        XSCALE_PERFCTR_INSTRUCTION              = 0x07,
+        XSCALE_PERFCTR_DCACHE_FULL_STALL        = 0x08,
+        XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
+        XSCALE_PERFCTR_DCACHE_ACCESS            = 0x0A,
+        XSCALE_PERFCTR_DCACHE_MISS              = 0x0B,
+        XSCALE_PERFCTR_DCACHE_WRITE_BACK        = 0x0C,
+        XSCALE_PERFCTR_PC_CHANGED               = 0x0D,
+        XSCALE_PERFCTR_BCU_REQUEST              = 0x10,
+        XSCALE_PERFCTR_BCU_FULL                 = 0x11,
+        XSCALE_PERFCTR_BCU_DRAIN                = 0x12,
+        XSCALE_PERFCTR_BCU_ECC_NO_ELOG          = 0x14,
+        XSCALE_PERFCTR_BCU_1_BIT_ERR            = 0x15,
+        XSCALE_PERFCTR_RMW                      = 0x16,
+        /* XSCALE_PERFCTR_CCNT is not hardware defined */
+        XSCALE_PERFCTR_CCNT                     = 0xFE,
+        XSCALE_PERFCTR_UNUSED                   = 0xFF,
+};
+
+enum xscale_counters {
+        XSCALE_CYCLE_COUNTER    = 1,
+        XSCALE_COUNTER0,
+        XSCALE_COUNTER1,
+        XSCALE_COUNTER2,
+        XSCALE_COUNTER3,
+};
+
+static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = XSCALE_PERFCTR_CCNT,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = XSCALE_PERFCTR_INSTRUCTION,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = XSCALE_PERFCTR_BRANCH_MISS,
+        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                           [PERF_COUNT_HW_CACHE_OP_MAX]
+                                           [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = XSCALE_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = XSCALE_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+#define XSCALE_PMU_ENABLE       0x001
+#define XSCALE_PMN_RESET        0x002
+#define XSCALE_CCNT_RESET       0x004
+#define XSCALE_PMU_RESET        (CCNT_RESET | PMN_RESET)
+#define XSCALE_PMU_CNT64        0x008
+
+#define XSCALE1_OVERFLOWED_MASK 0x700
+#define XSCALE1_CCOUNT_OVERFLOW 0x400
+#define XSCALE1_COUNT0_OVERFLOW 0x100
+#define XSCALE1_COUNT1_OVERFLOW 0x200
+#define XSCALE1_CCOUNT_INT_EN   0x040
+#define XSCALE1_COUNT0_INT_EN   0x010
+#define XSCALE1_COUNT1_INT_EN   0x020
+#define XSCALE1_COUNT0_EVT_SHFT 12
+#define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
+#define XSCALE1_COUNT1_EVT_SHFT 20
+#define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
+
+static inline u32
+xscale1pmu_read_pmnc(void)
+{
+        u32 val;
+        asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
+        return val;
+}
+
+static inline void
+xscale1pmu_write_pmnc(u32 val)
+{
+        /* upper 4bits and 7, 11 are write-as-0 */
+        val &= 0xffff77f;
+        asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
+}
+
+static inline int
+xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
+                                        enum xscale_counters counter)
+{
+        int ret = 0;
+
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
+                break;
+        case XSCALE_COUNTER0:
+                ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
+                break;
+        case XSCALE_COUNTER1:
+                ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+        }
+
+        return ret;
+}
+
+static irqreturn_t
+xscale1pmu_handle_irq(int irq_num, void *dev)
+{
+        unsigned long pmnc;
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        /*
+         * NOTE: there's an A stepping erratum that states if an overflow
+         *       bit already exists and another occurs, the previous
+         *       Overflow bit gets cleared. There's no workaround.
+         *       Fixed in B stepping or later.
+         */
+        pmnc = xscale1pmu_read_pmnc();
+
+        /*
+         * Write the value back to clear the overflow flags. Overflow
+         * flags remain in pmnc for use below. We also disable the PMU
+         * while we process the interrupt.
+         */
+        xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
+
+        if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
+                return IRQ_NONE;
+
+        regs = get_irq_regs();
+
+        perf_sample_data_init(&data, 0);
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        irq_work_run();
+
+        /*
+         * Re-enable the PMU.
+         */
+        pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
+        xscale1pmu_write_pmnc(pmnc);
+
+        return IRQ_HANDLED;
+}
+
+static void
+xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        switch (idx) {
+        case XSCALE_CYCLE_COUNTER:
+                mask = 0;
+                evt = XSCALE1_CCOUNT_INT_EN;
+                break;
+        case XSCALE_COUNTER0:
+                mask = XSCALE1_COUNT0_EVT_MASK;
+                evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
+                        XSCALE1_COUNT0_INT_EN;
+                break;
+        case XSCALE_COUNTER1:
+                mask = XSCALE1_COUNT1_EVT_MASK;
+                evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
+                        XSCALE1_COUNT1_INT_EN;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale1pmu_read_pmnc();
+        val &= ~mask;
+        val |= evt;
+        xscale1pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        switch (idx) {
+        case XSCALE_CYCLE_COUNTER:
+                mask = XSCALE1_CCOUNT_INT_EN;
+                evt = 0;
+                break;
+        case XSCALE_COUNTER0:
+                mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
+                evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER1:
+                mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
+                evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale1pmu_read_pmnc();
+        val &= ~mask;
+        val |= evt;
+        xscale1pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static int
+xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                        struct hw_perf_event *event)
+{
+        if (XSCALE_PERFCTR_CCNT == event->config_base) {
+                if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
+                        return -EAGAIN;
+
+                return XSCALE_CYCLE_COUNTER;
+        } else {
+                if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask))
+                        return XSCALE_COUNTER1;
+
+                if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask))
+                        return XSCALE_COUNTER0;
+
+                return -EAGAIN;
+        }
+}
+
+static void
+xscale1pmu_start(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale1pmu_read_pmnc();
+        val |= XSCALE_PMU_ENABLE;
+        xscale1pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+xscale1pmu_stop(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale1pmu_read_pmnc();
+        val &= ~XSCALE_PMU_ENABLE;
+        xscale1pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static inline u32
+xscale1pmu_read_counter(int counter)
+{
+        u32 val = 0;
+
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER0:
+                asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER1:
+                asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
+                break;
+        }
+
+        return val;
+}
+
+static inline void
+xscale1pmu_write_counter(int counter, u32 val)
+{
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER0:
+                asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER1:
+                asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
+                break;
+        }
+}
+
+static const struct arm_pmu xscale1pmu = {
+        .id             = ARM_PERF_PMU_ID_XSCALE1,
+        .name           = "xscale1",
+        .handle_irq     = xscale1pmu_handle_irq,
+        .enable         = xscale1pmu_enable_event,
+        .disable        = xscale1pmu_disable_event,
+        .read_counter   = xscale1pmu_read_counter,
+        .write_counter  = xscale1pmu_write_counter,
+        .get_event_idx  = xscale1pmu_get_event_idx,
+        .start          = xscale1pmu_start,
+        .stop           = xscale1pmu_stop,
+        .cache_map      = &xscale_perf_cache_map,
+        .event_map      = &xscale_perf_map,
+        .raw_event_mask = 0xFF,
+        .num_events     = 3,
+        .max_period     = (1LLU << 32) - 1,
+};
+
+static const struct arm_pmu *__init xscale1pmu_init(void)
+{
+        return &xscale1pmu;
+}
+
+#define XSCALE2_OVERFLOWED_MASK 0x01f
+#define XSCALE2_CCOUNT_OVERFLOW 0x001
+#define XSCALE2_COUNT0_OVERFLOW 0x002
+#define XSCALE2_COUNT1_OVERFLOW 0x004
+#define XSCALE2_COUNT2_OVERFLOW 0x008
+#define XSCALE2_COUNT3_OVERFLOW 0x010
+#define XSCALE2_CCOUNT_INT_EN   0x001
+#define XSCALE2_COUNT0_INT_EN   0x002
+#define XSCALE2_COUNT1_INT_EN   0x004
+#define XSCALE2_COUNT2_INT_EN   0x008
+#define XSCALE2_COUNT3_INT_EN   0x010
+#define XSCALE2_COUNT0_EVT_SHFT 0
+#define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
+#define XSCALE2_COUNT1_EVT_SHFT 8
+#define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
+#define XSCALE2_COUNT2_EVT_SHFT 16
+#define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
+#define XSCALE2_COUNT3_EVT_SHFT 24
+#define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
+
+static inline u32
+xscale2pmu_read_pmnc(void)
+{
+        u32 val;
+        asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
+        /* bits 1-2 and 4-23 are read-unpredictable */
+        return val & 0xff000009;
+}
+
+static inline void
+xscale2pmu_write_pmnc(u32 val)
+{
+        /* bits 4-23 are write-as-0, 24-31 are write ignored */
+        val &= 0xf;
+        asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
+}
+
+static inline u32
+xscale2pmu_read_overflow_flags(void)
+{
+        u32 val;
+        asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
+        return val;
+}
+
+static inline void
+xscale2pmu_write_overflow_flags(u32 val)
+{
+        asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
+}
+
+static inline u32
+xscale2pmu_read_event_select(void)
+{
+        u32 val;
+        asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
+        return val;
+}
+
+static inline void
+xscale2pmu_write_event_select(u32 val)
+{
+        asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
+}
+
+static inline u32
+xscale2pmu_read_int_enable(void)
+{
+        u32 val;
+        asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
+        return val;
+}
+
+static void
+xscale2pmu_write_int_enable(u32 val)
+{
+        asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
+}
+
+static inline int
+xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
+                                        enum xscale_counters counter)
+{
+        int ret = 0;
+
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
+                break;
+        case XSCALE_COUNTER0:
+                ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
+                break;
+        case XSCALE_COUNTER1:
+                ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
+                break;
+        case XSCALE_COUNTER2:
+                ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
+                break;
+        case XSCALE_COUNTER3:
+                ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+        }
+
+        return ret;
+}
+
+static irqreturn_t
+xscale2pmu_handle_irq(int irq_num, void *dev)
+{
+        unsigned long pmnc, of_flags;
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        /* Disable the PMU. */
+        pmnc = xscale2pmu_read_pmnc();
+        xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
+
+        /* Check the overflow flag register. */
+        of_flags = xscale2pmu_read_overflow_flags();
+        if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
+                return IRQ_NONE;
+
+        /* Clear the overflow bits. */
+        xscale2pmu_write_overflow_flags(of_flags);
+
+        regs = get_irq_regs();
+
+        perf_sample_data_init(&data, 0);
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        irq_work_run();
+
+        /*
+         * Re-enable the PMU.
+         */
+        pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
+        xscale2pmu_write_pmnc(pmnc);
+
+        return IRQ_HANDLED;
+}
+
+static void
+xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags, ien, evtsel;
+
+        ien = xscale2pmu_read_int_enable();
+        evtsel = xscale2pmu_read_event_select();
+
+        switch (idx) {
+        case XSCALE_CYCLE_COUNTER:
+                ien |= XSCALE2_CCOUNT_INT_EN;
+                break;
+        case XSCALE_COUNTER0:
+                ien |= XSCALE2_COUNT0_INT_EN;
+                evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
+                evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER1:
+                ien |= XSCALE2_COUNT1_INT_EN;
+                evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
+                evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER2:
+                ien |= XSCALE2_COUNT2_INT_EN;
+                evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
+                evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER3:
+                ien |= XSCALE2_COUNT3_INT_EN;
+                evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
+                evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        xscale2pmu_write_event_select(evtsel);
+        xscale2pmu_write_int_enable(ien);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags, ien, evtsel;
+
+        ien = xscale2pmu_read_int_enable();
+        evtsel = xscale2pmu_read_event_select();
+
+        switch (idx) {
+        case XSCALE_CYCLE_COUNTER:
+                ien &= ~XSCALE2_CCOUNT_INT_EN;
+                break;
+        case XSCALE_COUNTER0:
+                ien &= ~XSCALE2_COUNT0_INT_EN;
+                evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
+                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER1:
+                ien &= ~XSCALE2_COUNT1_INT_EN;
+                evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
+                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER2:
+                ien &= ~XSCALE2_COUNT2_INT_EN;
+                evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
+                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER3:
+                ien &= ~XSCALE2_COUNT3_INT_EN;
+                evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
+                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        xscale2pmu_write_event_select(evtsel);
+        xscale2pmu_write_int_enable(ien);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static int
+xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                        struct hw_perf_event *event)
+{
+        int idx = xscale1pmu_get_event_idx(cpuc, event);
+        if (idx >= 0)
+                goto out;
+
+        if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
+                idx = XSCALE_COUNTER3;
+        else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
+                idx = XSCALE_COUNTER2;
+out:
+        return idx;
+}
+
+static void
+xscale2pmu_start(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
+        val |= XSCALE_PMU_ENABLE;
+        xscale2pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+xscale2pmu_stop(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale2pmu_read_pmnc();
+        val &= ~XSCALE_PMU_ENABLE;
+        xscale2pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static inline u32
+xscale2pmu_read_counter(int counter)
+{
+        u32 val = 0;
+
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER0:
+                asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER1:
+                asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER2:
+                asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER3:
+                asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
+                break;
+        }
+
+        return val;
+}
+
+static inline void
+xscale2pmu_write_counter(int counter, u32 val)
+{
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER0:
+                asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER1:
+                asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER2:
+                asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER3:
+                asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
+                break;
+        }
+}
+
+static const struct arm_pmu xscale2pmu = {
+        .id             = ARM_PERF_PMU_ID_XSCALE2,
+        .name           = "xscale2",
+        .handle_irq     = xscale2pmu_handle_irq,
+        .enable         = xscale2pmu_enable_event,
+        .disable        = xscale2pmu_disable_event,
+        .read_counter   = xscale2pmu_read_counter,
+        .write_counter  = xscale2pmu_write_counter,
+        .get_event_idx  = xscale2pmu_get_event_idx,
+        .start          = xscale2pmu_start,
+        .stop           = xscale2pmu_stop,
+        .cache_map      = &xscale_perf_cache_map,
+        .event_map      = &xscale_perf_map,
+        .raw_event_mask = 0xFF,
+        .num_events     = 5,
+        .max_period     = (1LLU << 32) - 1,
+};
+
+static const struct arm_pmu *__init xscale2pmu_init(void)
+{
+        return &xscale2pmu;
+}
+#else
+static const struct arm_pmu *__init xscale1pmu_init(void)
+{
+        return NULL;
+}
+
+static const struct arm_pmu *__init xscale2pmu_init(void)
+{
+        return NULL;
+}
+#endif  /* CONFIG_CPU_XSCALE */
diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c
new file mode 100644
index 000000000000..a4b1b0748fd3
--- /dev/null
+++ b/arch/arm/kernel/pj4-cp0.c
@@ -0,0 +1,94 @@
+/*
+ * linux/arch/arm/kernel/pj4-cp0.c
+ *
+ * PJ4 iWMMXt coprocessor context switching and handling
+ *
+ * Copyright (c) 2010 Marvell International Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/thread_notify.h>
+
+static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
+{
+        struct thread_info *thread = t;
+
+        switch (cmd) {
+        case THREAD_NOTIFY_FLUSH:
+                /*
+                 * flush_thread() zeroes thread->fpstate, so no need
+                 * to do anything here.
+                 *
+                 * FALLTHROUGH: Ensure we don't try to overwrite our newly
+                 * initialised state information on the first fault.
+                 */
+
+        case THREAD_NOTIFY_EXIT:
+                iwmmxt_task_release(thread);
+                break;
+
+        case THREAD_NOTIFY_SWITCH:
+                iwmmxt_task_switch(thread);
+                break;
+        }
+
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block iwmmxt_notifier_block = {
+        .notifier_call  = iwmmxt_do,
+};
+
+
+static u32 __init pj4_cp_access_read(void)
+{
+        u32 value;
+
+        __asm__ __volatile__ (
+                "mrc    p15, 0, %0, c1, c0, 2\n\t"
+                : "=r" (value));
+        return value;
+}
+
+static void __init pj4_cp_access_write(u32 value)
+{
+        u32 temp;
+
+        __asm__ __volatile__ (
+                "mcr    p15, 0, %1, c1, c0, 2\n\t"
+                "mrc    p15, 0, %0, c1, c0, 2\n\t"
+                "mov    %0, %0\n\t"
+                "sub    pc, pc, #4\n\t"
+                : "=r" (temp) : "r" (value));
+}
+
+
+/*
+ * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
+ * switch code handle iWMMXt context switching.
+ */
+static int __init pj4_cp0_init(void)
+{
+        u32 cp_access;
+
+        cp_access = pj4_cp_access_read() & ~0xf;
+        pj4_cp_access_write(cp_access);
+
+        printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
+        elf_hwcap |= HWCAP_IWMMXT;
+        thread_register_notifier(&iwmmxt_notifier_block);
+
+        return 0;
+}
+
+late_initcall(pj4_cp0_init);
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3e97483abcf0..19c6816db61e 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -1060,8 +1060,8 @@ static int ptrace_sethbpregs(struct task_struct *tsk, long num,
                         goto out;
 
                 if ((gen_type & implied_type) != gen_type) {
-                                ret = -EINVAL;
-                                goto out;
+                        ret = -EINVAL;
+                        goto out;
                 }
 
                 attr.bp_len     = gen_len;
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
new file mode 100644
index 000000000000..2cdcc9287c74
--- /dev/null
+++ b/arch/arm/kernel/sched_clock.c
@@ -0,0 +1,69 @@
+/*
+ * sched_clock.c: support for extending counters to full 64-bit ns counter
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clocksource.h>
+#include <linux/init.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+
+#include <asm/sched_clock.h>
+
+static void sched_clock_poll(unsigned long wrap_ticks);
+static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0);
+static void (*sched_clock_update_fn)(void);
+
+static void sched_clock_poll(unsigned long wrap_ticks)
+{
+        mod_timer(&sched_clock_timer, round_jiffies(jiffies + wrap_ticks));
+        sched_clock_update_fn();
+}
+
+void __init init_sched_clock(struct clock_data *cd, void (*update)(void),
+        unsigned int clock_bits, unsigned long rate)
+{
+        unsigned long r, w;
+        u64 res, wrap;
+        char r_unit;
+
+        sched_clock_update_fn = update;
+
+        /* calculate the mult/shift to convert counter ticks to ns. */
+        clocks_calc_mult_shift(&cd->mult, &cd->shift, rate, NSEC_PER_SEC, 60);
+
+        r = rate;
+        if (r >= 4000000) {
+                r /= 1000000;
+                r_unit = 'M';
+        } else {
+                r /= 1000;
+                r_unit = 'k';
+        }
+
+        /* calculate how many ns until we wrap */
+        wrap = cyc_to_ns((1ULL << clock_bits) - 1, cd->mult, cd->shift);
+        do_div(wrap, NSEC_PER_MSEC);
+        w = wrap;
+
+        /* calculate the ns resolution of this counter */
+        res = cyc_to_ns(1ULL, cd->mult, cd->shift);
+        pr_info("sched_clock: %u bits at %lu%cHz, resolution %lluns, wraps every %lums\n",
+                clock_bits, r, r_unit, res, w);
+
+        /*
+         * Start the timer to keep sched_clock() properly updated and
+         * sets the initial epoch.
+         */
+        sched_clock_timer.data = msecs_to_jiffies(w - (w / 10));
+        sched_clock_poll(sched_clock_timer.data);
+
+        /*
+         * Ensure that sched_clock() starts off at 0ns
+         */
+        cd->epoch_ns = 0;
+}
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 336f14e0e5c2..3455ad33de4c 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -75,9 +75,9 @@ extern void reboot_setup(char *str);
 
 unsigned int processor_id;
 EXPORT_SYMBOL(processor_id);
-unsigned int __machine_arch_type;
+unsigned int __machine_arch_type __read_mostly;
 EXPORT_SYMBOL(__machine_arch_type);
-unsigned int cacheid;
+unsigned int cacheid __read_mostly;
 EXPORT_SYMBOL(cacheid);
 
 unsigned int __atags_pointer __initdata;
@@ -91,24 +91,24 @@ EXPORT_SYMBOL(system_serial_low);
 unsigned int system_serial_high;
 EXPORT_SYMBOL(system_serial_high);
 
-unsigned int elf_hwcap;
+unsigned int elf_hwcap __read_mostly;
 EXPORT_SYMBOL(elf_hwcap);
 
 
 #ifdef MULTI_CPU
-struct processor processor;
+struct processor processor __read_mostly;
 #endif
 #ifdef MULTI_TLB
-struct cpu_tlb_fns cpu_tlb;
+struct cpu_tlb_fns cpu_tlb __read_mostly;
 #endif
 #ifdef MULTI_USER
-struct cpu_user_fns cpu_user;
+struct cpu_user_fns cpu_user __read_mostly;
 #endif
 #ifdef MULTI_CACHE
-struct cpu_cache_fns cpu_cache;
+struct cpu_cache_fns cpu_cache __read_mostly;
 #endif
 #ifdef CONFIG_OUTER_CACHE
-struct outer_cache_fns outer_cache;
+struct outer_cache_fns outer_cache __read_mostly;
 EXPORT_SYMBOL(outer_cache);
 #endif
 
@@ -126,6 +126,7 @@ EXPORT_SYMBOL(elf_platform);
 static const char *cpu_name;
 static const char *machine_name;
 static char __initdata cmd_line[COMMAND_LINE_SIZE];
+struct machine_desc *machine_desc __initdata;
 
 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
@@ -708,13 +709,11 @@ static struct init_tags {
         { 0, ATAG_NONE }
 };
 
-static void (*init_machine)(void) __initdata;
-
 static int __init customize_machine(void)
 {
         /* customizes platform devices, or adds new ones */
-        if (init_machine)
-                init_machine();
+        if (machine_desc->init_machine)
+                machine_desc->init_machine();
         return 0;
 }
 arch_initcall(customize_machine);
@@ -809,6 +808,7 @@ void __init setup_arch(char **cmdline_p)
 
         setup_processor();
         mdesc = setup_machine(machine_arch_type);
+        machine_desc = mdesc;
         machine_name = mdesc->name;
 
         if (mdesc->soft_reboot)
@@ -868,13 +868,9 @@ void __init setup_arch(char **cmdline_p)
         cpu_init();
         tcm_init();
 
-        /*
-         * Set up various architecture-specific pointers
-         */
-        arch_nr_irqs = mdesc->nr_irqs;
-        init_arch_irq = mdesc->init_irq;
-        system_timer = mdesc->timer;
-        init_machine = mdesc->init_machine;
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+        handle_arch_irq = mdesc->handle_irq;
+#endif
 
 #ifdef CONFIG_VT
 #if defined(CONFIG_VGA_CONSOLE)
@@ -884,6 +880,9 @@ void __init setup_arch(char **cmdline_p)
 #endif
 #endif
         early_trap_init();
+
+        if (mdesc->init_early)
+                mdesc->init_early();
 }
 
 
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 9066473c0ebc..4539ebcb089f 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -16,6 +16,7 @@
 #include <linux/cache.h>
 #include <linux/profile.h>
 #include <linux/errno.h>
+#include <linux/ftrace.h>
 #include <linux/mm.h>
 #include <linux/err.h>
 #include <linux/cpu.h>
@@ -24,6 +25,7 @@
 #include <linux/irq.h>
 #include <linux/percpu.h>
 #include <linux/clockchips.h>
+#include <linux/completion.h>
 
 #include <asm/atomic.h>
 #include <asm/cacheflush.h>
@@ -37,7 +39,6 @@
 #include <asm/tlbflush.h>
 #include <asm/ptrace.h>
 #include <asm/localtimer.h>
-#include <asm/smp_plat.h>
 
 /*
  * as from 2.5, kernels no longer have an init_tasks structure
@@ -46,64 +47,14 @@
  */
 struct secondary_data secondary_data;
 
-/*
- * structures for inter-processor calls
- * - A collection of single bit ipi messages.
- */
-struct ipi_data {
-        spinlock_t lock;
-        unsigned long ipi_count;
-        unsigned long bits;
-};
-
-static DEFINE_PER_CPU(struct ipi_data, ipi_data) = {
-        .lock   = SPIN_LOCK_UNLOCKED,
-};
-
 enum ipi_msg_type {
-        IPI_TIMER,
+        IPI_TIMER = 2,
         IPI_RESCHEDULE,
         IPI_CALL_FUNC,
         IPI_CALL_FUNC_SINGLE,
         IPI_CPU_STOP,
 };
 
-static inline void identity_mapping_add(pgd_t *pgd, unsigned long start,
-        unsigned long end)
-{
-        unsigned long addr, prot;
-        pmd_t *pmd;
-
-        prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE;
-        if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
-                prot |= PMD_BIT4;
-
-        for (addr = start & PGDIR_MASK; addr < end;) {
-                pmd = pmd_offset(pgd + pgd_index(addr), addr);
-                pmd[0] = __pmd(addr | prot);
-                addr += SECTION_SIZE;
-                pmd[1] = __pmd(addr | prot);
-                addr += SECTION_SIZE;
-                flush_pmd_entry(pmd);
-                outer_clean_range(__pa(pmd), __pa(pmd + 1));
-        }
-}
-
-static inline void identity_mapping_del(pgd_t *pgd, unsigned long start,
-        unsigned long end)
-{
-        unsigned long addr;
-        pmd_t *pmd;
-
-        for (addr = start & PGDIR_MASK; addr < end; addr += PGDIR_SIZE) {
-                pmd = pmd_offset(pgd + pgd_index(addr), addr);
-                pmd[0] = __pmd(0);
-                pmd[1] = __pmd(0);
-                clean_pmd_entry(pmd);
-                outer_clean_range(__pa(pmd), __pa(pmd + 1));
-        }
-}
-
 int __cpuinit __cpu_up(unsigned int cpu)
 {
         struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu);
@@ -177,8 +128,12 @@ int __cpuinit __cpu_up(unsigned int cpu)
                         barrier();
                 }
 
-                if (!cpu_online(cpu))
+                if (!cpu_online(cpu)) {
+                        pr_crit("CPU%u: failed to come online\n", cpu);
                         ret = -EIO;
+                }
+        } else {
+                pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
         }
 
         secondary_data.stack = NULL;
@@ -194,18 +149,12 @@ int __cpuinit __cpu_up(unsigned int cpu)
 
         pgd_free(&init_mm, pgd);
 
-        if (ret) {
-                printk(KERN_CRIT "CPU%u: processor failed to boot\n", cpu);
-
-                /*
-                 * FIXME: We need to clean up the new idle thread. --rmk
-                 */
-        }
-
         return ret;
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
+static void percpu_timer_stop(void);
+
 /*
  * __cpu_disable runs on the processor to be shutdown.
  */
@@ -233,7 +182,7 @@ int __cpu_disable(void)
         /*
          * Stop the local timer for this CPU.
          */
-        local_timer_stop();
+        percpu_timer_stop();
 
         /*
          * Flush user cache and TLB mappings, and then remove this CPU
@@ -252,12 +201,20 @@ int __cpu_disable(void)
         return 0;
 }
 
+static DECLARE_COMPLETION(cpu_died);
+
 /*
  * called on the thread which is asking for a CPU to be shutdown -
  * waits until shutdown has completed, or it is timed out.
  */
 void __cpu_die(unsigned int cpu)
 {
+        if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
+                pr_err("CPU%u: cpu didn't die\n", cpu);
+                return;
+        }
+        printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
+
         if (!platform_cpu_kill(cpu))
                 printk("CPU%u: unable to kill\n", cpu);
 }
@@ -274,12 +231,17 @@ void __ref cpu_die(void)
 {
         unsigned int cpu = smp_processor_id();
 
-        local_irq_disable();
         idle_task_exit();
 
+        local_irq_disable();
+        mb();
+
+        /* Tell __cpu_die() that this CPU is now safe to dispose of */
+        complete(&cpu_died);
+
         /*
          * actual CPU shutdown procedure is at least platform (if not
-         * CPU) specific
+         * CPU) specific.
          */
         platform_cpu_die(cpu);
 
@@ -289,6 +251,7 @@ void __ref cpu_die(void)
          * to be repeated to undo the effects of taking the CPU offline.
          */
         __asm__("mov    sp, %0\n"
+        "       mov     fp, #0\n"
         "       b       secondary_start_kernel"
                 :
                 : "r" (task_stack_page(current) + THREAD_SIZE - 8));
@@ -296,6 +259,17 @@ void __ref cpu_die(void)
 #endif /* CONFIG_HOTPLUG_CPU */
 
 /*
+ * Called by both boot and secondaries to move global data into
+ * per-processor storage.
+ */
+static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
+{
+        struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
+
+        cpu_info->loops_per_jiffy = loops_per_jiffy;
+}
+
+/*
  * This is the secondary CPU boot entry.  We're using this CPUs
  * idle thread stack, but a set of temporary page tables.
  */
@@ -319,6 +293,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
 
         cpu_init();
         preempt_disable();
+        trace_hardirqs_off();
 
         /*
          * Give the platform a chance to do its own initialisation.
@@ -352,17 +327,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
         cpu_idle();
 }
 
-/*
- * Called by both boot and secondaries to move global data into
- * per-processor storage.
- */
-void __cpuinit smp_store_cpu_info(unsigned int cpuid)
-{
-        struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid);
-
-        cpu_info->loops_per_jiffy = loops_per_jiffy;
-}
-
 void __init smp_cpus_done(unsigned int max_cpus)
 {
         int cpu;
@@ -385,61 +349,80 @@ void __init smp_prepare_boot_cpu(void)
         per_cpu(cpu_data, cpu).idle = current;
 }
 
-static void send_ipi_message(const struct cpumask *mask, enum ipi_msg_type msg)
+void __init smp_prepare_cpus(unsigned int max_cpus)
 {
-        unsigned long flags;
-        unsigned int cpu;
+        unsigned int ncores = num_possible_cpus();
 
-        local_irq_save(flags);
-
-        for_each_cpu(cpu, mask) {
-                struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
-
-                spin_lock(&ipi->lock);
-                ipi->bits |= 1 << msg;
-                spin_unlock(&ipi->lock);
-        }
+        smp_store_cpu_info(smp_processor_id());
 
         /*
-         * Call the platform specific cross-CPU call function.
+         * are we trying to boot more cores than exist?
          */
-        smp_cross_call(mask);
+        if (max_cpus > ncores)
+                max_cpus = ncores;
+
+        if (max_cpus > 1) {
+                /*
+                 * Enable the local timer or broadcast device for the
+                 * boot CPU, but only if we have more than one CPU.
+                 */
+                percpu_timer_setup();
 
-        local_irq_restore(flags);
+                /*
+                 * Initialise the SCU if there are more than one CPU
+                 * and let them know where to start.
+                 */
+                platform_smp_prepare_cpus(max_cpus);
+        }
 }
 
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 {
-        send_ipi_message(mask, IPI_CALL_FUNC);
+        smp_cross_call(mask, IPI_CALL_FUNC);
 }
 
 void arch_send_call_function_single_ipi(int cpu)
 {
-        send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
+        smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
 }
 
-void show_ipi_list(struct seq_file *p)
+static const char *ipi_types[NR_IPI] = {
+#define S(x,s)  [x - IPI_TIMER] = s
+        S(IPI_TIMER, "Timer broadcast interrupts"),
+        S(IPI_RESCHEDULE, "Rescheduling interrupts"),
+        S(IPI_CALL_FUNC, "Function call interrupts"),
+        S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
+        S(IPI_CPU_STOP, "CPU stop interrupts"),
+};
+
+void show_ipi_list(struct seq_file *p, int prec)
 {
-        unsigned int cpu;
+        unsigned int cpu, i;
 
-        seq_puts(p, "IPI:");
+        for (i = 0; i < NR_IPI; i++) {
+                seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
 
-        for_each_present_cpu(cpu)
-                seq_printf(p, " %10lu", per_cpu(ipi_data, cpu).ipi_count);
+                for_each_present_cpu(cpu)
+                        seq_printf(p, "%10u ",
+                                   __get_irq_stat(cpu, ipi_irqs[i]));
 
-        seq_putc(p, '\n');
+                seq_printf(p, " %s\n", ipi_types[i]);
+        }
 }
 
-void show_local_irqs(struct seq_file *p)
+u64 smp_irq_stat_cpu(unsigned int cpu)
 {
-        unsigned int cpu;
+        u64 sum = 0;
+        int i;
 
-        seq_printf(p, "LOC: ");
+        for (i = 0; i < NR_IPI; i++)
+                sum += __get_irq_stat(cpu, ipi_irqs[i]);
 
-        for_each_present_cpu(cpu)
-                seq_printf(p, "%10u ", irq_stat[cpu].local_timer_irqs);
+#ifdef CONFIG_LOCAL_TIMERS
+        sum += __get_irq_stat(cpu, local_timer_irqs);
+#endif
 
-        seq_putc(p, '\n');
+        return sum;
 }
 
 /*
@@ -456,24 +439,36 @@ static void ipi_timer(void)
 }
 
 #ifdef CONFIG_LOCAL_TIMERS
-asmlinkage void __exception do_local_timer(struct pt_regs *regs)
+asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)
 {
         struct pt_regs *old_regs = set_irq_regs(regs);
         int cpu = smp_processor_id();
 
         if (local_timer_ack()) {
-                irq_stat[cpu].local_timer_irqs++;
+                __inc_irq_stat(cpu, local_timer_irqs);
                 ipi_timer();
         }
 
         set_irq_regs(old_regs);
 }
+
+void show_local_irqs(struct seq_file *p, int prec)
+{
+        unsigned int cpu;
+
+        seq_printf(p, "%*s: ", prec, "LOC");
+
+        for_each_present_cpu(cpu)
+                seq_printf(p, "%10u ", __get_irq_stat(cpu, local_timer_irqs));
+
+        seq_printf(p, " Local timer interrupts\n");
+}
 #endif
 
 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 static void smp_timer_broadcast(const struct cpumask *mask)
 {
-        send_ipi_message(mask, IPI_TIMER);
+        smp_cross_call(mask, IPI_TIMER);
 }
 #else
 #define smp_timer_broadcast     NULL
@@ -510,6 +505,21 @@ void __cpuinit percpu_timer_setup(void)
         local_timer_setup(evt);
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+/*
+ * The generic clock events code purposely does not stop the local timer
+ * on CPU_DEAD/CPU_DEAD_FROZEN hotplug events, so we have to do it
+ * manually here.
+ */
+static void percpu_timer_stop(void)
+{
+        unsigned int cpu = smp_processor_id();
+        struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
+
+        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
+}
+#endif
+
 static DEFINE_SPINLOCK(stop_lock);
 
 /*
@@ -536,216 +546,76 @@ static void ipi_cpu_stop(unsigned int cpu)
 
 /*
  * Main handler for inter-processor interrupts
- *
- * For ARM, the ipimask now only identifies a single
- * category of IPI (Bit 1 IPIs have been replaced by a
- * different mechanism):
- *
- *  Bit 0 - Inter-processor function call
  */
-asmlinkage void __exception do_IPI(struct pt_regs *regs)
+asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs)
 {
         unsigned int cpu = smp_processor_id();
-        struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
         struct pt_regs *old_regs = set_irq_regs(regs);
 
-        ipi->ipi_count++;
-
-        for (;;) {
-                unsigned long msgs;
-
-                spin_lock(&ipi->lock);
-                msgs = ipi->bits;
-                ipi->bits = 0;
-                spin_unlock(&ipi->lock);
+        if (ipinr >= IPI_TIMER && ipinr < IPI_TIMER + NR_IPI)
+                __inc_irq_stat(cpu, ipi_irqs[ipinr - IPI_TIMER]);
 
-                if (!msgs)
-                        break;
-
-                do {
-                        unsigned nextmsg;
-
-                        nextmsg = msgs & -msgs;
-                        msgs &= ~nextmsg;
-                        nextmsg = ffz(~nextmsg);
-
-                        switch (nextmsg) {
-                        case IPI_TIMER:
-                                ipi_timer();
-                                break;
+        switch (ipinr) {
+        case IPI_TIMER:
+                ipi_timer();
+                break;
 
-                        case IPI_RESCHEDULE:
-                                /*
-                                 * nothing more to do - eveything is
-                                 * done on the interrupt return path
-                                 */
-                                break;
+        case IPI_RESCHEDULE:
+                /*
+                 * nothing more to do - eveything is
+                 * done on the interrupt return path
+                 */
+                break;
 
-                        case IPI_CALL_FUNC:
-                                generic_smp_call_function_interrupt();
-                                break;
+        case IPI_CALL_FUNC:
+                generic_smp_call_function_interrupt();
+                break;
 
-                        case IPI_CALL_FUNC_SINGLE:
-                                generic_smp_call_function_single_interrupt();
-                                break;
+        case IPI_CALL_FUNC_SINGLE:
+                generic_smp_call_function_single_interrupt();
+                break;
 
-                        case IPI_CPU_STOP:
-                                ipi_cpu_stop(cpu);
-                                break;
+        case IPI_CPU_STOP:
+                ipi_cpu_stop(cpu);
+                break;
 
-                        default:
-                                printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n",
-                                       cpu, nextmsg);
-                                break;
-                        }
-                } while (msgs);
+        default:
+                printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n",
+                       cpu, ipinr);
+                break;
         }
-
         set_irq_regs(old_regs);
 }
 
 void smp_send_reschedule(int cpu)
 {
-        send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+        smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
 void smp_send_stop(void)
 {
-        cpumask_t mask = cpu_online_map;
-        cpu_clear(smp_processor_id(), mask);
-        if (!cpus_empty(mask))
-                send_ipi_message(&mask, IPI_CPU_STOP);
-}
+        unsigned long timeout;
 
-/*
- * not supported here
- */
-int setup_profiling_timer(unsigned int multiplier)
-{
-        return -EINVAL;
-}
+        if (num_online_cpus() > 1) {
+                cpumask_t mask = cpu_online_map;
+                cpu_clear(smp_processor_id(), mask);
 
-static void
-on_each_cpu_mask(void (*func)(void *), void *info, int wait,
-                const struct cpumask *mask)
-{
-        preempt_disable();
+                smp_cross_call(&mask, IPI_CPU_STOP);
+        }
 
-        smp_call_function_many(mask, func, info, wait);
-        if (cpumask_test_cpu(smp_processor_id(), mask))
-                func(info);
+        /* Wait up to one second for other CPUs to stop */
+        timeout = USEC_PER_SEC;
+        while (num_online_cpus() > 1 && timeout--)
+                udelay(1);
 
-        preempt_enable();
+        if (num_online_cpus() > 1)
+                pr_warning("SMP: failed to stop secondary CPUs\n");
 }
 
-/**********************************************************************/
-
 /*
- * TLB operations
+ * not supported here
  */
-struct tlb_args {
-        struct vm_area_struct *ta_vma;
-        unsigned long ta_start;
-        unsigned long ta_end;
-};
-
-static inline void ipi_flush_tlb_all(void *ignored)
-{
-        local_flush_tlb_all();
-}
-
-static inline void ipi_flush_tlb_mm(void *arg)
-{
-        struct mm_struct *mm = (struct mm_struct *)arg;
-
-        local_flush_tlb_mm(mm);
-}
-
-static inline void ipi_flush_tlb_page(void *arg)
-{
-        struct tlb_args *ta = (struct tlb_args *)arg;
-
-        local_flush_tlb_page(ta->ta_vma, ta->ta_start);
-}
-
-static inline void ipi_flush_tlb_kernel_page(void *arg)
-{
-        struct tlb_args *ta = (struct tlb_args *)arg;
-
-        local_flush_tlb_kernel_page(ta->ta_start);
-}
-
-static inline void ipi_flush_tlb_range(void *arg)
-{
-        struct tlb_args *ta = (struct tlb_args *)arg;
-
-        local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
-}
-
-static inline void ipi_flush_tlb_kernel_range(void *arg)
-{
-        struct tlb_args *ta = (struct tlb_args *)arg;
-
-        local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
-}
-
-void flush_tlb_all(void)
-{
-        if (tlb_ops_need_broadcast())
-                on_each_cpu(ipi_flush_tlb_all, NULL, 1);
-        else
-                local_flush_tlb_all();
-}
-
-void flush_tlb_mm(struct mm_struct *mm)
-{
-        if (tlb_ops_need_broadcast())
-                on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, mm_cpumask(mm));
-        else
-                local_flush_tlb_mm(mm);
-}
-
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
-{
-        if (tlb_ops_need_broadcast()) {
-                struct tlb_args ta;
-                ta.ta_vma = vma;
-                ta.ta_start = uaddr;
-                on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, mm_cpumask(vma->vm_mm));
-        } else
-                local_flush_tlb_page(vma, uaddr);
-}
-
-void flush_tlb_kernel_page(unsigned long kaddr)
-{
-        if (tlb_ops_need_broadcast()) {
-                struct tlb_args ta;
-                ta.ta_start = kaddr;
-                on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
-        } else
-                local_flush_tlb_kernel_page(kaddr);
-}
-
-void flush_tlb_range(struct vm_area_struct *vma,
-                     unsigned long start, unsigned long end)
-{
-        if (tlb_ops_need_broadcast()) {
-                struct tlb_args ta;
-                ta.ta_vma = vma;
-                ta.ta_start = start;
-                ta.ta_end = end;
-                on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, mm_cpumask(vma->vm_mm));
-        } else
-                local_flush_tlb_range(vma, start, end);
-}
-
-void flush_tlb_kernel_range(unsigned long start, unsigned long end)
+int setup_profiling_timer(unsigned int multiplier)
 {
-        if (tlb_ops_need_broadcast()) {
-                struct tlb_args ta;
-                ta.ta_start = start;
-                ta.ta_end = end;
-                on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
-        } else
-                local_flush_tlb_kernel_range(start, end);
+        return -EINVAL;
 }
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
new file mode 100644
index 000000000000..7dcb35285be7
--- /dev/null
+++ b/arch/arm/kernel/smp_tlb.c
@@ -0,0 +1,139 @@
+/*
+ *  linux/arch/arm/kernel/smp_tlb.c
+ *
+ *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/preempt.h>
+#include <linux/smp.h>
+
+#include <asm/smp_plat.h>
+#include <asm/tlbflush.h>
+
+static void on_each_cpu_mask(void (*func)(void *), void *info, int wait,
+        const struct cpumask *mask)
+{
+        preempt_disable();
+
+        smp_call_function_many(mask, func, info, wait);
+        if (cpumask_test_cpu(smp_processor_id(), mask))
+                func(info);
+
+        preempt_enable();
+}
+
+/**********************************************************************/
+
+/*
+ * TLB operations
+ */
+struct tlb_args {
+        struct vm_area_struct *ta_vma;
+        unsigned long ta_start;
+        unsigned long ta_end;
+};
+
+static inline void ipi_flush_tlb_all(void *ignored)
+{
+        local_flush_tlb_all();
+}
+
+static inline void ipi_flush_tlb_mm(void *arg)
+{
+        struct mm_struct *mm = (struct mm_struct *)arg;
+
+        local_flush_tlb_mm(mm);
+}
+
+static inline void ipi_flush_tlb_page(void *arg)
+{
+        struct tlb_args *ta = (struct tlb_args *)arg;
+
+        local_flush_tlb_page(ta->ta_vma, ta->ta_start);
+}
+
+static inline void ipi_flush_tlb_kernel_page(void *arg)
+{
+        struct tlb_args *ta = (struct tlb_args *)arg;
+
+        local_flush_tlb_kernel_page(ta->ta_start);
+}
+
+static inline void ipi_flush_tlb_range(void *arg)
+{
+        struct tlb_args *ta = (struct tlb_args *)arg;
+
+        local_flush_tlb_range(ta->ta_vma, ta->ta_start, ta->ta_end);
+}
+
+static inline void ipi_flush_tlb_kernel_range(void *arg)
+{
+        struct tlb_args *ta = (struct tlb_args *)arg;
+
+        local_flush_tlb_kernel_range(ta->ta_start, ta->ta_end);
+}
+
+void flush_tlb_all(void)
+{
+        if (tlb_ops_need_broadcast())
+                on_each_cpu(ipi_flush_tlb_all, NULL, 1);
+        else
+                local_flush_tlb_all();
+}
+
+void flush_tlb_mm(struct mm_struct *mm)
+{
+        if (tlb_ops_need_broadcast())
+                on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, mm_cpumask(mm));
+        else
+                local_flush_tlb_mm(mm);
+}
+
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
+{
+        if (tlb_ops_need_broadcast()) {
+                struct tlb_args ta;
+                ta.ta_vma = vma;
+                ta.ta_start = uaddr;
+                on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, mm_cpumask(vma->vm_mm));
+        } else
+                local_flush_tlb_page(vma, uaddr);
+}
+
+void flush_tlb_kernel_page(unsigned long kaddr)
+{
+        if (tlb_ops_need_broadcast()) {
+                struct tlb_args ta;
+                ta.ta_start = kaddr;
+                on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1);
+        } else
+                local_flush_tlb_kernel_page(kaddr);
+}
+
+void flush_tlb_range(struct vm_area_struct *vma,
+                     unsigned long start, unsigned long end)
+{
+        if (tlb_ops_need_broadcast()) {
+                struct tlb_args ta;
+                ta.ta_vma = vma;
+                ta.ta_start = start;
+                ta.ta_end = end;
+                on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, mm_cpumask(vma->vm_mm));
+        } else
+                local_flush_tlb_range(vma, start, end);
+}
+
+void flush_tlb_kernel_range(unsigned long start, unsigned long end)
+{
+        if (tlb_ops_need_broadcast()) {
+                struct tlb_args ta;
+                ta.ta_start = start;
+                ta.ta_end = end;
+                on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1);
+        } else
+                local_flush_tlb_kernel_range(start, end);
+}
+
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 35882fbf37f9..dd790745b3ef 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -127,8 +127,6 @@ static void __cpuinit twd_calibrate_rate(void)
  */
 void __cpuinit twd_timer_setup(struct clock_event_device *clk)
 {
-        unsigned long flags;
-
         twd_calibrate_rate();
 
         clk->name = "local_timer";
@@ -143,20 +141,7 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
         clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
 
         /* Make sure our local interrupt controller has this enabled */
-        local_irq_save(flags);
-        irq_to_desc(clk->irq)->status |= IRQ_NOPROBE;
-        get_irq_chip(clk->irq)->unmask(clk->irq);
-        local_irq_restore(flags);
+        gic_enable_ppi(clk->irq);
 
         clockevents_register_device(clk);
 }
-
-#ifdef CONFIG_HOTPLUG_CPU
-/*
- * take a local timer down
- */
-void twd_timer_stop(void)
-{
-        __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
-}
-#endif
diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c
new file mode 100644
index 000000000000..7a5760922914
--- /dev/null
+++ b/arch/arm/kernel/swp_emulate.c
@@ -0,0 +1,267 @@
+/*
+ *  linux/arch/arm/kernel/swp_emulate.c
+ *
+ *  Copyright (C) 2009 ARM Limited
+ *  __user_* functions adapted from include/asm/uaccess.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Implements emulation of the SWP/SWPB instructions using load-exclusive and
+ *  store-exclusive for processors that have them disabled (or future ones that
+ *  might not implement them).
+ *
+ *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
+ *  Where: Rt  = destination
+ *         Rt2 = source
+ *         Rn  = address
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/proc_fs.h>
+#include <linux/sched.h>
+#include <linux/syscalls.h>
+#include <linux/perf_event.h>
+
+#include <asm/traps.h>
+#include <asm/uaccess.h>
+
+/*
+ * Error-checking SWP macros implemented using ldrex{b}/strex{b}
+ */
+#define __user_swpX_asm(data, addr, res, temp, B)               \
+        __asm__ __volatile__(                                   \
+        "       mov             %2, %1\n"                       \
+        "0:     ldrex"B"        %1, [%3]\n"                     \
+        "1:     strex"B"        %0, %2, [%3]\n"                 \
+        "       cmp             %0, #0\n"                       \
+        "       movne           %0, %4\n"                       \
+        "2:\n"                                                  \
+        "       .section         .fixup,\"ax\"\n"               \
+        "       .align          2\n"                            \
+        "3:     mov             %0, %5\n"                       \
+        "       b               2b\n"                           \
+        "       .previous\n"                                    \
+        "       .section         __ex_table,\"a\"\n"            \
+        "       .align          3\n"                            \
+        "       .long           0b, 3b\n"                       \
+        "       .long           1b, 3b\n"                       \
+        "       .previous"                                      \
+        : "=&r" (res), "+r" (data), "=&r" (temp)                \
+        : "r" (addr), "i" (-EAGAIN), "i" (-EFAULT)              \
+        : "cc", "memory")
+
+#define __user_swp_asm(data, addr, res, temp) \
+        __user_swpX_asm(data, addr, res, temp, "")
+#define __user_swpb_asm(data, addr, res, temp) \
+        __user_swpX_asm(data, addr, res, temp, "b")
+
+/*
+ * Macros/defines for extracting register numbers from instruction.
+ */
+#define EXTRACT_REG_NUM(instruction, offset) \
+        (((instruction) & (0xf << (offset))) >> (offset))
+#define RN_OFFSET  16
+#define RT_OFFSET  12
+#define RT2_OFFSET  0
+/*
+ * Bit 22 of the instruction encoding distinguishes between
+ * the SWP and SWPB variants (bit set means SWPB).
+ */
+#define TYPE_SWPB (1 << 22)
+
+static unsigned long swpcounter;
+static unsigned long swpbcounter;
+static unsigned long abtcounter;
+static pid_t         previous_pid;
+
+#ifdef CONFIG_PROC_FS
+static int proc_read_status(char *page, char **start, off_t off, int count,
+                            int *eof, void *data)
+{
+        char *p = page;
+        int len;
+
+        p += sprintf(p, "Emulated SWP:\t\t%lu\n", swpcounter);
+        p += sprintf(p, "Emulated SWPB:\t\t%lu\n", swpbcounter);
+        p += sprintf(p, "Aborted SWP{B}:\t\t%lu\n", abtcounter);
+        if (previous_pid != 0)
+                p += sprintf(p, "Last process:\t\t%d\n", previous_pid);
+
+        len = (p - page) - off;
+        if (len < 0)
+                len = 0;
+
+        *eof = (len <= count) ? 1 : 0;
+        *start = page + off;
+
+        return len;
+}
+#endif
+
+/*
+ * Set up process info to signal segmentation fault - called on access error.
+ */
+static void set_segfault(struct pt_regs *regs, unsigned long addr)
+{
+        siginfo_t info;
+
+        if (find_vma(current->mm, addr) == NULL)
+                info.si_code = SEGV_MAPERR;
+        else
+                info.si_code = SEGV_ACCERR;
+
+        info.si_signo = SIGSEGV;
+        info.si_errno = 0;
+        info.si_addr  = (void *) instruction_pointer(regs);
+
+        pr_debug("SWP{B} emulation: access caused memory abort!\n");
+        arm_notify_die("Illegal memory access", regs, &info, 0, 0);
+
+        abtcounter++;
+}
+
+static int emulate_swpX(unsigned int address, unsigned int *data,
+                        unsigned int type)
+{
+        unsigned int res = 0;
+
+        if ((type != TYPE_SWPB) && (address & 0x3)) {
+                /* SWP to unaligned address not permitted */
+                pr_debug("SWP instruction on unaligned pointer!\n");
+                return -EFAULT;
+        }
+
+        while (1) {
+                unsigned long temp;
+
+                /*
+                 * Barrier required between accessing protected resource and
+                 * releasing a lock for it. Legacy code might not have done
+                 * this, and we cannot determine that this is not the case
+                 * being emulated, so insert always.
+                 */
+                smp_mb();
+
+                if (type == TYPE_SWPB)
+                        __user_swpb_asm(*data, address, res, temp);
+                else
+                        __user_swp_asm(*data, address, res, temp);
+
+                if (likely(res != -EAGAIN) || signal_pending(current))
+                        break;
+
+                cond_resched();
+        }
+
+        if (res == 0) {
+                /*
+                 * Barrier also required between aquiring a lock for a
+                 * protected resource and accessing the resource. Inserted for
+                 * same reason as above.
+                 */
+                smp_mb();
+
+                if (type == TYPE_SWPB)
+                        swpbcounter++;
+                else
+                        swpcounter++;
+        }
+
+        return res;
+}
+
+/*
+ * swp_handler logs the id of calling process, dissects the instruction, sanity
+ * checks the memory location, calls emulate_swpX for the actual operation and
+ * deals with fixup/error handling before returning
+ */
+static int swp_handler(struct pt_regs *regs, unsigned int instr)
+{
+        unsigned int address, destreg, data, type;
+        unsigned int res = 0;
+
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, regs->ARM_pc);
+
+        if (current->pid != previous_pid) {
+                pr_debug("\"%s\" (%ld) uses deprecated SWP{B} instruction\n",
+                         current->comm, (unsigned long)current->pid);
+                previous_pid = current->pid;
+        }
+
+        address = regs->uregs[EXTRACT_REG_NUM(instr, RN_OFFSET)];
+        data    = regs->uregs[EXTRACT_REG_NUM(instr, RT2_OFFSET)];
+        destreg = EXTRACT_REG_NUM(instr, RT_OFFSET);
+
+        type = instr & TYPE_SWPB;
+
+        pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
+                 EXTRACT_REG_NUM(instr, RN_OFFSET), address,
+                 destreg, EXTRACT_REG_NUM(instr, RT2_OFFSET), data);
+
+        /* Check access in reasonable access range for both SWP and SWPB */
+        if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
+                pr_debug("SWP{B} emulation: access to %p not allowed!\n",
+                         (void *)address);
+                res = -EFAULT;
+        } else {
+                res = emulate_swpX(address, &data, type);
+        }
+
+        if (res == 0) {
+                /*
+                 * On successful emulation, revert the adjustment to the PC
+                 * made in kernel/traps.c in order to resume execution at the
+                 * instruction following the SWP{B}.
+                 */
+                regs->ARM_pc += 4;
+                regs->uregs[destreg] = data;
+        } else if (res == -EFAULT) {
+                /*
+                 * Memory errors do not mean emulation failed.
+                 * Set up signal info to return SEGV, then return OK
+                 */
+                set_segfault(regs, address);
+        }
+
+        return 0;
+}
+
+/*
+ * Only emulate SWP/SWPB executed in ARM state/User mode.
+ * The kernel must be SWP free and SWP{B} does not exist in Thumb/ThumbEE.
+ */
+static struct undef_hook swp_hook = {
+        .instr_mask = 0x0fb00ff0,
+        .instr_val  = 0x01000090,
+        .cpsr_mask  = MODE_MASK | PSR_T_BIT | PSR_J_BIT,
+        .cpsr_val   = USR_MODE,
+        .fn         = swp_handler
+};
+
+/*
+ * Register handler and create status file in /proc/cpu
+ * Invoked as late_initcall, since not needed before init spawned.
+ */
+static int __init swp_emulation_init(void)
+{
+#ifdef CONFIG_PROC_FS
+        struct proc_dir_entry *res;
+
+        res = create_proc_entry("cpu/swp_emulation", S_IRUGO, NULL);
+
+        if (!res)
+                return -ENOMEM;
+
+        res->read_proc = proc_read_status;
+#endif /* CONFIG_PROC_FS */
+
+        printk(KERN_NOTICE "Registering SWP/SWPB emulation handler\n");
+        register_undef_hook(&swp_hook);
+
+        return 0;
+}
+
+late_initcall(swp_emulation_init);
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index 38c261f9951c..f1e2eb19a67d 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -30,12 +30,13 @@
 #include <asm/leds.h>
 #include <asm/thread_info.h>
 #include <asm/stacktrace.h>
+#include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
 /*
  * Our system timer.
  */
-struct sys_timer *system_timer;
+static struct sys_timer *system_timer;
 
 #if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE)
 /* this needs a better home */
@@ -160,6 +161,7 @@ device_initcall(timer_init_sysfs);
 
 void __init time_init(void)
 {
+        system_timer = machine_desc->timer;
         system_timer->init();
 }
 
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 446aee97436f..ee57640ba2bb 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -37,6 +37,8 @@
 
 static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" };
 
+void *vectors_page;
+
 #ifdef CONFIG_DEBUG_USER
 unsigned int user_debug;
 
@@ -708,19 +710,19 @@ void __readwrite_bug(const char *fn)
 }
 EXPORT_SYMBOL(__readwrite_bug);
 
-void __pte_error(const char *file, int line, unsigned long val)
+void __pte_error(const char *file, int line, pte_t pte)
 {
-        printk("%s:%d: bad pte %08lx.\n", file, line, val);
+        printk("%s:%d: bad pte %08lx.\n", file, line, pte_val(pte));
 }
 
-void __pmd_error(const char *file, int line, unsigned long val)
+void __pmd_error(const char *file, int line, pmd_t pmd)
 {
-        printk("%s:%d: bad pmd %08lx.\n", file, line, val);
+        printk("%s:%d: bad pmd %08lx.\n", file, line, pmd_val(pmd));
 }
 
-void __pgd_error(const char *file, int line, unsigned long val)
+void __pgd_error(const char *file, int line, pgd_t pgd)
 {
-        printk("%s:%d: bad pgd %08lx.\n", file, line, val);
+        printk("%s:%d: bad pgd %08lx.\n", file, line, pgd_val(pgd));
 }
 
 asmlinkage void __div0(void)
@@ -756,7 +758,11 @@ static void __init kuser_get_tls_init(unsigned long vectors)
 
 void __init early_trap_init(void)
 {
+#if defined(CONFIG_CPU_USE_DOMAINS)
         unsigned long vectors = CONFIG_VECTORS_BASE;
+#else
+        unsigned long vectors = (unsigned long)vectors_page;
+#endif
         extern char __stubs_start[], __stubs_end[];
         extern char __vectors_start[], __vectors_end[];
         extern char __kuser_helper_start[], __kuser_helper_end[];
@@ -780,10 +786,10 @@ void __init early_trap_init(void)
          * Copy signal return handlers into the vector page, and
          * set sigreturn to be a pointer to these.
          */
-        memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes,
-               sizeof(sigreturn_codes));
-        memcpy((void *)KERN_RESTART_CODE, syscall_restart_code,
-               sizeof(syscall_restart_code));
+        memcpy((void *)(vectors + KERN_SIGRETURN_CODE - CONFIG_VECTORS_BASE),
+               sigreturn_codes, sizeof(sigreturn_codes));
+        memcpy((void *)(vectors + KERN_RESTART_CODE - CONFIG_VECTORS_BASE),
+               syscall_restart_code, sizeof(syscall_restart_code));
 
         flush_icache_range(vectors, vectors + PAGE_SIZE);
         modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index cead8893b46b..86b66f3f2031 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -101,6 +101,7 @@ SECTIONS
                         __exception_text_start = .;
                         *(.exception.text)
                         __exception_text_end = .;
+                        IRQENTRY_TEXT
                         TEXT_TEXT
                         SCHED_TEXT
                         LOCK_TEXT
@@ -167,6 +168,7 @@ SECTIONS
 
                 NOSAVE_DATA
                 CACHELINE_ALIGNED_DATA(32)
+                READ_MOSTLY_DATA(32)
 
                 /*
                  * The exception fixup table (might need resorting at runtime)
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index b1631a7dbe75..1b049cd7a49a 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -28,20 +28,21 @@
  */
 #include <linux/linkage.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 ENTRY(__get_user_1)
-1:      ldrbt   r2, [r0]
+1:      T(ldrb) r2, [r0]
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__get_user_1)
 
 ENTRY(__get_user_2)
 #ifdef CONFIG_THUMB2_KERNEL
-2:      ldrbt   r2, [r0]
-3:      ldrbt   r3, [r0, #1]
+2:      T(ldrb) r2, [r0]
+3:      T(ldrb) r3, [r0, #1]
 #else
-2:      ldrbt   r2, [r0], #1
-3:      ldrbt   r3, [r0]
+2:      T(ldrb) r2, [r0], #1
+3:      T(ldrb) r3, [r0]
 #endif
 #ifndef __ARMEB__
         orr     r2, r2, r3, lsl #8
@@ -53,7 +54,7 @@ ENTRY(__get_user_2)
 ENDPROC(__get_user_2)
 
 ENTRY(__get_user_4)
-4:      ldrt    r2, [r0]
+4:      T(ldr)  r2, [r0]
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__get_user_4)
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 5a01a23c6c06..c023fc11e86c 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -28,9 +28,10 @@
  */
 #include <linux/linkage.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 ENTRY(__put_user_1)
-1:      strbt   r2, [r0]
+1:      T(strb) r2, [r0]
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__put_user_1)
@@ -39,19 +40,19 @@ ENTRY(__put_user_2)
         mov     ip, r2, lsr #8
 #ifdef CONFIG_THUMB2_KERNEL
 #ifndef __ARMEB__
-2:      strbt   r2, [r0]
-3:      strbt   ip, [r0, #1]
+2:      T(strb) r2, [r0]
+3:      T(strb) ip, [r0, #1]
 #else
-2:      strbt   ip, [r0]
-3:      strbt   r2, [r0, #1]
+2:      T(strb) ip, [r0]
+3:      T(strb) r2, [r0, #1]
 #endif
 #else   /* !CONFIG_THUMB2_KERNEL */
 #ifndef __ARMEB__
-2:      strbt   r2, [r0], #1
-3:      strbt   ip, [r0]
+2:      T(strb) r2, [r0], #1
+3:      T(strb) ip, [r0]
 #else
-2:      strbt   ip, [r0], #1
-3:      strbt   r2, [r0]
+2:      T(strb) ip, [r0], #1
+3:      T(strb) r2, [r0]
 #endif
 #endif  /* CONFIG_THUMB2_KERNEL */
         mov     r0, #0
@@ -59,18 +60,18 @@ ENTRY(__put_user_2)
 ENDPROC(__put_user_2)
 
 ENTRY(__put_user_4)
-4:      strt    r2, [r0]
+4:      T(str)  r2, [r0]
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__put_user_4)
 
 ENTRY(__put_user_8)
 #ifdef CONFIG_THUMB2_KERNEL
-5:      strt    r2, [r0]
-6:      strt    r3, [r0, #4]
+5:      T(str)  r2, [r0]
+6:      T(str)  r3, [r0, #4]
 #else
-5:      strt    r2, [r0], #4
-6:      strt    r3, [r0]
+5:      T(str)  r2, [r0], #4
+6:      T(str)  r3, [r0]
 #endif
         mov     r0, #0
         mov     pc, lr
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index fee9f6f88adb..d0ece2aeb70d 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -14,6 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
                 .text
 
@@ -31,11 +32,11 @@
                 rsb     ip, ip, #4
                 cmp     ip, #2
                 ldrb    r3, [r1], #1
-USER(           strbt   r3, [r0], #1)                   @ May fault
+USER(           T(strb) r3, [r0], #1)                   @ May fault
                 ldrgeb  r3, [r1], #1
-USER(           strgebt r3, [r0], #1)                   @ May fault
+USER(           T(strgeb) r3, [r0], #1)                 @ May fault
                 ldrgtb  r3, [r1], #1
-USER(           strgtbt r3, [r0], #1)                   @ May fault
+USER(           T(strgtb) r3, [r0], #1)                 @ May fault
                 sub     r2, r2, ip
                 b       .Lc2u_dest_aligned
 
@@ -58,7 +59,7 @@ ENTRY(__copy_to_user)
                 addmi   ip, r2, #4
                 bmi     .Lc2u_0nowords
                 ldr     r3, [r1], #4
-USER(           strt    r3, [r0], #4)                   @ May fault
+USER(           T(str)  r3, [r0], #4)                   @ May fault
                 mov     ip, r0, lsl #32 - PAGE_SHIFT    @ On each page, use a ld/st??t instruction
                 rsb     ip, ip, #0
                 movs    ip, ip, lsr #32 - PAGE_SHIFT
@@ -87,18 +88,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
                 stmneia r0!, {r3 - r4}                  @ Shouldnt fault
                 tst     ip, #4
                 ldrne   r3, [r1], #4
-                strnet  r3, [r0], #4                    @ Shouldnt fault
+                T(strne) r3, [r0], #4                   @ Shouldnt fault
                 ands    ip, ip, #3
                 beq     .Lc2u_0fupi
 .Lc2u_0nowords: teq     ip, #0
                 beq     .Lc2u_finished
 .Lc2u_nowords:  cmp     ip, #2
                 ldrb    r3, [r1], #1
-USER(           strbt   r3, [r0], #1)                   @ May fault
+USER(           T(strb) r3, [r0], #1)                   @ May fault
                 ldrgeb  r3, [r1], #1
-USER(           strgebt r3, [r0], #1)                   @ May fault
+USER(           T(strgeb) r3, [r0], #1)                 @ May fault
                 ldrgtb  r3, [r1], #1
-USER(           strgtbt r3, [r0], #1)                   @ May fault
+USER(           T(strgtb) r3, [r0], #1)                 @ May fault
                 b       .Lc2u_finished
 
 .Lc2u_not_enough:
@@ -119,7 +120,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
                 mov     r3, r7, pull #8
                 ldr     r7, [r1], #4
                 orr     r3, r3, r7, push #24
-USER(           strt    r3, [r0], #4)                   @ May fault
+USER(           T(str)  r3, [r0], #4)                   @ May fault
                 mov     ip, r0, lsl #32 - PAGE_SHIFT
                 rsb     ip, ip, #0
                 movs    ip, ip, lsr #32 - PAGE_SHIFT
@@ -154,18 +155,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
                 movne   r3, r7, pull #8
                 ldrne   r7, [r1], #4
                 orrne   r3, r3, r7, push #24
-                strnet  r3, [r0], #4                    @ Shouldnt fault
+                T(strne) r3, [r0], #4                   @ Shouldnt fault
                 ands    ip, ip, #3
                 beq     .Lc2u_1fupi
 .Lc2u_1nowords: mov     r3, r7, get_byte_1
                 teq     ip, #0
                 beq     .Lc2u_finished
                 cmp     ip, #2
-USER(           strbt   r3, [r0], #1)                   @ May fault
+USER(           T(strb) r3, [r0], #1)                   @ May fault
                 movge   r3, r7, get_byte_2
-USER(           strgebt r3, [r0], #1)                   @ May fault
+USER(           T(strgeb) r3, [r0], #1)                 @ May fault
                 movgt   r3, r7, get_byte_3
-USER(           strgtbt r3, [r0], #1)                   @ May fault
+USER(           T(strgtb) r3, [r0], #1)                 @ May fault
                 b       .Lc2u_finished
 
 .Lc2u_2fupi:    subs    r2, r2, #4
@@ -174,7 +175,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
                 mov     r3, r7, pull #16
                 ldr     r7, [r1], #4
                 orr     r3, r3, r7, push #16
-USER(           strt    r3, [r0], #4)                   @ May fault
+USER(           T(str)  r3, [r0], #4)                   @ May fault
                 mov     ip, r0, lsl #32 - PAGE_SHIFT
                 rsb     ip, ip, #0
                 movs    ip, ip, lsr #32 - PAGE_SHIFT
@@ -209,18 +210,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
                 movne   r3, r7, pull #16
                 ldrne   r7, [r1], #4
                 orrne   r3, r3, r7, push #16
-                strnet  r3, [r0], #4                    @ Shouldnt fault
+                T(strne) r3, [r0], #4                   @ Shouldnt fault
                 ands    ip, ip, #3
                 beq     .Lc2u_2fupi
 .Lc2u_2nowords: mov     r3, r7, get_byte_2
                 teq     ip, #0
                 beq     .Lc2u_finished
                 cmp     ip, #2
-USER(           strbt   r3, [r0], #1)                   @ May fault
+USER(           T(strb) r3, [r0], #1)                   @ May fault
                 movge   r3, r7, get_byte_3
-USER(           strgebt r3, [r0], #1)                   @ May fault
+USER(           T(strgeb) r3, [r0], #1)                 @ May fault
                 ldrgtb  r3, [r1], #0
-USER(           strgtbt r3, [r0], #1)                   @ May fault
+USER(           T(strgtb) r3, [r0], #1)                 @ May fault
                 b       .Lc2u_finished
 
 .Lc2u_3fupi:    subs    r2, r2, #4
@@ -229,7 +230,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
                 mov     r3, r7, pull #24
                 ldr     r7, [r1], #4
                 orr     r3, r3, r7, push #8
-USER(           strt    r3, [r0], #4)                   @ May fault
+USER(           T(str)  r3, [r0], #4)                   @ May fault
                 mov     ip, r0, lsl #32 - PAGE_SHIFT
                 rsb     ip, ip, #0
                 movs    ip, ip, lsr #32 - PAGE_SHIFT
@@ -264,18 +265,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
                 movne   r3, r7, pull #24
                 ldrne   r7, [r1], #4
                 orrne   r3, r3, r7, push #8
-                strnet  r3, [r0], #4                    @ Shouldnt fault
+                T(strne) r3, [r0], #4                   @ Shouldnt fault
                 ands    ip, ip, #3
                 beq     .Lc2u_3fupi
 .Lc2u_3nowords: mov     r3, r7, get_byte_3
                 teq     ip, #0
                 beq     .Lc2u_finished
                 cmp     ip, #2
-USER(           strbt   r3, [r0], #1)                   @ May fault
+USER(           T(strb) r3, [r0], #1)                   @ May fault
                 ldrgeb  r3, [r1], #1
-USER(           strgebt r3, [r0], #1)                   @ May fault
+USER(           T(strgeb) r3, [r0], #1)                 @ May fault
                 ldrgtb  r3, [r1], #0
-USER(           strgtbt r3, [r0], #1)                   @ May fault
+USER(           T(strgtb) r3, [r0], #1)                 @ May fault
                 b       .Lc2u_finished
 ENDPROC(__copy_to_user)
 
@@ -294,11 +295,11 @@ ENDPROC(__copy_to_user)
 .Lcfu_dest_not_aligned:
                 rsb     ip, ip, #4
                 cmp     ip, #2
-USER(           ldrbt   r3, [r1], #1)                   @ May fault
+USER(           T(ldrb) r3, [r1], #1)                   @ May fault
                 strb    r3, [r0], #1
-USER(           ldrgebt r3, [r1], #1)                   @ May fault
+USER(           T(ldrgeb) r3, [r1], #1)                 @ May fault
                 strgeb  r3, [r0], #1
-USER(           ldrgtbt r3, [r1], #1)                   @ May fault
+USER(           T(ldrgtb) r3, [r1], #1)                 @ May fault
                 strgtb  r3, [r0], #1
                 sub     r2, r2, ip
                 b       .Lcfu_dest_aligned
@@ -321,7 +322,7 @@ ENTRY(__copy_from_user)
 .Lcfu_0fupi:    subs    r2, r2, #4
                 addmi   ip, r2, #4
                 bmi     .Lcfu_0nowords
-USER(           ldrt    r3, [r1], #4)
+USER(           T(ldr)  r3, [r1], #4)
                 str     r3, [r0], #4
                 mov     ip, r1, lsl #32 - PAGE_SHIFT    @ On each page, use a ld/st??t instruction
                 rsb     ip, ip, #0
@@ -350,18 +351,18 @@ USER(		ldrt	r3, [r1], #4)
                 ldmneia r1!, {r3 - r4}                  @ Shouldnt fault
                 stmneia r0!, {r3 - r4}
                 tst     ip, #4
-                ldrnet  r3, [r1], #4                    @ Shouldnt fault
+                T(ldrne) r3, [r1], #4                   @ Shouldnt fault
                 strne   r3, [r0], #4
                 ands    ip, ip, #3
                 beq     .Lcfu_0fupi
 .Lcfu_0nowords: teq     ip, #0
                 beq     .Lcfu_finished
 .Lcfu_nowords:  cmp     ip, #2
-USER(           ldrbt   r3, [r1], #1)                   @ May fault
+USER(           T(ldrb) r3, [r1], #1)                   @ May fault
                 strb    r3, [r0], #1
-USER(           ldrgebt r3, [r1], #1)                   @ May fault
+USER(           T(ldrgeb) r3, [r1], #1)                 @ May fault
                 strgeb  r3, [r0], #1
-USER(           ldrgtbt r3, [r1], #1)                   @ May fault
+USER(           T(ldrgtb) r3, [r1], #1)                 @ May fault
                 strgtb  r3, [r0], #1
                 b       .Lcfu_finished
 
@@ -374,7 +375,7 @@ USER(		ldrgtbt	r3, [r1], #1)			@ May fault
 
 .Lcfu_src_not_aligned:
                 bic     r1, r1, #3
-USER(           ldrt    r7, [r1], #4)                   @ May fault
+USER(           T(ldr)  r7, [r1], #4)                   @ May fault
                 cmp     ip, #2
                 bgt     .Lcfu_3fupi
                 beq     .Lcfu_2fupi
@@ -382,7 +383,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
                 addmi   ip, r2, #4
                 bmi     .Lcfu_1nowords
                 mov     r3, r7, pull #8
-USER(           ldrt    r7, [r1], #4)                   @ May fault
+USER(           T(ldr)  r7, [r1], #4)                   @ May fault
                 orr     r3, r3, r7, push #24
                 str     r3, [r0], #4
                 mov     ip, r1, lsl #32 - PAGE_SHIFT
@@ -417,7 +418,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
                 stmneia r0!, {r3 - r4}
                 tst     ip, #4
                 movne   r3, r7, pull #8
-USER(           ldrnet  r7, [r1], #4)                   @ May fault
+USER(           T(ldrne) r7, [r1], #4)                  @ May fault
                 orrne   r3, r3, r7, push #24
                 strne   r3, [r0], #4
                 ands    ip, ip, #3
@@ -437,7 +438,7 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
                 addmi   ip, r2, #4
                 bmi     .Lcfu_2nowords
                 mov     r3, r7, pull #16
-USER(           ldrt    r7, [r1], #4)                   @ May fault
+USER(           T(ldr)  r7, [r1], #4)                   @ May fault
                 orr     r3, r3, r7, push #16
                 str     r3, [r0], #4
                 mov     ip, r1, lsl #32 - PAGE_SHIFT
@@ -473,7 +474,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
                 stmneia r0!, {r3 - r4}
                 tst     ip, #4
                 movne   r3, r7, pull #16
-USER(           ldrnet  r7, [r1], #4)                   @ May fault
+USER(           T(ldrne) r7, [r1], #4)                  @ May fault
                 orrne   r3, r3, r7, push #16
                 strne   r3, [r0], #4
                 ands    ip, ip, #3
@@ -485,7 +486,7 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
                 strb    r3, [r0], #1
                 movge   r3, r7, get_byte_3
                 strgeb  r3, [r0], #1
-USER(           ldrgtbt r3, [r1], #0)                   @ May fault
+USER(           T(ldrgtb) r3, [r1], #0)                 @ May fault
                 strgtb  r3, [r0], #1
                 b       .Lcfu_finished
 
@@ -493,7 +494,7 @@ USER(		ldrgtbt	r3, [r1], #0)			@ May fault
                 addmi   ip, r2, #4
                 bmi     .Lcfu_3nowords
                 mov     r3, r7, pull #24
-USER(           ldrt    r7, [r1], #4)                   @ May fault
+USER(           T(ldr)  r7, [r1], #4)                   @ May fault
                 orr     r3, r3, r7, push #8
                 str     r3, [r0], #4
                 mov     ip, r1, lsl #32 - PAGE_SHIFT
@@ -528,7 +529,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
                 stmneia r0!, {r3 - r4}
                 tst     ip, #4
                 movne   r3, r7, pull #24
-USER(           ldrnet  r7, [r1], #4)                   @ May fault
+USER(           T(ldrne) r7, [r1], #4)                  @ May fault
                 orrne   r3, r3, r7, push #8
                 strne   r3, [r0], #4
                 ands    ip, ip, #3
@@ -538,9 +539,9 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
                 beq     .Lcfu_finished
                 cmp     ip, #2
                 strb    r3, [r0], #1
-USER(           ldrgebt r3, [r1], #1)                   @ May fault
+USER(           T(ldrgeb) r3, [r1], #1)                 @ May fault
                 strgeb  r3, [r0], #1
-USER(           ldrgtbt r3, [r1], #1)                   @ May fault
+USER(           T(ldrgtb) r3, [r1], #1)                 @ May fault
                 strgtb  r3, [r0], #1
                 b       .Lcfu_finished
 ENDPROC(__copy_from_user)
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 2500f41d8d2d..1dd69c85dfec 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -101,7 +101,6 @@ static struct clocksource clk32k = {
         .rating         = 150,
         .read           = read_clk32k,
         .mask           = CLOCKSOURCE_MASK(20),
-        .shift          = 10,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -201,8 +200,7 @@ void __init at91rm9200_timer_init(void)
         clockevents_register_device(&clkevt);
 
         /* register clocksource */
-        clk32k.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, clk32k.shift);
-        clocksource_register(&clk32k);
+        clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
 }
 
 struct sys_timer at91rm9200_timer = {
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 608a63240b64..4ba85499fa97 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -51,7 +51,6 @@ static struct clocksource pit_clk = {
         .name           = "pit",
         .rating         = 175,
         .read           = read_pit_clk,
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -163,10 +162,9 @@ static void __init at91sam926x_pit_init(void)
          * Register clocksource.  The high order bits of PIV are unused,
          * so this isn't a 32-bit counter unless we get clockevent irqs.
          */
-        pit_clk.mult = clocksource_hz2mult(pit_rate, pit_clk.shift);
         bits = 12 /* PICNT */ + ilog2(pit_cycle) /* PIV */;
         pit_clk.mask = CLOCKSOURCE_MASK(bits);
-        clocksource_register(&pit_clk);
+        clocksource_register_hz(&pit_clk, pit_rate);
 
         /* Set up irq handler */
         setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
index 14bafc38f2dc..ad237a42d265 100644
--- a/arch/arm/mach-bcmring/clock.c
+++ b/arch/arm/mach-bcmring/clock.c
@@ -21,13 +21,12 @@
 #include <linux/string.h>
 #include <linux/clk.h>
 #include <linux/spinlock.h>
+#include <linux/clkdev.h>
 #include <mach/csp/hw_cfg.h>
 #include <mach/csp/chipcHw_def.h>
 #include <mach/csp/chipcHw_reg.h>
 #include <mach/csp/chipcHw_inline.h>
 
-#include <asm/clkdev.h>
-
 #include "clock.h"
 
 #define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index d3f959e92b2d..8fc2035759fb 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -30,10 +30,10 @@
 #include <linux/amba/bus.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
+#include <linux/clkdev.h>
 
 #include <mach/csp/mm_addr.h>
 #include <mach/hardware.h>
-#include <asm/clkdev.h>
 #include <linux/io.h>
 #include <asm/irq.h>
 #include <asm/hardware/arm_timer.h>
@@ -294,7 +294,6 @@ static struct clocksource clocksource_bcmring_timer1 = {
         .rating = 200,
         .read = bcmring_get_cycles_timer1,
         .mask = CLOCKSOURCE_MASK(32),
-        .shift = 20,
         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -303,7 +302,6 @@ static struct clocksource clocksource_bcmring_timer3 = {
         .rating = 100,
         .read = bcmring_get_cycles_timer3,
         .mask = CLOCKSOURCE_MASK(32),
-        .shift = 20,
         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -316,10 +314,8 @@ static int __init bcmring_clocksource_init(void)
         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
                TIMER1_VA_BASE + TIMER_CTRL);
 
-        clocksource_bcmring_timer1.mult =
-            clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000,
-                                 clocksource_bcmring_timer1.shift);
-        clocksource_register(&clocksource_bcmring_timer1);
+        clocksource_register_khz(&clocksource_bcmring_timer1,
+                                 TIMER1_FREQUENCY_MHZ * 1000);
 
         /* setup timer3 as free-running clocksource */
         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
@@ -328,10 +324,8 @@ static int __init bcmring_clocksource_init(void)
         writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
                TIMER3_VA_BASE + TIMER_CTRL);
 
-        clocksource_bcmring_timer3.mult =
-            clocksource_khz2mult(TIMER3_FREQUENCY_KHZ,
-                                 clocksource_bcmring_timer3.shift);
-        clocksource_register(&clocksource_bcmring_timer3);
+        clocksource_register_khz(&clocksource_bcmring_timer3,
+                                 TIMER3_FREQUENCY_KHZ);
 
         return 0;
 }
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index 9ebfcc46feb1..29b13f249aa9 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -3,6 +3,7 @@ menu "CNS3XXX platform type"
 
 config MACH_CNS3420VB
         bool "Support for CNS3420 Validation Board"
+        select MIGHT_HAVE_PCI
         help
           Include support for the Cavium Networks CNS3420 MPCore Platform
           Baseboard.
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 90fe9ab8591d..08e5c8759502 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -17,6 +17,7 @@
 #include <linux/kernel.h>
 #include <linux/compiler.h>
 #include <linux/io.h>
+#include <linux/dma-mapping.h>
 #include <linux/serial_core.h>
 #include <linux/serial_8250.h>
 #include <linux/platform_device.h>
@@ -108,10 +109,63 @@ static void __init cns3420_early_serial_setup(void)
 }
 
 /*
+ * USB
+ */
+static struct resource cns3xxx_usb_ehci_resources[] = {
+        [0] = {
+                .start = CNS3XXX_USB_BASE,
+                .end   = CNS3XXX_USB_BASE + SZ_16M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_CNS3XXX_USB_EHCI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_usb_ehci_device = {
+        .name          = "cns3xxx-ehci",
+        .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
+        .resource      = cns3xxx_usb_ehci_resources,
+        .dev           = {
+                .dma_mask          = &cns3xxx_usb_ehci_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource cns3xxx_usb_ohci_resources[] = {
+        [0] = {
+                .start = CNS3XXX_USB_OHCI_BASE,
+                .end   = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_CNS3XXX_USB_OHCI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_usb_ohci_device = {
+        .name          = "cns3xxx-ohci",
+        .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
+        .resource      = cns3xxx_usb_ohci_resources,
+        .dev           = {
+                .dma_mask          = &cns3xxx_usb_ohci_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+/*
  * Initialization
  */
 static struct platform_device *cns3420_pdevs[] __initdata = {
         &cns3420_nor_pdev,
+        &cns3xxx_usb_ehci_device,
+        &cns3xxx_usb_ohci_device,
 };
 
 static void __init cns3420_init(void)
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 9ca4d581016f..da30078a80c1 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -69,13 +69,10 @@ void __init cns3xxx_map_io(void)
 }
 
 /* used by entry-macro.S */
-void __iomem *gic_cpu_base_addr;
-
 void __init cns3xxx_init_irq(void)
 {
-        gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
-        gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29);
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
+                 __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
 }
 
 void cns3xxx_power_off(void)
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index 6b33ec11346e..ffeb3a8b73ba 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -11,13 +11,10 @@
 #ifndef __CNS3XXX_CORE_H
 #define __CNS3XXX_CORE_H
 
-extern void __iomem *gic_cpu_base_addr;
 extern struct sys_timer cns3xxx_timer;
 
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
-void cns3xxx_pwr_power_up(unsigned int block);
-void cns3xxx_pwr_power_down(unsigned int block);
 
 #endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
index 50b4d31c27c0..79d1fb02c23f 100644
--- a/arch/arm/mach-cns3xxx/devices.c
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
+#include <mach/pm.h>
 #include "core.h"
 #include "devices.h"
 
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 6dbce13771ca..191c8e57f289 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -165,7 +165,6 @@
 #define CNS3XXX_USBOTG_BASE_VIRT                0xFFF15000
 
 #define CNS3XXX_USB_BASE                        0x82000000      /* USB Host Control */
-#define CNS3XXX_USB_BASE_VIRT                   0xFFF16000
 
 #define CNS3XXX_SATA2_BASE                      0x83000000      /* SATA */
 #define CNS3XXX_SATA2_SIZE                      SZ_16M
@@ -184,7 +183,6 @@
 #define CNS3XXX_2DG_BASE_VIRT                   0xFFF1B000
 
 #define CNS3XXX_USB_OHCI_BASE                   0x88000000      /* USB OHCI */
-#define CNS3XXX_USB_OHCI_BASE_VIRT              0xFFF1C000
 
 #define CNS3XXX_L2C_BASE                        0x92000000      /* L2 Cache Control */
 #define CNS3XXX_L2C_BASE_VIRT                   0xFFF27000
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
index 5e1c5545680f..6bd83ed90afe 100644
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -9,74 +9,10 @@
  */
 
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
                 .macro  disable_fiq
                 .endm
 
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =gic_cpu_base_addr
-                ldr     \base, [\base]
-                .endm
-
                 .macro  arch_ret_to_user, tmp1, tmp2
                 .endm
-
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an interrupt if it's
-                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
-                ldr     \tmp, =1021
-
-                bic     \irqnr, \irqstat, #0x1c00
-
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-
-                .endm
-
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt on the
-                 * controller, since this requires the original irqstat value which
-                 * we won't easily be able to recreate later.
-                 */
-
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* As above, this assumes that irqstat and base are preserved.. */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
diff --git a/arch/arm/mach-cns3xxx/include/mach/pm.h b/arch/arm/mach-cns3xxx/include/mach/pm.h
new file mode 100644
index 000000000000..6eae7f764d1d
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/pm.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2000 Deep Blue Solutions Ltd
+ * Copyright 2004 ARM Limited
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CNS3XXX_PM_H
+#define __CNS3XXX_PM_H
+
+#include <asm/atomic.h>
+
+void cns3xxx_pwr_clk_en(unsigned int block);
+void cns3xxx_pwr_clk_dis(unsigned int block);
+void cns3xxx_pwr_power_up(unsigned int block);
+void cns3xxx_pwr_power_down(unsigned int block);
+
+extern atomic_t usb_pwr_ref;
+
+#endif /* __CNS3XXX_PM_H */
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 38e44706feab..5e579552aa54 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -6,10 +6,14 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/init.h>
+#include <linux/module.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <asm/atomic.h>
 #include <mach/system.h>
 #include <mach/cns3xxx.h>
+#include <mach/pm.h>
 
 void cns3xxx_pwr_clk_en(unsigned int block)
 {
@@ -18,6 +22,16 @@ void cns3xxx_pwr_clk_en(unsigned int block)
         reg |= (block & PM_CLK_GATE_REG_MASK);
         __raw_writel(reg, PM_CLK_GATE_REG);
 }
+EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
+
+void cns3xxx_pwr_clk_dis(unsigned int block)
+{
+        u32 reg = __raw_readl(PM_CLK_GATE_REG);
+
+        reg &= ~(block & PM_CLK_GATE_REG_MASK);
+        __raw_writel(reg, PM_CLK_GATE_REG);
+}
+EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
 
 void cns3xxx_pwr_power_up(unsigned int block)
 {
@@ -29,6 +43,7 @@ void cns3xxx_pwr_power_up(unsigned int block)
         /* Wait for 300us for the PLL output clock locked. */
         udelay(300);
 };
+EXPORT_SYMBOL(cns3xxx_pwr_power_up);
 
 void cns3xxx_pwr_power_down(unsigned int block)
 {
@@ -38,6 +53,7 @@ void cns3xxx_pwr_power_down(unsigned int block)
         reg |= (block & CNS3XXX_PWR_PLL_ALL);
         __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 };
+EXPORT_SYMBOL(cns3xxx_pwr_power_down);
 
 static void cns3xxx_pwr_soft_rst_force(unsigned int block)
 {
@@ -51,11 +67,13 @@ static void cns3xxx_pwr_soft_rst_force(unsigned int block)
                 reg &= ~(block & PM_SOFT_RST_REG_MASK);
         } else {
                 reg &= ~(block & PM_SOFT_RST_REG_MASK);
+                __raw_writel(reg, PM_SOFT_RST_REG);
                 reg |= (block & PM_SOFT_RST_REG_MASK);
         }
 
         __raw_writel(reg, PM_SOFT_RST_REG);
 }
+EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
 
 void cns3xxx_pwr_soft_rst(unsigned int block)
 {
@@ -69,6 +87,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
         }
         cns3xxx_pwr_soft_rst_force(block);
 }
+EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
 
 void arch_reset(char mode, const char *cmd)
 {
@@ -99,3 +118,7 @@ int cns3xxx_cpu_clock(void)
 
         return cpu;
 }
+EXPORT_SYMBOL(cns3xxx_cpu_clock);
+
+atomic_t usb_pwr_ref = ATOMIC_INIT(0);
+EXPORT_SYMBOL(usb_pwr_ref);
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index b77b860b36d7..32f147998cd9 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -61,6 +61,8 @@ config MACH_DAVINCI_EVM
         bool "TI DM644x EVM"
         default ARCH_DAVINCI_DM644x
         depends on ARCH_DAVINCI_DM644x
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Configure this option to specify the whether the board used
           for development is a DM644x EVM
@@ -68,6 +70,8 @@ config MACH_DAVINCI_EVM
 config MACH_SFFSDR
         bool "Lyrtech SFFSDR"
         depends on ARCH_DAVINCI_DM644x
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Say Y here to select the Lyrtech Small Form Factor
           Software Defined Radio (SFFSDR) board.
@@ -99,6 +103,8 @@ config MACH_DAVINCI_DM6467_EVM
         default ARCH_DAVINCI_DM646x
         depends on ARCH_DAVINCI_DM646x
         select MACH_DAVINCI_DM6467TEVM
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Configure this option to specify the whether the board used
           for development is a DM6467 EVM
@@ -110,6 +116,8 @@ config MACH_DAVINCI_DM365_EVM
         bool "TI DM365 EVM"
         default ARCH_DAVINCI_DM365
         depends on ARCH_DAVINCI_DM365
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Configure this option to specify whether the board used
           for development is a DM365 EVM
@@ -119,6 +127,8 @@ config MACH_DAVINCI_DA830_EVM
         default ARCH_DAVINCI_DA830
         depends on ARCH_DAVINCI_DA830
         select GPIO_PCF857X
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.
 
@@ -148,7 +158,6 @@ config MACH_DAVINCI_DA850_EVM
         bool "TI DA850/OMAP-L138/AM18x Reference Platform"
         default ARCH_DAVINCI_DA850
         depends on ARCH_DAVINCI_DA850
-        select GPIO_PCA953X
         help
           Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module.
 
@@ -178,6 +187,12 @@ config DA850_UI_RMII
 
 endchoice
 
+config GPIO_PCA953X
+        default MACH_DAVINCI_DA850_EVM
+
+config KEYBOARD_GPIO_POLLED
+        default MACH_DAVINCI_DA850_EVM
+
 config MACH_TNETV107X
         bool "TI TNETV107X Reference Platform"
         default ARCH_DAVINCI_TNETV107X
@@ -188,6 +203,8 @@ config MACH_TNETV107X
 config MACH_MITYOMAPL138
         bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
         depends on ARCH_DAVINCI_DA850
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
           System on Module.  Information on this SoM may be found at
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index 9c3f500fc12f..1ce70a91f2e9 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -90,7 +90,7 @@ int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
                                         void __iomem *base, unsigned cs)
 {
         unsigned set, val;
-        unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
+        int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
         unsigned offset = A1CR_OFFSET + cs * 4;
         struct clk *aemif_clk;
         unsigned long clkrate;
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index c6e11c682e4c..b01fb2ab944a 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -17,8 +17,10 @@
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/i2c/pca953x.h>
+#include <linux/input.h>
 #include <linux/mfd/tps6507x.h>
 #include <linux/gpio.h>
+#include <linux/gpio_keys.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -266,34 +268,115 @@ static inline void da850_evm_setup_emac_rmii(int rmii_sel)
         struct davinci_soc_info *soc_info = &davinci_soc_info;
 
         soc_info->emac_pdata->rmii_en = 1;
-        gpio_set_value(rmii_sel, 0);
+        gpio_set_value_cansleep(rmii_sel, 0);
 }
 #else
 static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
 #endif
 
+
+#define DA850_KEYS_DEBOUNCE_MS  10
+/*
+ * At 200ms polling interval it is possible to miss an
+ * event by tapping very lightly on the push button but most
+ * pushes do result in an event; longer intervals require the
+ * user to hold the button whereas shorter intervals require
+ * more CPU time for polling.
+ */
+#define DA850_GPIO_KEYS_POLL_MS 200
+
+enum da850_evm_ui_exp_pins {
+        DA850_EVM_UI_EXP_SEL_C = 5,
+        DA850_EVM_UI_EXP_SEL_B,
+        DA850_EVM_UI_EXP_SEL_A,
+        DA850_EVM_UI_EXP_PB8,
+        DA850_EVM_UI_EXP_PB7,
+        DA850_EVM_UI_EXP_PB6,
+        DA850_EVM_UI_EXP_PB5,
+        DA850_EVM_UI_EXP_PB4,
+        DA850_EVM_UI_EXP_PB3,
+        DA850_EVM_UI_EXP_PB2,
+        DA850_EVM_UI_EXP_PB1,
+};
+
+static const char const *da850_evm_ui_exp[] = {
+        [DA850_EVM_UI_EXP_SEL_C]        = "sel_c",
+        [DA850_EVM_UI_EXP_SEL_B]        = "sel_b",
+        [DA850_EVM_UI_EXP_SEL_A]        = "sel_a",
+        [DA850_EVM_UI_EXP_PB8]          = "pb8",
+        [DA850_EVM_UI_EXP_PB7]          = "pb7",
+        [DA850_EVM_UI_EXP_PB6]          = "pb6",
+        [DA850_EVM_UI_EXP_PB5]          = "pb5",
+        [DA850_EVM_UI_EXP_PB4]          = "pb4",
+        [DA850_EVM_UI_EXP_PB3]          = "pb3",
+        [DA850_EVM_UI_EXP_PB2]          = "pb2",
+        [DA850_EVM_UI_EXP_PB1]          = "pb1",
+};
+
+#define DA850_N_UI_PB           8
+
+static struct gpio_keys_button da850_evm_ui_keys[] = {
+        [0 ... DA850_N_UI_PB - 1] = {
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 0,
+                .debounce_interval      = DA850_KEYS_DEBOUNCE_MS,
+                .code                   = -1, /* assigned at runtime */
+                .gpio                   = -1, /* assigned at runtime */
+                .desc                   = NULL, /* assigned at runtime */
+        },
+};
+
+static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = {
+        .buttons = da850_evm_ui_keys,
+        .nbuttons = ARRAY_SIZE(da850_evm_ui_keys),
+        .poll_interval = DA850_GPIO_KEYS_POLL_MS,
+};
+
+static struct platform_device da850_evm_ui_keys_device = {
+        .name = "gpio-keys-polled",
+        .id = 0,
+        .dev = {
+                .platform_data = &da850_evm_ui_keys_pdata
+        },
+};
+
+static void da850_evm_ui_keys_init(unsigned gpio)
+{
+        int i;
+        struct gpio_keys_button *button;
+
+        for (i = 0; i < DA850_N_UI_PB; i++) {
+                button = &da850_evm_ui_keys[i];
+                button->code = KEY_F8 - i;
+                button->desc = (char *)
+                                da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
+                button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i;
+        }
+}
+
 static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
                                                 unsigned ngpio, void *c)
 {
         int sel_a, sel_b, sel_c, ret;
 
-        sel_a = gpio + 7;
-        sel_b = gpio + 6;
-        sel_c = gpio + 5;
+        sel_a = gpio + DA850_EVM_UI_EXP_SEL_A;
+        sel_b = gpio + DA850_EVM_UI_EXP_SEL_B;
+        sel_c = gpio + DA850_EVM_UI_EXP_SEL_C;
 
-        ret = gpio_request(sel_a, "sel_a");
+        ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]);
         if (ret) {
                 pr_warning("Cannot open UI expander pin %d\n", sel_a);
                 goto exp_setup_sela_fail;
         }
 
-        ret = gpio_request(sel_b, "sel_b");
+        ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]);
         if (ret) {
                 pr_warning("Cannot open UI expander pin %d\n", sel_b);
                 goto exp_setup_selb_fail;
         }
 
-        ret = gpio_request(sel_c, "sel_c");
+        ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]);
         if (ret) {
                 pr_warning("Cannot open UI expander pin %d\n", sel_c);
                 goto exp_setup_selc_fail;
@@ -304,6 +387,13 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
         gpio_direction_output(sel_b, 1);
         gpio_direction_output(sel_c, 1);
 
+        da850_evm_ui_keys_init(gpio);
+        ret = platform_device_register(&da850_evm_ui_keys_device);
+        if (ret) {
+                pr_warning("Could not register UI GPIO expander push-buttons");
+                goto exp_setup_keys_fail;
+        }
+
         ui_card_detected = 1;
         pr_info("DA850/OMAP-L138 EVM UI card detected\n");
 
@@ -313,6 +403,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
 
         return 0;
 
+exp_setup_keys_fail:
+        gpio_free(sel_c);
 exp_setup_selc_fail:
         gpio_free(sel_b);
 exp_setup_selb_fail:
@@ -324,14 +416,192 @@ exp_setup_sela_fail:
 static int da850_evm_ui_expander_teardown(struct i2c_client *client,
                                         unsigned gpio, unsigned ngpio, void *c)
 {
+        platform_device_unregister(&da850_evm_ui_keys_device);
+
         /* deselect all functionalities */
-        gpio_set_value(gpio + 5, 1);
-        gpio_set_value(gpio + 6, 1);
-        gpio_set_value(gpio + 7, 1);
+        gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1);
+        gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1);
+        gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1);
+
+        gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C);
+        gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B);
+        gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A);
+
+        return 0;
+}
+
+/* assign the baseboard expander's GPIOs after the UI board's */
+#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp)
+#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS)
+
+enum da850_evm_bb_exp_pins {
+        DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0,
+        DA850_EVM_BB_EXP_SW_RST,
+        DA850_EVM_BB_EXP_TP_23,
+        DA850_EVM_BB_EXP_TP_22,
+        DA850_EVM_BB_EXP_TP_21,
+        DA850_EVM_BB_EXP_USER_PB1,
+        DA850_EVM_BB_EXP_USER_LED2,
+        DA850_EVM_BB_EXP_USER_LED1,
+        DA850_EVM_BB_EXP_USER_SW1,
+        DA850_EVM_BB_EXP_USER_SW2,
+        DA850_EVM_BB_EXP_USER_SW3,
+        DA850_EVM_BB_EXP_USER_SW4,
+        DA850_EVM_BB_EXP_USER_SW5,
+        DA850_EVM_BB_EXP_USER_SW6,
+        DA850_EVM_BB_EXP_USER_SW7,
+        DA850_EVM_BB_EXP_USER_SW8
+};
+
+static const char const *da850_evm_bb_exp[] = {
+        [DA850_EVM_BB_EXP_DEEP_SLEEP_EN]        = "deep_sleep_en",
+        [DA850_EVM_BB_EXP_SW_RST]               = "sw_rst",
+        [DA850_EVM_BB_EXP_TP_23]                = "tp_23",
+        [DA850_EVM_BB_EXP_TP_22]                = "tp_22",
+        [DA850_EVM_BB_EXP_TP_21]                = "tp_21",
+        [DA850_EVM_BB_EXP_USER_PB1]             = "user_pb1",
+        [DA850_EVM_BB_EXP_USER_LED2]            = "user_led2",
+        [DA850_EVM_BB_EXP_USER_LED1]            = "user_led1",
+        [DA850_EVM_BB_EXP_USER_SW1]             = "user_sw1",
+        [DA850_EVM_BB_EXP_USER_SW2]             = "user_sw2",
+        [DA850_EVM_BB_EXP_USER_SW3]             = "user_sw3",
+        [DA850_EVM_BB_EXP_USER_SW4]             = "user_sw4",
+        [DA850_EVM_BB_EXP_USER_SW5]             = "user_sw5",
+        [DA850_EVM_BB_EXP_USER_SW6]             = "user_sw6",
+        [DA850_EVM_BB_EXP_USER_SW7]             = "user_sw7",
+        [DA850_EVM_BB_EXP_USER_SW8]             = "user_sw8",
+};
+
+#define DA850_N_BB_USER_SW      8
+
+static struct gpio_keys_button da850_evm_bb_keys[] = {
+        [0] = {
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 0,
+                .debounce_interval      = DA850_KEYS_DEBOUNCE_MS,
+                .code                   = KEY_PROG1,
+                .desc                   = NULL, /* assigned at runtime */
+                .gpio                   = -1, /* assigned at runtime */
+        },
+        [1 ... DA850_N_BB_USER_SW] = {
+                .type                   = EV_SW,
+                .active_low             = 1,
+                .wakeup                 = 0,
+                .debounce_interval      = DA850_KEYS_DEBOUNCE_MS,
+                .code                   = -1, /* assigned at runtime */
+                .desc                   = NULL, /* assigned at runtime */
+                .gpio                   = -1, /* assigned at runtime */
+        },
+};
+
+static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = {
+        .buttons = da850_evm_bb_keys,
+        .nbuttons = ARRAY_SIZE(da850_evm_bb_keys),
+        .poll_interval = DA850_GPIO_KEYS_POLL_MS,
+};
+
+static struct platform_device da850_evm_bb_keys_device = {
+        .name = "gpio-keys-polled",
+        .id = 1,
+        .dev = {
+                .platform_data = &da850_evm_bb_keys_pdata
+        },
+};
+
+static void da850_evm_bb_keys_init(unsigned gpio)
+{
+        int i;
+        struct gpio_keys_button *button;
+
+        button = &da850_evm_bb_keys[0];
+        button->desc = (char *)
+                da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
+        button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1;
+
+        for (i = 0; i < DA850_N_BB_USER_SW; i++) {
+                button = &da850_evm_bb_keys[i + 1];
+                button->code = SW_LID + i;
+                button->desc = (char *)
+                                da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
+                button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i;
+        }
+}
 
-        gpio_free(gpio + 5);
-        gpio_free(gpio + 6);
-        gpio_free(gpio + 7);
+#define DA850_N_BB_USER_LED     2
+
+static struct gpio_led da850_evm_bb_leds[] = {
+        [0 ... DA850_N_BB_USER_LED - 1] = {
+                .active_low = 1,
+                .gpio = -1, /* assigned at runtime */
+                .name = NULL, /* assigned at runtime */
+        },
+};
+
+static struct gpio_led_platform_data da850_evm_bb_leds_pdata = {
+        .leds = da850_evm_bb_leds,
+        .num_leds = ARRAY_SIZE(da850_evm_bb_leds),
+};
+
+static struct platform_device da850_evm_bb_leds_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev = {
+                .platform_data = &da850_evm_bb_leds_pdata
+        }
+};
+
+static void da850_evm_bb_leds_init(unsigned gpio)
+{
+        int i;
+        struct gpio_led *led;
+
+        for (i = 0; i < DA850_N_BB_USER_LED; i++) {
+                led = &da850_evm_bb_leds[i];
+
+                led->gpio = gpio + DA850_EVM_BB_EXP_USER_LED2 + i;
+                led->name =
+                        da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_LED2 + i];
+        }
+}
+
+static int da850_evm_bb_expander_setup(struct i2c_client *client,
+                                                unsigned gpio, unsigned ngpio,
+                                                void *c)
+{
+        int ret;
+
+        /*
+         * Register the switches and pushbutton on the baseboard as a gpio-keys
+         * device.
+         */
+        da850_evm_bb_keys_init(gpio);
+        ret = platform_device_register(&da850_evm_bb_keys_device);
+        if (ret) {
+                pr_warning("Could not register baseboard GPIO expander keys");
+                goto io_exp_setup_sw_fail;
+        }
+
+        da850_evm_bb_leds_init(gpio);
+        ret = platform_device_register(&da850_evm_bb_leds_device);
+        if (ret) {
+                pr_warning("Could not register baseboard GPIO expander LEDS");
+                goto io_exp_setup_leds_fail;
+        }
+
+        return 0;
+
+io_exp_setup_leds_fail:
+        platform_device_unregister(&da850_evm_bb_keys_device);
+io_exp_setup_sw_fail:
+        return ret;
+}
+
+static int da850_evm_bb_expander_teardown(struct i2c_client *client,
+                                        unsigned gpio, unsigned ngpio, void *c)
+{
+        platform_device_unregister(&da850_evm_bb_leds_device);
+        platform_device_unregister(&da850_evm_bb_keys_device);
 
         return 0;
 }
@@ -340,6 +610,14 @@ static struct pca953x_platform_data da850_evm_ui_expander_info = {
         .gpio_base      = DAVINCI_N_GPIO,
         .setup          = da850_evm_ui_expander_setup,
         .teardown       = da850_evm_ui_expander_teardown,
+        .names          = da850_evm_ui_exp,
+};
+
+static struct pca953x_platform_data da850_evm_bb_expander_info = {
+        .gpio_base      = DA850_BB_EXPANDER_GPIO_BASE,
+        .setup          = da850_evm_bb_expander_setup,
+        .teardown       = da850_evm_bb_expander_teardown,
+        .names          = da850_evm_bb_exp,
 };
 
 static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
@@ -350,6 +628,10 @@ static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
                 I2C_BOARD_INFO("tca6416", 0x20),
                 .platform_data = &da850_evm_ui_expander_info,
         },
+        {
+                I2C_BOARD_INFO("tca6416", 0x21),
+                .platform_data = &da850_evm_bb_expander_info,
+        },
 };
 
 static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
@@ -540,7 +822,7 @@ static struct regulator_init_data tps65070_regulator_data[] = {
         {
                 .constraints = {
                         .min_uV = 950000,
-                        .max_uV = 1320000,
+                        .max_uV = 1350000,
                         .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
                                 REGULATOR_CHANGE_STATUS),
                         .boot_on = 1,
@@ -591,7 +873,7 @@ static struct tps6507x_board tps_board = {
         .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
 };
 
-static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
+static struct i2c_board_info __initdata da850_evm_tps65070_info[] = {
         {
                 I2C_BOARD_INFO("tps6507x", 0x48),
                 .platform_data = &tps_board,
@@ -600,8 +882,8 @@ static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
 
 static int __init pmic_tps65070_init(void)
 {
-        return i2c_register_board_info(1, da850evm_tps65070_info,
-                                        ARRAY_SIZE(da850evm_tps65070_info));
+        return i2c_register_board_info(1, da850_evm_tps65070_info,
+                                        ARRAY_SIZE(da850_evm_tps65070_info));
 }
 
 static const short da850_evm_lcdc_pins[] = {
@@ -736,6 +1018,27 @@ static struct edma_rsv_info *da850_edma_rsv[2] = {
         &da850_edma_cc1_rsv,
 };
 
+#ifdef CONFIG_CPU_FREQ
+static __init int da850_evm_init_cpufreq(void)
+{
+        switch (system_rev & 0xF) {
+        case 3:
+                da850_max_speed = 456000;
+                break;
+        case 2:
+                da850_max_speed = 408000;
+                break;
+        case 1:
+                da850_max_speed = 372000;
+                break;
+        }
+
+        return da850_register_cpufreq("pll0_sysclk3");
+}
+#else
+static __init int da850_evm_init_cpufreq(void) { return 0; }
+#endif
+
 static __init void da850_evm_init(void)
 {
         int ret;
@@ -836,7 +1139,7 @@ static __init void da850_evm_init(void)
         if (ret)
                 pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
 
-        ret = da850_register_cpufreq("pll0_sysclk3");
+        ret = da850_evm_init_cpufreq();
         if (ret)
                 pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
                                 ret);
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 01ba080433db..e4e3af179f02 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -336,7 +336,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
                 ratio--;
         }
 
-        if (ratio > PLLDIV_RATIO_MASK)
+        if (ratio > pll->div_ratio_mask)
                 return -EINVAL;
 
         do {
@@ -344,7 +344,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
         } while (v & PLLSTAT_GOSTAT);
 
         v = __raw_readl(pll->base + clk->div_reg);
-        v &= ~PLLDIV_RATIO_MASK;
+        v &= ~pll->div_ratio_mask;
         v |= ratio | PLLDIV_EN;
         __raw_writel(v, pll->base + clk->div_reg);
 
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 11099980b58b..0dd22031ec62 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -68,7 +68,7 @@
 #ifndef __ASSEMBLER__
 
 #include <linux/list.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 #define PLLSTAT_GOSTAT  BIT(0)
 #define PLLCMD_GOSET    BIT(0)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 63916b902760..78b5ae29ae40 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -830,8 +830,7 @@ static void da850_set_async3_src(int pllnum)
  * According to the TRM, minimum PLLM results in maximum power savings.
  * The OPP definitions below should keep the PLLM as low as possible.
  *
- * The output of the PLLM must be between 400 to 600 MHz.
- * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
+ * The output of the PLLM must be between 300 to 600 MHz.
  */
 struct da850_opp {
         unsigned int    freq;   /* in KHz */
@@ -842,6 +841,33 @@ struct da850_opp {
         unsigned int    cvdd_max; /* in uV */
 };
 
+static const struct da850_opp da850_opp_456 = {
+        .freq           = 456000,
+        .prediv         = 1,
+        .mult           = 19,
+        .postdiv        = 1,
+        .cvdd_min       = 1300000,
+        .cvdd_max       = 1350000,
+};
+
+static const struct da850_opp da850_opp_408 = {
+        .freq           = 408000,
+        .prediv         = 1,
+        .mult           = 17,
+        .postdiv        = 1,
+        .cvdd_min       = 1300000,
+        .cvdd_max       = 1350000,
+};
+
+static const struct da850_opp da850_opp_372 = {
+        .freq           = 372000,
+        .prediv         = 2,
+        .mult           = 31,
+        .postdiv        = 1,
+        .cvdd_min       = 1200000,
+        .cvdd_max       = 1320000,
+};
+
 static const struct da850_opp da850_opp_300 = {
         .freq           = 300000,
         .prediv         = 1,
@@ -876,6 +902,9 @@ static const struct da850_opp da850_opp_96 = {
         }
 
 static struct cpufreq_frequency_table da850_freq_table[] = {
+        OPP(456),
+        OPP(408),
+        OPP(372),
         OPP(300),
         OPP(200),
         OPP(96),
@@ -886,6 +915,19 @@ static struct cpufreq_frequency_table da850_freq_table[] = {
 };
 
 #ifdef CONFIG_REGULATOR
+static int da850_set_voltage(unsigned int index);
+static int da850_regulator_init(void);
+#endif
+
+static struct davinci_cpufreq_config cpufreq_info = {
+        .freq_table = da850_freq_table,
+#ifdef CONFIG_REGULATOR
+        .init = da850_regulator_init,
+        .set_voltage = da850_set_voltage,
+#endif
+};
+
+#ifdef CONFIG_REGULATOR
 static struct regulator *cvdd;
 
 static int da850_set_voltage(unsigned int index)
@@ -895,7 +937,7 @@ static int da850_set_voltage(unsigned int index)
         if (!cvdd)
                 return -ENODEV;
 
-        opp = (struct da850_opp *) da850_freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
 
         return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
 }
@@ -912,14 +954,6 @@ static int da850_regulator_init(void)
 }
 #endif
 
-static struct davinci_cpufreq_config cpufreq_info = {
-        .freq_table = &da850_freq_table[0],
-#ifdef CONFIG_REGULATOR
-        .init = da850_regulator_init,
-        .set_voltage = da850_set_voltage,
-#endif
-};
-
 static struct platform_device da850_cpufreq_device = {
         .name                   = "cpufreq-davinci",
         .dev = {
@@ -928,12 +962,22 @@ static struct platform_device da850_cpufreq_device = {
         .id = -1,
 };
 
+unsigned int da850_max_speed = 300000;
+
 int __init da850_register_cpufreq(char *async_clk)
 {
+        int i;
+
         /* cpufreq driver can help keep an "async" clock constant */
         if (async_clk)
                 clk_add_alias("async", da850_cpufreq_device.name,
                                                         async_clk, NULL);
+        for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
+                if (da850_freq_table[i].frequency <= da850_max_speed) {
+                        cpufreq_info.freq_table = &da850_freq_table[i];
+                        break;
+                }
+        }
 
         return platform_device_register(&da850_cpufreq_device);
 }
@@ -942,17 +986,18 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
 {
         int i, ret = 0, diff;
         unsigned int best = (unsigned int) -1;
+        struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
 
         rate /= 1000; /* convert to kHz */
 
-        for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
-                diff = da850_freq_table[i].frequency - rate;
+        for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
+                diff = table[i].frequency - rate;
                 if (diff < 0)
                         diff = -diff;
 
                 if (diff < best) {
                         best = diff;
-                        ret = da850_freq_table[i].frequency;
+                        ret = table[i].frequency;
                 }
         }
 
@@ -973,7 +1018,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         struct pll_data *pll = clk->pll_data;
         int ret;
 
-        opp = (struct da850_opp *) da850_freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
         prediv = opp->prediv;
         mult = opp->mult;
         postdiv = opp->postdiv;
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index c9a86d8130d1..85503debda51 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -344,7 +344,20 @@ static struct platform_device tsc_device = {
 
 void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
 {
-        int i;
+        int i, error;
+        struct clk *tsc_clk;
+
+        /*
+         * The reset defaults for tnetv107x tsc clock divider is set too high.
+         * This forces the clock down to a range that allows the ADC to
+         * complete sample conversion in time.
+         */
+        tsc_clk = clk_get(NULL, "sys_tsc_clk");
+        if (tsc_clk) {
+                error = clk_set_rate(tsc_clk, 5000000);
+                WARN_ON(error < 0);
+                clk_put(tsc_clk);
+        }
 
         platform_device_register(&edma_device);
         platform_device_register(&tnetv107x_wdt_device);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 2652af124acd..a5f8a80c1f28 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -412,12 +412,7 @@ static struct resource dm355_spi0_resources[] = {
 static struct davinci_spi_platform_data dm355_spi0_pdata = {
         .version        = SPI_VERSION_1,
         .num_chipselect = 2,
-        .clk_internal   = 1,
-        .cs_hold        = 1,
-        .intr_level     = 0,
-        .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
-        .c2tdelay       = 0,
-        .t2cdelay       = 0,
+        .cshold_bug     = true,
 };
 static struct platform_device dm355_spi0_device = {
         .name = "spi_davinci",
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index c466d710d3c1..02d2cc380df7 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
 static struct davinci_spi_platform_data dm365_spi0_pdata = {
         .version        = SPI_VERSION_1,
         .num_chipselect = 2,
-        .clk_internal   = 1,
-        .cs_hold        = 1,
-        .intr_level     = 0,
-        .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
-        .c2tdelay       = 0,
-        .t2cdelay       = 0,
 };
 
 static struct resource dm365_spi0_resources[] = {
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 4247b3f53b33..e7f952066527 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -28,6 +28,13 @@ extern void __iomem *da8xx_syscfg0_base;
 extern void __iomem *da8xx_syscfg1_base;
 
 /*
+ * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
+ * (than the regular 300Mhz variant), the board code should set this up
+ * with the supported speed before calling da850_register_cpufreq().
+ */
+extern unsigned int da850_max_speed;
+
+/*
  * The cp_intc interrupt controller for the da8xx isn't in the same
  * chunk of physical memory space as the other registers (like it is
  * on the davincis) so it needs to be mapped separately.  It will be
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index 62b0a90309ad..d1b954955c12 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -22,8 +22,8 @@
 #define __mem_isa(a)            (a)
 
 #ifndef __ASSEMBLER__
-#define __arch_ioremap(p, s, t) davinci_ioremap(p, s, t)
-#define __arch_iounmap(v)       davinci_iounmap(v)
+#define __arch_ioremap          davinci_ioremap
+#define __arch_iounmap          davinci_iounmap
 
 void __iomem *davinci_ioremap(unsigned long phys, size_t size,
                               unsigned int type);
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h
index 910efbf099c0..38f4da5ca135 100644
--- a/arch/arm/mach-davinci/include/mach/spi.h
+++ b/arch/arm/mach-davinci/include/mach/spi.h
@@ -19,26 +19,66 @@
 #ifndef __ARCH_ARM_DAVINCI_SPI_H
 #define __ARCH_ARM_DAVINCI_SPI_H
 
+#define SPI_INTERN_CS   0xFF
+
 enum {
         SPI_VERSION_1, /* For DM355/DM365/DM6467 */
         SPI_VERSION_2, /* For DA8xx */
 };
 
+/**
+ * davinci_spi_platform_data - Platform data for SPI master device on DaVinci
+ *
+ * @version:    version of the SPI IP. Different DaVinci devices have slightly
+ *              varying versions of the same IP.
+ * @num_chipselect: number of chipselects supported by this SPI master
+ * @intr_line:  interrupt line used to connect the SPI IP to the ARM interrupt
+ *              controller withn the SoC. Possible values are 0 and 1.
+ * @chip_sel:   list of GPIOs which can act as chip-selects for the SPI.
+ *              SPI_INTERN_CS denotes internal SPI chip-select. Not necessary
+ *              to populate if all chip-selects are internal.
+ * @cshold_bug: set this to true if the SPI controller on your chip requires
+ *              a write to CSHOLD bit in between transfers (like in DM355).
+ */
 struct davinci_spi_platform_data {
         u8      version;
         u8      num_chipselect;
+        u8      intr_line;
+        u8      *chip_sel;
+        bool    cshold_bug;
+};
+
+/**
+ * davinci_spi_config - Per-chip-select configuration for SPI slave devices
+ *
+ * @wdelay:     amount of delay between transmissions. Measured in number of
+ *              SPI module clocks.
+ * @odd_parity: polarity of parity flag at the end of transmit data stream.
+ *              0 - odd parity, 1 - even parity.
+ * @parity_enable: enable transmission of parity at end of each transmit
+ *              data stream.
+ * @io_type:    type of IO transfer. Choose between polled, interrupt and DMA.
+ * @timer_disable: disable chip-select timers (setup and hold)
+ * @c2tdelay:   chip-select setup time. Measured in number of SPI module clocks.
+ * @t2cdelay:   chip-select hold time. Measured in number of SPI module clocks.
+ * @t2edelay:   transmit data finished to SPI ENAn pin inactive time. Measured
+ *              in number of SPI clocks.
+ * @c2edelay:   chip-select active to SPI ENAn signal active time. Measured in
+ *              number of SPI clocks.
+ */
+struct davinci_spi_config {
         u8      wdelay;
         u8      odd_parity;
         u8      parity_enable;
-        u8      wait_enable;
+#define SPI_IO_TYPE_INTR        0
+#define SPI_IO_TYPE_POLL        1
+#define SPI_IO_TYPE_DMA         2
+        u8      io_type;
         u8      timer_disable;
-        u8      clk_internal;
-        u8      cs_hold;
-        u8      intr_level;
-        u8      poll_mode;
-        u8      use_dma;
         u8      c2tdelay;
         u8      t2cdelay;
+        u8      t2edelay;
+        u8      c2edelay;
 };
 
 #endif  /* __ARCH_ARM_DAVINCI_SPI_H */
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 1b15dbd0a77b..a41580400701 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -83,21 +83,16 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
                 pdctl1 = __raw_readl(psc_base + PDCTL1);
                 pdctl1 |= 0x100;
                 __raw_writel(pdctl1, psc_base + PDCTL1);
-
-                do {
-                        ptstat = __raw_readl(psc_base +
-                                               PTSTAT);
-                } while (!(((ptstat >> domain) & 1) == 0));
         } else {
                 ptcmd = 1 << domain;
                 __raw_writel(ptcmd, psc_base + PTCMD);
-
-                do {
-                        ptstat = __raw_readl(psc_base + PTSTAT);
-                } while (!(((ptstat >> domain) & 1) == 0));
         }
 
         do {
+                ptstat = __raw_readl(psc_base + PTSTAT);
+        } while (!(((ptstat >> domain) & 1) == 0));
+
+        do {
                 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
         } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
 
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 0f21c36e65dd..e1969ce904dc 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -272,15 +272,35 @@ static cycle_t read_cycles(struct clocksource *cs)
         return (cycles_t)timer32_read(t);
 }
 
+/*
+ * Kernel assumes that sched_clock can be called early but may not have
+ * things ready yet.
+ */
+static cycle_t read_dummy(struct clocksource *cs)
+{
+        return 0;
+}
+
+
 static struct clocksource clocksource_davinci = {
         .rating         = 300,
-        .read           = read_cycles,
+        .read           = read_dummy,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 24,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
 /*
+ * Overwrite weak default sched_clock with something more precise
+ */
+unsigned long long notrace sched_clock(void)
+{
+        const cycle_t cyc = clocksource_davinci.read(&clocksource_davinci);
+
+        return clocksource_cyc2ns(cyc, clocksource_davinci.mult,
+                                clocksource_davinci.shift);
+}
+
+/*
  * clockevent
  */
 static int davinci_set_next_event(unsigned long cycles,
@@ -377,11 +397,10 @@ static void __init davinci_timer_init(void)
         davinci_clock_tick_rate = clk_get_rate(timer_clk);
 
         /* setup clocksource */
+        clocksource_davinci.read = read_cycles;
         clocksource_davinci.name = id_to_name[clocksource_id];
-        clocksource_davinci.mult =
-                clocksource_khz2mult(davinci_clock_tick_rate/1000,
-                                     clocksource_davinci.shift);
-        if (clocksource_register(&clocksource_davinci))
+        if (clocksource_register_hz(&clocksource_davinci,
+                                    davinci_clock_tick_rate))
                 printk(err, clocksource_davinci.name);
 
         /* setup clockevent */
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index daeae06430b9..6fcdecec8d8c 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -131,12 +131,13 @@ define_pll_clk(tdm, 1, 0x0ff, 0x200);
 define_pll_clk(eth, 2, 0x0ff, 0x400);
 
 /* Level 2 - divided outputs from the PLLs */
-#define define_pll_div_clk(pll, cname, div)             \
-        static struct clk pll##_##cname##_clk = {       \
-                .name           = #pll "_" #cname "_clk",\
-                .parent         = &pll_##pll##_clk,     \
-                .flags          = CLK_PLL,              \
-                .div_reg        = PLLDIV##div,          \
+#define define_pll_div_clk(pll, cname, div)                     \
+        static struct clk pll##_##cname##_clk = {               \
+                .name           = #pll "_" #cname "_clk",       \
+                .parent         = &pll_##pll##_clk,             \
+                .flags          = CLK_PLL,                      \
+                .div_reg        = PLLDIV##div,                  \
+                .set_rate       = davinci_set_sysclk_rate,      \
         }
 
 define_pll_div_clk(sys, arm1176,        1);
@@ -192,6 +193,7 @@ lpsc_clk_enabled(system,	sys_half_clk,	SYSTEM);
 lpsc_clk_enabled(ddr2_vrst,     sys_ddr_clk,    DDR2_EMIF1_VRST);
 lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk,    DDR2_EMIF2_VCTL_RST);
 lpsc_clk_enabled(wdt_arm,       sys_half_clk,   WDT_ARM);
+lpsc_clk_enabled(timer1,        sys_half_clk,   TIMER1);
 
 lpsc_clk(mbx_lite,      sys_arm1176_clk,        MBX_LITE);
 lpsc_clk(ethss,         eth_125mhz_clk,         ETHSS);
@@ -205,16 +207,15 @@ lpsc_clk(mdio,		sys_half_clk,		MDIO);
 lpsc_clk(sdio0,         sys_half_clk,           SDIO0);
 lpsc_clk(sdio1,         sys_half_clk,           SDIO1);
 lpsc_clk(timer0,        sys_half_clk,           TIMER0);
-lpsc_clk(timer1,        sys_half_clk,           TIMER1);
 lpsc_clk(wdt_dsp,       sys_half_clk,           WDT_DSP);
 lpsc_clk(ssp,           sys_half_clk,           SSP);
 lpsc_clk(tdm0,          tdm_0_clk,              TDM0);
 lpsc_clk(tdm1,          tdm_1_clk,              TDM1);
 lpsc_clk(vlynq,         sys_vlynq_ref_clk,      VLYNQ);
 lpsc_clk(mcdma,         sys_half_clk,           MCDMA);
-lpsc_clk(usb0,          sys_half_clk,           USB0);
-lpsc_clk(usb1,          sys_half_clk,           USB1);
 lpsc_clk(usbss,         sys_half_clk,           USBSS);
+lpsc_clk(usb0,          clk_usbss,              USB0);
+lpsc_clk(usb1,          clk_usbss,              USB1);
 lpsc_clk(ethss_rgmii,   eth_250mhz_clk,         ETHSS_RGMII);
 lpsc_clk(imcop,         sys_dsp_clk,            IMCOP);
 lpsc_clk(spare,         sys_half_clk,           SPARE);
@@ -281,7 +282,9 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "clk_tdm0",             &clk_tdm0),
         CLK(NULL,               "clk_vlynq",            &clk_vlynq),
         CLK(NULL,               "clk_mcdma",            &clk_mcdma),
+        CLK(NULL,               "clk_usbss",            &clk_usbss),
         CLK(NULL,               "clk_usb0",             &clk_usb0),
+        CLK(NULL,               "clk_usb1",             &clk_usb1),
         CLK(NULL,               "clk_tdm1",             &clk_tdm1),
         CLK(NULL,               "clk_debugss",          &clk_debugss),
         CLK(NULL,               "clk_ethss_rgmii",      &clk_ethss_rgmii),
@@ -289,8 +292,6 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "clk_imcop",            &clk_imcop),
         CLK(NULL,               "clk_spare",            &clk_spare),
         CLK("davinci_mmc.1",    NULL,                   &clk_sdio1),
-        CLK(NULL,               "clk_usb1",             &clk_usb1),
-        CLK(NULL,               "clk_usbss",            &clk_usbss),
         CLK(NULL,               "clk_ddr2_vrst",        &clk_ddr2_vrst),
         CLK(NULL,               "clk_ddr2_vctl_rst",    &clk_ddr2_vctl_rst),
         CLK(NULL,               NULL,                   NULL),
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 31f0cbea0caa..23d2b6d9fa63 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -64,17 +64,19 @@ static struct resource usb_resources[] = {
         {
                 .start          = IRQ_USBINT,
                 .flags          = IORESOURCE_IRQ,
+                .name           = "mc"
         },
         {
                 /* placeholder for the dedicated CPPI IRQ */
                 .flags          = IORESOURCE_IRQ,
+                .name           = "dma"
         },
 };
 
 static u64 usb_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device usb_dev = {
-        .name           = "musb_hdrc",
+        .name           = "musb-davinci",
         .id             = -1,
         .dev = {
                 .platform_data          = &usb_data,
@@ -110,6 +112,7 @@ static struct resource da8xx_usb20_resources[] = {
         {
                 .start          = IRQ_DA8XX_USB_INT,
                 .flags          = IORESOURCE_IRQ,
+                .name           = "mc",
         },
 };
 
@@ -121,6 +124,7 @@ int __init da8xx_register_usb20(unsigned mA, unsigned potpgt)
 
         usb_dev.resource = da8xx_usb20_resources;
         usb_dev.num_resources = ARRAY_SIZE(da8xx_usb20_resources);
+        usb_dev.name = "musb-da8xx";
 
         return platform_device_register(&usb_dev);
 }
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 3b9a32ace909..a4ed3900912a 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -9,6 +9,12 @@ config MACH_DOVE_DB
           Say 'Y' here if you want your kernel to support the
           Marvell DB-MV88AP510 Development Board.
 
+ config MACH_CM_A510
+        bool "CompuLab CM-A510 Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          CompuLab CM-A510 Board.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 7ab3be53f642..fa0f01856060 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,3 +1,4 @@
-obj-y                           += common.o addr-map.o irq.o pcie.o
+obj-y                           += common.o addr-map.o irq.o pcie.o mpp.o
 
 obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
+obj-$(CONFIG_MACH_CM_A510)      += cm-a510.o
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
new file mode 100644
index 000000000000..96e0e94e5fa9
--- /dev/null
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -0,0 +1,95 @@
+/*
+ * arch/arm/mach-dove/cm-a510.c
+ *
+ * Copyright (C) 2010 CompuLab, Ltd.
+ * Konstantin Sinyuk <kostyas@compulab.co.il>
+ *
+ * Based on Marvell DB-MV88AP510-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/dove.h>
+
+#include "common.h"
+
+static struct mv643xx_eth_platform_data cm_a510_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+
+static struct mv_sata_platform_data cm_a510_sata_data = {
+        .n_ports        = 1,
+};
+
+/*
+ * SPI Devices:
+ * SPI0: 1M Flash Winbond w25q32bv
+ */
+static const struct flash_platform_data cm_a510_spi_flash_data = {
+        .type           = "w25q32bv",
+};
+
+static struct spi_board_info __initdata cm_a510_spi_flash_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &cm_a510_spi_flash_data,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+static int __init cm_a510_pci_init(void)
+{
+        if (machine_is_cm_a510())
+                dove_pcie_init(1, 1);
+
+        return 0;
+}
+
+subsys_initcall(cm_a510_pci_init);
+
+/* Board Init */
+static void __init cm_a510_init(void)
+{
+        /*
+         * Basic Dove setup. Needs to be called early.
+         */
+        dove_init();
+
+        dove_ge00_init(&cm_a510_ge00_data);
+        dove_ehci0_init();
+        dove_ehci1_init();
+        dove_sata_init(&cm_a510_sata_data);
+        dove_sdio0_init();
+        dove_sdio1_init();
+        dove_spi0_init();
+        dove_spi1_init();
+        dove_uart0_init();
+        dove_uart1_init();
+        dove_i2c_init();
+        spi_register_board_info(cm_a510_spi_flash_info,
+                                ARRAY_SIZE(cm_a510_spi_flash_info));
+}
+
+MACHINE_START(CM_A510, "Compulab CM-A510 Board")
+        .boot_params    = 0x00000100,
+        .init_machine   = cm_a510_init,
+        .map_io         = dove_map_io,
+        .init_irq       = dove_init_irq,
+        .timer          = &dove_timer,
+MACHINE_END
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index f7a12586a1f5..fe627aba6da7 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -770,7 +770,7 @@ static struct resource dove_sdio0_resources[] = {
 };
 
 static struct platform_device dove_sdio0 = {
-        .name           = "sdhci-mv",
+        .name           = "sdhci-dove",
         .id             = 0,
         .dev            = {
                 .dma_mask               = &sdio_dmamask,
@@ -798,7 +798,7 @@ static struct resource dove_sdio1_resources[] = {
 };
 
 static struct platform_device dove_sdio1 = {
-        .name           = "sdhci-mv",
+        .name           = "sdhci-dove",
         .id             = 1,
         .dev            = {
                 .dma_mask               = &sdio_dmamask,
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index f6a08397f046..27b414578f2e 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -131,14 +131,21 @@
 #define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
 #define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
 #define DOVE_GPIO_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
 #define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
 #define  DOVE_NAND_GPIO_EN              (1 << 0)
 #define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_VIRT_BASE + 0x40)
-
+#define  DOVE_SPI_GPIO_SEL              (1 << 5)
+#define  DOVE_UART1_GPIO_SEL            (1 << 4)
+#define  DOVE_AU1_GPIO_SEL              (1 << 3)
+#define  DOVE_CAM_GPIO_SEL              (1 << 2)
+#define  DOVE_SD1_GPIO_SEL              (1 << 1)
+#define  DOVE_SD0_GPIO_SEL              (1 << 0)
 
 /* Power Management */
 #define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
+#define DOVE_PMU_SIG_CTRL       (DOVE_PMU_VIRT_BASE + 0x802c)
 
 /* Real Time Clock */
 #define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
index 0ee70ff39e11..340bb7af529d 100644
--- a/arch/arm/mach-dove/include/mach/gpio.h
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -14,12 +14,14 @@
 #include <plat/gpio.h>
 #include <asm-generic/gpio.h>           /* cansleep wrappers */
 
-#define GPIO_MAX        64
+#define GPIO_MAX        72
 
 #define GPIO_BASE_LO            (DOVE_GPIO_VIRT_BASE + 0x00)
 #define GPIO_BASE_HI            (DOVE_GPIO_VIRT_BASE + 0x20)
 
-#define GPIO_BASE(pin)          ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI)
+#define GPIO_BASE(pin)          ((pin < 32) ? GPIO_BASE_LO :            \
+                                 ((pin < 64) ? GPIO_BASE_HI :           \
+                                  DOVE_GPIO2_VIRT_BASE))
 
 #define GPIO_OUT(pin)           (GPIO_BASE(pin) + 0x00)
 #define GPIO_IO_CONF(pin)       (GPIO_BASE(pin) + 0x04)
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
new file mode 100644
index 000000000000..71db2bdf2f28
--- /dev/null
+++ b/arch/arm/mach-dove/mpp.c
@@ -0,0 +1,212 @@
+/*
+ * arch/arm/mach-dove/mpp.c
+ *
+ * MPP functions for Marvell Dove SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <mach/dove.h>
+
+#include "mpp.h"
+
+#define MPP_NR_REGS 4
+#define MPP_CTRL(i)     ((i) == 3 ?                             \
+                         DOVE_MPP_CTRL4_VIRT_BASE :             \
+                         DOVE_MPP_VIRT_BASE + (i) * 4)
+#define PMU_SIG_REGS 2
+#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
+
+struct dove_mpp_grp {
+        int start;
+        int end;
+};
+
+static struct dove_mpp_grp dove_mpp_grp[] = {
+        [MPP_24_39] = {
+                .start  = 24,
+                .end    = 39,
+        },
+        [MPP_40_45] = {
+                .start  = 40,
+                .end    = 45,
+        },
+        [MPP_46_51] = {
+                .start  = 40,
+                .end    = 45,
+        },
+        [MPP_58_61] = {
+                .start  = 58,
+                .end    = 61,
+        },
+        [MPP_62_63] = {
+                .start  = 62,
+                .end    = 63,
+        },
+};
+
+static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
+{
+        int i;
+
+        for (i = start; i <= end; i++)
+                orion_gpio_set_valid(i, gpio_mode);
+}
+
+static void dove_mpp_dump_regs(void)
+{
+#ifdef DEBUG
+        int i;
+
+        pr_debug("MPP_CTRL regs:");
+        for (i = 0; i < MPP_NR_REGS; i++)
+                printk(" %08x", readl(MPP_CTRL(i)));
+        printk("\n");
+
+        pr_debug("PMU_SIG_CTRL regs:");
+        for (i = 0; i < PMU_SIG_REGS; i++)
+                printk(" %08x", readl(PMU_SIG_CTRL(i)));
+        printk("\n");
+
+        pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
+        pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
+#endif
+}
+
+static void dove_mpp_cfg_nfc(int sel)
+{
+        u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+        mpp_gen_cfg &= ~0x1;
+        mpp_gen_cfg |= sel;
+        writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
+
+        dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
+}
+
+static void dove_mpp_cfg_au1(int sel)
+{
+        u32 mpp_ctrl4           = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
+        u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+        u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+        mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL);
+        ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1);
+        mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN);
+        global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO);
+
+        if (!sel || sel == 0x2)
+                dove_mpp_gpio_mode(52, 57, 0);
+        else
+                dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
+
+        if (sel & 0x1) {
+                global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO;
+                dove_mpp_gpio_mode(56, 57, 0);
+        }
+        if (sel & 0x2) {
+                mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN;
+                dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
+        }
+        if (sel & 0x4) {
+                ssp_ctrl1 |= DOVE_SSP_ON_AU1;
+                dove_mpp_gpio_mode(52, 55, 0);
+        }
+        if (sel & 0x8)
+                mpp_ctrl4 |= DOVE_AU1_GPIO_SEL;
+
+        writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
+        writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
+        writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
+        writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
+}
+
+static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
+{
+        int start = dove_mpp_grp[num].start;
+        int end = dove_mpp_grp[num].end;
+        int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
+
+        *mpp_ctrl &= ~(0x1 << num);
+        *mpp_ctrl |= sel << num;
+
+        dove_mpp_gpio_mode(start, end, gpio_mode);
+}
+
+void __init dove_mpp_conf(unsigned int *mpp_list)
+{
+        u32 mpp_ctrl[MPP_NR_REGS];
+        u32 pmu_mpp_ctrl = 0;
+        u32 pmu_sig_ctrl[PMU_SIG_REGS];
+        int i;
+
+        /* Initialize gpiolib. */
+        orion_gpio_init();
+
+        for (i = 0; i < MPP_NR_REGS; i++)
+                mpp_ctrl[i] = readl(MPP_CTRL(i));
+
+        for (i = 0; i < PMU_SIG_REGS; i++)
+                pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
+
+        pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+        dove_mpp_dump_regs();
+
+        for ( ; *mpp_list != MPP_END; mpp_list++) {
+                unsigned int num = MPP_NUM(*mpp_list);
+                unsigned int sel = MPP_SEL(*mpp_list);
+                int shift, gpio_mode;
+
+                if (num > MPP_MAX) {
+                        pr_err("dove: invalid MPP number (%u)\n", num);
+                        continue;
+                }
+
+                if (*mpp_list & MPP_NFC_MASK) {
+                        dove_mpp_cfg_nfc(sel);
+                        continue;
+                }
+
+                if (*mpp_list & MPP_AU1_MASK) {
+                        dove_mpp_cfg_au1(sel);
+                        continue;
+                }
+
+                if (*mpp_list & MPP_GRP_MASK) {
+                        dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
+                        continue;
+                }
+
+                shift = (num & 7) << 2;
+                if (*mpp_list & MPP_PMU_MASK) {
+                        pmu_mpp_ctrl |= (0x1 << num);
+                        pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
+                        pmu_sig_ctrl[num / 8] |= 0xf << shift;
+                        gpio_mode = 0;
+                } else {
+                        mpp_ctrl[num / 8] &= ~(0xf << shift);
+                        mpp_ctrl[num / 8] |= sel << shift;
+                        gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
+                }
+
+                orion_gpio_set_valid(num, gpio_mode);
+        }
+
+        for (i = 0; i < MPP_NR_REGS; i++)
+                writel(mpp_ctrl[i], MPP_CTRL(i));
+
+        for (i = 0; i < PMU_SIG_REGS; i++)
+                writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
+
+        writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
+
+        dove_mpp_dump_regs();
+}
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
new file mode 100644
index 000000000000..2a43ce413b15
--- /dev/null
+++ b/arch/arm/mach-dove/mpp.h
@@ -0,0 +1,220 @@
+#ifndef __ARCH_DOVE_MPP_CODED_H
+#define __ARCH_DOVE_MPP_CODED_H
+
+#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) (      \
+/* MPP/group number */          ((_num) & 0xff) |               \
+/* MPP select value */          (((_mode) & 0xf) << 8) |        \
+/* MPP PMU */                   ((!!(_pmu)) << 12) |            \
+/* group flag */                ((!!(_grp)) << 13) |            \
+/* AU1 flag */                  ((!!(_au1)) << 14) |            \
+/* NFCE flag */                 ((!!(_nfc)) << 15))
+
+#define MPP_MAX 71
+
+#define MPP_NUM(x)    ((x) & 0xff)
+#define MPP_SEL(x)    (((x) >> 8) & 0xf)
+
+#define MPP_PMU_MASK            MPP(0, 0x0, 1, 0, 0, 0)
+#define MPP_GRP_MASK            MPP(0, 0x0, 0, 1, 0, 0)
+#define MPP_AU1_MASK            MPP(0, 0x0, 0, 0, 1, 0)
+#define MPP_NFC_MASK            MPP(0, 0x0, 0, 0, 0, 1)
+
+#define MPP_END                 MPP(0xff, 0xf, 1, 1, 1, 1)
+
+#define MPP_PMU_DRIVE_0         0x1
+#define MPP_PMU_DRIVE_1         0x2
+#define MPP_PMU_SDI             0x3
+#define MPP_PMU_CPU_PWRDWN      0x4
+#define MPP_PMU_STBY_PWRDWN     0x5
+#define MPP_PMU_CORE_PWR_GOOD   0x8
+#define MPP_PMU_BAT_FAULT       0xa
+#define MPP_PMU_EXT0_WU         0xb
+#define MPP_PMU_EXT1_WU         0xc
+#define MPP_PMU_EXT2_WU         0xd
+#define MPP_PMU_BLINK           0xe
+#define MPP_PMU(_num, _mode)    MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
+
+#define MPP_PIN(_num, _mode)    MPP((_num), (_mode), 0, 0, 0, 0)
+#define MPP_GRP(_grp, _mode)    MPP((_grp), (_mode), 0, 1, 0, 0)
+#define MPP_GRP_AU1(_mode)      MPP(0, (_mode), 0, 0, 1, 0)
+#define MPP_GRP_NFC(_mode)      MPP(0, (_mode), 0, 0, 0, 1)
+
+#define MPP0_GPIO0              MPP_PIN(0, 0x0)
+#define MPP0_UA2_RTSn           MPP_PIN(0, 0x2)
+#define MPP0_SDIO0_CD           MPP_PIN(0, 0x3)
+#define MPP0_LCD0_PWM           MPP_PIN(0, 0xf)
+
+#define MPP1_GPIO1              MPP_PIN(1, 0x0)
+#define MPP1_UA2_CTSn           MPP_PIN(1, 0x2)
+#define MPP1_SDIO0_WP           MPP_PIN(1, 0x3)
+#define MPP1_LCD1_PWM           MPP_PIN(1, 0xf)
+
+#define MPP2_GPIO2              MPP_PIN(2, 0x0)
+#define MPP2_SATA_PRESENT       MPP_PIN(2, 0x1)
+#define MPP2_UA2_TXD            MPP_PIN(2, 0x2)
+#define MPP2_SDIO0_BUS_POWER    MPP_PIN(2, 0x3)
+#define MPP2_UA_RTSn1           MPP_PIN(2, 0x4)
+
+#define MPP3_GPIO3              MPP_PIN(3, 0x0)
+#define MPP3_SATA_ACT           MPP_PIN(3, 0x1)
+#define MPP3_UA2_RXD            MPP_PIN(3, 0x2)
+#define MPP3_SDIO0_LED_CTRL     MPP_PIN(3, 0x3)
+#define MPP3_UA_CTSn1           MPP_PIN(3, 0x4)
+#define MPP3_SPI_LCD_CS1        MPP_PIN(3, 0xf)
+
+#define MPP4_GPIO4              MPP_PIN(4, 0x0)
+#define MPP4_UA3_RTSn           MPP_PIN(4, 0x2)
+#define MPP4_SDIO1_CD           MPP_PIN(4, 0x3)
+#define MPP4_SPI_1_MISO         MPP_PIN(4, 0x4)
+
+#define MPP5_GPIO5              MPP_PIN(5, 0x0)
+#define MPP5_UA3_CTSn           MPP_PIN(5, 0x2)
+#define MPP5_SDIO1_WP           MPP_PIN(5, 0x3)
+#define MPP5_SPI_1_CS           MPP_PIN(5, 0x4)
+
+#define MPP6_GPIO6              MPP_PIN(6, 0x0)
+#define MPP6_UA3_TXD            MPP_PIN(6, 0x2)
+#define MPP6_SDIO1_BUS_POWER    MPP_PIN(6, 0x3)
+#define MPP6_SPI_1_MOSI         MPP_PIN(6, 0x4)
+
+#define MPP7_GPIO7              MPP_PIN(7, 0x0)
+#define MPP7_UA3_RXD            MPP_PIN(7, 0x2)
+#define MPP7_SDIO1_LED_CTRL     MPP_PIN(7, 0x3)
+#define MPP7_SPI_1_SCK          MPP_PIN(7, 0x4)
+
+#define MPP8_GPIO8              MPP_PIN(8, 0x0)
+#define MPP8_WD_RST_OUT         MPP_PIN(8, 0x1)
+
+#define MPP9_GPIO9              MPP_PIN(9, 0x0)
+#define MPP9_PEX1_CLKREQn       MPP_PIN(9, 0x5)
+
+#define MPP10_GPIO10            MPP_PIN(10, 0x0)
+#define MPP10_SSP_SCLK          MPP_PIN(10, 0x5)
+
+#define MPP11_GPIO11            MPP_PIN(11, 0x0)
+#define MPP11_SATA_PRESENT      MPP_PIN(11, 0x1)
+#define MPP11_SATA_ACT          MPP_PIN(11, 0x2)
+#define MPP11_SDIO0_LED_CTRL    MPP_PIN(11, 0x3)
+#define MPP11_SDIO1_LED_CTRL    MPP_PIN(11, 0x4)
+#define MPP11_PEX0_CLKREQn      MPP_PIN(11, 0x5)
+
+#define MPP12_GPIO12            MPP_PIN(12, 0x0)
+#define MPP12_SATA_ACT          MPP_PIN(12, 0x1)
+#define MPP12_UA2_RTSn          MPP_PIN(12, 0x2)
+#define MPP12_AD0_I2S_EXT_MCLK  MPP_PIN(12, 0x3)
+#define MPP12_SDIO1_CD          MPP_PIN(12, 0x4)
+
+#define MPP13_GPIO13            MPP_PIN(13, 0x0)
+#define MPP13_UA2_CTSn          MPP_PIN(13, 0x2)
+#define MPP13_AD1_I2S_EXT_MCLK  MPP_PIN(13, 0x3)
+#define MPP13_SDIO1WP           MPP_PIN(13, 0x4)
+#define MPP13_SSP_EXTCLK        MPP_PIN(13, 0x5)
+
+#define MPP14_GPIO14            MPP_PIN(14, 0x0)
+#define MPP14_UA2_TXD           MPP_PIN(14, 0x2)
+#define MPP14_SDIO1_BUS_POWER   MPP_PIN(14, 0x4)
+#define MPP14_SSP_RXD           MPP_PIN(14, 0x5)
+
+#define MPP15_GPIO15            MPP_PIN(15, 0x0)
+#define MPP15_UA2_RXD           MPP_PIN(15, 0x2)
+#define MPP15_SDIO1_LED_CTRL    MPP_PIN(15, 0x4)
+#define MPP15_SSP_SFRM          MPP_PIN(15, 0x5)
+
+#define MPP16_GPIO16            MPP_PIN(16, 0x0)
+#define MPP16_UA3_RTSn          MPP_PIN(16, 0x2)
+#define MPP16_SDIO0_CD          MPP_PIN(16, 0x3)
+#define MPP16_SPI_LCD_CS1       MPP_PIN(16, 0x4)
+#define MPP16_AC97_SDATA_IN1    MPP_PIN(16, 0x5)
+
+#define MPP17_GPIO17            MPP_PIN(17, 0x0)
+#define MPP17_AC97_SYSCLK_OUT   MPP_PIN(17, 0x1)
+#define MPP17_UA3_CTSn          MPP_PIN(17, 0x2)
+#define MPP17_SDIO0_WP          MPP_PIN(17, 0x3)
+#define MPP17_TW_SDA2           MPP_PIN(17, 0x4)
+#define MPP17_AC97_SDATA_IN2    MPP_PIN(17, 0x5)
+
+#define MPP18_GPIO18            MPP_PIN(18, 0x0)
+#define MPP18_UA3_TXD           MPP_PIN(18, 0x2)
+#define MPP18_SDIO0_BUS_POWER   MPP_PIN(18, 0x3)
+#define MPP18_LCD0_PWM          MPP_PIN(18, 0x4)
+#define MPP18_AC_SDATA_IN3      MPP_PIN(18, 0x5)
+
+#define MPP19_GPIO19            MPP_PIN(19, 0x0)
+#define MPP19_UA3_RXD           MPP_PIN(19, 0x2)
+#define MPP19_SDIO0_LED_CTRL    MPP_PIN(19, 0x3)
+#define MPP19_TW_SCK2           MPP_PIN(19, 0x4)
+
+#define MPP20_GPIO20            MPP_PIN(20, 0x0)
+#define MPP20_AC97_SYSCLK_OUT   MPP_PIN(20, 0x1)
+#define MPP20_SPI_LCD_MISO      MPP_PIN(20, 0x2)
+#define MPP20_SDIO1_CD          MPP_PIN(20, 0x3)
+#define MPP20_SDIO0_CD          MPP_PIN(20, 0x5)
+#define MPP20_SPI_1_MISO        MPP_PIN(20, 0x6)
+
+#define MPP21_GPIO21            MPP_PIN(21, 0x0)
+#define MPP21_UA1_RTSn          MPP_PIN(21, 0x1)
+#define MPP21_SPI_LCD_CS0       MPP_PIN(21, 0x2)
+#define MPP21_SDIO1_WP          MPP_PIN(21, 0x3)
+#define MPP21_SSP_SFRM          MPP_PIN(21, 0x4)
+#define MPP21_SDIO0_WP          MPP_PIN(21, 0x5)
+#define MPP21_SPI_1_CS          MPP_PIN(21, 0x6)
+
+#define MPP22_GPIO22            MPP_PIN(22, 0x0)
+#define MPP22_UA1_CTSn          MPP_PIN(22, 0x1)
+#define MPP22_SPI_LCD_MOSI      MPP_PIN(22, 0x2)
+#define MPP22_SDIO1_BUS_POWER   MPP_PIN(22, 0x3)
+#define MPP22_SSP_TXD           MPP_PIN(22, 0x4)
+#define MPP22_SDIO0_BUS_POWER   MPP_PIN(22, 0x5)
+#define MPP22_SPI_1_MOSI        MPP_PIN(22, 0x6)
+
+#define MPP23_GPIO23            MPP_PIN(23, 0x0)
+#define MPP23_SPI_LCD_SCK       MPP_PIN(23, 0x2)
+#define MPP23_SDIO1_LED_CTRL    MPP_PIN(23, 0x3)
+#define MPP23_SSP_SCLK          MPP_PIN(23, 0x4)
+#define MPP23_SDIO0_LED_CTRL    MPP_PIN(23, 0x5)
+#define MPP23_SPI_1_SCK         MPP_PIN(23, 0x6)
+
+/* for MPP groups _num is a group index */
+enum dove_mpp_grp_idx {
+        MPP_24_39 = 2,
+        MPP_40_45 = 0,
+        MPP_46_51 = 1,
+        MPP_58_61 = 5,
+        MPP_62_63 = 4,
+};
+
+#define MPP24_39_GPIO           MPP_GRP(MPP_24_39, 0x1)
+#define MPP24_39_CAM            MPP_GRP(MPP_24_39, 0x0)
+
+#define MPP40_45_GPIO           MPP_GRP(MPP_40_45, 0x1)
+#define MPP40_45_SD0            MPP_GRP(MPP_40_45, 0x0)
+
+#define MPP46_51_GPIO           MPP_GRP(MPP_46_51, 0x1)
+#define MPP46_51_SD1            MPP_GRP(MPP_46_51, 0x0)
+
+#define MPP58_61_GPIO           MPP_GRP(MPP_58_61, 0x1)
+#define MPP58_61_SPI            MPP_GRP(MPP_58_61, 0x0)
+
+#define MPP62_63_GPIO           MPP_GRP(MPP_62_63, 0x1)
+#define MPP62_63_UA1            MPP_GRP(MPP_62_63, 0x0)
+
+/* The MPP[64:71] control differs from other groups */
+#define MPP64_71_GPO            MPP_GRP_NFC(0x1)
+#define MPP64_71_NFC            MPP_GRP_NFC(0x0)
+
+/*
+ * The MPP[52:57] functionality is encoded by 4 bits in different
+ * registers. The _num field in this case encodes those bits in
+ * correspodence with Table 135 of 88AP510 Functional specification
+ */
+#define MPP52_57_AU1            MPP_GRP_AU1(0x0)
+#define MPP52_57_AU1_GPIO57     MPP_GRP_AU1(0x2)
+#define MPP52_57_GPIO           MPP_GRP_AU1(0xa)
+#define MPP52_57_TW_GPIO        MPP_GRP_AU1(0xb)
+#define MPP52_57_AU1_SSP        MPP_GRP_AU1(0xc)
+#define MPP52_57_SSP_GPIO       MPP_GRP_AU1(0xe)
+#define MPP52_57_SSP_TW         MPP_GRP_AU1(0xf)
+
+void dove_mpp_conf(unsigned int *mpp_list);
+
+#endif  /* __ARCH_DOVE_MPP_CODED_H */
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index ef06c66a6f16..ca4de7105097 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -19,10 +19,10 @@
 #include <linux/string.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+#include <linux/clkdev.h>
 
 #include <mach/hardware.h>
 
-#include <asm/clkdev.h>
 #include <asm/div64.h>
 
 
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 197f9e241cff..17d2e608a214 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,13 +1,37 @@
 config IMX_HAVE_DMA_V1
         bool
 
-if ARCH_MX1
-
 config SOC_IMX1
+        bool
         select CPU_ARM920T
         select IMX_HAVE_DMA_V1
         select IMX_HAVE_IOMUX_V1
+        select MXC_AVIC
+
+config SOC_IMX21
+        bool
+        select CPU_ARM926T
+        select ARCH_MXC_AUDMUX_V1
+        select IMX_HAVE_DMA_V1
+        select IMX_HAVE_IOMUX_V1
+        select MXC_AVIC
+
+config SOC_IMX25
         bool
+        select CPU_ARM926T
+        select ARCH_MXC_AUDMUX_V2
+        select ARCH_MXC_IOMUX_V3
+        select MXC_AVIC
+
+config SOC_IMX27
+        bool
+        select CPU_ARM926T
+        select ARCH_MXC_AUDMUX_V1
+        select IMX_HAVE_DMA_V1
+        select IMX_HAVE_IOMUX_V1
+        select MXC_AVIC
+
+if ARCH_MX1
 
 comment "MX1 platforms:"
 config MACH_MXLADS
@@ -31,33 +55,17 @@ endif
 
 if ARCH_MX2
 
-config SOC_IMX21
-        select CPU_ARM926T
-        select ARCH_MXC_AUDMUX_V1
-        select IMX_HAVE_DMA_V1
-        select IMX_HAVE_IOMUX_V1
-        bool
-
-config SOC_IMX27
-        select CPU_ARM926T
-        select ARCH_MXC_AUDMUX_V1
-        select IMX_HAVE_DMA_V1
-        select IMX_HAVE_IOMUX_V1
-        bool
-
 choice
         prompt "CPUs:"
         default MACH_MX21
 
 config MACH_MX21
         bool "i.MX21 support"
-        select SOC_IMX21
         help
           This enables support for Freescale's MX2 based i.MX21 processor.
 
 config MACH_MX27
         bool "i.MX27 support"
-        select SOC_IMX27
         help
           This enables support for Freescale's MX2 based i.MX27 processor.
 
@@ -71,7 +79,10 @@ comment "MX21 platforms:"
 
 config MACH_MX21ADS
         bool "MX21ADS platform"
+        select SOC_IMX21
+        select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
         help
           Include support for MX21ADS platform. This includes specific
@@ -79,24 +90,79 @@ config MACH_MX21ADS
 
 endif
 
+if ARCH_MX25
+
+comment "MX25 platforms:"
+
+config MACH_MX25_3DS
+        bool "Support MX25PDK (3DS) Platform"
+        select SOC_IMX25
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMXDI_RTC
+        select IMX_HAVE_PLATFORM_IMX_FB
+        select IMX_HAVE_PLATFORM_IMX_KEYPAD
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+
+config MACH_EUKREA_CPUIMX25
+        bool "Support Eukrea CPUIMX25 Platform"
+        select SOC_IMX25
+        select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMXDI_RTC
+        select IMX_HAVE_PLATFORM_IMX_FB
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        select MXC_ULPI if USB_ULPI
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX25
+        default MACH_EUKREA_MBIMXSD25_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD25_BASEBOARD
+        bool "Eukrea MBIMXSD development board"
+        select IMX_HAVE_PLATFORM_IMX_SSI
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMXSD evaluation board.
+
+endchoice
+
+endif
+
 if MACH_MX27
 
 comment "MX27 platforms:"
 
 config MACH_MX27ADS
         bool "MX27ADS platform"
+        select SOC_IMX27
+        select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_MXC_W1
         help
           Include support for MX27ADS platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_PCM038
         bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
+        select SOC_IMX27
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_MXC_W1
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
@@ -109,8 +175,9 @@ choice
         default MACH_PCM970_BASEBOARD
 
 config MACH_PCM970_BASEBOARD
-        prompt "PHYTEC PCM970 development board"
-        bool
+        bool "PHYTEC PCM970 development board"
+        select IMX_HAVE_PLATFORM_IMX_FB
+        select IMX_HAVE_PLATFORM_MXC_MMC
         help
           This adds board specific devices that can be found on Phytec's
           PCM970 evaluation board.
@@ -119,9 +186,14 @@ endchoice
 
 config MACH_CPUIMX27
         bool "Eukrea CPUIMX27 module"
+        select SOC_IMX27
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_MXC_W1
         select MXC_ULPI if USB_ULPI
         help
           Include support for Eukrea CPUIMX27 platform. This includes
@@ -130,6 +202,7 @@ config MACH_CPUIMX27
 config MACH_EUKREA_CPUIMX27_USESDHC2
         bool "CPUIMX27 integrates SDHC2 module"
         depends on MACH_CPUIMX27
+        select IMX_HAVE_PLATFORM_MXC_MMC
         help
           This adds support for the internal SDHC2 used on CPUIMX27
           for wifi or eMMC.
@@ -148,8 +221,11 @@ choice
 
 config MACH_EUKREA_MBIMX27_BASEBOARD
         bool "Eukrea MBIMX27 development board"
+        select IMX_HAVE_PLATFORM_IMX_FB
+        select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
         help
           This adds board specific devices that can be found on Eukrea's
@@ -159,15 +235,26 @@ endchoice
 
 config MACH_MX27_3DS
         bool "MX27PDK platform"
+        select SOC_IMX27
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
+        select IMX_HAVE_PLATFORM_SPI_IMX
+        select MXC_ULPI if USB_ULPI
         help
           Include support for MX27PDK platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_IMX27_VISSTRIM_M10
         bool "Vista Silicon i.MX27 Visstrim_m10"
+        select SOC_IMX27
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_MMC
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         help
           Include support for Visstrim_m10 platform and its different variants.
           This includes specific configurations for the board and its
@@ -175,6 +262,7 @@ config MACH_IMX27_VISSTRIM_M10
 
 config MACH_IMX27LITE
         bool "LogicPD MX27 LITEKIT platform"
+        select SOC_IMX27
         select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for MX27 LITEKIT platform. This includes specific
@@ -182,10 +270,17 @@ config MACH_IMX27LITE
 
 config MACH_PCA100
         bool "Phytec phyCARD-s (pca100)"
+        select SOC_IMX27
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_MXC_W1
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
@@ -194,8 +289,11 @@ config MACH_PCA100
 
 config MACH_MXT_TD60
         bool "Maxtrack i-MXT TD60"
+        select SOC_IMX27
+        select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
         help
           Include support for i-MXT (aka td60) platform. This
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5582692bb176..77100bf26153 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,13 +4,13 @@
 
 # Object file lists.
 
-obj-y   :=  devices.o
-
 obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 
 obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
 obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
 
+obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o
+
 obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
 obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
 
@@ -22,6 +22,10 @@ obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
 
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
 
+obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
+
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 7988a85cf07d..3953d60bff0b 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -6,6 +6,10 @@ zreladdr-$(CONFIG_MACH_MX21)	:= 0xC0008000
 params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
 initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
 
+zreladdr-$(CONFIG_ARCH_MX25)    := 0x80008000
+params_phys-$(CONFIG_ARCH_MX25) := 0x80000100
+initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000
+
 zreladdr-$(CONFIG_MACH_MX27)    := 0xA0008000
 params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
 initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
index daca30b2d5b1..3938a563b280 100644
--- a/arch/arm/mach-imx/clock-imx1.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -22,8 +22,7 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 #include <mach/clock.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c
index cf15ea516a72..bf30a8c7ce6f 100644
--- a/arch/arm/mach-imx/clock-imx21.c
+++ b/arch/arm/mach-imx/clock-imx21.c
@@ -21,11 +21,11 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/clkdev.h>
 
 #include <mach/clock.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <asm/clkdev.h>
 #include <asm/div64.h>
 
 #define IO_ADDR_CCM(off)        (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
@@ -1185,7 +1185,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "brom", brom_clk)
         _REGISTER_CLOCK(NULL, "emma", emma_clk[0])
         _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
-        _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
         _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
         _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-imx/clock-imx25.c
index 9e4a5578c2fb..daa0165b6772 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -21,8 +21,7 @@
 #include <linux/list.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 #include <mach/clock.h>
 #include <mach/hardware.h>
@@ -296,7 +295,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
         _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-        _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 98a25bada783..583f2515c1d5 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -21,8 +21,8 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
 #include <asm/div64.h>
 
 #include <mach/clock.h>
@@ -125,7 +125,7 @@ static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
         if (clk->parent == parent)
                 return 0;
 
-        if (mx27_revision() >= CHIP_REV_2_0) {
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                 if (parent == &mpll_main1_clk) {
                         cscr |= CCM_CSCR_ARM_SRC;
                 } else {
@@ -174,7 +174,7 @@ static int set_rate_cpu(struct clk *clk, unsigned long rate)
         div--;
 
         reg = __raw_readl(CCM_CSCR);
-        if (mx27_revision() >= CHIP_REV_2_0) {
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                 reg &= ~(3 << 12);
                 reg |= div << 12;
                 reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
@@ -244,7 +244,7 @@ static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
 
         parent_rate = clk_get_rate(clk->parent);
 
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 pdf += 4;  /* MX27 TO2+ */
         else
                 pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
@@ -269,7 +269,7 @@ static unsigned long get_rate_nfc(struct clk *clk)
 
         parent_rate = clk_get_rate(clk->parent);
 
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
         else
                 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
@@ -284,7 +284,7 @@ static unsigned long get_rate_vpu(struct clk *clk)
 
         parent_rate = clk_get_rate(clk->parent);
 
-        if (mx27_revision() >= CHIP_REV_2_0) {
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
                 vpu_pdf += 4;
         } else {
@@ -347,7 +347,7 @@ static unsigned long get_rate_mpll_main(struct clk *clk)
          * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
          * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
          */
-        if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)
                 return 2UL * parent_rate / 3UL;
 
         return parent_rate;
@@ -365,7 +365,7 @@ static unsigned long get_rate_spll(struct clk *clk)
         /* On TO2 we have to write the value back. Otherwise we
          * read 0 from this register the next time.
          */
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 __raw_writel(reg, CCM_SPCTL0);
 
         return mxc_decode_pll(reg, rate);
@@ -376,7 +376,7 @@ static unsigned long get_rate_cpu(struct clk *clk)
         u32 div;
         unsigned long rate;
 
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
         else
                 div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
@@ -389,7 +389,7 @@ static unsigned long get_rate_ahb(struct clk *clk)
 {
         unsigned long rate, bclk_pdf;
 
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
         else
                 bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
@@ -402,7 +402,7 @@ static unsigned long get_rate_ipg(struct clk *clk)
 {
         unsigned long rate, ipg_pdf;
 
-        if (mx27_revision() >= CHIP_REV_2_0)
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                 return clk_get_rate(clk->parent);
         else
                 ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
@@ -667,7 +667,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
         _REGISTER_CLOCK(NULL, "ata", ata_clk)
         _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
-        _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
         _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
@@ -683,7 +683,7 @@ static void __init to2_adjust_clocks(void)
 {
         unsigned long cscr = __raw_readl(CCM_CSCR);
 
-        if (mx27_revision() >= CHIP_REV_2_0) {
+        if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                 if (cscr & CCM_CSCR_ARM_SRC)
                         cpu_clk.parent = &mpll_main1_clk;
 
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index d8d3b2d84dc5..3b117be37bd2 100644
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -42,7 +42,19 @@ static void query_silicon_parameter(void)
         val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
                                 + SYS_CHIP_ID));
 
-        cpu_silicon_rev = (int)(val >> 28);
+        switch (val >> 28) {
+        case 0:
+                cpu_silicon_rev = IMX_CHIP_REVISION_1_0;
+                break;
+        case 1:
+                cpu_silicon_rev = IMX_CHIP_REVISION_2_0;
+                break;
+        case 2:
+                cpu_silicon_rev = IMX_CHIP_REVISION_2_1;
+                break;
+        default:
+                cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN;
+        }
         cpu_partnumber = (int)((val >> 12) & 0xFFFF);
 }
 
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index d189039749b0..16744d2d9b81 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -9,10 +9,26 @@
 #include <mach/mx21.h>
 #include <mach/devices-common.h>
 
+extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst;
+#define imx21_add_imx21_hcd(pdata)      \
+        imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
+
+extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst;
+#define imx21_add_imx2_wdt(pdata)       \
+        imx_add_imx2_wdt(&imx21_imx2_wdt_data)
+
+extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst;
+#define imx21_add_imx_fb(pdata) \
+        imx_add_imx_fb(&imx21_imx_fb_data, pdata)
+
 extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
 #define imx21_add_imx_i2c(pdata)        \
         imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
 
+extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst;
+#define imx21_add_imx_keypad(pdata)     \
+        imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
+
 extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
 #define imx21_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
@@ -25,10 +41,18 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
 #define imx21_add_imx_uart2(pdata)      imx21_add_imx_uart(2, pdata)
 #define imx21_add_imx_uart3(pdata)      imx21_add_imx_uart(3, pdata)
 
+extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst;
+#define imx21_add_mxc_mmc(id, pdata)    \
+        imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
+
 extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
 #define imx21_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
 
+extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst;
+#define imx21_add_mxc_w1(pdata) \
+        imx_add_mxc_w1(&imx21_mxc_w1_data)
+
 extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
 #define imx21_add_cspi(id, pdata)       \
         imx_add_spi_imx(&imx21_cspi_data[id], pdata)
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index d94d282fa676..bde33caf1b90 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -13,10 +13,27 @@ extern const struct imx_fec_data imx25_fec_data __initconst;
 #define imx25_add_fec(pdata)    \
         imx_add_fec(&imx25_fec_data, pdata)
 
-#define imx25_add_flexcan0(pdata)       \
-        imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
-#define imx25_add_flexcan1(pdata)       \
-        imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
+extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst;
+#define imx25_add_flexcan(id, pdata)    \
+        imx_add_flexcan(&imx25_flexcan_data[id], pdata)
+#define imx25_add_flexcan0(pdata)       imx25_add_flexcan(0, pdata)
+#define imx25_add_flexcan1(pdata)       imx25_add_flexcan(1, pdata)
+
+extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst;
+#define imx25_add_fsl_usb2_udc(pdata)   \
+        imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
+
+extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst;
+#define imx25_add_imxdi_rtc(pdata)      \
+        imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
+
+extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst;
+#define imx25_add_imx2_wdt(pdata)       \
+        imx_add_imx2_wdt(&imx25_imx2_wdt_data)
+
+extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst;
+#define imx25_add_imx_fb(pdata) \
+        imx_add_imx_fb(&imx25_imx_fb_data, pdata)
 
 extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
 #define imx25_add_imx_i2c(id, pdata)    \
@@ -25,6 +42,10 @@ extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
 #define imx25_add_imx_i2c1(pdata)       imx25_add_imx_i2c(1, pdata)
 #define imx25_add_imx_i2c2(pdata)       imx25_add_imx_i2c(2, pdata)
 
+extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst;
+#define imx25_add_imx_keypad(pdata)     \
+        imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
+
 extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
 #define imx25_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
@@ -38,17 +59,29 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
 #define imx25_add_imx_uart3(pdata)      imx25_add_imx_uart(3, pdata)
 #define imx25_add_imx_uart4(pdata)      imx25_add_imx_uart(4, pdata)
 
+extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst;
+#define imx25_add_mx2_camera(pdata)     \
+        imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
+
+extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst;
+#define imx25_add_mxc_ehci_otg(pdata)   \
+        imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
+extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst;
+#define imx25_add_mxc_ehci_hs(pdata)    \
+        imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
+
 extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
 #define imx25_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
 
+extern const struct imx_sdhci_esdhc_imx_data
+imx25_sdhci_esdhc_imx_data[] __initconst;
+#define imx25_add_sdhci_esdhc_imx(id, pdata)    \
+        imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
+
 extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
 #define imx25_add_spi_imx(id, pdata)    \
-        imx_add_spi_imx(&imx25_cspi_data[id], pdata)
+        imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
 #define imx25_add_spi_imx0(pdata)       imx25_add_spi_imx(0, pdata)
 #define imx25_add_spi_imx1(pdata)       imx25_add_spi_imx(1, pdata)
 #define imx25_add_spi_imx2(pdata)       imx25_add_spi_imx(2, pdata)
-
-extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst;
-#define imx25_add_esdhc(id, pdata)      \
-        imx_add_esdhc(&imx25_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 7011690364f2..f1272d4b5a33 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -13,10 +13,26 @@ extern const struct imx_fec_data imx27_fec_data __initconst;
 #define imx27_add_fec(pdata)    \
         imx_add_fec(&imx27_fec_data, pdata)
 
+extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst;
+#define imx27_add_fsl_usb2_udc(pdata)   \
+        imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
+
+extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst;
+#define imx27_add_imx2_wdt(pdata)       \
+        imx_add_imx2_wdt(&imx27_imx2_wdt_data)
+
+extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst;
+#define imx27_add_imx_fb(pdata) \
+        imx_add_imx_fb(&imx27_imx_fb_data, pdata)
+
 extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
 #define imx27_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
 
+extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst;
+#define imx27_add_imx_keypad(pdata)     \
+        imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
+
 extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
 #define imx27_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
@@ -31,10 +47,29 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
 #define imx27_add_imx_uart4(pdata)      imx27_add_imx_uart(4, pdata)
 #define imx27_add_imx_uart5(pdata)      imx27_add_imx_uart(5, pdata)
 
+extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst;
+#define imx27_add_mx2_camera(pdata)     \
+        imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
+
+extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst;
+#define imx27_add_mxc_ehci_otg(pdata)   \
+        imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
+extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst;
+#define imx27_add_mxc_ehci_hs(id, pdata)        \
+        imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
+
+extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst;
+#define imx27_add_mxc_mmc(id, pdata)    \
+        imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
+
 extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
 #define imx27_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
 
+extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst;
+#define imx27_add_mxc_w1(pdata) \
+        imx_add_mxc_w1(&imx27_mxc_w1_data)
+
 extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
 #define imx27_add_cspi(id, pdata)       \
         imx_add_spi_imx(&imx27_cspi_data[id], pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
deleted file mode 100644
index fba5047de8b1..000000000000
--- a/arch/arm/mach-imx/devices.c
+++ /dev/null
@@ -1,553 +0,0 @@
-/*
- * Author: MontaVista Software, Inc.
- *       <source@mvista.com>
- *
- * Based on the OMAP devices.c
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/dma-mapping.h>
-#include <linux/serial.h>
-
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/mmc.h>
-
-#include "devices.h"
-
-#if defined(CONFIG_ARCH_MX1)
-static struct resource imx1_camera_resources[] = {
-        {
-                .start  = 0x00224000,
-                .end    = 0x00224010,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX1_CSI_INT,
-                .end    = MX1_CSI_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device imx1_camera_device = {
-        .name           = "mx1-camera",
-        .id             = 0, /* This is used to put cameras on this interface */
-        .dev            = {
-                .dma_mask = &imx1_camera_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-        .resource       = imx1_camera_resources,
-        .num_resources  = ARRAY_SIZE(imx1_camera_resources),
-};
-
-static struct resource imx_rtc_resources[] = {
-        {
-                .start  = 0x00204000,
-                .end    = 0x00204024,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX1_RTC_INT,
-                .end    = MX1_RTC_INT,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = MX1_RTC_SAMINT,
-                .end    = MX1_RTC_SAMINT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_rtc_device = {
-        .name           = "rtc-imx",
-        .id             = 0,
-        .resource       = imx_rtc_resources,
-        .num_resources  = ARRAY_SIZE(imx_rtc_resources),
-};
-
-static struct resource imx_wdt_resources[] = {
-        {
-                .start  = 0x00201000,
-                .end    = 0x00201008,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX1_WDT_INT,
-                .end    = MX1_WDT_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_wdt_device = {
-        .name           = "imx-wdt",
-        .id             = 0,
-        .resource       = imx_wdt_resources,
-        .num_resources  = ARRAY_SIZE(imx_wdt_resources),
-};
-
-static struct resource imx_usb_resources[] = {
-        {
-                .start  = 0x00212000,
-                .end    = 0x00212148,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MX1_USBD_INT0,
-                .end    = MX1_USBD_INT0,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = MX1_USBD_INT1,
-                .end    = MX1_USBD_INT1,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = MX1_USBD_INT2,
-                .end    = MX1_USBD_INT2,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = MX1_USBD_INT3,
-                .end    = MX1_USBD_INT3,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = MX1_USBD_INT4,
-                .end    = MX1_USBD_INT4,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = MX1_USBD_INT5,
-                .end    = MX1_USBD_INT5,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = MX1_USBD_INT6,
-                .end    = MX1_USBD_INT6,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_usb_device = {
-        .name           = "imx_udc",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(imx_usb_resources),
-        .resource       = imx_usb_resources,
-};
-
-/* GPIO port description */
-static struct mxc_gpio_port imx_gpio_ports[] = {
-        {
-                .chip.label = "gpio-0",
-                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
-                .irq = MX1_GPIO_INT_PORTA,
-                .virtual_irq_start = MXC_GPIO_IRQ_START,
-        }, {
-                .chip.label = "gpio-1",
-                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
-                .irq = MX1_GPIO_INT_PORTB,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        }, {
-                .chip.label = "gpio-2",
-                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
-                .irq = MX1_GPIO_INT_PORTC,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-        }, {
-                .chip.label = "gpio-3",
-                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
-                .irq = MX1_GPIO_INT_PORTD,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
-        }
-};
-
-int __init imx1_register_gpios(void)
-{
-        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
-}
-#endif
-
-#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
-
-#ifdef CONFIG_MACH_MX27
-static struct resource mx27_camera_resources[] = {
-        {
-               .start = MX27_CSI_BASE_ADDR,
-               .end = MX27_CSI_BASE_ADDR + 0x1f,
-               .flags = IORESOURCE_MEM,
-        }, {
-               .start = MX27_EMMA_PRP_BASE_ADDR,
-               .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
-               .flags = IORESOURCE_MEM,
-        }, {
-               .start = MX27_INT_CSI,
-               .end = MX27_INT_CSI,
-               .flags = IORESOURCE_IRQ,
-        },{
-               .start = MX27_INT_EMMAPRP,
-               .end = MX27_INT_EMMAPRP,
-               .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device mx27_camera_device = {
-        .name = "mx2-camera",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mx27_camera_resources),
-        .resource = mx27_camera_resources,
-        .dev = {
-                .coherent_dma_mask = 0xffffffff,
-        },
-};
-#endif
-
-/*
- * General Purpose Timer
- * - i.MX21: 3 timers
- * - i.MX27: 6 timers
- */
-#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq)                         \
-        static struct resource timer ## n ##_resources[] = {            \
-                {                                                       \
-                        .start = baseaddr,                              \
-                        .end = baseaddr + SZ_4K - 1,                    \
-                        .flags = IORESOURCE_MEM,                        \
-                }, {                                                    \
-                        .start = irq,                                   \
-                        .end = irq,                                     \
-                        .flags = IORESOURCE_IRQ,                        \
-                }                                                       \
-        };                                                              \
-                                                                        \
-        struct platform_device mxc_gpt ## n = {                         \
-                .name = "imx_gpt",                                      \
-                .id = n,                                                \
-                .num_resources = ARRAY_SIZE(timer ## n ## _resources),  \
-                .resource = timer ## n ## _resources,                   \
-        }
-
-/* We use gpt1 as system timer, so do not add a device for this one */
-DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
-DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
-DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
-DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
-#endif
-
-/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
-static struct resource mxc_wdt_resources[] = {
-        {
-                .start = MX2x_WDOG_BASE_ADDR,
-                .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device mxc_wdt = {
-        .name = "imx2-wdt",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_wdt_resources),
-        .resource = mxc_wdt_resources,
-};
-
-static struct resource mxc_w1_master_resources[] = {
-        {
-                .start = MX2x_OWIRE_BASE_ADDR,
-                .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device mxc_w1_master_device = {
-        .name = "mxc_w1",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
-        .resource = mxc_w1_master_resources,
-};
-
-/*
- * lcdc:
- * - i.MX1: the basic controller
- * - i.MX21: to be checked
- * - i.MX27: like i.MX1, with slightly variations
- */
-static struct resource mxc_fb[] = {
-        {
-                .start = MX2x_LCDC_BASE_ADDR,
-                .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX2x_INT_LCDC,
-                .end = MX2x_INT_LCDC,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-
-/* mxc lcd driver */
-struct platform_device mxc_fb_device = {
-        .name = "imx-fb",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_fb),
-        .resource = mxc_fb,
-        .dev = {
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-static struct resource mxc_pwm_resources[] = {
-        {
-                .start = MX2x_PWM_BASE_ADDR,
-                .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX2x_INT_PWM,
-                .end = MX2x_INT_PWM,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_pwm_device = {
-        .name = "mxc_pwm",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_pwm_resources),
-        .resource = mxc_pwm_resources,
-};
-
-#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq)                 \
-        static struct resource mxc_sdhc_resources ## n[] = {            \
-                {                                                       \
-                        .start = baseaddr,                              \
-                        .end = baseaddr + SZ_4K - 1,                    \
-                        .flags = IORESOURCE_MEM,                        \
-                }, {                                                    \
-                        .start = irq,                                   \
-                        .end = irq,                                     \
-                        .flags = IORESOURCE_IRQ,                        \
-                }, {                                                    \
-                        .start = dmareq,                                \
-                        .end = dmareq,                                  \
-                        .flags = IORESOURCE_DMA,                        \
-                },                                                      \
-        };                                                              \
-                                                                        \
-        static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32);        \
-                                                                        \
-        struct platform_device mxc_sdhc_device ## n = {                 \
-                .name = "mxc-mmc",                                      \
-                .id = n,                                                \
-                .dev = {                                                \
-                        .dma_mask = &mxc_sdhc ## n ## _dmamask,         \
-                        .coherent_dma_mask = DMA_BIT_MASK(32),          \
-                },                                                      \
-                .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n),   \
-                .resource = mxc_sdhc_resources ## n,            \
-        }
-
-DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
-DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
-
-#ifdef CONFIG_MACH_MX27
-static struct resource otg_resources[] = {
-        {
-                .start = MX27_USBOTG_BASE_ADDR,
-                .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX27_INT_USB3,
-                .end = MX27_INT_USB3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static u64 otg_dmamask = DMA_BIT_MASK(32);
-
-/* OTG gadget device */
-struct platform_device mxc_otg_udc_device = {
-        .name           = "fsl-usb2-udc",
-        .id             = -1,
-        .dev            = {
-                .dma_mask               = &otg_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = otg_resources,
-        .num_resources  = ARRAY_SIZE(otg_resources),
-};
-
-/* OTG host */
-struct platform_device mxc_otg_host = {
-        .name = "mxc-ehci",
-        .id = 0,
-        .dev = {
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .dma_mask = &otg_dmamask,
-        },
-        .resource = otg_resources,
-        .num_resources = ARRAY_SIZE(otg_resources),
-};
-
-/* USB host 1 */
-
-static u64 usbh1_dmamask = DMA_BIT_MASK(32);
-
-static struct resource mxc_usbh1_resources[] = {
-        {
-                .start = MX27_USBOTG_BASE_ADDR + 0x200,
-                .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX27_INT_USB1,
-                .end = MX27_INT_USB1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_usbh1 = {
-        .name = "mxc-ehci",
-        .id = 1,
-        .dev = {
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .dma_mask = &usbh1_dmamask,
-        },
-        .resource = mxc_usbh1_resources,
-        .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
-};
-
-/* USB host 2 */
-static u64 usbh2_dmamask = DMA_BIT_MASK(32);
-
-static struct resource mxc_usbh2_resources[] = {
-        {
-                .start = MX27_USBOTG_BASE_ADDR + 0x400,
-                .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX27_INT_USB2,
-                .end = MX27_INT_USB2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_usbh2 = {
-        .name = "mxc-ehci",
-        .id = 2,
-        .dev = {
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .dma_mask = &usbh2_dmamask,
-        },
-        .resource = mxc_usbh2_resources,
-        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
-};
-#endif
-
-/* GPIO port description */
-#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq)                          \
-        {                                                               \
-                .chip.label = "gpio-" #n,                               \
-                .irq = _irq,                                            \
-                .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR +        \
-                                n * 0x100),                             \
-                .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32,       \
-        }
-
-#define DEFINE_MXC_GPIO_PORT(SOC, n)                                    \
-        {                                                               \
-                .chip.label = "gpio-" #n,                               \
-                .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR +        \
-                                n * 0x100),                             \
-                .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32,       \
-        }
-
-#define DEFINE_MXC_GPIO_PORTS(SOC, pfx)                                 \
-        static struct mxc_gpio_port pfx ## _gpio_ports[] = {            \
-                DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO),     \
-                DEFINE_MXC_GPIO_PORT(SOC, 1),                           \
-                DEFINE_MXC_GPIO_PORT(SOC, 2),                           \
-                DEFINE_MXC_GPIO_PORT(SOC, 3),                           \
-                DEFINE_MXC_GPIO_PORT(SOC, 4),                           \
-                DEFINE_MXC_GPIO_PORT(SOC, 5),                           \
-        }
-
-#ifdef CONFIG_MACH_MX21
-DEFINE_MXC_GPIO_PORTS(MX21, imx21);
-
-int __init imx21_register_gpios(void)
-{
-        return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
-}
-#endif
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_MXC_GPIO_PORTS(MX27, imx27);
-
-int __init imx27_register_gpios(void)
-{
-        return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
-}
-#endif
-
-#ifdef CONFIG_MACH_MX21
-static struct resource mx21_usbhc_resources[] = {
-        {
-                .start  = MX21_USBOTG_BASE_ADDR,
-                .end    = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start          = MX21_INT_USBHOST,
-                .end            = MX21_INT_USBHOST,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mx21_usbhc_device = {
-        .name           = "imx21-hcd",
-        .id             = 0,
-        .dev            = {
-                .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-        .num_resources  = ARRAY_SIZE(mx21_usbhc_resources),
-        .resource       = mx21_usbhc_resources,
-};
-#endif
-
-static struct resource imx_kpp_resources[] = {
-        {
-                .start  = MX2x_KPP_BASE_ADDR,
-                .end    = MX2x_KPP_BASE_ADDR + 0xf,
-                .flags  = IORESOURCE_MEM
-        }, {
-                .start  = MX2x_INT_KPP,
-                .end    = MX2x_INT_KPP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_kpp_device = {
-        .name = "imx-keypad",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(imx_kpp_resources),
-        .resource = imx_kpp_resources,
-};
-
-#endif
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
deleted file mode 100644
index 807f02a031c9..000000000000
--- a/arch/arm/mach-imx/devices.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifdef CONFIG_ARCH_MX1
-extern struct platform_device imx1_camera_device;
-extern struct platform_device imx_rtc_device;
-extern struct platform_device imx_wdt_device;
-extern struct platform_device imx_usb_device;
-#endif
-
-#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
-extern struct platform_device mxc_gpt1;
-extern struct platform_device mxc_gpt2;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_gpt3;
-extern struct platform_device mxc_gpt4;
-extern struct platform_device mxc_gpt5;
-#endif
-extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_w1_master_device;
-extern struct platform_device mxc_fb_device;
-extern struct platform_device mxc_pwm_device;
-extern struct platform_device mxc_sdhc_device0;
-extern struct platform_device mxc_sdhc_device1;
-extern struct platform_device mxc_otg_udc_device;
-extern struct platform_device mx27_camera_device;
-extern struct platform_device mxc_otg_host;
-extern struct platform_device mxc_usbh1;
-extern struct platform_device mxc_usbh2;
-extern struct platform_device mx21_usbhc_device;
-extern struct platform_device imx_kpp_device;
-#endif
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index 3e8c47c63bac..e9f1769b49f5 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -818,9 +818,11 @@ static int __init imx_dma_init(void)
                 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
         else
 #endif
-                BUG();
+                return 0;
 
         dma_clk = clk_get(NULL, "dma");
+        if (IS_ERR(dma_clk))
+                return PTR_ERR(dma_clk);
         clk_enable(dma_clk);
 
         /* reset DMA module */
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 7e1e9dc2c8fc..275c8589d797 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -26,20 +26,16 @@
 #include <linux/spi/ads7846.h>
 #include <linux/backlight.h>
 #include <video/platform_lcd.h>
-#include <linux/input/matrix_keypad.h>
 
 #include <asm/mach/arch.h>
 
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
-#include <mach/imxfb.h>
 #include <mach/hardware.h>
-#include <mach/mmc.h>
 #include <mach/spi.h>
 #include <mach/audmux.h>
 
 #include "devices-imx27.h"
-#include "devices.h"
 
 static const int eukrea_mbimx27_pins[] __initconst = {
         /* UART2 */
@@ -111,7 +107,8 @@ static const uint32_t eukrea_mbimx27_keymap[] = {
         KEY(1, 1, KEY_LEFT),
 };
 
-static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
+static const struct matrix_keymap_data
+eukrea_mbimx27_keymap_data __initconst = {
         .keymap         = eukrea_mbimx27_keymap,
         .keymap_size    = ARRAY_SIZE(eukrea_mbimx27_keymap),
 };
@@ -196,7 +193,7 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
         },
 };
 
-static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
+static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = {
         .mode = eukrea_mbimx27_modes,
         .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
 
@@ -300,7 +297,7 @@ static struct platform_device *platform_devices[] __initdata = {
         &leds_gpio,
 };
 
-static struct imxmmc_platform_data sdhc_pdata = {
+static const struct imxmmc_platform_data sdhc_pdata __initconst = {
         .dat3_card_detect = 1,
 };
 
@@ -345,8 +342,8 @@ void __init eukrea_mbimx27_baseboard_init(void)
         imx27_add_imx_uart3(&uart_pdata);
 #endif
 
-        mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
-        mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
+        imx27_add_imx_fb(&eukrea_mbimx27_fb_data);
+        imx27_add_mxc_mmc(0, &sdhc_pdata);
 
         i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
                                 ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
@@ -380,7 +377,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
         gpio_request(GPIO_PORTA | 25, "lcd_enable");
         platform_device_register(&eukrea_mbimx27_lcd_powerdev);
 
-        mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
+        imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index e765ac5d9a08..cb705c28de02 100644
--- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -33,13 +33,11 @@
 #include <asm/mach/arch.h>
 #include <mach/mx25.h>
 #include <mach/imx-uart.h>
-#include <mach/imxfb.h>
 #include <mach/audmux.h>
 
 #include "devices-imx25.h"
-#include "devices.h"
 
-static struct pad_desc eukrea_mbimxsd_pads[] = {
+static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
         /* LCD */
         MX25_PAD_LD0__LD0,
         MX25_PAD_LD1__LD1,
@@ -151,7 +149,7 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
         },
 };
 
-static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
+static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = {
         .mode           = eukrea_mximxsd_modes,
         .num_modes      = ARRAY_SIZE(eukrea_mximxsd_modes),
         .pwmr           = 0x00A903FF,
@@ -273,11 +271,11 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
 #endif
 
         imx25_add_imx_uart1(&uart_pdata);
-        mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
+        imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
         imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
 
         imx25_add_flexcan1(NULL);
-        imx25_add_esdhc(0, NULL);
+        imx25_add_sdhci_esdhc_imx(0, NULL);
 
         gpio_request(GPIO_LED1, "LED1");
         gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 745ee60fb068..6cf04da2456a 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -28,7 +28,6 @@
 #include <linux/serial_8250.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <linux/fsl_devices.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -40,11 +39,9 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx27.h"
-#include "devices.h"
 
 static const int eukrea_cpuimx27_pins[] __initconst = {
         /* UART1 */
@@ -157,8 +154,6 @@ cpuimx27_nand_board_info __initconst = {
 
 static struct platform_device *platform_devices[] __initdata = {
         &eukrea_cpuimx27_nor_mtd_device,
-        &mxc_wdt,
-        &mxc_w1_master_device,
 };
 
 static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
@@ -215,18 +210,18 @@ static struct platform_device serial_device = {
 #endif
 
 #if defined(CONFIG_USB_ULPI)
-static struct mxc_usbh_platform_data otg_pdata = {
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
-static struct mxc_usbh_platform_data usbh2_pdata = {
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 #endif
 
-static struct fsl_usb2_platform_data otg_device_pdata = {
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
@@ -262,10 +257,12 @@ static void __init eukrea_cpuimx27_init(void)
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx27_add_imx2_wdt(NULL);
+        imx27_add_mxc_w1(NULL);
 
 #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
         /* SDHC2 can be used for Wifi */
-        mxc_register_device(&mxc_sdhc_device1, NULL);
+        imx27_add_mxc_mmc(1, NULL);
 #endif
 #if defined(MACH_EUKREA_CPUIMX27_USEUART4)
         /* in which case UART4 is also used for Bluetooth */
@@ -281,16 +278,16 @@ static void __init eukrea_cpuimx27_init(void)
                 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-                mxc_register_device(&mxc_otg_host, &otg_pdata);
+                imx27_add_mxc_ehci_otg(&otg_pdata);
         }
 
         usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+        imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
 #endif
         if (!otg_mode_host)
-                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+                imx27_add_fsl_usb2_udc(&otg_device_pdata);
 
 #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
         eukrea_mbimx27_baseboard_init();
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index f6f9ad60c25e..eb395aba9237 100644
--- a/arch/arm/mach-mx25/mach-cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -26,7 +26,6 @@
 #include <linux/platform_device.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <linux/fsl_devices.h>
 
 #include <mach/eukrea-baseboards.h>
 #include <mach/hardware.h>
@@ -39,17 +38,15 @@
 #include <mach/mx25.h>
 #include <mach/mxc_nand.h>
 #include <mach/imxfb.h>
-#include <mach/mxc_ehci.h>
 #include <mach/iomux-mx25.h>
 
 #include "devices-imx25.h"
-#include "devices.h"
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct pad_desc eukrea_cpuimx25_pads[] = {
+static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
         /* FEC - RMII */
         MX25_PAD_FEC_MDC__FEC_MDC,
         MX25_PAD_FEC_MDIO__FEC_MDIO,
@@ -87,18 +84,18 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
         },
 };
 
-static struct mxc_usbh_platform_data otg_pdata = {
+static const struct mxc_usbh_platform_data otg_pdata __initconst = {
         .portsc = MXC_EHCI_MODE_UTMI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
-static struct mxc_usbh_platform_data usbh2_pdata = {
+static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
         .portsc = MXC_EHCI_MODE_SERIAL,
         .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
                   MXC_EHCI_IPPUE_DOWN,
 };
 
-static struct fsl_usb2_platform_data otg_device_pdata = {
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI,
 };
@@ -126,7 +123,7 @@ static void __init eukrea_cpuimx25_init(void)
 
         imx25_add_imx_uart0(&uart_pdata);
         imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
-        mxc_register_device(&mx25_rtc_device, NULL);
+        imx25_add_imxdi_rtc(NULL);
         imx25_add_fec(&mx25_fec_pdata);
 
         i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
@@ -134,11 +131,11 @@ static void __init eukrea_cpuimx25_init(void)
         imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
 
         if (otg_mode_host)
-                mxc_register_device(&mxc_otg, &otg_pdata);
+                imx25_add_mxc_ehci_otg(&otg_pdata);
         else
-                mxc_register_device(&otg_udc_device, &otg_device_pdata);
+                imx25_add_fsl_usb2_udc(&otg_device_pdata);
 
-        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+        imx25_add_mxc_ehci_hs(&usbh2_pdata);
 
 #ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
         eukrea_mbimxsd25_baseboard_init();
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 59716fab586d..40a3666ea632 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -34,12 +34,9 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
-#include <mach/mmc.h>
 #include <mach/iomux.h>
-#include <mach/mxc_ehci.h>
 
 #include "devices-imx27.h"
-#include "devices.h"
 
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
 #define SDHC1_IRQ IRQ_GPIOB(25)
@@ -156,7 +153,7 @@ static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
         free_irq(SDHC1_IRQ, data);
 }
 
-static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = {
+static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {
         .init = visstrim_m10_sdhc1_init,
         .exit = visstrim_m10_sdhc1_exit,
 };
@@ -216,7 +213,8 @@ static int otg_phy_init(struct platform_device *pdev)
         return 0;
 }
 
-static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = {
+static const struct mxc_usbh_platform_data
+visstrim_m10_usbotg_pdata __initconst = {
         .init = otg_phy_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED,
@@ -237,8 +235,8 @@ static void __init visstrim_m10_board_init(void)
                                 ARRAY_SIZE(visstrim_m10_i2c_devices));
         imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
         imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
-        mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata);
-        mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata);
+        imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
+        imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index bbdbc75127d3..3a1202e47212 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -25,7 +25,6 @@
 #include <mach/iomux-mx27.h>
 
 #include "devices-imx27.h"
-#include "devices.h"
 
 static const int mx27lite_pins[] __initconst = {
         /* UART1 */
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 6187ce9ba7d5..1f446e5eb636 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -30,7 +30,6 @@
 #include <mach/irqs.h>
 
 #include "devices-imx1.h"
-#include "devices.h"
 
 static const int mx1ads_pins[] __initconst = {
         /* UART1 */
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index e1282e9f50ff..0a372577c2ac 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -24,13 +24,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/imxfb.h>
 #include <mach/iomux-mx21.h>
 #include <mach/mxc_nand.h>
-#include <mach/mmc.h>
 
 #include "devices-imx21.h"
-#include "devices.h"
 
 /*
  * Memory-mapped I/O on MX21ADS base board
@@ -213,7 +210,7 @@ static struct imx_fb_videomode mx21ads_modes[] = {
         },
 };
 
-static struct imx_fb_platform_data mx21ads_fb_data = {
+static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
         .mode = mx21ads_modes,
         .num_modes = ARRAY_SIZE(mx21ads_modes),
 
@@ -233,15 +230,8 @@ static int mx21ads_sdhc_get_ro(struct device *dev)
 static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
         void *data)
 {
-        int ret;
-
-        ret = request_irq(IRQ_GPIOD(25), detect_irq,
+        return request_irq(IRQ_GPIOD(25), detect_irq,
                 IRQF_TRIGGER_FALLING, "mmc-detect", data);
-        if (ret)
-                goto out;
-        return 0;
-out:
-        return ret;
 }
 
 static void mx21ads_sdhc_exit(struct device *dev, void *data)
@@ -249,7 +239,7 @@ static void mx21ads_sdhc_exit(struct device *dev, void *data)
         free_irq(IRQ_GPIOD(25), data);
 }
 
-static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
+static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
         .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
         .get_ro = mx21ads_sdhc_get_ro,
         .init = mx21ads_sdhc_init,
@@ -296,8 +286,8 @@ static void __init mx21ads_board_init(void)
         imx21_add_imx_uart0(&uart_pdata_rts);
         imx21_add_imx_uart2(&uart_pdata_norts);
         imx21_add_imx_uart3(&uart_pdata_rts);
-        mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
-        mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
+        imx21_add_imx_fb(&mx21ads_fb_data);
+        imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
         imx21_add_mxc_nand(&mx21ads_nand_board_info);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index f8be1eb0c062..aa76cfd9f348 100644
--- a/arch/arm/mach-mx25/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -30,6 +30,7 @@
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/usb/otg.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -39,17 +40,15 @@
 #include <asm/mach/map.h>
 #include <mach/common.h>
 #include <mach/mx25.h>
-#include <mach/imxfb.h>
 #include <mach/iomux-mx25.h>
 
 #include "devices-imx25.h"
-#include "devices.h"
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct pad_desc mx25pdk_pads[] = {
+static iomux_v3_cfg_t mx25pdk_pads[] = {
         MX25_PAD_FEC_MDC__FEC_MDC,
         MX25_PAD_FEC_MDIO__FEC_MDIO,
         MX25_PAD_FEC_TDATA0__FEC_TDATA0,
@@ -107,7 +106,7 @@ static struct pad_desc mx25pdk_pads[] = {
 };
 
 static const struct fec_platform_data mx25_fec_pdata __initconst = {
-        .phy    = PHY_INTERFACE_MODE_RMII,
+        .phy    = PHY_INTERFACE_MODE_RMII,
 };
 
 #define FEC_ENABLE_GPIO         35
@@ -154,7 +153,7 @@ static struct imx_fb_videomode mx25pdk_modes[] = {
         },
 };
 
-static struct imx_fb_platform_data mx25pdk_fb_pdata = {
+static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = {
         .mode           = mx25pdk_modes,
         .num_modes      = ARRAY_SIZE(mx25pdk_modes),
         .pwmr           = 0x00A903FF,
@@ -181,28 +180,39 @@ static const uint32_t mx25pdk_keymap[] = {
         KEY(3, 3, KEY_POWER),
 };
 
-static struct matrix_keymap_data mx25pdk_keymap_data = {
+static const struct matrix_keymap_data mx25pdk_keymap_data __initdata = {
         .keymap         = mx25pdk_keymap,
         .keymap_size    = ARRAY_SIZE(mx25pdk_keymap),
 };
 
+static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
+        .portsc = MXC_EHCI_MODE_SERIAL,
+        .flags  = MXC_EHCI_INTERNAL_PHY,
+};
+
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI,
+};
+
 static void __init mx25pdk_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
                         ARRAY_SIZE(mx25pdk_pads));
 
         imx25_add_imx_uart0(&uart_pdata);
-        mxc_register_device(&mxc_usbh2, NULL);
+        imx25_add_fsl_usb2_udc(&otg_device_pdata);
+        imx25_add_mxc_ehci_hs(&usbh2_pdata);
         imx25_add_mxc_nand(&mx25pdk_nand_board_info);
-        mxc_register_device(&mx25_rtc_device, NULL);
-        mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
-        mxc_register_device(&mxc_wdt, NULL);
+        imx25_add_imxdi_rtc(NULL);
+        imx25_add_imx_fb(&mx25pdk_fb_pdata);
+        imx25_add_imx2_wdt(NULL);
 
         mx25pdk_fec_reset();
         imx25_add_fec(&mx25_fec_pdata);
-        mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
+        imx25_add_imx_keypad(&mx25pdk_keymap_data);
 
-        imx25_add_esdhc(0, NULL);
+        imx25_add_sdhci_esdhc_imx(0, NULL);
 }
 
 static void __init mx25pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 84a5ba03f1ba..6fd0f8f6deb6 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -22,20 +22,27 @@
 
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
-#include <linux/input/matrix_keypad.h>
 #include <linux/irq.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/delay.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
+#include <linux/regulator/machine.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
-#include <mach/mmc.h>
+#include <mach/ulpi.h>
 
 #include "devices-imx27.h"
-#include "devices.h"
 
 #define SD1_EN_GPIO (GPIO_PORTB + 25)
+#define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23)
+#define SPI2_SS0 (GPIO_PORTD + 21)
 
 static const int mx27pdk_pins[] __initconst = {
         /* UART1 */
@@ -70,6 +77,24 @@ static const int mx27pdk_pins[] __initconst = {
         PE22_PF_SD1_CMD,
         PE23_PF_SD1_CLK,
         SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
+        /* OTG */
+        OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT,
+        PC7_PF_USBOTG_DATA5,
+        PC8_PF_USBOTG_DATA6,
+        PC9_PF_USBOTG_DATA0,
+        PC10_PF_USBOTG_DATA2,
+        PC11_PF_USBOTG_DATA1,
+        PC12_PF_USBOTG_DATA4,
+        PC13_PF_USBOTG_DATA3,
+        PE0_PF_USBOTG_NXT,
+        PE1_PF_USBOTG_STP,
+        PE2_PF_USBOTG_DIR,
+        PE24_PF_USBOTG_CLK,
+        PE25_PF_USBOTG_DATA7,
+        /* CSPI2 */
+        PD22_PF_CSPI2_SCLK,
+        PD23_PF_CSPI2_MISO,
+        PD24_PF_CSPI2_MOSI,
 };
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -92,7 +117,7 @@ static const uint32_t mx27_3ds_keymap[] = {
         KEY(2, 3, KEY_F10),
 };
 
-static struct matrix_keymap_data mx27_3ds_keymap_data = {
+static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = {
         .keymap         = mx27_3ds_keymap,
         .keymap_size    = ARRAY_SIZE(mx27_3ds_keymap),
 };
@@ -109,7 +134,7 @@ static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
         free_irq(IRQ_GPIOB(26), data);
 }
 
-static struct imxmmc_platform_data sdhc1_pdata = {
+static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
         .init = mx27_3ds_sdhc1_init,
         .exit = mx27_3ds_sdhc1_exit,
 };
@@ -121,6 +146,111 @@ static void mx27_3ds_sdhc1_enable_level_translator(void)
         gpio_direction_output(SD1_EN_GPIO, 1);
 }
 
+
+static int otg_phy_init(void)
+{
+        gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset");
+        gpio_direction_output(OTG_PHY_RESET_GPIO, 0);
+        mdelay(1);
+        gpio_set_value(OTG_PHY_RESET_GPIO, 1);
+        return 0;
+}
+
+#if defined(CONFIG_USB_ULPI)
+
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+#endif
+
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+
+static int otg_mode_host;
+
+static int __init mx27_3ds_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", mx27_3ds_otg_mode);
+
+/* Regulators */
+static struct regulator_consumer_supply vmmc1_consumers[] = {
+        REGULATOR_SUPPLY("lcd_2v8", NULL),
+};
+
+static struct regulator_init_data vmmc1_init = {
+        .constraints = {
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
+        .consumer_supplies = vmmc1_consumers,
+};
+
+static struct regulator_consumer_supply vgen_consumers[] = {
+        REGULATOR_SUPPLY("vdd_lcdio", NULL),
+};
+
+static struct regulator_init_data vgen_init = {
+        .constraints = {
+                .min_uV = 1800000,
+                .max_uV = 1800000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
+        .consumer_supplies = vgen_consumers,
+};
+
+static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
+        {
+                .id = MC13783_REGU_VMMC1,
+                .init_data = &vmmc1_init,
+        }, {
+                .id = MC13783_REGU_VGEN,
+                .init_data = &vgen_init,
+        },
+};
+
+/* MC13783 */
+static struct mc13783_platform_data mc13783_pdata __initdata = {
+        .regulators = mx27_3ds_regulators,
+        .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
+        .flags  = MC13783_USE_REGULATOR,
+};
+
+/* SPI */
+static int spi2_internal_chipselect[] = {SPI2_SS0};
+
+static const struct spi_imx_master spi2_pdata __initconst = {
+        .chipselect     = spi2_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi2_internal_chipselect),
+};
+
+static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
+        {
+                .modalias       = "mc13783",
+                .max_speed_hz   = 1000000,
+                .bus_num        = 1,
+                .chip_select    = 0, /* SS0 */
+                .platform_data  = &mc13783_pdata,
+                .irq = IRQ_GPIOC(14),
+                .mode = SPI_CS_HIGH,
+        },
+};
+
+
 static void __init mx27pdk_init(void)
 {
         mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
@@ -128,8 +258,24 @@ static void __init mx27pdk_init(void)
         mx27_3ds_sdhc1_enable_level_translator();
         imx27_add_imx_uart0(&uart_pdata);
         imx27_add_fec(NULL);
-        mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
-        mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
+        imx27_add_imx_keypad(&mx27_3ds_keymap_data);
+        imx27_add_mxc_mmc(0, &sdhc1_pdata);
+        imx27_add_imx2_wdt(NULL);
+        otg_phy_init();
+#if defined(CONFIG_USB_ULPI)
+        if (otg_mode_host) {
+                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+
+                imx27_add_mxc_ehci_otg(&otg_pdata);
+        }
+#endif
+        if (!otg_mode_host)
+                imx27_add_fsl_usb2_udc(&otg_device_pdata);
+
+        imx27_add_spi_imx1(&spi2_pdata);
+        spi_register_board_info(mx27_3ds_spi_devs,
+                                                ARRAY_SIZE(mx27_3ds_spi_devs));
 }
 
 static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index a1e4bc573afc..b832f960fec4 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -30,11 +30,8 @@
 #include <mach/gpio.h>
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
-#include <mach/imxfb.h>
-#include <mach/mmc.h>
 
 #include "devices-imx27.h"
-#include "devices.h"
 
 /*
  * Base address of PBC controller, CS4
@@ -228,7 +225,7 @@ static struct imx_fb_videomode mx27ads_modes[] = {
         },
 };
 
-static struct imx_fb_platform_data mx27ads_fb_data = {
+static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
         .mode = mx27ads_modes,
         .num_modes = ARRAY_SIZE(mx27ads_modes),
 
@@ -272,19 +269,18 @@ static void mx27ads_sdhc2_exit(struct device *dev, void *data)
         free_irq(IRQ_GPIOB(7), data);
 }
 
-static struct imxmmc_platform_data sdhc1_pdata = {
+static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
         .init = mx27ads_sdhc1_init,
         .exit = mx27ads_sdhc1_exit,
 };
 
-static struct imxmmc_platform_data sdhc2_pdata = {
+static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
         .init = mx27ads_sdhc2_init,
         .exit = mx27ads_sdhc2_exit,
 };
 
 static struct platform_device *platform_devices[] __initdata = {
         &mx27ads_nor_mtd_device,
-        &mxc_w1_master_device,
 };
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -308,12 +304,13 @@ static void __init mx27ads_board_init(void)
         i2c_register_board_info(1, mx27ads_i2c_devices,
                                 ARRAY_SIZE(mx27ads_i2c_devices));
         imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
-        mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
-        mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
-        mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
+        imx27_add_imx_fb(&mx27ads_fb_data);
+        imx27_add_mxc_mmc(0, &sdhc1_pdata);
+        imx27_add_mxc_mmc(1, &sdhc2_pdata);
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx27_add_mxc_w1(NULL);
 }
 
 static void __init mx27ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 38d3a4ae17c7..4ce71b0401db 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -31,11 +31,8 @@
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
 #include <linux/i2c/pca953x.h>
-#include <mach/imxfb.h>
-#include <mach/mmc.h>
 
 #include "devices-imx27.h"
-#include "devices.h"
 
 static const int mxt_td60_pins[] __initconst = {
         /* UART0 */
@@ -196,7 +193,7 @@ static struct imx_fb_videomode mxt_td60_modes[] = {
         },
 };
 
-static struct imx_fb_platform_data mxt_td60_fb_data = {
+static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
         .mode = mxt_td60_modes,
         .num_modes = ARRAY_SIZE(mxt_td60_modes),
 
@@ -226,7 +223,7 @@ static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
         free_irq(IRQ_GPIOF(8), data);
 }
 
-static struct imxmmc_platform_data sdhc1_pdata = {
+static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
         .init = mxt_td60_sdhc1_init,
         .exit = mxt_td60_sdhc1_exit,
 };
@@ -253,8 +250,8 @@ static void __init mxt_td60_board_init(void)
 
         imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
         imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
-        mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
-        mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
+        imx27_add_imx_fb(&mxt_td60_fb_data);
+        imx27_add_mxc_mmc(0, &sdhc1_pdata);
         imx27_add_fec(NULL);
 }
 
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 8c720d44602a..cccc0a0a9c72 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -29,7 +29,6 @@
 #include <linux/gpio.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <linux/fsl_devices.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -40,13 +39,9 @@
 #include <mach/audmux.h>
 #include <mach/mxc_nand.h>
 #include <mach/irqs.h>
-#include <mach/mmc.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
-#include <mach/imxfb.h>
 
 #include "devices-imx27.h"
-#include "devices.h"
 
 #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
 #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
@@ -171,11 +166,6 @@ pca100_nand_board_info __initconst = {
         .hw_ecc = 1,
 };
 
-static struct platform_device *platform_devices[] __initdata = {
-        &mxc_w1_master_device,
-        &mxc_wdt,
-};
-
 static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
         .bitrate = 100000,
 };
@@ -274,7 +264,7 @@ static void pca100_sdhc2_exit(struct device *dev, void *data)
         free_irq(IRQ_GPIOC(29), data);
 }
 
-static struct imxmmc_platform_data sdhc_pdata = {
+static const struct imxmmc_platform_data sdhc_pdata __initconst = {
         .init = pca100_sdhc2_init,
         .exit = pca100_sdhc2_exit,
 };
@@ -286,7 +276,7 @@ static int otg_phy_init(struct platform_device *pdev)
         return 0;
 }
 
-static struct mxc_usbh_platform_data otg_pdata = {
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
         .init   = otg_phy_init,
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -298,14 +288,14 @@ static int usbh2_phy_init(struct platform_device *pdev)
         return 0;
 }
 
-static struct mxc_usbh_platform_data usbh2_pdata = {
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .init   = usbh2_phy_init,
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 #endif
 
-static struct fsl_usb2_platform_data otg_device_pdata = {
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
@@ -355,7 +345,7 @@ static struct imx_fb_videomode pca100_fb_modes[] = {
         },
 };
 
-static struct imx_fb_platform_data pca100_fb_data = {
+static const struct imx_fb_platform_data pca100_fb_data __initconst = {
         .mode = pca100_fb_modes,
         .num_modes = ARRAY_SIZE(pca100_fb_modes),
 
@@ -389,7 +379,7 @@ static void __init pca100_init(void)
 
         imx27_add_imx_uart0(&uart_pdata);
 
-        mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+        imx27_add_mxc_mmc(1, &sdhc_pdata);
 
         imx27_add_mxc_nand(&pca100_nand_board_info);
 
@@ -417,23 +407,24 @@ static void __init pca100_init(void)
                 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-                mxc_register_device(&mxc_otg_host, &otg_pdata);
+                imx27_add_mxc_ehci_otg(&otg_pdata);
         }
 
         usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+        imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
 #endif
         if (!otg_mode_host) {
                 gpio_set_value(OTG_PHY_CS_GPIO, 0);
-                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+                imx27_add_fsl_usb2_udc(&otg_device_pdata);
         }
 
-        mxc_register_device(&mxc_fb_device, &pca100_fb_data);
+        imx27_add_imx_fb(&pca100_fb_data);
 
         imx27_add_fec(NULL);
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx27_add_imx2_wdt(NULL);
+        imx27_add_mxc_w1(NULL);
 }
 
 static void __init pca100_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 49a97ce07426..f667a262dfc1 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -37,11 +37,9 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx27.h"
-#include "devices.h"
 
 static const int pcm038_pins[] __initconst = {
         /* UART1 */
@@ -172,9 +170,7 @@ pcm038_nand_board_info __initconst = {
 
 static struct platform_device *platform_devices[] __initdata = {
         &pcm038_nor_mtd_device,
-        &mxc_w1_master_device,
         &pcm038_sram_mtd_device,
-        &mxc_wdt,
 };
 
 /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
@@ -214,7 +210,7 @@ static const struct spi_imx_master pcm038_spi0_data __initconst = {
 
 static struct regulator_consumer_supply sdhc1_consumers[] = {
         {
-                .dev    = &mxc_sdhc_device1.dev,
+                .dev_name = "mxc-mmc.1",
                 .supply = "sdhc_vcc",
         },
 };
@@ -285,7 +281,7 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
         }
 };
 
-static struct mxc_usbh_platform_data usbh2_pdata = {
+static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
 };
@@ -322,10 +318,12 @@ static void __init pcm038_init(void)
         spi_register_board_info(pcm038_spi_board_info,
                                 ARRAY_SIZE(pcm038_spi_board_info));
 
-        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+        imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx27_add_imx2_wdt(NULL);
+        imx27_add_mxc_w1(NULL);
 
 #ifdef CONFIG_MACH_PCM970_BASEBOARD
         pcm970_baseboard_init();
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 1fbdd3faa7ab..eae878f306c6 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -25,7 +25,6 @@
 #include <mach/iomux-mx1.h>
 
 #include "devices-imx1.h"
-#include "devices.h"
 
 /*
  * This scb9328 has a 32MiB flash
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 9be92b96dc89..729ae0915af8 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -25,12 +25,7 @@
 #include <mach/hardware.h>
 
 static struct map_desc imx_io_desc[] __initdata = {
-        {
-                .virtual = MX1_IO_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
-                .length = MX1_IO_SIZE,
-                .type = MT_DEVICE
-        }
+        imx_map_entry(MX1, IO, MT_DEVICE),
 };
 
 void __init mx1_map_io(void)
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 12faeeaa0a97..e728af81d1b1 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -35,33 +35,18 @@ static struct map_desc imx21_io_desc[] __initdata = {
          * - ROM Patch
          * - and some reserved space
          */
-        {
-                .virtual = MX21_AIPI_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR),
-                .length = MX21_AIPI_SIZE,
-                .type = MT_DEVICE
-        },
+        imx_map_entry(MX21, AIPI, MT_DEVICE),
         /*
          * this fixed mapping covers:
          * - CSI
          * - ATA
          */
-        {
-                .virtual = MX21_SAHB1_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR),
-                .length = MX21_SAHB1_SIZE,
-                .type = MT_DEVICE
-        },
+        imx_map_entry(MX21, SAHB1, MT_DEVICE),
         /*
          * this fixed mapping covers:
          * - EMI
          */
-        {
-                .virtual = MX21_X_MEMC_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR),
-                .length = MX21_X_MEMC_SIZE,
-                .type = MT_DEVICE
-        },
+        imx_map_entry(MX21, X_MEMC, MT_DEVICE),
 };
 
 /*
diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-imx/mm-imx25.c
index bb677111fb0f..2edec6ce8fe7 100644
--- a/arch/arm/mach-mx25/mm.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -30,25 +30,12 @@
 
 /*
  * This table defines static virtual address mappings for I/O regions.
- * These are the mappings common across all MX3 boards.
+ * These are the mappings common across all MX25 boards.
  */
-static struct map_desc mxc_io_desc[] __initdata = {
-        {
-                .virtual        = MX25_AVIC_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MX25_AVIC_BASE_ADDR),
-                .length         = MX25_AVIC_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
-                .virtual        = MX25_AIPS1_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MX25_AIPS1_BASE_ADDR),
-                .length         = MX25_AIPS1_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
-                .virtual        = MX25_AIPS2_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MX25_AIPS2_BASE_ADDR),
-                .length         = MX25_AIPS2_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        },
+static struct map_desc mx25_io_desc[] __initdata = {
+        imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
 };
 
 /*
@@ -62,14 +49,14 @@ void __init mx25_map_io(void)
         mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
 
-        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+        iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
 }
 
 int imx25_register_gpios(void);
 
 void __init mx25_init_irq(void)
 {
-        mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
+        mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
         imx25_register_gpios();
 }
 
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index a24622957ff2..374e48b7a412 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -35,33 +35,18 @@ static struct map_desc imx27_io_desc[] __initdata = {
          * - ROM Patch
          * - and some reserved space
          */
-        {
-                .virtual = MX27_AIPI_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR),
-                .length = MX27_AIPI_SIZE,
-                .type = MT_DEVICE
-        },
+        imx_map_entry(MX27, AIPI, MT_DEVICE),
         /*
          * this fixed mapping covers:
          * - CSI
          * - ATA
          */
-        {
-                .virtual = MX27_SAHB1_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR),
-                .length = MX27_SAHB1_SIZE,
-                .type = MT_DEVICE
-        },
+        imx_map_entry(MX27, SAHB1, MT_DEVICE),
         /*
          * this fixed mapping covers:
          * - EMI
          */
-        {
-                .virtual = MX27_X_MEMC_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR),
-                .length = MX27_X_MEMC_SIZE,
-                .type = MT_DEVICE
-        },
+        imx_map_entry(MX27, X_MEMC, MT_DEVICE),
 };
 
 /*
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index 9110d9cca7a2..99afbc3f43a3 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -25,11 +25,9 @@
 
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
-#include <mach/imxfb.h>
 #include <mach/hardware.h>
-#include <mach/mmc.h>
 
-#include "devices.h"
+#include "devices-imx27.h"
 
 static const int pcm970_pins[] __initconst = {
         /* SDHC */
@@ -119,7 +117,7 @@ static void pcm970_sdhc2_exit(struct device *dev, void *data)
         gpio_free(GPIO_PORTC + 28);
 }
 
-static struct imxmmc_platform_data sdhc_pdata = {
+static const struct imxmmc_platform_data sdhc_pdata __initconst = {
         .get_ro = pcm970_sdhc2_get_ro,
         .init = pcm970_sdhc2_init,
         .exit = pcm970_sdhc2_exit,
@@ -179,7 +177,7 @@ static struct imx_fb_videomode pcm970_modes[] = {
         },
 };
 
-static struct imx_fb_platform_data pcm038_fb_data = {
+static const struct imx_fb_platform_data pcm038_fb_data __initconst = {
         .mode = pcm970_modes,
         .num_modes = ARRAY_SIZE(pcm970_modes),
 
@@ -226,8 +224,8 @@ void __init pcm970_baseboard_init(void)
         mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
                         "PCM970");
 
-        mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
+        imx27_add_imx_fb(&pcm038_fb_data);
         mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
-        mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+        imx27_add_mxc_mmc(1, &sdhc_pdata);
         platform_device_register(&pcm970_sja1000);
 }
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index afc17ce0bb54..6bf81ceea137 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -39,6 +39,9 @@ static struct platform_suspend_ops mx27_suspend_ops = {
 
 static int __init mx27_pm_init(void)
 {
+        if (!cpu_is_mx27())
+                return 0;
+
         suspend_set_ops(&mx27_suspend_ops);
         return 0;
 }
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index 27db275b367c..769b0f10c834 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -4,6 +4,7 @@ menu "Integrator Options"
 
 config ARCH_INTEGRATOR_AP
         bool "Support Integrator/AP and Integrator/PP2 platforms"
+        select MIGHT_HAVE_PCI
         help
           Include support for the ARM(R) Integrator/AP and
           Integrator/PP2 platforms.
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 8f4fb6d638f7..b8e884b450da 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -21,9 +21,8 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
 #include <linux/io.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
-#include <mach/clkdev.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <asm/irq.h>
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index fd684bf205e5..5db574f8ae3f 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -22,9 +22,8 @@
 #include <linux/amba/clcd.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
-#include <mach/clkdev.h>
 #include <asm/hardware/icst.h>
 #include <mach/lm.h>
 #include <mach/impd1.h>
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 548208f11179..2774df8021dc 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -372,7 +372,6 @@ static struct clocksource clocksource_timersp = {
         .rating         = 200,
         .read           = timersp_read,
         .mask           = CLOCKSOURCE_MASK(16),
-        .shift          = 16,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -390,8 +389,7 @@ static void integrator_clocksource_init(u32 khz)
         writel(ctrl, base + TIMER_CTRL);
         writel(0xffff, base + TIMER_LOAD);
 
-        cs->mult = clocksource_khz2mult(khz, cs->shift);
-        clocksource_register(cs);
+        clocksource_register_khz(cs, khz);
 }
 
 static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 6258c90d020c..85e48a5f77b9 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -21,9 +21,8 @@
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
 #include <linux/gfp.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
-#include <mach/clkdev.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <asm/irq.h>
@@ -41,7 +40,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include <plat/timer-sp.h>
+#include <asm/hardware/timer-sp.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index a6e0f9e6ddcf..dffb234bb967 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -35,7 +35,7 @@ extern u32 iop13xx_atux_mem_base;
 extern size_t iop13xx_atue_mem_size;
 extern size_t iop13xx_atux_mem_size;
 
-#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
-#define __arch_iounmap(a)        __iop13xx_iounmap(a)
+#define __arch_ioremap  __iop13xx_ioremap
+#define __arch_iounmap  __iop13xx_iounmap
 
 #endif
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index 7415e4338651..3ad455318868 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -58,13 +58,13 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
                 __dma;                                                  \
         })
 
-#define __arch_page_to_dma(dev, page)                                   \
+#define __arch_pfn_to_dma(dev, pfn)                                     \
         ({                                                              \
                 /* __is_lbus_virt() can never be true for RAM pages */  \
-                (dma_addr_t)page_to_phys(page);                         \
+                (dma_addr_t)__pfn_to_phys(pfn);                         \
         })
 
-#define __arch_dma_to_page(dev, addr)   phys_to_page(addr)
+#define __arch_dma_to_pfn(dev, addr)    __phys_to_pfn(addr)
 
 #endif /* CONFIG_ARCH_IOP13XX */
 #endif /* !ASSEMBLY */
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
index 339e5854728b..059c783ce0b2 100644
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ b/arch/arm/mach-iop32x/include/mach/io.h
@@ -21,7 +21,7 @@ extern void __iop3xx_iounmap(void __iomem *addr);
 #define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
 #define __mem_pci(a)            (a)
 
-#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
-#define __arch_iounmap(a)        __iop3xx_iounmap(a)
+#define __arch_ioremap  __iop3xx_ioremap
+#define __arch_iounmap  __iop3xx_iounmap
 
 #endif
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
index e99a7ed6d050..39e893e97c21 100644
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ b/arch/arm/mach-iop33x/include/mach/io.h
@@ -21,7 +21,7 @@ extern void __iop3xx_iounmap(void __iomem *addr);
 #define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
 #define __mem_pci(a)            (a)
 
-#define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
-#define __arch_iounmap(a)        __iop3xx_iounmap(a)
+#define __arch_ioremap  __iop3xx_ioremap
+#define __arch_iounmap  __iop3xx_iounmap
 
 #endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
index fd9ef8e519f7..a1749d0fd896 100644
--- a/arch/arm/mach-ixp23xx/include/mach/io.h
+++ b/arch/arm/mach-ixp23xx/include/mach/io.h
@@ -45,8 +45,8 @@ ixp23xx_iounmap(void __iomem *addr)
         __iounmap(addr);
 }
 
-#define __arch_ioremap(a,s,f)   ixp23xx_ioremap(a,s,f)
-#define __arch_iounmap(a)       ixp23xx_iounmap(a)
+#define __arch_ioremap  ixp23xx_ioremap
+#define __arch_iounmap  ixp23xx_iounmap
 
 
 #endif
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 0bce09799d18..4dbfcbb9163c 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -35,6 +35,7 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/irq.h>
+#include <asm/sched_clock.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -399,6 +400,23 @@ void __init ixp4xx_sys_init(void)
 }
 
 /*
+ * sched_clock()
+ */
+static DEFINE_CLOCK_DATA(cd);
+
+unsigned long long notrace sched_clock(void)
+{
+        u32 cyc = *IXP4XX_OSTS;
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
+
+static void notrace ixp4xx_update_sched_clock(void)
+{
+        u32 cyc = *IXP4XX_OSTS;
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+
+/*
  * clocksource
  */
 static cycle_t ixp4xx_get_cycles(struct clocksource *cs)
@@ -411,7 +429,6 @@ static struct clocksource clocksource_ixp4xx = {
         .rating         = 200,
         .read           = ixp4xx_get_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -419,21 +436,9 @@ unsigned long ixp4xx_timer_freq = FREQ;
 EXPORT_SYMBOL(ixp4xx_timer_freq);
 static void __init ixp4xx_clocksource_init(void)
 {
-        clocksource_ixp4xx.mult =
-                clocksource_hz2mult(ixp4xx_timer_freq,
-                                    clocksource_ixp4xx.shift);
-        clocksource_register(&clocksource_ixp4xx);
-}
-
-/*
- * sched_clock()
- */
-unsigned long long sched_clock(void)
-{
-        cycle_t cyc = ixp4xx_get_cycles(NULL);
-        struct clocksource *cs = &clocksource_ixp4xx;
+        init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq);
 
-        return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+        clocksource_register_hz(&clocksource_ixp4xx, ixp4xx_timer_freq);
 }
 
 /*
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index de274a1f19d7..57b5410c31f4 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -74,8 +74,8 @@ static inline void __indirect_iounmap(void __iomem *addr)
                 __iounmap(addr);
 }
 
-#define __arch_ioremap(a, s, f)         __indirect_ioremap(a, s, f)
-#define __arch_iounmap(a)               __indirect_iounmap(a)
+#define __arch_ioremap                  __indirect_ioremap
+#define __arch_iounmap                  __indirect_iounmap
 
 #define writeb(v, p)                    __indirect_writeb(v, p)
 #define writew(v, p)                    __indirect_writew(v, p)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 34106335c728..7fc603b46891 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -45,18 +45,18 @@ config MACH_GURUPLUG
           Marvell GuruPlug Reference Board.
 
 config MACH_TS219
-        bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS"
+        bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
         help
           Say 'Y' here if you want your kernel to support the
-          QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS
-          devices.
+          QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
+          TS-219P+ Turbo NAS devices.
 
 config MACH_TS41X
-        bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS"
+        bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
         help
           Say 'Y' here if you want your kernel to support the
-          QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
-          devices.
+          QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
+          NAS devices.
 
 config MACH_DOCKSTAR
         bool "Seagate FreeAgent DockStar"
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
index 44e8be04f259..1aaddc364f2e 100644
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ b/arch/arm/mach-kirkwood/include/mach/io.h
@@ -42,8 +42,8 @@ __arch_iounmap(void __iomem *addr)
                 __iounmap(addr);
 }
 
-#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
-#define __arch_iounmap(a)       __arch_iounmap(a)
+#define __arch_ioremap          __arch_ioremap
+#define __arch_iounmap          __arch_iounmap
 #define __io(a)                 __io(a)
 #define __mem_pci(a)            (a)
 
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 6710bd7773b8..dc999c4c5806 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -80,15 +80,19 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
         MPP11_UART0_RXD,
         MPP13_UART1_TXD,        /* PIC controller */
         MPP14_UART1_RXD,        /* PIC controller */
-        MPP15_GPIO,             /* USB Copy button */
-        MPP16_GPIO,             /* Reset button */
+        MPP15_GPIO,             /* USB Copy button (on devices with 88F6281) */
+        MPP16_GPIO,             /* Reset button (on devices with 88F6281) */
         MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
+        MPP37_GPIO,             /* Reset button (on devices with 88F6282) */
+        MPP43_GPIO,             /* USB Copy button (on devices with 88F6282) */
         MPP44_GPIO,             /* Board ID: 0: TS-11x, 1: TS-21x */
         0
 };
 
 static void __init qnap_ts219_init(void)
 {
+        u32 dev, rev;
+
         /*
          * Basic setup. Needs to be called early.
          */
@@ -100,6 +104,14 @@ static void __init qnap_ts219_init(void)
         qnap_tsx1x_register_flash();
         kirkwood_i2c_init();
         i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
+
+        kirkwood_pcie_id(&dev, &rev);
+        if (dev == MV88F6282_DEV_ID) {
+                qnap_ts219_buttons[0].gpio = 43; /* USB Copy button */
+                qnap_ts219_buttons[1].gpio = 37; /* Reset button */
+                qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+        }
+
         kirkwood_ge00_init(&qnap_ts219_ge00_data);
         kirkwood_sata_init(&qnap_ts219_sata_data);
         kirkwood_ehci_init();
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 3587a281d993..9a44029915e2 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -119,6 +119,8 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
 
 static void __init qnap_ts41x_init(void)
 {
+        u32 dev, rev;
+
         /*
          * Basic setup. Needs to be called early.
          */
@@ -130,8 +132,15 @@ static void __init qnap_ts41x_init(void)
         qnap_tsx1x_register_flash();
         kirkwood_i2c_init();
         i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1);
+
+        kirkwood_pcie_id(&dev, &rev);
+        if (dev == MV88F6282_DEV_ID) {
+                qnap_ts41x_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+                qnap_ts41x_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
+        }
         kirkwood_ge00_init(&qnap_ts41x_ge00_data);
         kirkwood_ge01_init(&qnap_ts41x_ge01_data);
+
         kirkwood_sata_init(&qnap_ts41x_sata_data);
         kirkwood_ehci_init();
         platform_device_register(&qnap_ts41x_button_device);
diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig
index fe0c82e30b2d..f5c39a8c2b00 100644
--- a/arch/arm/mach-ks8695/Kconfig
+++ b/arch/arm/mach-ks8695/Kconfig
@@ -4,6 +4,7 @@ menu "Kendin/Micrel KS8695 Implementations"
 
 config MACH_KS8695
         bool "KS8695 development board"
+        select MIGHT_HAVE_PCI
         help
           Say 'Y' here if you want your kernel to run on the original
           Kendin-Micrel KS8695 development board.
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h
index ffa19aae6e05..bace9a681adc 100644
--- a/arch/arm/mach-ks8695/include/mach/memory.h
+++ b/arch/arm/mach-ks8695/include/mach/memory.h
@@ -35,17 +35,17 @@ extern struct bus_type platform_bus_type;
                                         __phys_to_virt(x) : __bus_to_virt(x)); })
 #define __arch_virt_to_dma(dev, x)      ({ is_lbus_device(dev) ? \
                                         (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); })
-#define __arch_page_to_dma(dev, x)      \
-        ({ dma_addr_t __dma = page_to_phys(page); \
+#define __arch_pfn_to_dma(dev, pfn)     \
+        ({ dma_addr_t __dma = __pfn_to_phys(pfn); \
            if (!is_lbus_device(dev)) \
                 __dma = __dma - PHYS_OFFSET + KS8695_PCIMEM_PA; \
            __dma; })
 
-#define __arch_dma_to_page(dev, x)      \
+#define __arch_dma_to_pfn(dev, x)       \
         ({ dma_addr_t __dma = x;                                \
            if (!is_lbus_device(dev))                            \
                 __dma += PHYS_OFFSET - KS8695_PCIMEM_PA;        \
-           phys_to_page(__dma);                                 \
+           __phys_to_pfn(__dma);                                \
         })
 
 #endif
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 32d63796430a..da0e6498110a 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -90,10 +90,9 @@
 #include <linux/clk.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/clkdev.h>
 
 #include <mach/hardware.h>
-#include <asm/clkdev.h>
-#include <mach/clkdev.h>
 #include <mach/platform.h>
 #include "clock.h"
 #include "common.h"
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index 630dd4a74b26..6162ac308c20 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -38,7 +38,6 @@ static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
 
 static struct clocksource lpc32xx_clksrc = {
         .name   = "lpc32xx_clksrc",
-        .shift  = 24,
         .rating = 300,
         .read   = lpc32xx_clksrc_read,
         .mask   = CLOCKSOURCE_MASK(32),
@@ -171,9 +170,7 @@ static void __init lpc32xx_timer_init(void)
         __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
         __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
                 LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
-        lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate,
-                lpc32xx_clksrc.shift);
-        clocksource_register(&lpc32xx_clksrc);
+        clocksource_register_hz(&lpc32xx_clksrc, clkrate);
 }
 
 struct sys_timer lpc32xx_timer = {
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 0711d3b620ad..67793a690272 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -37,25 +37,38 @@ config MACH_TTC_DKB
           Say 'Y' here if you want to support the Marvell PXA910-based
           TTC_DKB Development Board.
 
+config MACH_BROWNSTONE
+        bool "Marvell's Brownstone Development Platform"
+        depends on !CPU_MOHAWK
+        select CPU_MMP2
+        help
+          Say 'Y' here if you want to support the Marvell MMP2-based
+          Brown Development Platform.
+          MMP2-based board can't be co-existed with PXA168-based &
+          PXA910-based development board. Since MMP2 is compatible to
+          ARMv7 architecture.
+
 config MACH_FLINT
         bool "Marvell's Flint Development Platform"
+        depends on !CPU_MOHAWK
         select CPU_MMP2
         help
           Say 'Y' here if you want to support the Marvell MMP2-based
           Flint Development Platform.
           MMP2-based board can't be co-existed with PXA168-based &
           PXA910-based development board. Since MMP2 is compatible to
-          ARMv6 architecture.
+          ARMv7 architecture.
 
 config MACH_MARVELL_JASPER
         bool "Marvell's Jasper Development Platform"
+        depends on !CPU_MOHAWK
         select CPU_MMP2
         help
           Say 'Y' here if you want to support the Marvell MMP2-base
           Jasper Development Platform.
           MMP2-based board can't be co-existed with PXA168-based &
           PXA910-based development board. Since MMP2 is compatible to
-          ARMv6 architecture.
+          ARMv7 architecture.
 
 config MACH_TETON_BGA
         bool "Marvell's PXA168 Teton BGA Development Board"
@@ -80,8 +93,7 @@ config CPU_PXA910
 
 config CPU_MMP2
         bool
-        select CPU_V6
-        select CPU_32v6K
+        select CPU_PJ4
         help
-          Select code specific to MMP2. MMP2 is ARMv6 compatible.
+          Select code specific to MMP2. MMP2 is ARMv7 compatible.
 endif
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 751cdbf733c8..5c68382141af 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_MACH_ZYLONITE2)	+= aspenite.o
 obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o
 obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
 obj-$(CONFIG_MACH_TTC_DKB)      += ttc_dkb.o
+obj-$(CONFIG_MACH_BROWNSTONE)   += brownstone.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
new file mode 100644
index 000000000000..7bb78fd5a2a6
--- /dev/null
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -0,0 +1,204 @@
+/*
+ *  linux/arch/arm/mach-mmp/brownstone.c
+ *
+ *  Support for the Marvell Brownstone Development Platform.
+ *
+ *  Copyright (C) 2009-2010 Marvell International Ltd.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/max8649.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/max8925.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/addr-map.h>
+#include <mach/mfp-mmp2.h>
+#include <mach/mmp2.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+#define BROWNSTONE_NR_IRQS      (IRQ_BOARD_START + 40)
+
+#define GPIO_5V_ENABLE          (89)
+
+static unsigned long brownstone_pin_config[] __initdata = {
+        /* UART1 */
+        GPIO29_UART1_RXD,
+        GPIO30_UART1_TXD,
+
+        /* UART3 */
+        GPIO51_UART3_RXD,
+        GPIO52_UART3_TXD,
+
+        /* DFI */
+        GPIO168_DFI_D0,
+        GPIO167_DFI_D1,
+        GPIO166_DFI_D2,
+        GPIO165_DFI_D3,
+        GPIO107_DFI_D4,
+        GPIO106_DFI_D5,
+        GPIO105_DFI_D6,
+        GPIO104_DFI_D7,
+        GPIO111_DFI_D8,
+        GPIO164_DFI_D9,
+        GPIO163_DFI_D10,
+        GPIO162_DFI_D11,
+        GPIO161_DFI_D12,
+        GPIO110_DFI_D13,
+        GPIO109_DFI_D14,
+        GPIO108_DFI_D15,
+        GPIO143_ND_nCS0,
+        GPIO144_ND_nCS1,
+        GPIO147_ND_nWE,
+        GPIO148_ND_nRE,
+        GPIO150_ND_ALE,
+        GPIO149_ND_CLE,
+        GPIO112_ND_RDY0,
+        GPIO160_ND_RDY1,
+
+        /* PMIC */
+        PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
+
+        /* MMC0 */
+        GPIO131_MMC1_DAT3 | MFP_PULL_HIGH,
+        GPIO132_MMC1_DAT2 | MFP_PULL_HIGH,
+        GPIO133_MMC1_DAT1 | MFP_PULL_HIGH,
+        GPIO134_MMC1_DAT0 | MFP_PULL_HIGH,
+        GPIO136_MMC1_CMD | MFP_PULL_HIGH,
+        GPIO139_MMC1_CLK,
+        GPIO140_MMC1_CD | MFP_PULL_LOW,
+        GPIO141_MMC1_WP | MFP_PULL_LOW,
+
+        /* MMC1 */
+        GPIO37_MMC2_DAT3 | MFP_PULL_HIGH,
+        GPIO38_MMC2_DAT2 | MFP_PULL_HIGH,
+        GPIO39_MMC2_DAT1 | MFP_PULL_HIGH,
+        GPIO40_MMC2_DAT0 | MFP_PULL_HIGH,
+        GPIO41_MMC2_CMD | MFP_PULL_HIGH,
+        GPIO42_MMC2_CLK,
+
+        /* MMC2 */
+        GPIO165_MMC3_DAT7 | MFP_PULL_HIGH,
+        GPIO162_MMC3_DAT6 | MFP_PULL_HIGH,
+        GPIO166_MMC3_DAT5 | MFP_PULL_HIGH,
+        GPIO163_MMC3_DAT4 | MFP_PULL_HIGH,
+        GPIO167_MMC3_DAT3 | MFP_PULL_HIGH,
+        GPIO164_MMC3_DAT2 | MFP_PULL_HIGH,
+        GPIO168_MMC3_DAT1 | MFP_PULL_HIGH,
+        GPIO111_MMC3_DAT0 | MFP_PULL_HIGH,
+        GPIO112_MMC3_CMD | MFP_PULL_HIGH,
+        GPIO151_MMC3_CLK,
+
+        /* 5V regulator */
+        GPIO89_GPIO,
+};
+
+static struct regulator_consumer_supply max8649_supply[] = {
+        REGULATOR_SUPPLY("vcc_core", NULL),
+};
+
+static struct regulator_init_data max8649_init_data = {
+        .constraints    = {
+                .name           = "vcc_core range",
+                .min_uV         = 1150000,
+                .max_uV         = 1280000,
+                .always_on      = 1,
+                .boot_on        = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &max8649_supply[0],
+};
+
+static struct max8649_platform_data brownstone_max8649_info = {
+        .mode           = 2,    /* VID1 = 1, VID0 = 0 */
+        .extclk         = 0,
+        .ramp_timing    = MAX8649_RAMP_32MV,
+        .regulator      = &max8649_init_data,
+};
+
+static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = {
+        REGULATOR_SUPPLY("v_5vp", NULL),
+};
+
+static struct regulator_init_data brownstone_v_5vp_data = {
+        .constraints    = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(brownstone_v_5vp_supplies),
+        .consumer_supplies      = brownstone_v_5vp_supplies,
+};
+
+static struct fixed_voltage_config brownstone_v_5vp = {
+        .supply_name            = "v_5vp",
+        .microvolts             = 5000000,
+        .gpio                   = GPIO_5V_ENABLE,
+        .enable_high            = 1,
+        .enabled_at_boot        = 1,
+        .init_data              = &brownstone_v_5vp_data,
+};
+
+static struct platform_device brownstone_v_5vp_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data = &brownstone_v_5vp,
+        },
+};
+
+static struct max8925_platform_data brownstone_max8925_info = {
+        .irq_base               = IRQ_BOARD_START,
+};
+
+static struct i2c_board_info brownstone_twsi1_info[] = {
+        [0] = {
+                .type           = "max8649",
+                .addr           = 0x60,
+                .platform_data  = &brownstone_max8649_info,
+        },
+        [1] = {
+                .type           = "max8925",
+                .addr           = 0x3c,
+                .irq            = IRQ_MMP2_PMIC,
+                .platform_data  = &brownstone_max8925_info,
+        },
+};
+
+static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
+        .max_speed      = 25000000,
+};
+
+static void __init brownstone_init(void)
+{
+        mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
+
+        /* on-chip devices */
+        mmp2_add_uart(1);
+        mmp2_add_uart(3);
+        mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
+        mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
+
+        /* enable 5v regulator */
+        platform_device_register(&brownstone_v_5vp_device);
+}
+
+MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
+        /* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */
+        .map_io         = mmp_map_io,
+        .nr_irqs        = BROWNSTONE_NR_IRQS,
+        .init_irq       = mmp2_init_irq,
+        .timer          = &mmp2_timer,
+        .init_machine   = brownstone_init,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
index 016ae94691c0..9b027d7491f5 100644
--- a/arch/arm/mach-mmp/clock.h
+++ b/arch/arm/mach-mmp/clock.h
@@ -6,7 +6,7 @@
  *  published by the Free Software Foundation.
  */
 
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 struct clkops {
         void                    (*enable)(struct clk *);
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index bdeb6db4d49a..c4fd806b15b4 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -47,7 +47,7 @@ static unsigned long flint_pin_config[] __initdata = {
         GPIO113_SMC_RDY,
 
         /*Ethernet*/
-        GPIO155_GPIO155,
+        GPIO155_GPIO,
 
         /* DFI */
         GPIO168_DFI_D0,
diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
index 761c2dacc079..117e30366087 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
@@ -9,175 +9,175 @@
 #define MFP_DRIVE_FAST          (0x8 << 13)
 
 /* GPIO */
-#define GPIO0_GPIO0             MFP_CFG(GPIO0, AF0)
-#define GPIO1_GPIO1             MFP_CFG(GPIO1, AF0)
-#define GPIO2_GPIO2             MFP_CFG(GPIO2, AF0)
-#define GPIO3_GPIO3             MFP_CFG(GPIO3, AF0)
-#define GPIO4_GPIO4             MFP_CFG(GPIO4, AF0)
-#define GPIO5_GPIO5             MFP_CFG(GPIO5, AF0)
-#define GPIO6_GPIO6             MFP_CFG(GPIO6, AF0)
-#define GPIO7_GPIO7             MFP_CFG(GPIO7, AF0)
-#define GPIO8_GPIO8             MFP_CFG(GPIO8, AF0)
-#define GPIO9_GPIO9             MFP_CFG(GPIO9, AF0)
-#define GPIO10_GPIO10           MFP_CFG(GPIO10, AF0)
-#define GPIO11_GPIO11           MFP_CFG(GPIO11, AF0)
-#define GPIO12_GPIO12           MFP_CFG(GPIO12, AF0)
-#define GPIO13_GPIO13           MFP_CFG(GPIO13, AF0)
-#define GPIO14_GPIO14           MFP_CFG(GPIO14, AF0)
-#define GPIO15_GPIO15           MFP_CFG(GPIO15, AF0)
-#define GPIO16_GPIO16           MFP_CFG(GPIO16, AF0)
-#define GPIO17_GPIO17           MFP_CFG(GPIO17, AF0)
-#define GPIO18_GPIO18           MFP_CFG(GPIO18, AF0)
-#define GPIO19_GPIO19           MFP_CFG(GPIO19, AF0)
-#define GPIO20_GPIO20           MFP_CFG(GPIO20, AF0)
-#define GPIO21_GPIO21           MFP_CFG(GPIO21, AF0)
-#define GPIO22_GPIO22           MFP_CFG(GPIO22, AF0)
-#define GPIO23_GPIO23           MFP_CFG(GPIO23, AF0)
-#define GPIO24_GPIO24           MFP_CFG(GPIO24, AF0)
-#define GPIO25_GPIO25           MFP_CFG(GPIO25, AF0)
-#define GPIO26_GPIO26           MFP_CFG(GPIO26, AF0)
-#define GPIO27_GPIO27           MFP_CFG(GPIO27, AF0)
-#define GPIO28_GPIO28           MFP_CFG(GPIO28, AF0)
-#define GPIO29_GPIO29           MFP_CFG(GPIO29, AF0)
-#define GPIO30_GPIO30           MFP_CFG(GPIO30, AF0)
-#define GPIO31_GPIO31           MFP_CFG(GPIO31, AF0)
-#define GPIO32_GPIO32           MFP_CFG(GPIO32, AF0)
-#define GPIO33_GPIO33           MFP_CFG(GPIO33, AF0)
-#define GPIO34_GPIO34           MFP_CFG(GPIO34, AF0)
-#define GPIO35_GPIO35           MFP_CFG(GPIO35, AF0)
-#define GPIO36_GPIO36           MFP_CFG(GPIO36, AF0)
-#define GPIO37_GPIO37           MFP_CFG(GPIO37, AF0)
-#define GPIO38_GPIO38           MFP_CFG(GPIO38, AF0)
-#define GPIO39_GPIO39           MFP_CFG(GPIO39, AF0)
-#define GPIO40_GPIO40           MFP_CFG(GPIO40, AF0)
-#define GPIO41_GPIO41           MFP_CFG(GPIO41, AF0)
-#define GPIO42_GPIO42           MFP_CFG(GPIO42, AF0)
-#define GPIO43_GPIO43           MFP_CFG(GPIO43, AF0)
-#define GPIO44_GPIO44           MFP_CFG(GPIO44, AF0)
-#define GPIO45_GPIO45           MFP_CFG(GPIO45, AF0)
-#define GPIO46_GPIO46           MFP_CFG(GPIO46, AF0)
-#define GPIO47_GPIO47           MFP_CFG(GPIO47, AF0)
-#define GPIO48_GPIO48           MFP_CFG(GPIO48, AF0)
-#define GPIO49_GPIO49           MFP_CFG(GPIO49, AF0)
-#define GPIO50_GPIO50           MFP_CFG(GPIO50, AF0)
-#define GPIO51_GPIO51           MFP_CFG(GPIO51, AF0)
-#define GPIO52_GPIO52           MFP_CFG(GPIO52, AF0)
-#define GPIO53_GPIO53           MFP_CFG(GPIO53, AF0)
-#define GPIO54_GPIO54           MFP_CFG(GPIO54, AF0)
-#define GPIO55_GPIO55           MFP_CFG(GPIO55, AF0)
-#define GPIO56_GPIO56           MFP_CFG(GPIO56, AF0)
-#define GPIO57_GPIO57           MFP_CFG(GPIO57, AF0)
-#define GPIO58_GPIO58           MFP_CFG(GPIO58, AF0)
-#define GPIO59_GPIO59           MFP_CFG(GPIO59, AF0)
-#define GPIO60_GPIO60           MFP_CFG(GPIO60, AF0)
-#define GPIO61_GPIO61           MFP_CFG(GPIO61, AF0)
-#define GPIO62_GPIO62           MFP_CFG(GPIO62, AF0)
-#define GPIO63_GPIO63           MFP_CFG(GPIO63, AF0)
-#define GPIO64_GPIO64           MFP_CFG(GPIO64, AF0)
-#define GPIO65_GPIO65           MFP_CFG(GPIO65, AF0)
-#define GPIO66_GPIO66           MFP_CFG(GPIO66, AF0)
-#define GPIO67_GPIO67           MFP_CFG(GPIO67, AF0)
-#define GPIO68_GPIO68           MFP_CFG(GPIO68, AF0)
-#define GPIO69_GPIO69           MFP_CFG(GPIO69, AF0)
-#define GPIO70_GPIO70           MFP_CFG(GPIO70, AF0)
-#define GPIO71_GPIO71           MFP_CFG(GPIO71, AF0)
-#define GPIO72_GPIO72           MFP_CFG(GPIO72, AF0)
-#define GPIO73_GPIO73           MFP_CFG(GPIO73, AF0)
-#define GPIO74_GPIO74           MFP_CFG(GPIO74, AF0)
-#define GPIO75_GPIO75           MFP_CFG(GPIO75, AF0)
-#define GPIO76_GPIO76           MFP_CFG(GPIO76, AF0)
-#define GPIO77_GPIO77           MFP_CFG(GPIO77, AF0)
-#define GPIO78_GPIO78           MFP_CFG(GPIO78, AF0)
-#define GPIO79_GPIO79           MFP_CFG(GPIO79, AF0)
-#define GPIO80_GPIO80           MFP_CFG(GPIO80, AF0)
-#define GPIO81_GPIO81           MFP_CFG(GPIO81, AF0)
-#define GPIO82_GPIO82           MFP_CFG(GPIO82, AF0)
-#define GPIO83_GPIO83           MFP_CFG(GPIO83, AF0)
-#define GPIO84_GPIO84           MFP_CFG(GPIO84, AF0)
-#define GPIO85_GPIO85           MFP_CFG(GPIO85, AF0)
-#define GPIO86_GPIO86           MFP_CFG(GPIO86, AF0)
-#define GPIO87_GPIO87           MFP_CFG(GPIO87, AF0)
-#define GPIO88_GPIO88           MFP_CFG(GPIO88, AF0)
-#define GPIO89_GPIO89           MFP_CFG(GPIO89, AF0)
-#define GPIO90_GPIO90           MFP_CFG(GPIO90, AF0)
-#define GPIO91_GPIO91           MFP_CFG(GPIO91, AF0)
-#define GPIO92_GPIO92           MFP_CFG(GPIO92, AF0)
-#define GPIO93_GPIO93           MFP_CFG(GPIO93, AF0)
-#define GPIO94_GPIO94           MFP_CFG(GPIO94, AF0)
-#define GPIO95_GPIO95           MFP_CFG(GPIO95, AF0)
-#define GPIO96_GPIO96           MFP_CFG(GPIO96, AF0)
-#define GPIO97_GPIO97           MFP_CFG(GPIO97, AF0)
-#define GPIO98_GPIO98           MFP_CFG(GPIO98, AF0)
-#define GPIO99_GPIO99           MFP_CFG(GPIO99, AF0)
-#define GPIO100_GPIO100         MFP_CFG(GPIO100, AF0)
-#define GPIO101_GPIO101         MFP_CFG(GPIO101, AF0)
-#define GPIO102_GPIO102         MFP_CFG(GPIO102, AF1)
-#define GPIO103_GPIO103         MFP_CFG(GPIO103, AF1)
-#define GPIO104_GPIO104         MFP_CFG(GPIO104, AF1)
-#define GPIO105_GPIO105         MFP_CFG(GPIO105, AF1)
-#define GPIO106_GPIO106         MFP_CFG(GPIO106, AF1)
-#define GPIO107_GPIO107         MFP_CFG(GPIO107, AF1)
-#define GPIO108_GPIO108         MFP_CFG(GPIO108, AF1)
-#define GPIO109_GPIO109         MFP_CFG(GPIO109, AF1)
-#define GPIO110_GPIO110         MFP_CFG(GPIO110, AF1)
-#define GPIO111_GPIO111         MFP_CFG(GPIO111, AF1)
-#define GPIO112_GPIO112         MFP_CFG(GPIO112, AF1)
-#define GPIO113_GPIO113         MFP_CFG(GPIO113, AF1)
-#define GPIO114_GPIO114         MFP_CFG(GPIO114, AF0)
-#define GPIO115_GPIO115         MFP_CFG(GPIO115, AF0)
-#define GPIO116_GPIO116         MFP_CFG(GPIO116, AF0)
-#define GPIO117_GPIO117         MFP_CFG(GPIO117, AF0)
-#define GPIO118_GPIO118         MFP_CFG(GPIO118, AF0)
-#define GPIO119_GPIO119         MFP_CFG(GPIO119, AF0)
-#define GPIO120_GPIO120         MFP_CFG(GPIO120, AF0)
-#define GPIO121_GPIO121         MFP_CFG(GPIO121, AF0)
-#define GPIO122_GPIO122         MFP_CFG(GPIO122, AF0)
-#define GPIO123_GPIO123         MFP_CFG(GPIO123, AF0)
-#define GPIO124_GPIO124         MFP_CFG(GPIO124, AF0)
-#define GPIO125_GPIO125         MFP_CFG(GPIO125, AF0)
-#define GPIO126_GPIO126         MFP_CFG(GPIO126, AF0)
-#define GPIO127_GPIO127         MFP_CFG(GPIO127, AF0)
-#define GPIO128_GPIO128         MFP_CFG(GPIO128, AF0)
-#define GPIO129_GPIO129         MFP_CFG(GPIO129, AF0)
-#define GPIO130_GPIO130         MFP_CFG(GPIO130, AF0)
-#define GPIO131_GPIO131         MFP_CFG(GPIO131, AF0)
-#define GPIO132_GPIO132         MFP_CFG(GPIO132, AF0)
-#define GPIO133_GPIO133         MFP_CFG(GPIO133, AF0)
-#define GPIO134_GPIO134         MFP_CFG(GPIO134, AF0)
-#define GPIO135_GPIO135         MFP_CFG(GPIO135, AF0)
-#define GPIO136_GPIO136         MFP_CFG(GPIO136, AF0)
-#define GPIO137_GPIO137         MFP_CFG(GPIO137, AF0)
-#define GPIO138_GPIO138         MFP_CFG(GPIO138, AF0)
-#define GPIO139_GPIO139         MFP_CFG(GPIO139, AF0)
-#define GPIO140_GPIO140         MFP_CFG(GPIO140, AF0)
-#define GPIO141_GPIO141         MFP_CFG(GPIO141, AF0)
-#define GPIO142_GPIO142         MFP_CFG(GPIO142, AF1)
-#define GPIO143_GPIO143         MFP_CFG(GPIO143, AF1)
-#define GPIO144_GPIO144         MFP_CFG(GPIO144, AF1)
-#define GPIO145_GPIO145         MFP_CFG(GPIO145, AF1)
-#define GPIO146_GPIO146         MFP_CFG(GPIO146, AF1)
-#define GPIO147_GPIO147         MFP_CFG(GPIO147, AF1)
-#define GPIO148_GPIO148         MFP_CFG(GPIO148, AF1)
-#define GPIO149_GPIO149         MFP_CFG(GPIO149, AF1)
-#define GPIO150_GPIO150         MFP_CFG(GPIO150, AF1)
-#define GPIO151_GPIO151         MFP_CFG(GPIO151, AF1)
-#define GPIO152_GPIO152         MFP_CFG(GPIO152, AF1)
-#define GPIO153_GPIO153         MFP_CFG(GPIO153, AF1)
-#define GPIO154_GPIO154         MFP_CFG(GPIO154, AF1)
-#define GPIO155_GPIO155         MFP_CFG(GPIO155, AF1)
-#define GPIO156_GPIO156         MFP_CFG(GPIO156, AF1)
-#define GPIO157_GPIO157         MFP_CFG(GPIO157, AF1)
-#define GPIO158_GPIO158         MFP_CFG(GPIO158, AF1)
-#define GPIO159_GPIO159         MFP_CFG(GPIO159, AF1)
-#define GPIO160_GPIO160         MFP_CFG(GPIO160, AF1)
-#define GPIO161_GPIO161         MFP_CFG(GPIO161, AF1)
-#define GPIO162_GPIO162         MFP_CFG(GPIO162, AF1)
-#define GPIO163_GPIO163         MFP_CFG(GPIO163, AF1)
-#define GPIO164_GPIO164         MFP_CFG(GPIO164, AF1)
-#define GPIO165_GPIO165         MFP_CFG(GPIO165, AF1)
-#define GPIO166_GPIO166         MFP_CFG(GPIO166, AF1)
-#define GPIO167_GPIO167         MFP_CFG(GPIO167, AF1)
-#define GPIO168_GPIO168         MFP_CFG(GPIO168, AF1)
+#define GPIO0_GPIO      MFP_CFG(GPIO0, AF0)
+#define GPIO1_GPIO      MFP_CFG(GPIO1, AF0)
+#define GPIO2_GPIO      MFP_CFG(GPIO2, AF0)
+#define GPIO3_GPIO      MFP_CFG(GPIO3, AF0)
+#define GPIO4_GPIO      MFP_CFG(GPIO4, AF0)
+#define GPIO5_GPIO      MFP_CFG(GPIO5, AF0)
+#define GPIO6_GPIO      MFP_CFG(GPIO6, AF0)
+#define GPIO7_GPIO      MFP_CFG(GPIO7, AF0)
+#define GPIO8_GPIO      MFP_CFG(GPIO8, AF0)
+#define GPIO9_GPIO      MFP_CFG(GPIO9, AF0)
+#define GPIO10_GPIO     MFP_CFG(GPIO10, AF0)
+#define GPIO11_GPIO     MFP_CFG(GPIO11, AF0)
+#define GPIO12_GPIO     MFP_CFG(GPIO12, AF0)
+#define GPIO13_GPIO     MFP_CFG(GPIO13, AF0)
+#define GPIO14_GPIO     MFP_CFG(GPIO14, AF0)
+#define GPIO15_GPIO     MFP_CFG(GPIO15, AF0)
+#define GPIO16_GPIO     MFP_CFG(GPIO16, AF0)
+#define GPIO17_GPIO     MFP_CFG(GPIO17, AF0)
+#define GPIO18_GPIO     MFP_CFG(GPIO18, AF0)
+#define GPIO19_GPIO     MFP_CFG(GPIO19, AF0)
+#define GPIO20_GPIO     MFP_CFG(GPIO20, AF0)
+#define GPIO21_GPIO     MFP_CFG(GPIO21, AF0)
+#define GPIO22_GPIO     MFP_CFG(GPIO22, AF0)
+#define GPIO23_GPIO     MFP_CFG(GPIO23, AF0)
+#define GPIO24_GPIO     MFP_CFG(GPIO24, AF0)
+#define GPIO25_GPIO     MFP_CFG(GPIO25, AF0)
+#define GPIO26_GPIO     MFP_CFG(GPIO26, AF0)
+#define GPIO27_GPIO     MFP_CFG(GPIO27, AF0)
+#define GPIO28_GPIO     MFP_CFG(GPIO28, AF0)
+#define GPIO29_GPIO     MFP_CFG(GPIO29, AF0)
+#define GPIO30_GPIO     MFP_CFG(GPIO30, AF0)
+#define GPIO31_GPIO     MFP_CFG(GPIO31, AF0)
+#define GPIO32_GPIO     MFP_CFG(GPIO32, AF0)
+#define GPIO33_GPIO     MFP_CFG(GPIO33, AF0)
+#define GPIO34_GPIO     MFP_CFG(GPIO34, AF0)
+#define GPIO35_GPIO     MFP_CFG(GPIO35, AF0)
+#define GPIO36_GPIO     MFP_CFG(GPIO36, AF0)
+#define GPIO37_GPIO     MFP_CFG(GPIO37, AF0)
+#define GPIO38_GPIO     MFP_CFG(GPIO38, AF0)
+#define GPIO39_GPIO     MFP_CFG(GPIO39, AF0)
+#define GPIO40_GPIO     MFP_CFG(GPIO40, AF0)
+#define GPIO41_GPIO     MFP_CFG(GPIO41, AF0)
+#define GPIO42_GPIO     MFP_CFG(GPIO42, AF0)
+#define GPIO43_GPIO     MFP_CFG(GPIO43, AF0)
+#define GPIO44_GPIO     MFP_CFG(GPIO44, AF0)
+#define GPIO45_GPIO     MFP_CFG(GPIO45, AF0)
+#define GPIO46_GPIO     MFP_CFG(GPIO46, AF0)
+#define GPIO47_GPIO     MFP_CFG(GPIO47, AF0)
+#define GPIO48_GPIO     MFP_CFG(GPIO48, AF0)
+#define GPIO49_GPIO     MFP_CFG(GPIO49, AF0)
+#define GPIO50_GPIO     MFP_CFG(GPIO50, AF0)
+#define GPIO51_GPIO     MFP_CFG(GPIO51, AF0)
+#define GPIO52_GPIO     MFP_CFG(GPIO52, AF0)
+#define GPIO53_GPIO     MFP_CFG(GPIO53, AF0)
+#define GPIO54_GPIO     MFP_CFG(GPIO54, AF0)
+#define GPIO55_GPIO     MFP_CFG(GPIO55, AF0)
+#define GPIO56_GPIO     MFP_CFG(GPIO56, AF0)
+#define GPIO57_GPIO     MFP_CFG(GPIO57, AF0)
+#define GPIO58_GPIO     MFP_CFG(GPIO58, AF0)
+#define GPIO59_GPIO     MFP_CFG(GPIO59, AF0)
+#define GPIO60_GPIO     MFP_CFG(GPIO60, AF0)
+#define GPIO61_GPIO     MFP_CFG(GPIO61, AF0)
+#define GPIO62_GPIO     MFP_CFG(GPIO62, AF0)
+#define GPIO63_GPIO     MFP_CFG(GPIO63, AF0)
+#define GPIO64_GPIO     MFP_CFG(GPIO64, AF0)
+#define GPIO65_GPIO     MFP_CFG(GPIO65, AF0)
+#define GPIO66_GPIO     MFP_CFG(GPIO66, AF0)
+#define GPIO67_GPIO     MFP_CFG(GPIO67, AF0)
+#define GPIO68_GPIO     MFP_CFG(GPIO68, AF0)
+#define GPIO69_GPIO     MFP_CFG(GPIO69, AF0)
+#define GPIO70_GPIO     MFP_CFG(GPIO70, AF0)
+#define GPIO71_GPIO     MFP_CFG(GPIO71, AF0)
+#define GPIO72_GPIO     MFP_CFG(GPIO72, AF0)
+#define GPIO73_GPIO     MFP_CFG(GPIO73, AF0)
+#define GPIO74_GPIO     MFP_CFG(GPIO74, AF0)
+#define GPIO75_GPIO     MFP_CFG(GPIO75, AF0)
+#define GPIO76_GPIO     MFP_CFG(GPIO76, AF0)
+#define GPIO77_GPIO     MFP_CFG(GPIO77, AF0)
+#define GPIO78_GPIO     MFP_CFG(GPIO78, AF0)
+#define GPIO79_GPIO     MFP_CFG(GPIO79, AF0)
+#define GPIO80_GPIO     MFP_CFG(GPIO80, AF0)
+#define GPIO81_GPIO     MFP_CFG(GPIO81, AF0)
+#define GPIO82_GPIO     MFP_CFG(GPIO82, AF0)
+#define GPIO83_GPIO     MFP_CFG(GPIO83, AF0)
+#define GPIO84_GPIO     MFP_CFG(GPIO84, AF0)
+#define GPIO85_GPIO     MFP_CFG(GPIO85, AF0)
+#define GPIO86_GPIO     MFP_CFG(GPIO86, AF0)
+#define GPIO87_GPIO     MFP_CFG(GPIO87, AF0)
+#define GPIO88_GPIO     MFP_CFG(GPIO88, AF0)
+#define GPIO89_GPIO     MFP_CFG(GPIO89, AF0)
+#define GPIO90_GPIO     MFP_CFG(GPIO90, AF0)
+#define GPIO91_GPIO     MFP_CFG(GPIO91, AF0)
+#define GPIO92_GPIO     MFP_CFG(GPIO92, AF0)
+#define GPIO93_GPIO     MFP_CFG(GPIO93, AF0)
+#define GPIO94_GPIO     MFP_CFG(GPIO94, AF0)
+#define GPIO95_GPIO     MFP_CFG(GPIO95, AF0)
+#define GPIO96_GPIO     MFP_CFG(GPIO96, AF0)
+#define GPIO97_GPIO     MFP_CFG(GPIO97, AF0)
+#define GPIO98_GPIO     MFP_CFG(GPIO98, AF0)
+#define GPIO99_GPIO     MFP_CFG(GPIO99, AF0)
+#define GPIO100_GPIO    MFP_CFG(GPIO100, AF0)
+#define GPIO101_GPIO    MFP_CFG(GPIO101, AF0)
+#define GPIO102_GPIO    MFP_CFG(GPIO102, AF1)
+#define GPIO103_GPIO    MFP_CFG(GPIO103, AF1)
+#define GPIO104_GPIO    MFP_CFG(GPIO104, AF1)
+#define GPIO105_GPIO    MFP_CFG(GPIO105, AF1)
+#define GPIO106_GPIO    MFP_CFG(GPIO106, AF1)
+#define GPIO107_GPIO    MFP_CFG(GPIO107, AF1)
+#define GPIO108_GPIO    MFP_CFG(GPIO108, AF1)
+#define GPIO109_GPIO    MFP_CFG(GPIO109, AF1)
+#define GPIO110_GPIO    MFP_CFG(GPIO110, AF1)
+#define GPIO111_GPIO    MFP_CFG(GPIO111, AF1)
+#define GPIO112_GPIO    MFP_CFG(GPIO112, AF1)
+#define GPIO113_GPIO    MFP_CFG(GPIO113, AF1)
+#define GPIO114_GPIO    MFP_CFG(GPIO114, AF0)
+#define GPIO115_GPIO    MFP_CFG(GPIO115, AF0)
+#define GPIO116_GPIO    MFP_CFG(GPIO116, AF0)
+#define GPIO117_GPIO    MFP_CFG(GPIO117, AF0)
+#define GPIO118_GPIO    MFP_CFG(GPIO118, AF0)
+#define GPIO119_GPIO    MFP_CFG(GPIO119, AF0)
+#define GPIO120_GPIO    MFP_CFG(GPIO120, AF0)
+#define GPIO121_GPIO    MFP_CFG(GPIO121, AF0)
+#define GPIO122_GPIO    MFP_CFG(GPIO122, AF0)
+#define GPIO123_GPIO    MFP_CFG(GPIO123, AF0)
+#define GPIO124_GPIO    MFP_CFG(GPIO124, AF0)
+#define GPIO125_GPIO    MFP_CFG(GPIO125, AF0)
+#define GPIO126_GPIO    MFP_CFG(GPIO126, AF0)
+#define GPIO127_GPIO    MFP_CFG(GPIO127, AF0)
+#define GPIO128_GPIO    MFP_CFG(GPIO128, AF0)
+#define GPIO129_GPIO    MFP_CFG(GPIO129, AF0)
+#define GPIO130_GPIO    MFP_CFG(GPIO130, AF0)
+#define GPIO131_GPIO    MFP_CFG(GPIO131, AF0)
+#define GPIO132_GPIO    MFP_CFG(GPIO132, AF0)
+#define GPIO133_GPIO    MFP_CFG(GPIO133, AF0)
+#define GPIO134_GPIO    MFP_CFG(GPIO134, AF0)
+#define GPIO135_GPIO    MFP_CFG(GPIO135, AF0)
+#define GPIO136_GPIO    MFP_CFG(GPIO136, AF0)
+#define GPIO137_GPIO    MFP_CFG(GPIO137, AF0)
+#define GPIO138_GPIO    MFP_CFG(GPIO138, AF0)
+#define GPIO139_GPIO    MFP_CFG(GPIO139, AF0)
+#define GPIO140_GPIO    MFP_CFG(GPIO140, AF0)
+#define GPIO141_GPIO    MFP_CFG(GPIO141, AF0)
+#define GPIO142_GPIO    MFP_CFG(GPIO142, AF1)
+#define GPIO143_GPIO    MFP_CFG(GPIO143, AF1)
+#define GPIO144_GPIO    MFP_CFG(GPIO144, AF1)
+#define GPIO145_GPIO    MFP_CFG(GPIO145, AF1)
+#define GPIO146_GPIO    MFP_CFG(GPIO146, AF1)
+#define GPIO147_GPIO    MFP_CFG(GPIO147, AF1)
+#define GPIO148_GPIO    MFP_CFG(GPIO148, AF1)
+#define GPIO149_GPIO    MFP_CFG(GPIO149, AF1)
+#define GPIO150_GPIO    MFP_CFG(GPIO150, AF1)
+#define GPIO151_GPIO    MFP_CFG(GPIO151, AF1)
+#define GPIO152_GPIO    MFP_CFG(GPIO152, AF1)
+#define GPIO153_GPIO    MFP_CFG(GPIO153, AF1)
+#define GPIO154_GPIO    MFP_CFG(GPIO154, AF1)
+#define GPIO155_GPIO    MFP_CFG(GPIO155, AF1)
+#define GPIO156_GPIO    MFP_CFG(GPIO156, AF1)
+#define GPIO157_GPIO    MFP_CFG(GPIO157, AF1)
+#define GPIO158_GPIO    MFP_CFG(GPIO158, AF1)
+#define GPIO159_GPIO    MFP_CFG(GPIO159, AF1)
+#define GPIO160_GPIO    MFP_CFG(GPIO160, AF1)
+#define GPIO161_GPIO    MFP_CFG(GPIO161, AF1)
+#define GPIO162_GPIO    MFP_CFG(GPIO162, AF1)
+#define GPIO163_GPIO    MFP_CFG(GPIO163, AF1)
+#define GPIO164_GPIO    MFP_CFG(GPIO164, AF1)
+#define GPIO165_GPIO    MFP_CFG(GPIO165, AF1)
+#define GPIO166_GPIO    MFP_CFG(GPIO166, AF1)
+#define GPIO167_GPIO    MFP_CFG(GPIO167, AF1)
+#define GPIO168_GPIO    MFP_CFG(GPIO168, AF1)
 
 /* DFI */
 #define GPIO108_DFI_D15         MFP_CFG(GPIO108, AF0)
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index dbba6e8a60c4..4aec493640b4 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_MACH_MMP2_H
 #define __ASM_MACH_MMP2_H
 
+#include <plat/sdhci.h>
+
 struct sys_timer;
 
 extern struct sys_timer mmp2_timer;
@@ -22,6 +24,10 @@ extern struct pxa_device_desc mmp2_device_twsi3;
 extern struct pxa_device_desc mmp2_device_twsi4;
 extern struct pxa_device_desc mmp2_device_twsi5;
 extern struct pxa_device_desc mmp2_device_twsi6;
+extern struct pxa_device_desc mmp2_device_sdh0;
+extern struct pxa_device_desc mmp2_device_sdh1;
+extern struct pxa_device_desc mmp2_device_sdh2;
+extern struct pxa_device_desc mmp2_device_sdh3;
 
 static inline int mmp2_add_uart(int id)
 {
@@ -63,5 +69,21 @@ static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data,
         return pxa_register_device(d, data, sizeof(*data));
 }
 
+static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data)
+{
+        struct pxa_device_desc *d = NULL;
+
+        switch (id) {
+        case 0: d = &mmp2_device_sdh0; break;
+        case 1: d = &mmp2_device_sdh1; break;
+        case 2: d = &mmp2_device_sdh2; break;
+        case 3: d = &mmp2_device_sdh3; break;
+        default:
+                return -EINVAL;
+        }
+
+        return pxa_register_device(d, data, sizeof(*data));
+}
+
 #endif /* __ASM_MACH_MMP2_H */
 
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index ac4702357a6e..f7011ef70bf5 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -27,6 +27,8 @@
 #define APMU_DMA        APMU_REG(0x064)
 #define APMU_GEU        APMU_REG(0x068)
 #define APMU_BUS        APMU_REG(0x06c)
+#define APMU_SDH2       APMU_REG(0x0e8)
+#define APMU_SDH3       APMU_REG(0x0ec)
 
 #define APMU_FNCLK_EN   (1 << 4)
 #define APMU_AXICLK_EN  (1 << 3)
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 2a684fa50773..24172a0aad59 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -67,6 +67,36 @@ static unsigned long jasper_pin_config[] __initdata = {
 
         /* PMIC */
         PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
+
+        /* MMC1 */
+        GPIO131_MMC1_DAT3,
+        GPIO132_MMC1_DAT2,
+        GPIO133_MMC1_DAT1,
+        GPIO134_MMC1_DAT0,
+        GPIO136_MMC1_CMD,
+        GPIO139_MMC1_CLK,
+        GPIO140_MMC1_CD,
+        GPIO141_MMC1_WP,
+
+        /* MMC2 */
+        GPIO37_MMC2_DAT3,
+        GPIO38_MMC2_DAT2,
+        GPIO39_MMC2_DAT1,
+        GPIO40_MMC2_DAT0,
+        GPIO41_MMC2_CMD,
+        GPIO42_MMC2_CLK,
+
+        /* MMC3 */
+        GPIO165_MMC3_DAT7,
+        GPIO162_MMC3_DAT6,
+        GPIO166_MMC3_DAT5,
+        GPIO163_MMC3_DAT4,
+        GPIO167_MMC3_DAT3,
+        GPIO164_MMC3_DAT2,
+        GPIO168_MMC3_DAT1,
+        GPIO111_MMC3_DAT0,
+        GPIO112_MMC3_CMD,
+        GPIO151_MMC3_CLK,
 };
 
 static struct regulator_consumer_supply max8649_supply[] = {
@@ -123,6 +153,10 @@ static struct i2c_board_info jasper_twsi1_info[] = {
         },
 };
 
+static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
+        .max_speed      = 25000000,
+};
+
 static void __init jasper_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(jasper_pin_config));
@@ -131,6 +165,7 @@ static void __init jasper_init(void)
         mmp2_add_uart(1);
         mmp2_add_uart(3);
         mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
+        mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
 
         regulator_has_full_constraints();
 }
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 2e3dd08ccc3f..8e6c3ac7f7c1 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -115,6 +115,29 @@ void __init mmp2_init_irq(void)
         mmp2_init_gpio();
 }
 
+static void sdhc_clk_enable(struct clk *clk)
+{
+        uint32_t clk_rst;
+
+        clk_rst  =  __raw_readl(clk->clk_rst);
+        clk_rst |= clk->enable_val;
+        __raw_writel(clk_rst, clk->clk_rst);
+}
+
+static void sdhc_clk_disable(struct clk *clk)
+{
+        uint32_t clk_rst;
+
+        clk_rst  =  __raw_readl(clk->clk_rst);
+        clk_rst &= ~clk->enable_val;
+        __raw_writel(clk_rst, clk->clk_rst);
+}
+
+struct clkops sdhc_clk_ops = {
+        .enable         = sdhc_clk_enable,
+        .disable        = sdhc_clk_disable,
+};
+
 /* APB peripheral clocks */
 static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
 static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
@@ -128,6 +151,10 @@ static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
 static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
 
 static APMU_CLK(nand, NAND, 0xbf, 100000000);
+static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
 
 static struct clk_lookup mmp2_clkregs[] = {
         INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
@@ -141,6 +168,10 @@ static struct clk_lookup mmp2_clkregs[] = {
         INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
         INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_sdh0, "sdhci-pxa.0", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh1, "sdhci-pxa.1", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh2, "sdhci-pxa.2", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh3, "sdhci-pxa.3", "PXA-SDHCLK"),
 };
 
 static int __init mmp2_init(void)
@@ -191,4 +222,8 @@ MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
 MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
 MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
 MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
+MMP2_DEVICE(sdh0, "sdhci-pxa", 0, MMC, 0xd4280000, 0x120);
+MMP2_DEVICE(sdh1, "sdhci-pxa", 1, MMC2, 0xd4280800, 0x120);
+MMP2_DEVICE(sdh2, "sdhci-pxa", 2, MMC3, 0xd4281000, 0x120);
+MMP2_DEVICE(sdh3, "sdhci-pxa", 3, MMC4, 0xd4281800, 0x120);
 
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 46f2d69bef3c..8f92ccd26edf 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -111,6 +111,7 @@ static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
 
 static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(u2o, USB, 0x1b, 480000000);
 
 /* device and clock bindings */
 static struct clk_lookup pxa910_clkregs[] = {
@@ -123,6 +124,7 @@ static struct clk_lookup pxa910_clkregs[] = {
         INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
         INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
 };
 
 static int __init pxa910_init(void)
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 66528193f939..aeb9ae23e6ce 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -26,8 +26,8 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/sched.h>
-#include <linux/cnt32_to_63.h>
 
+#include <asm/sched_clock.h>
 #include <mach/addr-map.h>
 #include <mach/regs-timers.h>
 #include <mach/regs-apbc.h>
@@ -42,23 +42,7 @@
 #define MAX_DELTA               (0xfffffffe)
 #define MIN_DELTA               (16)
 
-#define TCR2NS_SCALE_FACTOR     10
-
-static unsigned long tcr2ns_scale;
-
-static void __init set_tcr2ns_scale(unsigned long tcr_rate)
-{
-        unsigned long long v = 1000000000ULL << TCR2NS_SCALE_FACTOR;
-        do_div(v, tcr_rate);
-        tcr2ns_scale = v;
-        /*
-         * We want an even value to automatically clear the top bit
-         * returned by cnt32_to_63() without an additional run time
-         * instruction. So if the LSB is 1 then round it up.
-         */
-        if (tcr2ns_scale & 1)
-                tcr2ns_scale++;
-}
+static DEFINE_CLOCK_DATA(cd);
 
 /*
  * FIXME: the timer needs some delay to stablize the counter capture
@@ -75,10 +59,16 @@ static inline uint32_t timer_read(void)
         return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0));
 }
 
-unsigned long long sched_clock(void)
+unsigned long long notrace sched_clock(void)
 {
-        unsigned long long v = cnt32_to_63(timer_read());
-        return (v * tcr2ns_scale) >> TCR2NS_SCALE_FACTOR;
+        u32 cyc = timer_read();
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
+
+static void notrace mmp_update_sched_clock(void)
+{
+        u32 cyc = timer_read();
+        update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 static irqreturn_t timer_interrupt(int irq, void *dev_id)
@@ -146,7 +136,6 @@ static cycle_t clksrc_read(struct clocksource *cs)
 
 static struct clocksource cksrc = {
         .name           = "clocksource",
-        .shift          = 20,
         .rating         = 200,
         .read           = clksrc_read,
         .mask           = CLOCKSOURCE_MASK(32),
@@ -186,17 +175,15 @@ void __init timer_init(int irq)
 {
         timer_config();
 
-        set_tcr2ns_scale(CLOCK_TICK_RATE);
+        init_sched_clock(&cd, mmp_update_sched_clock, 32, CLOCK_TICK_RATE);
 
         ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
         ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
         ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
         ckevt.cpumask = cpumask_of(0);
 
-        cksrc.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc.shift);
-
         setup_irq(irq, &timer_irq);
 
-        clocksource_register(&cksrc);
+        clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
         clockevents_register_device(&ckevt);
 }
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index dbbcfeb919db..5d3d9ade12fb 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -40,15 +40,20 @@ config ARCH_MSM8X60
         bool "MSM8X60"
         select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
                                   && !MACH_MSM8X60_FFA)
+        select ARCH_MSM_SCORPIONMP
         select ARM_GIC
         select CPU_V7
         select MSM_V2_TLMM
         select MSM_GPIOMUX
+        select IOMMU_API
+        select MSM_SCM if SMP
 
 endchoice
 
 config MSM_SOC_REV_A
         bool
+config  ARCH_MSM_SCORPIONMP
+        bool
 
 config  ARCH_MSM_ARM11
         bool
@@ -122,6 +127,10 @@ config MACH_MSM8X60_FFA
 
 endmenu
 
+config IOMMU_PGTABLES_L2
+        def_bool y
+        depends on ARCH_MSM8X60 && MMU && SMP && CPU_DCACHE_DISABLE=n
+
 config MSM_DEBUG_UART
         int
         default 1 if MSM_DEBUG_UART1
@@ -162,4 +171,10 @@ config MSM_GPIOMUX
 
 config MSM_V2_TLMM
         bool
+
+config IOMMU_API
+        bool
+
+config MSM_SCM
+        bool
 endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index b5a7b07a44f5..94195c190e13 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -18,8 +18,13 @@ obj-$(CONFIG_MSM_PROC_COMM) += clock.o
 obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
+obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
+
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 
 obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o
+obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
@@ -28,6 +33,8 @@ obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
 obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
-ifndef CONFIG_MSM_V2_TLMM
+ifdef CONFIG_MSM_V2_TLMM
+obj-y   += gpio-v2.o
+else
 obj-y   += gpio.o
 endif
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 05241df3f9b6..6f3b9735e970 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -22,6 +22,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
+#include <linux/usb/msm_hsusb.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,11 +40,26 @@
 
 extern struct sys_timer msm_timer;
 
+static int hsusb_phy_init_seq[] = {
+        0x30, 0x32,     /* Enable and set Pre-Emphasis Depth to 20% */
+        0x02, 0x36,     /* Disable CDR Auto Reset feature */
+        -1
+};
+
+static struct msm_otg_platform_data msm_otg_pdata = {
+        .phy_init_seq           = hsusb_phy_init_seq,
+        .mode                   = USB_PERIPHERAL,
+        .otg_control            = OTG_PHY_CONTROL,
+};
+
 static struct platform_device *devices[] __initdata = {
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
         &msm_device_uart2,
 #endif
         &msm_device_smd,
+        &msm_device_otg,
+        &msm_device_hsusb,
+        &msm_device_hsusb_host,
 };
 
 static void __init msm7x30_init_irq(void)
@@ -53,6 +69,10 @@ static void __init msm7x30_init_irq(void)
 
 static void __init msm7x30_init(void)
 {
+        msm_device_otg.dev.platform_data = &msm_otg_pdata;
+        msm_device_hsusb.dev.parent = &msm_device_otg.dev;
+        msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
+
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 7486a681cc71..9b5eb2b4ae1b 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -28,8 +28,6 @@
 #include <mach/board.h>
 #include <mach/msm_iomap.h>
 
-void __iomem *gic_cpu_base_addr;
-
 unsigned long clk_get_max_axi_khz(void)
 {
         return 0;
@@ -44,9 +42,8 @@ static void __init msm8x60_init_irq(void)
 {
         unsigned int i;
 
-        gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
-        gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
-        gic_cpu_init(0, MSM_QGIC_CPU_BASE);
+        gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+                 (void *)MSM_QGIC_CPU_BASE);
 
         /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
         writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index ed2af4ad97ed..2e8391307f55 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -20,6 +20,7 @@
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <linux/usb/msm_hsusb.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -74,9 +75,24 @@ static int __init msm_init_smc91x(void)
 }
 module_init(msm_init_smc91x);
 
+static int hsusb_phy_init_seq[] = {
+        0x08, 0x31,     /* Increase HS Driver Amplitude */
+        0x20, 0x32,     /* Enable and set Pre-Emphasis Depth to 10% */
+        -1
+};
+
+static struct msm_otg_platform_data msm_otg_pdata = {
+        .phy_init_seq           = hsusb_phy_init_seq,
+        .mode                   = USB_PERIPHERAL,
+        .otg_control            = OTG_PHY_CONTROL,
+};
+
 static struct platform_device *devices[] __initdata = {
         &msm_device_uart3,
         &msm_device_smd,
+        &msm_device_otg,
+        &msm_device_hsusb,
+        &msm_device_hsusb_host,
 };
 
 static void __init qsd8x50_map_io(void)
@@ -93,6 +109,9 @@ static void __init qsd8x50_init_irq(void)
 
 static void __init qsd8x50_init(void)
 {
+        msm_device_otg.dev.platform_data = &msm_otg_pdata;
+        msm_device_hsusb.dev.parent = &msm_device_otg.dev;
+        msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index c50f3afc3134..f8c09ef6666f 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -72,6 +72,13 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip,
         return 0;
 }
 
+static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
+
+        return TROUT_GPIO_TO_INT(offset + chip->base);
+}
+
 #define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val)           \
         {                                                               \
                 .chip = {                                               \
@@ -80,6 +87,7 @@ static int msm_gpiolib_direction_output(struct gpio_chip *chip,
                         .direction_output = msm_gpiolib_direction_output, \
                         .get              = msm_gpiolib_get,            \
                         .set              = msm_gpiolib_set,            \
+                        .to_irq           = trout_gpio_to_irq,          \
                         .base             = base_gpio,                  \
                         .ngpio            = 8,                          \
                 },                                                      \
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
new file mode 100644
index 000000000000..729bb49a44ca
--- /dev/null
+++ b/arch/arm/mach-msm/board-trout-panel.c
@@ -0,0 +1,297 @@
+/* linux/arch/arm/mach-msm/board-trout-mddi.c
+** Author: Brian Swetland <swetland@google.com>
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/leds.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+
+#include <mach/msm_fb.h>
+#include <mach/vreg.h>
+
+#include "board-trout.h"
+#include "proc_comm.h"
+#include "devices.h"
+
+#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
+
+#define MDDI_CLIENT_CORE_BASE  0x108000
+#define LCD_CONTROL_BLOCK_BASE 0x110000
+#define SPI_BLOCK_BASE         0x120000
+#define I2C_BLOCK_BASE         0x130000
+#define PWM_BLOCK_BASE         0x140000
+#define GPIO_BLOCK_BASE        0x150000
+#define SYSTEM_BLOCK1_BASE     0x160000
+#define SYSTEM_BLOCK2_BASE     0x170000
+
+
+#define DPSUS       (MDDI_CLIENT_CORE_BASE|0x24)
+#define SYSCLKENA   (MDDI_CLIENT_CORE_BASE|0x2C)
+#define PWM0OFF       (PWM_BLOCK_BASE|0x1C)
+
+#define V_VDDE2E_VDD2_GPIO 0
+#define MDDI_RST_N 82
+
+#define MDDICAP0    (MDDI_CLIENT_CORE_BASE|0x00)
+#define MDDICAP1    (MDDI_CLIENT_CORE_BASE|0x04)
+#define MDDICAP2    (MDDI_CLIENT_CORE_BASE|0x08)
+#define MDDICAP3    (MDDI_CLIENT_CORE_BASE|0x0C)
+#define MDCAPCHG    (MDDI_CLIENT_CORE_BASE|0x10)
+#define MDCRCERC    (MDDI_CLIENT_CORE_BASE|0x14)
+#define TTBUSSEL    (MDDI_CLIENT_CORE_BASE|0x18)
+#define DPSET0      (MDDI_CLIENT_CORE_BASE|0x1C)
+#define DPSET1      (MDDI_CLIENT_CORE_BASE|0x20)
+#define DPSUS       (MDDI_CLIENT_CORE_BASE|0x24)
+#define DPRUN       (MDDI_CLIENT_CORE_BASE|0x28)
+#define SYSCKENA    (MDDI_CLIENT_CORE_BASE|0x2C)
+#define TESTMODE    (MDDI_CLIENT_CORE_BASE|0x30)
+#define FIFOMONI    (MDDI_CLIENT_CORE_BASE|0x34)
+#define INTMONI     (MDDI_CLIENT_CORE_BASE|0x38)
+#define MDIOBIST    (MDDI_CLIENT_CORE_BASE|0x3C)
+#define MDIOPSET    (MDDI_CLIENT_CORE_BASE|0x40)
+#define BITMAP0     (MDDI_CLIENT_CORE_BASE|0x44)
+#define BITMAP1     (MDDI_CLIENT_CORE_BASE|0x48)
+#define BITMAP2     (MDDI_CLIENT_CORE_BASE|0x4C)
+#define BITMAP3     (MDDI_CLIENT_CORE_BASE|0x50)
+#define BITMAP4     (MDDI_CLIENT_CORE_BASE|0x54)
+
+#define SRST        (LCD_CONTROL_BLOCK_BASE|0x00)
+#define PORT_ENB    (LCD_CONTROL_BLOCK_BASE|0x04)
+#define START       (LCD_CONTROL_BLOCK_BASE|0x08)
+#define PORT        (LCD_CONTROL_BLOCK_BASE|0x0C)
+#define CMN         (LCD_CONTROL_BLOCK_BASE|0x10)
+#define GAMMA       (LCD_CONTROL_BLOCK_BASE|0x14)
+#define INTFLG      (LCD_CONTROL_BLOCK_BASE|0x18)
+#define INTMSK      (LCD_CONTROL_BLOCK_BASE|0x1C)
+#define MPLFBUF     (LCD_CONTROL_BLOCK_BASE|0x20)
+#define HDE_LEFT    (LCD_CONTROL_BLOCK_BASE|0x24)
+#define VDE_TOP     (LCD_CONTROL_BLOCK_BASE|0x28)
+#define PXL         (LCD_CONTROL_BLOCK_BASE|0x30)
+#define HCYCLE      (LCD_CONTROL_BLOCK_BASE|0x34)
+#define HSW         (LCD_CONTROL_BLOCK_BASE|0x38)
+#define HDE_START   (LCD_CONTROL_BLOCK_BASE|0x3C)
+#define HDE_SIZE    (LCD_CONTROL_BLOCK_BASE|0x40)
+#define VCYCLE      (LCD_CONTROL_BLOCK_BASE|0x44)
+#define VSW         (LCD_CONTROL_BLOCK_BASE|0x48)
+#define VDE_START   (LCD_CONTROL_BLOCK_BASE|0x4C)
+#define VDE_SIZE    (LCD_CONTROL_BLOCK_BASE|0x50)
+#define WAKEUP      (LCD_CONTROL_BLOCK_BASE|0x54)
+#define WSYN_DLY    (LCD_CONTROL_BLOCK_BASE|0x58)
+#define REGENB      (LCD_CONTROL_BLOCK_BASE|0x5C)
+#define VSYNIF      (LCD_CONTROL_BLOCK_BASE|0x60)
+#define WRSTB       (LCD_CONTROL_BLOCK_BASE|0x64)
+#define RDSTB       (LCD_CONTROL_BLOCK_BASE|0x68)
+#define ASY_DATA    (LCD_CONTROL_BLOCK_BASE|0x6C)
+#define ASY_DATB    (LCD_CONTROL_BLOCK_BASE|0x70)
+#define ASY_DATC    (LCD_CONTROL_BLOCK_BASE|0x74)
+#define ASY_DATD    (LCD_CONTROL_BLOCK_BASE|0x78)
+#define ASY_DATE    (LCD_CONTROL_BLOCK_BASE|0x7C)
+#define ASY_DATF    (LCD_CONTROL_BLOCK_BASE|0x80)
+#define ASY_DATG    (LCD_CONTROL_BLOCK_BASE|0x84)
+#define ASY_DATH    (LCD_CONTROL_BLOCK_BASE|0x88)
+#define ASY_CMDSET  (LCD_CONTROL_BLOCK_BASE|0x8C)
+
+#define SSICTL      (SPI_BLOCK_BASE|0x00)
+#define SSITIME     (SPI_BLOCK_BASE|0x04)
+#define SSITX       (SPI_BLOCK_BASE|0x08)
+#define SSIRX       (SPI_BLOCK_BASE|0x0C)
+#define SSIINTC     (SPI_BLOCK_BASE|0x10)
+#define SSIINTS     (SPI_BLOCK_BASE|0x14)
+#define SSIDBG1     (SPI_BLOCK_BASE|0x18)
+#define SSIDBG2     (SPI_BLOCK_BASE|0x1C)
+#define SSIID       (SPI_BLOCK_BASE|0x20)
+
+#define WKREQ       (SYSTEM_BLOCK1_BASE|0x00)
+#define CLKENB      (SYSTEM_BLOCK1_BASE|0x04)
+#define DRAMPWR     (SYSTEM_BLOCK1_BASE|0x08)
+#define INTMASK     (SYSTEM_BLOCK1_BASE|0x0C)
+#define GPIOSEL     (SYSTEM_BLOCK2_BASE|0x00)
+
+#define GPIODATA    (GPIO_BLOCK_BASE|0x00)
+#define GPIODIR     (GPIO_BLOCK_BASE|0x04)
+#define GPIOIS      (GPIO_BLOCK_BASE|0x08)
+#define GPIOIBE     (GPIO_BLOCK_BASE|0x0C)
+#define GPIOIEV     (GPIO_BLOCK_BASE|0x10)
+#define GPIOIE      (GPIO_BLOCK_BASE|0x14)
+#define GPIORIS     (GPIO_BLOCK_BASE|0x18)
+#define GPIOMIS     (GPIO_BLOCK_BASE|0x1C)
+#define GPIOIC      (GPIO_BLOCK_BASE|0x20)
+#define GPIOOMS     (GPIO_BLOCK_BASE|0x24)
+#define GPIOPC      (GPIO_BLOCK_BASE|0x28)
+#define GPIOID      (GPIO_BLOCK_BASE|0x30)
+
+#define SPI_WRITE(reg, val) \
+        { SSITX,        0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
+        { 0, 5 },
+
+#define SPI_WRITE1(reg) \
+        { SSITX,        (reg) & 0xff }, \
+        { 0, 5 },
+
+struct mddi_table {
+        uint32_t reg;
+        uint32_t value;
+};
+static struct mddi_table mddi_toshiba_init_table[] = {
+        { DPSET0,       0x09e90046 },
+        { DPSET1,       0x00000118 },
+        { DPSUS,        0x00000000 },
+        { DPRUN,        0x00000001 },
+        { 1,            14         }, /* msleep 14 */
+        { SYSCKENA,     0x00000001 },
+        { CLKENB,       0x0000A1EF },  /*    # SYS.CLKENB  # Enable clocks for each module (without DCLK , i2cCLK) */
+
+        { GPIODATA,     0x02000200 },  /*   # GPI .GPIODATA  # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
+        { GPIODIR,      0x000030D  },  /* 24D   # GPI .GPIODIR  # Select direction of GPIO port (0,2,3,6,9 output) */
+        { GPIOSEL,      0/*0x00000173*/},  /*   # SYS.GPIOSEL  # GPIO port multiplexing control */
+        { GPIOPC,       0x03C300C0 },  /*   # GPI .GPIOPC  # GPIO2,3 PD cut */
+        { WKREQ,        0x00000000 },  /*   # SYS.WKREQ  # Wake-up request event is VSYNC alignment */
+
+        { GPIOIBE,      0x000003FF },
+        { GPIOIS,       0x00000000 },
+        { GPIOIC,       0x000003FF },
+        { GPIOIE,       0x00000000 },
+
+        { GPIODATA,     0x00040004 },  /*   # GPI .GPIODATA  # eDRAM VD supply */
+        { 1,            1          }, /* msleep 1 */
+        { GPIODATA,     0x02040004 },  /*   # GPI .GPIODATA  # eDRAM VD supply */
+        { DRAMPWR,      0x00000001 }, /* eDRAM power */
+};
+
+#define GPIOSEL_VWAKEINT (1U << 0)
+#define INTMASK_VWAKEOUT (1U << 0)
+
+
+static struct clk *gp_clk;
+static int trout_new_backlight = 1;
+static struct vreg *vreg_mddi_1v5;
+static struct vreg *vreg_lcm_2v85;
+
+static void trout_process_mddi_table(struct msm_mddi_client_data *client_data,
+                                     struct mddi_table *table, size_t count)
+{
+        int i;
+        for (i = 0; i < count; i++) {
+                uint32_t reg = table[i].reg;
+                uint32_t value = table[i].value;
+
+                if (reg == 0)
+                        udelay(value);
+                else if (reg == 1)
+                        msleep(value);
+                else
+                        client_data->remote_write(client_data, value, reg);
+        }
+}
+
+static int trout_mddi_toshiba_client_init(
+        struct msm_mddi_bridge_platform_data *bridge_data,
+        struct msm_mddi_client_data *client_data)
+{
+        int panel_id;
+
+        client_data->auto_hibernate(client_data, 0);
+        trout_process_mddi_table(client_data, mddi_toshiba_init_table,
+                                 ARRAY_SIZE(mddi_toshiba_init_table));
+        client_data->auto_hibernate(client_data, 1);
+        panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
+        if (panel_id > 1) {
+                printk(KERN_WARNING "unknown panel id at mddi_enable\n");
+                return -1;
+        }
+        return 0;
+}
+
+static int trout_mddi_toshiba_client_uninit(
+        struct msm_mddi_bridge_platform_data *bridge_data,
+        struct msm_mddi_client_data *client_data)
+{
+        return 0;
+}
+
+static struct resource resources_msm_fb[] = {
+        {
+                .start = MSM_FB_BASE,
+                .end = MSM_FB_BASE + MSM_FB_SIZE,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct msm_mddi_bridge_platform_data toshiba_client_data = {
+        .init = trout_mddi_toshiba_client_init,
+        .uninit = trout_mddi_toshiba_client_uninit,
+        .fb_data = {
+                .xres = 320,
+                .yres = 480,
+                .width = 45,
+                .height = 67,
+                .output_format = 0,
+        },
+};
+
+static struct msm_mddi_platform_data mddi_pdata = {
+        .clk_rate = 122880000,
+        .fb_resource = resources_msm_fb,
+        .num_clients = 1,
+        .client_platform_data = {
+                {
+                        .product_id = (0xd263 << 16 | 0),
+                        .name = "mddi_c_d263_0000",
+                        .id = 0,
+                        .client_data = &toshiba_client_data,
+                        .clk_rate = 0,
+                },
+        },
+};
+
+int __init trout_init_panel(void)
+{
+        int rc;
+
+        if (!machine_is_trout())
+                return 0;
+        vreg_mddi_1v5 = vreg_get(0, "gp2");
+        if (IS_ERR(vreg_mddi_1v5))
+                return PTR_ERR(vreg_mddi_1v5);
+        vreg_lcm_2v85 = vreg_get(0, "gp4");
+        if (IS_ERR(vreg_lcm_2v85))
+                return PTR_ERR(vreg_lcm_2v85);
+
+        trout_new_backlight = system_rev >= 5;
+        if (trout_new_backlight) {
+                uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT,
+                                                GPIO_NO_PULL, GPIO_8MA);
+                msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
+        } else {
+                uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
+                                                GPIO_NO_PULL, GPIO_8MA);
+                msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
+
+                gp_clk = clk_get(NULL, "gp_clk");
+                if (IS_ERR(gp_clk)) {
+                        printk(KERN_ERR "trout_init_panel: could not get gp"
+                               "clock\n");
+                        gp_clk = NULL;
+                }
+                rc = clk_set_rate(gp_clk, 19200000);
+                if (rc)
+                        printk(KERN_ERR "trout_init_panel: set clock rate "
+                               "failed\n");
+        }
+
+        rc = platform_device_register(&msm_device_mdp);
+        if (rc)
+                return rc;
+        msm_device_mddi0.dev.platform_data = &mddi_pdata;
+        return platform_device_register(&msm_device_mddi0);
+}
+
+device_initcall(trout_init_panel);
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index c57210f4f06a..2069bfaa3a26 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -120,6 +120,21 @@ EXPORT_SYMBOL(clk_get_rate);
 
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
+        int ret;
+        if (clk->flags & CLKFLAG_MAX) {
+                ret = clk->ops->set_max_rate(clk->id, rate);
+                if (ret)
+                        return ret;
+        }
+        if (clk->flags & CLKFLAG_MIN) {
+                ret = clk->ops->set_min_rate(clk->id, rate);
+                if (ret)
+                        return ret;
+        }
+
+        if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN)
+                return ret;
+
         return clk->ops->set_rate(clk->id, rate);
 }
 EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 4e8c0bcdc92d..fb548a8a21db 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -347,6 +347,73 @@ int __init msm_add_sdcc(unsigned int controller,
         return platform_device_register(pdev);
 }
 
+static struct resource resources_mddi0[] = {
+        {
+                .start  = MSM_PMDH_PHYS,
+                .end    = MSM_PMDH_PHYS + MSM_PMDH_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_MDDI_PRI,
+                .end    = INT_MDDI_PRI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource resources_mddi1[] = {
+        {
+                .start  = MSM_EMDH_PHYS,
+                .end    = MSM_EMDH_PHYS + MSM_EMDH_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_MDDI_EXT,
+                .end    = INT_MDDI_EXT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device msm_device_mddi0 = {
+        .name = "msm_mddi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(resources_mddi0),
+        .resource = resources_mddi0,
+        .dev = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+struct platform_device msm_device_mddi1 = {
+        .name = "msm_mddi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(resources_mddi1),
+        .resource = resources_mddi1,
+        .dev = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+static struct resource resources_mdp[] = {
+        {
+                .start  = MSM_MDP_PHYS,
+                .end    = MSM_MDP_PHYS + MSM_MDP_SIZE - 1,
+                .name   = "mdp",
+                .flags  = IORESOURCE_MEM
+        },
+        {
+                .start  = INT_MDP,
+                .end    = INT_MDP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device msm_device_mdp = {
+        .name = "msm_mdp",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(resources_mdp),
+        .resource = resources_mdp,
+};
+
 struct clk msm_clocks_7x01a[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
@@ -364,7 +431,7 @@ struct clk msm_clocks_7x01a[] = {
         CLK_PCOM("mdp_clk",     MDP_CLK,        NULL, OFF),
         CLK_PCOM("pbus_clk",    PBUS_CLK,       NULL, 0),
         CLK_PCOM("pcm_clk",     PCM_CLK,        NULL, 0),
-        CLK_PCOM("pmdh_clk",    PMDH_CLK,       NULL, OFF ),
+        CLK_PCOM("mddi_clk",    PMDH_CLK,       NULL, OFF | CLK_MINMAX),
         CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
         CLK_PCOM("sdc_clk",     SDC1_CLK,       &msm_device_sdc1.dev, OFF),
         CLK_PCOM("sdc_pclk",    SDC1_P_CLK,     &msm_device_sdc1.dev, OFF),
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 7fcf2e3b7698..4e9a0ab3e937 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -56,6 +56,77 @@ struct platform_device msm_device_smd = {
         .id     = -1,
 };
 
+static struct resource resources_otg[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device msm_device_otg = {
+        .name           = "msm_otg",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_otg),
+        .resource       = resources_otg,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+static struct resource resources_hsusb[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device msm_device_hsusb = {
+        .name           = "msm_hsusb",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_hsusb),
+        .resource       = resources_hsusb,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+static u64 dma_mask = 0xffffffffULL;
+static struct resource resources_hsusb_host[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device msm_device_hsusb_host = {
+        .name           = "msm_hsusb_host",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_hsusb_host),
+        .resource       = resources_hsusb_host,
+        .dev            = {
+                .dma_mask               = &dma_mask,
+                .coherent_dma_mask      = 0xffffffffULL,
+        },
+};
+
 struct clk msm_clocks_7x30[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
@@ -107,6 +178,7 @@ struct clk msm_clocks_7x30[] = {
         CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
         CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
         CLK_PCOM("uart_clk",    UART2_CLK,      &msm_device_uart2.dev, 0),
+        CLK_PCOM("usb_phy_clk", USB_PHY_CLK,    NULL, 0),
         CLK_PCOM("usb_hs_clk",          USB_HS_CLK,             NULL, OFF),
         CLK_PCOM("usb_hs_pclk",         USB_HS_P_CLK,           NULL, OFF),
         CLK_PCOM("usb_hs_core_clk",     USB_HS_CORE_CLK,        NULL, OFF),
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c
index 89b9d4437e92..f9e7bd34ec59 100644
--- a/arch/arm/mach-msm/devices-msm8x60-iommu.c
+++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c
@@ -254,60 +254,86 @@ static struct resource msm_iommu_gfx2d0_resources[] = {
         },
 };
 
+static struct resource msm_iommu_gfx2d1_resources[] = {
+        {
+                .start = MSM_IOMMU_GFX2D1_PHYS,
+                .end   = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1,
+                .name  = "physbase",
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name = "nonsecure_irq",
+                .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
+                .end   = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .name = "secure_irq",
+                .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
+                .end   = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
 static struct platform_device msm_root_iommu_dev = {
         .name = "msm_iommu",
         .id = -1,
 };
 
-static struct msm_iommu_dev jpegd_smmu = {
+static struct msm_iommu_dev jpegd_iommu = {
         .name = "jpegd",
         .clk_rate = -1
 };
 
-static struct msm_iommu_dev vpe_smmu = {
+static struct msm_iommu_dev vpe_iommu = {
         .name = "vpe"
 };
 
-static struct msm_iommu_dev mdp0_smmu = {
+static struct msm_iommu_dev mdp0_iommu = {
         .name = "mdp0"
 };
 
-static struct msm_iommu_dev mdp1_smmu = {
+static struct msm_iommu_dev mdp1_iommu = {
         .name = "mdp1"
 };
 
-static struct msm_iommu_dev rot_smmu = {
+static struct msm_iommu_dev rot_iommu = {
         .name = "rot"
 };
 
-static struct msm_iommu_dev ijpeg_smmu = {
+static struct msm_iommu_dev ijpeg_iommu = {
         .name = "ijpeg"
 };
 
-static struct msm_iommu_dev vfe_smmu = {
+static struct msm_iommu_dev vfe_iommu = {
         .name = "vfe",
         .clk_rate = -1
 };
 
-static struct msm_iommu_dev vcodec_a_smmu = {
+static struct msm_iommu_dev vcodec_a_iommu = {
         .name = "vcodec_a"
 };
 
-static struct msm_iommu_dev vcodec_b_smmu = {
+static struct msm_iommu_dev vcodec_b_iommu = {
         .name = "vcodec_b"
 };
 
-static struct msm_iommu_dev gfx3d_smmu = {
+static struct msm_iommu_dev gfx3d_iommu = {
         .name = "gfx3d",
         .clk_rate = 27000000
 };
 
-static struct msm_iommu_dev gfx2d0_smmu = {
+static struct msm_iommu_dev gfx2d0_iommu = {
         .name = "gfx2d0",
         .clk_rate = 27000000
 };
 
-static struct platform_device msm_device_smmu_jpegd = {
+static struct msm_iommu_dev gfx2d1_iommu = {
+        .name = "gfx2d1",
+        .clk_rate = 27000000
+};
+
+static struct platform_device msm_device_iommu_jpegd = {
         .name = "msm_iommu",
         .id = 0,
         .dev = {
@@ -317,7 +343,7 @@ static struct platform_device msm_device_smmu_jpegd = {
         .resource = msm_iommu_jpegd_resources,
 };
 
-static struct platform_device msm_device_smmu_vpe = {
+static struct platform_device msm_device_iommu_vpe = {
         .name = "msm_iommu",
         .id = 1,
         .dev = {
@@ -327,7 +353,7 @@ static struct platform_device msm_device_smmu_vpe = {
         .resource = msm_iommu_vpe_resources,
 };
 
-static struct platform_device msm_device_smmu_mdp0 = {
+static struct platform_device msm_device_iommu_mdp0 = {
         .name = "msm_iommu",
         .id = 2,
         .dev = {
@@ -337,7 +363,7 @@ static struct platform_device msm_device_smmu_mdp0 = {
         .resource = msm_iommu_mdp0_resources,
 };
 
-static struct platform_device msm_device_smmu_mdp1 = {
+static struct platform_device msm_device_iommu_mdp1 = {
         .name = "msm_iommu",
         .id = 3,
         .dev = {
@@ -347,7 +373,7 @@ static struct platform_device msm_device_smmu_mdp1 = {
         .resource = msm_iommu_mdp1_resources,
 };
 
-static struct platform_device msm_device_smmu_rot = {
+static struct platform_device msm_device_iommu_rot = {
         .name = "msm_iommu",
         .id = 4,
         .dev = {
@@ -357,7 +383,7 @@ static struct platform_device msm_device_smmu_rot = {
         .resource = msm_iommu_rot_resources,
 };
 
-static struct platform_device msm_device_smmu_ijpeg = {
+static struct platform_device msm_device_iommu_ijpeg = {
         .name = "msm_iommu",
         .id = 5,
         .dev = {
@@ -367,7 +393,7 @@ static struct platform_device msm_device_smmu_ijpeg = {
         .resource = msm_iommu_ijpeg_resources,
 };
 
-static struct platform_device msm_device_smmu_vfe = {
+static struct platform_device msm_device_iommu_vfe = {
         .name = "msm_iommu",
         .id = 6,
         .dev = {
@@ -377,7 +403,7 @@ static struct platform_device msm_device_smmu_vfe = {
         .resource = msm_iommu_vfe_resources,
 };
 
-static struct platform_device msm_device_smmu_vcodec_a = {
+static struct platform_device msm_device_iommu_vcodec_a = {
         .name = "msm_iommu",
         .id = 7,
         .dev = {
@@ -387,7 +413,7 @@ static struct platform_device msm_device_smmu_vcodec_a = {
         .resource = msm_iommu_vcodec_a_resources,
 };
 
-static struct platform_device msm_device_smmu_vcodec_b = {
+static struct platform_device msm_device_iommu_vcodec_b = {
         .name = "msm_iommu",
         .id = 8,
         .dev = {
@@ -397,7 +423,7 @@ static struct platform_device msm_device_smmu_vcodec_b = {
         .resource = msm_iommu_vcodec_b_resources,
 };
 
-static struct platform_device msm_device_smmu_gfx3d = {
+static struct platform_device msm_device_iommu_gfx3d = {
         .name = "msm_iommu",
         .id = 9,
         .dev = {
@@ -407,7 +433,7 @@ static struct platform_device msm_device_smmu_gfx3d = {
         .resource = msm_iommu_gfx3d_resources,
 };
 
-static struct platform_device msm_device_smmu_gfx2d0 = {
+static struct platform_device msm_device_iommu_gfx2d0 = {
         .name = "msm_iommu",
         .id = 10,
         .dev = {
@@ -417,6 +443,16 @@ static struct platform_device msm_device_smmu_gfx2d0 = {
         .resource = msm_iommu_gfx2d0_resources,
 };
 
+struct platform_device msm_device_iommu_gfx2d1 = {
+        .name = "msm_iommu",
+        .id = 11,
+        .dev = {
+                .parent = &msm_root_iommu_dev.dev,
+        },
+        .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
+        .resource = msm_iommu_gfx2d1_resources,
+};
+
 static struct msm_iommu_ctx_dev jpegd_src_ctx = {
         .name = "jpegd_src",
         .num = 0,
@@ -519,41 +555,36 @@ static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
         .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
 };
 
-static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = {
-        .name = "gfx3d_rbpa",
+static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
+        .name = "gfx3d_user",
         .num = 0,
-        .mids = {-1}
+        .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
 };
 
-static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = {
-        .name = "gfx3d_cpvgttc",
+static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
+        .name = "gfx3d_priv",
         .num = 1,
-        .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
-};
-
-static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = {
-        .name = "gfx3d_smmu",
-        .num = 2,
-        .mids = {8, 9, 10, 11, 12, -1}
+        .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
+                 31, -1}
 };
 
-static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = {
-        .name = "gfx2d0_pixv1_smmu",
+static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
+        .name = "gfx2d0_2d0",
         .num = 0,
-        .mids = {0, 3, 4, -1}
+        .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
 };
 
-static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = {
-        .name = "gfx2d0_texv3_smmu",
-        .num = 1,
-        .mids = {1, 6, 7, -1}
+static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
+        .name = "gfx2d1_2d1",
+        .num = 0,
+        .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
 };
 
 static struct platform_device msm_device_jpegd_src_ctx = {
         .name = "msm_iommu_ctx",
         .id = 0,
         .dev = {
-                .parent = &msm_device_smmu_jpegd.dev,
+                .parent = &msm_device_iommu_jpegd.dev,
         },
 };
 
@@ -561,7 +592,7 @@ static struct platform_device msm_device_jpegd_dst_ctx = {
         .name = "msm_iommu_ctx",
         .id = 1,
         .dev = {
-                .parent = &msm_device_smmu_jpegd.dev,
+                .parent = &msm_device_iommu_jpegd.dev,
         },
 };
 
@@ -569,7 +600,7 @@ static struct platform_device msm_device_vpe_src_ctx = {
         .name = "msm_iommu_ctx",
         .id = 2,
         .dev = {
-                .parent = &msm_device_smmu_vpe.dev,
+                .parent = &msm_device_iommu_vpe.dev,
         },
 };
 
@@ -577,7 +608,7 @@ static struct platform_device msm_device_vpe_dst_ctx = {
         .name = "msm_iommu_ctx",
         .id = 3,
         .dev = {
-                .parent = &msm_device_smmu_vpe.dev,
+                .parent = &msm_device_iommu_vpe.dev,
         },
 };
 
@@ -585,7 +616,7 @@ static struct platform_device msm_device_mdp_vg1_ctx = {
         .name = "msm_iommu_ctx",
         .id = 4,
         .dev = {
-                .parent = &msm_device_smmu_mdp0.dev,
+                .parent = &msm_device_iommu_mdp0.dev,
         },
 };
 
@@ -593,7 +624,7 @@ static struct platform_device msm_device_mdp_rgb1_ctx = {
         .name = "msm_iommu_ctx",
         .id = 5,
         .dev = {
-                .parent = &msm_device_smmu_mdp0.dev,
+                .parent = &msm_device_iommu_mdp0.dev,
         },
 };
 
@@ -601,7 +632,7 @@ static struct platform_device msm_device_mdp_vg2_ctx = {
         .name = "msm_iommu_ctx",
         .id = 6,
         .dev = {
-                .parent = &msm_device_smmu_mdp1.dev,
+                .parent = &msm_device_iommu_mdp1.dev,
         },
 };
 
@@ -609,7 +640,7 @@ static struct platform_device msm_device_mdp_rgb2_ctx = {
         .name = "msm_iommu_ctx",
         .id = 7,
         .dev = {
-                .parent = &msm_device_smmu_mdp1.dev,
+                .parent = &msm_device_iommu_mdp1.dev,
         },
 };
 
@@ -617,7 +648,7 @@ static struct platform_device msm_device_rot_src_ctx = {
         .name = "msm_iommu_ctx",
         .id = 8,
         .dev = {
-                .parent = &msm_device_smmu_rot.dev,
+                .parent = &msm_device_iommu_rot.dev,
         },
 };
 
@@ -625,7 +656,7 @@ static struct platform_device msm_device_rot_dst_ctx = {
         .name = "msm_iommu_ctx",
         .id = 9,
         .dev = {
-                .parent = &msm_device_smmu_rot.dev,
+                .parent = &msm_device_iommu_rot.dev,
         },
 };
 
@@ -633,7 +664,7 @@ static struct platform_device msm_device_ijpeg_src_ctx = {
         .name = "msm_iommu_ctx",
         .id = 10,
         .dev = {
-                .parent = &msm_device_smmu_ijpeg.dev,
+                .parent = &msm_device_iommu_ijpeg.dev,
         },
 };
 
@@ -641,7 +672,7 @@ static struct platform_device msm_device_ijpeg_dst_ctx = {
         .name = "msm_iommu_ctx",
         .id = 11,
         .dev = {
-                .parent = &msm_device_smmu_ijpeg.dev,
+                .parent = &msm_device_iommu_ijpeg.dev,
         },
 };
 
@@ -649,7 +680,7 @@ static struct platform_device msm_device_vfe_imgwr_ctx = {
         .name = "msm_iommu_ctx",
         .id = 12,
         .dev = {
-                .parent = &msm_device_smmu_vfe.dev,
+                .parent = &msm_device_iommu_vfe.dev,
         },
 };
 
@@ -657,7 +688,7 @@ static struct platform_device msm_device_vfe_misc_ctx = {
         .name = "msm_iommu_ctx",
         .id = 13,
         .dev = {
-                .parent = &msm_device_smmu_vfe.dev,
+                .parent = &msm_device_iommu_vfe.dev,
         },
 };
 
@@ -665,7 +696,7 @@ static struct platform_device msm_device_vcodec_a_stream_ctx = {
         .name = "msm_iommu_ctx",
         .id = 14,
         .dev = {
-                .parent = &msm_device_smmu_vcodec_a.dev,
+                .parent = &msm_device_iommu_vcodec_a.dev,
         },
 };
 
@@ -673,7 +704,7 @@ static struct platform_device msm_device_vcodec_a_mm1_ctx = {
         .name = "msm_iommu_ctx",
         .id = 15,
         .dev = {
-                .parent = &msm_device_smmu_vcodec_a.dev,
+                .parent = &msm_device_iommu_vcodec_a.dev,
         },
 };
 
@@ -681,76 +712,70 @@ static struct platform_device msm_device_vcodec_b_mm2_ctx = {
         .name = "msm_iommu_ctx",
         .id = 16,
         .dev = {
-                .parent = &msm_device_smmu_vcodec_b.dev,
+                .parent = &msm_device_iommu_vcodec_b.dev,
         },
 };
 
-static struct platform_device msm_device_gfx3d_rbpa_ctx = {
+static struct platform_device msm_device_gfx3d_user_ctx = {
         .name = "msm_iommu_ctx",
         .id = 17,
         .dev = {
-                .parent = &msm_device_smmu_gfx3d.dev,
+                .parent = &msm_device_iommu_gfx3d.dev,
         },
 };
 
-static struct platform_device msm_device_gfx3d_cpvgttc_ctx = {
+static struct platform_device msm_device_gfx3d_priv_ctx = {
         .name = "msm_iommu_ctx",
         .id = 18,
         .dev = {
-                .parent = &msm_device_smmu_gfx3d.dev,
+                .parent = &msm_device_iommu_gfx3d.dev,
         },
 };
 
-static struct platform_device msm_device_gfx3d_smmu_ctx = {
+static struct platform_device msm_device_gfx2d0_2d0_ctx = {
         .name = "msm_iommu_ctx",
         .id = 19,
         .dev = {
-                .parent = &msm_device_smmu_gfx3d.dev,
+                .parent = &msm_device_iommu_gfx2d0.dev,
         },
 };
 
-static struct platform_device msm_device_gfx2d0_pixv1_ctx = {
+static struct platform_device msm_device_gfx2d1_2d1_ctx = {
         .name = "msm_iommu_ctx",
         .id = 20,
         .dev = {
-                .parent = &msm_device_smmu_gfx2d0.dev,
-        },
-};
-
-static struct platform_device msm_device_gfx2d0_texv3_ctx = {
-        .name = "msm_iommu_ctx",
-        .id = 21,
-        .dev = {
-                .parent = &msm_device_smmu_gfx2d0.dev,
+                .parent = &msm_device_iommu_gfx2d1.dev,
         },
 };
 
 static struct platform_device *msm_iommu_devs[] = {
-        &msm_device_smmu_jpegd,
-        &msm_device_smmu_vpe,
-        &msm_device_smmu_mdp0,
-        &msm_device_smmu_mdp1,
-        &msm_device_smmu_rot,
-        &msm_device_smmu_ijpeg,
-        &msm_device_smmu_vfe,
-        &msm_device_smmu_vcodec_a,
-        &msm_device_smmu_vcodec_b,
-        &msm_device_smmu_gfx3d,
-        &msm_device_smmu_gfx2d0,
+        &msm_device_iommu_jpegd,
+        &msm_device_iommu_vpe,
+        &msm_device_iommu_mdp0,
+        &msm_device_iommu_mdp1,
+        &msm_device_iommu_rot,
+        &msm_device_iommu_ijpeg,
+        &msm_device_iommu_vfe,
+        &msm_device_iommu_vcodec_a,
+        &msm_device_iommu_vcodec_b,
+        &msm_device_iommu_gfx3d,
+        &msm_device_iommu_gfx2d0,
+        &msm_device_iommu_gfx2d1,
 };
 
 static struct msm_iommu_dev *msm_iommu_data[] = {
-        &jpegd_smmu,
-        &vpe_smmu,
-        &mdp0_smmu,
-        &mdp1_smmu,
-        &rot_smmu,
-        &ijpeg_smmu,
-        &vfe_smmu,
-        &vcodec_a_smmu,
-        &vcodec_b_smmu,
-        &gfx3d_smmu,
-        &gfx2d0_smmu,
+        &jpegd_iommu,
+        &vpe_iommu,
+        &mdp0_iommu,
+        &mdp1_iommu,
+        &rot_iommu,
+        &ijpeg_iommu,
+        &vfe_iommu,
+        &vcodec_a_iommu,
+        &vcodec_b_iommu,
+        &gfx3d_iommu,
+        &gfx2d0_iommu,
+        &gfx2d1_iommu,
 };
 
 static struct platform_device *msm_iommu_ctx_devs[] = {
@@ -771,11 +796,10 @@ static struct platform_device *msm_iommu_ctx_devs[] = {
         &msm_device_vcodec_a_stream_ctx,
         &msm_device_vcodec_a_mm1_ctx,
         &msm_device_vcodec_b_mm2_ctx,
-        &msm_device_gfx3d_rbpa_ctx,
-        &msm_device_gfx3d_cpvgttc_ctx,
-        &msm_device_gfx3d_smmu_ctx,
-        &msm_device_gfx2d0_pixv1_ctx,
-        &msm_device_gfx2d0_texv3_ctx,
+        &msm_device_gfx3d_user_ctx,
+        &msm_device_gfx3d_priv_ctx,
+        &msm_device_gfx2d0_2d0_ctx,
+        &msm_device_gfx2d1_2d1_ctx,
 };
 
 static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
@@ -796,14 +820,13 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
         &vcodec_a_stream_ctx,
         &vcodec_a_mm1_ctx,
         &vcodec_b_mm2_ctx,
-        &gfx3d_rbpa_ctx,
-        &gfx3d_cpvgttc_ctx,
-        &gfx3d_smmu_ctx,
-        &gfx2d0_pixv1_ctx,
-        &gfx2d0_texv3_ctx,
+        &gfx3d_user_ctx,
+        &gfx3d_priv_ctx,
+        &gfx2d0_2d0_ctx,
+        &gfx2d1_2d1_ctx,
 };
 
-static int msm8x60_iommu_init(void)
+static int __init msm8x60_iommu_init(void)
 {
         int ret, i;
 
@@ -826,7 +849,7 @@ static int msm8x60_iommu_init(void)
                 ret = platform_device_register(msm_iommu_devs[i]);
 
                 if (ret != 0) {
-                        pr_err("platform_device_register smmu failed, "
+                        pr_err("platform_device_register iommu failed, "
                                "i = %d\n", i);
                         goto failure_unwind;
                 }
@@ -837,7 +860,7 @@ static int msm8x60_iommu_init(void)
                                                msm_iommu_ctx_data[i],
                                                sizeof(*msm_iommu_ctx_devs[i]));
                 if (ret != 0) {
-                        pr_err("platform_device_add_data smmu failed, "
+                        pr_err("platform_device_add_data iommu failed, "
                                "i = %d\n", i);
                         goto failure_unwind2;
                 }
@@ -863,7 +886,7 @@ failure:
         return ret;
 }
 
-static void msm8x60_iommu_exit(void)
+static void __exit msm8x60_iommu_exit(void)
 {
         int i;
 
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 6fe67c5d1ae0..a4b798f20ccb 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -53,6 +53,77 @@ struct platform_device msm_device_smd = {
         .id     = -1,
 };
 
+static struct resource resources_otg[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device msm_device_otg = {
+        .name           = "msm_otg",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_otg),
+        .resource       = resources_otg,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+static struct resource resources_hsusb[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device msm_device_hsusb = {
+        .name           = "msm_hsusb",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_hsusb),
+        .resource       = resources_hsusb,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+static u64 dma_mask = 0xffffffffULL;
+static struct resource resources_hsusb_host[] = {
+        {
+                .start  = MSM_HSUSB_PHYS,
+                .end    = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_USB_HS,
+                .end    = INT_USB_HS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device msm_device_hsusb_host = {
+        .name           = "msm_hsusb_host",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(resources_hsusb_host),
+        .resource       = resources_hsusb_host,
+        .dev            = {
+                .dma_mask               = &dma_mask,
+                .coherent_dma_mask      = 0xffffffffULL,
+        },
+};
+
 struct clk msm_clocks_8x50[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 568443e76423..87c70bfce2bd 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -28,6 +28,8 @@ extern struct platform_device msm_device_sdc3;
 extern struct platform_device msm_device_sdc4;
 
 extern struct platform_device msm_device_hsusb;
+extern struct platform_device msm_device_otg;
+extern struct platform_device msm_device_hsusb_host;
 
 extern struct platform_device msm_device_i2c;
 
@@ -35,6 +37,10 @@ extern struct platform_device msm_device_smd;
 
 extern struct platform_device msm_device_nand;
 
+extern struct platform_device msm_device_mddi0;
+extern struct platform_device msm_device_mddi1;
+extern struct platform_device msm_device_mdp;
+
 extern struct clk msm_clocks_7x01a[];
 extern unsigned msm_num_clocks_7x01a;
 
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
new file mode 100644
index 000000000000..0de19ec74e34
--- /dev/null
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -0,0 +1,426 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <mach/msm_iomap.h>
+#include "gpiomux.h"
+
+/* Bits of interest in the GPIO_IN_OUT register.
+ */
+enum {
+        GPIO_IN  = 0,
+        GPIO_OUT = 1
+};
+
+/* Bits of interest in the GPIO_INTR_STATUS register.
+ */
+enum {
+        INTR_STATUS = 0,
+};
+
+/* Bits of interest in the GPIO_CFG register.
+ */
+enum {
+        GPIO_OE = 9,
+};
+
+/* Bits of interest in the GPIO_INTR_CFG register.
+ * When a GPIO triggers, two separate decisions are made, controlled
+ * by two separate flags.
+ *
+ * - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
+ * register for that GPIO will be updated to reflect the triggering of that
+ * gpio.  If this bit is 0, this register will not be updated.
+ * - Second, INTR_ENABLE controls whether an interrupt is triggered.
+ *
+ * If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
+ * can be triggered but the status register will not reflect it.
+ */
+enum {
+        INTR_ENABLE        = 0,
+        INTR_POL_CTL       = 1,
+        INTR_DECT_CTL      = 2,
+        INTR_RAW_STATUS_EN = 3,
+};
+
+/* Codes of interest in GPIO_INTR_CFG_SU.
+ */
+enum {
+        TARGET_PROC_SCORPION = 4,
+        TARGET_PROC_NONE     = 7,
+};
+
+
+#define GPIO_INTR_CFG_SU(gpio)    (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
+#define GPIO_CONFIG(gpio)         (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
+#define GPIO_IN_OUT(gpio)         (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
+#define GPIO_INTR_CFG(gpio)       (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
+#define GPIO_INTR_STATUS(gpio)    (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))
+
+/**
+ * struct msm_gpio_dev: the MSM8660 SoC GPIO device structure
+ *
+ * @enabled_irqs: a bitmap used to optimize the summary-irq handler.  By
+ * keeping track of which gpios are unmasked as irq sources, we avoid
+ * having to do readl calls on hundreds of iomapped registers each time
+ * the summary interrupt fires in order to locate the active interrupts.
+ *
+ * @wake_irqs: a bitmap for tracking which interrupt lines are enabled
+ * as wakeup sources.  When the device is suspended, interrupts which are
+ * not wakeup sources are disabled.
+ *
+ * @dual_edge_irqs: a bitmap used to track which irqs are configured
+ * as dual-edge, as this is not supported by the hardware and requires
+ * some special handling in the driver.
+ */
+struct msm_gpio_dev {
+        struct gpio_chip gpio_chip;
+        DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS);
+        DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS);
+        DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS);
+};
+
+static DEFINE_SPINLOCK(tlmm_lock);
+
+static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
+{
+        return container_of(chip, struct msm_gpio_dev, gpio_chip);
+}
+
+static inline void set_gpio_bits(unsigned n, void __iomem *reg)
+{
+        writel(readl(reg) | n, reg);
+}
+
+static inline void clear_gpio_bits(unsigned n, void __iomem *reg)
+{
+        writel(readl(reg) & ~n, reg);
+}
+
+static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN);
+}
+
+static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+        writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset));
+}
+
+static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        unsigned long irq_flags;
+
+        spin_lock_irqsave(&tlmm_lock, irq_flags);
+        clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
+        spin_unlock_irqrestore(&tlmm_lock, irq_flags);
+        return 0;
+}
+
+static int msm_gpio_direction_output(struct gpio_chip *chip,
+                                unsigned offset,
+                                int val)
+{
+        unsigned long irq_flags;
+
+        spin_lock_irqsave(&tlmm_lock, irq_flags);
+        msm_gpio_set(chip, offset, val);
+        set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset));
+        spin_unlock_irqrestore(&tlmm_lock, irq_flags);
+        return 0;
+}
+
+static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        return msm_gpiomux_get(chip->base + offset);
+}
+
+static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        msm_gpiomux_put(chip->base + offset);
+}
+
+static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        return MSM_GPIO_TO_INT(chip->base + offset);
+}
+
+static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq)
+{
+        return irq - MSM_GPIO_TO_INT(chip->base);
+}
+
+static struct msm_gpio_dev msm_gpio = {
+        .gpio_chip = {
+                .base             = 0,
+                .ngpio            = NR_GPIO_IRQS,
+                .direction_input  = msm_gpio_direction_input,
+                .direction_output = msm_gpio_direction_output,
+                .get              = msm_gpio_get,
+                .set              = msm_gpio_set,
+                .to_irq           = msm_gpio_to_irq,
+                .request          = msm_gpio_request,
+                .free             = msm_gpio_free,
+        },
+};
+
+/* For dual-edge interrupts in software, since the hardware has no
+ * such support:
+ *
+ * At appropriate moments, this function may be called to flip the polarity
+ * settings of both-edge irq lines to try and catch the next edge.
+ *
+ * The attempt is considered successful if:
+ * - the status bit goes high, indicating that an edge was caught, or
+ * - the input value of the gpio doesn't change during the attempt.
+ * If the value changes twice during the process, that would cause the first
+ * test to fail but would force the second, as two opposite
+ * transitions would cause a detection no matter the polarity setting.
+ *
+ * The do-loop tries to sledge-hammer closed the timing hole between
+ * the initial value-read and the polarity-write - if the line value changes
+ * during that window, an interrupt is lost, the new polarity setting is
+ * incorrect, and the first success test will fail, causing a retry.
+ *
+ * Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c.
+ */
+static void msm_gpio_update_dual_edge_pos(unsigned gpio)
+{
+        int loop_limit = 100;
+        unsigned val, val2, intstat;
+
+        do {
+                val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
+                if (val)
+                        clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
+                else
+                        set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio));
+                val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN);
+                intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS);
+                if (intstat || val == val2)
+                        return;
+        } while (loop_limit-- > 0);
+        pr_err("dual-edge irq failed to stabilize, "
+               "interrupts dropped. %#08x != %#08x\n",
+               val, val2);
+}
+
+static void msm_gpio_irq_ack(unsigned int irq)
+{
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+
+        writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
+        if (test_bit(gpio, msm_gpio.dual_edge_irqs))
+                msm_gpio_update_dual_edge_pos(gpio);
+}
+
+static void msm_gpio_irq_mask(unsigned int irq)
+{
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        unsigned long irq_flags;
+
+        spin_lock_irqsave(&tlmm_lock, irq_flags);
+        writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio));
+        clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
+        __clear_bit(gpio, msm_gpio.enabled_irqs);
+        spin_unlock_irqrestore(&tlmm_lock, irq_flags);
+}
+
+static void msm_gpio_irq_unmask(unsigned int irq)
+{
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        unsigned long irq_flags;
+
+        spin_lock_irqsave(&tlmm_lock, irq_flags);
+        __set_bit(gpio, msm_gpio.enabled_irqs);
+        set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio));
+        writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
+        spin_unlock_irqrestore(&tlmm_lock, irq_flags);
+}
+
+static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        unsigned long irq_flags;
+        uint32_t bits;
+
+        spin_lock_irqsave(&tlmm_lock, irq_flags);
+
+        bits = readl(GPIO_INTR_CFG(gpio));
+
+        if (flow_type & IRQ_TYPE_EDGE_BOTH) {
+                bits |= BIT(INTR_DECT_CTL);
+                irq_desc[irq].handle_irq = handle_edge_irq;
+                if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
+                        __set_bit(gpio, msm_gpio.dual_edge_irqs);
+                else
+                        __clear_bit(gpio, msm_gpio.dual_edge_irqs);
+        } else {
+                bits &= ~BIT(INTR_DECT_CTL);
+                irq_desc[irq].handle_irq = handle_level_irq;
+                __clear_bit(gpio, msm_gpio.dual_edge_irqs);
+        }
+
+        if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
+                bits |= BIT(INTR_POL_CTL);
+        else
+                bits &= ~BIT(INTR_POL_CTL);
+
+        writel(bits, GPIO_INTR_CFG(gpio));
+
+        if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
+                msm_gpio_update_dual_edge_pos(gpio);
+
+        spin_unlock_irqrestore(&tlmm_lock, irq_flags);
+
+        return 0;
+}
+
+/*
+ * When the summary IRQ is raised, any number of GPIO lines may be high.
+ * It is the job of the summary handler to find all those GPIO lines
+ * which have been set as summary IRQ lines and which are triggered,
+ * and to call their interrupt handlers.
+ */
+static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long i;
+
+        for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
+             i < NR_GPIO_IRQS;
+             i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) {
+                if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS))
+                        generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
+                                                           i));
+        }
+        desc->chip->ack(irq);
+}
+
+static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+
+        if (on) {
+                if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
+                        set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
+                set_bit(gpio, msm_gpio.wake_irqs);
+        } else {
+                clear_bit(gpio, msm_gpio.wake_irqs);
+                if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
+                        set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
+        }
+
+        return 0;
+}
+
+static struct irq_chip msm_gpio_irq_chip = {
+        .name           = "msmgpio",
+        .mask           = msm_gpio_irq_mask,
+        .unmask         = msm_gpio_irq_unmask,
+        .ack            = msm_gpio_irq_ack,
+        .set_type       = msm_gpio_irq_set_type,
+        .set_wake       = msm_gpio_irq_set_wake,
+};
+
+static int __devinit msm_gpio_probe(struct platform_device *dev)
+{
+        int i, irq, ret;
+
+        bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
+        bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS);
+        bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS);
+        msm_gpio.gpio_chip.label = dev->name;
+        ret = gpiochip_add(&msm_gpio.gpio_chip);
+        if (ret < 0)
+                return ret;
+
+        for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
+                irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
+                set_irq_chip(irq, &msm_gpio_irq_chip);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+
+        set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
+                                msm_summary_irq_handler);
+        return 0;
+}
+
+static int __devexit msm_gpio_remove(struct platform_device *dev)
+{
+        int ret = gpiochip_remove(&msm_gpio.gpio_chip);
+
+        if (ret < 0)
+                return ret;
+
+        set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
+
+        return 0;
+}
+
+static struct platform_driver msm_gpio_driver = {
+        .probe = msm_gpio_probe,
+        .remove = __devexit_p(msm_gpio_remove),
+        .driver = {
+                .name = "msmgpio",
+                .owner = THIS_MODULE,
+        },
+};
+
+static struct platform_device msm_device_gpio = {
+        .name = "msmgpio",
+        .id   = -1,
+};
+
+static int __init msm_gpio_init(void)
+{
+        int rc;
+
+        rc = platform_driver_register(&msm_gpio_driver);
+        if (!rc) {
+                rc = platform_device_register(&msm_device_gpio);
+                if (rc)
+                        platform_driver_unregister(&msm_gpio_driver);
+        }
+
+        return rc;
+}
+
+static void __exit msm_gpio_exit(void)
+{
+        platform_device_unregister(&msm_device_gpio);
+        platform_driver_unregister(&msm_gpio_driver);
+}
+
+postcore_initcall(msm_gpio_init);
+module_exit(msm_gpio_exit);
+
+MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>");
+MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:msmgpio");
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
new file mode 100644
index 000000000000..d0c214338df9
--- /dev/null
+++ b/arch/arm/mach-msm/headsmp.S
@@ -0,0 +1,40 @@
+/*
+ *  linux/arch/arm/mach-realview/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        __INIT
+
+/*
+ * MSM specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(msm_secondary_startup)
+        mrc     p15, 0, r0, c0, c0, 5
+        and     r0, r0, #15
+        adr     r4, 1f
+        ldmia   r4, {r5, r6}
+        sub     r4, r4, r5
+        add     r6, r6, r4
+pen:    ldr     r7, [r6]
+        cmp     r7, r0
+        bne     pen
+
+        /*
+         * we've been released from the holding pen: secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+
+        .align
+1:      .long   .
+        .long   pen_release
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
new file mode 100644
index 000000000000..5a31f70dfb8e
--- /dev/null
+++ b/arch/arm/mach-msm/hotplug.c
@@ -0,0 +1,91 @@
+/*
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+        /* Just flush the cache. Changing the coherency is not yet
+         * available on msm. */
+        flush_cache_all();
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+}
+
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+        /* Just enter wfi for now. TODO: Properly shut off the cpu. */
+        for (;;) {
+                /*
+                 * here's the WFI
+                 */
+                asm("wfi"
+                    :
+                    :
+                    : "memory", "cc");
+
+                if (pen_release == cpu) {
+                        /*
+                         * OK, proper wakeup, we're done
+                         */
+                        break;
+                }
+
+                /*
+                 * getting here, means that we have come out of WFI without
+                 * having been woken up - this shouldn't happen
+                 *
+                 * The trouble is, letting people know about this is not really
+                 * possible, since we are currently running incoherently, and
+                 * therefore cannot safely call printk() or anything else
+                 */
+                pr_debug("CPU%u: spurious wakeup call\n", cpu);
+        }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+        /*
+         * we're ready for shutdown now, so do it
+         */
+        cpu_enter_lowpower();
+        platform_do_lowpower(cpu);
+
+        /*
+         * bring this CPU back into the world of cache
+         * coherency, and then restore interrupts
+         */
+        cpu_leave_lowpower();
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+        /*
+         * we don't allow CPU 0 to be shutdown (it is still too special
+         * e.g. clock tick interrupts)
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
index 218ef5732a24..296c0f10f230 100644
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -20,13 +20,26 @@
 
 #include <linux/interrupt.h>
 
+/* Sharability attributes of MSM IOMMU mappings */
+#define MSM_IOMMU_ATTR_NON_SH           0x0
+#define MSM_IOMMU_ATTR_SH               0x4
+
+/* Cacheability attributes of MSM IOMMU mappings */
+#define MSM_IOMMU_ATTR_NONCACHED        0x0
+#define MSM_IOMMU_ATTR_CACHED_WB_WA     0x1
+#define MSM_IOMMU_ATTR_CACHED_WB_NWA    0x2
+#define MSM_IOMMU_ATTR_CACHED_WT        0x3
+
+/* Mask for the cache policy attribute */
+#define MSM_IOMMU_CP_MASK               0x03
+
 /* Maximum number of Machine IDs that we are allowing to be mapped to the same
  * context bank. The number of MIDs mapped to the same CB does not affect
  * performance, but there is a practical limit on how many distinct MIDs may
  * be present. These mappings are typically determined at design time and are
  * not expected to change at run time.
  */
-#define MAX_NUM_MIDS    16
+#define MAX_NUM_MIDS    32
 
 /**
  * struct msm_iommu_dev - a single IOMMU hardware instance
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
index f9386d3a2f77..c2c3da9444f4 100644
--- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
+++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
@@ -54,6 +54,7 @@ do { \
 
 #define NUM_FL_PTE      4096
 #define NUM_SL_PTE      256
+#define NUM_TEX_CLASS   8
 
 /* First-level page table bits */
 #define FL_BASE_MASK            0xFFFFFC00
@@ -63,6 +64,9 @@ do { \
 #define FL_AP_WRITE             (1 << 10)
 #define FL_AP_READ              (1 << 11)
 #define FL_SHARED               (1 << 16)
+#define FL_BUFFERABLE           (1 << 2)
+#define FL_CACHEABLE            (1 << 3)
+#define FL_TEX0                 (1 << 12)
 #define FL_OFFSET(va)           (((va) & 0xFFF00000) >> 20)
 
 /* Second-level page table bits */
@@ -73,8 +77,20 @@ do { \
 #define SL_AP0                  (1 << 4)
 #define SL_AP1                  (2 << 4)
 #define SL_SHARED               (1 << 10)
+#define SL_BUFFERABLE           (1 << 2)
+#define SL_CACHEABLE            (1 << 3)
+#define SL_TEX0                 (1 << 6)
 #define SL_OFFSET(va)           (((va) & 0xFF000) >> 12)
 
+/* Memory type and cache policy attributes */
+#define MT_SO                   0
+#define MT_DEV                  1
+#define MT_NORMAL               2
+#define CP_NONCACHED            0
+#define CP_WB_WA                1
+#define CP_WT                   2
+#define CP_WB_NWA               3
+
 /* Global register setters / getters */
 #define SET_M2VCBR_N(b, N, v)    SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
 #define SET_CBACR_N(b, N, v)     SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
@@ -706,7 +722,9 @@ do { \
 #define GET_OCPC5(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
 #define GET_OCPC6(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
 #define GET_OCPC7(b, c)         GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
-
+#define NMRR_ICP(nmrr, n)       (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2))
+#define NMRR_OCP(nmrr, n)       (((nmrr) & (3 << ((n) * 2 + 16))) >> \
+                                                                ((n) * 2 + 16))
 
 /* PAR */
 #define GET_FAULT(b, c)         GET_CONTEXT_FIELD(b, c, PAR, FAULT)
@@ -750,6 +768,8 @@ do { \
 #define GET_NOS5(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
 #define GET_NOS6(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
 #define GET_NOS7(b, c)          GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
+#define PRRR_NOS(prrr, n)        ((prrr) & (1 << ((n) + 24)) ? 1 : 0)
+#define PRRR_MT(prrr, n)         ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2)))
 
 
 /* RESUME */
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h
index 36074cfc9ad2..f65841c74c0b 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8x60.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h
@@ -237,7 +237,12 @@
 #define GSBI11_QUP_IRQ                          (GIC_SPI_START + 194)
 #define INT_UART12DM_IRQ                        (GIC_SPI_START + 195)
 #define GSBI12_QUP_IRQ                          (GIC_SPI_START + 196)
-/*SPI 197 to 216 arent used in 8x60*/
+
+/*SPI 197 to 209 arent used in 8x60*/
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ            (GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ        (GIC_SPI_START + 211)
+
+/*SPI 212 to 216 arent used in 8x60*/
 #define SMPSS_SPARE_1                           (GIC_SPI_START + 217)
 #define SMPSS_SPARE_2                           (GIC_SPI_START + 218)
 #define SMPSS_SPARE_3                           (GIC_SPI_START + 219)
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 8a00c2defbc1..0fd7b68ca114 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -119,4 +119,7 @@
 #define MSM_AD5_PHYS          0xA7000000
 #define MSM_AD5_SIZE          (SZ_1M*13)
 
+#define MSM_HSUSB_PHYS        0xA3600000
+#define MSM_HSUSB_SIZE        SZ_1K
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 45bab50e3ee6..a54e33b0882e 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -60,7 +60,11 @@
 
 #define MSM_TMR_BASE            IOMEM(0xF0200000)
 #define MSM_TMR_PHYS            0x02000000
-#define MSM_TMR_SIZE            (SZ_1M)
+#define MSM_TMR_SIZE            SZ_4K
+
+#define MSM_TMR0_BASE           IOMEM(0xF0201000)
+#define MSM_TMR0_PHYS           0x02040000
+#define MSM_TMR0_SIZE           SZ_4K
 
 #define MSM_GPT_BASE            (MSM_TMR_BASE + 0x4)
 #define MSM_DGT_BASE            (MSM_TMR_BASE + 0x24)
@@ -98,4 +102,7 @@
 #define MSM_IOMMU_GFX2D0_PHYS   0x07D00000
 #define MSM_IOMMU_GFX2D0_SIZE   SZ_1M
 
+#define MSM_IOMMU_GFX2D1_PHYS   0x07E00000
+#define MSM_IOMMU_GFX2D1_SIZE   SZ_1M
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h
index 3ff7bf5e679e..a95f7b9efe31 100644
--- a/arch/arm/mach-msm/include/mach/smp.h
+++ b/arch/arm/mach-msm/include/mach/smp.h
@@ -31,9 +31,9 @@
 
 #include <asm/hardware/gic.h>
 
-static inline void smp_cross_call(const struct cpumask *mask)
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
 {
-        gic_raise_softirq(mask, 1);
+        gic_raise_softirq(mask, ipi);
 }
 
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index d36b61074146..800f327a7ecc 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -105,6 +105,7 @@ static struct map_desc msm8x60_io_desc[] __initdata = {
         MSM_DEVICE(QGIC_DIST),
         MSM_DEVICE(QGIC_CPU),
         MSM_DEVICE(TMR),
+        MSM_DEVICE(TMR0),
         MSM_DEVICE(ACC),
         MSM_DEVICE(GCC),
 };
@@ -163,3 +164,4 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
         return __arm_ioremap_caller(phys_addr, size, mtype,
                 __builtin_return_address(0));
 }
+EXPORT_SYMBOL(__msm_ioremap);
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
index f71747db3bee..e2d58e4cb0d7 100644
--- a/arch/arm/mach-msm/iommu.c
+++ b/arch/arm/mach-msm/iommu.c
@@ -33,6 +33,16 @@
 #include <mach/iommu_hw-8xxx.h>
 #include <mach/iommu.h>
 
+#define MRC(reg, processor, op1, crn, crm, op2)                         \
+__asm__ __volatile__ (                                                  \
+"   mrc   "   #processor "," #op1 ", %0,"  #crn "," #crm "," #op2 "\n"  \
+: "=r" (reg))
+
+#define RCP15_PRRR(reg)         MRC(reg, p15, 0, c10, c2, 0)
+#define RCP15_NMRR(reg)         MRC(reg, p15, 0, c10, c2, 1)
+
+static int msm_iommu_tex_class[4];
+
 DEFINE_SPINLOCK(msm_iommu_lock);
 
 struct msm_priv {
@@ -40,23 +50,26 @@ struct msm_priv {
         struct list_head list_attached;
 };
 
-static void __flush_iotlb(struct iommu_domain *domain)
+static int __flush_iotlb(struct iommu_domain *domain)
 {
         struct msm_priv *priv = domain->priv;
         struct msm_iommu_drvdata *iommu_drvdata;
         struct msm_iommu_ctx_drvdata *ctx_drvdata;
-
+        int ret = 0;
 #ifndef CONFIG_IOMMU_PGTABLES_L2
         unsigned long *fl_table = priv->pgtable;
         int i;
 
-        dmac_flush_range(fl_table, fl_table + SZ_16K);
+        if (!list_empty(&priv->list_attached)) {
+                dmac_flush_range(fl_table, fl_table + SZ_16K);
 
-        for (i = 0; i < NUM_FL_PTE; i++)
-                if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
-                        void *sl_table = __va(fl_table[i] & FL_BASE_MASK);
-                        dmac_flush_range(sl_table, sl_table + SZ_4K);
-                }
+                for (i = 0; i < NUM_FL_PTE; i++)
+                        if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
+                                void *sl_table = __va(fl_table[i] &
+                                                                FL_BASE_MASK);
+                                dmac_flush_range(sl_table, sl_table + SZ_4K);
+                        }
+        }
 #endif
 
         list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
@@ -66,6 +79,8 @@ static void __flush_iotlb(struct iommu_domain *domain)
                 iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
                 SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
         }
+
+        return ret;
 }
 
 static void __reset_context(void __iomem *base, int ctx)
@@ -95,6 +110,7 @@ static void __reset_context(void __iomem *base, int ctx)
 
 static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
 {
+        unsigned int prrr, nmrr;
         __reset_context(base, ctx);
 
         /* Set up HTW mode */
@@ -127,11 +143,11 @@ static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
         /* Turn on TEX Remap */
         SET_TRE(base, ctx, 1);
 
-        /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume
-         * TEX class 0 for everything until attributes are properly worked out
-         */
-        SET_PRRR(base, ctx, 0);
-        SET_NMRR(base, ctx, 0);
+        /* Set TEX remap attributes */
+        RCP15_PRRR(prrr);
+        RCP15_NMRR(nmrr);
+        SET_PRRR(base, ctx, prrr);
+        SET_NMRR(base, ctx, nmrr);
 
         /* Turn on BFB prefetch */
         SET_BFBDFE(base, ctx, 1);
@@ -238,6 +254,11 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
                 goto fail;
         }
 
+        if (!list_empty(&ctx_drvdata->attached_elm)) {
+                ret = -EBUSY;
+                goto fail;
+        }
+
         list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
                 if (tmp_drvdata == ctx_drvdata) {
                         ret = -EBUSY;
@@ -248,7 +269,7 @@ static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
                           __pa(priv->pgtable));
 
         list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
-        __flush_iotlb(domain);
+        ret = __flush_iotlb(domain);
 
 fail:
         spin_unlock_irqrestore(&msm_iommu_lock, flags);
@@ -263,6 +284,7 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain,
         struct msm_iommu_drvdata *iommu_drvdata;
         struct msm_iommu_ctx_drvdata *ctx_drvdata;
         unsigned long flags;
+        int ret;
 
         spin_lock_irqsave(&msm_iommu_lock, flags);
         priv = domain->priv;
@@ -277,7 +299,10 @@ static void msm_iommu_detach_dev(struct iommu_domain *domain,
         if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
                 goto fail;
 
-        __flush_iotlb(domain);
+        ret = __flush_iotlb(domain);
+        if (ret)
+                goto fail;
+
         __reset_context(iommu_drvdata->base, ctx_dev->num);
         list_del_init(&ctx_drvdata->attached_elm);
 
@@ -296,12 +321,21 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
         unsigned long *sl_table;
         unsigned long *sl_pte;
         unsigned long sl_offset;
+        unsigned int pgprot;
         size_t len = 0x1000UL << order;
-        int ret = 0;
+        int ret = 0, tex, sh;
 
         spin_lock_irqsave(&msm_iommu_lock, flags);
-        priv = domain->priv;
 
+        sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0;
+        tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK];
+
+        if (tex < 0 || tex > NUM_TEX_CLASS - 1) {
+                ret = -EINVAL;
+                goto fail;
+        }
+
+        priv = domain->priv;
         if (!priv) {
                 ret = -EINVAL;
                 goto fail;
@@ -322,6 +356,18 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
                 goto fail;
         }
 
+        if (len == SZ_16M || len == SZ_1M) {
+                pgprot = sh ? FL_SHARED : 0;
+                pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0;
+                pgprot |= tex & 0x02 ? FL_CACHEABLE : 0;
+                pgprot |= tex & 0x04 ? FL_TEX0 : 0;
+        } else  {
+                pgprot = sh ? SL_SHARED : 0;
+                pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0;
+                pgprot |= tex & 0x02 ? SL_CACHEABLE : 0;
+                pgprot |= tex & 0x04 ? SL_TEX0 : 0;
+        }
+
         fl_offset = FL_OFFSET(va);      /* Upper 12 bits */
         fl_pte = fl_table + fl_offset;  /* int pointers, 4 bytes */
 
@@ -330,17 +376,17 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
                 for (i = 0; i < 16; i++)
                         *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
                                   FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
-                                  FL_SHARED;
+                                  FL_SHARED | pgprot;
         }
 
         if (len == SZ_1M)
                 *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE |
-                                                FL_TYPE_SECT | FL_SHARED;
+                                            FL_TYPE_SECT | FL_SHARED | pgprot;
 
         /* Need a 2nd level table */
         if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
                 unsigned long *sl;
-                sl = (unsigned long *) __get_free_pages(GFP_KERNEL,
+                sl = (unsigned long *) __get_free_pages(GFP_ATOMIC,
                                                         get_order(SZ_4K));
 
                 if (!sl) {
@@ -360,17 +406,17 @@ static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
 
         if (len == SZ_4K)
                 *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 |
-                                          SL_SHARED | SL_TYPE_SMALL;
+                                          SL_SHARED | SL_TYPE_SMALL | pgprot;
 
         if (len == SZ_64K) {
                 int i;
 
                 for (i = 0; i < 16; i++)
                         *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
-                                            SL_AP1 | SL_SHARED | SL_TYPE_LARGE;
+                                SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot;
         }
 
-        __flush_iotlb(domain);
+        ret = __flush_iotlb(domain);
 fail:
         spin_unlock_irqrestore(&msm_iommu_lock, flags);
         return ret;
@@ -455,7 +501,7 @@ static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
                 }
         }
 
-        __flush_iotlb(domain);
+        ret = __flush_iotlb(domain);
 fail:
         spin_unlock_irqrestore(&msm_iommu_lock, flags);
         return ret;
@@ -490,9 +536,6 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
         SET_CTX_TLBIALL(base, ctx, 0);
         SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT);
 
-        if (GET_FAULT(base, ctx))
-                goto fail;
-
         par = GET_PAR(base, ctx);
 
         /* We are dealing with a supersection */
@@ -501,6 +544,9 @@ static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
         else    /* Upper 20 bits from PAR, lower 12 from VA */
                 ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
 
+        if (GET_FAULT(base, ctx))
+                ret = 0;
+
 fail:
         spin_unlock_irqrestore(&msm_iommu_lock, flags);
         return ret;
@@ -543,8 +589,8 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
 {
         struct msm_iommu_drvdata *drvdata = dev_id;
         void __iomem *base;
-        unsigned int fsr = 0;
-        int ncb = 0, i = 0;
+        unsigned int fsr;
+        int ncb, i;
 
         spin_lock(&msm_iommu_lock);
 
@@ -555,7 +601,6 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
 
         base = drvdata->base;
 
-        pr_err("===== WOAH! =====\n");
         pr_err("Unexpected IOMMU page fault!\n");
         pr_err("base = %08x\n", (unsigned int) base);
 
@@ -585,8 +630,47 @@ static struct iommu_ops msm_iommu_ops = {
         .domain_has_cap = msm_iommu_domain_has_cap
 };
 
-static int msm_iommu_init(void)
+static int __init get_tex_class(int icp, int ocp, int mt, int nos)
+{
+        int i = 0;
+        unsigned int prrr = 0;
+        unsigned int nmrr = 0;
+        int c_icp, c_ocp, c_mt, c_nos;
+
+        RCP15_PRRR(prrr);
+        RCP15_NMRR(nmrr);
+
+        for (i = 0; i < NUM_TEX_CLASS; i++) {
+                c_nos = PRRR_NOS(prrr, i);
+                c_mt = PRRR_MT(prrr, i);
+                c_icp = NMRR_ICP(nmrr, i);
+                c_ocp = NMRR_OCP(nmrr, i);
+
+                if (icp == c_icp && ocp == c_ocp && c_mt == mt && c_nos == nos)
+                        return i;
+        }
+
+        return -ENODEV;
+}
+
+static void __init setup_iommu_tex_classes(void)
+{
+        msm_iommu_tex_class[MSM_IOMMU_ATTR_NONCACHED] =
+                        get_tex_class(CP_NONCACHED, CP_NONCACHED, MT_NORMAL, 1);
+
+        msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_WA] =
+                        get_tex_class(CP_WB_WA, CP_WB_WA, MT_NORMAL, 1);
+
+        msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_NWA] =
+                        get_tex_class(CP_WB_NWA, CP_WB_NWA, MT_NORMAL, 1);
+
+        msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WT] =
+                        get_tex_class(CP_WT, CP_WT, MT_NORMAL, 1);
+}
+
+static int __init msm_iommu_init(void)
 {
+        setup_iommu_tex_classes();
         register_iommu(&msm_iommu_ops);
         return 0;
 }
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
index 9019cee2907b..b83c73b41fd1 100644
--- a/arch/arm/mach-msm/iommu_dev.c
+++ b/arch/arm/mach-msm/iommu_dev.c
@@ -346,7 +346,7 @@ static struct platform_driver msm_iommu_ctx_driver = {
         .remove         = msm_iommu_ctx_remove,
 };
 
-static int msm_iommu_driver_init(void)
+static int __init msm_iommu_driver_init(void)
 {
         int ret;
         ret = platform_driver_register(&msm_iommu_driver);
@@ -365,7 +365,7 @@ error:
         return ret;
 }
 
-static void msm_iommu_driver_exit(void)
+static void __exit msm_iommu_driver_exit(void)
 {
         platform_driver_unregister(&msm_iommu_ctx_driver);
         platform_driver_unregister(&msm_iommu_driver);
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
new file mode 100644
index 000000000000..0f427bc94447
--- /dev/null
+++ b/arch/arm/mach-msm/platsmp.c
@@ -0,0 +1,166 @@
+/*
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/hardware/gic.h>
+#include <asm/cacheflush.h>
+#include <asm/mach-types.h>
+
+#include <mach/msm_iomap.h>
+
+#include "scm-boot.h"
+
+#define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
+#define SCSS_CPU1CORE_RESET 0xD80
+#define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
+
+/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+#define GIC_PPI_EDGE_MASK 0xFFFFD7FF
+
+extern void msm_secondary_startup(void);
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen".
+ */
+volatile int pen_release = -1;
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        /* Configure edge-triggered PPIs */
+        writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+        /*
+         * if any interrupts are already enabled for the primary
+         * core (e.g. timer irq), then they will not have been enabled
+         * for us: do so
+         */
+        gic_secondary_init(0);
+
+        /*
+         * let the primary processor know we're out of the
+         * pen, then head off into the C entry point
+         */
+        pen_release = -1;
+        smp_wmb();
+
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+
+static __cpuinit void prepare_cold_cpu(unsigned int cpu)
+{
+        int ret;
+        ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
+                                SCM_FLAG_COLDBOOT_CPU1);
+        if (ret == 0) {
+                void *sc1_base_ptr;
+                sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
+                if (sc1_base_ptr) {
+                        writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
+                        writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
+                        writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
+                        iounmap(sc1_base_ptr);
+                }
+        } else
+                printk(KERN_DEBUG "Failed to set secondary core boot "
+                                  "address\n");
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+        static int cold_boot_done;
+
+        /* Only need to bring cpu out of reset this way once */
+        if (cold_boot_done == false) {
+                prepare_cold_cpu(cpu);
+                cold_boot_done = true;
+        }
+
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+
+        /*
+         * The secondary processor is waiting to be released from
+         * the holding pen - release it, then wait for it to flag
+         * that it has been released by resetting pen_release.
+         *
+         * Note that "pen_release" is the hardware CPU ID, whereas
+         * "cpu" is Linux's internal ID.
+         */
+        pen_release = cpu;
+        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+
+        /*
+         * Send the secondary CPU a soft interrupt, thereby causing
+         * the boot monitor to read the system wide flags register,
+         * and branch to the address found there.
+         */
+        smp_cross_call(cpumask_of(cpu), 1);
+
+        timeout = jiffies + (1 * HZ);
+        while (time_before(jiffies, timeout)) {
+                smp_rmb();
+                if (pen_release == -1)
+                        break;
+
+                udelay(10);
+        }
+
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+
+        return pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system. The msm8x60
+ * does not support the ARM SCU, so just set the possible cpu mask to
+ * NR_CPUS.
+ */
+void __init smp_init_cpus(void)
+{
+        unsigned int i;
+
+        for (i = 0; i < NR_CPUS; i++)
+                set_cpu_possible(i, true);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
+
+        /*
+         * Initialise the present map, which describes the set of CPUs
+         * actually populated at the present time.
+         */
+        for (i = 0; i < max_cpus; i++)
+                set_cpu_present(i, true);
+}
diff --git a/arch/arm/mach-msm/scm-boot.c b/arch/arm/mach-msm/scm-boot.c
new file mode 100644
index 000000000000..45cee3e469a5
--- /dev/null
+++ b/arch/arm/mach-msm/scm-boot.c
@@ -0,0 +1,39 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+
+#include "scm.h"
+#include "scm-boot.h"
+
+/*
+ * Set the cold/warm boot address for one of the CPU cores.
+ */
+int scm_set_boot_addr(phys_addr_t addr, int flags)
+{
+        struct {
+                unsigned int flags;
+                phys_addr_t  addr;
+        } cmd;
+
+        cmd.addr = addr;
+        cmd.flags = flags;
+        return scm_call(SCM_SVC_BOOT, SCM_BOOT_ADDR,
+                        &cmd, sizeof(cmd), NULL, 0);
+}
+EXPORT_SYMBOL(scm_set_boot_addr);
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-msm/scm-boot.h
new file mode 100644
index 000000000000..68f9b6153d74
--- /dev/null
+++ b/arch/arm/mach-msm/scm-boot.h
@@ -0,0 +1,38 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __MACH_SCM_BOOT_H
+#define __MACH_SCM_BOOT_H
+
+#define SCM_BOOT_ADDR                   0x1
+#define SCM_FLAG_COLDBOOT_CPU1          0x1
+#define SCM_FLAG_WARMBOOT_CPU1          0x2
+#define SCM_FLAG_WARMBOOT_CPU0          0x4
+
+int scm_set_boot_addr(phys_addr_t addr, int flags);
+
+#endif
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c
new file mode 100644
index 000000000000..f4b9bc90d6a7
--- /dev/null
+++ b/arch/arm/mach-msm/scm.c
@@ -0,0 +1,287 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+
+#include <asm/cacheflush.h>
+
+#include "scm.h"
+
+/* Cache line size for msm8x60 */
+#define CACHELINESIZE 32
+
+#define SCM_ENOMEM              -5
+#define SCM_EOPNOTSUPP          -4
+#define SCM_EINVAL_ADDR         -3
+#define SCM_EINVAL_ARG          -2
+#define SCM_ERROR               -1
+#define SCM_INTERRUPTED         1
+
+static DEFINE_MUTEX(scm_lock);
+
+/**
+ * struct scm_command - one SCM command buffer
+ * @len: total available memory for command and response
+ * @buf_offset: start of command buffer
+ * @resp_hdr_offset: start of response buffer
+ * @id: command to be executed
+ * @buf: buffer returned from scm_get_command_buffer()
+ *
+ * An SCM command is layed out in memory as follows:
+ *
+ *      ------------------- <--- struct scm_command
+ *      | command header  |
+ *      ------------------- <--- scm_get_command_buffer()
+ *      | command buffer  |
+ *      ------------------- <--- struct scm_response and
+ *      | response header |      scm_command_to_response()
+ *      ------------------- <--- scm_get_response_buffer()
+ *      | response buffer |
+ *      -------------------
+ *
+ * There can be arbitrary padding between the headers and buffers so
+ * you should always use the appropriate scm_get_*_buffer() routines
+ * to access the buffers in a safe manner.
+ */
+struct scm_command {
+        u32     len;
+        u32     buf_offset;
+        u32     resp_hdr_offset;
+        u32     id;
+        u32     buf[0];
+};
+
+/**
+ * struct scm_response - one SCM response buffer
+ * @len: total available memory for response
+ * @buf_offset: start of response data relative to start of scm_response
+ * @is_complete: indicates if the command has finished processing
+ */
+struct scm_response {
+        u32     len;
+        u32     buf_offset;
+        u32     is_complete;
+};
+
+/**
+ * alloc_scm_command() - Allocate an SCM command
+ * @cmd_size: size of the command buffer
+ * @resp_size: size of the response buffer
+ *
+ * Allocate an SCM command, including enough room for the command
+ * and response headers as well as the command and response buffers.
+ *
+ * Returns a valid &scm_command on success or %NULL if the allocation fails.
+ */
+static struct scm_command *alloc_scm_command(size_t cmd_size, size_t resp_size)
+{
+        struct scm_command *cmd;
+        size_t len = sizeof(*cmd) + sizeof(struct scm_response) + cmd_size +
+                resp_size;
+
+        cmd = kzalloc(PAGE_ALIGN(len), GFP_KERNEL);
+        if (cmd) {
+                cmd->len = len;
+                cmd->buf_offset = offsetof(struct scm_command, buf);
+                cmd->resp_hdr_offset = cmd->buf_offset + cmd_size;
+        }
+        return cmd;
+}
+
+/**
+ * free_scm_command() - Free an SCM command
+ * @cmd: command to free
+ *
+ * Free an SCM command.
+ */
+static inline void free_scm_command(struct scm_command *cmd)
+{
+        kfree(cmd);
+}
+
+/**
+ * scm_command_to_response() - Get a pointer to a scm_response
+ * @cmd: command
+ *
+ * Returns a pointer to a response for a command.
+ */
+static inline struct scm_response *scm_command_to_response(
+                const struct scm_command *cmd)
+{
+        return (void *)cmd + cmd->resp_hdr_offset;
+}
+
+/**
+ * scm_get_command_buffer() - Get a pointer to a command buffer
+ * @cmd: command
+ *
+ * Returns a pointer to the command buffer of a command.
+ */
+static inline void *scm_get_command_buffer(const struct scm_command *cmd)
+{
+        return (void *)cmd->buf;
+}
+
+/**
+ * scm_get_response_buffer() - Get a pointer to a response buffer
+ * @rsp: response
+ *
+ * Returns a pointer to a response buffer of a response.
+ */
+static inline void *scm_get_response_buffer(const struct scm_response *rsp)
+{
+        return (void *)rsp + rsp->buf_offset;
+}
+
+static int scm_remap_error(int err)
+{
+        switch (err) {
+        case SCM_ERROR:
+                return -EIO;
+        case SCM_EINVAL_ADDR:
+        case SCM_EINVAL_ARG:
+                return -EINVAL;
+        case SCM_EOPNOTSUPP:
+                return -EOPNOTSUPP;
+        case SCM_ENOMEM:
+                return -ENOMEM;
+        }
+        return -EINVAL;
+}
+
+static u32 smc(u32 cmd_addr)
+{
+        int context_id;
+        register u32 r0 asm("r0") = 1;
+        register u32 r1 asm("r1") = (u32)&context_id;
+        register u32 r2 asm("r2") = cmd_addr;
+        asm(
+                __asmeq("%0", "r0")
+                __asmeq("%1", "r0")
+                __asmeq("%2", "r1")
+                __asmeq("%3", "r2")
+                "smc    #0      @ switch to secure world\n"
+                : "=r" (r0)
+                : "r" (r0), "r" (r1), "r" (r2)
+                : "r3");
+        return r0;
+}
+
+static int __scm_call(const struct scm_command *cmd)
+{
+        int ret;
+        u32 cmd_addr = virt_to_phys(cmd);
+
+        /*
+         * Flush the entire cache here so callers don't have to remember
+         * to flush the cache when passing physical addresses to the secure
+         * side in the buffer.
+         */
+        flush_cache_all();
+        do {
+                ret = smc(cmd_addr);
+                if (ret < 0) {
+                        ret = scm_remap_error(ret);
+                        break;
+                }
+        } while (ret == SCM_INTERRUPTED);
+
+        return ret;
+}
+
+/**
+ * scm_call() - Send an SCM command
+ * @svc_id: service identifier
+ * @cmd_id: command identifier
+ * @cmd_buf: command buffer
+ * @cmd_len: length of the command buffer
+ * @resp_buf: response buffer
+ * @resp_len: length of the response buffer
+ *
+ * Sends a command to the SCM and waits for the command to finish processing.
+ */
+int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
+                void *resp_buf, size_t resp_len)
+{
+        int ret;
+        struct scm_command *cmd;
+        struct scm_response *rsp;
+
+        cmd = alloc_scm_command(cmd_len, resp_len);
+        if (!cmd)
+                return -ENOMEM;
+
+        cmd->id = (svc_id << 10) | cmd_id;
+        if (cmd_buf)
+                memcpy(scm_get_command_buffer(cmd), cmd_buf, cmd_len);
+
+        mutex_lock(&scm_lock);
+        ret = __scm_call(cmd);
+        mutex_unlock(&scm_lock);
+        if (ret)
+                goto out;
+
+        rsp = scm_command_to_response(cmd);
+        do {
+                u32 start = (u32)rsp;
+                u32 end = (u32)scm_get_response_buffer(rsp) + resp_len;
+                start &= ~(CACHELINESIZE - 1);
+                while (start < end) {
+                        asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
+                             : "memory");
+                        start += CACHELINESIZE;
+                }
+        } while (!rsp->is_complete);
+
+        if (resp_buf)
+                memcpy(resp_buf, scm_get_response_buffer(rsp), resp_len);
+out:
+        free_scm_command(cmd);
+        return ret;
+}
+EXPORT_SYMBOL(scm_call);
+
+u32 scm_get_version(void)
+{
+        int context_id;
+        static u32 version = -1;
+        register u32 r0 asm("r0") = 0x1 << 8;
+        register u32 r1 asm("r1") = (u32)&context_id;
+
+        if (version != -1)
+                return version;
+
+        mutex_lock(&scm_lock);
+        asm(
+                __asmeq("%0", "r1")
+                __asmeq("%1", "r0")
+                __asmeq("%2", "r1")
+                "smc    #0      @ switch to secure world\n"
+                : "=r" (r1)
+                : "r" (r0), "r" (r1)
+                : "r2", "r3");
+        version = r1;
+        mutex_unlock(&scm_lock);
+
+        return version;
+}
+EXPORT_SYMBOL(scm_get_version);
diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-msm/scm.h
new file mode 100644
index 000000000000..261786be11c5
--- /dev/null
+++ b/arch/arm/mach-msm/scm.h
@@ -0,0 +1,41 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __MACH_SCM_H
+#define __MACH_SCM_H
+
+#define SCM_SVC_BOOT                    0x1
+#define SCM_SVC_PIL                     0x2
+
+extern int scm_call(u32 svc_id, u32 cmd_id, const void *cmd_buf, size_t cmd_len,
+                void *resp_buf, size_t resp_len);
+
+#define SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
+
+extern u32 scm_get_version(void);
+
+#endif
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
index b0794524ba6e..152eefda3ce6 100644
--- a/arch/arm/mach-msm/sirc.c
+++ b/arch/arm/mach-msm/sirc.c
@@ -40,9 +40,6 @@ static struct sirc_cascade_regs sirc_reg_table[] = {
         }
 };
 
-static unsigned int save_type;
-static unsigned int save_polarity;
-
 /* Mask off the given interrupt. Keep the int_enable mask in sync with
    the enable reg, so it can be restored after power collapse. */
 static void sirc_irq_mask(unsigned int irq)
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index f07dc7c738f0..657be73297db 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -14,6 +14,8 @@
  *
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/fs.h>
@@ -89,7 +91,7 @@ static void smd_diag(void)
         x = smem_find(ID_DIAG_ERR_MSG, SZ_DIAG_ERR_MSG);
         if (x != 0) {
                 x[SZ_DIAG_ERR_MSG - 1] = 0;
-                pr_info("smem: DIAG '%s'\n", x);
+                pr_debug("DIAG '%s'\n", x);
         }
 }
 
@@ -312,7 +314,7 @@ static void smd_state_change(struct smd_channel *ch,
 {
         ch->last_state = next;
 
-        pr_info("SMD: ch %d %d -> %d\n", ch->n, last, next);
+        pr_debug("ch %d %d -> %d\n", ch->n, last, next);
 
         switch (next) {
         case SMD_SS_OPENING:
@@ -601,7 +603,7 @@ static int smd_alloc_channel(const char *name, uint32_t cid, uint32_t type)
         ch->pdev.name = ch->name;
         ch->pdev.id = -1;
 
-        pr_info("smd_alloc_channel() cid=%02d size=%05d '%s'\n",
+        pr_debug("smd_alloc_channel() cid=%02d size=%05d '%s'\n",
                 ch->n, ch->fifo_size, ch->name);
 
         mutex_lock(&smd_creation_mutex);
@@ -621,7 +623,7 @@ static void smd_channel_probe_worker(struct work_struct *work)
 
         shared = smem_find(ID_CH_ALLOC_TBL, sizeof(*shared) * 64);
         if (!shared) {
-                pr_err("smd: cannot find allocation table\n");
+                pr_err("cannot find allocation table\n");
                 return;
         }
         for (n = 0; n < 64; n++) {
@@ -725,8 +727,6 @@ int smd_close(smd_channel_t *ch)
 {
         unsigned long flags;
 
-        pr_info("smd_close(%p)\n", ch);
-
         if (ch == 0)
                 return -1;
 
@@ -939,7 +939,6 @@ int smsm_set_sleep_duration(uint32_t delay)
 int smd_core_init(void)
 {
         int r;
-        pr_info("smd_core_init()\n");
 
         /* wait for essential items to be initialized */
         for (;;) {
@@ -992,15 +991,11 @@ int smd_core_init(void)
         smsm_change_state(SMSM_STATE_APPS_DEM, ~0, 0);
 #endif
 
-        pr_info("smd_core_init() done\n");
-
         return 0;
 }
 
 static int __devinit msm_smd_probe(struct platform_device *pdev)
 {
-        pr_info("smd_init()\n");
-
         /*
          * If we haven't waited for the ARM9 to boot up till now,
          * then we need to wait here. Otherwise this should just
diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c
index f91c3b7bc655..8736afff82f3 100644
--- a/arch/arm/mach-msm/smd_debug.c
+++ b/arch/arm/mach-msm/smd_debug.c
@@ -270,8 +270,10 @@ void smsm_print_sleep_info(void)
 {
         unsigned long flags;
         uint32_t *ptr;
+#ifndef CONFIG_ARCH_MSM_SCORPION
         struct tramp_gpio_smem *gpio;
         struct smsm_interrupt_info *int_info;
+#endif
 
 
         spin_lock_irqsave(&smem_lock, flags);
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 950100f19d07..c105d28b53e3 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -47,6 +47,19 @@ enum {
 
 #define GPT_HZ 32768
 
+enum timer_location {
+        LOCAL_TIMER = 0,
+        GLOBAL_TIMER = 1,
+};
+
+#ifdef MSM_TMR0_BASE
+#define MSM_TMR_GLOBAL          (MSM_TMR0_BASE - MSM_TMR_BASE)
+#else
+#define MSM_TMR_GLOBAL          0
+#endif
+
+#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
+
 #if defined(CONFIG_ARCH_QSD8X50)
 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
 #define MSM_DGT_SHIFT (0)
@@ -65,49 +78,67 @@ struct msm_clock {
         void __iomem                *regbase;
         uint32_t                    freq;
         uint32_t                    shift;
+        void __iomem                *global_counter;
+        void __iomem                *local_counter;
+};
+
+enum {
+        MSM_CLOCK_GPT,
+        MSM_CLOCK_DGT,
+        NR_TIMERS,
 };
 
+
+static struct msm_clock msm_clocks[];
+static struct clock_event_device *local_clock_event;
+
 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *evt = dev_id;
+        if (smp_processor_id() != 0)
+                evt = local_clock_event;
+        if (evt->event_handler == NULL)
+                return IRQ_HANDLED;
         evt->event_handler(evt);
         return IRQ_HANDLED;
 }
 
-static cycle_t msm_gpt_read(struct clocksource *cs)
+static cycle_t msm_read_timer_count(struct clocksource *cs)
 {
-        return readl(MSM_GPT_BASE + TIMER_COUNT_VAL);
+        struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
+
+        return readl(clk->global_counter);
 }
 
-static cycle_t msm_dgt_read(struct clocksource *cs)
+static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
 {
-        return readl(MSM_DGT_BASE + TIMER_COUNT_VAL) >> MSM_DGT_SHIFT;
+#ifdef CONFIG_SMP
+        int i;
+        for (i = 0; i < NR_TIMERS; i++)
+                if (evt == &(msm_clocks[i].clockevent))
+                        return &msm_clocks[i];
+        return &msm_clocks[MSM_GLOBAL_TIMER];
+#else
+        return container_of(evt, struct msm_clock, clockevent);
+#endif
 }
 
 static int msm_timer_set_next_event(unsigned long cycles,
                                     struct clock_event_device *evt)
 {
-        struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);
-        uint32_t now = readl(clock->regbase + TIMER_COUNT_VAL);
+        struct msm_clock *clock = clockevent_to_clock(evt);
+        uint32_t now = readl(clock->local_counter);
         uint32_t alarm = now + (cycles << clock->shift);
-        int late;
 
         writel(alarm, clock->regbase + TIMER_MATCH_VAL);
-        now = readl(clock->regbase + TIMER_COUNT_VAL);
-        late = now - alarm;
-        if (late >= (-2 << clock->shift) && late < DGT_HZ*5) {
-                printk(KERN_NOTICE "msm_timer_set_next_event(%lu) clock %s, "
-                       "alarm already expired, now %x, alarm %x, late %d\n",
-                       cycles, clock->clockevent.name, now, alarm, late);
-                return -ETIME;
-        }
         return 0;
 }
 
 static void msm_timer_set_mode(enum clock_event_mode mode,
                               struct clock_event_device *evt)
 {
-        struct msm_clock *clock = container_of(evt, struct msm_clock, clockevent);
+        struct msm_clock *clock = clockevent_to_clock(evt);
+
         switch (mode) {
         case CLOCK_EVT_MODE_RESUME:
         case CLOCK_EVT_MODE_PERIODIC:
@@ -123,7 +154,7 @@ static void msm_timer_set_mode(enum clock_event_mode mode,
 }
 
 static struct msm_clock msm_clocks[] = {
-        {
+        [MSM_CLOCK_GPT] = {
                 .clockevent = {
                         .name           = "gp_timer",
                         .features       = CLOCK_EVT_FEAT_ONESHOT,
@@ -135,9 +166,8 @@ static struct msm_clock msm_clocks[] = {
                 .clocksource = {
                         .name           = "gp_timer",
                         .rating         = 200,
-                        .read           = msm_gpt_read,
+                        .read           = msm_read_timer_count,
                         .mask           = CLOCKSOURCE_MASK(32),
-                        .shift          = 17,
                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
                 },
                 .irq = {
@@ -148,9 +178,12 @@ static struct msm_clock msm_clocks[] = {
                         .irq     = INT_GP_TIMER_EXP
                 },
                 .regbase = MSM_GPT_BASE,
-                .freq = GPT_HZ
+                .freq = GPT_HZ,
+                .local_counter = MSM_GPT_BASE + TIMER_COUNT_VAL,
+                .global_counter = MSM_GPT_BASE + TIMER_COUNT_VAL +
+                        MSM_TMR_GLOBAL,
         },
-        {
+        [MSM_CLOCK_DGT] = {
                 .clockevent = {
                         .name           = "dg_timer",
                         .features       = CLOCK_EVT_FEAT_ONESHOT,
@@ -162,9 +195,8 @@ static struct msm_clock msm_clocks[] = {
                 .clocksource = {
                         .name           = "dg_timer",
                         .rating         = 300,
-                        .read           = msm_dgt_read,
+                        .read           = msm_read_timer_count,
                         .mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
-                        .shift          = 24 - MSM_DGT_SHIFT,
                         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
                 },
                 .irq = {
@@ -176,7 +208,10 @@ static struct msm_clock msm_clocks[] = {
                 },
                 .regbase = MSM_DGT_BASE,
                 .freq = DGT_HZ >> MSM_DGT_SHIFT,
-                .shift = MSM_DGT_SHIFT
+                .shift = MSM_DGT_SHIFT,
+                .local_counter = MSM_DGT_BASE + TIMER_COUNT_VAL,
+                .global_counter = MSM_DGT_BASE + TIMER_COUNT_VAL +
+                        MSM_TMR_GLOBAL,
         }
 };
 
@@ -185,7 +220,7 @@ static void __init msm_timer_init(void)
         int i;
         int res;
 
-#ifdef CONFIG_ARCH_MSM8X60
+#ifdef CONFIG_ARCH_MSM_SCORPIONMP
         writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 #endif
 
@@ -205,8 +240,7 @@ static void __init msm_timer_init(void)
                 ce->min_delta_ns = clockevent_delta2ns(4, ce);
                 ce->cpumask = cpumask_of(0);
 
-                cs->mult = clocksource_hz2mult(clock->freq, cs->shift);
-                res = clocksource_register(cs);
+                res = clocksource_register_hz(cs, clock->freq);
                 if (res)
                         printk(KERN_ERR "msm_timer_init: clocksource_register "
                                "failed for %s\n", cs->name);
@@ -220,6 +254,48 @@ static void __init msm_timer_init(void)
         }
 }
 
+#ifdef CONFIG_SMP
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+        struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
+
+        /* Use existing clock_event for cpu 0 */
+        if (!smp_processor_id())
+                return;
+
+        writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
+
+        if (!local_clock_event) {
+                writel(0, clock->regbase  + TIMER_ENABLE);
+                writel(0, clock->regbase + TIMER_CLEAR);
+                writel(~0, clock->regbase + TIMER_MATCH_VAL);
+        }
+        evt->irq = clock->irq.irq;
+        evt->name = "local_timer";
+        evt->features = CLOCK_EVT_FEAT_ONESHOT;
+        evt->rating = clock->clockevent.rating;
+        evt->set_mode = msm_timer_set_mode;
+        evt->set_next_event = msm_timer_set_next_event;
+        evt->shift = clock->clockevent.shift;
+        evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
+        evt->max_delta_ns =
+                clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
+        evt->min_delta_ns = clockevent_delta2ns(4, evt);
+
+        local_clock_event = evt;
+
+        gic_enable_ppi(clock->irq.irq);
+
+        clockevents_register_device(evt);
+}
+
+inline int local_timer_ack(void)
+{
+        return 1;
+}
+
+#endif
+
 struct sys_timer msm_timer = {
         .init = msm_timer_init
 };
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 788bdace1304..3eff39921d4d 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -65,7 +65,7 @@
  */
 #define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
 #define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
-#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1700)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1570)
 
 #define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
 #define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
deleted file mode 100644
index 38ca09a5df9d..000000000000
--- a/arch/arm/mach-mx25/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-if ARCH_MX25
-
-comment "MX25 platforms:"
-
-config MACH_MX25_3DS
-        bool "Support MX25PDK (3DS) Platform"
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_ESDHC
-
-config MACH_EUKREA_CPUIMX25
-        bool "Support Eukrea CPUIMX25 Platform"
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_FLEXCAN
-        select IMX_HAVE_PLATFORM_ESDHC
-        select MXC_ULPI if USB_ULPI
-
-choice
-        prompt "Baseboard"
-        depends on MACH_EUKREA_CPUIMX25
-        default MACH_EUKREA_MBIMXSD25_BASEBOARD
-
-config MACH_EUKREA_MBIMXSD25_BASEBOARD
-        bool "Eukrea MBIMXSD development board"
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        help
-          This adds board specific devices that can be found on Eukrea's
-          MBIMXSD evaluation board.
-
-endchoice
-
-endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
deleted file mode 100644
index d9e46ce00a4e..000000000000
--- a/arch/arm/mach-mx25/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-obj-y                           := mm.o devices.o
-obj-$(CONFIG_ARCH_MX25)         += clock.o
-obj-$(CONFIG_MACH_MX25_3DS)     += mach-mx25_3ds.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX25)              += mach-cpuimx25.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD)   += eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx25/Makefile.boot b/arch/arm/mach-mx25/Makefile.boot
deleted file mode 100644
index e1dd366f836b..000000000000
--- a/arch/arm/mach-mx25/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-   zreladdr-y   := 0x80008000
-params_phys-y   := 0x80000100
-initrd_phys-y   := 0x80800000
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
deleted file mode 100644
index 1d0eb3e85941..000000000000
--- a/arch/arm/mach-mx25/devices.c
+++ /dev/null
@@ -1,308 +0,0 @@
-/*
- * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <mach/mx25.h>
-#include <mach/irqs.h>
-
-static u64 otg_dmamask = DMA_BIT_MASK(32);
-
-static struct resource mxc_otg_resources[] = {
-        {
-                .start = MX25_OTG_BASE_ADDR,
-                .end = MX25_OTG_BASE_ADDR + 0x1ff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 37,
-                .end = 37,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_otg = {
-        .name = "mxc-ehci",
-        .id = 0,
-        .dev = {
-                .coherent_dma_mask = 0xffffffff,
-                .dma_mask = &otg_dmamask,
-        },
-        .resource = mxc_otg_resources,
-        .num_resources = ARRAY_SIZE(mxc_otg_resources),
-};
-
-/* OTG gadget device */
-struct platform_device otg_udc_device = {
-        .name = "fsl-usb2-udc",
-        .id   = -1,
-        .dev  = {
-                .dma_mask          = &otg_dmamask,
-                .coherent_dma_mask = 0xffffffff,
-        },
-        .resource = mxc_otg_resources,
-        .num_resources = ARRAY_SIZE(mxc_otg_resources),
-};
-
-static u64 usbh2_dmamask = DMA_BIT_MASK(32);
-
-static struct resource mxc_usbh2_resources[] = {
-        {
-                .start = MX25_OTG_BASE_ADDR + 0x400,
-                .end = MX25_OTG_BASE_ADDR + 0x5ff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 35,
-                .end = 35,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_usbh2 = {
-        .name = "mxc-ehci",
-        .id = 1,
-        .dev = {
-                .coherent_dma_mask = 0xffffffff,
-                .dma_mask = &usbh2_dmamask,
-        },
-        .resource = mxc_usbh2_resources,
-        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
-};
-
-static struct resource mxc_pwm_resources0[] = {
-        {
-                .start  = 0x53fe0000,
-                .end    = 0x53fe3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start   = 26,
-                .end     = 26,
-                .flags   = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_pwm_device0 = {
-        .name = "mxc_pwm",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_pwm_resources0),
-        .resource = mxc_pwm_resources0,
-};
-
-static struct resource mxc_pwm_resources1[] = {
-        {
-                .start  = 0x53fa0000,
-                .end    = 0x53fa3fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start   = 36,
-                .end     = 36,
-                .flags   = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_pwm_device1 = {
-        .name = "mxc_pwm",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_pwm_resources1),
-        .resource = mxc_pwm_resources1,
-};
-
-static struct resource mxc_pwm_resources2[] = {
-        {
-                .start  = 0x53fa8000,
-                .end    = 0x53fabfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start   = 41,
-                .end     = 41,
-                .flags   = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_pwm_device2 = {
-        .name = "mxc_pwm",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_pwm_resources2),
-        .resource = mxc_pwm_resources2,
-};
-
-static struct resource mxc_keypad_resources[] = {
-        {
-                .start  = 0x43fa8000,
-                .end    = 0x43fabfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start   = 24,
-                .end     = 24,
-                .flags   = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_keypad_device = {
-        .name = "mxc-keypad",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(mxc_keypad_resources),
-        .resource = mxc_keypad_resources,
-};
-
-static struct resource mxc_pwm_resources3[] = {
-        {
-                .start  = 0x53fc8000,
-                .end    = 0x53fcbfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start   = 42,
-                .end     = 42,
-                .flags   = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_pwm_device3 = {
-        .name = "mxc_pwm",
-        .id = 3,
-        .num_resources = ARRAY_SIZE(mxc_pwm_resources3),
-        .resource = mxc_pwm_resources3,
-};
-
-static struct mxc_gpio_port imx_gpio_ports[] = {
-        {
-                .chip.label = "gpio-0",
-                .base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT,
-                .irq = 52,
-                .virtual_irq_start = MXC_GPIO_IRQ_START,
-        }, {
-                .chip.label = "gpio-1",
-                .base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT,
-                .irq = 51,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        }, {
-                .chip.label = "gpio-2",
-                .base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT,
-                .irq = 16,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-        }, {
-                .chip.label = "gpio-3",
-                .base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT,
-                .irq = 23,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
-        }
-};
-
-int __init imx25_register_gpios(void)
-{
-        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
-}
-
-static struct resource mx25_rtc_resources[] = {
-        {
-                .start  = MX25_DRYICE_BASE_ADDR,
-                .end    = MX25_DRYICE_BASE_ADDR + 0x40,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MX25_INT_DRYICE,
-                .flags  = IORESOURCE_IRQ
-        },
-};
-
-struct platform_device mx25_rtc_device = {
-        .name   = "imxdi_rtc",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(mx25_rtc_resources),
-        .resource       = mx25_rtc_resources,
-};
-
-static struct resource mx25_fb_resources[] = {
-        {
-                .start  = MX25_LCDC_BASE_ADDR,
-                .end    = MX25_LCDC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MX25_INT_LCDC,
-                .end    = MX25_INT_LCDC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mx25_fb_device = {
-        .name           = "imx-fb",
-        .id             = 0,
-        .resource       = mx25_fb_resources,
-        .num_resources  = ARRAY_SIZE(mx25_fb_resources),
-        .dev            = {
-                .coherent_dma_mask = 0xFFFFFFFF,
-        },
-};
-
-static struct resource mxc_wdt_resources[] = {
-        {
-                .start = MX25_WDOG_BASE_ADDR,
-                .end = MX25_WDOG_BASE_ADDR + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device mxc_wdt = {
-        .name = "imx2-wdt",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_wdt_resources),
-        .resource = mxc_wdt_resources,
-};
-
-static struct resource mx25_kpp_resources[] = {
-        {
-                .start  = MX25_KPP_BASE_ADDR,
-                .end    = MX25_KPP_BASE_ADDR + 0xf,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MX25_INT_KPP,
-                .end    = MX25_INT_KPP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mx25_kpp_device = {
-        .name   = "imx-keypad",
-        .id     = -1,
-        .num_resources  = ARRAY_SIZE(mx25_kpp_resources),
-        .resource       = mx25_kpp_resources,
-};
-
-static struct resource mx25_csi_resources[] = {
-        {
-                .start  = MX25_CSI_BASE_ADDR,
-                .end    = MX25_CSI_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MX25_INT_CSI,
-                .flags  = IORESOURCE_IRQ
-        },
-};
-
-struct platform_device mx25_csi_device = {
-        .name   = "mx2-camera",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(mx25_csi_resources),
-        .resource       = mx25_csi_resources,
-        .dev            = {
-                .coherent_dma_mask = 0xffffffff,
-        },
-};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
deleted file mode 100644
index 7b70a43c3a4b..000000000000
--- a/arch/arm/mach-mx25/devices.h
+++ /dev/null
@@ -1,13 +0,0 @@
-extern struct platform_device mxc_otg;
-extern struct platform_device otg_udc_device;
-extern struct platform_device mxc_usbh2;
-extern struct platform_device mxc_pwm_device0;
-extern struct platform_device mxc_pwm_device1;
-extern struct platform_device mxc_pwm_device2;
-extern struct platform_device mxc_pwm_device3;
-extern struct platform_device mxc_keypad_device;
-extern struct platform_device mx25_rtc_device;
-extern struct platform_device mx25_fb_device;
-extern struct platform_device mxc_wdt;
-extern struct platform_device mx25_kpp_device;
-extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 5000ac1f93e3..0717f887cba0 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -1,21 +1,35 @@
 if ARCH_MX3
 
+# ARCH_MX31 and ARCH_MX35 are left for compatibility
+# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
+# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
+# more sensible) names are used: SOC_IMX31 and SOC_IMX35
 config ARCH_MX31
-        select ARCH_HAS_RNGA
-        select ARCH_MXC_AUDMUX_V2
         bool
 
 config ARCH_MX35
         bool
+
+config SOC_IMX31
+        bool
+        select IMX_HAVE_PLATFORM_MXC_RNGA
+        select ARCH_MXC_AUDMUX_V2
+        select ARCH_MX31
+        select MXC_AVIC
+
+config SOC_IMX35
+        bool
         select ARCH_MXC_IOMUX_V3
         select ARCH_MXC_AUDMUX_V2
         select HAVE_EPIT
+        select ARCH_MX35
+        select MXC_AVIC
 
 comment "MX3 platforms:"
 
 config MACH_MX31ADS
         bool "Support MX31ADS platforms"
-        select ARCH_MX31
+        select SOC_IMX31
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
@@ -37,10 +51,15 @@ config MACH_MX31ADS_WM1133_EV1
 
 config MACH_PCM037
         bool "Support Phytec pcm037 (i.MX31) platforms"
-        select ARCH_MX31
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_MXC_W1
         select MXC_ULPI if USB_ULPI
         help
           Include support for Phytec pcm037 platform. This includes
@@ -57,9 +76,12 @@ config MACH_PCM037_EET
 
 config MACH_MX31LITE
         bool "Support MX31 LITEKIT (LogicPD)"
-        select ARCH_MX31
+        select SOC_IMX31
         select MXC_ULPI if USB_ULPI
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SPI_IMX
         help
@@ -68,11 +90,16 @@ config MACH_MX31LITE
 
 config MACH_MX31_3DS
         bool "Support MX31PDK (3DS)"
-        select ARCH_MX31
+        select SOC_IMX31
         select MXC_DEBUG_BOARD
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SPI_IMX
+        select MXC_ULPI if USB_ULPI
         help
           Include support for MX31PDK (3DS) platform. This includes specific
           configurations for the board and its peripherals.
@@ -88,9 +115,12 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
 
 config MACH_MX31MOBOARD
         bool "Support mx31moboard platforms (EPFL Mobots group)"
-        select ARCH_MX31
+        select SOC_IMX31
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
@@ -99,8 +129,10 @@ config MACH_MX31MOBOARD
 
 config MACH_MX31LILLY
         bool "Support MX31 LILLY-1131 platforms (INCO startec)"
-        select ARCH_MX31
+        select SOC_IMX31
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
@@ -109,7 +141,7 @@ config MACH_MX31LILLY
 
 config MACH_QONG
         bool "Support Dave/DENX QongEVB-LITE platform"
-        select ARCH_MX31
+        select SOC_IMX31
         select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for Dave/DENX QongEVB-LITE platform. This includes
@@ -117,13 +149,16 @@ config MACH_QONG
 
 config MACH_PCM043
         bool "Support Phytec pcm043 (i.MX35) platforms"
-        select ARCH_MX35
+        select SOC_IMX35
+        select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_FLEXCAN
-        select IMX_HAVE_PLATFORM_ESDHC
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select MXC_ULPI if USB_ULPI
         help
           Include support for Phytec pcm043 platform. This includes
@@ -131,9 +166,11 @@ config MACH_PCM043
 
 config MACH_ARMADILLO5X0
         bool "Support Atmark Armadillo-500 Development Base Board"
-        select ARCH_MX31
+        select SOC_IMX31
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
+        select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
         select MXC_ULPI if USB_ULPI
         help
@@ -142,19 +179,21 @@ config MACH_ARMADILLO5X0
 
 config MACH_MX35_3DS
         bool "Support MX35PDK platform"
-        select ARCH_MX35
+        select SOC_IMX35
         select MXC_DEBUG_BOARD
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_ESDHC
-        default n
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         help
           Include support for MX35PDK platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_KZM_ARM11_01
         bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
-        select ARCH_MX31
+        select SOC_IMX31
         select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for KZM-ARM11-01. This includes specific
@@ -162,12 +201,15 @@ config MACH_KZM_ARM11_01
 
 config MACH_EUKREA_CPUIMX35
         bool "Support Eukrea CPUIMX35 Platform"
-        select ARCH_MX35
-        select IMX_HAVE_PLATFORM_IMX_UART
+        select SOC_IMX35
+        select IMX_HAVE_PLATFORM_FLEXCAN
+        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_FLEXCAN
-        select IMX_HAVE_PLATFORM_ESDHC
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select MXC_ULPI if USB_ULPI
         help
           Include support for Eukrea CPUIMX35 platform. This includes
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 8a182d0a3fcf..8db13294ad27 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -5,17 +5,14 @@
 # Object file lists.
 
 obj-y                           := mm.o devices.o cpu.o
-CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
-CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
-obj-$(CONFIG_ARCH_MX31)         += clock-imx31.o iomux-imx31.o
-obj-$(CONFIG_ARCH_MX35)         += clock-imx35.o
+obj-$(CONFIG_SOC_IMX31)         += clock-imx31.o iomux-imx31.o
+obj-$(CONFIG_SOC_IMX35)         += clock-imx35.o
 obj-$(CONFIG_MACH_MX31ADS)      += mach-mx31ads.o
 obj-$(CONFIG_MACH_MX31LILLY)    += mach-mx31lilly.o mx31lilly-db.o
 obj-$(CONFIG_MACH_MX31LITE)     += mach-mx31lite.o mx31lite-db.o
 obj-$(CONFIG_MACH_PCM037)       += mach-pcm037.o
 obj-$(CONFIG_MACH_PCM037_EET)   += mach-pcm037_eet.o
 obj-$(CONFIG_MACH_MX31_3DS)     += mach-mx31_3ds.o
-CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
 obj-$(CONFIG_MACH_MX31MOBOARD)  += mach-mx31moboard.o mx31moboard-devboard.o \
                                    mx31moboard-marxbot.o mx31moboard-smartbot.o
 obj-$(CONFIG_MACH_QONG)         += mach-qong.o
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
index 109e98f323e0..d423cac8cab7 100644
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -23,8 +23,8 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
 #include <asm/div64.h>
 
 #include <mach/clock.h>
@@ -530,7 +530,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
-        _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
         _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
         _REGISTER_CLOCK(NULL, "epit", epit1_clk)
         _REGISTER_CLOCK(NULL, "epit", epit2_clk)
@@ -615,7 +615,7 @@ int __init mx31_clocks_init(unsigned long fref)
 
         mx31_read_cpu_rev();
 
-        if (mx31_revision() >= MX31_CHIP_REV_2_0) {
+        if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
                 reg = __raw_readl(MXC_CCM_PMCR1);
                 /* No PLL restart on DVFS switch; enable auto EMI handshake */
                 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 61e4a318980a..448a038cd1ec 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -21,8 +21,7 @@
 #include <linux/list.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 #include <mach/clock.h>
 #include <mach/hardware.h>
@@ -495,7 +494,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
-        _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
         _REGISTER_CLOCK(NULL, "max", max_clk)
         _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
         _REGISTER_CLOCK(NULL, "csi", csi_clk)
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
index d00a75457812..d1d339576fdf 100644
--- a/arch/arm/mach-mx3/cpu.c
+++ b/arch/arm/mach-mx3/cpu.c
@@ -25,15 +25,15 @@ struct mx3_cpu_type {
 };
 
 static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
-        { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = MX3x_CHIP_REV_1_0 },
-        { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = MX3x_CHIP_REV_1_1 },
-        { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = MX3x_CHIP_REV_1_1 },
-        { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
-        { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
-        { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = MX3x_CHIP_REV_1_2 },
-        { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = MX3x_CHIP_REV_1_2 },
-        { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = MX3x_CHIP_REV_2_0 },
-        { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = MX3x_CHIP_REV_2_0 },
+        { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = IMX_CHIP_REVISION_1_0  },
+        { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = IMX_CHIP_REVISION_1_1  },
+        { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2  },
+        { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2  },
+        { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0  },
+        { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0  },
 };
 
 void __init mx31_read_cpu_rev(void)
@@ -53,6 +53,8 @@ void __init mx31_read_cpu_rev(void)
                         return;
                 }
 
+        mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+
         printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
 }
 
@@ -62,22 +64,25 @@ EXPORT_SYMBOL(mx35_cpu_rev);
 void __init mx35_read_cpu_rev(void)
 {
         u32 rev;
-        char *srev = "unknown";
+        char *srev;
 
         rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
         switch (rev) {
         case 0x00:
-                mx35_cpu_rev = MX3x_CHIP_REV_1_0;
+                mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
                 srev = "1.0";
                 break;
         case 0x10:
-                mx35_cpu_rev = MX3x_CHIP_REV_2_0;
+                mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
                 srev = "2.0";
                 break;
         case 0x11:
-                mx35_cpu_rev = MX3x_CHIP_REV_2_1;
+                mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
                 srev = "2.1";
                 break;
+        default:
+                mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+                srev = "unknown";
         }
 
         printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
index de9598590eba..40f4e848a671 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -9,6 +9,14 @@
 #include <mach/mx31.h>
 #include <mach/devices-common.h>
 
+extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst;
+#define imx31_add_fsl_usb2_udc(pdata)   \
+        imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
+
+extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst;
+#define imx31_add_imx2_wdt(pdata)       \
+        imx_add_imx2_wdt(&imx31_imx2_wdt_data)
+
 extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
 #define imx31_add_imx_i2c(id, pdata)    \
         imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
@@ -16,6 +24,10 @@ extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
 #define imx31_add_imx_i2c1(pdata)       imx31_add_imx_i2c(1, pdata)
 #define imx31_add_imx_i2c2(pdata)       imx31_add_imx_i2c(2, pdata)
 
+extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst;
+#define imx31_add_imx_keypad(pdata)     \
+        imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
+
 extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
 #define imx31_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
@@ -29,10 +41,25 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
 #define imx31_add_imx_uart3(pdata)      imx31_add_imx_uart(3, pdata)
 #define imx31_add_imx_uart4(pdata)      imx31_add_imx_uart(4, pdata)
 
+extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst;
+#define imx31_add_mxc_ehci_otg(pdata)   \
+        imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
+extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst;
+#define imx31_add_mxc_ehci_hs(id, pdata)        \
+        imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
+
+extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst;
+#define imx31_add_mxc_mmc(id, pdata)    \
+        imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
+
 extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
 #define imx31_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
 
+extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst;
+#define imx31_add_mxc_w1(pdata) \
+        imx_add_mxc_w1(&imx31_mxc_w1_data)
+
 extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
 #define imx31_add_cspi(id, pdata)       \
         imx_add_spi_imx(&imx31_cspi_data[id], pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index 5eb917b638d0..677b18aa7ae6 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -13,10 +13,19 @@ extern const struct imx_fec_data imx35_fec_data __initconst;
 #define imx35_add_fec(pdata)    \
         imx_add_fec(&imx35_fec_data, pdata)
 
-#define imx35_add_flexcan0(pdata)       \
-        imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
-#define imx35_add_flexcan1(pdata)       \
-        imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
+extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst;
+#define imx35_add_fsl_usb2_udc(pdata)   \
+        imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
+
+extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst;
+#define imx35_add_flexcan(id, pdata)    \
+        imx_add_flexcan(&imx35_flexcan_data[id], pdata)
+#define imx35_add_flexcan0(pdata)       imx35_add_flexcan(0, pdata)
+#define imx35_add_flexcan1(pdata)       imx35_add_flexcan(1, pdata)
+
+extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst;
+#define imx35_add_imx2_wdt(pdata)       \
+        imx_add_imx2_wdt(&imx35_imx2_wdt_data)
 
 extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
 #define imx35_add_imx_i2c(id, pdata)    \
@@ -25,6 +34,10 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
 #define imx35_add_imx_i2c1(pdata)       imx35_add_imx_i2c(1, pdata)
 #define imx35_add_imx_i2c2(pdata)       imx35_add_imx_i2c(2, pdata)
 
+extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
+#define imx31_add_imx_keypad(pdata)     \
+        imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
+
 extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
 #define imx35_add_imx_ssi(id, pdata)    \
         imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
@@ -36,16 +49,28 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
 #define imx35_add_imx_uart1(pdata)      imx35_add_imx_uart(1, pdata)
 #define imx35_add_imx_uart2(pdata)      imx35_add_imx_uart(2, pdata)
 
+extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst;
+#define imx35_add_mxc_ehci_otg(pdata)   \
+        imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
+extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst;
+#define imx35_add_mxc_ehci_hs(pdata)    \
+        imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
+
 extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
 #define imx35_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
 
+extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst;
+#define imx35_add_mxc_w1(pdata) \
+        imx_add_mxc_w1(&imx35_mxc_w1_data)
+
+extern const struct imx_sdhci_esdhc_imx_data
+imx35_sdhci_esdhc_imx_data[] __initconst;
+#define imx35_add_sdhci_esdhc_imx(id, pdata)    \
+        imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
+
 extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
 #define imx35_add_cspi(id, pdata)       \
         imx_add_spi_imx(&imx35_cspi_data[id], pdata)
 #define imx35_add_spi_imx0(pdata)       imx35_add_cspi(0, pdata)
 #define imx35_add_spi_imx1(pdata)       imx35_add_cspi(1, pdata)
-
-extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst;
-#define imx35_add_esdhc(id, pdata)      \
-        imx_add_esdhc(&imx35_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index d4da9496089a..b6672db788fb 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -29,120 +29,25 @@
 
 #include "devices.h"
 
-/* GPIO port description */
-static struct mxc_gpio_port imx_gpio_ports[] = {
-        {
-                .chip.label = "gpio-0",
-                .base = IO_ADDRESS(GPIO1_BASE_ADDR),
-                .irq = MXC_INT_GPIO1,
-                .virtual_irq_start = MXC_GPIO_IRQ_START,
-        }, {
-                .chip.label = "gpio-1",
-                .base = IO_ADDRESS(GPIO2_BASE_ADDR),
-                .irq = MXC_INT_GPIO2,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        }, {
-                .chip.label = "gpio-2",
-                .base = IO_ADDRESS(GPIO3_BASE_ADDR),
-                .irq = MXC_INT_GPIO3,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-        }
-};
-
-int __init imx3x_register_gpios(void)
-{
-        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
-}
-
-static struct resource mxc_w1_master_resources[] = {
-        {
-                .start = OWIRE_BASE_ADDR,
-                .end   = OWIRE_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device mxc_w1_master_device = {
-        .name = "mxc_w1",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
-        .resource = mxc_w1_master_resources,
-};
-
-#ifdef CONFIG_ARCH_MX31
-static struct resource mxcsdhc0_resources[] = {
-        {
-                .start = MX31_MMC_SDHC1_BASE_ADDR,
-                .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX31_INT_MMC_SDHC1,
-                .end = MX31_INT_MMC_SDHC1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource mxcsdhc1_resources[] = {
-        {
-                .start = MX31_MMC_SDHC2_BASE_ADDR,
-                .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX31_INT_MMC_SDHC2,
-                .end = MX31_INT_MMC_SDHC2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxcsdhc_device0 = {
-        .name = "mxc-mmc",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
-        .resource = mxcsdhc0_resources,
-};
-
-struct platform_device mxcsdhc_device1 = {
-        .name = "mxc-mmc",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
-        .resource = mxcsdhc1_resources,
-};
-
-static struct resource rnga_resources[] = {
-        {
-                .start = RNGA_BASE_ADDR,
-                .end = RNGA_BASE_ADDR + 0x28,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device mxc_rnga_device = {
-        .name = "mxc_rnga",
-        .id = -1,
-        .num_resources = 1,
-        .resource = rnga_resources,
-};
-#endif /* CONFIG_ARCH_MX31 */
-
 /* i.MX31 Image Processing Unit */
 
 /* The resource order is important! */
 static struct resource mx3_ipu_rsrc[] = {
         {
-                .start = IPU_CTRL_BASE_ADDR,
-                .end = IPU_CTRL_BASE_ADDR + 0x5F,
+                .start = MX3x_IPU_CTRL_BASE_ADDR,
+                .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
                 .flags = IORESOURCE_MEM,
         }, {
-                .start = IPU_CTRL_BASE_ADDR + 0x88,
-                .end = IPU_CTRL_BASE_ADDR + 0xB3,
+                .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
+                .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
                 .flags = IORESOURCE_MEM,
         }, {
-                .start = MXC_INT_IPU_SYN,
-                .end = MXC_INT_IPU_SYN,
+                .start = MX3x_INT_IPU_SYN,
+                .end = MX3x_INT_IPU_SYN,
                 .flags = IORESOURCE_IRQ,
         }, {
-                .start = MXC_INT_IPU_ERR,
-                .end = MXC_INT_IPU_ERR,
+                .start = MX3x_INT_IPU_ERR,
+                .end = MX3x_INT_IPU_ERR,
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -156,8 +61,8 @@ struct platform_device mx3_ipu = {
 
 static struct resource fb_resources[] = {
         {
-                .start  = IPU_CTRL_BASE_ADDR + 0xB4,
-                .end    = IPU_CTRL_BASE_ADDR + 0x1BF,
+                .start  = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
+                .end    = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
                 .flags  = IORESOURCE_MEM,
         },
 };
@@ -174,8 +79,8 @@ struct platform_device mx3_fb = {
 
 static struct resource camera_resources[] = {
         {
-                .start  = IPU_CTRL_BASE_ADDR + 0x60,
-                .end    = IPU_CTRL_BASE_ADDR + 0x87,
+                .start  = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
+                .end    = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
                 .flags  = IORESOURCE_MEM,
         },
 };
@@ -190,110 +95,6 @@ struct platform_device mx3_camera = {
         },
 };
 
-static struct resource otg_resources[] = {
-        {
-                .start  = MX31_OTG_BASE_ADDR,
-                .end    = MX31_OTG_BASE_ADDR + 0x1ff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MXC_INT_USB3,
-                .end    = MXC_INT_USB3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 otg_dmamask = DMA_BIT_MASK(32);
-
-/* OTG gadget device */
-struct platform_device mxc_otg_udc_device = {
-        .name           = "fsl-usb2-udc",
-        .id             = -1,
-        .dev            = {
-                .dma_mask               = &otg_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = otg_resources,
-        .num_resources  = ARRAY_SIZE(otg_resources),
-};
-
-/* OTG host */
-struct platform_device mxc_otg_host = {
-        .name = "mxc-ehci",
-        .id = 0,
-        .dev = {
-                .coherent_dma_mask = 0xffffffff,
-                .dma_mask = &otg_dmamask,
-        },
-        .resource = otg_resources,
-        .num_resources = ARRAY_SIZE(otg_resources),
-};
-
-/* USB host 1 */
-
-static u64 usbh1_dmamask = ~(u32)0;
-
-static struct resource mxc_usbh1_resources[] = {
-        {
-                .start = MX31_OTG_BASE_ADDR + 0x200,
-                .end = MX31_OTG_BASE_ADDR + 0x3ff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_USB1,
-                .end = MXC_INT_USB1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_usbh1 = {
-        .name = "mxc-ehci",
-        .id = 1,
-        .dev = {
-                .coherent_dma_mask = 0xffffffff,
-                .dma_mask = &usbh1_dmamask,
-        },
-        .resource = mxc_usbh1_resources,
-        .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
-};
-
-/* USB host 2 */
-static u64 usbh2_dmamask = ~(u32)0;
-
-static struct resource mxc_usbh2_resources[] = {
-        {
-                .start = MX31_OTG_BASE_ADDR + 0x400,
-                .end = MX31_OTG_BASE_ADDR + 0x5ff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_USB2,
-                .end = MXC_INT_USB2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_usbh2 = {
-        .name = "mxc-ehci",
-        .id = 2,
-        .dev = {
-                .coherent_dma_mask = 0xffffffff,
-                .dma_mask = &usbh2_dmamask,
-        },
-        .resource = mxc_usbh2_resources,
-        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
-};
-
-static struct resource imx_wdt_resources[] = {
-        {
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device imx_wdt_device0 = {
-        .name           = "imx2-wdt",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(imx_wdt_resources),
-        .resource       = imx_wdt_resources,
-};
-
 static struct resource imx_rtc_resources[] = {
         {
                 .start  = MX31_RTC_BASE_ADDR,
@@ -312,51 +113,3 @@ struct platform_device imx_rtc_device0 = {
         .num_resources  = ARRAY_SIZE(imx_rtc_resources),
         .resource       = imx_rtc_resources,
 };
-
-static struct resource imx_kpp_resources[] = {
-        {
-                .start  = MX3x_KPP_BASE_ADDR,
-                .end    = MX3x_KPP_BASE_ADDR + 0xf,
-                .flags  = IORESOURCE_MEM
-        }, {
-                .start  = MX3x_INT_KPP,
-                .end    = MX3x_INT_KPP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_kpp_device = {
-        .name = "imx-keypad",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(imx_kpp_resources),
-        .resource = imx_kpp_resources,
-};
-
-static int __init mx3_devices_init(void)
-{
-#if defined(CONFIG_ARCH_MX31)
-        if (cpu_is_mx31()) {
-                imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
-                imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
-                mxc_register_device(&mxc_rnga_device, NULL);
-        }
-#endif
-#if defined(CONFIG_ARCH_MX35)
-        if (cpu_is_mx35()) {
-                otg_resources[0].start = MX35_OTG_BASE_ADDR;
-                otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
-                otg_resources[1].start = MXC_INT_USBOTG;
-                otg_resources[1].end = MXC_INT_USBOTG;
-                mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
-                mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
-                mxc_usbh1_resources[1].start = MXC_INT_USBHS;
-                mxc_usbh1_resources[1].end = MXC_INT_USBHS;
-                imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
-                imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
-        }
-#endif
-
-        return 0;
-}
-
-subsys_initcall(mx3_devices_init);
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 585f814473d5..121962c568d1 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -1,14 +1,4 @@
-extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
 extern struct platform_device mx3_camera;
-extern struct platform_device mxcsdhc_device0;
-extern struct platform_device mxcsdhc_device1;
-extern struct platform_device mxc_otg_udc_device;
-extern struct platform_device mxc_otg_host;
-extern struct platform_device mxc_usbh1;
-extern struct platform_device mxc_usbh2;
-extern struct platform_device mxc_rnga_device;
-extern struct platform_device imx_wdt_device0;
 extern struct platform_device imx_rtc_device0;
-extern struct platform_device imx_kpp_device;
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index 1abc10d52922..14a5ffc939ad 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -111,7 +111,7 @@ static struct mx3fb_platform_data mx3fb_pdata = {
         .num_modes      = ARRAY_SIZE(fb_modedb),
 };
 
-static struct pad_desc eukrea_mbimxsd_pads[] = {
+static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
         /* LCD */
         MX35_PAD_LD0__IPU_DISPB_DAT_0,
         MX35_PAD_LD1__IPU_DISPB_DAT_1,
@@ -289,7 +289,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
         imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
 
         imx35_add_flexcan1(NULL);
-        imx35_add_esdhc(0, NULL);
+        imx35_add_sdhci_esdhc_imx(0, NULL);
 
         gpio_request(GPIO_LED1, "LED1");
         gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index aaa30fe18f85..28b6f414b5d5 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -49,10 +49,8 @@
 
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
-#include <mach/mmc.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
@@ -245,13 +243,13 @@ h2_free_cs:
         return err;
 }
 
-static struct mxc_usbh_platform_data usbotg_pdata = {
+static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
         .init   = usbotg_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
-static struct mxc_usbh_platform_data usbh2_pdata = {
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .init   = usbh2_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -453,7 +451,7 @@ static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
         gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
 }
 
-static struct imxmmc_platform_data sdhc_pdata = {
+static const struct imxmmc_platform_data sdhc_pdata __initconst = {
         .get_ro = armadillo5x0_sdhc1_get_ro,
         .init = armadillo5x0_sdhc1_init,
         .exit = armadillo5x0_sdhc1_exit,
@@ -520,7 +518,7 @@ static void __init armadillo5x0_init(void)
         gpio_direction_input(MX31_PIN_GPIO1_0);
 
         /* Register SDHC */
-        mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
+        imx31_add_mxc_mmc(0, &sdhc_pdata);
 
         /* Register FB */
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
@@ -555,8 +553,8 @@ static void __init armadillo5x0_init(void)
         usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                         ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-        mxc_register_device(&mxc_otg_host, &usbotg_pdata);
-        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+        imx31_add_mxc_ehci_otg(&usbotg_pdata);
+        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 #endif
 }
 
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 9fde873f5889..26ae90f02582 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -30,7 +30,6 @@
 #include <linux/i2c/tsc2007.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <linux/fsl_devices.h>
 #include <linux/i2c-gpio.h>
 
 #include <asm/mach-types.h>
@@ -43,7 +42,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
 #include <mach/mxc_nand.h>
-#include <mach/mxc_ehci.h>
 
 #include "devices-imx35.h"
 #include "devices.h"
@@ -74,11 +72,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
         },
 };
 
-static struct platform_device *devices[] __initdata = {
-        &imx_wdt_device0,
-};
-
-static struct pad_desc eukrea_cpuimx35_pads[] = {
+static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
         /* UART1 */
         MX35_PAD_CTS1__UART1_CTS,
         MX35_PAD_RTS1__UART1_RTS,
@@ -117,18 +111,18 @@ static const struct mxc_nand_platform_data
         .flash_bbt      = 1,
 };
 
-static struct mxc_usbh_platform_data __maybe_unused otg_pdata = {
+static const struct mxc_usbh_platform_data otg_pdata __initconst = {
         .portsc = MXC_EHCI_MODE_UTMI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
-static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = {
+static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
         .portsc = MXC_EHCI_MODE_SERIAL,
         .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
                   MXC_EHCI_IPPUE_DOWN,
 };
 
-static struct fsl_usb2_platform_data otg_device_pdata = {
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI,
         .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
@@ -158,7 +152,7 @@ static void __init mxc_board_init(void)
                         ARRAY_SIZE(eukrea_cpuimx35_pads));
 
         imx35_add_fec(NULL);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        imx35_add_imx2_wdt(NULL);
 
         imx35_add_imx_uart0(&uart_pdata);
         imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
@@ -168,11 +162,11 @@ static void __init mxc_board_init(void)
         imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
 
         if (otg_mode_host)
-                mxc_register_device(&mxc_otg_host, &otg_pdata);
+                imx35_add_mxc_ehci_otg(&otg_pdata);
         else
-                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+                imx35_add_fsl_usb2_udc(&otg_device_pdata);
 
-        mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+        imx35_add_mxc_ehci_hs(&usbh1_pdata);
 
 #ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
         eukrea_mbimxsd35_baseboard_init();
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index 042cd5655e17..a5f3eb24e4d5 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -41,9 +41,9 @@
 #include "devices-imx31.h"
 #include "devices.h"
 
-#define KZM_ARM11_IO_ADDRESS(x) (                                       \
-        IMX_IO_ADDRESS(x, MX31_CS4) ?:                                  \
-        IMX_IO_ADDRESS(x, MX31_CS5) ?:                                  \
+#define KZM_ARM11_IO_ADDRESS(x) (IOMEM(                                 \
+        IMX_IO_P2V_MODULE(x, MX31_CS4) ?:                               \
+        IMX_IO_P2V_MODULE(x, MX31_CS5)) ?:                              \
         MX31_IO_ADDRESS(x))
 
 /*
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 0ad9e7821082..4e516b49a901 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -22,8 +22,8 @@
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
 #include <linux/regulator/machine.h>
-#include <linux/fsl_devices.h>
-#include <linux/input/matrix_keypad.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -34,6 +34,7 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/3ds_debugboard.h>
+#include <mach/ulpi.h>
 
 #include "devices-imx31.h"
 #include "devices.h"
@@ -84,6 +85,21 @@ static int mx31_3ds_pins[] = {
         MX31_PIN_KEY_COL1_KEY_COL1,
         MX31_PIN_KEY_COL2_KEY_COL2,
         MX31_PIN_KEY_COL3_KEY_COL3,
+        /* USB Host 2 */
+        IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
+        IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
+        IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
+        IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
+        IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
+        IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
+        IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
+        /* USB Host2 reset */
+        IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
 };
 
 /*
@@ -102,7 +118,7 @@ static const uint32_t mx31_3ds_keymap[] = {
         KEY(2, 3, KEY_F10),
 };
 
-static struct matrix_keymap_data mx31_3ds_keymap_data = {
+static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
         .keymap         = mx31_3ds_keymap,
         .keymap_size    = ARRAY_SIZE(mx31_3ds_keymap),
 };
@@ -115,6 +131,13 @@ static struct regulator_init_data pwgtx_init = {
         },
 };
 
+static struct regulator_init_data gpo_init = {
+        .constraints = {
+                .boot_on = 1,
+                .always_on = 1,
+        }
+};
+
 static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
         {
                 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
@@ -122,6 +145,13 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
         }, {
                 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
                 .init_data = &pwgtx_init,
+        }, {
+
+                .id = MC13783_REGU_GPO1, /* Turn on 1.8V */
+                .init_data = &gpo_init,
+        }, {
+                .id = MC13783_REGU_GPO3, /* Turn on 3.3V */
+                .init_data = &gpo_init,
         },
 };
 
@@ -129,7 +159,7 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
 static struct mc13783_platform_data mc13783_pdata __initdata = {
         .regulators = mx31_3ds_regulators,
         .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
-        .flags  = MC13783_USE_REGULATOR,
+        .flags  = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
 };
 
 /* SPI */
@@ -175,6 +205,7 @@ mx31_3ds_nand_board_info __initconst = {
                      PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 
 #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
+#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
 
 static int mx31_3ds_usbotg_init(void)
 {
@@ -214,11 +245,77 @@ usbotg_free_reset:
         return err;
 }
 
-static struct fsl_usb2_platform_data usbotg_pdata = {
+static int mx31_3ds_host2_init(struct platform_device *pdev)
+{
+        int err;
+
+        mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
+
+        err = gpio_request(USBH2_RST_B, "usbh2-reset");
+        if (err) {
+                pr_err("Failed to request the USB Host 2 reset gpio\n");
+                return err;
+        }
+
+        err = gpio_direction_output(USBH2_RST_B, 0);
+        if (err) {
+                pr_err("Failed to drive the USB Host 2 reset gpio\n");
+                goto usbotg_free_reset;
+        }
+
+        mdelay(1);
+        gpio_set_value(USBH2_RST_B, 1);
+        return 0;
+
+usbotg_free_reset:
+        gpio_free(USBH2_RST_B);
+        return err;
+}
+
+#if defined(CONFIG_USB_ULPI)
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+        .init = mx31_3ds_host2_init,
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+#endif
+
+static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
+static int otg_mode_host;
+
+static int __init mx31_3ds_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", mx31_3ds_otg_mode);
+
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -246,14 +343,27 @@ static void __init mxc_board_init(void)
         spi_register_board_info(mx31_3ds_spi_devs,
                                                 ARRAY_SIZE(mx31_3ds_spi_devs));
 
-        mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
+        imx31_add_imx_keypad(&mx31_3ds_keymap_data);
 
         mx31_3ds_usbotg_init();
-        mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
+#if defined(CONFIG_USB_ULPI)
+        if (otg_mode_host) {
+                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+
+                imx31_add_mxc_ehci_otg(&otg_pdata);
+        }
+        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+#endif
+        if (!otg_mode_host)
+                imx31_add_fsl_usb2_udc(&usbotg_pdata);
 
         if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 printk(KERN_WARNING "Init of the debug board failed, all "
                                     "devices on the debug board are unusable.\n");
+        imx31_add_imx2_wdt(NULL);
 }
 
 static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 42f47faa6fd6..2c595483f356 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -42,7 +42,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
@@ -230,13 +229,13 @@ static struct mxc_usbh_platform_data usbotg_pdata = {
         .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 
-static struct mxc_usbh_platform_data usbh1_pdata = {
+static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
         .init   = usbh1_init,
         .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
 };
 
-static struct mxc_usbh_platform_data usbh2_pdata = {
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .init   = usbh2_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED,
@@ -249,8 +248,8 @@ static void lilly1131_usb_init(void)
         usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-        mxc_register_device(&mxc_usbh1, &usbh1_pdata);
-        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+        imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
+        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 }
 
 #else
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index b93895814cdf..9e64c66396e0 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -40,7 +40,6 @@
 #include <mach/board-mx31lite.h>
 #include <mach/iomux-mx3.h>
 #include <mach/irqs.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
@@ -171,7 +170,7 @@ static int usbh2_init(struct platform_device *pdev)
         return 0;
 }
 
-static struct mxc_usbh_platform_data usbh2_pdata = {
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .init   = usbh2_init,
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED,
@@ -258,7 +257,7 @@ static void __init mxc_board_init(void)
         usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 #endif
 
         /* SMSC9117 IRQ pin */
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index eb5f426df224..203d21a510aa 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -40,8 +40,6 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
-#include <mach/mmc.h>
-#include <mach/mxc_ehci.h>
 #include <mach/mx3_camera.h>
 #include <mach/spi.h>
 #include <mach/ulpi.h>
@@ -170,11 +168,11 @@ static const struct spi_imx_master moboard_spi1_pdata __initconst = {
 
 static struct regulator_consumer_supply sdhc_consumers[] = {
         {
-                .dev    = &mxcsdhc_device0.dev,
+                .dev_name = "mxc-mmc.0",
                 .supply = "sdhc0_vcc",
         },
         {
-                .dev    = &mxcsdhc_device1.dev,
+                .dev_name = "mxc-mmc.1",
                 .supply = "sdhc1_vcc",
         },
 };
@@ -345,7 +343,7 @@ static void moboard_sdhc1_exit(struct device *dev, void *data)
         gpio_free(SDHC1_CD);
 }
 
-static struct imxmmc_platform_data sdhc1_pdata = {
+static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
         .get_ro = moboard_sdhc1_get_ro,
         .init   = moboard_sdhc1_init,
         .exit   = moboard_sdhc1_exit,
@@ -404,17 +402,23 @@ static void usb_xcvr_reset(void)
 
 #if defined(CONFIG_USB_ULPI)
 
-static struct mxc_usbh_platform_data usbh2_pdata = {
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 
 static int __init moboard_usbh2_init(void)
 {
+        struct platform_device *pdev;
+
         usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                         ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-        return mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+        pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+
+        return 0;
 }
 #else
 static inline int moboard_usbh2_init(void) { return 0; }
@@ -520,7 +524,7 @@ static void __init mxc_board_init(void)
         spi_register_board_info(moboard_spi_board_info,
                 ARRAY_SIZE(moboard_spi_board_info));
 
-        mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
+        imx31_add_mxc_mmc(0, &sdhc1_pdata);
 
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
         if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index b66a75aa2e88..b1963f257c20 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -26,7 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/memory.h>
 #include <linux/gpio.h>
-#include <linux/fsl_devices.h>
+#include <linux/usb/otg.h>
 
 #include <linux/mtd/physmap.h>
 
@@ -40,7 +40,6 @@
 #include <mach/iomux-mx35.h>
 #include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
-#include <mach/mxc_ehci.h>
 
 #include "devices-imx35.h"
 #include "devices.h"
@@ -81,7 +80,7 @@ static struct platform_device *devices[] __initdata = {
         &mx35pdk_flash,
 };
 
-static struct pad_desc mx35pdk_pads[] = {
+static iomux_v3_cfg_t mx35pdk_pads[] = {
         /* UART1 */
         MX35_PAD_CTS1__UART1_CTS,
         MX35_PAD_RTS1__UART1_RTS,
@@ -122,18 +121,38 @@ static struct pad_desc mx35pdk_pads[] = {
 };
 
 /* OTG config */
-static struct fsl_usb2_platform_data usb_otg_pdata = {
+static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 };
 
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
+        .portsc = MXC_EHCI_MODE_UTMI,
+        .flags  = MXC_EHCI_INTERNAL_PHY,
+};
+
 /* USB HOST config */
-static struct mxc_usbh_platform_data usb_host_pdata = {
+static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
         .portsc         = MXC_EHCI_MODE_SERIAL,
         .flags          = MXC_EHCI_INTERFACE_SINGLE_UNI |
                           MXC_EHCI_INTERNAL_PHY,
 };
 
+static int otg_mode_host;
+
+static int __init mx35_3ds_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", mx35_3ds_otg_mode);
+
 /*
  * Board specific initialization.
  */
@@ -142,16 +161,21 @@ static void __init mxc_board_init(void)
         mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
 
         imx35_add_fec(NULL);
+        imx35_add_imx2_wdt(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx35_add_imx_uart0(&uart_pdata);
 
-        mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata);
+        if (otg_mode_host)
+                imx35_add_mxc_ehci_otg(&otg_pdata);
+
+        imx35_add_mxc_ehci_hs(&usb_host_pdata);
 
-        mxc_register_device(&mxc_usbh1, &usb_host_pdata);
+        if (!otg_mode_host)
+                imx35_add_fsl_usb2_udc(&usb_otg_pdata);
 
         imx35_add_mxc_nand(&mx35pdk_nand_board_info);
-        imx35_add_esdhc(0, NULL);
+        imx35_add_sdhci_esdhc_imx(0, NULL);
 
         if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 pr_warn("Init of the debugboard failed, all "
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 2ff3f661a48e..b752f6bc20a2 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -27,7 +27,6 @@
 #include <linux/delay.h>
 #include <linux/spi/spi.h>
 #include <linux/irq.h>
-#include <linux/fsl_devices.h>
 #include <linux/can/platform/sja1000.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
@@ -43,10 +42,8 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
-#include <mach/mmc.h>
 #include <mach/mx3_camera.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
@@ -399,7 +396,7 @@ static void pcm970_sdhc1_exit(struct device *dev, void *data)
         gpio_free(SDHC1_GPIO_WP);
 }
 
-static struct imxmmc_platform_data sdhc_pdata = {
+static const struct imxmmc_platform_data sdhc_pdata __initconst = {
 #ifdef PCM970_SDHC_RW_SWITCH
         .get_ro = pcm970_sdhc1_get_ro,
 #endif
@@ -441,7 +438,6 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size)
 static struct platform_device *devices[] __initdata = {
         &pcm037_flash,
         &pcm037_sram_device,
-        &imx_wdt_device0,
         &pcm037_mt9t031,
         &pcm037_mt9v022,
 };
@@ -538,18 +534,18 @@ static struct platform_device pcm970_sja1000 = {
 };
 
 #if defined(CONFIG_USB_ULPI)
-static struct mxc_usbh_platform_data otg_pdata = {
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
-static struct mxc_usbh_platform_data usbh2_pdata = {
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 #endif
 
-static struct fsl_usb2_platform_data otg_device_pdata = {
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
@@ -607,12 +603,13 @@ static void __init mxc_board_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
+        imx31_add_imx2_wdt(NULL);
         imx31_add_imx_uart0(&uart_pdata);
         /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
         imx31_add_imx_uart1(&uart_pdata);
         imx31_add_imx_uart2(&uart_pdata);
 
-        mxc_register_device(&mxc_w1_master_device, NULL);
+        imx31_add_mxc_w1(NULL);
 
         /* LAN9217 IRQ pin */
         ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
@@ -632,7 +629,7 @@ static void __init mxc_board_init(void)
         imx31_add_imx_i2c2(&pcm037_i2c2_data);
 
         imx31_add_mxc_nand(&pcm037_nand_board_info);
-        mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
+        imx31_add_mxc_mmc(0, &sdhc_pdata);
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
         mxc_register_device(&mx3_fb, &mx3fb_pdata);
 
@@ -654,16 +651,16 @@ static void __init mxc_board_init(void)
                 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-                mxc_register_device(&mxc_otg_host, &otg_pdata);
+                imx31_add_mxc_ehci_otg(&otg_pdata);
         }
 
         usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+        imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
 #endif
         if (!otg_mode_host)
-                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+                imx31_add_fsl_usb2_udc(&otg_device_pdata);
 
 }
 
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 4e1de87995d4..bcf83fc7e701 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -27,7 +27,6 @@
 #include <linux/i2c/at24.h>
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
-#include <linux/fsl_devices.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,7 +38,6 @@
 #include <mach/iomux-mx35.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 #include <mach/audmux.h>
 
@@ -140,10 +138,9 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
 
 static struct platform_device *devices[] __initdata = {
         &pcm043_flash,
-        &imx_wdt_device0,
 };
 
-static struct pad_desc pcm043_pads[] = {
+static iomux_v3_cfg_t pcm043_pads[] = {
         /* UART1 */
         MX35_PAD_CTS1__UART1_CTS,
         MX35_PAD_RTS1__UART1_RTS,
@@ -230,8 +227,8 @@ static struct pad_desc pcm043_pads[] = {
 
 static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
 {
-        struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
-        struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
+        iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
+        iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
         int ret;
 
         ret = gpio_request(AC97_GPIO_TXFS, "SSI");
@@ -240,7 +237,7 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
                 return;
         }
 
-        mxc_iomux_v3_setup_pad(&txfs_gpio);
+        mxc_iomux_v3_setup_pad(txfs_gpio);
 
         /* warm reset */
         gpio_direction_output(AC97_GPIO_TXFS, 1);
@@ -248,16 +245,16 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
         gpio_set_value(AC97_GPIO_TXFS, 0);
 
         gpio_free(AC97_GPIO_TXFS);
-        mxc_iomux_v3_setup_pad(&txfs);
+        mxc_iomux_v3_setup_pad(txfs);
 }
 
 static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
 {
-        struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
-        struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
-        struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
-        struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
-        struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
+        iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
+        iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
+        iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
+        iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
+        iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
         int ret;
 
         ret = gpio_request(AC97_GPIO_TXFS, "SSI");
@@ -272,9 +269,9 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
         if (ret)
                 goto err3;
 
-        mxc_iomux_v3_setup_pad(&txfs_gpio);
-        mxc_iomux_v3_setup_pad(&txd_gpio);
-        mxc_iomux_v3_setup_pad(&reset_gpio);
+        mxc_iomux_v3_setup_pad(txfs_gpio);
+        mxc_iomux_v3_setup_pad(txd_gpio);
+        mxc_iomux_v3_setup_pad(reset_gpio);
 
         gpio_direction_output(AC97_GPIO_TXFS, 0);
         gpio_direction_output(AC97_GPIO_TXD, 0);
@@ -284,8 +281,8 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
         udelay(10);
         gpio_direction_output(AC97_GPIO_RESET, 1);
 
-        mxc_iomux_v3_setup_pad(&txd);
-        mxc_iomux_v3_setup_pad(&txfs);
+        mxc_iomux_v3_setup_pad(txd);
+        mxc_iomux_v3_setup_pad(txfs);
 
         gpio_free(AC97_GPIO_RESET);
 err3:
@@ -311,19 +308,19 @@ pcm037_nand_board_info __initconst = {
 };
 
 #if defined(CONFIG_USB_ULPI)
-static struct mxc_usbh_platform_data otg_pdata = {
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
         .portsc = MXC_EHCI_MODE_UTMI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
 
-static struct mxc_usbh_platform_data usbh1_pdata = {
+static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
         .portsc = MXC_EHCI_MODE_SERIAL,
         .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
                   MXC_EHCI_IPPUE_DOWN,
 };
 #endif
 
-static struct fsl_usb2_platform_data otg_device_pdata = {
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_UTMI,
 };
@@ -364,6 +361,7 @@ static void __init mxc_board_init(void)
 
         imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
+        imx35_add_imx2_wdt(NULL);
 
         imx35_add_imx_uart0(&uart_pdata);
         imx35_add_mxc_nand(&pcm037_nand_board_info);
@@ -386,16 +384,16 @@ static void __init mxc_board_init(void)
                 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                                 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-                mxc_register_device(&mxc_otg_host, &otg_pdata);
+                imx35_add_mxc_ehci_otg(&otg_pdata);
         }
 
-        mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+        imx35_add_mxc_ehci_hs(&usbh1_pdata);
 #endif
         if (!otg_mode_host)
-                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+                imx35_add_fsl_usb2_udc(&otg_device_pdata);
 
         imx35_add_flexcan1(NULL);
-        imx35_add_esdhc(0, NULL);
+        imx35_add_sdhci_esdhc_imx(0, NULL);
 }
 
 static void __init pcm043_timer_init(void)
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index b4ffc531a82c..47118f760244 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -36,40 +36,16 @@
  * @ingroup Memory
  */
 
-/*!
- * This table defines static virtual address mappings for I/O regions.
- * These are the mappings common across all MX3 boards.
- */
-static struct map_desc mxc_io_desc[] __initdata = {
-        {
-                .virtual        = X_MEMC_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(X_MEMC_BASE_ADDR),
-                .length         = X_MEMC_SIZE,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = AVIC_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AVIC_BASE_ADDR),
-                .length         = AVIC_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
-                .virtual        = AIPS1_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AIPS1_BASE_ADDR),
-                .length         = AIPS1_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
-                .virtual        = AIPS2_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(AIPS2_BASE_ADDR),
-                .length         = AIPS2_SIZE,
-                .type           = MT_DEVICE_NONSHARED
-        }, {
-                .virtual = SPBA0_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
-                .length = SPBA0_SIZE,
-                .type = MT_DEVICE_NONSHARED
-        },
+#ifdef CONFIG_SOC_IMX31
+static struct map_desc mx31_io_desc[] __initdata = {
+        imx_map_entry(MX31, X_MEMC, MT_DEVICE),
+        imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
 };
 
-/*!
+/*
  * This function initializes the memory map. It is called during the
  * system startup to create static physical to virtual memory mappings
  * for the IO modules.
@@ -77,34 +53,44 @@ static struct map_desc mxc_io_desc[] __initdata = {
 void __init mx31_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX31);
-        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
+        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
 
-        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
 }
 
-#ifdef CONFIG_ARCH_MX35
-void __init mx35_map_io(void)
+int imx31_register_gpios(void);
+void __init mx31_init_irq(void)
 {
-        mxc_set_cpu_type(MXC_CPU_MX35);
-        mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
-
-        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
+        imx31_register_gpios();
 }
-#endif
-
-int imx3x_register_gpios(void);
+#endif /* ifdef CONFIG_SOC_IMX31 */
+
+#ifdef CONFIG_SOC_IMX35
+static struct map_desc mx35_io_desc[] __initdata = {
+        imx_map_entry(MX35, X_MEMC, MT_DEVICE),
+        imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
+        imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
+};
 
-void __init mx31_init_irq(void)
+void __init mx35_map_io(void)
 {
-        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
-        imx3x_register_gpios();
+        mxc_set_cpu_type(MXC_CPU_MX35);
+        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
+
+        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
 }
 
+int imx35_register_gpios(void);
 void __init mx35_init_irq(void)
 {
-        mx31_init_irq();
+        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
+        imx35_register_gpios();
 }
+#endif /* ifdef CONFIG_SOC_IMX35 */
 
 #ifdef CONFIG_CACHE_L2X0
 static int mxc_init_l2x0(void)
@@ -129,7 +115,7 @@ static int mxc_init_l2x0(void)
                 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
         }
 
-        l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
+        l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
         if (IS_ERR(l2x0_base)) {
                 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
                                 PTR_ERR(l2x0_base));
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 827fd3c80201..8f1a38ebf5c8 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -34,7 +34,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
-#include <mach/mmc.h>
 #include <mach/mx3fb.h>
 #include <mach/ipu.h>
 
@@ -158,7 +157,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
         free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
 }
 
-static struct imxmmc_platform_data mmc_pdata = {
+static const struct imxmmc_platform_data mmc_pdata __initconst = {
         .get_ro = mxc_mmc1_get_ro,
         .init   = mxc_mmc1_init,
         .exit   = mxc_mmc1_exit,
@@ -216,7 +215,7 @@ void __init mx31lilly_db_init(void)
         imx31_add_imx_uart0(&uart_pdata);
         imx31_add_imx_uart1(&uart_pdata);
         imx31_add_imx_uart2(&uart_pdata);
-        mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
+        imx31_add_mxc_mmc(0, &mmc_pdata);
         mx31lilly_init_fb();
 }
 
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 7b0e74e275ba..3124ea837ac7 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -35,7 +35,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lite.h>
-#include <mach/mmc.h>
 
 #include "devices-imx31.h"
 #include "devices.h"
@@ -142,7 +141,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
         free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
 }
 
-static struct imxmmc_platform_data mmc_pdata = {
+static const struct imxmmc_platform_data mmc_pdata __initconst = {
         .get_ro  = mxc_mmc1_get_ro,
         .init      = mxc_mmc1_init,
         .exit      = mxc_mmc1_exit,
@@ -197,10 +196,9 @@ void __init mx31lite_db_init(void)
                                         ARRAY_SIZE(litekit_db_board_pins),
                                         "development board pins");
         imx31_add_imx_uart0(&uart_pdata);
-        mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
+        imx31_add_mxc_mmc(0, &mmc_pdata);
         imx31_add_spi_imx0(&spi0_pdata);
         platform_device_register(&litekit_led_device);
-        mxc_register_device(&imx_wdt_device0, NULL);
+        imx31_add_imx2_wdt(NULL);
         mxc_register_device(&imx_rtc_device0, NULL);
 }
-
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index fc395a7a8599..94a0b9e4b7f3 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -18,15 +18,12 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 #include <linux/types.h>
-#include <linux/fsl_devices.h>
 
 #include <linux/usb/otg.h>
 
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/hardware.h>
-#include <mach/mmc.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
@@ -103,7 +100,7 @@ static void devboard_sdhc2_exit(struct device *dev, void *data)
         gpio_free(SDHC2_CD);
 }
 
-static struct imxmmc_platform_data sdhc2_pdata = {
+static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
         .get_ro = devboard_sdhc2_get_ro,
         .init   = devboard_sdhc2_init,
         .exit   = devboard_sdhc2_exit,
@@ -187,7 +184,7 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
         return 0;
 }
 
-static struct mxc_usbh_platform_data usbh1_pdata = {
+static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
         .init   = devboard_usbh1_hw_init,
         .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
@@ -196,6 +193,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
 static int __init devboard_usbh1_init(void)
 {
         struct otg_transceiver *otg;
+        struct platform_device *pdev;
 
         otg = kzalloc(sizeof(*otg), GFP_KERNEL);
         if (!otg)
@@ -207,11 +205,15 @@ static int __init devboard_usbh1_init(void)
 
         usbh1_pdata.otg = otg;
 
-        return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+        pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+
+        return 0;
 }
 
 
-static struct fsl_usb2_platform_data usb_pdata = {
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
@@ -228,11 +230,11 @@ void __init mx31moboard_devboard_init(void)
 
         imx31_add_imx_uart1(&uart_pdata);
 
-        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        imx31_add_mxc_mmc(1, &sdhc2_pdata);
 
         devboard_init_sel_gpios();
 
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+        imx31_add_fsl_usb2_udc(&usb_pdata);
 
         devboard_usbh1_init();
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 18069cb7d068..f449a97ae1a2 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -21,7 +21,6 @@
 #include <linux/slab.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
-#include <linux/fsl_devices.h>
 
 #include <linux/usb/otg.h>
 
@@ -29,12 +28,11 @@
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/mmc.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
 #include <media/soc_camera.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int marxbot_pins[] = {
@@ -116,7 +114,7 @@ static void marxbot_sdhc2_exit(struct device *dev, void *data)
         gpio_free(SDHC2_CD);
 }
 
-static struct imxmmc_platform_data sdhc2_pdata = {
+static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
         .get_ro = marxbot_sdhc2_get_ro,
         .init   = marxbot_sdhc2_init,
         .exit   = marxbot_sdhc2_exit,
@@ -302,7 +300,7 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
         return 0;
 }
 
-static struct mxc_usbh_platform_data usbh1_pdata = {
+static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
         .init   = marxbot_usbh1_hw_init,
         .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
@@ -311,6 +309,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
 static int __init marxbot_usbh1_init(void)
 {
         struct otg_transceiver *otg;
+        struct platform_device *pdev;
 
         otg = kzalloc(sizeof(*otg), GFP_KERNEL);
         if (!otg)
@@ -322,10 +321,14 @@ static int __init marxbot_usbh1_init(void)
 
         usbh1_pdata.otg = otg;
 
-        return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+        pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+
+        return 0;
 }
 
-static struct fsl_usb2_platform_data usb_pdata = {
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
@@ -344,7 +347,7 @@ void __init mx31moboard_marxbot_init(void)
 
         dspics_resets_init();
 
-        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        imx31_add_mxc_mmc(1, &sdhc2_pdata);
 
         spi_register_board_info(marxbot_spi_board_info,
                 ARRAY_SIZE(marxbot_spi_board_info));
@@ -357,7 +360,7 @@ void __init mx31moboard_marxbot_init(void)
         gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
         gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
 
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+        imx31_add_fsl_usb2_udc(&usb_pdata);
 
         marxbot_usbh1_init();
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 04760a53005a..bbec3c82264a 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -19,7 +19,6 @@
 #include <linux/i2c.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
-#include <linux/fsl_devices.h>
 
 #include <linux/usb/otg.h>
 #include <linux/usb/ulpi.h>
@@ -28,7 +27,6 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31moboard.h>
-#include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
 #include <media/soc_camera.h>
@@ -118,24 +116,30 @@ static int __init smartbot_cam_init(void)
         return 0;
 }
 
-static struct fsl_usb2_platform_data usb_pdata = {
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
         .operating_mode = FSL_USB2_DR_DEVICE,
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
 #if defined(CONFIG_USB_ULPI)
 
-static struct mxc_usbh_platform_data otg_host_pdata = {
+static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
         .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
         .flags  = MXC_EHCI_POWER_PINS_ENABLED,
 };
 
 static int __init smartbot_otg_host_init(void)
 {
+        struct platform_device *pdev;
+
         otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
                         ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
-        return mxc_register_device(&mxc_otg_host, &otg_host_pdata);
+        pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
+
+        return 0;
 }
 #else
 static inline int smartbot_otg_host_init(void) { return 0; }
@@ -182,7 +186,7 @@ void __init mx31moboard_smartbot_init(int board)
 
         switch (board) {
         case MX31SMARTBOT:
-                mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+                imx31_add_fsl_usb2_udc(&usb_pdata);
                 break;
         case MX31EYEBOT:
                 smartbot_otg_host_init();
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 3ec910a7a182..55254b6e9460 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,20 +1,47 @@
 if ARCH_MX5
+# ARCH_MX51 and ARCH_MX50 are left for compatibility
+
+config ARCH_MX50
+        bool
 
 config ARCH_MX51
         bool
-        default y
+
+config ARCH_MX53
+        bool
+
+config SOC_IMX50
+        bool
+        select MXC_TZIC
+        select ARCH_MXC_IOMUX_V3
+        select ARCH_MXC_AUDMUX_V2
+        select ARCH_HAS_CPUFREQ
+        select ARCH_MX50
+
+config  SOC_IMX51
+        bool
         select MXC_TZIC
         select ARCH_MXC_IOMUX_V3
         select ARCH_MXC_AUDMUX_V2
         select ARCH_HAS_CPUFREQ
+        select ARCH_MX51
+
+config  SOC_IMX53
+        bool
+        select MXC_TZIC
+        select ARCH_MXC_IOMUX_V3
+        select ARCH_MX53
 
 comment "MX5 platforms:"
 
 config MACH_MX51_BABBAGE
         bool "Support MX51 BABBAGE platforms"
+        select SOC_IMX51
+        select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_ESDHC
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Include support for MX51 Babbage platform, also known as MX51EVK in
           u-boot. This includes specific configurations for the board and its
@@ -22,7 +49,9 @@ config MACH_MX51_BABBAGE
 
 config MACH_MX51_3DS
         bool "Support MX51PDK (3DS)"
+        select SOC_IMX51
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_DEBUG_BOARD
         help
@@ -31,6 +60,7 @@ config MACH_MX51_3DS
 
 config MACH_EUKREA_CPUIMX51
         bool "Support Eukrea CPUIMX51 module"
+        select SOC_IMX51
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_IMX_UART
         select IMX_HAVE_PLATFORM_MXC_NAND
@@ -47,7 +77,7 @@ choice
 config MACH_EUKREA_MBIMX51_BASEBOARD
         prompt "Eukrea MBIMX51 development board"
         bool
-        select IMX_HAVE_PLATFORM_ESDHC
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         help
           This adds board specific devices that can be found on Eukrea's
           MBIMX51 evaluation board.
@@ -56,6 +86,7 @@ endchoice
 
 config MACH_EUKREA_CPUIMX51SD
         bool "Support Eukrea CPUIMX51SD module"
+        select SOC_IMX51
         select IMX_HAVE_PLATFORM_IMX_I2C
         select IMX_HAVE_PLATFORM_SPI_IMX
         select IMX_HAVE_PLATFORM_IMX_UART
@@ -72,7 +103,7 @@ choice
 config MACH_EUKREA_MBIMXSD51_BASEBOARD
         prompt "Eukrea MBIMXSD development board"
         bool
-        select IMX_HAVE_PLATFORM_ESDHC
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         help
           This adds board specific devices that can be found on Eukrea's
           MBIMXSD evaluation board.
@@ -81,9 +112,33 @@ endchoice
 
 config MACH_MX51_EFIKAMX
         bool "Support MX51 Genesi Efika MX nettop"
+        select SOC_IMX51
         select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Include support for Genesi Efika MX nettop. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_MX53_EVK
+        bool "Support MX53 EVK platforms"
+        select SOC_IMX53
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Include support for MX53 EVK platform. This includes specific
+          configurations for the board and its peripherals.
+
+
+config MACH_MX50_RDP
+        bool "Support MX50 reference design platform"
+        depends on BROKEN
+        select SOC_IMX50
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        select IMX_HAVE_PLATFORM_SPI_IMX
+        help
+          Include support for MX50 reference design platform (RDP) board. This
+          includes specific configurations for the board and its peripherals.
+
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 462f177eddfe..0c398baf11fe 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,13 +3,16 @@
 #
 
 # Object file lists.
-obj-y   := cpu.o mm.o clock-mx51.o devices.o
+obj-y   := cpu.o mm.o clock-mx51-mx53.o devices.o
+obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
 
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpu_op-mx51.o
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
+obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
 obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
+obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot
index 9939a19d99a1..e928be1b6757 100644
--- a/arch/arm/mach-mx5/Makefile.boot
+++ b/arch/arm/mach-mx5/Makefile.boot
@@ -1,3 +1,9 @@
-   zreladdr-y   := 0x90008000
-params_phys-y   := 0x90000100
-initrd_phys-y   := 0x90800000
+   zreladdr-$(CONFIG_ARCH_MX50) := 0x70008000
+params_phys-$(CONFIG_ARCH_MX50) := 0x70000100
+initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000
+   zreladdr-$(CONFIG_ARCH_MX51) := 0x90008000
+params_phys-$(CONFIG_ARCH_MX51) := 0x90000100
+initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000
+   zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000
+params_phys-$(CONFIG_ARCH_MX53) := 0x70000100
+initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 6a9792fd0a76..f8652ef25f85 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -40,11 +40,11 @@
 #include "devices-imx51.h"
 #include "devices.h"
 
-#define CPUIMX51_USBH1_STP      (0*32 + 27)
-#define CPUIMX51_QUARTA_GPIO    (2*32 + 28)
-#define CPUIMX51_QUARTB_GPIO    (2*32 + 25)
-#define CPUIMX51_QUARTC_GPIO    (2*32 + 26)
-#define CPUIMX51_QUARTD_GPIO    (2*32 + 27)
+#define CPUIMX51_USBH1_STP      IMX_GPIO_NR(1, 27)
+#define CPUIMX51_QUARTA_GPIO    IMX_GPIO_NR(3, 28)
+#define CPUIMX51_QUARTB_GPIO    IMX_GPIO_NR(3, 25)
+#define CPUIMX51_QUARTC_GPIO    IMX_GPIO_NR(3, 26)
+#define CPUIMX51_QUARTD_GPIO    IMX_GPIO_NR(3, 27)
 #define CPUIMX51_QUARTA_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
 #define CPUIMX51_QUARTB_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
 #define CPUIMX51_QUARTC_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
@@ -113,7 +113,7 @@ static struct platform_device *devices[] __initdata = {
 #endif
 };
 
-static struct pad_desc eukrea_cpuimx51_pads[] = {
+static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
         /* UART1 */
         MX51_PAD_UART1_RXD__UART1_RXD,
         MX51_PAD_UART1_TXD__UART1_TXD,
@@ -121,15 +121,15 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
         MX51_PAD_UART1_CTS__UART1_CTS,
 
         /* I2C2 */
-        MX51_PAD_GPIO_1_2__I2C2_SCL,
-        MX51_PAD_GPIO_1_3__I2C2_SDA,
-        MX51_PAD_NANDF_D10__GPIO_3_30,
+        MX51_PAD_GPIO1_2__I2C2_SCL,
+        MX51_PAD_GPIO1_3__I2C2_SDA,
+        MX51_PAD_NANDF_D10__GPIO3_30,
 
         /* QUART IRQ */
-        MX51_PAD_NANDF_D15__GPIO_3_25,
-        MX51_PAD_NANDF_D14__GPIO_3_26,
-        MX51_PAD_NANDF_D13__GPIO_3_27,
-        MX51_PAD_NANDF_D12__GPIO_3_28,
+        MX51_PAD_NANDF_D15__GPIO3_25,
+        MX51_PAD_NANDF_D14__GPIO3_26,
+        MX51_PAD_NANDF_D13__GPIO3_27,
+        MX51_PAD_NANDF_D12__GPIO3_28,
 
         /* USB HOST1 */
         MX51_PAD_USBH1_CLK__USBH1_CLK,
@@ -178,6 +178,8 @@ static int initialize_otg_port(struct platform_device *pdev)
         void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base)
+                return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 
         /* Set the PHY clock to 19.2MHz */
@@ -196,6 +198,8 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base)
+                return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 
         /* The clock for the USBH1 ULPI port will come externally from the PHY. */
@@ -292,7 +296,7 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
         /* Maintainer: Eric Bénard <eric@eukrea.com> */
-        .boot_params = PHYS_OFFSET + 0x100,
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
         .init_irq = mx51_init_irq,
         .init_machine = eukrea_cpuimx51_init,
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index 4b3a6119c5fb..ad931895d8b6 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -43,19 +43,19 @@
 #include "devices-imx51.h"
 #include "devices.h"
 
-#define USBH1_RST               (1*32 + 28)
-#define ETH_RST                 (1*32 + 31)
-#define TSC2007_IRQGPIO         (2*32 + 12)
-#define CAN_IRQGPIO             (0*32 + 1)
-#define CAN_RST                 (3*32 + 15)
-#define CAN_NCS                 (3*32 + 24)
-#define CAN_RXOBF               (0*32 + 4)
-#define CAN_RX1BF               (0*32 + 6)
-#define CAN_TXORTS              (0*32 + 7)
-#define CAN_TX1RTS              (0*32 + 8)
-#define CAN_TX2RTS              (0*32 + 9)
-#define I2C_SCL                 (3*32 + 16)
-#define I2C_SDA                 (3*32 + 17)
+#define USBH1_RST               IMX_GPIO_NR(2, 28)
+#define ETH_RST                 IMX_GPIO_NR(2, 31)
+#define TSC2007_IRQGPIO         IMX_GPIO_NR(3, 12)
+#define CAN_IRQGPIO             IMX_GPIO_NR(1, 1)
+#define CAN_RST                 IMX_GPIO_NR(4, 15)
+#define CAN_NCS                 IMX_GPIO_NR(4, 24)
+#define CAN_RXOBF               IMX_GPIO_NR(1, 4)
+#define CAN_RX1BF               IMX_GPIO_NR(1, 6)
+#define CAN_TXORTS              IMX_GPIO_NR(1, 7)
+#define CAN_TX1RTS              IMX_GPIO_NR(1, 8)
+#define CAN_TX2RTS              IMX_GPIO_NR(1, 9)
+#define I2C_SCL                 IMX_GPIO_NR(4, 16)
+#define I2C_SDA                 IMX_GPIO_NR(4, 17)
 
 /* USB_CTRL_1 */
 #define MX51_USB_CTRL_1_OFFSET          0x10
@@ -65,10 +65,7 @@
 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
 #define MX51_USB_PLL_DIV_24_MHZ         0x02
 
-#define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \
-                                MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
-
-static struct pad_desc eukrea_cpuimx51sd_pads[] = {
+static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
         /* UART1 */
         MX51_PAD_UART1_RXD__UART1_RXD,
         MX51_PAD_UART1_TXD__UART1_TXD,
@@ -88,30 +85,33 @@ static struct pad_desc eukrea_cpuimx51sd_pads[] = {
         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
         MX51_PAD_USBH1_STP__USBH1_STP,
-        MX51_PAD_EIM_CS3__GPIO_2_28,            /* PHY nRESET */
+        MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
 
         /* FEC */
-        MX51_PAD_EIM_DTACK__GPIO_2_31,          /* PHY nRESET */
+        MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
 
         /* HSI2C */
-        MX51_PAD_I2C1_CLK__GPIO_4_16,
-        MX51_PAD_I2C1_DAT__GPIO_4_17,
+        MX51_PAD_I2C1_CLK__GPIO4_16,
+        MX51_PAD_I2C1_DAT__GPIO4_17,
 
         /* CAN */
         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
         MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-        MX51_PAD_CSPI1_SS0__GPIO_4_24,          /* nCS */
-        MX51_PAD_CSI2_PIXCLK__GPIO_4_15,        /* nReset */
-        MX51_PAD_GPIO_1_1__GPIO_1_1,            /* IRQ */
-        MX51_PAD_GPIO_1_4__GPIO_1_4,            /* Control signals */
-        MX51_PAD_GPIO_1_6__GPIO_1_6,
-        MX51_PAD_GPIO_1_7__GPIO_1_7,
-        MX51_PAD_GPIO_1_8__GPIO_1_8,
-        MX51_PAD_GPIO_1_9__GPIO_1_9,
+        MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
+        MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
+        MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
+        MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
+        MX51_PAD_GPIO1_6__GPIO1_6,
+        MX51_PAD_GPIO1_7__GPIO1_7,
+        MX51_PAD_GPIO1_8__GPIO1_8,
+        MX51_PAD_GPIO1_9__GPIO1_9,
 
         /* Touchscreen */
-        CPUIMX51SD_GPIO_3_12,                   /* IRQ */
+        /* IRQ */
+        _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
+                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 };
 
 static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -157,6 +157,8 @@ static int initialize_otg_port(struct platform_device *pdev)
         void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base)
+                return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 
         /* Set the PHY clock to 19.2MHz */
@@ -175,6 +177,8 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base)
+                return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 
         /* The clock for the USBH1 ULPI port will come from the PHY. */
@@ -243,7 +247,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
                 .mode           = SPI_MODE_0,
                 .chip_select     = 0,
                 .platform_data   = &mcp251x_info,
-                .irq             = gpio_to_irq(0 * 32 + 1)
+                .irq             = gpio_to_irq(CAN_IRQGPIO)
         },
 };
 
@@ -323,7 +327,7 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
         /* Maintainer: Eric Bénard <eric@eukrea.com> */
-        .boot_params = PHYS_OFFSET + 0x100,
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
         .init_irq = mx51_init_irq,
         .init_machine = eukrea_cpuimx51sd_init,
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
new file mode 100644
index 000000000000..fd32e4c450e8
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx50.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices-mx50.h"
+
+static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
+        /* SD1 */
+        MX50_PAD_ECSPI2_SS0__GPIO_4_19,
+        MX50_PAD_EIM_CRE__GPIO_1_27,
+        MX50_PAD_SD1_CMD__SD1_CMD,
+
+        MX50_PAD_SD1_CLK__SD1_CLK,
+        MX50_PAD_SD1_D0__SD1_D0,
+        MX50_PAD_SD1_D1__SD1_D1,
+        MX50_PAD_SD1_D2__SD1_D2,
+        MX50_PAD_SD1_D3__SD1_D3,
+
+        /* SD2 */
+        MX50_PAD_SD2_CD__GPIO_5_17,
+        MX50_PAD_SD2_WP__GPIO_5_16,
+        MX50_PAD_SD2_CMD__SD2_CMD,
+        MX50_PAD_SD2_CLK__SD2_CLK,
+        MX50_PAD_SD2_D0__SD2_D0,
+        MX50_PAD_SD2_D1__SD2_D1,
+        MX50_PAD_SD2_D2__SD2_D2,
+        MX50_PAD_SD2_D3__SD2_D3,
+        MX50_PAD_SD2_D4__SD2_D4,
+        MX50_PAD_SD2_D5__SD2_D5,
+        MX50_PAD_SD2_D6__SD2_D6,
+        MX50_PAD_SD2_D7__SD2_D7,
+
+        /* SD3 */
+        MX50_PAD_SD3_CMD__SD3_CMD,
+        MX50_PAD_SD3_CLK__SD3_CLK,
+        MX50_PAD_SD3_D0__SD3_D0,
+        MX50_PAD_SD3_D1__SD3_D1,
+        MX50_PAD_SD3_D2__SD3_D2,
+        MX50_PAD_SD3_D3__SD3_D3,
+        MX50_PAD_SD3_D4__SD3_D4,
+        MX50_PAD_SD3_D5__SD3_D5,
+        MX50_PAD_SD3_D6__SD3_D6,
+        MX50_PAD_SD3_D7__SD3_D7,
+
+        /* PWR_INT */
+        MX50_PAD_ECSPI2_MISO__GPIO_4_18,
+
+        /* UART pad setting */
+        MX50_PAD_UART1_TXD__UART1_TXD,
+        MX50_PAD_UART1_RXD__UART1_RXD,
+        MX50_PAD_UART1_RTS__UART1_RTS,
+        MX50_PAD_UART2_TXD__UART2_TXD,
+        MX50_PAD_UART2_RXD__UART2_RXD,
+        MX50_PAD_UART2_CTS__UART2_CTS,
+        MX50_PAD_UART2_RTS__UART2_RTS,
+
+        MX50_PAD_I2C1_SCL__I2C1_SCL,
+        MX50_PAD_I2C1_SDA__I2C1_SDA,
+        MX50_PAD_I2C2_SCL__I2C2_SCL,
+        MX50_PAD_I2C2_SDA__I2C2_SDA,
+
+        MX50_PAD_EPITO__USBH1_PWR,
+        /* Need to comment below line if
+         * one needs to debug owire.
+         */
+        MX50_PAD_OWIRE__USBH1_OC,
+        /* using gpio to control otg pwr */
+        MX50_PAD_PWM2__GPIO_6_25,
+        MX50_PAD_I2C3_SCL__USBOTG_OC,
+
+        MX50_PAD_SSI_RXC__FEC_MDIO,
+        MX50_PAD_SSI_RXC__FEC_MDIO,
+        MX50_PAD_DISP_D0__FEC_TXCLK,
+        MX50_PAD_DISP_D1__FEC_RX_ER,
+        MX50_PAD_DISP_D2__FEC_RX_DV,
+        MX50_PAD_DISP_D3__FEC_RXD1,
+        MX50_PAD_DISP_D4__FEC_RXD0,
+        MX50_PAD_DISP_D5__FEC_TX_EN,
+        MX50_PAD_DISP_D6__FEC_TXD1,
+        MX50_PAD_DISP_D7__FEC_TXD0,
+        MX50_PAD_SSI_RXFS__FEC_MDC,
+        MX50_PAD_I2C3_SDA__GPIO_6_23,
+        MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
+
+        MX50_PAD_CSPI_SS0__CSPI_SS0,
+        MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
+        MX50_PAD_CSPI_MOSI__CSPI_MOSI,
+        MX50_PAD_CSPI_MISO__CSPI_MISO,
+
+        /* SGTL500_OSC_EN */
+        MX50_PAD_UART1_CTS__GPIO_6_8,
+
+        /* SGTL_AMP_SHDN */
+        MX50_PAD_UART3_RXD__GPIO_6_15,
+
+        /* Keypad */
+        MX50_PAD_KEY_COL0__KEY_COL0,
+        MX50_PAD_KEY_ROW0__KEY_ROW0,
+        MX50_PAD_KEY_COL1__KEY_COL1,
+        MX50_PAD_KEY_ROW1__KEY_ROW1,
+        MX50_PAD_KEY_COL2__KEY_COL2,
+        MX50_PAD_KEY_ROW2__KEY_ROW2,
+        MX50_PAD_KEY_COL3__KEY_COL3,
+        MX50_PAD_KEY_ROW3__KEY_ROW3,
+        MX50_PAD_EIM_DA0__KEY_COL4,
+        MX50_PAD_EIM_DA1__KEY_ROW4,
+        MX50_PAD_EIM_DA2__KEY_COL5,
+        MX50_PAD_EIM_DA3__KEY_ROW5,
+        MX50_PAD_EIM_DA4__KEY_COL6,
+        MX50_PAD_EIM_DA5__KEY_ROW6,
+        MX50_PAD_EIM_DA6__KEY_COL7,
+        MX50_PAD_EIM_DA7__KEY_ROW7,
+        /*EIM pads */
+        MX50_PAD_EIM_DA8__GPIO_1_8,
+        MX50_PAD_EIM_DA9__GPIO_1_9,
+        MX50_PAD_EIM_DA10__GPIO_1_10,
+        MX50_PAD_EIM_DA11__GPIO_1_11,
+        MX50_PAD_EIM_DA12__GPIO_1_12,
+        MX50_PAD_EIM_DA13__GPIO_1_13,
+        MX50_PAD_EIM_DA14__GPIO_1_14,
+        MX50_PAD_EIM_DA15__GPIO_1_15,
+        MX50_PAD_EIM_CS2__GPIO_1_16,
+        MX50_PAD_EIM_CS1__GPIO_1_17,
+        MX50_PAD_EIM_CS0__GPIO_1_18,
+        MX50_PAD_EIM_EB0__GPIO_1_19,
+        MX50_PAD_EIM_EB1__GPIO_1_20,
+        MX50_PAD_EIM_WAIT__GPIO_1_21,
+        MX50_PAD_EIM_BCLK__GPIO_1_22,
+        MX50_PAD_EIM_RDY__GPIO_1_23,
+        MX50_PAD_EIM_OE__GPIO_1_24,
+};
+
+/* Serial ports */
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init mx50_rdp_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
+                                        ARRAY_SIZE(mx50_rdp_pads));
+
+        imx50_add_imx_uart(0, &uart_pdata);
+        imx50_add_imx_uart(1, &uart_pdata);
+}
+
+static void __init mx50_rdp_timer_init(void)
+{
+        mx50_clocks_init(32768, 24000000, 22579200);
+}
+
+static struct sys_timer mx50_rdp_timer = {
+        .init   = mx50_rdp_timer_init,
+};
+
+MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
+        .map_io = mx50_map_io,
+        .init_irq = mx50_init_irq,
+        .init_machine = mx50_rdp_board_init,
+        .timer = &mx50_rdp_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 79ce8dcf3cda..e42bd2eb034e 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -30,7 +30,7 @@
 #define EXPIO_PARENT_INT        (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
 #define MX51_3DS_ECSPI2_CS      (GPIO_PORTC + 28)
 
-static struct pad_desc mx51_3ds_pads[] = {
+static iomux_v3_cfg_t mx51_3ds_pads[] = {
         /* UART1 */
         MX51_PAD_UART1_RXD__UART1_RXD,
         MX51_PAD_UART1_TXD__UART1_TXD,
@@ -50,7 +50,7 @@ static struct pad_desc mx51_3ds_pads[] = {
         MX51_PAD_EIM_D27__UART3_RTS,
 
         /* CPLD PARENT IRQ PIN */
-        MX51_PAD_GPIO_1_6__GPIO_1_6,
+        MX51_PAD_GPIO1_6__GPIO1_6,
 
         /* KPP */
         MX51_PAD_KEY_ROW0__KEY_ROW0,
@@ -68,7 +68,7 @@ static struct pad_desc mx51_3ds_pads[] = {
         MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
         MX51_PAD_NANDF_RB3__ECSPI2_MISO,
         MX51_PAD_NANDF_D15__ECSPI2_MOSI,
-        MX51_PAD_NANDF_D12__GPIO_3_28,
+        MX51_PAD_NANDF_D12__GPIO3_28,
 };
 
 /* Serial ports */
@@ -172,6 +172,7 @@ static void __init mxc_board_init(void)
                 printk(KERN_WARNING "Init of the debugboard failed, all "
                                     "devices on the board are unusable.\n");
 
+        imx51_add_sdhci_esdhc_imx(0, NULL);
         mxc_init_keypad();
 }
 
@@ -186,7 +187,7 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
         /* Maintainer: Freescale Semiconductor, Inc. */
-        .boot_params = PHYS_OFFSET + 0x100,
+        .boot_params = MX51_PHYS_OFFSET + 0x100,
         .map_io = mx51_map_io,
         .init_irq = mx51_init_irq,
         .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index acbe30df2e69..1d231e84107c 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -20,6 +20,8 @@
 #include <linux/fec.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
@@ -36,11 +38,13 @@
 #include "devices.h"
 #include "cpu_op-mx51.h"
 
-#define BABBAGE_USB_HUB_RESET   (0*32 + 7)      /* GPIO_1_7 */
-#define BABBAGE_USBH1_STP       (0*32 + 27)     /* GPIO_1_27 */
-#define BABBAGE_PHY_RESET       (1*32 + 5)      /* GPIO_2_5 */
-#define BABBAGE_FEC_PHY_RESET   (1*32 + 14)     /* GPIO_2_14 */
-#define BABBAGE_POWER_KEY       (1*32 + 21)     /* GPIO_2_21 */
+#define BABBAGE_USB_HUB_RESET   IMX_GPIO_NR(1, 7)
+#define BABBAGE_USBH1_STP       IMX_GPIO_NR(1, 27)
+#define BABBAGE_PHY_RESET       IMX_GPIO_NR(2, 5)
+#define BABBAGE_FEC_PHY_RESET   IMX_GPIO_NR(2, 14)
+#define BABBAGE_POWER_KEY       IMX_GPIO_NR(2, 21)
+#define BABBAGE_ECSPI1_CS0      IMX_GPIO_NR(4, 24)
+#define BABBAGE_ECSPI1_CS1      IMX_GPIO_NR(4, 25)
 
 /* USB_CTRL_1 */
 #define MX51_USB_CTRL_1_OFFSET                  0x10
@@ -65,7 +69,7 @@ static const struct gpio_keys_platform_data imx_button_data __initconst = {
         .nbuttons       = ARRAY_SIZE(babbage_buttons),
 };
 
-static struct pad_desc mx51babbage_pads[] = {
+static iomux_v3_cfg_t mx51babbage_pads[] = {
         /* UART1 */
         MX51_PAD_UART1_RXD__UART1_RXD,
         MX51_PAD_UART1_TXD__UART1_TXD,
@@ -91,8 +95,8 @@ static struct pad_desc mx51babbage_pads[] = {
         MX51_PAD_KEY_COL5__I2C2_SDA,
 
         /* HSI2C */
-        MX51_PAD_I2C1_CLK__HSI2C_CLK,
-        MX51_PAD_I2C1_DAT__HSI2C_DAT,
+        MX51_PAD_I2C1_CLK__I2C1_CLK,
+        MX51_PAD_I2C1_DAT__I2C1_DAT,
 
         /* USB HOST1 */
         MX51_PAD_USBH1_CLK__USBH1_CLK,
@@ -108,29 +112,29 @@ static struct pad_desc mx51babbage_pads[] = {
         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 
         /* USB HUB reset line*/
-        MX51_PAD_GPIO_1_7__GPIO_1_7,
+        MX51_PAD_GPIO1_7__GPIO1_7,
 
         /* FEC */
         MX51_PAD_EIM_EB2__FEC_MDIO,
-        MX51_PAD_EIM_EB3__FEC_RDAT1,
-        MX51_PAD_EIM_CS2__FEC_RDAT2,
-        MX51_PAD_EIM_CS3__FEC_RDAT3,
+        MX51_PAD_EIM_EB3__FEC_RDATA1,
+        MX51_PAD_EIM_CS2__FEC_RDATA2,
+        MX51_PAD_EIM_CS3__FEC_RDATA3,
         MX51_PAD_EIM_CS4__FEC_RX_ER,
         MX51_PAD_EIM_CS5__FEC_CRS,
         MX51_PAD_NANDF_RB2__FEC_COL,
-        MX51_PAD_NANDF_RB3__FEC_RXCLK,
-        MX51_PAD_NANDF_RB6__FEC_RDAT0,
-        MX51_PAD_NANDF_RB7__FEC_TDAT0,
+        MX51_PAD_NANDF_RB3__FEC_RX_CLK,
+        MX51_PAD_NANDF_D9__FEC_RDATA0,
+        MX51_PAD_NANDF_D8__FEC_TDATA0,
         MX51_PAD_NANDF_CS2__FEC_TX_ER,
         MX51_PAD_NANDF_CS3__FEC_MDC,
-        MX51_PAD_NANDF_CS4__FEC_TDAT1,
-        MX51_PAD_NANDF_CS5__FEC_TDAT2,
-        MX51_PAD_NANDF_CS6__FEC_TDAT3,
+        MX51_PAD_NANDF_CS4__FEC_TDATA1,
+        MX51_PAD_NANDF_CS5__FEC_TDATA2,
+        MX51_PAD_NANDF_CS6__FEC_TDATA3,
         MX51_PAD_NANDF_CS7__FEC_TX_EN,
         MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
 
         /* FEC PHY reset line */
-        MX51_PAD_EIM_A20__GPIO_2_14,
+        MX51_PAD_EIM_A20__GPIO2_14,
 
         /* SD 1 */
         MX51_PAD_SD1_CMD__SD1_CMD,
@@ -147,6 +151,13 @@ static struct pad_desc mx51babbage_pads[] = {
         MX51_PAD_SD2_DATA1__SD2_DATA1,
         MX51_PAD_SD2_DATA2__SD2_DATA2,
         MX51_PAD_SD2_DATA3__SD2_DATA3,
+
+        /* eCSPI1 */
+        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+        MX51_PAD_CSPI1_SS0__GPIO4_24,
+        MX51_PAD_CSPI1_SS1__GPIO4_25,
 };
 
 /* Serial ports */
@@ -177,12 +188,12 @@ static struct imxi2c_platform_data babbage_hsi2c_data = {
 
 static int gpio_usbh1_active(void)
 {
-        struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
-        struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
+        iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
+        iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5;
         int ret;
 
         /* Set USBH1_STP to GPIO and toggle it */
-        mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
+        mxc_iomux_v3_setup_pad(usbh1stp_gpio);
         ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
 
         if (ret) {
@@ -195,7 +206,7 @@ static int gpio_usbh1_active(void)
         gpio_free(BABBAGE_USBH1_STP);
 
         /* De-assert USB PHY RESETB */
-        mxc_iomux_v3_setup_pad(&phyreset_gpio);
+        mxc_iomux_v3_setup_pad(phyreset_gpio);
         ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
 
         if (ret) {
@@ -251,6 +262,8 @@ static int initialize_otg_port(struct platform_device *pdev)
         void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base)
+                return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 
         /* Set the PHY clock to 19.2MHz */
@@ -269,6 +282,8 @@ static int initialize_usbh1_port(struct platform_device *pdev)
         void __iomem *usbother_base;
 
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base)
+                return -ENOMEM;
         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 
         /* The clock for the USBH1 ULPI port will come externally from the PHY. */
@@ -310,13 +325,35 @@ static int __init babbage_otg_mode(char *options)
 }
 __setup("otg_mode=", babbage_otg_mode);
 
+static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
+        {
+                .modalias = "mtd_dataflash",
+                .max_speed_hz = 25000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .mode = SPI_MODE_0,
+                .platform_data = NULL,
+        },
+};
+
+static int mx51_babbage_spi_cs[] = {
+        BABBAGE_ECSPI1_CS0,
+        BABBAGE_ECSPI1_CS1,
+};
+
+static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
+        .chipselect     = mx51_babbage_spi_cs,
+        .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
+};
+
 /*
  * Board specific initialization.
  */
 static void __init mxc_board_init(void)
 {
-        struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-        struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21;
+        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
+        iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
+                MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
 
 #if defined(CONFIG_CPU_FREQ_IMX)
         get_cpu_op = mx51_get_cpu_op;
@@ -328,8 +365,7 @@ static void __init mxc_board_init(void)
         imx51_add_fec(NULL);
 
         /* Set the PAD settings for the pwr key. */
-        power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2;
-        mxc_iomux_v3_setup_pad(&power_key);
+        mxc_iomux_v3_setup_pad(power_key);
         imx51_add_gpio_keys(&imx_button_data);
 
         imx51_add_imx_i2c(0, &babbage_i2c_data);
@@ -346,11 +382,16 @@ static void __init mxc_board_init(void)
         gpio_usbh1_active();
         mxc_register_device(&mxc_usbh1_device, &usbh1_config);
         /* setback USBH1_STP to be function */
-        mxc_iomux_v3_setup_pad(&usbh1stp);
+        mxc_iomux_v3_setup_pad(usbh1stp);
         babbage_usbhub_reset();
 
-        imx51_add_esdhc(0, NULL);
-        imx51_add_esdhc(1, NULL);
+        imx51_add_sdhci_esdhc_imx(0, NULL);
+        imx51_add_sdhci_esdhc_imx(1, NULL);
+
+        spi_register_board_info(mx51_babbage_spi_board_info,
+                ARRAY_SIZE(mx51_babbage_spi_board_info));
+        imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
+        imx51_add_imx2_wdt(0, NULL);
 }
 
 static void __init mx51_babbage_timer_init(void)
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index 6e623bda3ee7..b7946f8e8d40 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -18,9 +18,13 @@
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/input.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/fsl_devices.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
@@ -39,12 +43,81 @@
 
 #define MX51_USB_PLL_DIV_24_MHZ 0x01
 
-static struct pad_desc mx51efikamx_pads[] = {
+#define EFIKAMX_PCBID0          IMX_GPIO_NR(3, 16)
+#define EFIKAMX_PCBID1          IMX_GPIO_NR(3, 17)
+#define EFIKAMX_PCBID2          IMX_GPIO_NR(3, 11)
+
+#define EFIKAMX_BLUE_LED        IMX_GPIO_NR(3, 13)
+#define EFIKAMX_GREEN_LED       IMX_GPIO_NR(3, 14)
+#define EFIKAMX_RED_LED         IMX_GPIO_NR(3, 15)
+
+#define EFIKAMX_POWER_KEY       IMX_GPIO_NR(2, 31)
+
+#define EFIKAMX_SPI_CS0         IMX_GPIO_NR(4, 24)
+#define EFIKAMX_SPI_CS1         IMX_GPIO_NR(4, 25)
+
+/* board 1.1 doesn't have same reset gpio */
+#define EFIKAMX_RESET1_1        IMX_GPIO_NR(3, 2)
+#define EFIKAMX_RESET           IMX_GPIO_NR(1, 4)
+
+/* the pci ids pin have pull up. they're driven low according to board id */
+#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
+
+static iomux_v3_cfg_t mx51efikamx_pads[] = {
         /* UART1 */
         MX51_PAD_UART1_RXD__UART1_RXD,
         MX51_PAD_UART1_TXD__UART1_TXD,
         MX51_PAD_UART1_RTS__UART1_RTS,
         MX51_PAD_UART1_CTS__UART1_CTS,
+        /* board id */
+        MX51_PAD_PCBID0,
+        MX51_PAD_PCBID1,
+        MX51_PAD_PCBID2,
+
+        /* SD 1 */
+        MX51_PAD_SD1_CMD__SD1_CMD,
+        MX51_PAD_SD1_CLK__SD1_CLK,
+        MX51_PAD_SD1_DATA0__SD1_DATA0,
+        MX51_PAD_SD1_DATA1__SD1_DATA1,
+        MX51_PAD_SD1_DATA2__SD1_DATA2,
+        MX51_PAD_SD1_DATA3__SD1_DATA3,
+
+        /* SD 2 */
+        MX51_PAD_SD2_CMD__SD2_CMD,
+        MX51_PAD_SD2_CLK__SD2_CLK,
+        MX51_PAD_SD2_DATA0__SD2_DATA0,
+        MX51_PAD_SD2_DATA1__SD2_DATA1,
+        MX51_PAD_SD2_DATA2__SD2_DATA2,
+        MX51_PAD_SD2_DATA3__SD2_DATA3,
+
+        /* SD/MMC WP/CD */
+        MX51_PAD_GPIO1_0__SD1_CD,
+        MX51_PAD_GPIO1_1__SD1_WP,
+        MX51_PAD_GPIO1_7__SD2_WP,
+        MX51_PAD_GPIO1_8__SD2_CD,
+
+        /* leds */
+        MX51_PAD_CSI1_D9__GPIO3_13,
+        MX51_PAD_CSI1_VSYNC__GPIO3_14,
+        MX51_PAD_CSI1_HSYNC__GPIO3_15,
+
+        /* power key */
+        MX51_PAD_PWRKEY,
+
+        /* spi */
+        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+        MX51_PAD_CSPI1_SS0__GPIO4_24,
+        MX51_PAD_CSPI1_SS1__GPIO4_25,
+        MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
+        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+
+        /* reset */
+        MX51_PAD_DI1_PIN13__GPIO3_2,
+        MX51_PAD_GPIO1_4__GPIO1_4,
 };
 
 /* Serial ports */
@@ -75,6 +148,8 @@ static int initialize_otg_port(struct platform_device *pdev)
         void __iomem *usb_base;
         void __iomem *usbother_base;
         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        if (!usb_base)
+                return -ENOMEM;
         usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
 
         /* Set the PHY clock to 19.2MHz */
@@ -92,12 +167,182 @@ static struct mxc_usbh_platform_data dr_utmi_config = {
         .flags  = MXC_EHCI_INTERNAL_PHY,
 };
 
+/*   PCBID2  PCBID1 PCBID0  STATE
+        1       1      1    ER1:rev1.1
+        1       1      0    ER2:rev1.2
+        1       0      1    ER3:rev1.3
+        1       0      0    ER4:rev1.4
+*/
+static void __init mx51_efikamx_board_id(void)
+{
+        int id;
+
+        /* things are taking time to settle */
+        msleep(150);
+
+        gpio_request(EFIKAMX_PCBID0, "pcbid0");
+        gpio_direction_input(EFIKAMX_PCBID0);
+        gpio_request(EFIKAMX_PCBID1, "pcbid1");
+        gpio_direction_input(EFIKAMX_PCBID1);
+        gpio_request(EFIKAMX_PCBID2, "pcbid2");
+        gpio_direction_input(EFIKAMX_PCBID2);
+
+        id = gpio_get_value(EFIKAMX_PCBID0);
+        id |= gpio_get_value(EFIKAMX_PCBID1) << 1;
+        id |= gpio_get_value(EFIKAMX_PCBID2) << 2;
+
+        switch (id) {
+        case 7:
+                system_rev = 0x11;
+                break;
+        case 6:
+                system_rev = 0x12;
+                break;
+        case 5:
+                system_rev = 0x13;
+                break;
+        case 4:
+                system_rev = 0x14;
+                break;
+        default:
+                system_rev = 0x10;
+                break;
+        }
+
+        if ((system_rev == 0x10)
+                || (system_rev == 0x12)
+                || (system_rev == 0x14)) {
+                printk(KERN_WARNING
+                        "EfikaMX: Unsupported board revision 1.%u!\n",
+                        system_rev & 0xf);
+        }
+}
+
+static struct gpio_led mx51_efikamx_leds[] = {
+        {
+                .name = "efikamx:green",
+                .default_trigger = "default-on",
+                .gpio = EFIKAMX_GREEN_LED,
+        },
+        {
+                .name = "efikamx:red",
+                .default_trigger = "ide-disk",
+                .gpio = EFIKAMX_RED_LED,
+        },
+        {
+                .name = "efikamx:blue",
+                .default_trigger = "mmc0",
+                .gpio = EFIKAMX_BLUE_LED,
+        },
+};
+
+static struct gpio_led_platform_data mx51_efikamx_leds_data = {
+        .leds = mx51_efikamx_leds,
+        .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
+};
+
+static struct platform_device mx51_efikamx_leds_device = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev = {
+                .platform_data = &mx51_efikamx_leds_data,
+        },
+};
+
+static struct gpio_keys_button mx51_efikamx_powerkey[] = {
+        {
+                .code = KEY_POWER,
+                .gpio = EFIKAMX_POWER_KEY,
+                .type = EV_PWR,
+                .desc = "Power Button (CM)",
+                .wakeup = 1,
+                .debounce_interval = 10, /* ms */
+        },
+};
+
+static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
+        .buttons = mx51_efikamx_powerkey,
+        .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
+};
+
+static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = {
+        {
+         .name = "u-boot",
+         .offset = 0,
+         .size = SZ_256K,
+        },
+        {
+          .name = "config",
+          .offset = MTDPART_OFS_APPEND,
+          .size = SZ_64K,
+        },
+};
+
+static struct flash_platform_data mx51_efikamx_spi_flash_data = {
+        .name           = "spi_flash",
+        .parts          = mx51_efikamx_spi_nor_partitions,
+        .nr_parts       = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions),
+        .type           = "sst25vf032b",
+};
+
+static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = {
+        {
+                .modalias = "m25p80",
+                .max_speed_hz = 25000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .platform_data = &mx51_efikamx_spi_flash_data,
+                .irq = -1,
+        },
+};
+
+static int mx51_efikamx_spi_cs[] = {
+        EFIKAMX_SPI_CS0,
+        EFIKAMX_SPI_CS1,
+};
+
+static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = {
+        .chipselect     = mx51_efikamx_spi_cs,
+        .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs),
+};
+
+void mx51_efikamx_reset(void)
+{
+        if (system_rev == 0x11)
+                gpio_direction_output(EFIKAMX_RESET1_1, 0);
+        else
+                gpio_direction_output(EFIKAMX_RESET, 0);
+}
+
 static void __init mxc_board_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
                                         ARRAY_SIZE(mx51efikamx_pads));
+        mx51_efikamx_board_id();
         mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
         mxc_init_imx_uart();
+        imx51_add_sdhci_esdhc_imx(0, NULL);
+
+        /* on < 1.2 boards both SD controllers are used */
+        if (system_rev < 0x12) {
+                imx51_add_sdhci_esdhc_imx(1, NULL);
+                mx51_efikamx_leds[2].default_trigger = "mmc1";
+        }
+
+        platform_device_register(&mx51_efikamx_leds_device);
+        imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
+
+        spi_register_board_info(mx51_efikamx_spi_board_info,
+                ARRAY_SIZE(mx51_efikamx_spi_board_info));
+        imx51_add_ecspi(0, &mx51_efikamx_spi_pdata);
+
+        if (system_rev == 0x11) {
+                gpio_request(EFIKAMX_RESET1_1, "reset");
+                gpio_direction_output(EFIKAMX_RESET1_1, 1);
+        } else {
+                gpio_request(EFIKAMX_RESET, "reset");
+                gpio_direction_output(EFIKAMX_RESET, 1);
+        }
 }
 
 static void __init mx51_efikamx_timer_init(void)
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
new file mode 100644
index 000000000000..fa97d0d5dd05
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx53.h>
+
+#include "crm_regs.h"
+#include "devices-imx53.h"
+
+static iomux_v3_cfg_t mx53_evk_pads[] = {
+        MX53_PAD_CSI0_D10__UART1_TXD,
+        MX53_PAD_CSI0_D11__UART1_RXD,
+        MX53_PAD_ATA_DIOW__UART1_TXD,
+        MX53_PAD_ATA_DMACK__UART1_RXD,
+
+        MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
+        MX53_PAD_ATA_DMARQ__UART2_TXD,
+        MX53_PAD_ATA_DIOR__UART2_RTS,
+        MX53_PAD_ATA_INTRQ__UART2_CTS,
+
+        MX53_PAD_ATA_CS_0__UART3_TXD,
+        MX53_PAD_ATA_CS_1__UART3_RXD,
+        MX53_PAD_ATA_DA_1__UART3_CTS,
+        MX53_PAD_ATA_DA_2__UART3_RTS,
+};
+
+static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mx53_evk_init_uart(void)
+{
+        imx53_add_imx_uart(0, &mx53_evk_uart_pdata);
+        imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
+        imx53_add_imx_uart(2, &mx53_evk_uart_pdata);
+}
+
+static void __init mx53_evk_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
+                                        ARRAY_SIZE(mx53_evk_pads));
+        mx53_evk_init_uart();
+}
+
+static void __init mx53_evk_timer_init(void)
+{
+        mx53_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mx53_evk_timer = {
+        .init   = mx53_evk_timer_init,
+};
+
+MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
+        .map_io = mx53_map_io,
+        .init_irq = mx53_init_irq,
+        .init_machine = mx53_evk_board_init,
+        .timer = &mx53_evk_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 8ac36d882927..785e1a336183 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -14,8 +14,8 @@
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
 #include <asm/div64.h>
 
 #include <mach/hardware.h>
@@ -33,11 +33,15 @@ static struct clk pll1_main_clk;
 static struct clk pll1_sw_clk;
 static struct clk pll2_sw_clk;
 static struct clk pll3_sw_clk;
+static struct clk mx53_pll4_sw_clk;
 static struct clk lp_apm_clk;
 static struct clk periph_apm_clk;
 static struct clk ahb_clk;
 static struct clk ipg_clk;
 static struct clk usboh3_clk;
+static struct clk emi_fast_clk;
+static struct clk ipu_clk;
+static struct clk mipi_hsc1_clk;
 
 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
 
@@ -123,7 +127,7 @@ static inline u32 _get_mux(struct clk *parent, struct clk *m0,
         return -EINVAL;
 }
 
-static inline void __iomem *_get_pll_base(struct clk *pll)
+static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
 {
         if (pll == &pll1_main_clk)
                 return MX51_DPLL1_BASE;
@@ -137,6 +141,30 @@ static inline void __iomem *_get_pll_base(struct clk *pll)
         return NULL;
 }
 
+static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
+{
+        if (pll == &pll1_main_clk)
+                return MX53_DPLL1_BASE;
+        else if (pll == &pll2_sw_clk)
+                return MX53_DPLL2_BASE;
+        else if (pll == &pll3_sw_clk)
+                return MX53_DPLL3_BASE;
+        else if (pll == &mx53_pll4_sw_clk)
+                return MX53_DPLL4_BASE;
+        else
+                BUG();
+
+        return NULL;
+}
+
+static inline void __iomem *_get_pll_base(struct clk *pll)
+{
+        if (cpu_is_mx51())
+                return _mx51_get_pll_base(pll);
+        else
+                return _mx53_get_pll_base(pll);
+}
+
 static unsigned long clk_pll_get_rate(struct clk *clk)
 {
         long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
@@ -514,7 +542,10 @@ static int _clk_max_enable(struct clk *clk)
 
         /* Handshake with MAX when LPM is entered. */
         reg = __raw_readl(MXC_CCM_CLPCR);
-        reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+        if (cpu_is_mx51())
+                reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+        else if (cpu_is_mx53())
+                reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
         __raw_writel(reg, MXC_CCM_CLPCR);
 
         return 0;
@@ -528,7 +559,10 @@ static void _clk_max_disable(struct clk *clk)
 
         /* No Handshake with MAX when LPM is entered as its disabled. */
         reg = __raw_readl(MXC_CCM_CLPCR);
-        reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+        if (cpu_is_mx51())
+                reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
+        else if (cpu_is_mx53())
+                reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
         __raw_writel(reg, MXC_CCM_CLPCR);
 }
 
@@ -679,6 +713,19 @@ static unsigned long clk_emi_slow_get_rate(struct clk *clk)
         return clk_get_rate(clk->parent) / div;
 }
 
+static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
+{
+        unsigned long rate;
+        u32 reg, div;
+
+        reg = __raw_readl(MXC_CCM_CBCDR);
+        div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
+                MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
+        rate = clk_get_rate(clk->parent) / div;
+
+        return rate;
+}
+
 /* External high frequency clock */
 static struct clk ckih_clk = {
         .get_rate = get_high_reference_clock_rate,
@@ -739,6 +786,14 @@ static struct clk pll3_sw_clk = {
         .disable = _clk_pll_disable,
 };
 
+/* PLL4 SW supplies to LVDS Display Bridge(LDB) */
+static struct clk mx53_pll4_sw_clk = {
+        .parent = &osc_clk,
+        .set_rate = _clk_pll_set_rate,
+        .enable = _clk_pll_enable,
+        .disable = _clk_pll_disable,
+};
+
 /* Low-power Audio Playback Mode clock */
 static struct clk lp_apm_clk = {
         .parent = &osc_clk,
@@ -763,6 +818,12 @@ static struct clk ahb_clk = {
         .round_rate = _clk_ahb_round_rate,
 };
 
+static struct clk iim_clk = {
+        .parent = &ipg_clk,
+        .enable_reg = MXC_CCM_CCGR0,
+        .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+};
+
 /* Main IP interface clock for access to registers */
 static struct clk ipg_clk = {
         .parent = &ahb_clk,
@@ -810,6 +871,10 @@ static struct clk kpp_clk = {
         .id = 0,
 };
 
+static struct clk dummy_clk = {
+        .id = 0,
+};
+
 static struct clk emi_slow_clk = {
         .parent = &pll2_sw_clk,
         .enable_reg = MXC_CCM_CCGR5,
@@ -819,6 +884,109 @@ static struct clk emi_slow_clk = {
         .get_rate = clk_emi_slow_get_rate,
 };
 
+static int clk_ipu_enable(struct clk *clk)
+{
+        u32 reg;
+
+        _clk_ccgr_enable(clk);
+
+        /* Enable handshake with IPU when certain clock rates are changed */
+        reg = __raw_readl(MXC_CCM_CCDR);
+        reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
+        __raw_writel(reg, MXC_CCM_CCDR);
+
+        /* Enable handshake with IPU when LPM is entered */
+        reg = __raw_readl(MXC_CCM_CLPCR);
+        reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+        __raw_writel(reg, MXC_CCM_CLPCR);
+
+        return 0;
+}
+
+static void clk_ipu_disable(struct clk *clk)
+{
+        u32 reg;
+
+        _clk_ccgr_disable(clk);
+
+        /* Disable handshake with IPU whe dividers are changed */
+        reg = __raw_readl(MXC_CCM_CCDR);
+        reg |= MXC_CCM_CCDR_IPU_HS_MASK;
+        __raw_writel(reg, MXC_CCM_CCDR);
+
+        /* Disable handshake with IPU when LPM is entered */
+        reg = __raw_readl(MXC_CCM_CLPCR);
+        reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
+        __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static struct clk ahbmux1_clk = {
+        .parent = &ahb_clk,
+        .secondary = &ahb_max_clk,
+        .enable_reg = MXC_CCM_CCGR0,
+        .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+        .enable = _clk_ccgr_enable,
+        .disable = _clk_ccgr_disable_inwait,
+};
+
+static struct clk ipu_sec_clk = {
+        .parent = &emi_fast_clk,
+        .secondary = &ahbmux1_clk,
+};
+
+static struct clk ddr_hf_clk = {
+        .parent = &pll1_sw_clk,
+        .get_rate = _clk_ddr_hf_get_rate,
+};
+
+static struct clk ddr_clk = {
+        .parent = &ddr_hf_clk,
+};
+
+/* clock definitions for MIPI HSC unit which has been removed
+ * from documentation, but not from hardware
+ */
+static int _clk_hsc_enable(struct clk *clk)
+{
+        u32 reg;
+
+        _clk_ccgr_enable(clk);
+        /* Handshake with IPU when certain clock rates are changed. */
+        reg = __raw_readl(MXC_CCM_CCDR);
+        reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
+        __raw_writel(reg, MXC_CCM_CCDR);
+
+        reg = __raw_readl(MXC_CCM_CLPCR);
+        reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
+        __raw_writel(reg, MXC_CCM_CLPCR);
+
+        return 0;
+}
+
+static void _clk_hsc_disable(struct clk *clk)
+{
+        u32 reg;
+
+        _clk_ccgr_disable(clk);
+        /* No handshake with HSC as its not enabled. */
+        reg = __raw_readl(MXC_CCM_CCDR);
+        reg |= MXC_CCM_CCDR_HSC_HS_MASK;
+        __raw_writel(reg, MXC_CCM_CCDR);
+
+        reg = __raw_readl(MXC_CCM_CLPCR);
+        reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
+        __raw_writel(reg, MXC_CCM_CLPCR);
+}
+
+static struct clk mipi_hsp_clk = {
+        .parent = &ipu_clk,
+        .enable_reg = MXC_CCM_CCGR4,
+        .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+        .enable = _clk_hsc_enable,
+        .disable = _clk_hsc_disable,
+        .secondary = &mipi_hsc1_clk,
+};
+
 #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s)   \
         static struct clk name = {                      \
                 .id             = i,                    \
@@ -927,6 +1095,41 @@ static struct clk usboh3_clk = {
         .parent = &pll2_sw_clk,
         .get_rate = clk_usboh3_get_rate,
         .set_parent = clk_usboh3_set_parent,
+        .enable = _clk_ccgr_enable,
+        .disable = _clk_ccgr_disable,
+        .enable_reg = MXC_CCM_CCGR2,
+        .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
+};
+
+static struct clk usb_ahb_clk = {
+        .parent = &ipg_clk,
+        .enable = _clk_ccgr_enable,
+        .disable = _clk_ccgr_disable,
+        .enable_reg = MXC_CCM_CCGR2,
+        .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
+};
+
+static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
+
+        if (parent == &pll3_sw_clk)
+                reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
+
+        __raw_writel(reg, MXC_CCM_CSCMR1);
+
+        return 0;
+}
+
+static struct clk usb_phy1_clk = {
+        .parent = &pll3_sw_clk,
+        .set_parent = clk_usb_phy1_set_parent,
+        .enable = _clk_ccgr_enable,
+        .enable_reg = MXC_CCM_CCGR2,
+        .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+        .disable = _clk_ccgr_disable,
 };
 
 /* eCSPI */
@@ -1013,6 +1216,10 @@ DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
         NULL, NULL, &ipg_clk, NULL);
 DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
         NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
+DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
+        NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
 
 /* eCSPI */
 DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
@@ -1046,6 +1253,23 @@ DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
 DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
         clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
 
+DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
+DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
+DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
+
+/* IPU */
+DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
+        NULL,  NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
+
+DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
+                NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
+                &ddr_clk, NULL);
+
+DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
+                NULL, NULL, &pll3_sw_clk, NULL);
+DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
+                NULL, NULL, &pll3_sw_clk, NULL);
+
 #define _REGISTER_CLOCK(d, n, c) \
        { \
                 .dev_id = d, \
@@ -1053,7 +1277,7 @@ DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
                 .clk = &c,   \
        },
 
-static struct clk_lookup lookups[] = {
+static struct clk_lookup mx51_lookups[] = {
         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
@@ -1063,15 +1287,19 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
         _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
         _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
-        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
         _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
-        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
         _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
         _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
         _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
@@ -1082,6 +1310,22 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
+        _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
+        _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
+        _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
+        _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
+        _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
+        _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
+        _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
+};
+
+static struct clk_lookup mx53_lookups[] = {
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+        _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
 };
 
 static void clk_tree_init(void)
@@ -1114,14 +1358,22 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
         ckih2_reference = ckih2;
         oscillator_reference = osc;
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
+                clkdev_add(&mx51_lookups[i]);
 
         clk_tree_init();
 
+        clk_set_parent(&uart_root_clk, &pll3_sw_clk);
         clk_enable(&cpu_clk);
         clk_enable(&main_bus_clk);
 
+        clk_enable(&iim_clk);
+        mx51_revision();
+        clk_disable(&iim_clk);
+
+        /* move usb_phy_clk to 24MHz */
+        clk_set_parent(&usb_phy1_clk, &osc_clk);
+
         /* set the usboh3_clk parent to pll2_sw_clk */
         clk_set_parent(&usboh3_clk, &pll2_sw_clk);
 
@@ -1138,3 +1390,31 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
                 MX51_MXC_INT_GPT);
         return 0;
 }
+
+int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
+                        unsigned long ckih1, unsigned long ckih2)
+{
+        int i;
+
+        external_low_reference = ckil;
+        external_high_reference = ckih1;
+        ckih2_reference = ckih2;
+        oscillator_reference = osc;
+
+        for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
+                clkdev_add(&mx53_lookups[i]);
+
+        clk_tree_init();
+
+        clk_enable(&cpu_clk);
+        clk_enable(&main_bus_clk);
+
+        clk_enable(&iim_clk);
+        mx53_revision();
+        clk_disable(&iim_clk);
+
+        /* System timer */
+        mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
+                MX53_INT_GPT);
+        return 0;
+}
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index eaacb6e9b5d0..d40671da4372 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * The code contained herein is licensed under the GNU General Public
  * License. You may obtain a copy of the GNU General Public License
@@ -20,37 +20,18 @@
 
 static int cpu_silicon_rev = -1;
 
-#define SI_REV 0x48
+#define IIM_SREV 0x24
 
-static void query_silicon_parameter(void)
+static int get_mx51_srev(void)
 {
-        void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
-        u32 rev;
+        void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
+        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
 
-        if (!rom) {
-                cpu_silicon_rev = -EINVAL;
-                return;
-        }
-
-        rev = readl(rom + SI_REV);
-        switch (rev) {
-        case 0x1:
-                cpu_silicon_rev = MX51_CHIP_REV_1_0;
-                break;
-        case 0x2:
-                cpu_silicon_rev = MX51_CHIP_REV_1_1;
-                break;
-        case 0x10:
-                cpu_silicon_rev = MX51_CHIP_REV_2_0;
-                break;
-        case 0x20:
-                cpu_silicon_rev = MX51_CHIP_REV_3_0;
-                break;
-        default:
-                cpu_silicon_rev = 0;
-        }
-
-        iounmap(rom);
+        if (rev == 0x0)
+                return IMX_CHIP_REVISION_2_0;
+        else if (rev == 0x10)
+                return IMX_CHIP_REVISION_3_0;
+        return 0;
 }
 
 /*
@@ -64,7 +45,7 @@ int mx51_revision(void)
                 return -EINVAL;
 
         if (cpu_silicon_rev == -1)
-                query_silicon_parameter();
+                cpu_silicon_rev = get_mx51_srev();
 
         return cpu_silicon_rev;
 }
@@ -79,7 +60,10 @@ EXPORT_SYMBOL(mx51_revision);
  */
 static int __init mx51_neon_fixup(void)
 {
-        if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
+        if (!cpu_is_mx51())
+                return 0;
+
+        if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
                 elf_hwcap &= ~HWCAP_NEON;
                 pr_info("Turning off NEON support, detected broken NEON implementation\n");
         }
@@ -89,29 +73,65 @@ static int __init mx51_neon_fixup(void)
 late_initcall(mx51_neon_fixup);
 #endif
 
+static int get_mx53_srev(void)
+{
+        void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
+        u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+
+        if (rev == 0x0)
+                return IMX_CHIP_REVISION_1_0;
+        else if (rev == 0x10)
+                return IMX_CHIP_REVISION_2_0;
+        return 0;
+}
+
+/*
+ * Returns:
+ *      the silicon revision of the cpu
+ *      -EINVAL - not a mx53
+ */
+int mx53_revision(void)
+{
+        if (!cpu_is_mx53())
+                return -EINVAL;
+
+        if (cpu_silicon_rev == -1)
+                cpu_silicon_rev = get_mx53_srev();
+
+        return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx53_revision);
+
 static int __init post_cpu_init(void)
 {
         unsigned int reg;
         void __iomem *base;
 
-        if (!cpu_is_mx51())
-                return 0;
-
-        base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
-        __raw_writel(0x0, base + 0x40);
-        __raw_writel(0x0, base + 0x44);
-        __raw_writel(0x0, base + 0x48);
-        __raw_writel(0x0, base + 0x4C);
-        reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-        __raw_writel(reg, base + 0x50);
-
-        base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
-        __raw_writel(0x0, base + 0x40);
-        __raw_writel(0x0, base + 0x44);
-        __raw_writel(0x0, base + 0x48);
-        __raw_writel(0x0, base + 0x4C);
-        reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
-        __raw_writel(reg, base + 0x50);
+        if (cpu_is_mx51() || cpu_is_mx53()) {
+                if (cpu_is_mx51())
+                        base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
+                else
+                        base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
+
+                __raw_writel(0x0, base + 0x40);
+                __raw_writel(0x0, base + 0x44);
+                __raw_writel(0x0, base + 0x48);
+                __raw_writel(0x0, base + 0x4C);
+                reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+                __raw_writel(reg, base + 0x50);
+
+                if (cpu_is_mx51())
+                        base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
+                else
+                        base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
+
+                __raw_writel(0x0, base + 0x40);
+                __raw_writel(0x0, base + 0x44);
+                __raw_writel(0x0, base + 0x48);
+                __raw_writel(0x0, base + 0x4C);
+                reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+                __raw_writel(reg, base + 0x50);
+        }
 
         return 0;
 }
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index c776b9af0624..b462c22f53d8 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -18,6 +18,13 @@
 #define MX51_CORTEXA8_BASE      MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
 #define MX51_GPC_BASE           MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
 
+/*MX53*/
+#define MX53_CCM_BASE           MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
+#define MX53_DPLL1_BASE         MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
+#define MX53_DPLL2_BASE         MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
+#define MX53_DPLL3_BASE         MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+#define MX53_DPLL4_BASE         MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
+
 /* PLL Register Offsets */
 #define MXC_PLL_DP_CTL                  0x00
 #define MXC_PLL_DP_CONFIG               0x04
@@ -380,7 +387,8 @@
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS         (0x1 << 23)
 #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS         (0x1 << 22)
-#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS         (0x1 << 21)
+#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS                (0x1 << 21)
+#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS                (0x1 << 25)
 #define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS        (0x1 << 20)
 #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS         (0x1 << 19)
 #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS         (0x1 << 18)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index 8c50cb5d05f5..6302e4670000 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -31,6 +31,11 @@ extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
 #define imx51_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
 
+extern const struct imx_sdhci_esdhc_imx_data
+imx51_sdhci_esdhc_imx_data[] __initconst;
+#define imx51_add_sdhci_esdhc_imx(id, pdata)    \
+        imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
+
 extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
 #define imx51_add_cspi(pdata)   \
         imx_add_spi_imx(&imx51_cspi_data, pdata)
@@ -39,6 +44,6 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
 #define imx51_add_ecspi(id, pdata)      \
         imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
 
-extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst;
-#define imx51_add_esdhc(id, pdata)      \
-        imx_add_esdhc(&imx51_esdhc_data[id], pdata)
+extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst;
+#define imx51_add_imx2_wdt(id, pdata)   \
+        imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
new file mode 100644
index 000000000000..9d0ec2507fa6
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx53.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst;
+#define imx53_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-mx50.h b/arch/arm/mach-mx5/devices-mx50.h
new file mode 100644
index 000000000000..98ab07468a0e
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-mx50.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/mx50.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
+#define imx50_add_imx_uart(id, pdata)   \
+        imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 4c7be87a7c9d..1bda5cb339dc 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -97,19 +97,27 @@ struct platform_device mxc_usbh1_device = {
         },
 };
 
-static struct resource mxc_wdt_resources[] = {
+static struct resource usbh2_resources[] = {
         {
-                .start = MX51_WDOG_BASE_ADDR,
-                .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1,
+                .start = MX51_OTG_BASE_ADDR + 0x400,
+                .end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .start = MX51_MXC_INT_USB_H2,
+                .flags = IORESOURCE_IRQ,
+        },
 };
 
-struct platform_device mxc_wdt = {
-        .name = "imx2-wdt",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_wdt_resources),
-        .resource = mxc_wdt_resources,
+struct platform_device mxc_usbh2_device = {
+        .name = "mxc-ehci",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(usbh2_resources),
+        .resource = usbh2_resources,
+        .dev = {
+                .dma_mask = &usb_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
 };
 
 static struct resource mxc_kpp_resources[] = {
@@ -160,9 +168,36 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
                 .irq_high = MX51_MXC_INT_GPIO4_HIGH,
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
         },
+        {
+                .chip.label = "gpio-4",
+                .base = MX53_IO_ADDRESS(MX53_GPIO5_BASE_ADDR),
+                .irq = MX53_INT_GPIO5_LOW,
+                .irq_high = MX53_INT_GPIO5_HIGH,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4
+        },
+        {
+                .chip.label = "gpio-5",
+                .base = MX53_IO_ADDRESS(MX53_GPIO6_BASE_ADDR),
+                .irq = MX53_INT_GPIO6_LOW,
+                .irq_high = MX53_INT_GPIO6_HIGH,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5
+        },
+        {
+                .chip.label = "gpio-6",
+                .base = MX53_IO_ADDRESS(MX53_GPIO7_BASE_ADDR),
+                .irq = MX53_INT_GPIO7_LOW,
+                .irq_high = MX53_INT_GPIO7_HIGH,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6
+        },
 };
 
 int __init imx51_register_gpios(void)
 {
+        return mxc_gpio_init(mxc_gpio_ports, 4);
+}
+
+int __init imx53_register_gpios(void)
+{
         return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
 }
+
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index af1d07c0bbc1..16891aa3573c 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -1,6 +1,6 @@
 extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
+extern struct platform_device mxc_usbh2_device;
 extern struct platform_device mxc_usbdr_udc_device;
-extern struct platform_device mxc_wdt;
 extern struct platform_device mxc_hsi2c_device;
 extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index a2e6e8c39d25..c96d018ff8a2 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -33,12 +33,12 @@
 #include "devices-imx51.h"
 #include "devices.h"
 
-#define MBIMX51_TSC2007_GPIO    (2*32 + 30)
+#define MBIMX51_TSC2007_GPIO    IMX_GPIO_NR(3, 30)
 #define MBIMX51_TSC2007_IRQ     (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO)
-#define MBIMX51_LED0            (2*32 + 5)
-#define MBIMX51_LED1            (2*32 + 6)
-#define MBIMX51_LED2            (2*32 + 7)
-#define MBIMX51_LED3            (2*32 + 8)
+#define MBIMX51_LED0            IMX_GPIO_NR(3, 5)
+#define MBIMX51_LED1            IMX_GPIO_NR(3, 6)
+#define MBIMX51_LED2            IMX_GPIO_NR(3, 7)
+#define MBIMX51_LED3            IMX_GPIO_NR(3, 8)
 
 static struct gpio_led mbimx51_leds[] = {
         {
@@ -84,7 +84,7 @@ static struct platform_device *devices[] __initdata = {
         &mbimx51_leds_gpio,
 };
 
-static struct pad_desc mbimx51_pads[] = {
+static iomux_v3_cfg_t mbimx51_pads[] = {
         /* UART2 */
         MX51_PAD_UART2_RXD__UART2_RXD,
         MX51_PAD_UART2_TXD__UART2_TXD,
@@ -96,13 +96,13 @@ static struct pad_desc mbimx51_pads[] = {
         MX51_PAD_KEY_COL5__UART3_CTS,
 
         /* TSC2007 IRQ */
-        MX51_PAD_NANDF_D10__GPIO_3_30,
+        MX51_PAD_NANDF_D10__GPIO3_30,
 
         /* LEDS */
-        MX51_PAD_DISPB2_SER_DIN__GPIO_3_5,
-        MX51_PAD_DISPB2_SER_DIO__GPIO_3_6,
-        MX51_PAD_DISPB2_SER_CLK__GPIO_3_7,
-        MX51_PAD_DISPB2_SER_RS__GPIO_3_8,
+        MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
+        MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
+        MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
+        MX51_PAD_DISPB2_SER_RS__GPIO3_8,
 
         /* KPP */
         MX51_PAD_KEY_ROW0__KEY_ROW0,
@@ -217,6 +217,6 @@ void __init eukrea_mbimx51_baseboard_init(void)
         i2c_register_board_info(1, mbimx51_i2c_devices,
                                 ARRAY_SIZE(mbimx51_i2c_devices));
 
-        imx51_add_esdhc(0, NULL);
-        imx51_add_esdhc(1, NULL);
+        imx51_add_sdhci_esdhc_imx(0, NULL);
+        imx51_add_sdhci_esdhc_imx(1, NULL);
 }
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
index 2b48f5190830..c372a4373691 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -45,14 +45,13 @@
 #include "devices-imx51.h"
 #include "devices.h"
 
-#define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \
-                                MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
-
-static struct pad_desc eukrea_mbimxsd_pads[] = {
+static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
         /* LED */
-        MX51_PAD_NANDF_D10__GPIO_3_30,
+        MX51_PAD_NANDF_D10__GPIO3_30,
         /* SWITCH */
-        MBIMXSD_GPIO_3_31,
+        _MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
+                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
+                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
         /* UART2 */
         MX51_PAD_UART2_RXD__UART2_RXD,
         MX51_PAD_UART2_TXD__UART2_TXD,
@@ -70,8 +69,8 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
         MX51_PAD_SD1_DATA3__SD1_DATA3,
 };
 
-#define GPIO_LED1       (2 * 32 + 30)
-#define GPIO_SWITCH1    (2 * 32 + 31)
+#define GPIO_LED1       IMX_GPIO_NR(3, 30)
+#define GPIO_SWITCH1    IMX_GPIO_NR(3, 31)
 
 static struct gpio_led eukrea_mbimxsd_leds[] = {
         {
@@ -149,7 +148,7 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
         imx51_add_imx_uart(1, NULL);
         imx51_add_imx_uart(2, &uart_pdata);
 
-        imx51_add_esdhc(0, NULL);
+        imx51_add_sdhci_esdhc_imx(0, NULL);
 
         gpio_request(GPIO_LED1, "LED1");
         gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
new file mode 100644
index 000000000000..8c6540e58390
--- /dev/null
+++ b/arch/arm/mach-mx5/mm-mx50.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Create static mapping between physical to virtual memory.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-v3.h>
+
+/*
+ * Define the MX50 memory map.
+ */
+static struct map_desc mx50_io_desc[] __initdata = {
+        imx_map_entry(MX50, TZIC, MT_DEVICE),
+        imx_map_entry(MX50, SPBA0, MT_DEVICE),
+        imx_map_entry(MX50, AIPS1, MT_DEVICE),
+        imx_map_entry(MX50, AIPS2, MT_DEVICE),
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx50_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX50);
+        mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
+        iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
+}
+
+int imx50_register_gpios(void);
+
+void __init mx50_init_irq(void)
+{
+        tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
+        imx50_register_gpios();
+}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index bc3f30db8d9a..457f9f95204b 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * The code contained herein is licensed under the GNU General Public
  * License.  You may obtain a copy of the GNU General Public License
@@ -23,33 +23,21 @@
 /*
  * Define the MX51 memory map.
  */
-static struct map_desc mxc_io_desc[] __initdata = {
-        {
-                .virtual = MX51_IRAM_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR),
-                .length = MX51_IRAM_SIZE,
-                .type = MT_DEVICE
-        }, {
-                .virtual = MX51_DEBUG_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
-                .length = MX51_DEBUG_SIZE,
-                .type = MT_DEVICE
-        }, {
-                .virtual = MX51_AIPS1_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
-                .length = MX51_AIPS1_SIZE,
-                .type = MT_DEVICE
-        }, {
-                .virtual = MX51_SPBA0_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),
-                .length = MX51_SPBA0_SIZE,
-                .type = MT_DEVICE
-        }, {
-                .virtual = MX51_AIPS2_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
-                .length = MX51_AIPS2_SIZE,
-                .type = MT_DEVICE
-        },
+static struct map_desc mx51_io_desc[] __initdata = {
+        imx_map_entry(MX51, IRAM, MT_DEVICE),
+        imx_map_entry(MX51, DEBUG, MT_DEVICE),
+        imx_map_entry(MX51, AIPS1, MT_DEVICE),
+        imx_map_entry(MX51, SPBA0, MT_DEVICE),
+        imx_map_entry(MX51, AIPS2, MT_DEVICE),
+};
+
+/*
+ * Define the MX53 memory map.
+ */
+static struct map_desc mx53_io_desc[] __initdata = {
+        imx_map_entry(MX53, AIPS1, MT_DEVICE),
+        imx_map_entry(MX53, SPBA0, MT_DEVICE),
+        imx_map_entry(MX53, AIPS2, MT_DEVICE),
 };
 
 /*
@@ -61,8 +49,16 @@ void __init mx51_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
-        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
+        iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
+}
+
+void __init mx53_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX53);
+        mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR));
+        iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
 }
 
 int imx51_register_gpios(void);
@@ -72,7 +68,7 @@ void __init mx51_init_irq(void)
         unsigned long tzic_addr;
         void __iomem *tzic_virt;
 
-        if (mx51_revision() < MX51_CHIP_REV_2_0)
+        if (mx51_revision() < IMX_CHIP_REVISION_2_0)
                 tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
         else
                 tzic_addr = MX51_TZIC_BASE_ADDR;
@@ -84,3 +80,20 @@ void __init mx51_init_irq(void)
         tzic_init_irq(tzic_virt);
         imx51_register_gpios();
 }
+
+int imx53_register_gpios(void);
+
+void __init mx53_init_irq(void)
+{
+        unsigned long tzic_addr;
+        void __iomem *tzic_virt;
+
+        tzic_addr = MX53_TZIC_BASE_ADDR;
+
+        tzic_virt = ioremap(tzic_addr, SZ_16K);
+        if (!tzic_virt)
+                panic("unable to map TZIC interrupt controller\n");
+
+        tzic_init_irq(tzic_virt);
+        imx53_register_gpios();
+}
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
index 5c85075d8a56..9fab505f1eb1 100644
--- a/arch/arm/mach-mxc91231/clock.c
+++ b/arch/arm/mach-mxc91231/clock.c
@@ -2,12 +2,12 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/clkdev.h>
 
 #include <mach/clock.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 
-#include <asm/clkdev.h>
 #include <asm/bug.h>
 #include <asm/div64.h>
 
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index aeccfd755fee..7652c301da88 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -27,48 +27,15 @@
 /*
  * This structure defines the MXC memory map.
  */
-static struct map_desc mxc_io_desc[] __initdata = {
-        {
-                .virtual        = MXC91231_L2CC_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR),
-                .length         = MXC91231_L2CC_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = MXC91231_X_MEMC_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR),
-                .length         = MXC91231_X_MEMC_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = MXC91231_ROMP_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR),
-                .length         = MXC91231_ROMP_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = MXC91231_AVIC_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR),
-                .length         = MXC91231_AVIC_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = MXC91231_AIPS1_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR),
-                .length         = MXC91231_AIPS1_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = MXC91231_SPBA0_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR),
-                .length         = MXC91231_SPBA0_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = MXC91231_SPBA1_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR),
-                .length         = MXC91231_SPBA1_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = MXC91231_AIPS2_BASE_ADDR_VIRT,
-                .pfn            = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR),
-                .length         = MXC91231_AIPS2_SIZE,
-                .type           = MT_DEVICE,
-        },
+static struct map_desc mxc91231_io_desc[] __initdata = {
+        imx_map_entry(MXC91231, L2CC, MT_DEVICE),
+        imx_map_entry(MXC91231, X_MEMC, MT_DEVICE),
+        imx_map_entry(MXC91231, ROMP, MT_DEVICE),
+        imx_map_entry(MXC91231, AVIC, MT_DEVICE),
+        imx_map_entry(MXC91231, AIPS1, MT_DEVICE),
+        imx_map_entry(MXC91231, SPBA0, MT_DEVICE),
+        imx_map_entry(MXC91231, SPBA1, MT_DEVICE),
+        imx_map_entry(MXC91231, AIPS2, MT_DEVICE),
 };
 
 /*
@@ -80,7 +47,7 @@ void __init mxc91231_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MXC91231);
 
-        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+        iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
 }
 
 int mxc91231_register_gpios(void);
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
new file mode 100644
index 000000000000..c4ac7b415195
--- /dev/null
+++ b/arch/arm/mach-mxs/Kconfig
@@ -0,0 +1,34 @@
+if ARCH_MXS
+
+source "arch/arm/mach-mxs/devices/Kconfig"
+
+config SOC_IMX23
+        bool
+        select CPU_ARM926T
+
+config SOC_IMX28
+        bool
+        select CPU_ARM926T
+
+comment "MXS platforms:"
+
+config MACH_MX23EVK
+        bool "Support MX23EVK Platform"
+        select SOC_IMX23
+        select MXS_HAVE_PLATFORM_DUART
+        default y
+        help
+          Include support for MX23EVK platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_MX28EVK
+        bool "Support MX28EVK Platform"
+        select SOC_IMX28
+        select MXS_HAVE_PLATFORM_DUART
+        select MXS_HAVE_PLATFORM_FEC
+        default y
+        help
+          Include support for MX28EVK platform. This includes specific
+          configurations for the board and its peripherals.
+
+endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
new file mode 100644
index 000000000000..39d3f9c2a841
--- /dev/null
+++ b/arch/arm/mach-mxs/Makefile
@@ -0,0 +1,10 @@
+# Common support
+obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
+
+obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
+obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
+
+obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
+obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
+
+obj-y += devices/
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
new file mode 100644
index 000000000000..eb541e0291da
--- /dev/null
+++ b/arch/arm/mach-mxs/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y := 0x40008000
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
new file mode 100644
index 000000000000..8f5a19ab558c
--- /dev/null
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -0,0 +1,526 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+
+#include <asm/clkdev.h>
+#include <asm/div64.h>
+
+#include <mach/mx23.h>
+#include <mach/common.h>
+#include <mach/clock.h>
+
+#include "regs-clkctrl-mx23.h"
+
+#define CLKCTRL_BASE_ADDR       MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
+#define DIGCTRL_BASE_ADDR       MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
+
+#define PARENT_RATE_SHIFT       8
+
+static int _raw_clk_enable(struct clk *clk)
+{
+        u32 reg;
+
+        if (clk->enable_reg) {
+                reg = __raw_readl(clk->enable_reg);
+                reg &= ~(1 << clk->enable_shift);
+                __raw_writel(reg, clk->enable_reg);
+        }
+
+        return 0;
+}
+
+static void _raw_clk_disable(struct clk *clk)
+{
+        u32 reg;
+
+        if (clk->enable_reg) {
+                reg = __raw_readl(clk->enable_reg);
+                reg |= 1 << clk->enable_shift;
+                __raw_writel(reg, clk->enable_reg);
+        }
+}
+
+/*
+ * ref_xtal_clk
+ */
+static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
+{
+        return 24000000;
+}
+
+static struct clk ref_xtal_clk = {
+        .get_rate = ref_xtal_clk_get_rate,
+};
+
+/*
+ * pll_clk
+ */
+static unsigned long pll_clk_get_rate(struct clk *clk)
+{
+        return 480000000;
+}
+
+static int pll_clk_enable(struct clk *clk)
+{
+        __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
+                        BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
+
+        /* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
+         * and is incorrect (excessive). Per definition of the PLLCTRL0
+         * POWER field, waiting at least 10us.
+         */
+        udelay(10);
+
+        return 0;
+}
+
+static void pll_clk_disable(struct clk *clk)
+{
+        __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
+                        BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
+}
+
+static struct clk pll_clk = {
+         .get_rate = pll_clk_get_rate,
+         .enable = pll_clk_enable,
+         .disable = pll_clk_disable,
+         .parent = &ref_xtal_clk,
+};
+
+/*
+ * ref_clk
+ */
+#define _CLK_GET_RATE_REF(name, sr, ss)                                 \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        unsigned long parent_rate;                                      \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
+        div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
+        parent_rate = clk_get_rate(clk->parent);                        \
+                                                                        \
+        return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
+                        div, PARENT_RATE_SHIFT);                        \
+}
+
+_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
+_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
+_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
+_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
+
+#define _DEFINE_CLOCK_REF(name, er, es)                                 \
+        static struct clk name = {                                      \
+                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
+                .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
+                .get_rate       = name##_get_rate,                      \
+                .enable         = _raw_clk_enable,                      \
+                .disable        = _raw_clk_disable,                     \
+                .parent         = &pll_clk,                             \
+        }
+
+_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
+_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
+_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
+_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
+
+/*
+ * General clocks
+ *
+ * clk_get_rate
+ */
+static unsigned long rtc_clk_get_rate(struct clk *clk)
+{
+        /* ref_xtal_clk is implemented as the only parent */
+        return clk_get_rate(clk->parent) / 768;
+}
+
+static unsigned long clk32k_clk_get_rate(struct clk *clk)
+{
+        return clk->parent->get_rate(clk->parent) / 750;
+}
+
+#define _CLK_GET_RATE(name, rs)                                         \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+                                                                        \
+        if (clk->parent == &ref_xtal_clk)                               \
+                div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
+                        BP_CLKCTRL_##rs##_DIV_XTAL;                     \
+        else                                                            \
+                div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
+                        BP_CLKCTRL_##rs##_DIV_##rs;                     \
+                                                                        \
+        if (!div)                                                       \
+                return -EINVAL;                                         \
+                                                                        \
+        return clk_get_rate(clk->parent) / div;                         \
+}
+
+_CLK_GET_RATE(cpu_clk, CPU)
+_CLK_GET_RATE(emi_clk, EMI)
+
+#define _CLK_GET_RATE1(name, rs)                                        \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+        div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
+                                                                        \
+        if (!div)                                                       \
+                return -EINVAL;                                         \
+                                                                        \
+        return clk_get_rate(clk->parent) / div;                         \
+}
+
+_CLK_GET_RATE1(hbus_clk, HBUS)
+_CLK_GET_RATE1(xbus_clk, XBUS)
+_CLK_GET_RATE1(ssp_clk, SSP)
+_CLK_GET_RATE1(gpmi_clk, GPMI)
+_CLK_GET_RATE1(lcdif_clk, PIX)
+
+#define _CLK_GET_RATE_STUB(name)                                        \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        return clk_get_rate(clk->parent);                               \
+}
+
+_CLK_GET_RATE_STUB(uart_clk)
+_CLK_GET_RATE_STUB(audio_clk)
+_CLK_GET_RATE_STUB(pwm_clk)
+
+/*
+ * clk_set_rate
+ */
+static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg, bm_busy, div_max, d, f, div, frac;
+        unsigned long diff, parent_rate, calc_rate;
+        int i;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->parent == &ref_xtal_clk) {
+                div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
+                bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
+                div = DIV_ROUND_UP(parent_rate, rate);
+                if (div == 0 || div > div_max)
+                        return -EINVAL;
+        } else {
+                div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
+                bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
+                rate >>= PARENT_RATE_SHIFT;
+                parent_rate >>= PARENT_RATE_SHIFT;
+                diff = parent_rate;
+                div = frac = 1;
+                for (d = 1; d <= div_max; d++) {
+                        f = parent_rate * 18 / d / rate;
+                        if ((parent_rate * 18 / d) % rate)
+                                f++;
+                        if (f < 18 || f > 35)
+                                continue;
+
+                        calc_rate = parent_rate * 18 / f / d;
+                        if (calc_rate > rate)
+                                continue;
+
+                        if (rate - calc_rate < diff) {
+                                frac = f;
+                                div = d;
+                                diff = rate - calc_rate;
+                        }
+
+                        if (diff == 0)
+                                break;
+                }
+
+                if (diff == parent_rate)
+                        return -EINVAL;
+
+                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
+                reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
+                reg |= frac;
+                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
+        }
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
+        reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
+        reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
+
+        for (i = 10000; i; i--)
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
+                                        HW_CLKCTRL_CPU) & bm_busy))
+                        break;
+        if (!i) {
+                pr_err("%s: divider writing timeout\n", __func__);
+                return -ETIMEDOUT;
+        }
+
+        return 0;
+}
+
+#define _CLK_SET_RATE(name, dr)                                         \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        u32 reg, div_max, div;                                          \
+        unsigned long parent_rate;                                      \
+        int i;                                                          \
+                                                                        \
+        parent_rate = clk_get_rate(clk->parent);                        \
+        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
+                                                                        \
+        div = DIV_ROUND_UP(parent_rate, rate);                          \
+        if (div == 0 || div > div_max)                                  \
+                return -EINVAL;                                         \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
+        reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
+        reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
+        if (reg | (1 << clk->enable_shift)) {                           \
+                pr_err("%s: clock is gated\n", __func__);               \
+                return -EINVAL;                                         \
+        }                                                               \
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
+                                                                        \
+        for (i = 10000; i; i--)                                         \
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
+                        HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY))     \
+                        break;                                          \
+        if (!i) {                                                       \
+                pr_err("%s: divider writing timeout\n", __func__);      \
+                return -ETIMEDOUT;                                      \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+
+_CLK_SET_RATE(xbus_clk, XBUS)
+_CLK_SET_RATE(ssp_clk, SSP)
+_CLK_SET_RATE(gpmi_clk, GPMI)
+_CLK_SET_RATE(lcdif_clk, PIX)
+
+#define _CLK_SET_RATE_STUB(name)                                        \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        return -EINVAL;                                                 \
+}
+
+_CLK_SET_RATE_STUB(emi_clk)
+_CLK_SET_RATE_STUB(uart_clk)
+_CLK_SET_RATE_STUB(audio_clk)
+_CLK_SET_RATE_STUB(pwm_clk)
+_CLK_SET_RATE_STUB(clk32k_clk)
+
+/*
+ * clk_set_parent
+ */
+#define _CLK_SET_PARENT(name, bit)                                      \
+static int name##_set_parent(struct clk *clk, struct clk *parent)       \
+{                                                                       \
+        if (parent != clk->parent) {                                    \
+                __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
+                         HW_CLKCTRL_CLKSEQ_TOG);                        \
+                clk->parent = parent;                                   \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+
+_CLK_SET_PARENT(cpu_clk, CPU)
+_CLK_SET_PARENT(emi_clk, EMI)
+_CLK_SET_PARENT(ssp_clk, SSP)
+_CLK_SET_PARENT(gpmi_clk, GPMI)
+_CLK_SET_PARENT(lcdif_clk, PIX)
+
+#define _CLK_SET_PARENT_STUB(name)                                      \
+static int name##_set_parent(struct clk *clk, struct clk *parent)       \
+{                                                                       \
+        if (parent != clk->parent)                                      \
+                return -EINVAL;                                         \
+        else                                                            \
+                return 0;                                               \
+}
+
+_CLK_SET_PARENT_STUB(uart_clk)
+_CLK_SET_PARENT_STUB(audio_clk)
+_CLK_SET_PARENT_STUB(pwm_clk)
+_CLK_SET_PARENT_STUB(clk32k_clk)
+
+/*
+ * clk definition
+ */
+static struct clk cpu_clk = {
+        .get_rate = cpu_clk_get_rate,
+        .set_rate = cpu_clk_set_rate,
+        .set_parent = cpu_clk_set_parent,
+        .parent = &ref_cpu_clk,
+};
+
+static struct clk hbus_clk = {
+        .get_rate = hbus_clk_get_rate,
+        .parent = &cpu_clk,
+};
+
+static struct clk xbus_clk = {
+        .get_rate = xbus_clk_get_rate,
+        .set_rate = xbus_clk_set_rate,
+        .parent = &ref_xtal_clk,
+};
+
+static struct clk rtc_clk = {
+        .get_rate = rtc_clk_get_rate,
+        .parent = &ref_xtal_clk,
+};
+
+/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
+static struct clk usb_clk = {
+        .enable_reg = DIGCTRL_BASE_ADDR,
+        .enable_shift = 2,
+        .enable = _raw_clk_enable,
+        .disable = _raw_clk_disable,
+        .parent = &pll_clk,
+};
+
+#define _DEFINE_CLOCK(name, er, es, p)                                  \
+        static struct clk name = {                                      \
+                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
+                .enable_shift   = BP_CLKCTRL_##er##_##es,               \
+                .get_rate       = name##_get_rate,                      \
+                .set_rate       = name##_set_rate,                      \
+                .set_parent     = name##_set_parent,                    \
+                .enable         = _raw_clk_enable,                      \
+                .disable        = _raw_clk_disable,                     \
+                .parent         = p,                                    \
+        }
+
+_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
+        _REGISTER_CLOCK("rtc", NULL, rtc_clk)
+        _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
+        _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
+        _REGISTER_CLOCK(NULL, "usb", usb_clk)
+        _REGISTER_CLOCK(NULL, "audio", audio_clk)
+        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+};
+
+static int clk_misc_init(void)
+{
+        u32 reg;
+        int i;
+
+        /* Fix up parent per register setting */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
+        cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
+                        &ref_xtal_clk : &ref_cpu_clk;
+        emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
+                        &ref_xtal_clk : &ref_emi_clk;
+        ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
+                        &ref_xtal_clk : &ref_io_clk;
+        gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
+                        &ref_xtal_clk : &ref_io_clk;
+        lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
+                        &ref_xtal_clk : &ref_pix_clk;
+
+        /* Use int div over frac when both are available */
+        __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
+        __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
+        __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
+        reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
+        reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
+        reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
+        reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
+
+        /*
+         * Set safe hbus clock divider. A divider of 3 ensure that
+         * the Vddd voltage required for the cpu clock is sufficiently
+         * high for the hbus clock.
+         */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+        reg &= BM_CLKCTRL_HBUS_DIV;
+        reg |= 3 << BP_CLKCTRL_HBUS_DIV;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+
+        for (i = 10000; i; i--)
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
+                        HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_BUSY))
+                        break;
+        if (!i) {
+                pr_err("%s: divider writing timeout\n", __func__);
+                return -ETIMEDOUT;
+        }
+
+        /* Gate off cpu clock in WFI for power saving */
+        __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
+
+        return 0;
+}
+
+int __init mx23_clocks_init(void)
+{
+        clk_misc_init();
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
+
+        return 0;
+}
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
new file mode 100644
index 000000000000..74e2103c6011
--- /dev/null
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -0,0 +1,734 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/jiffies.h>
+
+#include <asm/clkdev.h>
+#include <asm/div64.h>
+
+#include <mach/mx28.h>
+#include <mach/common.h>
+#include <mach/clock.h>
+
+#include "regs-clkctrl-mx28.h"
+
+#define CLKCTRL_BASE_ADDR       MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
+#define DIGCTRL_BASE_ADDR       MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
+
+#define PARENT_RATE_SHIFT       8
+
+static struct clk pll2_clk;
+static struct clk cpu_clk;
+static struct clk emi_clk;
+static struct clk saif0_clk;
+static struct clk saif1_clk;
+static struct clk clk32k_clk;
+
+static int _raw_clk_enable(struct clk *clk)
+{
+        u32 reg;
+
+        if (clk->enable_reg) {
+                reg = __raw_readl(clk->enable_reg);
+                reg &= ~(1 << clk->enable_shift);
+                __raw_writel(reg, clk->enable_reg);
+        }
+
+        return 0;
+}
+
+static void _raw_clk_disable(struct clk *clk)
+{
+        u32 reg;
+
+        if (clk->enable_reg) {
+                reg = __raw_readl(clk->enable_reg);
+                reg |= 1 << clk->enable_shift;
+                __raw_writel(reg, clk->enable_reg);
+        }
+}
+
+/*
+ * ref_xtal_clk
+ */
+static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
+{
+        return 24000000;
+}
+
+static struct clk ref_xtal_clk = {
+        .get_rate = ref_xtal_clk_get_rate,
+};
+
+/*
+ * pll_clk
+ */
+static unsigned long pll0_clk_get_rate(struct clk *clk)
+{
+        return 480000000;
+}
+
+static unsigned long pll1_clk_get_rate(struct clk *clk)
+{
+        return 480000000;
+}
+
+static unsigned long pll2_clk_get_rate(struct clk *clk)
+{
+        return 50000000;
+}
+
+#define _CLK_ENABLE_PLL(name, r, g)                                     \
+static int name##_enable(struct clk *clk)                               \
+{                                                                       \
+        __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
+                     CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET);    \
+        udelay(10);                                                     \
+                                                                        \
+        if (clk == &pll2_clk)                                           \
+                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
+        else                                                            \
+                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
+                                                                        \
+        return 0;                                                       \
+}
+
+_CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
+_CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
+_CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
+
+#define _CLK_DISABLE_PLL(name, r, g)                                    \
+static void name##_disable(struct clk *clk)                             \
+{                                                                       \
+        __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER,                       \
+                     CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR);    \
+                                                                        \
+        if (clk == &pll2_clk)                                           \
+                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
+        else                                                            \
+                __raw_writel(BM_CLKCTRL_##r##CTRL0_##g,                 \
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
+                                                                        \
+}
+
+_CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
+_CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
+_CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
+
+#define _DEFINE_CLOCK_PLL(name)                                         \
+        static struct clk name = {                                      \
+                .get_rate       = name##_get_rate,                      \
+                .enable         = name##_enable,                        \
+                .disable        = name##_disable,                       \
+                .parent         = &ref_xtal_clk,                        \
+        }
+
+_DEFINE_CLOCK_PLL(pll0_clk);
+_DEFINE_CLOCK_PLL(pll1_clk);
+_DEFINE_CLOCK_PLL(pll2_clk);
+
+/*
+ * ref_clk
+ */
+#define _CLK_GET_RATE_REF(name, sr, ss)                                 \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        unsigned long parent_rate;                                      \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
+        div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
+        parent_rate = clk_get_rate(clk->parent);                        \
+                                                                        \
+        return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
+                        div, PARENT_RATE_SHIFT);                        \
+}
+
+_CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
+_CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
+_CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
+_CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
+_CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
+_CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
+
+#define _DEFINE_CLOCK_REF(name, er, es)                                 \
+        static struct clk name = {                                      \
+                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
+                .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
+                .get_rate       = name##_get_rate,                      \
+                .enable         = _raw_clk_enable,                      \
+                .disable        = _raw_clk_disable,                     \
+                .parent         = &pll0_clk,                            \
+        }
+
+_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
+_DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
+_DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
+_DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
+_DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
+_DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
+
+/*
+ * General clocks
+ *
+ * clk_get_rate
+ */
+static unsigned long lradc_clk_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 16;
+}
+
+static unsigned long rtc_clk_get_rate(struct clk *clk)
+{
+        /* ref_xtal_clk is implemented as the only parent */
+        return clk_get_rate(clk->parent) / 768;
+}
+
+static unsigned long clk32k_clk_get_rate(struct clk *clk)
+{
+        return clk->parent->get_rate(clk->parent) / 750;
+}
+
+static unsigned long spdif_clk_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / 4;
+}
+
+#define _CLK_GET_RATE(name, rs)                                         \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+                                                                        \
+        if (clk->parent == &ref_xtal_clk)                               \
+                div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
+                        BP_CLKCTRL_##rs##_DIV_XTAL;                     \
+        else                                                            \
+                div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
+                        BP_CLKCTRL_##rs##_DIV_##rs;                     \
+                                                                        \
+        if (!div)                                                       \
+                return -EINVAL;                                         \
+                                                                        \
+        return clk_get_rate(clk->parent) / div;                         \
+}
+
+_CLK_GET_RATE(cpu_clk, CPU)
+_CLK_GET_RATE(emi_clk, EMI)
+
+#define _CLK_GET_RATE1(name, rs)                                        \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        u32 reg, div;                                                   \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+        div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
+                                                                        \
+        if (!div)                                                       \
+                return -EINVAL;                                         \
+                                                                        \
+        if (clk == &saif0_clk || clk == &saif1_clk)                     \
+                return clk_get_rate(clk->parent) >> 16 * div;           \
+        else                                                            \
+                return clk_get_rate(clk->parent) / div;                 \
+}
+
+_CLK_GET_RATE1(hbus_clk, HBUS)
+_CLK_GET_RATE1(xbus_clk, XBUS)
+_CLK_GET_RATE1(ssp0_clk, SSP0)
+_CLK_GET_RATE1(ssp1_clk, SSP1)
+_CLK_GET_RATE1(ssp2_clk, SSP2)
+_CLK_GET_RATE1(ssp3_clk, SSP3)
+_CLK_GET_RATE1(gpmi_clk, GPMI)
+_CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
+_CLK_GET_RATE1(saif0_clk, SAIF0)
+_CLK_GET_RATE1(saif1_clk, SAIF1)
+
+#define _CLK_GET_RATE_STUB(name)                                        \
+static unsigned long name##_get_rate(struct clk *clk)                   \
+{                                                                       \
+        return clk_get_rate(clk->parent);                               \
+}
+
+_CLK_GET_RATE_STUB(uart_clk)
+_CLK_GET_RATE_STUB(pwm_clk)
+_CLK_GET_RATE_STUB(can0_clk)
+_CLK_GET_RATE_STUB(can1_clk)
+_CLK_GET_RATE_STUB(fec_clk)
+
+/*
+ * clk_set_rate
+ */
+/* fool compiler */
+#define BM_CLKCTRL_CPU_DIV      0
+#define BP_CLKCTRL_CPU_DIV      0
+#define BM_CLKCTRL_CPU_BUSY     0
+
+#define _CLK_SET_RATE(name, dr, fr, fs)                                 \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        u32 reg, bm_busy, div_max, d, f, div, frac;                     \
+        unsigned long diff, parent_rate, calc_rate;                     \
+        int i;                                                          \
+                                                                        \
+        parent_rate = clk_get_rate(clk->parent);                        \
+        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
+        bm_busy = BM_CLKCTRL_##dr##_BUSY;                               \
+                                                                        \
+        if (clk->parent == &ref_xtal_clk) {                             \
+                div = DIV_ROUND_UP(parent_rate, rate);                  \
+                if (clk == &cpu_clk) {                                  \
+                        div_max = BM_CLKCTRL_CPU_DIV_XTAL >>            \
+                                BP_CLKCTRL_CPU_DIV_XTAL;                \
+                        bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;         \
+                }                                                       \
+                if (div == 0 || div > div_max)                          \
+                        return -EINVAL;                                 \
+        } else {                                                        \
+                rate >>= PARENT_RATE_SHIFT;                             \
+                parent_rate >>= PARENT_RATE_SHIFT;                      \
+                diff = parent_rate;                                     \
+                div = frac = 1;                                         \
+                if (clk == &cpu_clk) {                                  \
+                        div_max = BM_CLKCTRL_CPU_DIV_CPU >>             \
+                                BP_CLKCTRL_CPU_DIV_CPU;                 \
+                        bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;          \
+                }                                                       \
+                for (d = 1; d <= div_max; d++) {                        \
+                        f = parent_rate * 18 / d / rate;                \
+                        if ((parent_rate * 18 / d) % rate)              \
+                                f++;                                    \
+                        if (f < 18 || f > 35)                           \
+                                continue;                               \
+                                                                        \
+                        calc_rate = parent_rate * 18 / f / d;           \
+                        if (calc_rate > rate)                           \
+                                continue;                               \
+                                                                        \
+                        if (rate - calc_rate < diff) {                  \
+                                frac = f;                               \
+                                div = d;                                \
+                                diff = rate - calc_rate;                \
+                        }                                               \
+                                                                        \
+                        if (diff == 0)                                  \
+                                break;                                  \
+                }                                                       \
+                                                                        \
+                if (diff == parent_rate)                                \
+                        return -EINVAL;                                 \
+                                                                        \
+                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
+                reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC;                   \
+                reg |= frac;                                            \
+                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
+        }                                                               \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
+        if (clk == &cpu_clk) {                                          \
+                reg &= ~BM_CLKCTRL_CPU_DIV_CPU;                         \
+                reg |= div << BP_CLKCTRL_CPU_DIV_CPU;                   \
+        } else {                                                        \
+                reg &= ~BM_CLKCTRL_##dr##_DIV;                          \
+                reg |= div << BP_CLKCTRL_##dr##_DIV;                    \
+                if (reg | (1 << clk->enable_shift)) {                   \
+                        pr_err("%s: clock is gated\n", __func__);       \
+                        return -EINVAL;                                 \
+                }                                                       \
+        }                                                               \
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);          \
+                                                                        \
+        for (i = 10000; i; i--)                                         \
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
+                        HW_CLKCTRL_##dr) & bm_busy))                    \
+                        break;                                          \
+        if (!i) {                                                       \
+                pr_err("%s: divider writing timeout\n", __func__);      \
+                return -ETIMEDOUT;                                      \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+
+_CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
+_CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
+_CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
+_CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
+_CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
+_CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
+_CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
+
+#define _CLK_SET_RATE1(name, dr)                                        \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        u32 reg, div_max, div;                                          \
+        unsigned long parent_rate;                                      \
+        int i;                                                          \
+                                                                        \
+        parent_rate = clk_get_rate(clk->parent);                        \
+        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
+                                                                        \
+        div = DIV_ROUND_UP(parent_rate, rate);                          \
+        if (div == 0 || div > div_max)                                  \
+                return -EINVAL;                                         \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
+        reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
+        reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
+        if (reg | (1 << clk->enable_shift)) {                           \
+                pr_err("%s: clock is gated\n", __func__);               \
+                return -EINVAL;                                         \
+        }                                                               \
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
+                                                                        \
+        for (i = 10000; i; i--)                                         \
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
+                        HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY))     \
+                        break;                                          \
+        if (!i) {                                                       \
+                pr_err("%s: divider writing timeout\n", __func__);      \
+                return -ETIMEDOUT;                                      \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+
+_CLK_SET_RATE1(xbus_clk, XBUS)
+
+/* saif clock uses 16 bits frac div */
+#define _CLK_SET_RATE_SAIF(name, rs)                                    \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        u16 div;                                                        \
+        u32 reg;                                                        \
+        u64 lrate;                                                      \
+        unsigned long parent_rate;                                      \
+        int i;                                                          \
+                                                                        \
+        parent_rate = clk_get_rate(clk->parent);                        \
+        if (rate > parent_rate)                                         \
+                return -EINVAL;                                         \
+                                                                        \
+        lrate = (u64)rate << 16;                                        \
+        do_div(lrate, parent_rate);                                     \
+        div = (u16)lrate;                                               \
+                                                                        \
+        if (!div)                                                       \
+                return -EINVAL;                                         \
+                                                                        \
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+        reg &= ~BM_CLKCTRL_##rs##_DIV;                                  \
+        reg |= div << BP_CLKCTRL_##rs##_DIV;                            \
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
+                                                                        \
+        for (i = 10000; i; i--)                                         \
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +                   \
+                        HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY))     \
+                        break;                                          \
+        if (!i) {                                                       \
+                pr_err("%s: divider writing timeout\n", __func__);      \
+                return -ETIMEDOUT;                                      \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+
+_CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
+_CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
+
+#define _CLK_SET_RATE_STUB(name)                                        \
+static int name##_set_rate(struct clk *clk, unsigned long rate)         \
+{                                                                       \
+        return -EINVAL;                                                 \
+}
+
+_CLK_SET_RATE_STUB(emi_clk)
+_CLK_SET_RATE_STUB(uart_clk)
+_CLK_SET_RATE_STUB(pwm_clk)
+_CLK_SET_RATE_STUB(spdif_clk)
+_CLK_SET_RATE_STUB(clk32k_clk)
+_CLK_SET_RATE_STUB(can0_clk)
+_CLK_SET_RATE_STUB(can1_clk)
+_CLK_SET_RATE_STUB(fec_clk)
+
+/*
+ * clk_set_parent
+ */
+#define _CLK_SET_PARENT(name, bit)                                      \
+static int name##_set_parent(struct clk *clk, struct clk *parent)       \
+{                                                                       \
+        if (parent != clk->parent) {                                    \
+                __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
+                         HW_CLKCTRL_CLKSEQ_TOG);                        \
+                clk->parent = parent;                                   \
+        }                                                               \
+                                                                        \
+        return 0;                                                       \
+}
+
+_CLK_SET_PARENT(cpu_clk, CPU)
+_CLK_SET_PARENT(emi_clk, EMI)
+_CLK_SET_PARENT(ssp0_clk, SSP0)
+_CLK_SET_PARENT(ssp1_clk, SSP1)
+_CLK_SET_PARENT(ssp2_clk, SSP2)
+_CLK_SET_PARENT(ssp3_clk, SSP3)
+_CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
+_CLK_SET_PARENT(gpmi_clk, GPMI)
+_CLK_SET_PARENT(saif0_clk, SAIF0)
+_CLK_SET_PARENT(saif1_clk, SAIF1)
+
+#define _CLK_SET_PARENT_STUB(name)                                      \
+static int name##_set_parent(struct clk *clk, struct clk *parent)       \
+{                                                                       \
+        if (parent != clk->parent)                                      \
+                return -EINVAL;                                         \
+        else                                                            \
+                return 0;                                               \
+}
+
+_CLK_SET_PARENT_STUB(pwm_clk)
+_CLK_SET_PARENT_STUB(uart_clk)
+_CLK_SET_PARENT_STUB(clk32k_clk)
+_CLK_SET_PARENT_STUB(spdif_clk)
+_CLK_SET_PARENT_STUB(fec_clk)
+_CLK_SET_PARENT_STUB(can0_clk)
+_CLK_SET_PARENT_STUB(can1_clk)
+
+/*
+ * clk definition
+ */
+static struct clk cpu_clk = {
+        .get_rate = cpu_clk_get_rate,
+        .set_rate = cpu_clk_set_rate,
+        .set_parent = cpu_clk_set_parent,
+        .parent = &ref_cpu_clk,
+};
+
+static struct clk hbus_clk = {
+        .get_rate = hbus_clk_get_rate,
+        .parent = &cpu_clk,
+};
+
+static struct clk xbus_clk = {
+        .get_rate = xbus_clk_get_rate,
+        .set_rate = xbus_clk_set_rate,
+        .parent = &ref_xtal_clk,
+};
+
+static struct clk lradc_clk = {
+        .get_rate = lradc_clk_get_rate,
+        .parent = &clk32k_clk,
+};
+
+static struct clk rtc_clk = {
+        .get_rate = rtc_clk_get_rate,
+        .parent = &ref_xtal_clk,
+};
+
+/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
+static struct clk usb0_clk = {
+        .enable_reg = DIGCTRL_BASE_ADDR,
+        .enable_shift = 2,
+        .enable = _raw_clk_enable,
+        .disable = _raw_clk_disable,
+        .parent = &pll0_clk,
+};
+
+static struct clk usb1_clk = {
+        .enable_reg = DIGCTRL_BASE_ADDR,
+        .enable_shift = 16,
+        .enable = _raw_clk_enable,
+        .disable = _raw_clk_disable,
+        .parent = &pll1_clk,
+};
+
+#define _DEFINE_CLOCK(name, er, es, p)                                  \
+        static struct clk name = {                                      \
+                .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
+                .enable_shift   = BP_CLKCTRL_##er##_##es,               \
+                .get_rate       = name##_get_rate,                      \
+                .set_rate       = name##_set_rate,                      \
+                .set_parent     = name##_set_parent,                    \
+                .enable         = _raw_clk_enable,                      \
+                .disable        = _raw_clk_disable,                     \
+                .parent         = p,                                    \
+        }
+
+_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
+_DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
+_DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
+_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
+_DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
+_DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
+        _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK("rtc", NULL, rtc_clk)
+        _REGISTER_CLOCK("pll2", NULL, pll2_clk)
+        _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
+        _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
+        _REGISTER_CLOCK(NULL, "can0", can0_clk)
+        _REGISTER_CLOCK(NULL, "can1", can1_clk)
+        _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
+        _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
+        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+        _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
+        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
+};
+
+static int clk_misc_init(void)
+{
+        u32 reg;
+        int i;
+
+        /* Fix up parent per register setting */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
+        cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
+                        &ref_xtal_clk : &ref_cpu_clk;
+        emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
+                        &ref_xtal_clk : &ref_emi_clk;
+        ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
+                        &ref_xtal_clk : &ref_io0_clk;
+        ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
+                        &ref_xtal_clk : &ref_io0_clk;
+        ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
+                        &ref_xtal_clk : &ref_io1_clk;
+        ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
+                        &ref_xtal_clk : &ref_io1_clk;
+        lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
+                        &ref_xtal_clk : &ref_pix_clk;
+        gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
+                        &ref_xtal_clk : &ref_gpmi_clk;
+        saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
+                        &ref_xtal_clk : &pll0_clk;
+        saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
+                        &ref_xtal_clk : &pll0_clk;
+
+        /* Use int div over frac when both are available */
+        __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
+        __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
+        __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
+        reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
+        reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
+        reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
+        reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
+        reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
+        reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
+        reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
+
+        /* SAIF has to use frac div for functional operation */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
+        reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
+
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
+        reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
+
+        /*
+         * Set safe hbus clock divider. A divider of 3 ensure that
+         * the Vddd voltage required for the cpu clock is sufficiently
+         * high for the hbus clock.
+         */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+        reg &= BM_CLKCTRL_HBUS_DIV;
+        reg |= 3 << BP_CLKCTRL_HBUS_DIV;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+
+        for (i = 10000; i; i--)
+                if (!(__raw_readl(CLKCTRL_BASE_ADDR +
+                        HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
+                        break;
+        if (!i) {
+                pr_err("%s: divider writing timeout\n", __func__);
+                return -ETIMEDOUT;
+        }
+
+        /* Gate off cpu clock in WFI for power saving */
+        __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
+                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
+
+        /* Extra fec clock setting */
+        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+        reg &= ~BM_CLKCTRL_ENET_SLEEP;
+        reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
+        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+
+        return 0;
+}
+
+int __init mx28_clocks_init(void)
+{
+        clk_misc_init();
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
+
+        return 0;
+}
diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
new file mode 100644
index 000000000000..e7d2269cf70e
--- /dev/null
+++ b/arch/arm/mach-mxs/clock.c
@@ -0,0 +1,200 @@
+/*
+ * Based on arch/arm/plat-omap/clock.c
+ *
+ * Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
+ * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+/* #define DEBUG */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/proc_fs.h>
+#include <linux/semaphore.h>
+#include <linux/string.h>
+
+#include <mach/clock.h>
+
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+
+/*-------------------------------------------------------------------------
+ * Standard clock functions defined in include/linux/clk.h
+ *-------------------------------------------------------------------------*/
+
+static void __clk_disable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+        WARN_ON(!clk->usecount);
+
+        if (!(--clk->usecount)) {
+                if (clk->disable)
+                        clk->disable(clk);
+                __clk_disable(clk->parent);
+                __clk_disable(clk->secondary);
+        }
+}
+
+static int __clk_enable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        if (clk->usecount++ == 0) {
+                __clk_enable(clk->parent);
+                __clk_enable(clk->secondary);
+
+                if (clk->enable)
+                        clk->enable(clk);
+        }
+        return 0;
+}
+
+/* This function increments the reference count on the clock and enables the
+ * clock if not already enabled. The parent clock tree is recursively enabled
+ */
+int clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        if (clk == NULL || IS_ERR(clk))
+                return -EINVAL;
+
+        mutex_lock(&clocks_mutex);
+        ret = __clk_enable(clk);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+/* This function decrements the reference count on the clock and disables
+ * the clock when reference count is 0. The parent clock tree is
+ * recursively disabled
+ */
+void clk_disable(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return;
+
+        mutex_lock(&clocks_mutex);
+        __clk_disable(clk);
+        mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL(clk_disable);
+
+/* Retrieve the *current* clock rate. If the clock itself
+ * does not provide a special calculation routine, ask
+ * its parent and so on, until one is able to return
+ * a valid clock rate
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (clk == NULL || IS_ERR(clk))
+                return 0UL;
+
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+
+        return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/* Round the requested clock rate to the nearest supported
+ * rate that is less than or equal to the requested rate.
+ * This is dependent on the clock's current parent.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
+                return 0;
+
+        return clk->round_rate(clk, rate);
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+/* Set the clock to the requested clock rate. The rate must
+ * match a supported rate exactly based on what clk_round_rate returns
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EINVAL;
+
+        if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
+                return ret;
+
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_rate(clk, rate);
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+/* Set the clock's parent to another clock source */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        int ret = -EINVAL;
+        struct clk *old;
+
+        if (clk == NULL || IS_ERR(clk) || parent == NULL ||
+            IS_ERR(parent) || clk->set_parent == NULL)
+                return ret;
+
+        if (clk->usecount)
+                clk_enable(parent);
+
+        mutex_lock(&clocks_mutex);
+        ret = clk->set_parent(clk, parent);
+        if (ret == 0) {
+                old = clk->parent;
+                clk->parent = parent;
+        } else {
+                old = parent;
+        }
+        mutex_unlock(&clocks_mutex);
+
+        if (clk->usecount)
+                clk_disable(old);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+/* Retrieve the clock's parent clock source */
+struct clk *clk_get_parent(struct clk *clk)
+{
+        struct clk *ret = NULL;
+
+        if (clk == NULL || IS_ERR(clk))
+                return ret;
+
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
new file mode 100644
index 000000000000..d0f49fc0abb5
--- /dev/null
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx23.h>
+#include <mach/devices-common.h>
+
+extern const struct mxs_duart_data mx23_duart_data __initconst;
+#define mx23_add_duart() \
+        mxs_add_duart(&mx23_duart_data)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
new file mode 100644
index 000000000000..00b736c434ba
--- /dev/null
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+
+extern const struct mxs_duart_data mx28_duart_data __initconst;
+#define mx28_add_duart() \
+        mxs_add_duart(&mx28_duart_data)
+
+extern const struct mxs_fec_data mx28_fec_data[] __initconst;
+#define mx28_add_fec(id, pdata) \
+        mxs_add_fec(&mx28_fec_data[id], pdata)
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
new file mode 100644
index 000000000000..6b60f02ca2e3
--- /dev/null
+++ b/arch/arm/mach-mxs/devices.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <mach/common.h>
+
+struct platform_device *__init mxs_add_platform_device_dmamask(
+                const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data, u64 dmamask)
+{
+        int ret = -ENOMEM;
+        struct platform_device *pdev;
+
+        pdev = platform_device_alloc(name, id);
+        if (!pdev)
+                goto err;
+
+        if (dmamask) {
+                /*
+                 * This memory isn't freed when the device is put,
+                 * I don't have a nice idea for that though.  Conceptually
+                 * dma_mask in struct device should not be a pointer.
+                 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
+                 */
+                pdev->dev.dma_mask =
+                        kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
+                if (!pdev->dev.dma_mask)
+                        /* ret is still -ENOMEM; */
+                        goto err;
+
+                *pdev->dev.dma_mask = dmamask;
+                pdev->dev.coherent_dma_mask = dmamask;
+        }
+
+        if (res) {
+                ret = platform_device_add_resources(pdev, res, num_resources);
+                if (ret)
+                        goto err;
+        }
+
+        if (data) {
+                ret = platform_device_add_data(pdev, data, size_data);
+                if (ret)
+                        goto err;
+        }
+
+        ret = platform_device_add(pdev);
+        if (ret) {
+err:
+                platform_device_put(pdev);
+                return ERR_PTR(ret);
+        }
+
+        return pdev;
+}
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
new file mode 100644
index 000000000000..a35a2dc55395
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -0,0 +1,5 @@
+config MXS_HAVE_PLATFORM_DUART
+        bool
+
+config MXS_HAVE_PLATFORM_FEC
+        bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
new file mode 100644
index 000000000000..4b5266a3e6d9
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_MXS_HAVE_PLATFORM_DUART) += platform-duart.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
diff --git a/arch/arm/mach-mxs/devices/platform-duart.c b/arch/arm/mach-mxs/devices/platform-duart.c
new file mode 100644
index 000000000000..2fe0df5b0aad
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-duart.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+
+#define mxs_duart_data_entry(soc)                                       \
+        {                                                               \
+                .iobase = soc ## _DUART_BASE_ADDR,                      \
+                .irq = soc ## _INT_DUART,                               \
+        }
+
+#ifdef CONFIG_SOC_IMX23
+const struct mxs_duart_data mx23_duart_data __initconst =
+        mxs_duart_data_entry(MX23);
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_duart_data mx28_duart_data __initconst =
+        mxs_duart_data_entry(MX28);
+#endif
+
+struct platform_device *__init mxs_add_duart(
+                const struct mxs_duart_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return mxs_add_platform_device("mxs-duart", 0, res, ARRAY_SIZE(res),
+                                        NULL, 0);
+}
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
new file mode 100644
index 000000000000..c08168cf3dec
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-fec.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/mx28.h>
+#include <mach/devices-common.h>
+
+#define mxs_fec_data_entry_single(soc, _id)                             \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR,        \
+                .irq = soc ## _INT_ENET_MAC ## _id,                     \
+        }
+
+#define mxs_fec_data_entry(soc, _id)                                    \
+        [_id] = mxs_fec_data_entry_single(soc, _id)
+
+#ifdef CONFIG_SOC_IMX28
+const struct mxs_fec_data mx28_fec_data[] __initconst = {
+#define mx28_fec_data_entry(_id)                                        \
+        mxs_fec_data_entry(MX28, _id)
+        mx28_fec_data_entry(0),
+        mx28_fec_data_entry(1),
+};
+#endif
+
+struct platform_device *__init mxs_add_fec(
+                const struct mxs_fec_data *data,
+                const struct fec_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_16K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return mxs_add_platform_device("fec", data->id,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
new file mode 100644
index 000000000000..d7ad7a61366d
--- /dev/null
+++ b/arch/arm/mach-mxs/gpio.c
@@ -0,0 +1,325 @@
+/*
+ * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * Based on code from Freescale,
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <asm-generic/bug.h>
+
+#include "gpio.h"
+
+static struct mxs_gpio_port *mxs_gpio_ports;
+static int gpio_table_size;
+
+#define PINCTRL_DOUT(n)         ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
+#define PINCTRL_DIN(n)          ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
+#define PINCTRL_DOE(n)          ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
+#define PINCTRL_PIN2IRQ(n)      ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
+#define PINCTRL_IRQEN(n)        ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
+#define PINCTRL_IRQLEV(n)       ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
+#define PINCTRL_IRQPOL(n)       ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
+#define PINCTRL_IRQSTAT(n)      ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
+
+#define GPIO_INT_FALL_EDGE      0x0
+#define GPIO_INT_LOW_LEV        0x1
+#define GPIO_INT_RISE_EDGE      0x2
+#define GPIO_INT_HIGH_LEV       0x3
+#define GPIO_INT_LEV_MASK       (1 << 0)
+#define GPIO_INT_POL_MASK       (1 << 1)
+
+/* Note: This driver assumes 32 GPIOs are handled in one register */
+
+static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
+{
+        __mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id));
+}
+
+static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
+                                int enable)
+{
+        if (enable) {
+                __mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id));
+                __mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id));
+        } else {
+                __mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id));
+        }
+}
+
+static void mxs_gpio_ack_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
+}
+
+static void mxs_gpio_mask_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
+}
+
+static void mxs_gpio_unmask_irq(u32 irq)
+{
+        u32 gpio = irq_to_gpio(irq);
+        set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
+}
+
+static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
+
+static int mxs_gpio_set_irq_type(u32 irq, u32 type)
+{
+        u32 gpio = irq_to_gpio(irq);
+        u32 pin_mask = 1 << (gpio & 31);
+        struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
+        void __iomem *pin_addr;
+        int edge;
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                edge = GPIO_INT_RISE_EDGE;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                edge = GPIO_INT_FALL_EDGE;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                edge = GPIO_INT_LOW_LEV;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                edge = GPIO_INT_HIGH_LEV;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* set level or edge */
+        pin_addr = port->base + PINCTRL_IRQLEV(port->id);
+        if (edge & GPIO_INT_LEV_MASK)
+                __mxs_setl(pin_mask, pin_addr);
+        else
+                __mxs_clrl(pin_mask, pin_addr);
+
+        /* set polarity */
+        pin_addr = port->base + PINCTRL_IRQPOL(port->id);
+        if (edge & GPIO_INT_POL_MASK)
+                __mxs_setl(pin_mask, pin_addr);
+        else
+                __mxs_clrl(pin_mask, pin_addr);
+
+        clear_gpio_irqstatus(port, gpio & 0x1f);
+
+        return 0;
+}
+
+/* MXS has one interrupt *per* gpio port */
+static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        u32 irq_stat;
+        struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq);
+        u32 gpio_irq_no_base = port->virtual_irq_start;
+
+        irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
+                        __raw_readl(port->base + PINCTRL_IRQEN(port->id));
+
+        while (irq_stat != 0) {
+                int irqoffset = fls(irq_stat) - 1;
+                generic_handle_irq(gpio_irq_no_base + irqoffset);
+                irq_stat &= ~(1 << irqoffset);
+        }
+}
+
+/*
+ * Set interrupt number "irq" in the GPIO as a wake-up source.
+ * While system is running, all registered GPIO interrupts need to have
+ * wake-up enabled. When system is suspended, only selected GPIO interrupts
+ * need to have wake-up enabled.
+ * @param  irq          interrupt source number
+ * @param  enable       enable as wake-up if equal to non-zero
+ * @return       This function returns 0 on success.
+ */
+static int mxs_gpio_set_wake_irq(u32 irq, u32 enable)
+{
+        u32 gpio = irq_to_gpio(irq);
+        u32 gpio_idx = gpio & 0x1f;
+        struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
+
+        if (enable) {
+                if (port->irq_high && (gpio_idx >= 16))
+                        enable_irq_wake(port->irq_high);
+                else
+                        enable_irq_wake(port->irq);
+        } else {
+                if (port->irq_high && (gpio_idx >= 16))
+                        disable_irq_wake(port->irq_high);
+                else
+                        disable_irq_wake(port->irq);
+        }
+
+        return 0;
+}
+
+static struct irq_chip gpio_irq_chip = {
+        .ack = mxs_gpio_ack_irq,
+        .mask = mxs_gpio_mask_irq,
+        .unmask = mxs_gpio_unmask_irq,
+        .set_type = mxs_gpio_set_irq_type,
+        .set_wake = mxs_gpio_set_wake_irq,
+};
+
+static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
+                                int dir)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+        void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
+
+        if (dir)
+                __mxs_setl(1 << offset, pin_addr);
+        else
+                __mxs_clrl(1 << offset, pin_addr);
+}
+
+static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+
+        return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
+}
+
+static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+        void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
+
+        if (value)
+                __mxs_setl(1 << offset, pin_addr);
+        else
+                __mxs_clrl(1 << offset, pin_addr);
+}
+
+static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct mxs_gpio_port *port =
+                container_of(chip, struct mxs_gpio_port, chip);
+
+        return port->virtual_irq_start + offset;
+}
+
+static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        mxs_set_gpio_direction(chip, offset, 0);
+        return 0;
+}
+
+static int mxs_gpio_direction_output(struct gpio_chip *chip,
+                                     unsigned offset, int value)
+{
+        mxs_gpio_set(chip, offset, value);
+        mxs_set_gpio_direction(chip, offset, 1);
+        return 0;
+}
+
+int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
+{
+        int i, j;
+
+        /* save for local usage */
+        mxs_gpio_ports = port;
+        gpio_table_size = cnt;
+
+        pr_info("MXS GPIO hardware\n");
+
+        for (i = 0; i < cnt; i++) {
+                /* disable the interrupt and clear the status */
+                __raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
+                __raw_writel(0, port[i].base + PINCTRL_IRQEN(i));
+
+                /* clear address has to be used to clear IRQSTAT bits */
+                __mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i));
+
+                for (j = port[i].virtual_irq_start;
+                        j < port[i].virtual_irq_start + 32; j++) {
+                        set_irq_chip(j, &gpio_irq_chip);
+                        set_irq_handler(j, handle_level_irq);
+                        set_irq_flags(j, IRQF_VALID);
+                }
+
+                /* setup one handler for each entry */
+                set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler);
+                set_irq_data(port[i].irq, &port[i]);
+
+                /* register gpio chip */
+                port[i].chip.direction_input = mxs_gpio_direction_input;
+                port[i].chip.direction_output = mxs_gpio_direction_output;
+                port[i].chip.get = mxs_gpio_get;
+                port[i].chip.set = mxs_gpio_set;
+                port[i].chip.to_irq = mxs_gpio_to_irq;
+                port[i].chip.base = i * 32;
+                port[i].chip.ngpio = 32;
+
+                /* its a serious configuration bug when it fails */
+                BUG_ON(gpiochip_add(&port[i].chip) < 0);
+        }
+
+        return 0;
+}
+
+#define DEFINE_MXS_GPIO_PORT(soc, _id)                                  \
+        {                                                               \
+                .chip.label = "gpio-" #_id,                             \
+                .id = _id,                                              \
+                .irq = soc ## _INT_GPIO ## _id,                         \
+                .base = soc ## _IO_ADDRESS(                             \
+                                soc ## _PINCTRL ## _BASE_ADDR),         \
+                .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32,   \
+        }
+
+#define DEFINE_REGISTER_FUNCTION(prefix)                                \
+int __init prefix ## _register_gpios(void)                              \
+{                                                                       \
+        return mxs_gpio_init(prefix ## _gpio_ports,                     \
+                        ARRAY_SIZE(prefix ## _gpio_ports));             \
+}
+
+#ifdef CONFIG_SOC_IMX23
+static struct mxs_gpio_port mx23_gpio_ports[] = {
+        DEFINE_MXS_GPIO_PORT(MX23, 0),
+        DEFINE_MXS_GPIO_PORT(MX23, 1),
+        DEFINE_MXS_GPIO_PORT(MX23, 2),
+};
+DEFINE_REGISTER_FUNCTION(mx23)
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+static struct mxs_gpio_port mx28_gpio_ports[] = {
+        DEFINE_MXS_GPIO_PORT(MX28, 0),
+        DEFINE_MXS_GPIO_PORT(MX28, 1),
+        DEFINE_MXS_GPIO_PORT(MX28, 2),
+        DEFINE_MXS_GPIO_PORT(MX28, 3),
+        DEFINE_MXS_GPIO_PORT(MX28, 4),
+};
+DEFINE_REGISTER_FUNCTION(mx28)
+#endif
diff --git a/arch/arm/mach-mxs/gpio.h b/arch/arm/mach-mxs/gpio.h
new file mode 100644
index 000000000000..005bb06630b1
--- /dev/null
+++ b/arch/arm/mach-mxs/gpio.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __MXS_GPIO_H__
+#define __MXS_GPIO_H__
+
+struct mxs_gpio_port {
+        void __iomem *base;
+        int id;
+        int irq;
+        int irq_high;
+        int virtual_irq_start;
+        struct gpio_chip chip;
+};
+
+int mxs_gpio_init(struct mxs_gpio_port*, int);
+
+#endif /* __MXS_GPIO_H__ */
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
new file mode 100644
index 000000000000..5dd43ba70058
--- /dev/null
+++ b/arch/arm/mach-mxs/icoll.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <mach/mxs.h>
+#include <mach/common.h>
+
+#define HW_ICOLL_VECTOR                         0x0000
+#define HW_ICOLL_LEVELACK                       0x0010
+#define HW_ICOLL_CTRL                           0x0020
+#define HW_ICOLL_INTERRUPTn_SET(n)              (0x0124 + (n) * 0x10)
+#define HW_ICOLL_INTERRUPTn_CLR(n)              (0x0128 + (n) * 0x10)
+#define BM_ICOLL_INTERRUPTn_ENABLE              0x00000004
+#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
+
+static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
+
+static void icoll_ack_irq(unsigned int irq)
+{
+        /*
+         * The Interrupt Collector is able to prioritize irqs.
+         * Currently only level 0 is used. So acking can use
+         * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
+         */
+        __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
+                        icoll_base + HW_ICOLL_LEVELACK);
+}
+
+static void icoll_mask_irq(unsigned int irq)
+{
+        __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+                        icoll_base + HW_ICOLL_INTERRUPTn_CLR(irq));
+}
+
+static void icoll_unmask_irq(unsigned int irq)
+{
+        __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
+                        icoll_base + HW_ICOLL_INTERRUPTn_SET(irq));
+}
+
+static struct irq_chip mxs_icoll_chip = {
+        .ack = icoll_ack_irq,
+        .mask = icoll_mask_irq,
+        .unmask = icoll_unmask_irq,
+};
+
+void __init icoll_init_irq(void)
+{
+        int i;
+
+        /*
+         * Interrupt Collector reset, which initializes the priority
+         * for each irq to level 0.
+         */
+        mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
+
+        for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
+                set_irq_chip(i, &mxs_icoll_chip);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/mach-mxs/include/mach/clkdev.h b/arch/arm/mach-mxs/include/mach/clkdev.h
new file mode 100644
index 000000000000..3a8f2e3a6309
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_MXS_CLKDEV_H__
+#define __MACH_MXS_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h
new file mode 100644
index 000000000000..041e276d8a32
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/clock.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_MXS_CLOCK_H__
+#define __MACH_MXS_CLOCK_H__
+
+#ifndef __ASSEMBLY__
+#include <linux/list.h>
+
+struct module;
+
+struct clk {
+        int id;
+        /* Source clock this clk depends on */
+        struct clk *parent;
+        /* Secondary clock to enable/disable with this clock */
+        struct clk *secondary;
+        /* Reference count of clock enable/disable */
+        __s8 usecount;
+        /* Register bit position for clock's enable/disable control. */
+        u8 enable_shift;
+        /* Register address for clock's enable/disable control. */
+        void __iomem *enable_reg;
+        u32 flags;
+        /* get the current clock rate (always a fresh value) */
+        unsigned long (*get_rate) (struct clk *);
+        /* Function ptr to set the clock to a new rate. The rate must match a
+           supported rate returned from round_rate. Leave blank if clock is not
+           programmable */
+        int (*set_rate) (struct clk *, unsigned long);
+        /* Function ptr to round the requested clock rate to the nearest
+           supported rate that is less than or equal to the requested rate. */
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        /* Function ptr to enable the clock. Leave blank if clock can not
+           be gated. */
+        int (*enable) (struct clk *);
+        /* Function ptr to disable the clock. Leave blank if clock can not
+           be gated. */
+        void (*disable) (struct clk *);
+        /* Function ptr to set the parent clock of the clock. */
+        int (*set_parent) (struct clk *, struct clk *);
+};
+
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __MACH_MXS_CLOCK_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
new file mode 100644
index 000000000000..59133eb3cc96
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_MXS_COMMON_H__
+#define __MACH_MXS_COMMON_H__
+
+struct clk;
+
+extern int mxs_reset_block(void __iomem *);
+extern void mxs_timer_init(struct clk *, int);
+
+extern int mx23_register_gpios(void);
+extern int mx23_clocks_init(void);
+extern void mx23_map_io(void);
+extern void mx23_init_irq(void);
+
+extern int mx28_register_gpios(void);
+extern int mx28_clocks_init(void);
+extern void mx28_map_io(void);
+extern void mx28_init_irq(void);
+
+extern void icoll_init_irq(void);
+
+#endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S
new file mode 100644
index 000000000000..79650a1ad78d
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/debug-macro.S
@@ -0,0 +1,38 @@
+/* arch/arm/mach-mxs/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+
+#ifdef CONFIG_SOC_IMX23
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
+#endif
+#define UART_PADDR      MX23_DUART_BASE_ADDR
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
+#endif
+#define UART_PADDR      MX28_DUART_BASE_ADDR
+#endif
+
+#define UART_VADDR      MXS_IO_ADDRESS(UART_PADDR)
+
+                .macro  addruart, rp, rv
+                ldr     \rp, =UART_PADDR        @ physical
+                ldr     \rv, =UART_VADDR        @ virtual
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
new file mode 100644
index 000000000000..3da48d4d3273
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+
+struct platform_device *mxs_add_platform_device_dmamask(
+                const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data, u64 dmamask);
+
+static inline struct platform_device *mxs_add_platform_device(
+                const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data)
+{
+        return mxs_add_platform_device_dmamask(
+                        name, id, res, num_resources, data, size_data, 0);
+}
+
+/* duart */
+struct mxs_duart_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init mxs_add_duart(
+                const struct mxs_duart_data *data);
+
+/* fec */
+#include <linux/fec.h>
+struct mxs_fec_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init mxs_add_fec(
+                const struct mxs_fec_data *data,
+                const struct fec_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/mach-mxs/include/mach/entry-macro.S
new file mode 100644
index 000000000000..9f0da12e657a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/entry-macro.S
@@ -0,0 +1,41 @@
+/*
+ * Low-level IRQ helper macros for Freescale MXS-based
+ *
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <mach/mxs.h>
+
+#define MXS_ICOLL_VBASE         MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR)
+#define HW_ICOLL_STAT_OFFSET    0x70
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqnr, [\base, #HW_ICOLL_STAT_OFFSET]
+        cmp     \irqnr, #0x7F
+        strne   \irqnr, [\base]
+        moveqs  \irqnr, #0
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =MXS_ICOLL_VBASE
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h
new file mode 100644
index 000000000000..828ccccb6aad
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/gpio.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_MXS_GPIO_H__
+#define __MACH_MXS_GPIO_H__
+
+#include <asm-generic/gpio.h>
+
+#define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
+
+/* use gpiolib dispatchers */
+#define gpio_get_value          __gpio_get_value
+#define gpio_set_value          __gpio_set_value
+#define gpio_cansleep           __gpio_cansleep
+#define gpio_to_irq             __gpio_to_irq
+
+#define irq_to_gpio(irq)        ((irq) - MXS_GPIO_IRQ_START)
+
+#endif /* __MACH_MXS_GPIO_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/hardware.h b/arch/arm/mach-mxs/include/mach/hardware.h
new file mode 100644
index 000000000000..53e89a09bf0d
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/hardware.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_MXS_HARDWARE_H__
+#define __MACH_MXS_HARDWARE_H__
+
+#ifdef __ASSEMBLER__
+#define IOMEM(addr)     (addr)
+#else
+#define IOMEM(addr)     ((void __force __iomem *)(addr))
+#endif
+
+#endif /* __MACH_MXS_HARDWARE_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/io.h b/arch/arm/mach-mxs/include/mach/io.h
new file mode 100644
index 000000000000..289b7227e072
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_MXS_IO_H__
+#define __MACH_MXS_IO_H__
+
+/* Allow IO space to be anywhere in the memory */
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* io address mapping macro */
+#define __io(a)         __typesafe_io(a)
+
+#define __mem_pci(a)    (a)
+
+#endif /* __MACH_MXS_IO_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
new file mode 100644
index 000000000000..94e5dd83cdb8
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MACH_IOMUX_MX23_H__
+#define __MACH_IOMUX_MX23_H__
+
+#include <mach/iomux.h>
+
+/*
+ * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux.h
+ *
+ *                                                                      BANK    PIN     MUX
+ */
+/* MUXSEL_0 */
+#define MX23_PAD_GPMI_D00__GPMI_D00             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D01__GPMI_D01             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D02__GPMI_D02             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D03__GPMI_D03             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D04__GPMI_D04             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D05__GPMI_D05             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D06__GPMI_D06             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D07__GPMI_D07             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D08__GPMI_D08             MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D09__GPMI_D09             MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D10__GPMI_D10             MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D11__GPMI_D11             MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D12__GPMI_D12             MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D13__GPMI_D13             MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D14__GPMI_D14             MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_D15__GPMI_D15             MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CLE__GPMI_CLE             MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_ALE__GPMI_ALE             MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE2N__GPMI_CE2N           MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY0__GPMI_RDY0           MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY1__GPMI_RDY1           MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY2__GPMI_RDY2           MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDY3__GPMI_RDY3           MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_WPN__GPMI_WPN             MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_WRN__GPMI_WRN             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_RDN__GPMI_RDN             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_CTS__AUART1_CTS         MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_RTS__AUART1_RTS         MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_RX__AUART1_RX           MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
+#define MX23_PAD_AUART1_TX__AUART1_TX           MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
+#define MX23_PAD_I2C_SCL__I2C_SCL               MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
+#define MX23_PAD_I2C_SDA__I2C_SDA               MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
+
+#define MX23_PAD_LCD_D00__LCD_D00               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D01__LCD_D01               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D02__LCD_D02               MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D03__LCD_D03               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D04__LCD_D04               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D05__LCD_D05               MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D06__LCD_D06               MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D07__LCD_D07               MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D08__LCD_D08               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D09__LCD_D09               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D10__LCD_D10               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D11__LCD_D11               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D12__LCD_D12               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D13__LCD_D13               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D14__LCD_D14               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D15__LCD_D15               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D16__LCD_D16               MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_D17__LCD_D17               MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_RESET__LCD_RESET           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_RS__LCD_RS                 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_WR__LCD_WR                 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_CS__LCD_CS                 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_DOTCK__LCD_DOTCK           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_ENABLE__LCD_ENABLE         MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_HSYNC__LCD_HSYNC           MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
+#define MX23_PAD_LCD_VSYNC__LCD_VSYNC           MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
+#define MX23_PAD_PWM0__PWM0                     MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
+#define MX23_PAD_PWM1__PWM1                     MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
+#define MX23_PAD_PWM2__PWM2                     MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
+#define MX23_PAD_PWM3__PWM3                     MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
+#define MX23_PAD_PWM4__PWM4                     MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
+
+#define MX23_PAD_SSP1_CMD__SSP1_CMD             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DETECT__SSP1_DETECT       MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA0__SSP1_DATA0         MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA1__SSP1_DATA1         MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA2__SSP1_DATA2         MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_DATA3__SSP1_DATA3         MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
+#define MX23_PAD_SSP1_SCK__SSP1_SCK             MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
+#define MX23_PAD_ROTARYA__ROTARYA               MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
+#define MX23_PAD_ROTARYB__ROTARYB               MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A00__EMI_A00               MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A01__EMI_A01               MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A02__EMI_A02               MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A03__EMI_A03               MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A04__EMI_A04               MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A05__EMI_A05               MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A06__EMI_A06               MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A07__EMI_A07               MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A08__EMI_A08               MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A09__EMI_A09               MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A10__EMI_A10               MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A11__EMI_A11               MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_A12__EMI_A12               MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_BA0__EMI_BA0               MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_BA1__EMI_BA1               MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CASN__EMI_CASN             MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CE0N__EMI_CE0N             MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CE1N__EMI_CE1N             MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE1N__GPMI_CE1N           MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
+#define MX23_PAD_GPMI_CE0N__GPMI_CE0N           MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CKE__EMI_CKE               MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_RASN__EMI_RASN             MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_WEN__EMI_WEN               MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
+
+#define MX23_PAD_EMI_D00__EMI_D00               MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D01__EMI_D01               MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D02__EMI_D02               MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D03__EMI_D03               MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D04__EMI_D04               MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D05__EMI_D05               MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D06__EMI_D06               MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D07__EMI_D07               MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D08__EMI_D08               MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D09__EMI_D09               MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D10__EMI_D10               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D11__EMI_D11               MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D12__EMI_D12               MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D13__EMI_D13               MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D14__EMI_D14               MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_D15__EMI_D15               MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQM0__EMI_DQM0             MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQM1__EMI_DQM1             MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQS0__EMI_DQS0             MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_DQS1__EMI_DQS1             MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CLK__EMI_CLK               MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
+#define MX23_PAD_EMI_CLKN__EMI_CLKN             MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
+
+/* MUXSEL_1 */
+#define MX23_PAD_GPMI_D00__LCD_D8               MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D01__LCD_D9               MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D02__LCD_D10              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D03__LCD_D11              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D04__LCD_D12              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D05__LCD_D13              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D06__LCD_D14              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D07__LCD_D15              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D08__LCD_D18              MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D09__LCD_D19              MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D10__LCD_D20              MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D11__LCD_D21              MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D12__LCD_D22              MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D13__LCD_D23              MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D14__AUART2_RX            MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_D15__AUART2_TX            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_CLE__LCD_D16              MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_ALE__LCD_D17              MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
+#define MX23_PAD_GPMI_CE2N__ATA_A2              MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_RTS__IR_CLK             MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_RX__IR_RX               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
+#define MX23_PAD_AUART1_TX__IR_TX               MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
+#define MX23_PAD_I2C_SCL__GPMI_RDY2             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
+#define MX23_PAD_I2C_SDA__GPMI_CE2N             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
+
+#define MX23_PAD_LCD_D00__ETM_DA8               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D01__ETM_DA9               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D02__ETM_DA10              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D03__ETM_DA11              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D04__ETM_DA12              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D05__ETM_DA13              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D06__ETM_DA14              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D07__ETM_DA15              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D08__ETM_DA0               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D09__ETM_DA1               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D10__ETM_DA2               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D11__ETM_DA3               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D12__ETM_DA4               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D13__ETM_DA5               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D14__ETM_DA6               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_D15__ETM_DA7               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_RESET__ETM_TCTL            MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_RS__ETM_TCLK               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_DOTCK__GPMI_RDY3           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_ENABLE__I2C_SCL            MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_HSYNC__I2C_SDA             MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
+#define MX23_PAD_LCD_VSYNC__LCD_BUSY            MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
+#define MX23_PAD_PWM0__ROTARYA                  MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
+#define MX23_PAD_PWM1__ROTARYB                  MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
+#define MX23_PAD_PWM2__GPMI_RDY3                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
+#define MX23_PAD_PWM3__ETM_TCTL                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
+#define MX23_PAD_PWM4__ETM_TCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
+
+#define MX23_PAD_SSP1_DETECT__GPMI_CE3N         MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DATA1__I2C_SCL            MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_1)
+#define MX23_PAD_SSP1_DATA2__I2C_SDA            MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
+#define MX23_PAD_ROTARYA__AUART2_RTS            MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
+#define MX23_PAD_ROTARYB__AUART2_CTS            MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_1)
+
+/* MUXSEL_2 */
+#define MX23_PAD_GPMI_D00__SSP2_DATA0           MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D01__SSP2_DATA1           MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D02__SSP2_DATA2           MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D03__SSP2_DATA3           MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D04__SSP2_DATA4           MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D05__SSP2_DATA5           MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D06__SSP2_DATA6           MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D07__SSP2_DATA7           MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D08__SSP1_DATA4           MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D09__SSP1_DATA5           MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D10__SSP1_DATA6           MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D11__SSP1_DATA7           MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_D15__GPMI_CE3N            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_RDY0__SSP2_DETECT         MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_RDY1__SSP2_CMD            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
+#define MX23_PAD_GPMI_WRN__SSP2_SCK             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_CTS__SSP1_DATA4         MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_RTS__SSP1_DATA5         MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_RX__SSP1_DATA6          MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
+#define MX23_PAD_AUART1_TX__SSP1_DATA7          MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
+#define MX23_PAD_I2C_SCL__AUART1_TX             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
+#define MX23_PAD_I2C_SDA__AUART1_RX             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
+
+#define MX23_PAD_LCD_D08__SAIF2_SDATA0          MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D09__SAIF1_SDATA0          MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK      MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D11__SAIF_LRCLK            MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D12__SAIF2_SDATA1          MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D13__SAIF2_SDATA2          MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D14__SAIF1_SDATA2          MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D15__SAIF1_SDATA1          MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
+#define MX23_PAD_LCD_RESET__GPMI_CE3N           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
+#define MX23_PAD_PWM0__DUART_RX                 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
+#define MX23_PAD_PWM1__DUART_TX                 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
+#define MX23_PAD_PWM3__AUART1_CTS               MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
+#define MX23_PAD_PWM4__AUART1_RTS               MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
+
+#define MX23_PAD_SSP1_CMD__JTAG_TDO             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DETECT__USB_OTG_ID        MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA0__JTAG_TDI           MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA1__JTAG_TCLK          MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA2__JTAG_RTCK          MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_DATA3__JTAG_TMS           MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_2)
+#define MX23_PAD_SSP1_SCK__JTAG_TRST            MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_2)
+#define MX23_PAD_ROTARYA__SPDIF                 MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_2)
+#define MX23_PAD_ROTARYB__GPMI_CE3N             MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
+
+/* MUXSEL_GPIO */
+#define MX23_PAD_GPMI_D00__GPO_0_0              MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D01__GPO_0_1              MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D02__GPO_0_2              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D03__GPO_0_3              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D04__GPO_0_4              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D05__GPO_0_5              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D06__GPO_0_6              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D07__GPO_0_7              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D08__GPO_0_8              MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D09__GPO_0_9              MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D10__GPO_0_10             MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D11__GPO_0_11             MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D12__GPO_0_12             MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D13__GPO_0_13             MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D14__GPO_0_14             MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_D15__GPO_0_15             MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CLE__GPO_0_16             MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_ALE__GPO_0_17             MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE2N__GPO_0_18            MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY0__GPO_0_19            MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY1__GPO_0_20            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY2__GPO_0_21            MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDY3__GPO_0_22            MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WPN__GPO_0_23             MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_WRN__GPO_0_24             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_RDN__GPO_0_25             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_CTS__GPO_0_26           MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RTS__GPO_0_27           MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_RX__GPO_0_28            MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_AUART1_TX__GPO_0_29            MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SCL__GPO_0_30              MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_I2C_SDA__GPO_0_31              MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
+
+#define MX23_PAD_LCD_D00__GPO_1_0               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D01__GPO_1_1               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D02__GPO_1_2               MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D03__GPO_1_3               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D04__GPO_1_4               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D05__GPO_1_5               MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D06__GPO_1_6               MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D07__GPO_1_7               MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D08__GPO_1_8               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D09__GPO_1_9               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D10__GPO_1_10              MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D11__GPO_1_11              MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D12__GPO_1_12              MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D13__GPO_1_13              MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D14__GPO_1_14              MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D15__GPO_1_15              MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D16__GPO_1_16              MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_D17__GPO_1_17              MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RESET__GPO_1_18            MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_RS__GPO_1_19               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_WR__GPO_1_20               MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_CS__GPO_1_21               MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_DOTCK__GPO_1_22            MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_ENABLE__GPO_1_23           MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_HSYNC__GPO_1_24            MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_LCD_VSYNC__GPO_1_25            MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM0__GPO_1_26                 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM1__GPO_1_27                 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM2__GPO_1_28                 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM3__GPO_1_29                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_PWM4__GPO_1_30                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+
+#define MX23_PAD_SSP1_CMD__GPO_2_0              MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DETECT__GPO_2_1           MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA0__GPO_2_2            MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA1__GPO_2_3            MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA2__GPO_2_4            MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_DATA3__GPO_2_5            MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX23_PAD_SSP1_SCK__GPO_2_6              MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYA__GPO_2_7               MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX23_PAD_ROTARYB__GPO_2_8               MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A00__GPO_2_9               MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A01__GPO_2_10              MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A02__GPO_2_11              MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A03__GPO_2_12              MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A04__GPO_2_13              MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A05__GPO_2_14              MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A06__GPO_2_15              MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A07__GPO_2_16              MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A08__GPO_2_17              MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A09__GPO_2_18              MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A10__GPO_2_19              MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A11__GPO_2_20              MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_A12__GPO_2_21              MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA0__GPO_2_22              MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_BA1__GPO_2_23              MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CASN__GPO_2_24             MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE0N__GPO_2_25             MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CE1N__GPO_2_26             MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE1N__GPO_2_27            MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+#define MX23_PAD_GPMI_CE0N__GPO_2_28            MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_CKE__GPO_2_29              MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_RASN__GPO_2_30             MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
+#define MX23_PAD_EMI_WEN__GPO_2_31              MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
+
+#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h
new file mode 100644
index 000000000000..f50fefd10520
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx28.h
@@ -0,0 +1,537 @@
+/*
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MACH_IOMUX_MX28_H__
+#define __MACH_IOMUX_MX28_H__
+
+#include <mach/iomux.h>
+
+/*
+ * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux.h
+ *
+ *                                                                      BANK    PIN     MUX
+ */
+/* MUXSEL_0 */
+#define MX28_PAD_GPMI_D00__GPMI_D0                      MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D01__GPMI_D1                      MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D02__GPMI_D2                      MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D03__GPMI_D3                      MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D04__GPMI_D4                      MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D05__GPMI_D5                      MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D06__GPMI_D6                      MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_D07__GPMI_D7                      MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE0N__GPMI_CE0N                   MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE1N__GPMI_CE1N                   MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE2N__GPMI_CE2N                   MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CE3N__GPMI_CE3N                   MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY0__GPMI_READY0                 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY1__GPMI_READY1                 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY2__GPMI_READY2                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDY3__GPMI_READY3                 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RDN__GPMI_RDN                     MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_WRN__GPMI_WRN                     MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_ALE__GPMI_ALE                     MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_CLE__GPMI_CLE                     MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
+#define MX28_PAD_GPMI_RESETN__GPMI_RESETN               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
+
+#define MX28_PAD_LCD_D00__LCD_D0                        MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D01__LCD_D1                        MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D02__LCD_D2                        MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D03__LCD_D3                        MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D04__LCD_D4                        MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D05__LCD_D5                        MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D06__LCD_D6                        MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D07__LCD_D7                        MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D08__LCD_D8                        MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D09__LCD_D9                        MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D10__LCD_D10                       MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D11__LCD_D11                       MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D12__LCD_D12                       MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D13__LCD_D13                       MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D14__LCD_D14                       MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D15__LCD_D15                       MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D16__LCD_D16                       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D17__LCD_D17                       MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D18__LCD_D18                       MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D19__LCD_D19                       MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D20__LCD_D20                       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D21__LCD_D21                       MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D22__LCD_D22                       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_D23__LCD_D23                       MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RD_E__LCD_RD_E                     MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN                 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RS__LCD_RS                         MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_CS__LCD_CS                         MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_VSYNC__LCD_VSYNC                   MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_HSYNC__LCD_HSYNC                   MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_ENABLE__LCD_ENABLE                 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
+
+#define MX28_PAD_SSP0_DATA0__SSP0_D0                    MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA1__SSP0_D1                    MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA2__SSP0_D2                    MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA3__SSP0_D3                    MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA4__SSP0_D4                    MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA5__SSP0_D5                    MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA6__SSP0_D6                    MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DATA7__SSP0_D7                    MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_CMD__SSP0_CMD                     MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT          MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
+#define MX28_PAD_SSP0_SCK__SSP0_SCK                     MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_SCK__SSP1_SCK                     MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_CMD__SSP1_CMD                     MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_DATA0__SSP1_D0                    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
+#define MX28_PAD_SSP1_DATA3__SSP1_D3                    MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SCK__SSP2_SCK                     MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_MOSI__SSP2_CMD                    MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_MISO__SSP2_D0                     MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS0__SSP2_D3                      MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS1__SSP2_D4                      MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
+#define MX28_PAD_SSP2_SS2__SSP2_D5                      MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_SCK__SSP3_SCK                     MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_MOSI__SSP3_CMD                    MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_MISO__SSP3_D0                     MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
+#define MX28_PAD_SSP3_SS0__SSP3_D3                      MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
+
+#define MX28_PAD_AUART0_RX__AUART0_RX                   MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_TX__AUART0_TX                   MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_CTS__AUART0_CTS                 MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
+#define MX28_PAD_AUART0_RTS__AUART0_RTS                 MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_RX__AUART1_RX                   MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_TX__AUART1_TX                   MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_CTS__AUART1_CTS                 MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
+#define MX28_PAD_AUART1_RTS__AUART1_RTS                 MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_RX__AUART2_RX                   MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_TX__AUART2_TX                   MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_CTS__AUART2_CTS                 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
+#define MX28_PAD_AUART2_RTS__AUART2_RTS                 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_RX__AUART3_RX                   MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_TX__AUART3_TX                   MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_CTS__AUART3_CTS                 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
+#define MX28_PAD_AUART3_RTS__AUART3_RTS                 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
+#define MX28_PAD_PWM0__PWM_0                            MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
+#define MX28_PAD_PWM1__PWM_1                            MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
+#define MX28_PAD_PWM2__PWM_2                            MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK                 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK               MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK             MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0             MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
+#define MX28_PAD_I2C0_SCL__I2C0_SCL                     MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
+#define MX28_PAD_I2C0_SDA__I2C0_SDA                     MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
+#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0             MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
+#define MX28_PAD_SPDIF__SPDIF_TX                        MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
+#define MX28_PAD_PWM3__PWM_3                            MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
+#define MX28_PAD_PWM4__PWM_4                            MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
+#define MX28_PAD_LCD_RESET__LCD_RESET                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
+
+#define MX28_PAD_ENET0_MDC__ENET0_MDC                   MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_MDIO__ENET0_MDIO                 MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN               MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD0__ENET0_RXD0                 MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD1__ENET0_RXD1                 MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK             MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN               MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD0__ENET0_TXD0                 MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD1__ENET0_TXD1                 MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD2__ENET0_RXD2                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RXD3__ENET0_RXD3                 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD2__ENET0_TXD2                 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_TXD3__ENET0_TXD3                 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK             MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_COL__ENET0_COL                   MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
+#define MX28_PAD_ENET0_CRS__ENET0_CRS                   MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
+#define MX28_PAD_ENET_CLK__CLKCTRL_ENET                 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
+#define MX28_PAD_JTAG_RTCK__JTAG_RTCK                   MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
+
+#define MX28_PAD_EMI_D00__EMI_DATA0                     MXS_IOMUX_PAD_NAKED(5,  0, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D01__EMI_DATA1                     MXS_IOMUX_PAD_NAKED(5,  1, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D02__EMI_DATA2                     MXS_IOMUX_PAD_NAKED(5,  2, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D03__EMI_DATA3                     MXS_IOMUX_PAD_NAKED(5,  3, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D04__EMI_DATA4                     MXS_IOMUX_PAD_NAKED(5,  4, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D05__EMI_DATA5                     MXS_IOMUX_PAD_NAKED(5,  5, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D06__EMI_DATA6                     MXS_IOMUX_PAD_NAKED(5,  6, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D07__EMI_DATA7                     MXS_IOMUX_PAD_NAKED(5,  7, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D08__EMI_DATA8                     MXS_IOMUX_PAD_NAKED(5,  8, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D09__EMI_DATA9                     MXS_IOMUX_PAD_NAKED(5,  9, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D10__EMI_DATA10                    MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D11__EMI_DATA11                    MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D12__EMI_DATA12                    MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D13__EMI_DATA13                    MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D14__EMI_DATA14                    MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_D15__EMI_DATA15                    MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_ODT0__EMI_ODT0                     MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQM0__EMI_DQM0                     MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_ODT1__EMI_ODT1                     MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQM1__EMI_DQM1                     MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CLK__EMI_CLK                       MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQS0__EMI_DQS0                     MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DQS1__EMI_DQS1                     MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN             MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
+
+#define MX28_PAD_EMI_A00__EMI_ADDR0                     MXS_IOMUX_PAD_NAKED(6,  0, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A01__EMI_ADDR1                     MXS_IOMUX_PAD_NAKED(6,  1, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A02__EMI_ADDR2                     MXS_IOMUX_PAD_NAKED(6,  2, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A03__EMI_ADDR3                     MXS_IOMUX_PAD_NAKED(6,  3, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A04__EMI_ADDR4                     MXS_IOMUX_PAD_NAKED(6,  4, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A05__EMI_ADDR5                     MXS_IOMUX_PAD_NAKED(6,  5, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A06__EMI_ADDR6                     MXS_IOMUX_PAD_NAKED(6,  6, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A07__EMI_ADDR7                     MXS_IOMUX_PAD_NAKED(6,  7, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A08__EMI_ADDR8                     MXS_IOMUX_PAD_NAKED(6,  8, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A09__EMI_ADDR9                     MXS_IOMUX_PAD_NAKED(6,  9, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A10__EMI_ADDR10                    MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A11__EMI_ADDR11                    MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A12__EMI_ADDR12                    MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A13__EMI_ADDR13                    MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_A14__EMI_ADDR14                    MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA0__EMI_BA0                       MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA1__EMI_BA1                       MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_BA2__EMI_BA2                       MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CASN__EMI_CASN                     MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_RASN__EMI_RASN                     MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_WEN__EMI_WEN                       MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CE0N__EMI_CE0N                     MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CE1N__EMI_CE1N                     MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
+#define MX28_PAD_EMI_CKE__EMI_CKE                       MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
+
+/* MUXSEL_1 */
+#define MX28_PAD_GPMI_D00__SSP1_D0                      MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D01__SSP1_D1                      MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D02__SSP1_D2                      MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D03__SSP1_D3                      MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D04__SSP1_D4                      MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D05__SSP1_D5                      MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D06__SSP1_D6                      MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_D07__SSP1_D7                      MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE0N__SSP3_D0                     MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE1N__SSP3_D3                     MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE2N__CAN1_TX                     MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CE3N__CAN1_RX                     MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY1__SSP1_CMD                    MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY2__CAN0_TX                     MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDY3__CAN0_RX                     MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RDN__SSP3_SCK                     MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_WRN__SSP1_SCK                     MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_ALE__SSP3_D1                      MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_CLE__SSP3_D2                      MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
+#define MX28_PAD_GPMI_RESETN__SSP3_CMD                  MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
+
+#define MX28_PAD_LCD_D03__ETM_DA8                       MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D04__ETM_DA9                       MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D08__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D09__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT         MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN          MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT         MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN          MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RD_E__LCD_VSYNC                    MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC                  MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RS__LCD_DOTCLK                     MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_CS__LCD_ENABLE                     MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1                MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
+
+#define MX28_PAD_SSP0_DATA4__SSP2_D0                    MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA5__SSP2_D3                    MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA6__SSP2_CMD                   MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_1)
+#define MX28_PAD_SSP0_DATA7__SSP2_SCK                   MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_SCK__SSP2_D1                      MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_CMD__SSP2_D2                      MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_DATA0__SSP2_D6                    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
+#define MX28_PAD_SSP1_DATA3__SSP2_D7                    MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SCK__AUART2_RX                    MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_MOSI__AUART2_TX                   MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_MISO__AUART3_RX                   MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS0__AUART3_TX                    MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS1__SSP2_D1                      MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
+#define MX28_PAD_SSP2_SS2__SSP2_D2                      MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_SCK__AUART4_TX                    MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_MOSI__AUART4_RX                   MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_MISO__AUART4_RTS                  MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
+#define MX28_PAD_SSP3_SS0__AUART4_CTS                   MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
+
+#define MX28_PAD_AUART0_RX__I2C0_SCL                    MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_TX__I2C0_SDA                    MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_CTS__AUART4_RX                  MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_1)
+#define MX28_PAD_AUART0_RTS__AUART4_TX                  MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT            MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT            MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT           MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_1)
+#define MX28_PAD_AUART1_RTS__USB0_ID                    MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_RX__SSP3_D1                     MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_TX__SSP3_D2                     MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_CTS__I2C1_SCL                   MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
+#define MX28_PAD_AUART2_RTS__I2C1_SDA                   MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_RX__CAN0_TX                     MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_TX__CAN0_RX                     MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_CTS__CAN1_TX                    MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
+#define MX28_PAD_AUART3_RTS__CAN1_RX                    MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
+#define MX28_PAD_PWM0__I2C1_SCL                         MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
+#define MX28_PAD_PWM1__I2C1_SDA                         MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
+#define MX28_PAD_PWM2__USB0_ID                          MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_MCLK__PWM_3                      MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_LRCLK__PWM_4                     MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_BITCLK__PWM_5                    MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF0_SDATA0__PWM_6                    MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
+#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA               MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
+#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB               MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
+#define MX28_PAD_SAIF1_SDATA0__PWM_7                    MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
+#define MX28_PAD_LCD_RESET__LCD_VSYNC                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
+
+#define MX28_PAD_ENET0_MDC__GPMI_CE4N                   MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_MDIO__GPMI_CE5N                  MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N                 MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD0__GPMI_CE7N                  MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD1__GPMI_READY4                MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER            MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TX_EN__GPMI_READY5               MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD0__GPMI_READY6                MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD1__GPMI_READY7                MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD2__ENET1_RXD0                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RXD3__ENET1_RXD1                 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD2__ENET1_TXD0                 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_TXD3__ENET1_TXD1                 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER              MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_COL__ENET1_TX_EN                 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
+#define MX28_PAD_ENET0_CRS__ENET1_RX_EN                 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
+
+/* MUXSEL_2 */
+#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER                 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK                  MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY0__USB0_ID                     MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER               MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_ALE__SSP3_D4                      MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
+#define MX28_PAD_GPMI_CLE__SSP3_D5                      MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_LCD_D00__ETM_DA0                       MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D01__ETM_DA1                       MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D02__ETM_DA2                       MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D03__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D04__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D05__ETM_DA5                       MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D06__ETM_DA6                       MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D07__ETM_DA7                       MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D08__ETM_DA8                       MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D09__ETM_DA9                       MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D10__ETM_DA10                      MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D11__ETM_DA11                      MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D12__ETM_DA12                      MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D13__ETM_DA13                      MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D14__ETM_DA14                      MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D15__ETM_DA15                      MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D16__ETM_DA7                       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D17__ETM_DA6                       MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D18__ETM_DA5                       MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D19__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D20__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D21__ETM_DA2                       MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D22__ETM_DA1                       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_D23__ETM_DA0                       MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_RD_E__ETM_TCTL                     MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_WR_RWN__ETM_TCLK                   MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_HSYNC__ETM_TCTL                    MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
+#define MX28_PAD_LCD_DOTCLK__ETM_TCLK                   MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
+
+#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT        MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN         MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT      MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
+#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN       MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1                 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2                MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1                MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2                 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT             MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
+#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT             MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT        MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN        MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT       MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
+#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN         MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_AUART0_RX__DUART_CTS                   MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_TX__DUART_RTS                   MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_CTS__DUART_RX                   MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_2)
+#define MX28_PAD_AUART0_RTS__DUART_TX                   MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_RX__PWM_0                       MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_TX__PWM_1                       MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA             MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_2)
+#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB             MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_RX__SSP3_D4                     MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_TX__SSP3_D5                     MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
+#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK                MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT       MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN        MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT      MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
+#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
+#define MX28_PAD_PWM0__DUART_RX                         MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
+#define MX28_PAD_PWM1__DUART_TX                         MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
+#define MX28_PAD_PWM2__USB1_OVERCURRENT                 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_MCLK__AUART4_CTS                 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS                MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_BITCLK__AUART4_RX                MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF0_SDATA0__AUART4_TX                MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
+#define MX28_PAD_I2C0_SCL__DUART_RX                     MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
+#define MX28_PAD_I2C0_SDA__DUART_TX                     MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
+#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1             MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
+#define MX28_PAD_SPDIF__ENET1_RX_ER                     MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
+
+#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1                MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2               MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1              MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2               MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT    MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT      MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN       MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT      MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN     MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT       MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
+#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN        MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
+
+/* MUXSEL_GPIO */
+#define MX28_PAD_GPMI_D00__GPIO_0_0                     MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D01__GPIO_0_1                     MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D02__GPIO_0_2                     MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D03__GPIO_0_3                     MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D04__GPIO_0_4                     MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D05__GPIO_0_5                     MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D06__GPIO_0_6                     MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_D07__GPIO_0_7                     MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE0N__GPIO_0_16                   MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE1N__GPIO_0_17                   MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE2N__GPIO_0_18                   MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CE3N__GPIO_0_19                   MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY0__GPIO_0_20                   MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY1__GPIO_0_21                   MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY2__GPIO_0_22                   MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDY3__GPIO_0_23                   MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RDN__GPIO_0_24                    MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_WRN__GPIO_0_25                    MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_ALE__GPIO_0_26                    MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_CLE__GPIO_0_27                    MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_GPMI_RESETN__GPIO_0_28                 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_LCD_D00__GPIO_1_0                      MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D01__GPIO_1_1                      MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D02__GPIO_1_2                      MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D03__GPIO_1_3                      MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D04__GPIO_1_4                      MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D05__GPIO_1_5                      MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D06__GPIO_1_6                      MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D07__GPIO_1_7                      MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D08__GPIO_1_8                      MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D09__GPIO_1_9                      MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D10__GPIO_1_10                     MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D11__GPIO_1_11                     MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D12__GPIO_1_12                     MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D13__GPIO_1_13                     MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D14__GPIO_1_14                     MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D15__GPIO_1_15                     MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D16__GPIO_1_16                     MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D17__GPIO_1_17                     MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D18__GPIO_1_18                     MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D19__GPIO_1_19                     MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D20__GPIO_1_20                     MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D21__GPIO_1_21                     MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D22__GPIO_1_22                     MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_D23__GPIO_1_23                     MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RD_E__GPIO_1_24                    MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_WR_RWN__GPIO_1_25                  MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RS__GPIO_1_26                      MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_CS__GPIO_1_27                      MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_VSYNC__GPIO_1_28                   MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_HSYNC__GPIO_1_29                   MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_DOTCLK__GPIO_1_30                  MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_ENABLE__GPIO_1_31                  MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_SSP0_DATA0__GPIO_2_0                   MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA1__GPIO_2_1                   MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA2__GPIO_2_2                   MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA3__GPIO_2_3                   MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA4__GPIO_2_4                   MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA5__GPIO_2_5                   MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA6__GPIO_2_6                   MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DATA7__GPIO_2_7                   MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_CMD__GPIO_2_8                     MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_DETECT__GPIO_2_9                  MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP0_SCK__GPIO_2_10                    MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_SCK__GPIO_2_12                    MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_CMD__GPIO_2_13                    MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_DATA0__GPIO_2_14                  MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP1_DATA3__GPIO_2_15                  MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SCK__GPIO_2_16                    MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_MOSI__GPIO_2_17                   MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_MISO__GPIO_2_18                   MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS0__GPIO_2_19                    MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS1__GPIO_2_20                    MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP2_SS2__GPIO_2_21                    MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_SCK__GPIO_2_24                    MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_MOSI__GPIO_2_25                   MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_MISO__GPIO_2_26                   MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SSP3_SS0__GPIO_2_27                    MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_AUART0_RX__GPIO_3_0                    MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_TX__GPIO_3_1                    MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_CTS__GPIO_3_2                   MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART0_RTS__GPIO_3_3                   MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_RX__GPIO_3_4                    MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_TX__GPIO_3_5                    MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_CTS__GPIO_3_6                   MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART1_RTS__GPIO_3_7                   MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_RX__GPIO_3_8                    MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_TX__GPIO_3_9                    MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_CTS__GPIO_3_10                  MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART2_RTS__GPIO_3_11                  MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_RX__GPIO_3_12                   MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_TX__GPIO_3_13                   MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_CTS__GPIO_3_14                  MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_AUART3_RTS__GPIO_3_15                  MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM0__GPIO_3_16                        MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM1__GPIO_3_17                        MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM2__GPIO_3_18                        MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_MCLK__GPIO_3_20                  MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21                 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22                MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23                MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
+#define MX28_PAD_I2C0_SCL__GPIO_3_24                    MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
+#define MX28_PAD_I2C0_SDA__GPIO_3_25                    MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26                MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
+#define MX28_PAD_SPDIF__GPIO_3_27                       MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM3__GPIO_3_28                        MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
+#define MX28_PAD_PWM4__GPIO_3_29                        MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
+#define MX28_PAD_LCD_RESET__GPIO_3_30                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
+
+#define MX28_PAD_ENET0_MDC__GPIO_4_0                    MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_MDIO__GPIO_4_1                   MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RX_EN__GPIO_4_2                  MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD0__GPIO_4_3                   MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD1__GPIO_4_4                   MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5                 MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TX_EN__GPIO_4_6                  MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD0__GPIO_4_7                   MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD1__GPIO_4_8                   MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD2__GPIO_4_9                   MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RXD3__GPIO_4_10                  MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD2__GPIO_4_11                  MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_TXD3__GPIO_4_12                  MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13                MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_COL__GPIO_4_14                   MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET0_CRS__GPIO_4_15                   MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
+#define MX28_PAD_ENET_CLK__GPIO_4_16                    MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
+#define MX28_PAD_JTAG_RTCK__GPIO_4_20                   MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
+
+#endif /* __MACH_IOMUX_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
new file mode 100644
index 000000000000..fe558e3c5a9a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/iomux.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                      <armlinux@phytec.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_MXS_IOMUX_H__
+#define __MACH_MXS_IOMUX_H__
+
+/*
+ * IOMUX/PAD Bit field definitions
+ *
+ * PAD_BANK:             0..2   (3)
+ * PAD_PIN:              3..7   (5)
+ * PAD_MUXSEL:           8..9   (2)
+ * PAD_MA:              10..11  (2)
+ * PAD_MA_VALID:        12      (1)
+ * PAD_VOL:             13      (1)
+ * PAD_VOL_VALID:       14      (1)
+ * PAD_PULL:            15      (1)
+ * PAD_PULL_VALID:      16      (1)
+ * RESERVED:            17..31  (15)
+ */
+typedef u32 iomux_cfg_t;
+
+#define MXS_PAD_BANK_SHIFT      0
+#define MXS_PAD_BANK_MASK       ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
+#define MXS_PAD_PIN_SHIFT       3
+#define MXS_PAD_PIN_MASK        ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
+#define MXS_PAD_MUXSEL_SHIFT    8
+#define MXS_PAD_MUXSEL_MASK     ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
+#define MXS_PAD_MA_SHIFT        10
+#define MXS_PAD_MA_MASK         ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
+#define MXS_PAD_MA_VALID_SHIFT  12
+#define MXS_PAD_MA_VALID_MASK   ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
+#define MXS_PAD_VOL_SHIFT       13
+#define MXS_PAD_VOL_MASK        ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
+#define MXS_PAD_VOL_VALID_SHIFT 14
+#define MXS_PAD_VOL_VALID_MASK  ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
+#define MXS_PAD_PULL_SHIFT      15
+#define MXS_PAD_PULL_MASK       ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
+#define MXS_PAD_PULL_VALID_SHIFT 16
+#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
+
+#define PAD_MUXSEL_0            0
+#define PAD_MUXSEL_1            1
+#define PAD_MUXSEL_2            2
+#define PAD_MUXSEL_GPIO         3
+
+#define PAD_4MA                 0
+#define PAD_8MA                 1
+#define PAD_12MA                2
+#define PAD_16MA                3
+
+#define PAD_1V8                 0
+#define PAD_3V3                 1
+
+#define PAD_NOPULL              0
+#define PAD_PULLUP              1
+
+#define MXS_PAD_4MA     ((PAD_4MA << MXS_PAD_MA_SHIFT) | \
+                                        MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_8MA     ((PAD_8MA << MXS_PAD_MA_SHIFT) | \
+                                        MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_12MA    ((PAD_12MA << MXS_PAD_MA_SHIFT) | \
+                                        MXS_PAD_MA_VALID_MASK)
+#define MXS_PAD_16MA    ((PAD_16MA << MXS_PAD_MA_SHIFT) | \
+                                        MXS_PAD_MA_VALID_MASK)
+
+#define MXS_PAD_1V8     ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
+                                        MXS_PAD_VOL_VALID_MASK)
+#define MXS_PAD_3V3     ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
+                                        MXS_PAD_VOL_VALID_MASK)
+
+#define MXS_PAD_NOPULL  ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
+                                        MXS_PAD_PULL_VALID_MASK)
+#define MXS_PAD_PULLUP  ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
+                                        MXS_PAD_PULL_VALID_MASK)
+
+#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull)           \
+                (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) |         \
+                ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) |            \
+                ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) |      \
+                ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) |              \
+                ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) |            \
+                ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
+
+/*
+ * A pad becomes naked, when none of mA, vol or pull
+ * validity bits is set.
+ */
+#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
+                MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
+
+static inline unsigned int PAD_BANK(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
+}
+
+static inline unsigned int PAD_PIN(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
+}
+
+static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
+}
+
+static inline unsigned int PAD_MA(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
+}
+
+static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
+}
+
+static inline unsigned int PAD_VOL(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
+}
+
+static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
+}
+
+static inline unsigned int PAD_PULL(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
+}
+
+static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
+{
+        return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
+}
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxs_iomux_setup_pad(iomux_cfg_t pad);
+
+/*
+ * configures multiple pads
+ * convenient way to call the above function with tables
+ */
+int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
+
+#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/mach-mxs/include/mach/irqs.h b/arch/arm/mach-mxs/include/mach/irqs.h
new file mode 100644
index 000000000000..f771039b814a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/irqs.h
@@ -0,0 +1,32 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_MXS_IRQS_H__
+#define __MACH_MXS_IRQS_H__
+
+#define MXS_INTERNAL_IRQS       128
+
+#define MXS_GPIO_IRQ_START      MXS_INTERNAL_IRQS
+
+/* the maximum for MXS-based */
+#define MXS_GPIO_IRQS           (32 * 5)
+
+/*
+ * The next 16 interrupts are for board specific purposes.  Since
+ * the kernel can only run on one machine at a time, we can re-use
+ * these.  If you need more, increase MXS_BOARD_IRQS, but keep it
+ * within sensible limits.
+ */
+#define MXS_BOARD_IRQ_START     (MXS_GPIO_IRQ_START + MXS_GPIO_IRQS)
+#define MXS_BOARD_IRQS          16
+
+#define NR_IRQS                 (MXS_BOARD_IRQ_START + MXS_BOARD_IRQS)
+
+#endif /* __MACH_MXS_IRQS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/memory.h b/arch/arm/mach-mxs/include/mach/memory.h
new file mode 100644
index 000000000000..b5420a5c2d4b
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/memory.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_MXS_MEMORY_H__
+#define __MACH_MXS_MEMORY_H__
+
+#define PHYS_OFFSET             UL(0x40000000)
+
+#endif /* __MACH_MXS_MEMORY_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
new file mode 100644
index 000000000000..9edd02ec8e30
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_MX23_H__
+#define __MACH_MX23_H__
+
+#include <mach/mxs.h>
+
+/*
+ * OCRAM
+ */
+#define MX23_OCRAM_BASE_ADDR            0x00000000
+#define MX23_OCRAM_SIZE                 SZ_32K
+
+/*
+ * IO
+ */
+#define MX23_IO_BASE_ADDR               0x80000000
+#define MX23_IO_SIZE                    SZ_1M
+
+#define MX23_ICOLL_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x000000)
+#define MX23_APBH_DMA_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x004000)
+#define MX23_BCH_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x00a000)
+#define MX23_GPMI_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x00c000)
+#define MX23_SSP1_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x010000)
+#define MX23_PINCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x018000)
+#define MX23_DIGCTL_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x01c000)
+#define MX23_ETM_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x020000)
+#define MX23_APBX_DMA_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x024000)
+#define MX23_DCP_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x028000)
+#define MX23_PXP_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x02a000)
+#define MX23_OCOTP_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x02c000)
+#define MX23_AXI_AHB0_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x02e000)
+#define MX23_LCDIF_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x030000)
+#define MX23_SSP2_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x034000)
+#define MX23_TVENC_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x038000)
+#define MX23_CLKCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x040000)
+#define MX23_SAIF0_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x042000)
+#define MX23_POWER_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x044000)
+#define MX23_SAIF1_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x046000)
+#define MX23_AUDIOOUT_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x048000)
+#define MX23_AUDIOIN_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x04c000)
+#define MX23_LRADC_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x050000)
+#define MX23_SPDIF_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x054000)
+#define MX23_I2C0_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x058000)
+#define MX23_RTC_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x05c000)
+#define MX23_PWM_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x064000)
+#define MX23_TIMROT_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x068000)
+#define MX23_AUART1_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x06c000)
+#define MX23_AUART2_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x06e000)
+#define MX23_DUART_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x070000)
+#define MX23_USBPHY_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x07c000)
+#define MX23_USBCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x080000)
+#define MX23_DRAM_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x0e0000)
+
+#define MX23_IO_P2V(x)                  MXS_IO_P2V(x)
+#define MX23_IO_ADDRESS(x)              IOMEM(MX23_IO_P2V(x))
+
+/*
+ * IRQ
+ */
+#define MX23_INT_DUART                  0
+#define MX23_INT_COMMS_RX               1
+#define MX23_INT_COMMS_TX               1
+#define MX23_INT_SSP2_ERROR             2
+#define MX23_INT_VDD5V                  3
+#define MX23_INT_HEADPHONE_SHORT        4
+#define MX23_INT_DAC_DMA                5
+#define MX23_INT_DAC_ERROR              6
+#define MX23_INT_ADC_DMA                7
+#define MX23_INT_ADC_ERROR              8
+#define MX23_INT_SPDIF_DMA              9
+#define MX23_INT_SAIF2_DMA              9
+#define MX23_INT_SPDIF_ERROR            10
+#define MX23_INT_SAIF1_IRQ              10
+#define MX23_INT_SAIF2_IRQ              10
+#define MX23_INT_USB_CTRL               11
+#define MX23_INT_USB_WAKEUP             12
+#define MX23_INT_GPMI_DMA               13
+#define MX23_INT_SSP1_DMA               14
+#define MX23_INT_SSP_ERROR              15
+#define MX23_INT_GPIO0                  16
+#define MX23_INT_GPIO1                  17
+#define MX23_INT_GPIO2                  18
+#define MX23_INT_SAIF1_DMA              19
+#define MX23_INT_SSP2_DMA               20
+#define MX23_INT_ECC8_IRQ               21
+#define MX23_INT_RTC_ALARM              22
+#define MX23_INT_UARTAPP_TX_DMA         23
+#define MX23_INT_UARTAPP_INTERNAL       24
+#define MX23_INT_UARTAPP_RX_DMA         25
+#define MX23_INT_I2C_DMA                26
+#define MX23_INT_I2C_ERROR              27
+#define MX23_INT_TIMER0                 28
+#define MX23_INT_TIMER1                 29
+#define MX23_INT_TIMER2                 30
+#define MX23_INT_TIMER3                 31
+#define MX23_INT_BATT_BRNOUT            32
+#define MX23_INT_VDDD_BRNOUT            33
+#define MX23_INT_VDDIO_BRNOUT           34
+#define MX23_INT_VDD18_BRNOUT           35
+#define MX23_INT_TOUCH_DETECT           36
+#define MX23_INT_LRADC_CH0              37
+#define MX23_INT_LRADC_CH1              38
+#define MX23_INT_LRADC_CH2              39
+#define MX23_INT_LRADC_CH3              40
+#define MX23_INT_LRADC_CH4              41
+#define MX23_INT_LRADC_CH5              42
+#define MX23_INT_LRADC_CH6              43
+#define MX23_INT_LRADC_CH7              44
+#define MX23_INT_LCDIF_DMA              45
+#define MX23_INT_LCDIF_ERROR            46
+#define MX23_INT_DIGCTL_DEBUG_TRAP      47
+#define MX23_INT_RTC_1MSEC              48
+#define MX23_INT_DRI_DMA                49
+#define MX23_INT_DRI_ATTENTION          50
+#define MX23_INT_GPMI_ATTENTION         51
+#define MX23_INT_IR                     52
+#define MX23_INT_DCP_VMI                53
+#define MX23_INT_DCP                    54
+#define MX23_INT_BCH                    56
+#define MX23_INT_PXP                    57
+#define MX23_INT_UARTAPP2_TX_DMA        58
+#define MX23_INT_UARTAPP2_INTERNAL      59
+#define MX23_INT_UARTAPP2_RX_DMA        60
+#define MX23_INT_VDAC_DETECT            61
+#define MX23_INT_VDD5V_DROOP            64
+#define MX23_INT_DCDC4P2_BO             65
+
+#endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
new file mode 100644
index 000000000000..0716745267ad
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mx28.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_MX28_H__
+#define __MACH_MX28_H__
+
+#include <mach/mxs.h>
+
+/*
+ * OCRAM
+ */
+#define MX28_OCRAM_BASE_ADDR            0x00000000
+#define MX28_OCRAM_SIZE                 SZ_128K
+
+/*
+ * IO
+ */
+#define MX28_IO_BASE_ADDR               0x80000000
+#define MX28_IO_SIZE                    SZ_1M
+
+#define MX28_ICOLL_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x000000)
+#define MX28_HSADC_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x002000)
+#define MX28_APBH_DMA_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x004000)
+#define MX28_PERFMON_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x006000)
+#define MX28_BCH_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x00a000)
+#define MX28_GPMI_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x00c000)
+#define MX28_SSP0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x010000)
+#define MX28_SSP1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x012000)
+#define MX28_SSP2_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x014000)
+#define MX28_SSP3_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x016000)
+#define MX28_PINCTRL_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x018000)
+#define MX28_DIGCTL_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x01c000)
+#define MX28_ETM_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x022000)
+#define MX28_APBX_DMA_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x024000)
+#define MX28_DCP_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x028000)
+#define MX28_PXP_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x02a000)
+#define MX28_OCOTP_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x02c000)
+#define MX28_AXI_AHB0_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x02e000)
+#define MX28_LCDIF_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x030000)
+#define MX28_CAN0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x032000)
+#define MX28_CAN1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x034000)
+#define MX28_SIMDBG_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x03c000)
+#define MX28_SIMGPMISEL_BASE_ADDR       (MX28_IO_BASE_ADDR + 0x03c200)
+#define MX28_SIMSSPSEL_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x03c300)
+#define MX28_SIMMEMSEL_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x03c400)
+#define MX28_GPIOMON_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c500)
+#define MX28_SIMENET_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c700)
+#define MX28_ARMJTAG_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c800)
+#define MX28_CLKCTRL_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x040000)
+#define MX28_SAIF0_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x042000)
+#define MX28_POWER_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x044000)
+#define MX28_SAIF1_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x046000)
+#define MX28_LRADC_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x050000)
+#define MX28_SPDIF_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x054000)
+#define MX28_RTC_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x056000)
+#define MX28_I2C0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x058000)
+#define MX28_I2C1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x05a000)
+#define MX28_PWM_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x064000)
+#define MX28_TIMROT_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x068000)
+#define MX28_AUART0_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06a000)
+#define MX28_AUART1_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06c000)
+#define MX28_AUART2_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06e000)
+#define MX28_AUART3_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x070000)
+#define MX28_AUART4_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x072000)
+#define MX28_DUART_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x074000)
+#define MX28_USBPHY0_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x07C000)
+#define MX28_USBPHY1_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x07e000)
+#define MX28_USBCTRL0_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x080000)
+#define MX28_USBCTRL1_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x090000)
+#define MX28_DFLPT_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x0c0000)
+#define MX28_DRAM_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x0e0000)
+#define MX28_ENET_MAC0_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x0f0000)
+#define MX28_ENET_MAC1_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x0f4000)
+
+#define MX28_IO_P2V(x)                  MXS_IO_P2V(x)
+#define MX28_IO_ADDRESS(x)              IOMEM(MX28_IO_P2V(x))
+
+/*
+ * IRQ
+ */
+#define MX28_INT_BATT_BRNOUT            0
+#define MX28_INT_VDDD_BRNOUT            1
+#define MX28_INT_VDDIO_BRNOUT           2
+#define MX28_INT_VDDA_BRNOUT            3
+#define MX28_INT_VDD5V_DROOP            4
+#define MX28_INT_DCDC4P2_BRNOUT         5
+#define MX28_INT_VDD5V                  6
+#define MX28_INT_CAN0                   8
+#define MX28_INT_CAN1                   9
+#define MX28_INT_LRADC_TOUCH            10
+#define MX28_INT_HSADC                  13
+#define MX28_INT_IRADC_THRESH0          14
+#define MX28_INT_IRADC_THRESH1          15
+#define MX28_INT_LRADC_CH0              16
+#define MX28_INT_LRADC_CH1              17
+#define MX28_INT_LRADC_CH2              18
+#define MX28_INT_LRADC_CH3              19
+#define MX28_INT_LRADC_CH4              20
+#define MX28_INT_LRADC_CH5              21
+#define MX28_INT_LRADC_CH6              22
+#define MX28_INT_LRADC_CH7              23
+#define MX28_INT_LRADC_BUTTON0          24
+#define MX28_INT_LRADC_BUTTON1          25
+#define MX28_INT_PERFMON                27
+#define MX28_INT_RTC_1MSEC              28
+#define MX28_INT_RTC_ALARM              29
+#define MX28_INT_COMMS                  31
+#define MX28_INT_EMI_ERR                32
+#define MX28_INT_LCDIF                  38
+#define MX28_INT_PXP                    39
+#define MX28_INT_BCH                    41
+#define MX28_INT_GPMI                   42
+#define MX28_INT_SPDIF_ERROR            45
+#define MX28_INT_DUART                  47
+#define MX28_INT_TIMER0                 48
+#define MX28_INT_TIMER1                 49
+#define MX28_INT_TIMER2                 50
+#define MX28_INT_TIMER3                 51
+#define MX28_INT_DCP_VMI                52
+#define MX28_INT_DCP                    53
+#define MX28_INT_DCP_SECURE             54
+#define MX28_INT_SAIF1                  58
+#define MX28_INT_SAIF0                  59
+#define MX28_INT_SPDIF_DMA              66
+#define MX28_INT_I2C0_DMA               68
+#define MX28_INT_I2C1_DMA               69
+#define MX28_INT_AUART0_RX_DMA          70
+#define MX28_INT_AUART0_TX_DMA          71
+#define MX28_INT_AUART1_RX_DMA          72
+#define MX28_INT_AUART1_TX_DMA          73
+#define MX28_INT_AUART2_RX_DMA          74
+#define MX28_INT_AUART2_TX_DMA          75
+#define MX28_INT_AUART3_RX_DMA          76
+#define MX28_INT_AUART3_TX_DMA          77
+#define MX28_INT_AUART4_RX_DMA          78
+#define MX28_INT_AUART4_TX_DMA          79
+#define MX28_INT_SAIF0_DMA              80
+#define MX28_INT_SAIF1_DMA              81
+#define MX28_INT_SSP0_DMA               82
+#define MX28_INT_SSP1_DMA               83
+#define MX28_INT_SSP2_DMA               84
+#define MX28_INT_SSP3_DMA               85
+#define MX28_INT_LCDIF_DMA              86
+#define MX28_INT_HSADC_DMA              87
+#define MX28_INT_GPMI_DMA               88
+#define MX28_INT_DIGCTL_DEBUG_TRAP      89
+#define MX28_INT_USB1                   92
+#define MX28_INT_USB0                   93
+#define MX28_INT_USB1_WAKEUP            94
+#define MX28_INT_USB0_WAKEUP            95
+#define MX28_INT_SSP0                   96
+#define MX28_INT_SSP1                   97
+#define MX28_INT_SSP2                   98
+#define MX28_INT_SSP3                   99
+#define MX28_INT_ENET_SWI               100
+#define MX28_INT_ENET_MAC0              101
+#define MX28_INT_ENET_MAC1              102
+#define MX28_INT_ENET_MAC0_1588         103
+#define MX28_INT_ENET_MAC1_1588         104
+#define MX28_INT_I2C1_ERROR             110
+#define MX28_INT_I2C0_ERROR             111
+#define MX28_INT_AUART0                 112
+#define MX28_INT_AUART1                 113
+#define MX28_INT_AUART2                 114
+#define MX28_INT_AUART3                 115
+#define MX28_INT_AUART4                 116
+#define MX28_INT_GPIO4                  123
+#define MX28_INT_GPIO3                  124
+#define MX28_INT_GPIO2                  125
+#define MX28_INT_GPIO1                  126
+#define MX28_INT_GPIO0                  127
+
+#endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
new file mode 100644
index 000000000000..f186c08c2911
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_MXS_H__
+#define __MACH_MXS_H__
+
+#ifndef __ASSEMBLER__
+#include <linux/io.h>
+#endif
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+/*
+ * MXS CPU types
+ */
+#define cpu_is_mx23()           (machine_is_mx23evk())
+#define cpu_is_mx28()           (machine_is_mx28evk())
+
+/*
+ * IO addresses common to MXS-based
+ */
+#define MXS_IO_BASE_ADDR                0x80000000
+#define MXS_IO_SIZE                     SZ_1M
+
+#define MXS_ICOLL_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x000000)
+#define MXS_APBH_DMA_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x004000)
+#define MXS_BCH_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x00a000)
+#define MXS_GPMI_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x00c000)
+#define MXS_PINCTRL_BASE_ADDR           (MXS_IO_BASE_ADDR + 0x018000)
+#define MXS_DIGCTL_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x01c000)
+#define MXS_APBX_DMA_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x024000)
+#define MXS_DCP_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x028000)
+#define MXS_PXP_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x02a000)
+#define MXS_OCOTP_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x02c000)
+#define MXS_AXI_AHB0_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x02e000)
+#define MXS_LCDIF_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x030000)
+#define MXS_CLKCTRL_BASE_ADDR           (MXS_IO_BASE_ADDR + 0x040000)
+#define MXS_SAIF0_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x042000)
+#define MXS_POWER_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x044000)
+#define MXS_SAIF1_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x046000)
+#define MXS_LRADC_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x050000)
+#define MXS_SPDIF_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x054000)
+#define MXS_I2C0_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x058000)
+#define MXS_PWM_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x064000)
+#define MXS_TIMROT_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x068000)
+#define MXS_AUART1_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x06c000)
+#define MXS_AUART2_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x06e000)
+#define MXS_DRAM_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x0e0000)
+
+/*
+ * It maps the whole address space to [0xf4000000, 0xf50fffff].
+ *
+ *      OCRAM   0x00000000+0x020000     ->      0xf4000000+0x020000
+ *      IO      0x80000000+0x100000     ->      0xf5000000+0x100000
+ */
+#define MXS_IO_P2V(x)   (0xf4000000 +                                   \
+                        (((x) & 0x80000000) >> 7) +                     \
+                        (((x) & 0x000fffff)))
+
+#define MXS_IO_ADDRESS(x)       IOMEM(MXS_IO_P2V(x))
+
+#define mxs_map_entry(soc, name, _type) {                               \
+        .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
+        .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),           \
+        .length = soc ## _ ## name ## _SIZE,                            \
+        .type = _type,                                                  \
+}
+
+#define MXS_SET_ADDR            0x4
+#define MXS_CLR_ADDR            0x8
+#define MXS_TOG_ADDR            0xc
+
+#ifndef __ASSEMBLER__
+static inline void __mxs_setl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_SET_ADDR);
+}
+
+static inline void __mxs_clrl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_CLR_ADDR);
+}
+
+static inline void __mxs_togl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_TOG_ADDR);
+}
+#endif
+
+#endif /* __MACH_MXS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/system.h b/arch/arm/mach-mxs/include/mach/system.h
new file mode 100644
index 000000000000..0e428239b433
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/system.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_MXS_SYSTEM_H__
+#define __MACH_MXS_SYSTEM_H__
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+void arch_reset(char mode, const char *cmd);
+
+#endif /* __MACH_MXS_SYSTEM_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/timex.h b/arch/arm/mach-mxs/include/mach/timex.h
new file mode 100644
index 000000000000..734ce8984a64
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/timex.h
@@ -0,0 +1,21 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_MXS_TIMEX_H__
+#define __MACH_MXS_TIMEX_H__
+
+#define CLOCK_TICK_RATE         32000   /* 32K */
+
+#endif /* __MACH_MXS_TIMEX_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
new file mode 100644
index 000000000000..a005e76f34f9
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -0,0 +1,76 @@
+/*
+ *  arch/arm/mach-mxs/include/mach/uncompress.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) Shane Nay (shane@minirl.com)
+ *  Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_MXS_UNCOMPRESS_H__
+#define __MACH_MXS_UNCOMPRESS_H__
+
+#include <asm/mach-types.h>
+
+static unsigned long mxs_duart_base;
+
+#define MXS_DUART(x)    (*(volatile unsigned long *)(mxs_duart_base + (x)))
+
+#define MXS_DUART_DR            0x00
+#define MXS_DUART_FR            0x18
+#define MXS_DUART_FR_TXFE       (1 << 7)
+#define MXS_DUART_CR            0x30
+#define MXS_DUART_CR_UARTEN     (1 << 0)
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader. If it's not, the output is
+ * simply discarded.
+ */
+
+static void putc(int ch)
+{
+        if (!mxs_duart_base)
+                return;
+        if (!(MXS_DUART(MXS_DUART_CR) & MXS_DUART_CR_UARTEN))
+                return;
+
+        while (!(MXS_DUART(MXS_DUART_FR) & MXS_DUART_FR_TXFE))
+                barrier();
+
+        MXS_DUART(MXS_DUART_DR) = ch;
+}
+
+static inline void flush(void)
+{
+}
+
+#define MX23_DUART_BASE_ADDR    0x80070000
+#define MX28_DUART_BASE_ADDR    0x80074000
+
+static inline void __arch_decomp_setup(unsigned long arch_id)
+{
+        switch (arch_id) {
+        case MACH_TYPE_MX23EVK:
+                mxs_duart_base = MX23_DUART_BASE_ADDR;
+                break;
+        case MACH_TYPE_MX28EVK:
+                mxs_duart_base = MX28_DUART_BASE_ADDR;
+                break;
+        default:
+                break;
+        }
+}
+
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+#define arch_decomp_wdog()
+
+#endif /* __MACH_MXS_UNCOMPRESS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/vmalloc.h b/arch/arm/mach-mxs/include/mach/vmalloc.h
new file mode 100644
index 000000000000..103b0165ed0b
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/vmalloc.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2000 Russell King.
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_MXS_VMALLOC_H__
+#define __MACH_MXS_VMALLOC_H__
+
+/* vmalloc ending address */
+#define VMALLOC_END       0xf4000000UL
+
+#endif /* __MACH_MXS_VMALLOC_H__ */
diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c
new file mode 100644
index 000000000000..0e804e2f11f4
--- /dev/null
+++ b/arch/arm/mach-mxs/iomux.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
+ *                       <armlinux@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/mxs.h>
+#include <mach/iomux.h>
+
+/*
+ * configures a single pad in the iomuxer
+ */
+int mxs_iomux_setup_pad(iomux_cfg_t pad)
+{
+        u32 reg, ofs, bp, bm;
+        void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR);
+
+        /* muxsel */
+        ofs = 0x100;
+        ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
+        bp = PAD_PIN(pad) % 16 * 2;
+        bm = 0x3 << bp;
+        reg = __raw_readl(iomux_base + ofs);
+        reg &= ~bm;
+        reg |= PAD_MUXSEL(pad) << bp;
+        __raw_writel(reg, iomux_base + ofs);
+
+        /* drive */
+        ofs = cpu_is_mx23() ? 0x200 : 0x300;
+        ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
+        /* mA */
+        if (PAD_MA_VALID(pad)) {
+                bp = PAD_PIN(pad) % 8 * 4;
+                bm = 0x3 << bp;
+                reg = __raw_readl(iomux_base + ofs);
+                reg &= ~bm;
+                reg |= PAD_MA(pad) << bp;
+                __raw_writel(reg, iomux_base + ofs);
+        }
+        /* vol */
+        if (PAD_VOL_VALID(pad)) {
+                bp = PAD_PIN(pad) % 8 * 4 + 2;
+                if (PAD_VOL(pad))
+                        __mxs_setl(1 << bp, iomux_base + ofs);
+                else
+                        __mxs_clrl(1 << bp, iomux_base + ofs);
+        }
+
+        /* pull */
+        if (PAD_PULL_VALID(pad)) {
+                ofs = cpu_is_mx23() ? 0x400 : 0x600;
+                ofs += PAD_BANK(pad) * 0x10;
+                bp = PAD_PIN(pad);
+                if (PAD_PULL(pad))
+                        __mxs_setl(1 << bp, iomux_base + ofs);
+                else
+                        __mxs_clrl(1 << bp, iomux_base + ofs);
+        }
+
+        return 0;
+}
+
+int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
+{
+        const iomux_cfg_t *p = pad_list;
+        int i;
+        int ret;
+
+        for (i = 0; i < count; i++) {
+                ret = mxs_iomux_setup_pad(*p);
+                if (ret)
+                        return ret;
+                p++;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
new file mode 100644
index 000000000000..aa0640052f58
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/iomux-mx23.h>
+
+#include "devices-mx23.h"
+
+static const iomux_cfg_t mx23evk_pads[] __initconst = {
+        /* duart */
+        MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA,
+        MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA,
+};
+
+static void __init mx23evk_init(void)
+{
+        mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
+
+        mx23_add_duart();
+}
+
+static void __init mx23evk_timer_init(void)
+{
+        mx23_clocks_init();
+}
+
+static struct sys_timer mx23evk_timer = {
+        .init   = mx23evk_timer_init,
+};
+
+MACHINE_START(MX23EVK, "Freescale MX23 EVK")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .map_io         = mx23_map_io,
+        .init_irq       = mx23_init_irq,
+        .init_machine   = mx23evk_init,
+        .timer          = &mx23evk_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
new file mode 100644
index 000000000000..d162e95910f3
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/iomux-mx28.h>
+
+#include "devices-mx28.h"
+#include "gpio.h"
+
+#define MX28EVK_FEC_PHY_POWER   MXS_GPIO_NR(2, 15)
+#define MX28EVK_FEC_PHY_RESET   MXS_GPIO_NR(4, 13)
+
+static const iomux_cfg_t mx28evk_pads[] __initconst = {
+        /* duart */
+        MX28_PAD_PWM0__DUART_RX |
+                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        MX28_PAD_PWM1__DUART_TX |
+                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+        /* fec0 */
+        MX28_PAD_ENET0_MDC__ENET0_MDC |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_MDIO__ENET0_MDIO |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_RXD0__ENET0_RXD0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_RXD1__ENET0_RXD1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TXD0__ENET0_TXD0 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET0_TXD1__ENET0_TXD1 |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        MX28_PAD_ENET_CLK__CLKCTRL_ENET |
+                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+        /* phy power line */
+        MX28_PAD_SSP1_DATA3__GPIO_2_15 |
+                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+        /* phy reset line */
+        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
+                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+};
+
+/* fec */
+static void __init mx28evk_fec_reset(void)
+{
+        int ret;
+        struct clk *clk;
+
+        /* Enable fec phy clock */
+        clk = clk_get_sys("pll2", NULL);
+        if (!IS_ERR(clk))
+                clk_enable(clk);
+
+        /* Power up fec phy */
+        ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power");
+        if (ret) {
+                pr_err("Failed to request gpio fec-phy-%s: %d\n", "power", ret);
+                return;
+        }
+
+        ret = gpio_direction_output(MX28EVK_FEC_PHY_POWER, 0);
+        if (ret) {
+                pr_err("Failed to drive gpio fec-phy-%s: %d\n", "power", ret);
+                return;
+        }
+
+        /* Reset fec phy */
+        ret = gpio_request(MX28EVK_FEC_PHY_RESET, "fec-phy-reset");
+        if (ret) {
+                pr_err("Failed to request gpio fec-phy-%s: %d\n", "reset", ret);
+                return;
+        }
+
+        gpio_direction_output(MX28EVK_FEC_PHY_RESET, 0);
+        if (ret) {
+                pr_err("Failed to drive gpio fec-phy-%s: %d\n", "reset", ret);
+                return;
+        }
+
+        mdelay(1);
+        gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
+}
+
+static const struct fec_platform_data mx28_fec_pdata __initconst = {
+        .phy = PHY_INTERFACE_MODE_RMII,
+};
+
+static void __init mx28evk_init(void)
+{
+        mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
+
+        mx28_add_duart();
+
+        mx28evk_fec_reset();
+        mx28_add_fec(0, &mx28_fec_pdata);
+}
+
+static void __init mx28evk_timer_init(void)
+{
+        mx28_clocks_init();
+}
+
+static struct sys_timer mx28evk_timer = {
+        .init   = mx28evk_timer_init,
+};
+
+MACHINE_START(MX28EVK, "Freescale MX28 EVK")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .map_io         = mx28_map_io,
+        .init_irq       = mx28_init_irq,
+        .init_machine   = mx28evk_init,
+        .timer          = &mx28evk_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm-mx23.c
new file mode 100644
index 000000000000..5148cd64a6b7
--- /dev/null
+++ b/arch/arm/mach-mxs/mm-mx23.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License.  You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ *
+ * Create static mapping between physical to virtual memory.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/mx23.h>
+#include <mach/common.h>
+#include <mach/iomux.h>
+
+/*
+ * Define the MX23 memory map.
+ */
+static struct map_desc mx23_io_desc[] __initdata = {
+        mxs_map_entry(MX23, OCRAM, MT_DEVICE),
+        mxs_map_entry(MX23, IO, MT_DEVICE),
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx23_map_io(void)
+{
+        iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
+}
+
+void __init mx23_init_irq(void)
+{
+        icoll_init_irq();
+        mx23_register_gpios();
+}
diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm-mx28.c
new file mode 100644
index 000000000000..7e4cea32ebc6
--- /dev/null
+++ b/arch/arm/mach-mxs/mm-mx28.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License.  You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ *
+ * Create static mapping between physical to virtual memory.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/mx28.h>
+#include <mach/common.h>
+#include <mach/iomux.h>
+
+/*
+ * Define the MX28 memory map.
+ */
+static struct map_desc mx28_io_desc[] __initdata = {
+        mxs_map_entry(MX28, OCRAM, MT_DEVICE),
+        mxs_map_entry(MX28, IO, MT_DEVICE),
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx28_map_io(void)
+{
+        iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
+}
+
+void __init mx28_init_irq(void)
+{
+        icoll_init_irq();
+        mx28_register_gpios();
+}
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
new file mode 100644
index 000000000000..dbc04747b691
--- /dev/null
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
@@ -0,0 +1,455 @@
+/*
+ * Freescale CLKCTRL Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.48
+ * Template revision: 26195
+ */
+
+#ifndef __REGS_CLKCTRL_MX23_H__
+#define __REGS_CLKCTRL_MX23_H__
+
+
+#define HW_CLKCTRL_PLLCTRL0     (0x00000000)
+#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004)
+#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
+#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
+
+#define BP_CLKCTRL_PLLCTRL0_RSRVD6      30
+#define BM_CLKCTRL_PLLCTRL0_RSRVD6      0xC0000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
+                (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
+#define BP_CLKCTRL_PLLCTRL0_LFR_SEL     28
+#define BM_CLKCTRL_PLLCTRL0_LFR_SEL     0x30000000
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v)  \
+                (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLLCTRL0_RSRVD5      26
+#define BM_CLKCTRL_PLLCTRL0_RSRVD5      0x0C000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v)  \
+                (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
+#define BP_CLKCTRL_PLLCTRL0_CP_SEL      24
+#define BM_CLKCTRL_PLLCTRL0_CP_SEL      0x03000000
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v)  \
+                (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLLCTRL0_RSRVD4      22
+#define BM_CLKCTRL_PLLCTRL0_RSRVD4      0x00C00000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v)  \
+                (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
+#define BP_CLKCTRL_PLLCTRL0_DIV_SEL     20
+#define BM_CLKCTRL_PLLCTRL0_DIV_SEL     0x00300000
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v)  \
+                (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER     0x1
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST    0x2
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_PLLCTRL0_RSRVD3      0x00080000
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
+#define BM_CLKCTRL_PLLCTRL0_RSRVD2      0x00020000
+#define BM_CLKCTRL_PLLCTRL0_POWER       0x00010000
+#define BP_CLKCTRL_PLLCTRL0_RSRVD1      0
+#define BM_CLKCTRL_PLLCTRL0_RSRVD1      0x0000FFFF
+#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
+
+#define HW_CLKCTRL_PLLCTRL1     (0x00000010)
+
+#define BM_CLKCTRL_PLLCTRL1_LOCK        0x80000000
+#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK  0x40000000
+#define BP_CLKCTRL_PLLCTRL1_RSRVD1      16
+#define BM_CLKCTRL_PLLCTRL1_RSRVD1      0x3FFF0000
+#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v)  \
+                (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
+#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT  0
+#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT  0x0000FFFF
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
+
+#define HW_CLKCTRL_CPU  (0x00000020)
+#define HW_CLKCTRL_CPU_SET      (0x00000024)
+#define HW_CLKCTRL_CPU_CLR      (0x00000028)
+#define HW_CLKCTRL_CPU_TOG      (0x0000002c)
+
+#define BP_CLKCTRL_CPU_RSRVD5   30
+#define BM_CLKCTRL_CPU_RSRVD5   0xC0000000
+#define BF_CLKCTRL_CPU_RSRVD5(v) \
+                (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL    0x20000000
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU     0x10000000
+#define BM_CLKCTRL_CPU_RSRVD4   0x08000000
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
+#define BP_CLKCTRL_CPU_DIV_XTAL 16
+#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
+                (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
+#define BP_CLKCTRL_CPU_RSRVD3   13
+#define BM_CLKCTRL_CPU_RSRVD3   0x0000E000
+#define BF_CLKCTRL_CPU_RSRVD3(v)  \
+                (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT   0x00001000
+#define BM_CLKCTRL_CPU_RSRVD2   0x00000800
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN  0x00000400
+#define BP_CLKCTRL_CPU_RSRVD1   6
+#define BM_CLKCTRL_CPU_RSRVD1   0x000003C0
+#define BF_CLKCTRL_CPU_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
+#define BP_CLKCTRL_CPU_DIV_CPU  0
+#define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
+#define BF_CLKCTRL_CPU_DIV_CPU(v)  \
+                (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
+
+#define HW_CLKCTRL_HBUS (0x00000030)
+#define HW_CLKCTRL_HBUS_SET     (0x00000034)
+#define HW_CLKCTRL_HBUS_CLR     (0x00000038)
+#define HW_CLKCTRL_HBUS_TOG     (0x0000003c)
+
+#define BP_CLKCTRL_HBUS_RSRVD4  30
+#define BM_CLKCTRL_HBUS_RSRVD4  0xC0000000
+#define BF_CLKCTRL_HBUS_RSRVD4(v) \
+                (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
+#define BM_CLKCTRL_HBUS_BUSY    0x20000000
+#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE   0x10000000
+#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE   0x08000000
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE       0x04000000
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE       0x02000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE   0x01000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE       0x00800000
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE      0x00400000
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE     0x00200000
+#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE  0x00100000
+#define BM_CLKCTRL_HBUS_RSRVD2  0x00080000
+#define BP_CLKCTRL_HBUS_SLOW_DIV        16
+#define BM_CLKCTRL_HBUS_SLOW_DIV        0x00070000
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
+                (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1  0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2  0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4  0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
+#define BP_CLKCTRL_HBUS_RSRVD1  6
+#define BM_CLKCTRL_HBUS_RSRVD1  0x0000FFC0
+#define BF_CLKCTRL_HBUS_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
+#define BP_CLKCTRL_HBUS_DIV     0
+#define BM_CLKCTRL_HBUS_DIV     0x0000001F
+#define BF_CLKCTRL_HBUS_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
+
+#define HW_CLKCTRL_XBUS (0x00000040)
+
+#define BM_CLKCTRL_XBUS_BUSY    0x80000000
+#define BP_CLKCTRL_XBUS_RSRVD1  11
+#define BM_CLKCTRL_XBUS_RSRVD1  0x7FFFF800
+#define BF_CLKCTRL_XBUS_RSRVD1(v)  \
+                (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x00000400
+#define BP_CLKCTRL_XBUS_DIV     0
+#define BM_CLKCTRL_XBUS_DIV     0x000003FF
+#define BF_CLKCTRL_XBUS_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
+
+#define HW_CLKCTRL_XTAL (0x00000050)
+#define HW_CLKCTRL_XTAL_SET     (0x00000054)
+#define HW_CLKCTRL_XTAL_CLR     (0x00000058)
+#define HW_CLKCTRL_XTAL_TOG     (0x0000005c)
+
+#define BP_CLKCTRL_XTAL_UART_CLK_GATE   31
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE   0x80000000
+#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE        30
+#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE        0x40000000
+#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
+#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE      0x08000000
+#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x04000000
+#define BP_CLKCTRL_XTAL_RSRVD1  2
+#define BM_CLKCTRL_XTAL_RSRVD1  0x03FFFFFC
+#define BF_CLKCTRL_XTAL_RSRVD1(v)  \
+                (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
+#define BP_CLKCTRL_XTAL_DIV_UART        0
+#define BM_CLKCTRL_XTAL_DIV_UART        0x00000003
+#define BF_CLKCTRL_XTAL_DIV_UART(v)  \
+                (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
+
+#define HW_CLKCTRL_PIX  (0x00000060)
+
+#define BP_CLKCTRL_PIX_CLKGATE  31
+#define BM_CLKCTRL_PIX_CLKGATE  0x80000000
+#define BM_CLKCTRL_PIX_RSRVD2   0x40000000
+#define BM_CLKCTRL_PIX_BUSY     0x20000000
+#define BP_CLKCTRL_PIX_RSRVD1   13
+#define BM_CLKCTRL_PIX_RSRVD1   0x1FFFE000
+#define BF_CLKCTRL_PIX_RSRVD1(v)  \
+                (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
+#define BM_CLKCTRL_PIX_DIV_FRAC_EN      0x00001000
+#define BP_CLKCTRL_PIX_DIV      0
+#define BM_CLKCTRL_PIX_DIV      0x00000FFF
+#define BF_CLKCTRL_PIX_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_PIX_DIV)
+
+#define HW_CLKCTRL_SSP  (0x00000070)
+
+#define BP_CLKCTRL_SSP_CLKGATE  31
+#define BM_CLKCTRL_SSP_CLKGATE  0x80000000
+#define BM_CLKCTRL_SSP_RSRVD2   0x40000000
+#define BM_CLKCTRL_SSP_BUSY     0x20000000
+#define BP_CLKCTRL_SSP_RSRVD1   10
+#define BM_CLKCTRL_SSP_RSRVD1   0x1FFFFC00
+#define BF_CLKCTRL_SSP_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
+#define BM_CLKCTRL_SSP_DIV_FRAC_EN      0x00000200
+#define BP_CLKCTRL_SSP_DIV      0
+#define BM_CLKCTRL_SSP_DIV      0x000001FF
+#define BF_CLKCTRL_SSP_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SSP_DIV)
+
+#define HW_CLKCTRL_GPMI (0x00000080)
+
+#define BP_CLKCTRL_GPMI_CLKGATE 31
+#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
+#define BM_CLKCTRL_GPMI_RSRVD2  0x40000000
+#define BM_CLKCTRL_GPMI_BUSY    0x20000000
+#define BP_CLKCTRL_GPMI_RSRVD1  11
+#define BM_CLKCTRL_GPMI_RSRVD1  0x1FFFF800
+#define BF_CLKCTRL_GPMI_RSRVD1(v)  \
+                (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x00000400
+#define BP_CLKCTRL_GPMI_DIV     0
+#define BM_CLKCTRL_GPMI_DIV     0x000003FF
+#define BF_CLKCTRL_GPMI_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
+
+#define HW_CLKCTRL_SPDIF        (0x00000090)
+
+#define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
+#define BP_CLKCTRL_SPDIF_RSRVD  0
+#define BM_CLKCTRL_SPDIF_RSRVD  0x7FFFFFFF
+#define BF_CLKCTRL_SPDIF_RSRVD(v)  \
+                (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
+
+#define HW_CLKCTRL_EMI  (0x000000a0)
+
+#define BP_CLKCTRL_EMI_CLKGATE  31
+#define BM_CLKCTRL_EMI_CLKGATE  0x80000000
+#define BM_CLKCTRL_EMI_SYNC_MODE_EN     0x40000000
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL    0x20000000
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
+#define BM_CLKCTRL_EMI_BUSY_REF_CPU     0x08000000
+#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE   0x04000000
+#define BP_CLKCTRL_EMI_RSRVD3   18
+#define BM_CLKCTRL_EMI_RSRVD3   0x03FC0000
+#define BF_CLKCTRL_EMI_RSRVD3(v)  \
+                (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
+#define BP_CLKCTRL_EMI_RSRVD2   12
+#define BM_CLKCTRL_EMI_RSRVD2   0x0000F000
+#define BF_CLKCTRL_EMI_RSRVD2(v)  \
+                (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
+#define BP_CLKCTRL_EMI_DIV_XTAL 8
+#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
+                (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
+#define BP_CLKCTRL_EMI_RSRVD1   6
+#define BM_CLKCTRL_EMI_RSRVD1   0x000000C0
+#define BF_CLKCTRL_EMI_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
+#define BP_CLKCTRL_EMI_DIV_EMI  0
+#define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
+#define BF_CLKCTRL_EMI_DIV_EMI(v)  \
+                (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
+
+#define HW_CLKCTRL_IR   (0x000000b0)
+
+#define BM_CLKCTRL_IR_CLKGATE   0x80000000
+#define BM_CLKCTRL_IR_RSRVD3    0x40000000
+#define BM_CLKCTRL_IR_AUTO_DIV  0x20000000
+#define BM_CLKCTRL_IR_IR_BUSY   0x10000000
+#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
+#define BP_CLKCTRL_IR_RSRVD2    25
+#define BM_CLKCTRL_IR_RSRVD2    0x06000000
+#define BF_CLKCTRL_IR_RSRVD2(v)  \
+                (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
+#define BP_CLKCTRL_IR_IROV_DIV  16
+#define BM_CLKCTRL_IR_IROV_DIV  0x01FF0000
+#define BF_CLKCTRL_IR_IROV_DIV(v)  \
+                (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
+#define BP_CLKCTRL_IR_RSRVD1    10
+#define BM_CLKCTRL_IR_RSRVD1    0x0000FC00
+#define BF_CLKCTRL_IR_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
+#define BP_CLKCTRL_IR_IR_DIV    0
+#define BM_CLKCTRL_IR_IR_DIV    0x000003FF
+#define BF_CLKCTRL_IR_IR_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
+
+#define HW_CLKCTRL_SAIF (0x000000c0)
+
+#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
+#define BM_CLKCTRL_SAIF_RSRVD2  0x40000000
+#define BM_CLKCTRL_SAIF_BUSY    0x20000000
+#define BP_CLKCTRL_SAIF_RSRVD1  17
+#define BM_CLKCTRL_SAIF_RSRVD1  0x1FFE0000
+#define BF_CLKCTRL_SAIF_RSRVD1(v)  \
+                (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
+#define BM_CLKCTRL_SAIF_DIV_FRAC_EN     0x00010000
+#define BP_CLKCTRL_SAIF_DIV     0
+#define BM_CLKCTRL_SAIF_DIV     0x0000FFFF
+#define BF_CLKCTRL_SAIF_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SAIF_DIV)
+
+#define HW_CLKCTRL_TV   (0x000000d0)
+
+#define BM_CLKCTRL_TV_CLK_TV108M_GATE   0x80000000
+#define BM_CLKCTRL_TV_CLK_TV_GATE       0x40000000
+#define BP_CLKCTRL_TV_RSRVD     0
+#define BM_CLKCTRL_TV_RSRVD     0x3FFFFFFF
+#define BF_CLKCTRL_TV_RSRVD(v)  \
+                (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
+
+#define HW_CLKCTRL_ETM  (0x000000e0)
+
+#define BM_CLKCTRL_ETM_CLKGATE  0x80000000
+#define BM_CLKCTRL_ETM_RSRVD2   0x40000000
+#define BM_CLKCTRL_ETM_BUSY     0x20000000
+#define BP_CLKCTRL_ETM_RSRVD1   7
+#define BM_CLKCTRL_ETM_RSRVD1   0x1FFFFF80
+#define BF_CLKCTRL_ETM_RSRVD1(v)  \
+                (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
+#define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x00000040
+#define BP_CLKCTRL_ETM_DIV      0
+#define BM_CLKCTRL_ETM_DIV      0x0000003F
+#define BF_CLKCTRL_ETM_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_ETM_DIV)
+
+#define HW_CLKCTRL_FRAC (0x000000f0)
+#define HW_CLKCTRL_FRAC_SET     (0x000000f4)
+#define HW_CLKCTRL_FRAC_CLR     (0x000000f8)
+#define HW_CLKCTRL_FRAC_TOG     (0x000000fc)
+
+#define BP_CLKCTRL_FRAC_CLKGATEIO       31
+#define BM_CLKCTRL_FRAC_CLKGATEIO       0x80000000
+#define BM_CLKCTRL_FRAC_IO_STABLE       0x40000000
+#define BP_CLKCTRL_FRAC_IOFRAC  24
+#define BM_CLKCTRL_FRAC_IOFRAC  0x3F000000
+#define BF_CLKCTRL_FRAC_IOFRAC(v)  \
+                (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
+#define BP_CLKCTRL_FRAC_CLKGATEPIX      23
+#define BM_CLKCTRL_FRAC_CLKGATEPIX      0x00800000
+#define BM_CLKCTRL_FRAC_PIX_STABLE      0x00400000
+#define BP_CLKCTRL_FRAC_PIXFRAC 16
+#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
+#define BF_CLKCTRL_FRAC_PIXFRAC(v)  \
+                (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
+#define BP_CLKCTRL_FRAC_CLKGATEEMI      15
+#define BM_CLKCTRL_FRAC_CLKGATEEMI      0x00008000
+#define BM_CLKCTRL_FRAC_EMI_STABLE      0x00004000
+#define BP_CLKCTRL_FRAC_EMIFRAC 8
+#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
+#define BF_CLKCTRL_FRAC_EMIFRAC(v)  \
+                (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
+#define BP_CLKCTRL_FRAC_CLKGATECPU      7
+#define BM_CLKCTRL_FRAC_CLKGATECPU      0x00000080
+#define BM_CLKCTRL_FRAC_CPU_STABLE      0x00000040
+#define BP_CLKCTRL_FRAC_CPUFRAC 0
+#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
+#define BF_CLKCTRL_FRAC_CPUFRAC(v)  \
+                (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
+
+#define HW_CLKCTRL_FRAC1        (0x00000100)
+#define HW_CLKCTRL_FRAC1_SET    (0x00000104)
+#define HW_CLKCTRL_FRAC1_CLR    (0x00000108)
+#define HW_CLKCTRL_FRAC1_TOG    (0x0000010c)
+
+#define BM_CLKCTRL_FRAC1_CLKGATEVID     0x80000000
+#define BM_CLKCTRL_FRAC1_VID_STABLE     0x40000000
+#define BP_CLKCTRL_FRAC1_RSRVD1 0
+#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
+#define BF_CLKCTRL_FRAC1_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
+
+#define HW_CLKCTRL_CLKSEQ       (0x00000110)
+#define HW_CLKCTRL_CLKSEQ_SET   (0x00000114)
+#define HW_CLKCTRL_CLKSEQ_CLR   (0x00000118)
+#define HW_CLKCTRL_CLKSEQ_TOG   (0x0000011c)
+
+#define BP_CLKCTRL_CLKSEQ_RSRVD1        9
+#define BM_CLKCTRL_CLKSEQ_RSRVD1        0xFFFFFE00
+#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
+                (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM    0x00000100
+#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU    0x00000080
+#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI    0x00000040
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP    0x00000020
+#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI   0x00000010
+#define BM_CLKCTRL_CLKSEQ_BYPASS_IR     0x00000008
+#define BM_CLKCTRL_CLKSEQ_RSRVD0        0x00000004
+#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX    0x00000002
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF   0x00000001
+
+#define HW_CLKCTRL_RESET        (0x00000120)
+
+#define BP_CLKCTRL_RESET_RSRVD  2
+#define BM_CLKCTRL_RESET_RSRVD  0xFFFFFFFC
+#define BF_CLKCTRL_RESET_RSRVD(v) \
+                (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
+#define BM_CLKCTRL_RESET_CHIP   0x00000002
+#define BM_CLKCTRL_RESET_DIG    0x00000001
+
+#define HW_CLKCTRL_STATUS       (0x00000130)
+
+#define BP_CLKCTRL_STATUS_CPU_LIMIT     30
+#define BM_CLKCTRL_STATUS_CPU_LIMIT     0xC0000000
+#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
+                (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
+#define BP_CLKCTRL_STATUS_RSRVD 0
+#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
+#define BF_CLKCTRL_STATUS_RSRVD(v)  \
+                (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
+
+#define HW_CLKCTRL_VERSION      (0x00000140)
+
+#define BP_CLKCTRL_VERSION_MAJOR        24
+#define BM_CLKCTRL_VERSION_MAJOR        0xFF000000
+#define BF_CLKCTRL_VERSION_MAJOR(v) \
+                (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
+#define BP_CLKCTRL_VERSION_MINOR        16
+#define BM_CLKCTRL_VERSION_MINOR        0x00FF0000
+#define BF_CLKCTRL_VERSION_MINOR(v)  \
+                (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
+#define BP_CLKCTRL_VERSION_STEP 0
+#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
+#define BF_CLKCTRL_VERSION_STEP(v)  \
+                (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
+
+#endif /* __REGS_CLKCTRL_MX23_H__ */
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
new file mode 100644
index 000000000000..661df18755f7
--- /dev/null
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
@@ -0,0 +1,663 @@
+/*
+ * Freescale CLKCTRL Register Definitions
+ *
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.48
+ * Template revision: 26195
+ */
+
+#ifndef __REGS_CLKCTRL_MX28_H__
+#define __REGS_CLKCTRL_MX28_H__
+
+#define HW_CLKCTRL_PLL0CTRL0    (0x00000000)
+#define HW_CLKCTRL_PLL0CTRL0_SET        (0x00000004)
+#define HW_CLKCTRL_PLL0CTRL0_CLR        (0x00000008)
+#define HW_CLKCTRL_PLL0CTRL0_TOG        (0x0000000c)
+
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD6     30
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD6     0xC0000000
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
+                (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
+#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL    28
+#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL    0x30000000
+#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v)  \
+                (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD5     26
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD5     0x0C000000
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v)  \
+                (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
+#define BP_CLKCTRL_PLL0CTRL0_CP_SEL     24
+#define BM_CLKCTRL_PLL0CTRL0_CP_SEL     0x03000000
+#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v)  \
+                (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD4     22
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD4     0x00C00000
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v)  \
+                (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
+#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL    20
+#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL    0x00300000
+#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v)  \
+                (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER     0x1
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST    0x2
+#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD3     0x00080000
+#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS        0x00040000
+#define BM_CLKCTRL_PLL0CTRL0_POWER      0x00020000
+#define BP_CLKCTRL_PLL0CTRL0_RSRVD1     0
+#define BM_CLKCTRL_PLL0CTRL0_RSRVD1     0x0001FFFF
+#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
+
+#define HW_CLKCTRL_PLL0CTRL1    (0x00000010)
+
+#define BM_CLKCTRL_PLL0CTRL1_LOCK       0x80000000
+#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
+#define BP_CLKCTRL_PLL0CTRL1_RSRVD1     16
+#define BM_CLKCTRL_PLL0CTRL1_RSRVD1     0x3FFF0000
+#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v)  \
+                (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
+#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
+#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
+#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
+
+#define HW_CLKCTRL_PLL1CTRL0    (0x00000020)
+#define HW_CLKCTRL_PLL1CTRL0_SET        (0x00000024)
+#define HW_CLKCTRL_PLL1CTRL0_CLR        (0x00000028)
+#define HW_CLKCTRL_PLL1CTRL0_TOG        (0x0000002c)
+
+#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD6     0x40000000
+#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL    28
+#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL    0x30000000
+#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v)  \
+                (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL1CTRL0_RSRVD5     26
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD5     0x0C000000
+#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v)  \
+                (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
+#define BP_CLKCTRL_PLL1CTRL0_CP_SEL     24
+#define BM_CLKCTRL_PLL1CTRL0_CP_SEL     0x03000000
+#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v)  \
+                (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2   0x1
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05  0x2
+#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLL1CTRL0_RSRVD4     22
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD4     0x00C00000
+#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v)  \
+                (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
+#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL    20
+#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL    0x00300000
+#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v)  \
+                (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT   0x0
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER     0x1
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST    0x2
+#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD3     0x00080000
+#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS        0x00040000
+#define BM_CLKCTRL_PLL1CTRL0_POWER      0x00020000
+#define BP_CLKCTRL_PLL1CTRL0_RSRVD1     0
+#define BM_CLKCTRL_PLL1CTRL0_RSRVD1     0x0001FFFF
+#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
+
+#define HW_CLKCTRL_PLL1CTRL1    (0x00000030)
+
+#define BM_CLKCTRL_PLL1CTRL1_LOCK       0x80000000
+#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
+#define BP_CLKCTRL_PLL1CTRL1_RSRVD1     16
+#define BM_CLKCTRL_PLL1CTRL1_RSRVD1     0x3FFF0000
+#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v)  \
+                (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
+#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
+#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
+#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
+
+#define HW_CLKCTRL_PLL2CTRL0    (0x00000040)
+#define HW_CLKCTRL_PLL2CTRL0_SET        (0x00000044)
+#define HW_CLKCTRL_PLL2CTRL0_CLR        (0x00000048)
+#define HW_CLKCTRL_PLL2CTRL0_TOG        (0x0000004c)
+
+#define BM_CLKCTRL_PLL2CTRL0_CLKGATE    0x80000000
+#define BM_CLKCTRL_PLL2CTRL0_RSRVD3     0x40000000
+#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL    28
+#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL    0x30000000
+#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v)  \
+                (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
+#define BM_CLKCTRL_PLL2CTRL0_RSRVD2     0x08000000
+#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B    0x04000000
+#define BP_CLKCTRL_PLL2CTRL0_CP_SEL     24
+#define BM_CLKCTRL_PLL2CTRL0_CP_SEL     0x03000000
+#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v)  \
+                (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
+#define BM_CLKCTRL_PLL2CTRL0_POWER      0x00800000
+#define BP_CLKCTRL_PLL2CTRL0_RSRVD1     0
+#define BM_CLKCTRL_PLL2CTRL0_RSRVD1     0x007FFFFF
+#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
+
+#define HW_CLKCTRL_CPU  (0x00000050)
+#define HW_CLKCTRL_CPU_SET      (0x00000054)
+#define HW_CLKCTRL_CPU_CLR      (0x00000058)
+#define HW_CLKCTRL_CPU_TOG      (0x0000005c)
+
+#define BP_CLKCTRL_CPU_RSRVD5   30
+#define BM_CLKCTRL_CPU_RSRVD5   0xC0000000
+#define BF_CLKCTRL_CPU_RSRVD5(v) \
+                (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL    0x20000000
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU     0x10000000
+#define BM_CLKCTRL_CPU_RSRVD4   0x08000000
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
+#define BP_CLKCTRL_CPU_DIV_XTAL 16
+#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v)  \
+                (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
+#define BP_CLKCTRL_CPU_RSRVD3   13
+#define BM_CLKCTRL_CPU_RSRVD3   0x0000E000
+#define BF_CLKCTRL_CPU_RSRVD3(v)  \
+                (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT   0x00001000
+#define BM_CLKCTRL_CPU_RSRVD2   0x00000800
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN  0x00000400
+#define BP_CLKCTRL_CPU_RSRVD1   6
+#define BM_CLKCTRL_CPU_RSRVD1   0x000003C0
+#define BF_CLKCTRL_CPU_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
+#define BP_CLKCTRL_CPU_DIV_CPU  0
+#define BM_CLKCTRL_CPU_DIV_CPU  0x0000003F
+#define BF_CLKCTRL_CPU_DIV_CPU(v)  \
+                (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
+
+#define HW_CLKCTRL_HBUS (0x00000060)
+#define HW_CLKCTRL_HBUS_SET     (0x00000064)
+#define HW_CLKCTRL_HBUS_CLR     (0x00000068)
+#define HW_CLKCTRL_HBUS_TOG     (0x0000006c)
+
+#define BM_CLKCTRL_HBUS_ASM_BUSY        0x80000000
+#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE   0x40000000
+#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE   0x20000000
+#define BM_CLKCTRL_HBUS_RSRVD2  0x10000000
+#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE   0x08000000
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE       0x04000000
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE       0x02000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE   0x01000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE       0x00800000
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE      0x00400000
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE     0x00200000
+#define BM_CLKCTRL_HBUS_ASM_ENABLE      0x00100000
+#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE   0x00080000
+#define BP_CLKCTRL_HBUS_SLOW_DIV        16
+#define BM_CLKCTRL_HBUS_SLOW_DIV        0x00070000
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v)  \
+                (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1  0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2  0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4  0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8  0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
+#define BP_CLKCTRL_HBUS_RSRVD1  6
+#define BM_CLKCTRL_HBUS_RSRVD1  0x0000FFC0
+#define BF_CLKCTRL_HBUS_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN     0x00000020
+#define BP_CLKCTRL_HBUS_DIV     0
+#define BM_CLKCTRL_HBUS_DIV     0x0000001F
+#define BF_CLKCTRL_HBUS_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
+
+#define HW_CLKCTRL_XBUS (0x00000070)
+
+#define BM_CLKCTRL_XBUS_BUSY    0x80000000
+#define BP_CLKCTRL_XBUS_RSRVD1  12
+#define BM_CLKCTRL_XBUS_RSRVD1  0x7FFFF000
+#define BF_CLKCTRL_XBUS_RSRVD1(v)  \
+                (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
+#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE   0x00000800
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN     0x00000400
+#define BP_CLKCTRL_XBUS_DIV     0
+#define BM_CLKCTRL_XBUS_DIV     0x000003FF
+#define BF_CLKCTRL_XBUS_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
+
+#define HW_CLKCTRL_XTAL (0x00000080)
+#define HW_CLKCTRL_XTAL_SET     (0x00000084)
+#define HW_CLKCTRL_XTAL_CLR     (0x00000088)
+#define HW_CLKCTRL_XTAL_TOG     (0x0000008c)
+
+#define BP_CLKCTRL_XTAL_UART_CLK_GATE   31
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE   0x80000000
+#define BM_CLKCTRL_XTAL_RSRVD3  0x40000000
+#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
+#define BP_CLKCTRL_XTAL_RSRVD2  27
+#define BM_CLKCTRL_XTAL_RSRVD2  0x18000000
+#define BF_CLKCTRL_XTAL_RSRVD2(v)  \
+                (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
+#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      26
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE      0x04000000
+#define BP_CLKCTRL_XTAL_RSRVD1  2
+#define BM_CLKCTRL_XTAL_RSRVD1  0x03FFFFFC
+#define BF_CLKCTRL_XTAL_RSRVD1(v)  \
+                (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
+#define BP_CLKCTRL_XTAL_DIV_UART        0
+#define BM_CLKCTRL_XTAL_DIV_UART        0x00000003
+#define BF_CLKCTRL_XTAL_DIV_UART(v)  \
+                (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
+
+#define HW_CLKCTRL_SSP0 (0x00000090)
+
+#define BP_CLKCTRL_SSP0_CLKGATE 31
+#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP0_RSRVD2  0x40000000
+#define BM_CLKCTRL_SSP0_BUSY    0x20000000
+#define BP_CLKCTRL_SSP0_RSRVD1  10
+#define BM_CLKCTRL_SSP0_RSRVD1  0x1FFFFC00
+#define BF_CLKCTRL_SSP0_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
+#define BM_CLKCTRL_SSP0_DIV_FRAC_EN     0x00000200
+#define BP_CLKCTRL_SSP0_DIV     0
+#define BM_CLKCTRL_SSP0_DIV     0x000001FF
+#define BF_CLKCTRL_SSP0_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SSP0_DIV)
+
+#define HW_CLKCTRL_SSP1 (0x000000a0)
+
+#define BP_CLKCTRL_SSP1_CLKGATE 31
+#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP1_RSRVD2  0x40000000
+#define BM_CLKCTRL_SSP1_BUSY    0x20000000
+#define BP_CLKCTRL_SSP1_RSRVD1  10
+#define BM_CLKCTRL_SSP1_RSRVD1  0x1FFFFC00
+#define BF_CLKCTRL_SSP1_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
+#define BM_CLKCTRL_SSP1_DIV_FRAC_EN     0x00000200
+#define BP_CLKCTRL_SSP1_DIV     0
+#define BM_CLKCTRL_SSP1_DIV     0x000001FF
+#define BF_CLKCTRL_SSP1_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SSP1_DIV)
+
+#define HW_CLKCTRL_SSP2 (0x000000b0)
+
+#define BP_CLKCTRL_SSP2_CLKGATE 31
+#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP2_RSRVD2  0x40000000
+#define BM_CLKCTRL_SSP2_BUSY    0x20000000
+#define BP_CLKCTRL_SSP2_RSRVD1  10
+#define BM_CLKCTRL_SSP2_RSRVD1  0x1FFFFC00
+#define BF_CLKCTRL_SSP2_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
+#define BM_CLKCTRL_SSP2_DIV_FRAC_EN     0x00000200
+#define BP_CLKCTRL_SSP2_DIV     0
+#define BM_CLKCTRL_SSP2_DIV     0x000001FF
+#define BF_CLKCTRL_SSP2_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SSP2_DIV)
+
+#define HW_CLKCTRL_SSP3 (0x000000c0)
+
+#define BP_CLKCTRL_SSP3_CLKGATE 31
+#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP3_RSRVD2  0x40000000
+#define BM_CLKCTRL_SSP3_BUSY    0x20000000
+#define BP_CLKCTRL_SSP3_RSRVD1  10
+#define BM_CLKCTRL_SSP3_RSRVD1  0x1FFFFC00
+#define BF_CLKCTRL_SSP3_RSRVD1(v)  \
+                (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
+#define BM_CLKCTRL_SSP3_DIV_FRAC_EN     0x00000200
+#define BP_CLKCTRL_SSP3_DIV     0
+#define BM_CLKCTRL_SSP3_DIV     0x000001FF
+#define BF_CLKCTRL_SSP3_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SSP3_DIV)
+
+#define HW_CLKCTRL_GPMI (0x000000d0)
+
+#define BP_CLKCTRL_GPMI_CLKGATE 31
+#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
+#define BM_CLKCTRL_GPMI_RSRVD2  0x40000000
+#define BM_CLKCTRL_GPMI_BUSY    0x20000000
+#define BP_CLKCTRL_GPMI_RSRVD1  11
+#define BM_CLKCTRL_GPMI_RSRVD1  0x1FFFF800
+#define BF_CLKCTRL_GPMI_RSRVD1(v)  \
+                (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN     0x00000400
+#define BP_CLKCTRL_GPMI_DIV     0
+#define BM_CLKCTRL_GPMI_DIV     0x000003FF
+#define BF_CLKCTRL_GPMI_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
+
+#define HW_CLKCTRL_SPDIF        (0x000000e0)
+
+#define BP_CLKCTRL_SPDIF_CLKGATE        31
+#define BM_CLKCTRL_SPDIF_CLKGATE        0x80000000
+#define BP_CLKCTRL_SPDIF_RSRVD  0
+#define BM_CLKCTRL_SPDIF_RSRVD  0x7FFFFFFF
+#define BF_CLKCTRL_SPDIF_RSRVD(v)  \
+                (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
+
+#define HW_CLKCTRL_EMI  (0x000000f0)
+
+#define BP_CLKCTRL_EMI_CLKGATE  31
+#define BM_CLKCTRL_EMI_CLKGATE  0x80000000
+#define BM_CLKCTRL_EMI_SYNC_MODE_EN     0x40000000
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL    0x20000000
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI     0x10000000
+#define BM_CLKCTRL_EMI_BUSY_REF_CPU     0x08000000
+#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE   0x04000000
+#define BP_CLKCTRL_EMI_RSRVD3   18
+#define BM_CLKCTRL_EMI_RSRVD3   0x03FC0000
+#define BF_CLKCTRL_EMI_RSRVD3(v)  \
+                (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC  0x00020000
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE        0x00010000
+#define BP_CLKCTRL_EMI_RSRVD2   12
+#define BM_CLKCTRL_EMI_RSRVD2   0x0000F000
+#define BF_CLKCTRL_EMI_RSRVD2(v)  \
+                (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
+#define BP_CLKCTRL_EMI_DIV_XTAL 8
+#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v)  \
+                (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
+#define BP_CLKCTRL_EMI_RSRVD1   6
+#define BM_CLKCTRL_EMI_RSRVD1   0x000000C0
+#define BF_CLKCTRL_EMI_RSRVD1(v)  \
+                (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
+#define BP_CLKCTRL_EMI_DIV_EMI  0
+#define BM_CLKCTRL_EMI_DIV_EMI  0x0000003F
+#define BF_CLKCTRL_EMI_DIV_EMI(v)  \
+                (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
+
+#define HW_CLKCTRL_SAIF0        (0x00000100)
+
+#define BP_CLKCTRL_SAIF0_CLKGATE        31
+#define BM_CLKCTRL_SAIF0_CLKGATE        0x80000000
+#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
+#define BM_CLKCTRL_SAIF0_BUSY   0x20000000
+#define BP_CLKCTRL_SAIF0_RSRVD1 17
+#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
+#define BF_CLKCTRL_SAIF0_RSRVD1(v)  \
+                (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
+#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN    0x00010000
+#define BP_CLKCTRL_SAIF0_DIV    0
+#define BM_CLKCTRL_SAIF0_DIV    0x0000FFFF
+#define BF_CLKCTRL_SAIF0_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
+
+#define HW_CLKCTRL_SAIF1        (0x00000110)
+
+#define BP_CLKCTRL_SAIF1_CLKGATE        31
+#define BM_CLKCTRL_SAIF1_CLKGATE        0x80000000
+#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
+#define BM_CLKCTRL_SAIF1_BUSY   0x20000000
+#define BP_CLKCTRL_SAIF1_RSRVD1 17
+#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
+#define BF_CLKCTRL_SAIF1_RSRVD1(v)  \
+                (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
+#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN    0x00010000
+#define BP_CLKCTRL_SAIF1_DIV    0
+#define BM_CLKCTRL_SAIF1_DIV    0x0000FFFF
+#define BF_CLKCTRL_SAIF1_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
+
+#define HW_CLKCTRL_DIS_LCDIF    (0x00000120)
+
+#define BP_CLKCTRL_DIS_LCDIF_CLKGATE    31
+#define BM_CLKCTRL_DIS_LCDIF_CLKGATE    0x80000000
+#define BM_CLKCTRL_DIS_LCDIF_RSRVD2     0x40000000
+#define BM_CLKCTRL_DIS_LCDIF_BUSY       0x20000000
+#define BP_CLKCTRL_DIS_LCDIF_RSRVD1     14
+#define BM_CLKCTRL_DIS_LCDIF_RSRVD1     0x1FFFC000
+#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v)  \
+                (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
+#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN        0x00002000
+#define BP_CLKCTRL_DIS_LCDIF_DIV        0
+#define BM_CLKCTRL_DIS_LCDIF_DIV        0x00001FFF
+#define BF_CLKCTRL_DIS_LCDIF_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
+
+#define HW_CLKCTRL_ETM  (0x00000130)
+
+#define BM_CLKCTRL_ETM_CLKGATE  0x80000000
+#define BM_CLKCTRL_ETM_RSRVD2   0x40000000
+#define BM_CLKCTRL_ETM_BUSY     0x20000000
+#define BP_CLKCTRL_ETM_RSRVD1   8
+#define BM_CLKCTRL_ETM_RSRVD1   0x1FFFFF00
+#define BF_CLKCTRL_ETM_RSRVD1(v)  \
+                (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
+#define BM_CLKCTRL_ETM_DIV_FRAC_EN      0x00000080
+#define BP_CLKCTRL_ETM_DIV      0
+#define BM_CLKCTRL_ETM_DIV      0x0000007F
+#define BF_CLKCTRL_ETM_DIV(v)  \
+                (((v) << 0) & BM_CLKCTRL_ETM_DIV)
+
+#define HW_CLKCTRL_ENET (0x00000140)
+
+#define BM_CLKCTRL_ENET_SLEEP   0x80000000
+#define BP_CLKCTRL_ENET_DISABLE 30
+#define BM_CLKCTRL_ENET_DISABLE 0x40000000
+#define BM_CLKCTRL_ENET_STATUS  0x20000000
+#define BM_CLKCTRL_ENET_RSRVD1  0x10000000
+#define BM_CLKCTRL_ENET_BUSY_TIME       0x08000000
+#define BP_CLKCTRL_ENET_DIV_TIME        21
+#define BM_CLKCTRL_ENET_DIV_TIME        0x07E00000
+#define BF_CLKCTRL_ENET_DIV_TIME(v)  \
+                (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
+#define BM_CLKCTRL_ENET_BUSY    0x08000000
+#define BP_CLKCTRL_ENET_DIV     21
+#define BM_CLKCTRL_ENET_DIV     0x07E00000
+#define BF_CLKCTRL_ENET_DIV(v)  \
+                (((v) << 21) & BM_CLKCTRL_ENET_DIV)
+#define BP_CLKCTRL_ENET_TIME_SEL        19
+#define BM_CLKCTRL_ENET_TIME_SEL        0x00180000
+#define BF_CLKCTRL_ENET_TIME_SEL(v)  \
+                (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
+#define BV_CLKCTRL_ENET_TIME_SEL__XTAL      0x0
+#define BV_CLKCTRL_ENET_TIME_SEL__PLL       0x1
+#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK  0x2
+#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_ENET_CLK_OUT_EN      0x00040000
+#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP        0x00020000
+#define BM_CLKCTRL_ENET_RESET_BY_SW     0x00010000
+#define BP_CLKCTRL_ENET_RSRVD0  0
+#define BM_CLKCTRL_ENET_RSRVD0  0x0000FFFF
+#define BF_CLKCTRL_ENET_RSRVD0(v)  \
+                (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
+
+#define HW_CLKCTRL_HSADC        (0x00000150)
+
+#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
+#define BM_CLKCTRL_HSADC_RESETB 0x40000000
+#define BP_CLKCTRL_HSADC_FREQDIV        28
+#define BM_CLKCTRL_HSADC_FREQDIV        0x30000000
+#define BF_CLKCTRL_HSADC_FREQDIV(v)  \
+                (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
+#define BP_CLKCTRL_HSADC_RSRVD1 0
+#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
+#define BF_CLKCTRL_HSADC_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
+
+#define HW_CLKCTRL_FLEXCAN      (0x00000160)
+
+#define BM_CLKCTRL_FLEXCAN_RSRVD2       0x80000000
+#define BP_CLKCTRL_FLEXCAN_STOP_CAN0    30
+#define BM_CLKCTRL_FLEXCAN_STOP_CAN0    0x40000000
+#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS  0x20000000
+#define BP_CLKCTRL_FLEXCAN_STOP_CAN1    28
+#define BM_CLKCTRL_FLEXCAN_STOP_CAN1    0x10000000
+#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS  0x08000000
+#define BP_CLKCTRL_FLEXCAN_RSRVD1       0
+#define BM_CLKCTRL_FLEXCAN_RSRVD1       0x07FFFFFF
+#define BF_CLKCTRL_FLEXCAN_RSRVD1(v)  \
+                (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
+
+#define HW_CLKCTRL_FRAC0        (0x000001b0)
+#define HW_CLKCTRL_FRAC0_SET    (0x000001b4)
+#define HW_CLKCTRL_FRAC0_CLR    (0x000001b8)
+#define HW_CLKCTRL_FRAC0_TOG    (0x000001bc)
+
+#define BP_CLKCTRL_FRAC0_CLKGATEIO0     31
+#define BM_CLKCTRL_FRAC0_CLKGATEIO0     0x80000000
+#define BM_CLKCTRL_FRAC0_IO0_STABLE     0x40000000
+#define BP_CLKCTRL_FRAC0_IO0FRAC        24
+#define BM_CLKCTRL_FRAC0_IO0FRAC        0x3F000000
+#define BF_CLKCTRL_FRAC0_IO0FRAC(v)  \
+                (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
+#define BP_CLKCTRL_FRAC0_CLKGATEIO1     23
+#define BM_CLKCTRL_FRAC0_CLKGATEIO1     0x00800000
+#define BM_CLKCTRL_FRAC0_IO1_STABLE     0x00400000
+#define BP_CLKCTRL_FRAC0_IO1FRAC        16
+#define BM_CLKCTRL_FRAC0_IO1FRAC        0x003F0000
+#define BF_CLKCTRL_FRAC0_IO1FRAC(v)  \
+                (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
+#define BP_CLKCTRL_FRAC0_CLKGATEEMI     15
+#define BM_CLKCTRL_FRAC0_CLKGATEEMI     0x00008000
+#define BM_CLKCTRL_FRAC0_EMI_STABLE     0x00004000
+#define BP_CLKCTRL_FRAC0_EMIFRAC        8
+#define BM_CLKCTRL_FRAC0_EMIFRAC        0x00003F00
+#define BF_CLKCTRL_FRAC0_EMIFRAC(v)  \
+                (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
+#define BP_CLKCTRL_FRAC0_CLKGATECPU     7
+#define BM_CLKCTRL_FRAC0_CLKGATECPU     0x00000080
+#define BM_CLKCTRL_FRAC0_CPU_STABLE     0x00000040
+#define BP_CLKCTRL_FRAC0_CPUFRAC        0
+#define BM_CLKCTRL_FRAC0_CPUFRAC        0x0000003F
+#define BF_CLKCTRL_FRAC0_CPUFRAC(v)  \
+                (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
+
+#define HW_CLKCTRL_FRAC1        (0x000001c0)
+#define HW_CLKCTRL_FRAC1_SET    (0x000001c4)
+#define HW_CLKCTRL_FRAC1_CLR    (0x000001c8)
+#define HW_CLKCTRL_FRAC1_TOG    (0x000001cc)
+
+#define BP_CLKCTRL_FRAC1_RSRVD2 24
+#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
+#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
+                (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
+#define BP_CLKCTRL_FRAC1_CLKGATEGPMI    23
+#define BM_CLKCTRL_FRAC1_CLKGATEGPMI    0x00800000
+#define BM_CLKCTRL_FRAC1_GPMI_STABLE    0x00400000
+#define BP_CLKCTRL_FRAC1_GPMIFRAC       16
+#define BM_CLKCTRL_FRAC1_GPMIFRAC       0x003F0000
+#define BF_CLKCTRL_FRAC1_GPMIFRAC(v)  \
+                (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
+#define BP_CLKCTRL_FRAC1_CLKGATEHSADC   15
+#define BM_CLKCTRL_FRAC1_CLKGATEHSADC   0x00008000
+#define BM_CLKCTRL_FRAC1_HSADC_STABLE   0x00004000
+#define BP_CLKCTRL_FRAC1_HSADCFRAC      8
+#define BM_CLKCTRL_FRAC1_HSADCFRAC      0x00003F00
+#define BF_CLKCTRL_FRAC1_HSADCFRAC(v)  \
+                (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
+#define BP_CLKCTRL_FRAC1_CLKGATEPIX     7
+#define BM_CLKCTRL_FRAC1_CLKGATEPIX     0x00000080
+#define BM_CLKCTRL_FRAC1_PIX_STABLE     0x00000040
+#define BP_CLKCTRL_FRAC1_PIXFRAC        0
+#define BM_CLKCTRL_FRAC1_PIXFRAC        0x0000003F
+#define BF_CLKCTRL_FRAC1_PIXFRAC(v)  \
+                (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
+
+#define HW_CLKCTRL_CLKSEQ       (0x000001d0)
+#define HW_CLKCTRL_CLKSEQ_SET   (0x000001d4)
+#define HW_CLKCTRL_CLKSEQ_CLR   (0x000001d8)
+#define HW_CLKCTRL_CLKSEQ_TOG   (0x000001dc)
+
+#define BP_CLKCTRL_CLKSEQ_RSRVD0        19
+#define BM_CLKCTRL_CLKSEQ_RSRVD0        0xFFF80000
+#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
+                (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU    0x00040000
+#define BP_CLKCTRL_CLKSEQ_RSRVD1        15
+#define BM_CLKCTRL_CLKSEQ_RSRVD1        0x00038000
+#define BF_CLKCTRL_CLKSEQ_RSRVD1(v)  \
+                (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF      0x00004000
+#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
+#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD    0x0
+#define BP_CLKCTRL_CLKSEQ_RSRVD2        9
+#define BM_CLKCTRL_CLKSEQ_RSRVD2        0x00003E00
+#define BF_CLKCTRL_CLKSEQ_RSRVD2(v)  \
+                (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM    0x00000100
+#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI    0x00000080
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3   0x00000040
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2   0x00000020
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1   0x00000010
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0   0x00000008
+#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI   0x00000004
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1  0x00000002
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0  0x00000001
+
+#define HW_CLKCTRL_RESET        (0x000001e0)
+
+#define BP_CLKCTRL_RESET_RSRVD  6
+#define BM_CLKCTRL_RESET_RSRVD  0xFFFFFFC0
+#define BF_CLKCTRL_RESET_RSRVD(v) \
+                (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
+#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE       0x00000020
+#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE  0x00000010
+#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE   0x00000008
+#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT  0x00000004
+#define BM_CLKCTRL_RESET_CHIP   0x00000002
+#define BM_CLKCTRL_RESET_DIG    0x00000001
+
+#define HW_CLKCTRL_STATUS       (0x000001f0)
+
+#define BP_CLKCTRL_STATUS_CPU_LIMIT     30
+#define BM_CLKCTRL_STATUS_CPU_LIMIT     0xC0000000
+#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
+                (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
+#define BP_CLKCTRL_STATUS_RSRVD 0
+#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
+#define BF_CLKCTRL_STATUS_RSRVD(v)  \
+                (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
+
+#define HW_CLKCTRL_VERSION      (0x00000200)
+
+#define BP_CLKCTRL_VERSION_MAJOR        24
+#define BM_CLKCTRL_VERSION_MAJOR        0xFF000000
+#define BF_CLKCTRL_VERSION_MAJOR(v) \
+                (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
+#define BP_CLKCTRL_VERSION_MINOR        16
+#define BM_CLKCTRL_VERSION_MINOR        0x00FF0000
+#define BF_CLKCTRL_VERSION_MINOR(v)  \
+                (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
+#define BP_CLKCTRL_VERSION_STEP 0
+#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
+#define BF_CLKCTRL_VERSION_STEP(v)  \
+                (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
+
+#endif /* __REGS_CLKCTRL_MX28_H__ */
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
new file mode 100644
index 000000000000..9343d7edd4f6
--- /dev/null
+++ b/arch/arm/mach-mxs/system.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+
+#include <asm/proc-fns.h>
+#include <asm/system.h>
+
+#include <mach/mxs.h>
+#include <mach/common.h>
+
+#define MX23_CLKCTRL_RESET_OFFSET       0x120
+#define MX28_CLKCTRL_RESET_OFFSET       0x1e0
+#define MXS_CLKCTRL_RESET_CHIP          (1 << 1)
+
+#define MXS_MODULE_CLKGATE              (1 << 30)
+#define MXS_MODULE_SFTRST               (1 << 31)
+
+static void __iomem *mxs_clkctrl_reset_addr;
+
+/*
+ * Reset the system. It is called by machine_restart().
+ */
+void arch_reset(char mode, const char *cmd)
+{
+        /* reset the chip */
+        __mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr);
+
+        pr_err("Failed to assert the chip reset\n");
+
+        /* Delay to allow the serial port to show the message */
+        mdelay(50);
+
+        /* We'll take a jump through zero as a poor second */
+        cpu_reset(0);
+}
+
+static int __init mxs_arch_reset_init(void)
+{
+        struct clk *clk;
+
+        mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) +
+                                (cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET :
+                                                 MX28_CLKCTRL_RESET_OFFSET);
+
+        clk = clk_get_sys("rtc", NULL);
+        if (!IS_ERR(clk))
+                clk_enable(clk);
+
+        return 0;
+}
+core_initcall(mxs_arch_reset_init);
+
+/*
+ * Clear the bit and poll it cleared.  This is usually called with
+ * a reset address and mask being either SFTRST(bit 31) or CLKGATE
+ * (bit 30).
+ */
+static int clear_poll_bit(void __iomem *addr, u32 mask)
+{
+        int timeout = 0x400;
+
+        /* clear the bit */
+        __mxs_clrl(mask, addr);
+
+        /*
+         * SFTRST needs 3 GPMI clocks to settle, the reference manual
+         * recommends to wait 1us.
+         */
+        udelay(1);
+
+        /* poll the bit becoming clear */
+        while ((__raw_readl(addr) & mask) && --timeout)
+                /* nothing */;
+
+        return !timeout;
+}
+
+int mxs_reset_block(void __iomem *reset_addr)
+{
+        int ret;
+        int timeout = 0x400;
+
+        /* clear and poll SFTRST */
+        ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
+        if (unlikely(ret))
+                goto error;
+
+        /* clear CLKGATE */
+        __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr);
+
+        /* set SFTRST to reset the block */
+        __mxs_setl(MXS_MODULE_SFTRST, reset_addr);
+        udelay(1);
+
+        /* poll CLKGATE becoming set */
+        while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout)
+                /* nothing */;
+        if (unlikely(!timeout))
+                goto error;
+
+        /* clear and poll SFTRST */
+        ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
+        if (unlikely(ret))
+                goto error;
+
+        /* clear and poll CLKGATE */
+        ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE);
+        if (unlikely(ret))
+                goto error;
+
+        return 0;
+
+error:
+        pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
+        return -ETIMEDOUT;
+}
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
new file mode 100644
index 000000000000..13647f301860
--- /dev/null
+++ b/arch/arm/mach-mxs/timer.c
@@ -0,0 +1,296 @@
+/*
+ *  Copyright (C) 2000-2001 Deep Blue Solutions
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
+ *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clk.h>
+
+#include <asm/mach/time.h>
+#include <mach/mxs.h>
+#include <mach/common.h>
+
+/*
+ * There are 2 versions of the timrot on Freescale MXS-based SoCs.
+ * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
+ * extends the counter to 32 bits.
+ *
+ * The implementation uses two timers, one for clock_event and
+ * another for clocksource. MX28 uses timrot 0 and 1, while MX23
+ * uses 0 and 2.
+ */
+
+#define MX23_TIMROT_VERSION_OFFSET      0x0a0
+#define MX28_TIMROT_VERSION_OFFSET      0x120
+#define BP_TIMROT_MAJOR_VERSION         24
+#define BV_TIMROT_VERSION_1             0x01
+#define BV_TIMROT_VERSION_2             0x02
+#define timrot_is_v1()  (timrot_major_version == BV_TIMROT_VERSION_1)
+
+/*
+ * There are 4 registers for each timrotv2 instance, and 2 registers
+ * for each timrotv1. So address step 0x40 in macros below strides
+ * one instance of timrotv2 while two instances of timrotv1.
+ *
+ * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
+ * on MX28 while timrot2 on MX23.
+ */
+/* common between v1 and v2 */
+#define HW_TIMROT_ROTCTRL               0x00
+#define HW_TIMROT_TIMCTRLn(n)           (0x20 + (n) * 0x40)
+/* v1 only */
+#define HW_TIMROT_TIMCOUNTn(n)          (0x30 + (n) * 0x40)
+/* v2 only */
+#define HW_TIMROT_RUNNING_COUNTn(n)     (0x30 + (n) * 0x40)
+#define HW_TIMROT_FIXED_COUNTn(n)       (0x40 + (n) * 0x40)
+
+#define BM_TIMROT_TIMCTRLn_RELOAD       (1 << 6)
+#define BM_TIMROT_TIMCTRLn_UPDATE       (1 << 7)
+#define BM_TIMROT_TIMCTRLn_IRQ_EN       (1 << 14)
+#define BM_TIMROT_TIMCTRLn_IRQ          (1 << 15)
+#define BP_TIMROT_TIMCTRLn_SELECT       0
+#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
+#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
+
+static struct clock_event_device mxs_clockevent_device;
+static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
+
+static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
+static u32 timrot_major_version;
+
+static inline void timrot_irq_disable(void)
+{
+        __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
+                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+}
+
+static inline void timrot_irq_enable(void)
+{
+        __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
+                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+}
+
+static void timrot_irq_acknowledge(void)
+{
+        __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
+                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+}
+
+static cycle_t timrotv1_get_cycles(struct clocksource *cs)
+{
+        return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
+                        & 0xffff0000) >> 16);
+}
+
+static cycle_t timrotv2_get_cycles(struct clocksource *cs)
+{
+        return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
+}
+
+static int timrotv1_set_next_event(unsigned long evt,
+                                        struct clock_event_device *dev)
+{
+        /* timrot decrements the count */
+        __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
+
+        return 0;
+}
+
+static int timrotv2_set_next_event(unsigned long evt,
+                                        struct clock_event_device *dev)
+{
+        /* timrot decrements the count */
+        __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
+
+        return 0;
+}
+
+static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+
+        timrot_irq_acknowledge();
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction mxs_timer_irq = {
+        .name           = "MXS Timer Tick",
+        .dev_id         = &mxs_clockevent_device,
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = mxs_timer_interrupt,
+};
+
+#ifdef DEBUG
+static const char *clock_event_mode_label[] const = {
+        [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
+        [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
+        [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
+        [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
+};
+#endif /* DEBUG */
+
+static void mxs_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *evt)
+{
+        /* Disable interrupt in timer module */
+        timrot_irq_disable();
+
+        if (mode != mxs_clockevent_mode) {
+                /* Set event time into the furthest future */
+                if (timrot_is_v1())
+                        __raw_writel(0xffff,
+                                mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
+                else
+                        __raw_writel(0xffffffff,
+                                mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
+
+                /* Clear pending interrupt */
+                timrot_irq_acknowledge();
+        }
+
+#ifdef DEBUG
+        pr_info("%s: changing mode from %s to %s\n", __func__,
+                clock_event_mode_label[mxs_clockevent_mode],
+                clock_event_mode_label[mode]);
+#endif /* DEBUG */
+
+        /* Remember timer mode */
+        mxs_clockevent_mode = mode;
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                pr_err("%s: Periodic mode is not implemented\n", __func__);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                timrot_irq_enable();
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                /* Left event sources disabled, no more interrupts appear */
+                break;
+        }
+}
+
+static struct clock_event_device mxs_clockevent_device = {
+        .name           = "mxs_timrot",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .set_mode       = mxs_set_mode,
+        .set_next_event = timrotv2_set_next_event,
+        .rating         = 200,
+};
+
+static int __init mxs_clockevent_init(struct clk *timer_clk)
+{
+        unsigned int c = clk_get_rate(timer_clk);
+
+        mxs_clockevent_device.mult =
+                div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
+        mxs_clockevent_device.cpumask = cpumask_of(0);
+        if (timrot_is_v1()) {
+                mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
+                mxs_clockevent_device.max_delta_ns =
+                        clockevent_delta2ns(0xfffe, &mxs_clockevent_device);
+                mxs_clockevent_device.min_delta_ns =
+                        clockevent_delta2ns(0xf, &mxs_clockevent_device);
+        } else {
+                mxs_clockevent_device.max_delta_ns =
+                        clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
+                mxs_clockevent_device.min_delta_ns =
+                        clockevent_delta2ns(0xf, &mxs_clockevent_device);
+        }
+
+        clockevents_register_device(&mxs_clockevent_device);
+
+        return 0;
+}
+
+static struct clocksource clocksource_mxs = {
+        .name           = "mxs_timer",
+        .rating         = 200,
+        .read           = timrotv2_get_cycles,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int __init mxs_clocksource_init(struct clk *timer_clk)
+{
+        unsigned int c = clk_get_rate(timer_clk);
+
+        if (timrot_is_v1()) {
+                clocksource_mxs.read = timrotv1_get_cycles;
+                clocksource_mxs.mask = CLOCKSOURCE_MASK(16);
+        }
+
+        clocksource_register_hz(&clocksource_mxs, c);
+
+        return 0;
+}
+
+void __init mxs_timer_init(struct clk *timer_clk, int irq)
+{
+        clk_enable(timer_clk);
+
+        /*
+         * Initialize timers to a known state
+         */
+        mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
+
+        /* get timrot version */
+        timrot_major_version = __raw_readl(mxs_timrot_base +
+                                (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
+                                                MX28_TIMROT_VERSION_OFFSET));
+        timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
+
+        /* one for clock_event */
+        __raw_writel((timrot_is_v1() ?
+                        BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
+                        BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
+                        BM_TIMROT_TIMCTRLn_UPDATE |
+                        BM_TIMROT_TIMCTRLn_IRQ_EN,
+                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+
+        /* another for clocksource */
+        __raw_writel((timrot_is_v1() ?
+                        BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
+                        BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
+                        BM_TIMROT_TIMCTRLn_RELOAD,
+                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
+
+        /* set clocksource timer fixed count to the maximum */
+        if (timrot_is_v1())
+                __raw_writel(0xffff,
+                        mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
+        else
+                __raw_writel(0xffffffff,
+                        mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
+
+        /* init and register the timer to the framework */
+        mxs_clocksource_init(timer_clk);
+        mxs_clockevent_init(timer_clk);
+
+        /* Make irqs happen */
+        setup_irq(irq, &mxs_timer_irq);
+}
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index 82801dbf0579..f12f22d09b6c 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -114,7 +114,6 @@ static struct clocksource clocksource_netx = {
         .rating         = 200,
         .read           = netx_get_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -151,9 +150,7 @@ static void __init netx_timer_init(void)
         writel(NETX_GPIO_COUNTER_CTRL_RUN,
                         NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
 
-        clocksource_netx.mult =
-                clocksource_hz2mult(CLOCK_TICK_RATE, clocksource_netx.shift);
-        clocksource_register(&clocksource_netx);
+        clocksource_register_hz(&clocksource_netx, CLOCK_TICK_RATE);
 
         netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
                         netx_clockevent.shift);
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c
index 89f793adf776..48a59f24e10c 100644
--- a/arch/arm/mach-nomadik/clock.c
+++ b/arch/arm/mach-nomadik/clock.c
@@ -7,7 +7,7 @@
 #include <linux/module.h>
 #include <linux/errno.h>
 #include <linux/clk.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include "clock.h"
 
 /*
diff --git a/arch/arm/mach-ns9xxx/time-ns9360.c b/arch/arm/mach-ns9xxx/time-ns9360.c
index 77281260358a..9ca32f55728b 100644
--- a/arch/arm/mach-ns9xxx/time-ns9360.c
+++ b/arch/arm/mach-ns9xxx/time-ns9360.c
@@ -35,7 +35,6 @@ static struct clocksource ns9360_clocksource = {
         .rating = 300,
         .read   = ns9360_clocksource_read,
         .mask   = CLOCKSOURCE_MASK(32),
-        .shift  = 20,
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -148,10 +147,7 @@ static void __init ns9360_timer_init(void)
 
         __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
 
-        ns9360_clocksource.mult = clocksource_hz2mult(ns9360_cpuclock(),
-                        ns9360_clocksource.shift);
-
-        clocksource_register(&ns9360_clocksource);
+        clocksource_register_hz(&ns9360_clocksource, ns9360_cpuclock());
 
         latch = SH_DIV(ns9360_cpuclock(), HZ, 0);
 
diff --git a/arch/arm/mach-nuc93x/clock.h b/arch/arm/mach-nuc93x/clock.h
index 18e51be4816f..4de1f1da9dc5 100644
--- a/arch/arm/mach-nuc93x/clock.h
+++ b/arch/arm/mach-nuc93x/clock.h
@@ -10,7 +10,7 @@
  * the Free Software Foundation; either version 2 of the License.
  */
 
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 void nuc93x_clk_enable(struct clk *clk, int enable);
 void clks_register(struct clk_lookup *clks, size_t num);
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 5f6496375404..8d2f2daba0c0 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -152,20 +152,11 @@ config MACH_NOKIA770
 config MACH_AMS_DELTA
         bool "Amstrad E3 (Delta)"
         depends on ARCH_OMAP1 && ARCH_OMAP15XX
+        select FIQ
         help
           Support for the Amstrad E3 (codename Delta) videophone. Say Y here
           if you have such a device.
 
-config AMS_DELTA_FIQ
-        bool "Fast Interrupt Request (FIQ) support for the E3"
-        depends on MACH_AMS_DELTA
-        select FIQ
-        help
-          Provide a FIQ handler for the E3.
-          This allows for fast handling of interrupts generated
-          by the clock line of the E3 mailboard (or a PS/2 keyboard)
-          connected to the GPIO based external keyboard port.
-
 config MACH_OMAP_GENERIC
         bool "Generic OMAP board"
         depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 9a304d854e33..6ee19504845f 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o
+obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o
 obj-y += clock.o clock_data.o opp_data.o
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
@@ -39,8 +39,8 @@ obj-$(CONFIG_MACH_OMAP_PALMTE)		+= board-palmte.o
 obj-$(CONFIG_MACH_OMAP_PALMZ71)         += board-palmz71.o
 obj-$(CONFIG_MACH_OMAP_PALMTT)          += board-palmtt.o
 obj-$(CONFIG_MACH_NOKIA770)             += board-nokia770.o
-obj-$(CONFIG_MACH_AMS_DELTA)            += board-ams-delta.o
-obj-$(CONFIG_AMS_DELTA_FIQ)             += ams-delta-fiq.o ams-delta-fiq-handler.o
+obj-$(CONFIG_MACH_AMS_DELTA)            += board-ams-delta.o ams-delta-fiq.o \
+                                           ams-delta-fiq-handler.o
 obj-$(CONFIG_MACH_SX1)                  += board-sx1.o board-sx1-mmc.o
 obj-$(CONFIG_MACH_HERALD)               += board-htcherald.o
 
@@ -49,6 +49,12 @@ ifeq ($(CONFIG_ARCH_OMAP15XX),y)
 obj-$(CONFIG_MACH_OMAP_INNOVATOR)       += fpga.o
 endif
 
+# GPIO
+obj-$(CONFIG_ARCH_OMAP730)              += gpio7xx.o
+obj-$(CONFIG_ARCH_OMAP850)              += gpio7xx.o
+obj-$(CONFIG_ARCH_OMAP15XX)             += gpio15xx.o
+obj-$(CONFIG_ARCH_OMAP16XX)             += gpio16xx.o
+
 # LEDs support
 led-$(CONFIG_MACH_OMAP_H2)              += leds-h2p2-debug.o
 led-$(CONFIG_MACH_OMAP_H3)              += leds-h2p2-debug.o
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 1d4163b9f0b7..bd0495a9ac3b 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -28,6 +28,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
+#include <plat/io.h>
 #include <plat/board-ams-delta.h>
 #include <mach/gpio.h>
 #include <plat/keypad.h>
@@ -42,84 +43,82 @@
 static u8 ams_delta_latch1_reg;
 static u16 ams_delta_latch2_reg;
 
-static int ams_delta_keymap[] = {
+static const unsigned int ams_delta_keymap[] = {
         KEY(0, 0, KEY_F1),              /* Advert    */
 
-        KEY(3, 0, KEY_COFFEE),          /* Games     */
-        KEY(2, 0, KEY_QUESTION),        /* Directory */
-        KEY(3, 2, KEY_CONNECT),         /* Internet  */
-        KEY(2, 1, KEY_SHOP),            /* Services  */
+        KEY(0, 3, KEY_COFFEE),          /* Games     */
+        KEY(0, 2, KEY_QUESTION),        /* Directory */
+        KEY(2, 3, KEY_CONNECT),         /* Internet  */
+        KEY(1, 2, KEY_SHOP),            /* Services  */
         KEY(1, 1, KEY_PHONE),           /* VoiceMail */
 
-        KEY(1, 0, KEY_DELETE),          /* Delete    */
+        KEY(0, 1, KEY_DELETE),          /* Delete    */
         KEY(2, 2, KEY_PLAY),            /* Play      */
-        KEY(0, 1, KEY_PAGEUP),          /* Up        */
-        KEY(3, 1, KEY_PAGEDOWN),        /* Down      */
-        KEY(0, 2, KEY_EMAIL),           /* ReadEmail */
-        KEY(1, 2, KEY_STOP),            /* Stop      */
+        KEY(1, 0, KEY_PAGEUP),          /* Up        */
+        KEY(1, 3, KEY_PAGEDOWN),        /* Down      */
+        KEY(2, 0, KEY_EMAIL),           /* ReadEmail */
+        KEY(2, 1, KEY_STOP),            /* Stop      */
 
         /* Numeric keypad portion */
-        KEY(7, 0, KEY_KP1),
-        KEY(6, 0, KEY_KP2),
-        KEY(5, 0, KEY_KP3),
-        KEY(7, 1, KEY_KP4),
-        KEY(6, 1, KEY_KP5),
-        KEY(5, 1, KEY_KP6),
-        KEY(7, 2, KEY_KP7),
-        KEY(6, 2, KEY_KP8),
-        KEY(5, 2, KEY_KP9),
-        KEY(6, 3, KEY_KP0),
-        KEY(7, 3, KEY_KPASTERISK),
-        KEY(5, 3, KEY_KPDOT),           /* # key     */
-        KEY(2, 7, KEY_NUMLOCK),         /* Mute      */
-        KEY(1, 7, KEY_KPMINUS),         /* Recall    */
-        KEY(1, 6, KEY_KPPLUS),          /* Redial    */
-        KEY(6, 7, KEY_KPSLASH),         /* Handsfree */
-        KEY(0, 6, KEY_ENTER),           /* Video     */
-
-        KEY(4, 7, KEY_CAMERA),          /* Photo     */
-
-        KEY(4, 0, KEY_F2),              /* Home      */
-        KEY(4, 1, KEY_F3),              /* Office    */
-        KEY(4, 2, KEY_F4),              /* Mobile    */
+        KEY(0, 7, KEY_KP1),
+        KEY(0, 6, KEY_KP2),
+        KEY(0, 5, KEY_KP3),
+        KEY(1, 7, KEY_KP4),
+        KEY(1, 6, KEY_KP5),
+        KEY(1, 5, KEY_KP6),
+        KEY(2, 7, KEY_KP7),
+        KEY(2, 6, KEY_KP8),
+        KEY(2, 5, KEY_KP9),
+        KEY(3, 6, KEY_KP0),
+        KEY(3, 7, KEY_KPASTERISK),
+        KEY(3, 5, KEY_KPDOT),           /* # key     */
+        KEY(7, 2, KEY_NUMLOCK),         /* Mute      */
+        KEY(7, 1, KEY_KPMINUS),         /* Recall    */
+        KEY(6, 1, KEY_KPPLUS),          /* Redial    */
+        KEY(7, 6, KEY_KPSLASH),         /* Handsfree */
+        KEY(6, 0, KEY_ENTER),           /* Video     */
+
+        KEY(7, 4, KEY_CAMERA),          /* Photo     */
+
+        KEY(0, 4, KEY_F2),              /* Home      */
+        KEY(1, 4, KEY_F3),              /* Office    */
+        KEY(2, 4, KEY_F4),              /* Mobile    */
         KEY(7, 7, KEY_F5),              /* SMS       */
-        KEY(5, 7, KEY_F6),              /* Email     */
+        KEY(7, 5, KEY_F6),              /* Email     */
 
         /* QWERTY portion of keypad */
-        KEY(4, 3, KEY_Q),
+        KEY(3, 4, KEY_Q),
         KEY(3, 3, KEY_W),
-        KEY(2, 3, KEY_E),
-        KEY(1, 3, KEY_R),
-        KEY(0, 3, KEY_T),
-        KEY(7, 4, KEY_Y),
-        KEY(6, 4, KEY_U),
-        KEY(5, 4, KEY_I),
+        KEY(3, 2, KEY_E),
+        KEY(3, 1, KEY_R),
+        KEY(3, 0, KEY_T),
+        KEY(4, 7, KEY_Y),
+        KEY(4, 6, KEY_U),
+        KEY(4, 5, KEY_I),
         KEY(4, 4, KEY_O),
-        KEY(3, 4, KEY_P),
+        KEY(4, 3, KEY_P),
 
-        KEY(2, 4, KEY_A),
-        KEY(1, 4, KEY_S),
-        KEY(0, 4, KEY_D),
-        KEY(7, 5, KEY_F),
-        KEY(6, 5, KEY_G),
+        KEY(4, 2, KEY_A),
+        KEY(4, 1, KEY_S),
+        KEY(4, 0, KEY_D),
+        KEY(5, 7, KEY_F),
+        KEY(5, 6, KEY_G),
         KEY(5, 5, KEY_H),
-        KEY(4, 5, KEY_J),
-        KEY(3, 5, KEY_K),
-        KEY(2, 5, KEY_L),
+        KEY(5, 4, KEY_J),
+        KEY(5, 3, KEY_K),
+        KEY(5, 2, KEY_L),
 
-        KEY(1, 5, KEY_Z),
-        KEY(0, 5, KEY_X),
-        KEY(7, 6, KEY_C),
+        KEY(5, 1, KEY_Z),
+        KEY(5, 0, KEY_X),
+        KEY(6, 7, KEY_C),
         KEY(6, 6, KEY_V),
-        KEY(5, 6, KEY_B),
-        KEY(4, 6, KEY_N),
-        KEY(3, 6, KEY_M),
-        KEY(2, 6, KEY_SPACE),
+        KEY(6, 5, KEY_B),
+        KEY(6, 4, KEY_N),
+        KEY(6, 3, KEY_M),
+        KEY(6, 2, KEY_SPACE),
 
-        KEY(0, 7, KEY_LEFTSHIFT),       /* Vol up    */
-        KEY(3, 7, KEY_LEFTCTRL),        /* Vol down  */
-
-        0
+        KEY(7, 0, KEY_LEFTSHIFT),       /* Vol up    */
+        KEY(7, 3, KEY_LEFTCTRL),        /* Vol down  */
 };
 
 void ams_delta_latch1_write(u8 mask, u8 value)
@@ -140,7 +139,6 @@ static void __init ams_delta_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static struct map_desc ams_delta_io_desc[] __initdata = {
@@ -189,11 +187,15 @@ static struct resource ams_delta_kp_resources[] = {
         },
 };
 
+static const struct matrix_keymap_data ams_delta_keymap_data = {
+        .keymap         = ams_delta_keymap,
+        .keymap_size    = ARRAY_SIZE(ams_delta_keymap),
+};
+
 static struct omap_kp_platform_data ams_delta_kp_data = {
         .rows           = 8,
         .cols           = 8,
-        .keymap         = ams_delta_keymap,
-        .keymapsize     = ARRAY_SIZE(ams_delta_keymap),
+        .keymap_data    = &ams_delta_keymap_data,
         .delay          = 9,
 };
 
@@ -307,16 +309,14 @@ static void __init ams_delta_init(void)
 #endif
         platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
 
-#ifdef CONFIG_AMS_DELTA_FIQ
         ams_delta_init_fiq();
-#endif
 
         omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
 }
 
 static struct plat_serial8250_port ams_delta_modem_ports[] = {
         {
-                .membase        = (void *) AMS_DELTA_MODEM_VIRT,
+                .membase        = IOMEM(AMS_DELTA_MODEM_VIRT),
                 .mapbase        = AMS_DELTA_MODEM_PHYS,
                 .irq            = -EINVAL, /* changed later */
                 .flags          = UPF_BOOT_AUTOCONF,
@@ -340,6 +340,9 @@ static int __init ams_delta_modem_init(void)
 {
         int err;
 
+        if (!machine_is_ams_delta())
+                return -ENODEV;
+
         omap_cfg_reg(M14_1510_GPIO2);
         ams_delta_modem_ports[0].irq =
                         gpio_to_irq(AMS_DELTA_GPIO_PIN_MODEM_IRQ);
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 149fdd32e127..0efb9dbae44c 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -69,36 +69,35 @@
 #define fsample_cpld_clear(bit) \
     fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
 
-static int fsample_keymap[] = {
-        KEY(0,0,KEY_UP),
-        KEY(0,1,KEY_RIGHT),
-        KEY(0,2,KEY_LEFT),
-        KEY(0,3,KEY_DOWN),
-        KEY(0,4,KEY_ENTER),
-        KEY(1,0,KEY_F10),
-        KEY(1,1,KEY_SEND),
-        KEY(1,2,KEY_END),
-        KEY(1,3,KEY_VOLUMEDOWN),
-        KEY(1,4,KEY_VOLUMEUP),
-        KEY(1,5,KEY_RECORD),
-        KEY(2,0,KEY_F9),
-        KEY(2,1,KEY_3),
-        KEY(2,2,KEY_6),
-        KEY(2,3,KEY_9),
-        KEY(2,4,KEY_KPDOT),
-        KEY(3,0,KEY_BACK),
-        KEY(3,1,KEY_2),
-        KEY(3,2,KEY_5),
-        KEY(3,3,KEY_8),
-        KEY(3,4,KEY_0),
-        KEY(3,5,KEY_KPSLASH),
-        KEY(4,0,KEY_HOME),
-        KEY(4,1,KEY_1),
-        KEY(4,2,KEY_4),
-        KEY(4,3,KEY_7),
-        KEY(4,4,KEY_KPASTERISK),
-        KEY(4,5,KEY_POWER),
-        0
+static const unsigned int fsample_keymap[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(2, 0, KEY_LEFT),
+        KEY(3, 0, KEY_DOWN),
+        KEY(4, 0, KEY_ENTER),
+        KEY(0, 1, KEY_F10),
+        KEY(1, 1, KEY_SEND),
+        KEY(2, 1, KEY_END),
+        KEY(3, 1, KEY_VOLUMEDOWN),
+        KEY(4, 1, KEY_VOLUMEUP),
+        KEY(5, 1, KEY_RECORD),
+        KEY(0, 2, KEY_F9),
+        KEY(1, 2, KEY_3),
+        KEY(2, 2, KEY_6),
+        KEY(3, 2, KEY_9),
+        KEY(4, 2, KEY_KPDOT),
+        KEY(0, 3, KEY_BACK),
+        KEY(1, 3, KEY_2),
+        KEY(2, 3, KEY_5),
+        KEY(3, 3, KEY_8),
+        KEY(4, 3, KEY_0),
+        KEY(5, 3, KEY_KPSLASH),
+        KEY(0, 4, KEY_HOME),
+        KEY(1, 4, KEY_1),
+        KEY(2, 4, KEY_4),
+        KEY(3, 4, KEY_7),
+        KEY(4, 4, KEY_KPASTERISK),
+        KEY(5, 4, KEY_POWER),
 };
 
 static struct smc91x_platdata smc91x_info = {
@@ -120,6 +119,15 @@ static struct resource smc91x_resources[] = {
         },
 };
 
+static void __init fsample_init_smc91x(void)
+{
+        fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+        mdelay(50);
+        fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+                   H2P2_DBG_FPGA_LAN_RESET);
+        mdelay(50);
+}
+
 static struct mtd_partition nor_partitions[] = {
         /* bootloader (U-Boot, etc) in first sector */
         {
@@ -244,11 +252,15 @@ static struct resource kp_resources[] = {
         },
 };
 
+static const struct matrix_keymap_data fsample_keymap_data = {
+        .keymap         = fsample_keymap,
+        .keymap_size    = ARRAY_SIZE(fsample_keymap),
+};
+
 static struct omap_kp_platform_data kp_data = {
         .rows           = 8,
         .cols           = 8,
-        .keymap         = fsample_keymap,
-        .keymapsize     = ARRAY_SIZE(fsample_keymap),
+        .keymap_data    = &fsample_keymap_data,
         .delay          = 4,
 };
 
@@ -285,6 +297,8 @@ static struct omap_board_config_kernel fsample_config[] = {
 
 static void __init omap_fsample_init(void)
 {
+        fsample_init_smc91x();
+
         if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
                 BUG();
         gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
@@ -312,21 +326,10 @@ static void __init omap_fsample_init(void)
         omap_register_i2c_bus(1, 100, NULL, 0);
 }
 
-static void __init fsample_init_smc91x(void)
-{
-        fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
-        mdelay(50);
-        fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
-                   H2P2_DBG_FPGA_LAN_RESET);
-        mdelay(50);
-}
-
 static void __init omap_fsample_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
-        fsample_init_smc91x();
 }
 
 /* Only FPGA needs to be mapped here. All others are done with ioremap */
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 197adb49dc5a..28b84aa9bdba 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -52,43 +52,42 @@
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define OMAP1610_ETHR_START             0x04000300
 
-static int h2_keymap[] = {
+static const unsigned int h2_keymap[] = {
         KEY(0, 0, KEY_LEFT),
-        KEY(0, 1, KEY_RIGHT),
-        KEY(0, 2, KEY_3),
-        KEY(0, 3, KEY_F10),
-        KEY(0, 4, KEY_F5),
-        KEY(0, 5, KEY_9),
-        KEY(1, 0, KEY_DOWN),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(2, 0, KEY_3),
+        KEY(3, 0, KEY_F10),
+        KEY(4, 0, KEY_F5),
+        KEY(5, 0, KEY_9),
+        KEY(0, 1, KEY_DOWN),
         KEY(1, 1, KEY_UP),
-        KEY(1, 2, KEY_2),
-        KEY(1, 3, KEY_F9),
-        KEY(1, 4, KEY_F7),
-        KEY(1, 5, KEY_0),
-        KEY(2, 0, KEY_ENTER),
-        KEY(2, 1, KEY_6),
+        KEY(2, 1, KEY_2),
+        KEY(3, 1, KEY_F9),
+        KEY(4, 1, KEY_F7),
+        KEY(5, 1, KEY_0),
+        KEY(0, 2, KEY_ENTER),
+        KEY(1, 2, KEY_6),
         KEY(2, 2, KEY_1),
-        KEY(2, 3, KEY_F2),
-        KEY(2, 4, KEY_F6),
-        KEY(2, 5, KEY_HOME),
-        KEY(3, 0, KEY_8),
-        KEY(3, 1, KEY_5),
-        KEY(3, 2, KEY_F12),
+        KEY(3, 2, KEY_F2),
+        KEY(4, 2, KEY_F6),
+        KEY(5, 2, KEY_HOME),
+        KEY(0, 3, KEY_8),
+        KEY(1, 3, KEY_5),
+        KEY(2, 3, KEY_F12),
         KEY(3, 3, KEY_F3),
-        KEY(3, 4, KEY_F8),
-        KEY(3, 5, KEY_END),
-        KEY(4, 0, KEY_7),
-        KEY(4, 1, KEY_4),
-        KEY(4, 2, KEY_F11),
-        KEY(4, 3, KEY_F1),
+        KEY(4, 3, KEY_F8),
+        KEY(5, 3, KEY_END),
+        KEY(0, 4, KEY_7),
+        KEY(1, 4, KEY_4),
+        KEY(2, 4, KEY_F11),
+        KEY(3, 4, KEY_F1),
         KEY(4, 4, KEY_F4),
-        KEY(4, 5, KEY_ESC),
-        KEY(5, 0, KEY_F13),
-        KEY(5, 1, KEY_F14),
-        KEY(5, 2, KEY_F15),
-        KEY(5, 3, KEY_F16),
-        KEY(5, 4, KEY_SLEEP),
-        0
+        KEY(5, 4, KEY_ESC),
+        KEY(0, 5, KEY_F13),
+        KEY(1, 5, KEY_F14),
+        KEY(2, 5, KEY_F15),
+        KEY(3, 5, KEY_F16),
+        KEY(4, 5, KEY_SLEEP),
 };
 
 static struct mtd_partition h2_nor_partitions[] = {
@@ -270,14 +269,18 @@ static struct resource h2_kp_resources[] = {
         },
 };
 
+static const struct matrix_keymap_data h2_keymap_data = {
+        .keymap         = h2_keymap,
+        .keymap_size    = ARRAY_SIZE(h2_keymap),
+};
+
 static struct omap_kp_platform_data h2_kp_data = {
         .rows           = 8,
         .cols           = 8,
-        .keymap         = h2_keymap,
-        .keymapsize     = ARRAY_SIZE(h2_keymap),
-        .rep            = 1,
+        .keymap_data    = &h2_keymap_data,
+        .rep            = true,
         .delay          = 9,
-        .dbounce        = 1,
+        .dbounce        = true,
 };
 
 static struct platform_device h2_kp_device = {
@@ -374,8 +377,6 @@ static void __init h2_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
-        h2_init_smc91x();
 }
 
 static struct omap_usb_config h2_usb_config __initdata = {
@@ -403,6 +404,8 @@ static struct omap_board_config_kernel h2_config[] __initdata = {
 
 static void __init h2_init(void)
 {
+        h2_init_smc91x();
+
         /* Here we assume the NOR boot config:  NOR on CS3 (possibly swapped
          * to address 0 by a dip switch), NAND on CS2B.  The NAND driver will
          * notice whether a NAND chip is enabled at probe time.
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 9126e3e37b4a..dbc8b8d882ba 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -56,43 +56,42 @@
 
 #define H3_TS_GPIO      48
 
-static int h3_keymap[] = {
+static const unsigned int h3_keymap[] = {
         KEY(0, 0, KEY_LEFT),
-        KEY(0, 1, KEY_RIGHT),
-        KEY(0, 2, KEY_3),
-        KEY(0, 3, KEY_F10),
-        KEY(0, 4, KEY_F5),
-        KEY(0, 5, KEY_9),
-        KEY(1, 0, KEY_DOWN),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(2, 0, KEY_3),
+        KEY(3, 0, KEY_F10),
+        KEY(4, 0, KEY_F5),
+        KEY(5, 0, KEY_9),
+        KEY(0, 1, KEY_DOWN),
         KEY(1, 1, KEY_UP),
-        KEY(1, 2, KEY_2),
-        KEY(1, 3, KEY_F9),
-        KEY(1, 4, KEY_F7),
-        KEY(1, 5, KEY_0),
-        KEY(2, 0, KEY_ENTER),
-        KEY(2, 1, KEY_6),
+        KEY(2, 1, KEY_2),
+        KEY(3, 1, KEY_F9),
+        KEY(4, 1, KEY_F7),
+        KEY(5, 1, KEY_0),
+        KEY(0, 2, KEY_ENTER),
+        KEY(1, 2, KEY_6),
         KEY(2, 2, KEY_1),
-        KEY(2, 3, KEY_F2),
-        KEY(2, 4, KEY_F6),
-        KEY(2, 5, KEY_HOME),
-        KEY(3, 0, KEY_8),
-        KEY(3, 1, KEY_5),
-        KEY(3, 2, KEY_F12),
+        KEY(3, 2, KEY_F2),
+        KEY(4, 2, KEY_F6),
+        KEY(5, 2, KEY_HOME),
+        KEY(0, 3, KEY_8),
+        KEY(1, 3, KEY_5),
+        KEY(2, 3, KEY_F12),
         KEY(3, 3, KEY_F3),
-        KEY(3, 4, KEY_F8),
-        KEY(3, 5, KEY_END),
-        KEY(4, 0, KEY_7),
-        KEY(4, 1, KEY_4),
-        KEY(4, 2, KEY_F11),
-        KEY(4, 3, KEY_F1),
+        KEY(4, 3, KEY_F8),
+        KEY(5, 3, KEY_END),
+        KEY(0, 4, KEY_7),
+        KEY(1, 4, KEY_4),
+        KEY(2, 4, KEY_F11),
+        KEY(3, 4, KEY_F1),
         KEY(4, 4, KEY_F4),
-        KEY(4, 5, KEY_ESC),
-        KEY(5, 0, KEY_F13),
-        KEY(5, 1, KEY_F14),
-        KEY(5, 2, KEY_F15),
-        KEY(5, 3, KEY_F16),
-        KEY(5, 4, KEY_SLEEP),
-        0
+        KEY(5, 4, KEY_ESC),
+        KEY(0, 5, KEY_F13),
+        KEY(1, 5, KEY_F14),
+        KEY(2, 5, KEY_F15),
+        KEY(3, 5, KEY_F16),
+        KEY(4, 5, KEY_SLEEP),
 };
 
 
@@ -264,6 +263,15 @@ static struct platform_device smc91x_device = {
         .resource       = smc91x_resources,
 };
 
+static void __init h3_init_smc91x(void)
+{
+        omap_cfg_reg(W15_1710_GPIO40);
+        if (gpio_request(40, "SMC91x irq") < 0) {
+                printk("Error requesting gpio 40 for smc91x irq\n");
+                return;
+        }
+}
+
 #define GPTIMER_BASE            0xFFFB1400
 #define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800))
 #define GPTIMER_REGS_SIZE       0x46
@@ -296,14 +304,18 @@ static struct resource h3_kp_resources[] = {
         },
 };
 
+static const struct matrix_keymap_data h3_keymap_data = {
+        .keymap         = h3_keymap,
+        .keymap_size    = ARRAY_SIZE(h3_keymap),
+};
+
 static struct omap_kp_platform_data h3_kp_data = {
         .rows           = 8,
         .cols           = 8,
-        .keymap         = h3_keymap,
-        .keymapsize     = ARRAY_SIZE(h3_keymap),
-        .rep            = 1,
+        .keymap_data    = &h3_keymap_data,
+        .rep            = true,
         .delay          = 9,
-        .dbounce        = 1,
+        .dbounce        = true,
 };
 
 static struct platform_device h3_kp_device = {
@@ -376,6 +388,8 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = {
 
 static void __init h3_init(void)
 {
+        h3_init_smc91x();
+
         /* Here we assume the NOR boot config:  NOR on CS3 (possibly swapped
          * to address 0 by a dip switch), NAND on CS2B.  The NAND driver will
          * notice whether a NAND chip is enabled at probe time.
@@ -422,21 +436,10 @@ static void __init h3_init(void)
         h3_mmc_init();
 }
 
-static void __init h3_init_smc91x(void)
-{
-        omap_cfg_reg(W15_1710_GPIO40);
-        if (gpio_request(40, "SMC91x irq") < 0) {
-                printk("Error requesting gpio 40 for smc91x irq\n");
-                return;
-        }
-}
-
 static void __init h3_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
-        h3_init_smc91x();
 }
 
 static void __init h3_map_io(void)
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 071af3e47789..f2c5c585bc83 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -180,64 +180,68 @@
 
 /* Keyboard definition */
 
-static int htc_herald_keymap[] = {
+static const unsigned int htc_herald_keymap[] = {
         KEY(0, 0, KEY_RECORD), /* Mail button */
-        KEY(0, 1, KEY_CAMERA), /* Camera */
-        KEY(0, 2, KEY_PHONE), /* Send key */
-        KEY(0, 3, KEY_VOLUMEUP), /* Volume up */
-        KEY(0, 4, KEY_F2),  /* Right bar (landscape) */
-        KEY(0, 5, KEY_MAIL), /* Win key (portrait) */
-        KEY(0, 6, KEY_DIRECTORY), /* Right bar (protrait) */
-        KEY(1, 0, KEY_LEFTCTRL), /* Windows key */
+        KEY(1, 0, KEY_CAMERA), /* Camera */
+        KEY(2, 0, KEY_PHONE), /* Send key */
+        KEY(3, 0, KEY_VOLUMEUP), /* Volume up */
+        KEY(4, 0, KEY_F2),  /* Right bar (landscape) */
+        KEY(5, 0, KEY_MAIL), /* Win key (portrait) */
+        KEY(6, 0, KEY_DIRECTORY), /* Right bar (protrait) */
+        KEY(0, 1, KEY_LEFTCTRL), /* Windows key */
         KEY(1, 1, KEY_COMMA),
-        KEY(1, 2, KEY_M),
-        KEY(1, 3, KEY_K),
-        KEY(1, 4, KEY_SLASH), /* OK key */
-        KEY(1, 5, KEY_I),
-        KEY(1, 6, KEY_U),
-        KEY(2, 0, KEY_LEFTALT),
-        KEY(2, 1, KEY_TAB),
+        KEY(2, 1, KEY_M),
+        KEY(3, 1, KEY_K),
+        KEY(4, 1, KEY_SLASH), /* OK key */
+        KEY(5, 1, KEY_I),
+        KEY(6, 1, KEY_U),
+        KEY(0, 2, KEY_LEFTALT),
+        KEY(1, 2, KEY_TAB),
         KEY(2, 2, KEY_N),
-        KEY(2, 3, KEY_J),
-        KEY(2, 4, KEY_ENTER),
-        KEY(2, 5, KEY_H),
-        KEY(2, 6, KEY_Y),
-        KEY(3, 0, KEY_SPACE),
-        KEY(3, 1, KEY_L),
-        KEY(3, 2, KEY_B),
+        KEY(3, 2, KEY_J),
+        KEY(4, 2, KEY_ENTER),
+        KEY(5, 2, KEY_H),
+        KEY(6, 2, KEY_Y),
+        KEY(0, 3, KEY_SPACE),
+        KEY(1, 3, KEY_L),
+        KEY(2, 3, KEY_B),
         KEY(3, 3, KEY_V),
-        KEY(3, 4, KEY_BACKSPACE),
-        KEY(3, 5, KEY_G),
-        KEY(3, 6, KEY_T),
-        KEY(4, 0, KEY_CAPSLOCK), /* Shift */
-        KEY(4, 1, KEY_C),
-        KEY(4, 2, KEY_F),
-        KEY(4, 3, KEY_R),
+        KEY(4, 3, KEY_BACKSPACE),
+        KEY(5, 3, KEY_G),
+        KEY(6, 3, KEY_T),
+        KEY(0, 4, KEY_CAPSLOCK), /* Shift */
+        KEY(1, 4, KEY_C),
+        KEY(2, 4, KEY_F),
+        KEY(3, 4, KEY_R),
         KEY(4, 4, KEY_O),
-        KEY(4, 5, KEY_E),
-        KEY(4, 6, KEY_D),
-        KEY(5, 0, KEY_X),
-        KEY(5, 1, KEY_Z),
-        KEY(5, 2, KEY_S),
-        KEY(5, 3, KEY_W),
-        KEY(5, 4, KEY_P),
+        KEY(5, 4, KEY_E),
+        KEY(6, 4, KEY_D),
+        KEY(0, 5, KEY_X),
+        KEY(1, 5, KEY_Z),
+        KEY(2, 5, KEY_S),
+        KEY(3, 5, KEY_W),
+        KEY(4, 5, KEY_P),
         KEY(5, 5, KEY_Q),
-        KEY(5, 6, KEY_A),
-        KEY(6, 0, KEY_CONNECT), /* Voice button */
-        KEY(6, 2, KEY_CANCEL), /* End key */
-        KEY(6, 3, KEY_VOLUMEDOWN), /* Volume down */
-        KEY(6, 4, KEY_F1), /* Left bar (landscape) */
-        KEY(6, 5, KEY_WWW), /* OK button (portrait) */
+        KEY(6, 5, KEY_A),
+        KEY(0, 6, KEY_CONNECT), /* Voice button */
+        KEY(2, 6, KEY_CANCEL), /* End key */
+        KEY(3, 6, KEY_VOLUMEDOWN), /* Volume down */
+        KEY(4, 6, KEY_F1), /* Left bar (landscape) */
+        KEY(5, 6, KEY_WWW), /* OK button (portrait) */
         KEY(6, 6, KEY_CALENDAR), /* Left bar (portrait) */
-        0
 };
 
-struct omap_kp_platform_data htcherald_kp_data = {
+static const struct matrix_keymap_data htc_herald_keymap_data = {
+        .keymap         = htc_herald_keymap,
+        .keymap_size    = ARRAY_SIZE(htc_herald_keymap),
+};
+
+static struct omap_kp_platform_data htcherald_kp_data = {
         .rows   = 7,
         .cols   = 7,
         .delay = 20,
-        .rep = 1,
-        .keymap = htc_herald_keymap,
+        .rep = true,
+        .keymap_data = &htc_herald_keymap_data,
 };
 
 static struct resource kp_resources[] = {
@@ -278,7 +282,7 @@ static struct gpio_keys_button herald_gpio_keys_table[] = {
 static struct gpio_keys_platform_data herald_gpio_keys_data = {
         .buttons        = herald_gpio_keys_table,
         .nbuttons       = ARRAY_SIZE(herald_gpio_keys_table),
-        .rep            = 1,
+        .rep            = true,
 };
 
 static struct platform_device herald_gpiokeys_device = {
@@ -439,7 +443,7 @@ static const struct ads7846_platform_data htcherald_ts_platform_data = {
         .keep_vref_on           = 1,
         .x_plate_ohms           = 496,
         .gpio_pendown           = HTCHERALD_GPIO_TS,
-        .pressure_max           = 100000,
+        .pressure_max           = 10000,
         .pressure_min           = 5000,
         .x_min                  = 528,
         .x_max                  = 3760,
@@ -577,8 +581,6 @@ static void __init htcherald_init(void)
         printk(KERN_INFO "HTC Herald init.\n");
 
         /* Do board initialization before we register all the devices */
-        omap_gpio_init();
-
         omap_board_config = htcherald_config;
         omap_board_config_size = ARRAY_SIZE(htcherald_config);
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index dc2b86fd66c1..a36e6742bf9b 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -44,17 +44,16 @@
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define INNOVATOR1610_ETHR_START        0x04000300
 
-static int innovator_keymap[] = {
+static const unsigned int innovator_keymap[] = {
         KEY(0, 0, KEY_F1),
-        KEY(0, 3, KEY_DOWN),
+        KEY(3, 0, KEY_DOWN),
         KEY(1, 1, KEY_F2),
-        KEY(1, 2, KEY_RIGHT),
-        KEY(2, 0, KEY_F3),
-        KEY(2, 1, KEY_F4),
+        KEY(2, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_F3),
+        KEY(1, 2, KEY_F4),
         KEY(2, 2, KEY_UP),
-        KEY(3, 2, KEY_ENTER),
+        KEY(2, 3, KEY_ENTER),
         KEY(3, 3, KEY_LEFT),
-        0
 };
 
 static struct mtd_partition innovator_partitions[] = {
@@ -126,11 +125,15 @@ static struct resource innovator_kp_resources[] = {
         },
 };
 
+static const struct matrix_keymap_data innovator_keymap_data = {
+        .keymap         = innovator_keymap,
+        .keymap_size    = ARRAY_SIZE(innovator_keymap),
+};
+
 static struct omap_kp_platform_data innovator_kp_data = {
         .rows           = 8,
         .cols           = 8,
-        .keymap         = innovator_keymap,
-        .keymapsize     = ARRAY_SIZE(innovator_keymap),
+        .keymap_data    = &innovator_keymap_data,
         .delay          = 4,
 };
 
@@ -290,13 +293,6 @@ static void __init innovator_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
-#ifdef CONFIG_ARCH_OMAP15XX
-        if (cpu_is_omap1510()) {
-                omap1510_fpga_init_irq();
-        }
-#endif
-        innovator_init_smc91x();
 }
 
 #ifdef CONFIG_ARCH_OMAP15XX
@@ -387,6 +383,10 @@ static struct omap_board_config_kernel innovator_config[] = {
 
 static void __init innovator_init(void)
 {
+        if (cpu_is_omap1510())
+                omap1510_fpga_init_irq();
+        innovator_init_smc91x();
+
 #ifdef CONFIG_ARCH_OMAP15XX
         if (cpu_is_omap1510()) {
                 unsigned char reg;
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index aa8375b2a0a3..d21f09dc78f4 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -54,19 +54,18 @@ static void __init omap_nokia770_init_irq(void)
         omap_init_irq();
 }
 
-static int nokia770_keymap[] = {
-        KEY(0, 1, GROUP_0 | KEY_UP),
-        KEY(0, 2, GROUP_1 | KEY_F5),
-        KEY(1, 0, GROUP_0 | KEY_LEFT),
+static const unsigned int nokia770_keymap[] = {
+        KEY(1, 0, GROUP_0 | KEY_UP),
+        KEY(2, 0, GROUP_1 | KEY_F5),
+        KEY(0, 1, GROUP_0 | KEY_LEFT),
         KEY(1, 1, GROUP_0 | KEY_ENTER),
-        KEY(1, 2, GROUP_0 | KEY_RIGHT),
-        KEY(2, 0, GROUP_1 | KEY_ESC),
-        KEY(2, 1, GROUP_0 | KEY_DOWN),
+        KEY(2, 1, GROUP_0 | KEY_RIGHT),
+        KEY(0, 2, GROUP_1 | KEY_ESC),
+        KEY(1, 2, GROUP_0 | KEY_DOWN),
         KEY(2, 2, GROUP_1 | KEY_F4),
-        KEY(3, 0, GROUP_2 | KEY_F7),
-        KEY(3, 1, GROUP_2 | KEY_F8),
-        KEY(3, 2, GROUP_2 | KEY_F6),
-        0
+        KEY(0, 3, GROUP_2 | KEY_F7),
+        KEY(1, 3, GROUP_2 | KEY_F8),
+        KEY(2, 3, GROUP_2 | KEY_F6),
 };
 
 static struct resource nokia770_kp_resources[] = {
@@ -77,11 +76,15 @@ static struct resource nokia770_kp_resources[] = {
         },
 };
 
+static const struct matrix_keymap_data nokia770_keymap_data = {
+        .keymap         = nokia770_keymap,
+        .keymap_size    = ARRAY_SIZE(nokia770_keymap),
+};
+
 static struct omap_kp_platform_data nokia770_kp_data = {
         .rows           = 8,
         .cols           = 8,
-        .keymap         = nokia770_keymap,
-        .keymapsize     = ARRAY_SIZE(nokia770_keymap),
+        .keymap_data    = &nokia770_keymap_data,
         .delay          = 4,
 };
 
@@ -246,7 +249,6 @@ static void __init omap_nokia770_init(void)
         platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
         spi_register_board_info(nokia770_spi_board_info,
                                 ARRAY_SIZE(nokia770_spi_board_info));
-        omap_gpio_init();
         omap_serial_init();
         omap_register_i2c_bus(1, 100, NULL, 0);
         hwa742_dev_init();
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index e9dd79149a8e..7c5e2112c776 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -283,9 +283,6 @@ static void __init osk_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
-        osk_init_smc91x();
-        osk_init_cf();
 }
 
 static struct omap_usb_config osk_usb_config __initdata = {
@@ -341,25 +338,28 @@ static struct i2c_board_info __initdata mistral_i2c_board_info[] = {
          */
 };
 
-static const int osk_keymap[] = {
+static const unsigned int osk_keymap[] = {
         /* KEY(col, row, code) */
         KEY(0, 0, KEY_F1),              /* SW4 */
-        KEY(0, 3, KEY_UP),              /* (sw2/up) */
+        KEY(3, 0, KEY_UP),              /* (sw2/up) */
         KEY(1, 1, KEY_LEFTCTRL),        /* SW5 */
-        KEY(1, 2, KEY_LEFT),            /* (sw2/left) */
-        KEY(2, 0, KEY_SPACE),           /* SW3 */
-        KEY(2, 1, KEY_ESC),             /* SW6 */
+        KEY(2, 1, KEY_LEFT),            /* (sw2/left) */
+        KEY(0, 2, KEY_SPACE),           /* SW3 */
+        KEY(1, 2, KEY_ESC),             /* SW6 */
         KEY(2, 2, KEY_DOWN),            /* (sw2/down) */
-        KEY(3, 2, KEY_ENTER),           /* (sw2/select) */
+        KEY(2, 3, KEY_ENTER),           /* (sw2/select) */
         KEY(3, 3, KEY_RIGHT),           /* (sw2/right) */
-        0
+};
+
+static const struct matrix_keymap_data osk_keymap_data = {
+        .keymap         = osk_keymap,
+        .keymap_size    = ARRAY_SIZE(osk_keymap),
 };
 
 static struct omap_kp_platform_data osk_kp_data = {
         .rows           = 8,
         .cols           = 8,
-        .keymap         = (int *) osk_keymap,
-        .keymapsize     = ARRAY_SIZE(osk_keymap),
+        .keymap_data    = &osk_keymap_data,
         .delay          = 9,
 };
 
@@ -541,6 +541,9 @@ static void __init osk_init(void)
 {
         u32 l;
 
+        osk_init_smc91x();
+        osk_init_cf();
+
         /* Workaround for wrong CS3 (NOR flash) timing
          * There are some U-Boot versions out there which configure
          * wrong CS3 memory timings. This mainly leads to CRC
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index f32738b1eb6b..fb51ce6123d8 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -63,28 +63,31 @@ static void __init omap_palmte_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
 }
 
-static const int palmte_keymap[] = {
+static const unsigned int palmte_keymap[] = {
         KEY(0, 0, KEY_F1),              /* Calendar */
-        KEY(0, 1, KEY_F2),              /* Contacts */
-        KEY(0, 2, KEY_F3),              /* Tasks List */
-        KEY(0, 3, KEY_F4),              /* Note Pad */
-        KEY(0, 4, KEY_POWER),
-        KEY(1, 0, KEY_LEFT),
+        KEY(1, 0, KEY_F2),              /* Contacts */
+        KEY(2, 0, KEY_F3),              /* Tasks List */
+        KEY(3, 0, KEY_F4),              /* Note Pad */
+        KEY(4, 0, KEY_POWER),
+        KEY(0, 1, KEY_LEFT),
         KEY(1, 1, KEY_DOWN),
-        KEY(1, 2, KEY_UP),
-        KEY(1, 3, KEY_RIGHT),
-        KEY(1, 4, KEY_ENTER),
-        0,
+        KEY(2, 1, KEY_UP),
+        KEY(3, 1, KEY_RIGHT),
+        KEY(4, 1, KEY_ENTER),
+};
+
+static const struct matrix_keymap_data palmte_keymap_data = {
+        .keymap         = palmte_keymap,
+        .keymap_size    = ARRAY_SIZE(palmte_keymap),
 };
 
 static struct omap_kp_platform_data palmte_kp_data = {
         .rows   = 8,
         .cols   = 8,
-        .keymap = (int *) palmte_keymap,
-        .rep    = 1,
+        .keymap_data = &palmte_keymap_data,
+        .rep    = true,
         .delay  = 12,
 };
 
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index ed1400a67f75..f04f2d36e7d3 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -51,19 +51,18 @@
 #define PALMTT_MMC_WP_GPIO      8
 #define PALMTT_HDQ_GPIO         11
 
-static int palmtt_keymap[] = {
+static const unsigned int palmtt_keymap[] = {
         KEY(0, 0, KEY_ESC),
-        KEY(0, 1, KEY_SPACE),
-        KEY(0, 2, KEY_LEFTCTRL),
-        KEY(0, 3, KEY_TAB),
-        KEY(0, 4, KEY_ENTER),
-        KEY(1, 0, KEY_LEFT),
+        KEY(1, 0, KEY_SPACE),
+        KEY(2, 0, KEY_LEFTCTRL),
+        KEY(3, 0, KEY_TAB),
+        KEY(4, 0, KEY_ENTER),
+        KEY(0, 1, KEY_LEFT),
         KEY(1, 1, KEY_DOWN),
-        KEY(1, 2, KEY_UP),
-        KEY(1, 3, KEY_RIGHT),
-        KEY(2, 0, KEY_SLEEP),
-        KEY(2, 4, KEY_Y),
-        0
+        KEY(2, 1, KEY_UP),
+        KEY(3, 1, KEY_RIGHT),
+        KEY(0, 2, KEY_SLEEP),
+        KEY(4, 2, KEY_Y),
 };
 
 static struct mtd_partition palmtt_partitions[] = {
@@ -136,10 +135,15 @@ static struct resource palmtt_kp_resources[] = {
         },
 };
 
+static const struct matrix_keymap_data palmtt_keymap_data = {
+        .keymap         = palmtt_keymap,
+        .keymap_size    = ARRAY_SIZE(palmtt_keymap),
+};
+
 static struct omap_kp_platform_data palmtt_kp_data = {
         .rows   = 6,
         .cols   = 3,
-        .keymap = palmtt_keymap,
+        .keymap_data = &palmtt_keymap_data,
 };
 
 static struct platform_device palmtt_kp_device = {
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index d7a245cef9a4..d7bbbe721a75 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -62,29 +62,32 @@ omap_palmz71_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
 }
 
-static int palmz71_keymap[] = {
+static const unsigned int palmz71_keymap[] = {
         KEY(0, 0, KEY_F1),
-        KEY(0, 1, KEY_F2),
-        KEY(0, 2, KEY_F3),
-        KEY(0, 3, KEY_F4),
-        KEY(0, 4, KEY_POWER),
-        KEY(1, 0, KEY_LEFT),
+        KEY(1, 0, KEY_F2),
+        KEY(2, 0, KEY_F3),
+        KEY(3, 0, KEY_F4),
+        KEY(4, 0, KEY_POWER),
+        KEY(0, 1, KEY_LEFT),
         KEY(1, 1, KEY_DOWN),
-        KEY(1, 2, KEY_UP),
-        KEY(1, 3, KEY_RIGHT),
-        KEY(1, 4, KEY_ENTER),
-        KEY(2, 0, KEY_CAMERA),
-        0,
+        KEY(2, 1, KEY_UP),
+        KEY(3, 1, KEY_RIGHT),
+        KEY(4, 1, KEY_ENTER),
+        KEY(0, 2, KEY_CAMERA),
+};
+
+static const struct matrix_keymap_data palmz71_keymap_data = {
+        .keymap         = palmz71_keymap,
+        .keymap_size    = ARRAY_SIZE(palmz71_keymap),
 };
 
 static struct omap_kp_platform_data palmz71_kp_data = {
         .rows   = 8,
         .cols   = 8,
-        .keymap = palmz71_keymap,
-        .rep    = 1,
+        .keymap_data    = &palmz71_keymap_data,
+        .rep    = true,
         .delay  = 80,
 };
 
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index a8d16a255c18..3c8ee8489458 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -36,36 +36,35 @@
 #include <plat/common.h>
 #include <plat/board.h>
 
-static int p2_keymap[] = {
-        KEY(0,0,KEY_UP),
-        KEY(0,1,KEY_RIGHT),
-        KEY(0,2,KEY_LEFT),
-        KEY(0,3,KEY_DOWN),
-        KEY(0,4,KEY_ENTER),
-        KEY(1,0,KEY_F10),
-        KEY(1,1,KEY_SEND),
-        KEY(1,2,KEY_END),
-        KEY(1,3,KEY_VOLUMEDOWN),
-        KEY(1,4,KEY_VOLUMEUP),
-        KEY(1,5,KEY_RECORD),
-        KEY(2,0,KEY_F9),
-        KEY(2,1,KEY_3),
-        KEY(2,2,KEY_6),
-        KEY(2,3,KEY_9),
-        KEY(2,4,KEY_KPDOT),
-        KEY(3,0,KEY_BACK),
-        KEY(3,1,KEY_2),
-        KEY(3,2,KEY_5),
-        KEY(3,3,KEY_8),
-        KEY(3,4,KEY_0),
-        KEY(3,5,KEY_KPSLASH),
-        KEY(4,0,KEY_HOME),
-        KEY(4,1,KEY_1),
-        KEY(4,2,KEY_4),
-        KEY(4,3,KEY_7),
-        KEY(4,4,KEY_KPASTERISK),
-        KEY(4,5,KEY_POWER),
-        0
+static const unsigned int p2_keymap[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(2, 0, KEY_LEFT),
+        KEY(3, 0, KEY_DOWN),
+        KEY(4, 0, KEY_ENTER),
+        KEY(0, 1, KEY_F10),
+        KEY(1, 1, KEY_SEND),
+        KEY(2, 1, KEY_END),
+        KEY(3, 1, KEY_VOLUMEDOWN),
+        KEY(4, 1, KEY_VOLUMEUP),
+        KEY(5, 1, KEY_RECORD),
+        KEY(0, 2, KEY_F9),
+        KEY(1, 2, KEY_3),
+        KEY(2, 2, KEY_6),
+        KEY(3, 2, KEY_9),
+        KEY(4, 2, KEY_KPDOT),
+        KEY(0, 3, KEY_BACK),
+        KEY(1, 3, KEY_2),
+        KEY(2, 3, KEY_5),
+        KEY(3, 3, KEY_8),
+        KEY(4, 3, KEY_0),
+        KEY(5, 3, KEY_KPSLASH),
+        KEY(0, 4, KEY_HOME),
+        KEY(1, 4, KEY_1),
+        KEY(2, 4, KEY_4),
+        KEY(3, 4, KEY_7),
+        KEY(4, 4, KEY_KPASTERISK),
+        KEY(5, 4, KEY_POWER),
 };
 
 static struct smc91x_platdata smc91x_info = {
@@ -211,13 +210,17 @@ static struct resource kp_resources[] = {
         },
 };
 
+static const struct matrix_keymap_data p2_keymap_data = {
+        .keymap         = p2_keymap,
+        .keymap_size    = ARRAY_SIZE(p2_keymap),
+};
+
 static struct omap_kp_platform_data kp_data = {
         .rows           = 8,
         .cols           = 8,
-        .keymap         = p2_keymap,
-        .keymapsize     = ARRAY_SIZE(p2_keymap),
+        .keymap_data    = &p2_keymap_data,
         .delay          = 4,
-        .dbounce        = 1,
+        .dbounce        = true,
 };
 
 static struct platform_device kp_device = {
@@ -251,8 +254,19 @@ static struct omap_board_config_kernel perseus2_config[] __initdata = {
         { OMAP_TAG_LCD,         &perseus2_lcd_config },
 };
 
+static void __init perseus2_init_smc91x(void)
+{
+        fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
+        mdelay(50);
+        fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
+                   H2P2_DBG_FPGA_LAN_RESET);
+        mdelay(50);
+}
+
 static void __init omap_perseus2_init(void)
 {
+        perseus2_init_smc91x();
+
         if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
                 BUG();
         gpio_direction_input(P2_NAND_RB_GPIO_PIN);
@@ -280,21 +294,10 @@ static void __init omap_perseus2_init(void)
         omap_register_i2c_bus(1, 100, NULL, 0);
 }
 
-static void __init perseus2_init_smc91x(void)
-{
-        fpga_write(1, H2P2_DBG_FPGA_LAN_RESET);
-        mdelay(50);
-        fpga_write(fpga_read(H2P2_DBG_FPGA_LAN_RESET) & ~1,
-                   H2P2_DBG_FPGA_LAN_RESET);
-        mdelay(50);
-}
-
 static void __init omap_perseus2_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
-        perseus2_init_smc91x();
 }
 /* Only FPGA needs to be mapped here. All others are done with ioremap */
 static struct map_desc omap_perseus2_io_desc[] __initdata = {
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index d25f59e5a773..d41fe2d0616a 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -164,36 +164,35 @@ EXPORT_SYMBOL(sx1_setusbpower);
 
 /*----------- Keypad -------------------------*/
 
-static int sx1_keymap[] = {
-        KEY(5, 3, GROUP_0 | 117), /* camera Qt::Key_F17 */
-        KEY(0, 4, GROUP_0 | 114), /* voice memo Qt::Key_F14 */
-        KEY(1, 4, GROUP_2 | 114), /* voice memo */
-        KEY(2, 4, GROUP_3 | 114), /* voice memo */
+static const unsigned int sx1_keymap[] = {
+        KEY(3, 5, GROUP_0 | 117), /* camera Qt::Key_F17 */
+        KEY(4, 0, GROUP_0 | 114), /* voice memo Qt::Key_F14 */
+        KEY(4, 1, GROUP_2 | 114), /* voice memo */
+        KEY(4, 2, GROUP_3 | 114), /* voice memo */
         KEY(0, 0, GROUP_1 | KEY_F12),   /* red button Qt::Key_Hangup */
-        KEY(4, 3, GROUP_1 | KEY_LEFT),
-        KEY(2, 3, GROUP_1 | KEY_DOWN),
-        KEY(1, 3, GROUP_1 | KEY_RIGHT),
-        KEY(0, 3, GROUP_1 | KEY_UP),
+        KEY(3, 4, GROUP_1 | KEY_LEFT),
+        KEY(3, 2, GROUP_1 | KEY_DOWN),
+        KEY(3, 1, GROUP_1 | KEY_RIGHT),
+        KEY(3, 0, GROUP_1 | KEY_UP),
         KEY(3, 3, GROUP_1 | KEY_POWER), /* joystick press or Qt::Key_Select */
-        KEY(5, 0, GROUP_1 | KEY_1),
-        KEY(4, 0, GROUP_1 | KEY_2),
-        KEY(3, 0, GROUP_1 | KEY_3),
-        KEY(3, 4, GROUP_1 | KEY_4),
+        KEY(0, 5, GROUP_1 | KEY_1),
+        KEY(0, 4, GROUP_1 | KEY_2),
+        KEY(0, 3, GROUP_1 | KEY_3),
+        KEY(4, 3, GROUP_1 | KEY_4),
         KEY(4, 4, GROUP_1 | KEY_5),
-        KEY(5, 4, GROUP_1 | KEY_KPASTERISK),/* "*" */
-        KEY(4, 1, GROUP_1 | KEY_6),
-        KEY(5, 1, GROUP_1 | KEY_7),
-        KEY(3, 1, GROUP_1 | KEY_8),
-        KEY(3, 2, GROUP_1 | KEY_9),
-        KEY(5, 2, GROUP_1 | KEY_0),
-        KEY(4, 2, GROUP_1 | 113),       /* # F13 Toggle input method Qt::Key_F13 */
-        KEY(0, 1, GROUP_1 | KEY_F11),   /* green button Qt::Key_Call */
-        KEY(1, 2, GROUP_1 | KEY_YEN),   /* left soft Qt::Key_Context1 */
+        KEY(4, 5, GROUP_1 | KEY_KPASTERISK),/* "*" */
+        KEY(1, 4, GROUP_1 | KEY_6),
+        KEY(1, 5, GROUP_1 | KEY_7),
+        KEY(1, 3, GROUP_1 | KEY_8),
+        KEY(2, 3, GROUP_1 | KEY_9),
+        KEY(2, 5, GROUP_1 | KEY_0),
+        KEY(2, 4, GROUP_1 | 113), /* # F13 Toggle input method Qt::Key_F13 */
+        KEY(1, 0, GROUP_1 | KEY_F11),   /* green button Qt::Key_Call */
+        KEY(2, 1, GROUP_1 | KEY_YEN),   /* left soft Qt::Key_Context1 */
         KEY(2, 2, GROUP_1 | KEY_F8),    /* right soft Qt::Key_Back */
-        KEY(2, 1, GROUP_1 | KEY_LEFTSHIFT), /* shift */
+        KEY(1, 2, GROUP_1 | KEY_LEFTSHIFT), /* shift */
         KEY(1, 1, GROUP_1 | KEY_BACKSPACE), /* C (clear) */
-        KEY(0, 2, GROUP_1 | KEY_F7),    /* menu Qt::Key_Menu */
-        0
+        KEY(2, 0, GROUP_1 | KEY_F7),    /* menu Qt::Key_Menu */
 };
 
 static struct resource sx1_kp_resources[] = {
@@ -204,11 +203,15 @@ static struct resource sx1_kp_resources[] = {
         },
 };
 
+static const struct matrix_keymap_data sx1_keymap_data = {
+        .keymap         = sx1_keymap,
+        .keymap_size    = ARRAY_SIZE(sx1_keymap),
+};
+
 static struct omap_kp_platform_data sx1_kp_data = {
         .rows           = 6,
         .cols           = 6,
-        .keymap = sx1_keymap,
-        .keymapsize = ARRAY_SIZE(sx1_keymap),
+        .keymap_data    = &sx1_keymap_data,
         .delay  = 80,
 };
 
@@ -409,7 +412,6 @@ static void __init omap_sx1_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
 }
 /*----------------------------------------*/
 
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index f5992c239bcd..815a69ce821d 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -83,6 +83,9 @@ static struct platform_device serial_device = {
 
 static int __init ext_uart_init(void)
 {
+        if (!machine_is_voiceblue())
+                return -ENODEV;
+
         return platform_device_register(&serial_device);
 }
 arch_initcall(ext_uart_init);
@@ -158,7 +161,6 @@ static void __init voiceblue_init_irq(void)
 {
         omap1_init_common_hw();
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static void __init voiceblue_init(void)
@@ -236,6 +238,9 @@ static struct notifier_block panic_block = {
 
 static int __init voiceblue_setup(void)
 {
+        if (!machine_is_voiceblue())
+                return -ENODEV;
+
         /* Setup panic notifier */
         atomic_notifier_chain_register(&panic_notifier_list, &panic_block);
 
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index b8c7fb9d7921..84ef70476b51 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -17,9 +17,9 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/clkdev.h>
 
 #include <asm/mach-types.h>
-#include <asm/clkdev.h>
 
 #include <plat/cpu.h>
 #include <plat/usb.h>
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index af54114b8f08..92400b9eb69f 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -143,7 +143,7 @@ static struct arm_idlect1_clk armper_ck = {
  * activation.  [ GPIO code for 1510 ]
  */
 static struct clk arm_gpio_ck = {
-        .name           = "arm_gpio_ck",
+        .name           = "ick",
         .ops            = &clkops_generic,
         .parent         = &ck_dpll1,
         .flags          = ENABLE_ON_INIT,
@@ -684,7 +684,7 @@ static struct omap_clk omap_clks[] = {
         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
-        CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
+        CLK("omap_gpio.0", "ick",       &arm_gpio_ck,   CK_1510 | CK_310),
         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
@@ -736,9 +736,9 @@ static struct omap_clk omap_clks[] = {
         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
         /* Virtual clocks */
         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
-        CLK("i2c_omap.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
-        CLK("i2c_omap.1", "ick",        &i2c_ick,       CK_16XX),
-        CLK("i2c_omap.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
+        CLK("omap_i2c.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
+        CLK("omap_i2c.1", "ick",        &i2c_ick,       CK_16XX),
+        CLK("omap_i2c.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
         CLK("omap1_spi100k.1", "fck",   &dummy_ck,      CK_7XX),
         CLK("omap1_spi100k.1", "ick",   &dummy_ck,      CK_7XX),
         CLK("omap1_spi100k.2", "fck",   &dummy_ck,      CK_7XX),
@@ -823,12 +823,10 @@ int __init omap1_clk_init(void)
                         crystal_type = info->system_clock_type;
         }
 
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        ck_ref.rate = 13000000;
-#elif defined(CONFIG_ARCH_OMAP16XX)
-        if (crystal_type == 2)
+        if (cpu_is_omap7xx())
+                ck_ref.rate = 13000000;
+        if (cpu_is_omap16xx() && crystal_type == 2)
                 ck_ref.rate = 19200000;
-#endif
 
         pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
                 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
@@ -883,10 +881,11 @@ int __init omap1_clk_init(void)
                ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 
-#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
-        /* Select slicer output as OMAP input clock */
-        omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
-#endif
+        if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
+                /* Select slicer output as OMAP input clock */
+                omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
+                                OMAP7XX_PCC_UPLD_CTRL);
+        }
 
         /* Amstrad Delta wants BCLK high when inactive */
         if (machine_is_ams_delta())
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index e7f9ee63dce5..b0f4c231595f 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -17,6 +17,7 @@
 #include <linux/io.h>
 #include <linux/spi/spi.h>
 
+#include <mach/camera.h>
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
 
@@ -287,6 +288,9 @@ static inline void omap_init_audio(void) {}
  */
 static int __init omap1_init_devices(void)
 {
+        if (!cpu_class_is_omap1())
+                return -ENODEV;
+
         /* please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
new file mode 100644
index 000000000000..d8559344c6e2
--- /dev/null
+++ b/arch/arm/mach-omap1/dma.c
@@ -0,0 +1,390 @@
+/*
+ * OMAP1/OMAP7xx - specific DMA driver
+ *
+ * Copyright (C) 2003 - 2008 Nokia Corporation
+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
+ * Graphics DMA and LCD DMA graphics tranformations
+ * by Imre Deak <imre.deak@nokia.com>
+ * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
+ * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Converted DMA library into platform driver
+ *                   - G, Manjunath Kondaiah <manjugk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <plat/dma.h>
+#include <plat/tc.h>
+#include <plat/irqs.h>
+
+#define OMAP1_DMA_BASE                  (0xfffed800)
+#define OMAP1_LOGICAL_DMA_CH_COUNT      17
+#define OMAP1_DMA_STRIDE                0x40
+
+static u32 errata;
+static u32 enable_1510_mode;
+static u8 dma_stride;
+static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+
+static u16 reg_map[] = {
+        [GCR]           = 0x400,
+        [GSCR]          = 0x404,
+        [GRST1]         = 0x408,
+        [HW_ID]         = 0x442,
+        [PCH2_ID]       = 0x444,
+        [PCH0_ID]       = 0x446,
+        [PCH1_ID]       = 0x448,
+        [PCHG_ID]       = 0x44a,
+        [PCHD_ID]       = 0x44c,
+        [CAPS_0]        = 0x44e,
+        [CAPS_1]        = 0x452,
+        [CAPS_2]        = 0x456,
+        [CAPS_3]        = 0x458,
+        [CAPS_4]        = 0x45a,
+        [PCH2_SR]       = 0x460,
+        [PCH0_SR]       = 0x480,
+        [PCH1_SR]       = 0x482,
+        [PCHD_SR]       = 0x4c0,
+
+        /* Common Registers */
+        [CSDP]          = 0x00,
+        [CCR]           = 0x02,
+        [CICR]          = 0x04,
+        [CSR]           = 0x06,
+        [CEN]           = 0x10,
+        [CFN]           = 0x12,
+        [CSFI]          = 0x14,
+        [CSEI]          = 0x16,
+        [CPC]           = 0x18, /* 15xx only */
+        [CSAC]          = 0x18,
+        [CDAC]          = 0x1a,
+        [CDEI]          = 0x1c,
+        [CDFI]          = 0x1e,
+        [CLNK_CTRL]     = 0x28,
+
+        /* Channel specific register offsets */
+        [CSSA]          = 0x08,
+        [CDSA]          = 0x0c,
+        [COLOR]         = 0x20,
+        [CCR2]          = 0x24,
+        [LCH_CTRL]      = 0x2a,
+};
+
+static struct resource res[] __initdata = {
+        [0] = {
+                .start  = OMAP1_DMA_BASE,
+                .end    = OMAP1_DMA_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "0",
+                .start  = INT_DMA_CH0_6,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .name   = "1",
+                .start  = INT_DMA_CH1_7,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .name   = "2",
+                .start  = INT_DMA_CH2_8,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [4] = {
+                .name   = "3",
+                .start  = INT_DMA_CH3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [5] = {
+                .name   = "4",
+                .start  = INT_DMA_CH4,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [6] = {
+                .name   = "5",
+                .start  = INT_DMA_CH5,
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* Handled in lcd_dma.c */
+        [7] = {
+                .name   = "6",
+                .start  = INT_1610_DMA_CH6,
+                .flags  = IORESOURCE_IRQ,
+        },
+        /* irq's for omap16xx and omap7xx */
+        [8] = {
+                .name   = "7",
+                .start  = INT_1610_DMA_CH7,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [9] = {
+                .name   = "8",
+                .start  = INT_1610_DMA_CH8,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [10] = {
+                .name  = "9",
+                .start = INT_1610_DMA_CH9,
+                .flags = IORESOURCE_IRQ,
+        },
+        [11] = {
+                .name  = "10",
+                .start = INT_1610_DMA_CH10,
+                .flags = IORESOURCE_IRQ,
+        },
+        [12] = {
+                .name  = "11",
+                .start = INT_1610_DMA_CH11,
+                .flags = IORESOURCE_IRQ,
+        },
+        [13] = {
+                .name  = "12",
+                .start = INT_1610_DMA_CH12,
+                .flags = IORESOURCE_IRQ,
+        },
+        [14] = {
+                .name  = "13",
+                .start = INT_1610_DMA_CH13,
+                .flags = IORESOURCE_IRQ,
+        },
+        [15] = {
+                .name  = "14",
+                .start = INT_1610_DMA_CH14,
+                .flags = IORESOURCE_IRQ,
+        },
+        [16] = {
+                .name  = "15",
+                .start = INT_1610_DMA_CH15,
+                .flags = IORESOURCE_IRQ,
+        },
+        [17] = {
+                .name  = "16",
+                .start = INT_DMA_LCD,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static void __iomem *dma_base;
+static inline void dma_write(u32 val, int reg, int lch)
+{
+        u8  stride;
+        u32 offset;
+
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+
+        __raw_writew(val, dma_base + offset);
+        if ((reg > CLNK_CTRL && reg < CCEN) ||
+                        (reg > PCHD_ID && reg < CAPS_2)) {
+                u32 offset2 = reg_map[reg] + 2 + (stride * lch);
+                __raw_writew(val >> 16, dma_base + offset2);
+        }
+}
+
+static inline u32 dma_read(int reg, int lch)
+{
+        u8 stride;
+        u32 offset, val;
+
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+
+        val = __raw_readw(dma_base + offset);
+        if ((reg > CLNK_CTRL && reg < CCEN) ||
+                        (reg > PCHD_ID && reg < CAPS_2)) {
+                u16 upper;
+                u32 offset2 = reg_map[reg] + 2 + (stride * lch);
+                upper = __raw_readw(dma_base + offset2);
+                val |= (upper << 16);
+        }
+        return val;
+}
+
+static void omap1_clear_lch_regs(int lch)
+{
+        int i = dma_common_ch_start;
+
+        for (; i <= dma_common_ch_end; i += 1)
+                dma_write(0, i, lch);
+}
+
+static void omap1_clear_dma(int lch)
+{
+        u32 l;
+
+        l = dma_read(CCR, lch);
+        l &= ~OMAP_DMA_CCR_EN;
+        dma_write(l, CCR, lch);
+
+        /* Clear pending interrupts */
+        l = dma_read(CSR, lch);
+}
+
+static void omap1_show_dma_caps(void)
+{
+        if (enable_1510_mode) {
+                printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
+        } else {
+                u16 w;
+                printk(KERN_INFO "OMAP DMA hardware version %d\n",
+                                                        dma_read(HW_ID, 0));
+                printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
+                        dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
+                        dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
+                        dma_read(CAPS_4, 0));
+
+                /* Disable OMAP 3.0/3.1 compatibility mode. */
+                w = dma_read(GSCR, 0);
+                w |= 1 << 3;
+                dma_write(w, GSCR, 0);
+        }
+        return;
+}
+
+static u32 configure_dma_errata(void)
+{
+
+        /*
+         * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
+         * read before the DMA controller finished disabling the channel.
+         */
+        if (!cpu_is_omap15xx())
+                SET_DMA_ERRATA(DMA_ERRATA_3_3);
+
+        return errata;
+}
+
+static int __init omap1_system_dma_init(void)
+{
+        struct omap_system_dma_plat_info        *p;
+        struct omap_dma_dev_attr                *d;
+        struct platform_device                  *pdev;
+        int ret;
+
+        pdev = platform_device_alloc("omap_dma_system", 0);
+        if (!pdev) {
+                pr_err("%s: Unable to device alloc for dma\n",
+                        __func__);
+                return -ENOMEM;
+        }
+
+        dma_base = ioremap(res[0].start, resource_size(&res[0]));
+        if (!dma_base) {
+                pr_err("%s: Unable to ioremap\n", __func__);
+                return -ENODEV;
+        }
+
+        ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
+        if (ret) {
+                dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
+                        __func__, pdev->name, pdev->id);
+                goto exit_device_del;
+        }
+
+        p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
+        if (!p) {
+                dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
+                        __func__, pdev->name);
+                ret = -ENOMEM;
+                goto exit_device_put;
+        }
+
+        d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
+        if (!d) {
+                dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
+                        __func__, pdev->name);
+                ret = -ENOMEM;
+                goto exit_release_p;
+        }
+
+        d->lch_count            = OMAP1_LOGICAL_DMA_CH_COUNT;
+
+        /* Valid attributes for omap1 plus processors */
+        if (cpu_is_omap15xx())
+                d->dev_caps = ENABLE_1510_MODE;
+        enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
+
+        d->dev_caps             |= SRC_PORT;
+        d->dev_caps             |= DST_PORT;
+        d->dev_caps             |= SRC_INDEX;
+        d->dev_caps             |= DST_INDEX;
+        d->dev_caps             |= IS_BURST_ONLY4;
+        d->dev_caps             |= CLEAR_CSR_ON_READ;
+        d->dev_caps             |= IS_WORD_16;
+
+
+        d->chan = kzalloc(sizeof(struct omap_dma_lch) *
+                                        (d->lch_count), GFP_KERNEL);
+        if (!d->chan) {
+                dev_err(&pdev->dev, "%s: Memory allocation failed"
+                                        "for d->chan!!!\n", __func__);
+                goto exit_release_d;
+        }
+
+        if (cpu_is_omap15xx())
+                d->chan_count = 9;
+        else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
+                if (!(d->dev_caps & ENABLE_1510_MODE))
+                        d->chan_count = 16;
+                else
+                        d->chan_count = 9;
+        }
+
+        p->dma_attr = d;
+
+        p->show_dma_caps        = omap1_show_dma_caps;
+        p->clear_lch_regs       = omap1_clear_lch_regs;
+        p->clear_dma            = omap1_clear_dma;
+        p->dma_write            = dma_write;
+        p->dma_read             = dma_read;
+        p->disable_irq_lch      = NULL;
+
+        p->errata = configure_dma_errata();
+
+        ret = platform_device_add_data(pdev, p, sizeof(*p));
+        if (ret) {
+                dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
+                        __func__, pdev->name, pdev->id);
+                goto exit_release_chan;
+        }
+
+        ret = platform_device_add(pdev);
+        if (ret) {
+                dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
+                        __func__, pdev->name, pdev->id);
+                goto exit_release_chan;
+        }
+
+        dma_stride              = OMAP1_DMA_STRIDE;
+        dma_common_ch_start     = CPC;
+        dma_common_ch_end       = COLOR;
+
+        return ret;
+
+exit_release_chan:
+        kfree(d->chan);
+exit_release_d:
+        kfree(d);
+exit_release_p:
+        kfree(p);
+exit_device_put:
+        platform_device_put(pdev);
+exit_device_del:
+        platform_device_del(pdev);
+
+        return ret;
+}
+arch_initcall(omap1_system_dma_init);
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index 0b07a78eeaa7..acd161666408 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -11,6 +11,7 @@
 
 #include <plat/io.h>
 #include <plat/tc.h>
+#include <plat/flash.h>
 
 void omap1_set_vpp(struct map_info *map, int enable)
 {
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 5cfce1636da0..8780e75cdc3d 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -143,7 +143,7 @@ static struct irq_chip omap_fpga_irq = {
  */
 void omap1510_fpga_init_irq(void)
 {
-        int i;
+        int i, res;
 
         __raw_writeb(0, OMAP1510_FPGA_IMR_LO);
         __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
@@ -177,10 +177,12 @@ void omap1510_fpga_init_irq(void)
          * NOTE: For general GPIO/MPUIO access and interrupts, please see
          * gpio.[ch]
          */
-        gpio_request(13, "FPGA irq");
+        res = gpio_request(13, "FPGA irq");
+        if (res) {
+                pr_err("%s failed to get gpio\n", __func__);
+                return;
+        }
         gpio_direction_input(13);
         set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
         set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
 }
-
-EXPORT_SYMBOL(omap1510_fpga_init_irq);
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
new file mode 100644
index 000000000000..04c4b04cf54e
--- /dev/null
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -0,0 +1,99 @@
+/*
+ * OMAP15xx specific gpio init
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author:
+ *      Charulatha V <charu@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+
+#define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
+#define OMAP1510_GPIO_BASE              0xFFFCE000
+
+/* gpio1 */
+static struct __initdata resource omap15xx_mpu_gpio_resources[] = {
+        {
+                .start  = OMAP1_MPUIO_VBASE,
+                .end    = OMAP1_MPUIO_VBASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_MPUIO,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
+        .virtual_irq_start      = IH_MPUIO_BASE,
+        .bank_type              = METHOD_MPUIO,
+        .bank_width             = 16,
+        .bank_stride            = 1,
+};
+
+static struct __initdata platform_device omap15xx_mpu_gpio = {
+        .name           = "omap_gpio",
+        .id             = 0,
+        .dev            = {
+                .platform_data = &omap15xx_mpu_gpio_config,
+        },
+        .num_resources = ARRAY_SIZE(omap15xx_mpu_gpio_resources),
+        .resource = omap15xx_mpu_gpio_resources,
+};
+
+/* gpio2 */
+static struct __initdata resource omap15xx_gpio_resources[] = {
+        {
+                .start  = OMAP1510_GPIO_BASE,
+                .end    = OMAP1510_GPIO_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_GPIO_BANK1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
+        .virtual_irq_start      = IH_GPIO_BASE,
+        .bank_type              = METHOD_GPIO_1510,
+        .bank_width             = 16,
+};
+
+static struct __initdata platform_device omap15xx_gpio = {
+        .name           = "omap_gpio",
+        .id             = 1,
+        .dev            = {
+                .platform_data = &omap15xx_gpio_config,
+        },
+        .num_resources = ARRAY_SIZE(omap15xx_gpio_resources),
+        .resource = omap15xx_gpio_resources,
+};
+
+/*
+ * omap15xx_gpio_init needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence omap15xx_gpio_init is a postcore_initcall.
+ */
+static int __init omap15xx_gpio_init(void)
+{
+        if (!cpu_is_omap15xx())
+                return -EINVAL;
+
+        platform_device_register(&omap15xx_mpu_gpio);
+        platform_device_register(&omap15xx_gpio);
+
+        gpio_bank_count = 2;
+        return 0;
+}
+postcore_initcall(omap15xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
new file mode 100644
index 000000000000..5dd0d4c82b24
--- /dev/null
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -0,0 +1,200 @@
+/*
+ * OMAP16xx specific gpio init
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author:
+ *      Charulatha V <charu@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+
+#define OMAP1610_GPIO1_BASE             0xfffbe400
+#define OMAP1610_GPIO2_BASE             0xfffbec00
+#define OMAP1610_GPIO3_BASE             0xfffbb400
+#define OMAP1610_GPIO4_BASE             0xfffbbc00
+#define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
+
+/* mpu gpio */
+static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
+        {
+                .start  = OMAP1_MPUIO_VBASE,
+                .end    = OMAP1_MPUIO_VBASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_MPUIO,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
+        .virtual_irq_start      = IH_MPUIO_BASE,
+        .bank_type              = METHOD_MPUIO,
+        .bank_width             = 16,
+        .bank_stride            = 1,
+};
+
+static struct __initdata platform_device omap16xx_mpu_gpio = {
+        .name           = "omap_gpio",
+        .id             = 0,
+        .dev            = {
+                .platform_data = &omap16xx_mpu_gpio_config,
+        },
+        .num_resources = ARRAY_SIZE(omap16xx_mpu_gpio_resources),
+        .resource = omap16xx_mpu_gpio_resources,
+};
+
+/* gpio1 */
+static struct __initdata resource omap16xx_gpio1_resources[] = {
+        {
+                .start  = OMAP1610_GPIO1_BASE,
+                .end    = OMAP1610_GPIO1_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_GPIO_BANK1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
+        .virtual_irq_start      = IH_GPIO_BASE,
+        .bank_type              = METHOD_GPIO_1610,
+        .bank_width             = 16,
+};
+
+static struct __initdata platform_device omap16xx_gpio1 = {
+        .name           = "omap_gpio",
+        .id             = 1,
+        .dev            = {
+                .platform_data = &omap16xx_gpio1_config,
+        },
+        .num_resources = ARRAY_SIZE(omap16xx_gpio1_resources),
+        .resource = omap16xx_gpio1_resources,
+};
+
+/* gpio2 */
+static struct __initdata resource omap16xx_gpio2_resources[] = {
+        {
+                .start  = OMAP1610_GPIO2_BASE,
+                .end    = OMAP1610_GPIO2_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_1610_GPIO_BANK2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
+        .virtual_irq_start      = IH_GPIO_BASE + 16,
+        .bank_type              = METHOD_GPIO_1610,
+        .bank_width             = 16,
+};
+
+static struct __initdata platform_device omap16xx_gpio2 = {
+        .name           = "omap_gpio",
+        .id             = 2,
+        .dev            = {
+                .platform_data = &omap16xx_gpio2_config,
+        },
+        .num_resources = ARRAY_SIZE(omap16xx_gpio2_resources),
+        .resource = omap16xx_gpio2_resources,
+};
+
+/* gpio3 */
+static struct __initdata resource omap16xx_gpio3_resources[] = {
+        {
+                .start  = OMAP1610_GPIO3_BASE,
+                .end    = OMAP1610_GPIO3_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_1610_GPIO_BANK3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
+        .virtual_irq_start      = IH_GPIO_BASE + 32,
+        .bank_type              = METHOD_GPIO_1610,
+        .bank_width             = 16,
+};
+
+static struct __initdata platform_device omap16xx_gpio3 = {
+        .name           = "omap_gpio",
+        .id             = 3,
+        .dev            = {
+                .platform_data = &omap16xx_gpio3_config,
+        },
+        .num_resources = ARRAY_SIZE(omap16xx_gpio3_resources),
+        .resource = omap16xx_gpio3_resources,
+};
+
+/* gpio4 */
+static struct __initdata resource omap16xx_gpio4_resources[] = {
+        {
+                .start  = OMAP1610_GPIO4_BASE,
+                .end    = OMAP1610_GPIO4_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_1610_GPIO_BANK4,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
+        .virtual_irq_start      = IH_GPIO_BASE + 48,
+        .bank_type              = METHOD_GPIO_1610,
+        .bank_width             = 16,
+};
+
+static struct __initdata platform_device omap16xx_gpio4 = {
+        .name           = "omap_gpio",
+        .id             = 4,
+        .dev            = {
+                .platform_data = &omap16xx_gpio4_config,
+        },
+        .num_resources = ARRAY_SIZE(omap16xx_gpio4_resources),
+        .resource = omap16xx_gpio4_resources,
+};
+
+static struct __initdata platform_device * omap16xx_gpio_dev[] = {
+        &omap16xx_mpu_gpio,
+        &omap16xx_gpio1,
+        &omap16xx_gpio2,
+        &omap16xx_gpio3,
+        &omap16xx_gpio4,
+};
+
+/*
+ * omap16xx_gpio_init needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence omap16xx_gpio_init is a postcore_initcall.
+ */
+static int __init omap16xx_gpio_init(void)
+{
+        int i;
+
+        if (!cpu_is_omap16xx())
+                return -EINVAL;
+
+        for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
+                platform_device_register(omap16xx_gpio_dev[i]);
+
+        gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
+
+        return 0;
+}
+postcore_initcall(omap16xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
new file mode 100644
index 000000000000..1204c8b871af
--- /dev/null
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -0,0 +1,262 @@
+/*
+ * OMAP7xx specific gpio init
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author:
+ *      Charulatha V <charu@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+
+#define OMAP7XX_GPIO1_BASE              0xfffbc000
+#define OMAP7XX_GPIO2_BASE              0xfffbc800
+#define OMAP7XX_GPIO3_BASE              0xfffbd000
+#define OMAP7XX_GPIO4_BASE              0xfffbd800
+#define OMAP7XX_GPIO5_BASE              0xfffbe000
+#define OMAP7XX_GPIO6_BASE              0xfffbe800
+#define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
+
+/* mpu gpio */
+static struct __initdata resource omap7xx_mpu_gpio_resources[] = {
+        {
+                .start  = OMAP1_MPUIO_VBASE,
+                .end    = OMAP1_MPUIO_VBASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_7XX_MPUIO,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
+        .virtual_irq_start      = IH_MPUIO_BASE,
+        .bank_type              = METHOD_MPUIO,
+        .bank_width             = 32,
+        .bank_stride            = 2,
+};
+
+static struct __initdata platform_device omap7xx_mpu_gpio = {
+        .name           = "omap_gpio",
+        .id             = 0,
+        .dev            = {
+                .platform_data = &omap7xx_mpu_gpio_config,
+        },
+        .num_resources = ARRAY_SIZE(omap7xx_mpu_gpio_resources),
+        .resource = omap7xx_mpu_gpio_resources,
+};
+
+/* gpio1 */
+static struct __initdata resource omap7xx_gpio1_resources[] = {
+        {
+                .start  = OMAP7XX_GPIO1_BASE,
+                .end    = OMAP7XX_GPIO1_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_7XX_GPIO_BANK1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
+        .virtual_irq_start      = IH_GPIO_BASE,
+        .bank_type              = METHOD_GPIO_7XX,
+        .bank_width             = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio1 = {
+        .name           = "omap_gpio",
+        .id             = 1,
+        .dev            = {
+                .platform_data = &omap7xx_gpio1_config,
+        },
+        .num_resources = ARRAY_SIZE(omap7xx_gpio1_resources),
+        .resource = omap7xx_gpio1_resources,
+};
+
+/* gpio2 */
+static struct __initdata resource omap7xx_gpio2_resources[] = {
+        {
+                .start  = OMAP7XX_GPIO2_BASE,
+                .end    = OMAP7XX_GPIO2_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_7XX_GPIO_BANK2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio2_config = {
+        .virtual_irq_start      = IH_GPIO_BASE + 32,
+        .bank_type              = METHOD_GPIO_7XX,
+        .bank_width             = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio2 = {
+        .name           = "omap_gpio",
+        .id             = 2,
+        .dev            = {
+                .platform_data = &omap7xx_gpio2_config,
+        },
+        .num_resources = ARRAY_SIZE(omap7xx_gpio2_resources),
+        .resource = omap7xx_gpio2_resources,
+};
+
+/* gpio3 */
+static struct __initdata resource omap7xx_gpio3_resources[] = {
+        {
+                .start  = OMAP7XX_GPIO3_BASE,
+                .end    = OMAP7XX_GPIO3_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_7XX_GPIO_BANK3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio3_config = {
+        .virtual_irq_start      = IH_GPIO_BASE + 64,
+        .bank_type              = METHOD_GPIO_7XX,
+        .bank_width             = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio3 = {
+        .name           = "omap_gpio",
+        .id             = 3,
+        .dev            = {
+                .platform_data = &omap7xx_gpio3_config,
+        },
+        .num_resources = ARRAY_SIZE(omap7xx_gpio3_resources),
+        .resource = omap7xx_gpio3_resources,
+};
+
+/* gpio4 */
+static struct __initdata resource omap7xx_gpio4_resources[] = {
+        {
+                .start  = OMAP7XX_GPIO4_BASE,
+                .end    = OMAP7XX_GPIO4_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_7XX_GPIO_BANK4,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio4_config = {
+        .virtual_irq_start      = IH_GPIO_BASE + 96,
+        .bank_type              = METHOD_GPIO_7XX,
+        .bank_width             = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio4 = {
+        .name           = "omap_gpio",
+        .id             = 4,
+        .dev            = {
+                .platform_data = &omap7xx_gpio4_config,
+        },
+        .num_resources = ARRAY_SIZE(omap7xx_gpio4_resources),
+        .resource = omap7xx_gpio4_resources,
+};
+
+/* gpio5 */
+static struct __initdata resource omap7xx_gpio5_resources[] = {
+        {
+                .start  = OMAP7XX_GPIO5_BASE,
+                .end    = OMAP7XX_GPIO5_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_7XX_GPIO_BANK5,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio5_config = {
+        .virtual_irq_start      = IH_GPIO_BASE + 128,
+        .bank_type              = METHOD_GPIO_7XX,
+        .bank_width             = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio5 = {
+        .name           = "omap_gpio",
+        .id             = 5,
+        .dev            = {
+                .platform_data = &omap7xx_gpio5_config,
+        },
+        .num_resources = ARRAY_SIZE(omap7xx_gpio5_resources),
+        .resource = omap7xx_gpio5_resources,
+};
+
+/* gpio6 */
+static struct __initdata resource omap7xx_gpio6_resources[] = {
+        {
+                .start  = OMAP7XX_GPIO6_BASE,
+                .end    = OMAP7XX_GPIO6_BASE + SZ_2K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = INT_7XX_GPIO_BANK6,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct __initdata omap_gpio_platform_data omap7xx_gpio6_config = {
+        .virtual_irq_start      = IH_GPIO_BASE + 160,
+        .bank_type              = METHOD_GPIO_7XX,
+        .bank_width             = 32,
+};
+
+static struct __initdata platform_device omap7xx_gpio6 = {
+        .name           = "omap_gpio",
+        .id             = 6,
+        .dev            = {
+                .platform_data = &omap7xx_gpio6_config,
+        },
+        .num_resources = ARRAY_SIZE(omap7xx_gpio6_resources),
+        .resource = omap7xx_gpio6_resources,
+};
+
+static struct __initdata platform_device * omap7xx_gpio_dev[] = {
+        &omap7xx_mpu_gpio,
+        &omap7xx_gpio1,
+        &omap7xx_gpio2,
+        &omap7xx_gpio3,
+        &omap7xx_gpio4,
+        &omap7xx_gpio5,
+        &omap7xx_gpio6,
+};
+
+/*
+ * omap7xx_gpio_init needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence omap7xx_gpio_init is a postcore_initcall.
+ */
+static int __init omap7xx_gpio_init(void)
+{
+        int i;
+
+        if (!cpu_is_omap7xx())
+                return -EINVAL;
+
+        for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
+                platform_device_register(omap7xx_gpio_dev[i]);
+
+        gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev);
+
+        return 0;
+}
+postcore_initcall(omap7xx_gpio_init);
diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index df9060edda28..c9be6d4d83e2 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -14,18 +14,17 @@
 #include <mach/irqs.h>
 #include <asm/hardware/gic.h>
 
-#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \
-        (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
-#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
-#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-#define INT_IH2_IRQ             INT_7XX_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP15XX)
-#define INT_IH2_IRQ             INT_1510_IH2_IRQ
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#define INT_IH2_IRQ             INT_1610_IH2_IRQ
-#else
-#warning "IH2 IRQ defaulted"
-#define INT_IH2_IRQ             INT_1510_IH2_IRQ
+/*
+ * We use __glue to avoid errors with multiple definitions of
+ * .globl omap_irq_flags as it's included from entry-armv.S but not
+ * from entry-common.S.
+ */
+#ifdef __glue
+                .pushsection .data
+                .globl  omap_irq_flags
+omap_irq_flags:
+                .word   0
+                .popsection
 #endif
 
                 .macro  disable_fiq
@@ -47,9 +46,11 @@
                 beq     1510f
 
                 ldr     \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
+                ldr     \tmp, =omap_irq_flags   @ irq flags address
+                ldr     \tmp, [\tmp, #0]        @ irq flags value
                 cmp     \irqnr, #0
                 ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
-                cmpeq   \irqnr, #INT_IH2_IRQ
+                cmpeq   \irqnr, \tmp
                 ldreq   \base, =OMAP1_IO_ADDRESS(OMAP_IH2_BASE)
                 ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
                 addeqs  \irqnr, \irqnr, #32
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 0ce3fec2d257..870886a29594 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -142,3 +142,42 @@ void __init omap1_init_common_hw(void)
         omap1_mux_init();
 }
 
+/*
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ */
+
+u8 omap_readb(u32 pa)
+{
+        return __raw_readb(OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readb);
+
+u16 omap_readw(u32 pa)
+{
+        return __raw_readw(OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readw);
+
+u32 omap_readl(u32 pa)
+{
+        return __raw_readl(OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readl);
+
+void omap_writeb(u8 v, u32 pa)
+{
+        __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writeb);
+
+void omap_writew(u16 v, u32 pa)
+{
+        __raw_writew(v, OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writew);
+
+void omap_writel(u32 v, u32 pa)
+{
+        __raw_writel(v, OMAP1_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index db913c34d1fe..6bddbc869f4c 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -176,26 +176,31 @@ static struct irq_chip omap_irq_chip = {
 
 void __init omap_init_irq(void)
 {
+        extern unsigned int omap_irq_flags;
         int i, j;
 
 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
         if (cpu_is_omap7xx()) {
+                omap_irq_flags = INT_7XX_IH2_IRQ;
                 irq_banks = omap7xx_irq_banks;
                 irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
         }
 #endif
 #ifdef CONFIG_ARCH_OMAP15XX
         if (cpu_is_omap1510()) {
+                omap_irq_flags = INT_1510_IH2_IRQ;
                 irq_banks = omap1510_irq_banks;
                 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
         }
         if (cpu_is_omap310()) {
+                omap_irq_flags = INT_1510_IH2_IRQ;
                 irq_banks = omap310_irq_banks;
                 irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
         }
 #endif
 #if defined(CONFIG_ARCH_OMAP16XX)
         if (cpu_is_omap16xx()) {
+                omap_irq_flags = INT_1510_IH2_IRQ;
                 irq_banks = omap1610_irq_banks;
                 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
         }
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 3be11af687bb..c9088d85da04 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -424,6 +424,9 @@ static int __init omap_init_lcd_dma(void)
 {
         int r;
 
+        if (!cpu_class_is_omap1())
+                return -ENODEV;
+
         if (cpu_is_omap16xx()) {
                 u16 w;
 
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
index 277f356d4cd0..22eb11dde9e7 100644
--- a/arch/arm/mach-omap1/leds.c
+++ b/arch/arm/mach-omap1/leds.c
@@ -17,6 +17,9 @@
 static int __init
 omap_leds_init(void)
 {
+        if (!cpu_class_is_omap1())
+                return -ENODEV;
+
         if (machine_is_omap_innovator())
                 leds_event = innovator_leds_event;
 
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 1a85a421007f..c0e1f48aa119 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -133,19 +133,18 @@ static struct omap_mbox1_priv omap1_mbox_dsp_priv = {
         },
 };
 
-struct omap_mbox mbox_dsp_info = {
+static struct omap_mbox mbox_dsp_info = {
         .name   = "dsp",
         .ops    = &omap1_mbox_ops,
         .priv   = &omap1_mbox_dsp_priv,
 };
 
-struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
+static struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
 
 static int __devinit omap1_mbox_probe(struct platform_device *pdev)
 {
         struct resource *mem;
         int ret;
-        int i;
         struct omap_mbox **list;
 
         list = omap1_mboxes;
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index b3a796a6da03..820973666f34 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -174,8 +174,11 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
 #define OMAP16XX_MCBSP_REG_NUM          0
 #endif
 
-int __init omap1_mcbsp_init(void)
+static int __init omap1_mcbsp_init(void)
 {
+        if (!cpu_class_is_omap1())
+                return -ENODEV;
+
         if (cpu_is_omap7xx()) {
                 omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
                 omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16);
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 7835add00344..5fdef7a34828 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -343,7 +343,7 @@ MUX_CFG("Y14_1610_CCP_DATAM",	 9,   21,    6,   2,   3,   1,    2,     0,  0)
 #define OMAP1XXX_PINS_SZ        0
 #endif  /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
 
-int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
+static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
 {
         static DEFINE_SPINLOCK(mux_spin_lock);
         unsigned long flags;
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index b1d3f9fade23..0cca23a85175 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -661,6 +661,9 @@ static int __init omap_pm_init(void)
         int error;
 #endif
 
+        if (!cpu_class_is_omap1())
+                return -ENODEV;
+
         printk("Power Management for TI OMAP.\n");
 
         /*
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
index 8b66392be745..6588c22b8a64 100644
--- a/arch/arm/mach-omap1/pm_bus.c
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -48,7 +48,6 @@ static int omap1_pm_runtime_suspend(struct device *dev)
 
 static int omap1_pm_runtime_resume(struct device *dev)
 {
-        int ret = 0;
         struct clk *iclk, *fclk;
 
         dev_dbg(dev, "%s\n", __func__);
@@ -73,6 +72,9 @@ static int __init omap1_pm_runtime_init(void)
         const struct dev_pm_ops *pm;
         struct dev_pm_ops *omap_pm;
 
+        if (!cpu_class_is_omap1())
+                return -ENODEV;
+
         pm = platform_bus_get_pm_ops();
         if (!pm) {
                 pr_err("%s: unable to get dev_pm_ops from platform_bus\n",
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index b78d0749f13d..550ca9d9991d 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -27,6 +27,8 @@
 #include <mach/gpio.h>
 #include <plat/fpga.h>
 
+#include "pm.h"
+
 static struct clk * uart1_ck;
 static struct clk * uart2_ck;
 static struct clk * uart3_ck;
@@ -52,9 +54,11 @@ static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
  */
 static void __init omap_serial_reset(struct plat_serial8250_port *p)
 {
-        omap_serial_outp(p, UART_OMAP_MDR1, 0x07);      /* disable UART */
+        omap_serial_outp(p, UART_OMAP_MDR1,
+                        UART_OMAP_MDR1_DISABLE);        /* disable UART */
         omap_serial_outp(p, UART_OMAP_SCR, 0x08);       /* TX watermark */
-        omap_serial_outp(p, UART_OMAP_MDR1, 0x00);      /* enable UART */
+        omap_serial_outp(p, UART_OMAP_MDR1,
+                        UART_OMAP_MDR1_16X_MODE);       /* enable UART */
 
         if (!cpu_is_omap15xx()) {
                 omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
@@ -254,6 +258,9 @@ late_initcall(omap_serial_wakeup_init);
 
 static int __init omap_init(void)
 {
+        if (!cpu_class_is_omap1())
+                return -ENODEV;
+
         return platform_device_register(&serial_device);
 }
 arch_initcall(omap_init);
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 1be6a214d88d..ed7a61ff916a 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -52,6 +52,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 
+#include <plat/common.h>
 
 #define OMAP_MPU_TIMER_BASE             OMAP_MPU_TIMER1_BASE
 #define OMAP_MPU_TIMER_OFFSET           0x100
@@ -208,7 +209,6 @@ static struct clocksource clocksource_mpu = {
         .rating         = 300,
         .read           = mpu_read,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 24,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -217,13 +217,10 @@ static void __init omap_init_clocksource(unsigned long rate)
         static char err[] __initdata = KERN_ERR
                         "%s: can't register clocksource!\n";
 
-        clocksource_mpu.mult
-                = clocksource_khz2mult(rate/1000, clocksource_mpu.shift);
-
         setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
         omap_mpu_timer_start(1, ~0, 1);
 
-        if (clocksource_register(&clocksource_mpu))
+        if (clocksource_register_hz(&clocksource_mpu, rate))
                 printk(err, clocksource_mpu.name);
 }
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index ab784bfde908..1a2cf6226a55 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -15,7 +15,7 @@ config ARCH_OMAP2PLUS_TYPICAL
         select SERIAL_OMAP_CONSOLE
         select I2C
         select I2C_OMAP
-        select MFD
+        select MFD_SUPPORT
         select MENELAUS if ARCH_OMAP2
         select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
         select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
@@ -35,6 +35,8 @@ config ARCH_OMAP3
         select CPU_V7
         select USB_ARCH_HAS_EHCI
         select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
+        select ARCH_HAS_OPP
+        select PM_OPP if PM
 
 config ARCH_OMAP4
         bool "TI OMAP4"
@@ -44,6 +46,9 @@ config ARCH_OMAP4
         select ARM_GIC
         select PL310_ERRATA_588369
         select ARM_ERRATA_720789
+        select ARCH_HAS_OPP
+        select PM_OPP if PM
+        select USB_ARCH_HAS_EHCI
 
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
@@ -85,6 +90,12 @@ config OMAP_PACKAGE_CUS
 config OMAP_PACKAGE_CBP
        bool
 
+config OMAP_PACKAGE_CBL
+       bool
+
+config OMAP_PACKAGE_CBS
+       bool
+
 comment "OMAP Board Type"
         depends on ARCH_OMAP2PLUS
 
@@ -128,7 +139,6 @@ config MACH_DEVKIT8000
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CUS
-        select OMAP_MUX
 
 config MACH_OMAP_LDP
         bool "OMAP3 LDP board"
@@ -174,11 +184,17 @@ config MACH_OMAP3517EVM
         default y
         select OMAP_PACKAGE_CBB
 
+config MACH_CRANEBOARD
+        bool "AM3517/05 CRANE board"
+        depends on ARCH_OMAP3
+        select OMAP_PACKAGE_CBB
+
 config MACH_OMAP3_PANDORA
         bool "OMAP3 Pandora"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
+        select REGULATOR_FIXED_VOLTAGE
 
 config MACH_OMAP3_TOUCHBOOK
         bool "OMAP3 Touch Book"
@@ -210,6 +226,12 @@ config MACH_NOKIA_N8X0
         select MACH_NOKIA_N810
         select MACH_NOKIA_N810_WIMAX
 
+config MACH_NOKIA_RM680
+        bool "Nokia RM-680 board"
+        depends on ARCH_OMAP3
+        default y
+        select OMAP_PACKAGE_CBB
+
 config MACH_NOKIA_RX51
         bool "Nokia RX-51 board"
         depends on ARCH_OMAP3
@@ -224,6 +246,7 @@ config MACH_OMAP_ZOOM2
         select SERIAL_8250
         select SERIAL_CORE_CONSOLE
         select SERIAL_8250_CONSOLE
+        select REGULATOR_FIXED_VOLTAGE
 
 config MACH_OMAP_ZOOM3
         bool "OMAP3630 Zoom3 board"
@@ -233,20 +256,19 @@ config MACH_OMAP_ZOOM3
         select SERIAL_8250
         select SERIAL_CORE_CONSOLE
         select SERIAL_8250_CONSOLE
+        select REGULATOR_FIXED_VOLTAGE
 
 config MACH_CM_T35
         bool "CompuLab CM-T35 module"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CUS
-        select OMAP_MUX
 
 config MACH_CM_T3517
         bool "CompuLab CM-T3517 module"
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
-        select OMAP_MUX
 
 config MACH_IGEP0020
         bool "IGEP v2 board"
@@ -265,7 +287,6 @@ config MACH_SBC3530
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CUS
-        select OMAP_MUX
 
 config MACH_OMAP_3630SDP
         bool "OMAP3630 SDP board"
@@ -277,11 +298,15 @@ config MACH_OMAP_4430SDP
         bool "OMAP 4430 SDP board"
         default y
         depends on ARCH_OMAP4
+        select OMAP_PACKAGE_CBL
+        select OMAP_PACKAGE_CBS
 
 config MACH_OMAP4_PANDA
         bool "OMAP4 Panda Board"
         default y
         depends on ARCH_OMAP4
+        select OMAP_PACKAGE_CBL
+        select OMAP_PACKAGE_CBS
 
 config OMAP3_EMU
         bool "OMAP3 debugging peripherals"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 60e51bcf53bd..cd7332f50b2d 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,30 +4,31 @@
 
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
-         common.o
+         common.o gpio.o dma.o wd_timer.o
 
-omap-2-3-common                         = irq.o sdrc.o prm2xxx_3xxx.o
+omap-2-3-common                         = irq.o sdrc.o
 hwmod-common                            = omap_hwmod.o \
                                           omap_hwmod_common_data.o
-prcm-common                             = prcm.o powerdomain.o
 clock-common                            = clock.o clock_common_data.o \
-                                          clockdomain.o clkt_dpll.o \
-                                          clkt_clksel.o
+                                          clkt_dpll.o clkt_clksel.o
 
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common) prm44xx.o $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common)
 
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
 
+obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
+
 # SMP support ONLY available for OMAP4
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)              += timer-mpu.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap44xx-smc.o omap4-common.o
 
-AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a
-AFLAGS_omap44xx-smc.o                   :=-Wa,-march=armv7-a
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_omap44xx-smc.o                   :=-Wa,-march=armv7-a$(plus_sec)
 
 # Functions loaded to SRAM
 obj-$(CONFIG_ARCH_OMAP2420)             += sram242x.o
@@ -42,18 +43,29 @@ AFLAGS_sram34xx.o			:=-Wa,-march=armv7-a
 obj-$(CONFIG_ARCH_OMAP2420)             += mux2420.o
 obj-$(CONFIG_ARCH_OMAP2430)             += mux2430.o
 obj-$(CONFIG_ARCH_OMAP3)                += mux34xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += mux44xx.o
 
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
 # obj-$(CONFIG_ARCH_OMAP3)              += sdrc3xxx.o
 
+# OPP table initialization
+ifeq ($(CONFIG_PM_OPP),y)
+obj-y                                   += opp.o
+obj-$(CONFIG_ARCH_OMAP3)                += opp3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += opp4xxx_data.o
+endif
+
 # Power Management
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
-obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o pm_bus.o
-obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o cpuidle34xx.o pm_bus.o
-obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o pm_bus.o voltage.o
+obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o voltage.o \
+                                           cpuidle34xx.o pm_bus.o
+obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o voltage.o pm_bus.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
+obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
+obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)   += smartreflex-class3.o
 
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a
@@ -65,10 +77,36 @@ endif
 endif
 
 # PRCM
-obj-$(CONFIG_ARCH_OMAP2)                += cm.o
-obj-$(CONFIG_ARCH_OMAP3)                += cm.o
-obj-$(CONFIG_ARCH_OMAP4)                += cm4xxx.o
-
+obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
+# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and
+# will be removed once the OMAP4 part of the codebase is converted to
+# use OMAP4-specific PRCM functions.
+obj-$(CONFIG_ARCH_OMAP4)                += prcm.o cm2xxx_3xxx.o cminst44xx.o \
+                                           cm44xx.o prcm_mpu44xx.o \
+                                           prminst44xx.o
+
+# OMAP powerdomain framework
+powerdomain-common                      += powerdomain.o powerdomain-common.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(powerdomain-common) \
+                                           powerdomain2xxx_3xxx.o \
+                                           powerdomains2xxx_data.o \
+                                           powerdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += $(powerdomain-common) \
+                                           powerdomain2xxx_3xxx.o \
+                                           powerdomains3xxx_data.o \
+                                           powerdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common) \
+                                           powerdomain44xx.o \
+                                           powerdomains44xx_data.o
+
+# PRCM clockdomain control
+obj-$(CONFIG_ARCH_OMAP2)                += clockdomain.o \
+                                           clockdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP3)                += clockdomain.o \
+                                           clockdomains2xxx_3xxx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += clockdomain.o \
+                                           clockdomains44xx_data.o
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o \
                                            clkt2xxx_sys.o \
@@ -139,17 +177,20 @@ obj-$(CONFIG_MACH_OMAP_3430SDP)		+= board-3430sdp.o \
                                            hsmmc.o \
                                            board-flash.o
 obj-$(CONFIG_MACH_NOKIA_N8X0)           += board-n8x0.o
+obj-$(CONFIG_MACH_NOKIA_RM680)          += board-rm680.o \
+                                           sdram-nokia.o \
+                                           hsmmc.o
 obj-$(CONFIG_MACH_NOKIA_RX51)           += board-rx51.o \
-                                           board-rx51-sdram.o \
+                                           sdram-nokia.o \
                                            board-rx51-peripherals.o \
                                            board-rx51-video.o \
                                            hsmmc.o
-obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom2.o \
+obj-$(CONFIG_MACH_OMAP_ZOOM2)           += board-zoom.o \
                                            board-zoom-peripherals.o \
                                            board-flash.o \
                                            hsmmc.o \
                                            board-zoom-debugboard.o
-obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom3.o \
+obj-$(CONFIG_MACH_OMAP_ZOOM3)           += board-zoom.o \
                                            board-zoom-peripherals.o \
                                            board-flash.o \
                                            hsmmc.o \
@@ -168,12 +209,16 @@ obj-$(CONFIG_MACH_IGEP0030)		+= board-igep0030.o \
 obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o \
-                                           hsmmc.o
+                                           hsmmc.o \
+                                           omap_phy_internal.o
 obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o \
-                                           hsmmc.o
+                                           hsmmc.o \
+                                           omap_phy_internal.o
 
 obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o
 
+obj-$(CONFIG_MACH_CRANEBOARD)           += board-am3517crane.o
+
 obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o \
                                            hsmmc.o
 # Platform specific device init code
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index b527f8d187ad..e0661777f599 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -135,7 +135,7 @@ static inline void board_smc91x_init(void)
 
 #endif
 
-static struct omap_board_config_kernel sdp2430_config[] = {
+static struct omap_board_config_kernel sdp2430_config[] __initdata = {
         {OMAP_TAG_LCD, &sdp2430_lcd_config},
 };
 
@@ -143,9 +143,9 @@ static void __init omap_2430sdp_init_irq(void)
 {
         omap_board_config = sdp2430_config;
         omap_board_config_size = ARRAY_SIZE(sdp2430_config);
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
@@ -218,8 +218,6 @@ static struct omap_usb_config sdp2430_usb_config __initdata = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static void __init omap_2430sdp_init(void)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 4e3742c512b8..3b39ef1a680a 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -326,9 +326,9 @@ static void __init omap_3430sdp_init_irq(void)
         omap_board_config = sdp3430_config;
         omap_board_config_size = ARRAY_SIZE(sdp3430_config);
         omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
-        omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static int sdp3430_batt_table[] = {
@@ -663,8 +663,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 /*
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index bbcf580fa097..5d41dbe059a3 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -73,18 +73,16 @@ static void __init omap_sdp_init_irq(void)
 {
         omap_board_config = sdp_config;
         omap_board_config_size = ARRAY_SIZE(sdp_config);
-        omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
-                        h8mbx00u0mer0em_sdrc_params);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
+                                  h8mbx00u0mer0em_sdrc_params);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 /*
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index df5a425a49d1..a70bdf28e2bc 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -23,6 +23,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/regulator/machine.h>
 #include <linux/leds.h>
+#include <linux/leds_pwm.h>
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -35,6 +36,7 @@
 #include <plat/usb.h>
 #include <plat/mmc.h>
 
+#include "mux.h"
 #include "hsmmc.h"
 #include "timer-gp.h"
 #include "control.h"
@@ -42,6 +44,7 @@
 #define ETH_KS8851_IRQ                  34
 #define ETH_KS8851_POWER_ON             48
 #define ETH_KS8851_QUART                138
+#define OMAP4SDP_MDM_PWR_EN_GPIO        157
 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO        184
 #define OMAP4_SFH7741_ENABLE_GPIO               188
 
@@ -96,6 +99,28 @@ static struct gpio_led_platform_data sdp4430_led_data = {
         .num_leds       = ARRAY_SIZE(sdp4430_gpio_leds),
 };
 
+static struct led_pwm sdp4430_pwm_leds[] = {
+        {
+                .name           = "omap4:green:chrg",
+                .pwm_id         = 1,
+                .max_brightness = 255,
+                .pwm_period_ns  = 7812500,
+        },
+};
+
+static struct led_pwm_platform_data sdp4430_pwm_data = {
+        .num_leds       = ARRAY_SIZE(sdp4430_pwm_leds),
+        .leds           = sdp4430_pwm_leds,
+};
+
+static struct platform_device sdp4430_leds_pwm = {
+        .name   = "leds_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &sdp4430_pwm_data,
+        },
+};
+
 static int omap_prox_activate(struct device *dev)
 {
         gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
@@ -203,6 +228,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
         &sdp4430_lcd_device,
         &sdp4430_gpio_keys_device,
         &sdp4430_leds_gpio,
+        &sdp4430_leds_pwm,
 };
 
 static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@@ -217,20 +243,37 @@ static void __init omap_4430sdp_init_irq(void)
 {
         omap_board_config = sdp4430_config;
         omap_board_config_size = ARRAY_SIZE(sdp4430_config);
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(1);
 #endif
         gic_init_irq();
-        omap_gpio_init();
 }
 
+static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
+        .port_mode[0]   = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1]   = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[2]   = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .phy_reset      = false,
+        .reset_gpio_port[0]  = -EINVAL,
+        .reset_gpio_port[1]  = -EINVAL,
+        .reset_gpio_port[2]  = -EINVAL,
+};
+
 static struct omap_musb_board_data musb_board_data = {
         .interface_type         = MUSB_INTERFACE_UTMI,
-        .mode                   = MUSB_PERIPHERAL,
+        .mode                   = MUSB_OTG,
         .power                  = 100,
 };
 
+static struct twl4030_usb_data omap4_usbphy_data = {
+        .phy_init       = omap4430_phy_init,
+        .phy_exit       = omap4430_phy_exit,
+        .phy_power      = omap4430_phy_power,
+        .phy_set_clock  = omap4430_phy_set_clk,
+};
+
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -450,6 +493,7 @@ static struct twl4030_platform_data sdp4430_twldata = {
         .vaux1          = &sdp4430_vaux1,
         .vaux2          = &sdp4430_vaux2,
         .vaux3          = &sdp4430_vaux3,
+        .usb            = &omap4_usbphy_data
 };
 
 static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = {
@@ -464,6 +508,9 @@ static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
         {
                 I2C_BOARD_INFO("tmp105", 0x48),
         },
+        {
+                I2C_BOARD_INFO("bh1780", 0x29),
+        },
 };
 static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
         {
@@ -505,20 +552,37 @@ static void __init omap_sfh7741prox_init(void)
         }
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap_4430sdp_init(void)
 {
         int status;
+        int package = OMAP_PACKAGE_CBS;
+
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                package = OMAP_PACKAGE_CBL;
+        omap4_mux_init(board_mux, package);
 
         omap4_i2c_init();
         omap_sfh7741prox_init();
         platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
         omap_serial_init();
         omap4_twl6030_hsmmc_init(mmc);
-        /* OMAP4 SDP uses internal transceiver so register nop transceiver */
-        usb_nop_xceiv_register();
-        /* FIXME: allow multi-omap to boot until musb is updated for omap4 */
-        if (!cpu_is_omap44xx())
-                usb_musb_init(&musb_board_data);
+
+        /* Power on the ULPI PHY */
+        if (gpio_is_valid(OMAP4SDP_MDM_PWR_EN_GPIO)) {
+                /* FIXME: Assumes pad is already muxed for GPIO mode */
+                gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3");
+                gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1);
+        }
+        usb_ehci_init(&ehci_pdata);
+        usb_musb_init(&musb_board_data);
 
         status = omap_ethernet_init();
         if (status) {
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
new file mode 100644
index 000000000000..71acb5ab281c
--- /dev/null
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -0,0 +1,116 @@
+/*
+ * Support for AM3517/05 Craneboard
+ * http://www.mistralsolutions.com/products/craneboard.php
+ *
+ * Copyright (C) 2010 Mistral Solutions Pvt Ltd. <www.mistralsolutions.com>
+ * Author: R.Srinath <srinath@mistralsolutions.com>
+ *
+ * Based on mach-omap2/board-am3517evm.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as  published by the
+ * Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/usb.h>
+
+#include "mux.h"
+#include "control.h"
+
+#define GPIO_USB_POWER          35
+#define GPIO_USB_NRESET         38
+
+
+/* Board initialization */
+static struct omap_board_config_kernel am3517_crane_config[] __initdata = {
+};
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
+static void __init am3517_crane_init_irq(void)
+{
+        omap_board_config = am3517_crane_config;
+        omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
+
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
+        omap_init_irq();
+}
+
+static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
+        .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
+        .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+        .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
+
+        .phy_reset  = true,
+        .reset_gpio_port[0]  = GPIO_USB_NRESET,
+        .reset_gpio_port[1]  = -EINVAL,
+        .reset_gpio_port[2]  = -EINVAL
+};
+
+static void __init am3517_crane_init(void)
+{
+        int ret;
+
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_serial_init();
+
+        /* Configure GPIO for EHCI port */
+        if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
+                pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
+                        GPIO_USB_NRESET);
+                return;
+        }
+
+        if (omap_mux_init_gpio(GPIO_USB_POWER, OMAP_PIN_OUTPUT)) {
+                pr_err("Can not configure mux for GPIO_USB_POWER %d\n",
+                        GPIO_USB_POWER);
+                return;
+        }
+
+        ret = gpio_request(GPIO_USB_POWER, "usb_ehci_enable");
+        if (ret < 0) {
+                pr_err("Can not request GPIO %d\n", GPIO_USB_POWER);
+                return;
+        }
+
+        ret = gpio_direction_output(GPIO_USB_POWER, 1);
+        if (ret < 0) {
+                gpio_free(GPIO_USB_POWER);
+                pr_err("Unable to initialize EHCI power\n");
+                return;
+        }
+
+        usb_ehci_init(&ehci_pdata);
+}
+
+MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .reserve        = omap_reserve,
+        .init_irq       = am3517_crane_init_irq,
+        .init_machine   = am3517_crane_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 07399505312b..bc1562648020 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -389,10 +389,9 @@ static void __init am3517_evm_init_irq(void)
 {
         omap_board_config = am3517_evm_config;
         omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
-
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static struct omap_musb_board_data musb_board_data = {
@@ -442,8 +441,6 @@ static struct omap_board_mux board_mux[] __initdata = {
         OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 2c6db1aaeb29..9f55b68687f7 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -270,7 +270,7 @@ static struct omap_lcd_config apollon_lcd_config __initdata = {
         .ctrl_name      = "internal",
 };
 
-static struct omap_board_config_kernel apollon_config[] = {
+static struct omap_board_config_kernel apollon_config[] __initdata = {
         { OMAP_TAG_LCD,         &apollon_lcd_config },
 };
 
@@ -278,10 +278,9 @@ static void __init omap_apollon_init_irq(void)
 {
         omap_board_config = apollon_config;
         omap_board_config_size = ARRAY_SIZE(apollon_config);
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
         omap_init_irq();
-        omap_gpio_init();
-        apollon_init_smc91x();
 }
 
 static void __init apollon_led_init(void)
@@ -314,8 +313,6 @@ static void __init apollon_usb_init(void)
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static void __init omap_apollon_init(void)
@@ -324,6 +321,7 @@ static void __init omap_apollon_init(void)
 
         omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
 
+        apollon_init_smc91x();
         apollon_led_init();
         apollon_flash_init();
         apollon_usb_init();
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 63f764e2af3f..486a3de5f401 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -600,8 +600,8 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
         .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
 
         .phy_reset  = true,
-        .reset_gpio_port[0]  = -EINVAL,
-        .reset_gpio_port[1]  = -EINVAL,
+        .reset_gpio_port[0]  = OMAP_MAX_GPIO_LINES + 6,
+        .reset_gpio_port[1]  = OMAP_MAX_GPIO_LINES + 7,
         .reset_gpio_port[2]  = -EINVAL
 };
 
@@ -630,12 +630,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
         cm_t35_vmmc1_supply.dev = mmc[0].dev;
         cm_t35_vsim_supply.dev = mmc[0].dev;
 
-        /* setup USB with proper PHY reset GPIOs */
-        ehci_pdata.reset_gpio_port[0] = gpio + 6;
-        ehci_pdata.reset_gpio_port[1] = gpio + 7;
-
-        usb_ehci_init(&ehci_pdata);
-
         return 0;
 }
 
@@ -683,10 +677,10 @@ static void __init cm_t35_init_irq(void)
         omap_board_config = cm_t35_config;
         omap_board_config_size = ARRAY_SIZE(cm_t35_config);
 
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                              mt46h32m32lf6_sdrc_params);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static struct omap_board_mux board_mux[] __initdata = {
@@ -805,6 +799,7 @@ static void __init cm_t35_init(void)
         cm_t35_init_display();
 
         usb_musb_init(&musb_board_data);
+        usb_ehci_init(&ehci_pdata);
 }
 
 MACHINE_START(CM_T35, "Compulab CM-T35")
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 1dd303e9a267..5b0c77732dfc 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -248,9 +248,9 @@ static void __init cm_t3517_init_irq(void)
         omap_board_config = cm_t3517_config;
         omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
 
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static struct omap_board_mux board_mux[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 53ac762518bd..451e7ff08b18 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -118,27 +118,27 @@ static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
         twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0);
 
         if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 1);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 1);
         return 0;
 }
 
 static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
         if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 0);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 0);
 }
 
 static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
 {
         if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 1);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 1);
         return 0;
 }
 
 static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
 {
         if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 0);
+                gpio_set_value_cansleep(dssdev->reset_gpio, 0);
 }
 
 static struct regulator_consumer_supply devkit8000_vmmc1_supply =
@@ -444,13 +444,13 @@ static struct platform_device keys_gpio = {
 
 static void __init devkit8000_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
 #endif
-        omap_gpio_init();
 }
 
 static void __init devkit8000_ads7846_init(void)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index b1c2c9a11c38..0e3d81e09f89 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -37,7 +37,8 @@ static void __init omap_generic_init_irq(void)
 {
         omap_board_config = generic_config;
         omap_board_config_size = ARRAY_SIZE(generic_config);
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
         omap_init_irq();
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 929993b4bf26..25cc9dad4b02 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -51,38 +51,37 @@
 static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
 static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
 
-static int h4_keymap[] = {
+static const unsigned int h4_keymap[] = {
         KEY(0, 0, KEY_LEFT),
-        KEY(0, 1, KEY_RIGHT),
-        KEY(0, 2, KEY_A),
-        KEY(0, 3, KEY_B),
-        KEY(0, 4, KEY_C),
-        KEY(1, 0, KEY_DOWN),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(2, 0, KEY_A),
+        KEY(3, 0, KEY_B),
+        KEY(4, 0, KEY_C),
+        KEY(0, 1, KEY_DOWN),
         KEY(1, 1, KEY_UP),
-        KEY(1, 2, KEY_E),
-        KEY(1, 3, KEY_F),
-        KEY(1, 4, KEY_G),
-        KEY(2, 0, KEY_ENTER),
-        KEY(2, 1, KEY_I),
+        KEY(2, 1, KEY_E),
+        KEY(3, 1, KEY_F),
+        KEY(4, 1, KEY_G),
+        KEY(0, 2, KEY_ENTER),
+        KEY(1, 2, KEY_I),
         KEY(2, 2, KEY_J),
-        KEY(2, 3, KEY_K),
-        KEY(2, 4, KEY_3),
-        KEY(3, 0, KEY_M),
-        KEY(3, 1, KEY_N),
-        KEY(3, 2, KEY_O),
+        KEY(3, 2, KEY_K),
+        KEY(4, 2, KEY_3),
+        KEY(0, 3, KEY_M),
+        KEY(1, 3, KEY_N),
+        KEY(2, 3, KEY_O),
         KEY(3, 3, KEY_P),
-        KEY(3, 4, KEY_Q),
-        KEY(4, 0, KEY_R),
-        KEY(4, 1, KEY_4),
-        KEY(4, 2, KEY_T),
-        KEY(4, 3, KEY_U),
+        KEY(4, 3, KEY_Q),
+        KEY(0, 4, KEY_R),
+        KEY(1, 4, KEY_4),
+        KEY(2, 4, KEY_T),
+        KEY(3, 4, KEY_U),
         KEY(4, 4, KEY_ENTER),
-        KEY(5, 0, KEY_V),
-        KEY(5, 1, KEY_W),
-        KEY(5, 2, KEY_L),
-        KEY(5, 3, KEY_S),
-        KEY(5, 4, KEY_ENTER),
-        0
+        KEY(0, 5, KEY_V),
+        KEY(1, 5, KEY_W),
+        KEY(2, 5, KEY_L),
+        KEY(3, 5, KEY_S),
+        KEY(4, 5, KEY_ENTER),
 };
 
 static struct mtd_partition h4_partitions[] = {
@@ -136,12 +135,16 @@ static struct platform_device h4_flash_device = {
         .resource       = &h4_flash_resource,
 };
 
+static const struct matrix_keymap_data h4_keymap_data = {
+        .keymap         = h4_keymap,
+        .keymap_size    = ARRAY_SIZE(h4_keymap),
+};
+
 static struct omap_kp_platform_data h4_kp_data = {
         .rows           = 6,
         .cols           = 7,
-        .keymap         = h4_keymap,
-        .keymapsize     = ARRAY_SIZE(h4_keymap),
-        .rep            = 1,
+        .keymap_data    = &h4_keymap_data,
+        .rep            = true,
         .row_gpios      = row_gpios,
         .col_gpios      = col_gpios,
 };
@@ -283,7 +286,7 @@ static struct omap_usb_config h4_usb_config __initdata = {
         .hmc_mode       = 0x00,         /* 0:dev|otg 1:disable 2:disable */
 };
 
-static struct omap_board_config_kernel h4_config[] = {
+static struct omap_board_config_kernel h4_config[] __initdata = {
         { OMAP_TAG_LCD,         &h4_lcd_config },
 };
 
@@ -291,9 +294,9 @@ static void __init omap_h4_init_irq(void)
 {
         omap_board_config = h4_config;
         omap_board_config_size = ARRAY_SIZE(h4_config);
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
         omap_init_irq();
-        omap_gpio_init();
         h4_init_flash();
 }
 
@@ -321,8 +324,6 @@ static struct i2c_board_info __initdata h4_i2c_board_info[] = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static void __init omap_h4_init(void)
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 5e035a58b809..0afa3011db0f 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -19,6 +19,7 @@
 #include <linux/interrupt.h>
 
 #include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
 
@@ -136,16 +137,9 @@ static struct mtd_partition igep2_onenand_partitions[] = {
         },
 };
 
-static int igep2_onenand_setup(void __iomem *onenand_base, int freq)
-{
-       /* nothing is required to be setup for onenand as of now */
-       return 0;
-}
-
 static struct omap_onenand_platform_data igep2_onenand_data = {
         .parts = igep2_onenand_partitions,
         .nr_parts = ARRAY_SIZE(igep2_onenand_partitions),
-        .onenand_setup = igep2_onenand_setup,
         .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
 };
 
@@ -159,35 +153,34 @@ static struct platform_device igep2_onenand_device = {
 
 static void __init igep2_flash_init(void)
 {
-        u8              cs = 0;
-        u8              onenandcs = GPMC_CS_NUM + 1;
+        u8 cs = 0;
+        u8 onenandcs = GPMC_CS_NUM + 1;
 
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                u32 ret;
                 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 
                 /* Check if NAND/oneNAND is configured */
                 if ((ret & 0xC00) == 0x800)
                         /* NAND found */
-                        pr_err("IGEP v2: Unsupported NAND found\n");
+                        pr_err("IGEP2: Unsupported NAND found\n");
                 else {
                         ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
                         if ((ret & 0x3F) == (ONENAND_MAP >> 24))
                                 /* ONENAND found */
                                 onenandcs = cs;
                 }
-                cs++;
         }
+
         if (onenandcs > GPMC_CS_NUM) {
-                pr_err("IGEP v2: Unable to find configuration in GPMC\n");
+                pr_err("IGEP2: Unable to find configuration in GPMC\n");
                 return;
         }
 
-        if (onenandcs < GPMC_CS_NUM) {
-                igep2_onenand_data.cs = onenandcs;
-                if (platform_device_register(&igep2_onenand_device) < 0)
-                        pr_err("IGEP v2: Unable to register OneNAND device\n");
-        }
+        igep2_onenand_data.cs = onenandcs;
+
+        if (platform_device_register(&igep2_onenand_device) < 0)
+                pr_err("IGEP2: Unable to register OneNAND device\n");
 }
 
 #else
@@ -254,12 +247,8 @@ static inline void __init igep2_init_smsc911x(void)
 static inline void __init igep2_init_smsc911x(void) { }
 #endif
 
-static struct omap_board_config_kernel igep2_config[] __initdata = {
-};
-
-static struct regulator_consumer_supply igep2_vmmc1_supply = {
-        .supply         = "vmmc",
-};
+static struct regulator_consumer_supply igep2_vmmc1_supply =
+        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
 
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
 static struct regulator_init_data igep2_vmmc1 = {
@@ -276,6 +265,52 @@ static struct regulator_init_data igep2_vmmc1 = {
         .consumer_supplies      = &igep2_vmmc1_supply,
 };
 
+static struct regulator_consumer_supply igep2_vio_supply =
+        REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
+
+static struct regulator_init_data igep2_vio = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = 1,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &igep2_vio_supply,
+};
+
+static struct regulator_consumer_supply igep2_vmmc2_supply =
+        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+
+static struct regulator_init_data igep2_vmmc2 = {
+        .constraints            = {
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .always_on              = 1,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &igep2_vmmc2_supply,
+};
+
+static struct fixed_voltage_config igep2_vwlan = {
+        .supply_name            = "vwlan",
+        .microvolts             = 3300000,
+        .gpio                   = -EINVAL,
+        .enabled_at_boot        = 1,
+        .init_data              = &igep2_vmmc2,
+};
+
+static struct platform_device igep2_vwlan_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &igep2_vwlan,
+        },
+};
+
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -317,6 +352,7 @@ static struct gpio_led igep2_gpio_leds[] = {
                 .name                   = "gpio-led:green:d1",
                 .default_trigger        = "heartbeat",
                 .gpio                   = -EINVAL, /* gets replaced */
+                .active_low             = 1,
         },
 };
 
@@ -342,24 +378,21 @@ static void __init igep2_leds_init(void)
 static inline void igep2_leds_init(void)
 {
         if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED0_RED, 1) == 0)) {
+            (gpio_direction_output(IGEP2_GPIO_LED0_RED, 0) == 0))
                 gpio_export(IGEP2_GPIO_LED0_RED, 0);
-                gpio_set_value(IGEP2_GPIO_LED0_RED, 0);
-        } else
+        else
                 pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n");
 
         if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 1) == 0)) {
+            (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 0) == 0))
                 gpio_export(IGEP2_GPIO_LED0_GREEN, 0);
-                gpio_set_value(IGEP2_GPIO_LED0_GREEN, 0);
-        } else
+        else
                 pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n");
 
         if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED1_RED, 1) == 0)) {
+            (gpio_direction_output(IGEP2_GPIO_LED1_RED, 0) == 0))
                 gpio_export(IGEP2_GPIO_LED1_RED, 0);
-                gpio_set_value(IGEP2_GPIO_LED1_RED, 0);
-        } else
+        else
                 pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n");
 
 }
@@ -373,12 +406,6 @@ static int igep2_twl_gpio_setup(struct device *dev,
         omap2_hsmmc_init(mmc);
 
         /*
-         * link regulators to MMC adapters ... we "know" the
-         * regulators will be set up only *after* we return.
-         */
-        igep2_vmmc1_supply.dev = mmc[0].dev;
-
-        /*
          * REVISIT: need ehci-omap hooks for external VBUS
          * power switch and overcurrent detect
          */
@@ -397,10 +424,9 @@ static int igep2_twl_gpio_setup(struct device *dev,
         /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
 #if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
         if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0)
-            && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) {
+            && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0))
                 gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
-                gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0);
-        } else
+        else
                 pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n");
 #else
         igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -489,15 +515,15 @@ static void __init igep2_display_init(void)
 
 static struct platform_device *igep2_devices[] __initdata = {
         &igep2_dss_device,
+        &igep2_vwlan_device,
 };
 
 static void __init igep2_init_irq(void)
 {
-        omap_board_config = igep2_config;
-        omap_board_config_size = ARRAY_SIZE(igep2_config);
-        omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(m65kxxxxam_sdrc_params,
+                                  m65kxxxxam_sdrc_params);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static struct twl4030_codec_audio_data igep2_audio_data = {
@@ -519,7 +545,7 @@ static struct twl4030_platform_data igep2_twldata = {
         .gpio           = &igep2_twl4030_gpio_pdata,
         .vmmc1          = &igep2_vmmc1,
         .vpll2          = &igep2_vpll2,
-
+        .vio            = &igep2_vio,
 };
 
 static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = {
@@ -577,8 +603,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 #if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
index 22b0b253e16b..bcccd68f1856 100644
--- a/arch/arm/mach-omap2/board-igep0030.c
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -289,9 +289,10 @@ static struct twl4030_usb_data igep3_twl4030_usb_data = {
 
 static void __init igep3_init_irq(void)
 {
-        omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(m65kxxxxam_sdrc_params,
+                                  m65kxxxxam_sdrc_params);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static struct twl4030_platform_data igep3_twl4030_pdata = {
@@ -366,8 +367,6 @@ void __init igep3_wifi_bt_init(void) {}
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static void __init igep3_init(void)
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 001fd9713f39..e5dc74875f9d 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -292,10 +292,9 @@ static void __init omap_ldp_init_irq(void)
 {
         omap_board_config = ldp_config;
         omap_board_config_size = ARRAY_SIZE(ldp_config);
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
         omap_init_irq();
-        omap_gpio_init();
-        ldp_init_smsc911x();
 }
 
 static struct twl4030_usb_data ldp_usb_data = {
@@ -381,8 +380,6 @@ static struct platform_device *ldp_devices[] __initdata = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
@@ -426,6 +423,7 @@ static struct mtd_partition ldp_nand_partitions[] = {
 static void __init omap_ldp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        ldp_init_smsc911x();
         omap_i2c_init();
         platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
         ts_gpio = 54;
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index e823c7042ab3..f396756872b7 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -46,8 +46,7 @@ static struct device *mmc_device;
 #define TUSB6010_GPIO_ENABLE    0
 #define TUSB6010_DMACHAN        0x3f
 
-#if defined(CONFIG_USB_TUSB6010) || \
-        defined(CONFIG_USB_TUSB6010_MODULE)
+#ifdef CONFIG_USB_MUSB_TUSB6010
 /*
  * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
  * 1.5 V voltage regulators of PM companion chip. Companion chip will then
@@ -134,7 +133,7 @@ err:
 
 static void __init n8x0_usb_init(void) {}
 
-#endif /*CONFIG_USB_TUSB6010 */
+#endif /*CONFIG_USB_MUSB_TUSB6010 */
 
 
 static struct omap2_mcspi_device_config p54spi_mcspi_config = {
@@ -184,23 +183,15 @@ static struct mtd_partition onenand_partitions[] = {
         },
 };
 
-static struct omap_onenand_platform_data board_onenand_data = {
-        .cs             = 0,
-        .gpio_irq       = 26,
-        .parts          = onenand_partitions,
-        .nr_parts       = ARRAY_SIZE(onenand_partitions),
-        .flags          = ONENAND_SYNC_READ,
+static struct omap_onenand_platform_data board_onenand_data[] = {
+        {
+                .cs             = 0,
+                .gpio_irq       = 26,
+                .parts          = onenand_partitions,
+                .nr_parts       = ARRAY_SIZE(onenand_partitions),
+                .flags          = ONENAND_SYNC_READ,
+        }
 };
-
-static void __init n8x0_onenand_init(void)
-{
-        gpmc_onenand_init(&board_onenand_data);
-}
-
-#else
-
-static void __init n8x0_onenand_init(void) {}
-
 #endif
 
 #if defined(CONFIG_MENELAUS) &&                                         \
@@ -639,9 +630,9 @@ static void __init n8x0_map_io(void)
 
 static void __init n8x0_init_irq(void)
 {
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 #ifdef CONFIG_OMAP_MUX
@@ -653,8 +644,43 @@ static struct omap_board_mux board_mux[] __initdata = {
         OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
+
+static struct omap_device_pad serial2_pads[] __initdata = {
+        {
+                .name   = "uart3_rx_irrx.uart3_rx_irrx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_MUX_MODE0,
+                .idle   = OMAP_MUX_MODE3        /* Mux as GPIO for idle */
+        },
+};
+
+static inline void board_serial_init(void)
+{
+        struct omap_board_data bdata;
+
+        bdata.flags = 0;
+        bdata.pads = NULL;
+        bdata.pads_cnt = 0;
+
+        bdata.id = 0;
+        omap_serial_init_port(&bdata);
+
+        bdata.id = 1;
+        omap_serial_init_port(&bdata);
+
+        bdata.id = 2;
+        bdata.pads = serial2_pads;
+        bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
+        omap_serial_init_port(&bdata);
+}
+
 #else
-#define board_mux       NULL
+
+static inline void board_serial_init(void)
+{
+        omap_serial_init();
+}
+
 #endif
 
 static void __init n8x0_init_machine(void)
@@ -669,9 +695,8 @@ static void __init n8x0_init_machine(void)
         if (machine_is_nokia_n810())
                 i2c_register_board_info(2, n810_i2c_board_info_2,
                                         ARRAY_SIZE(n810_i2c_board_info_2));
-
-        omap_serial_init();
-        n8x0_onenand_init();
+        board_serial_init();
+        gpmc_onenand_init(board_onenand_data);
         n8x0_mmc_init();
         n8x0_usb_init();
 }
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 14f42240ae79..6c127605942f 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -484,13 +484,13 @@ static struct platform_device keys_gpio = {
 
 static void __init omap3_beagle_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
 #endif
-        omap_gpio_init();
 }
 
 static struct platform_device *omap3_beagle_devices[] __initdata = {
@@ -548,8 +548,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b04365c6bb10..3de8d9b8ec76 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -623,9 +623,9 @@ static void __init omap3_evm_init_irq(void)
 {
         omap_board_config = omap3_evm_config;
         omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static struct platform_device *omap3_evm_devices[] __initdata = {
@@ -654,8 +654,6 @@ static struct omap_board_mux board_mux[] __initdata = {
                                 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 5f7d2c1e7ef5..15e4b08e99ba 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -197,17 +197,15 @@ static inline void __init board_smsc911x_init(void)
 
 static void __init omap3logic_init_irq(void)
 {
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static void __init omap3logic_init(void)
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 89ed1be2d62e..0b34beded11f 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -293,7 +293,7 @@ static struct omap2_hsmmc_info omap3pandora_mmc[] = {
         },
         {
                 .mmc            = 3,
-                .caps           = MMC_CAP_4_BIT_DATA,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = -EINVAL,
                 .init_card      = pandora_wl1251_init_card,
@@ -636,37 +636,19 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
 
 static void __init omap3pandora_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
         omap_init_irq();
-        omap_gpio_init();
-}
-
-static void pandora_wl1251_set_power(bool enable)
-{
-        /*
-         * Keep power always on until wl1251_sdio driver learns to re-init
-         * the chip after powering it down and back up.
-         */
 }
 
-static struct wl12xx_platform_data pandora_wl1251_pdata = {
-        .set_power      = pandora_wl1251_set_power,
-        .use_eeprom     = true,
-};
-
-static struct platform_device pandora_wl1251_data = {
-        .name           = "wl1251_data",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &pandora_wl1251_pdata,
-        },
-};
-
-static void pandora_wl1251_init(void)
+static void __init pandora_wl1251_init(void)
 {
+        struct wl12xx_platform_data pandora_wl1251_pdata;
         int ret;
 
+        memset(&pandora_wl1251_pdata, 0, sizeof(pandora_wl1251_pdata));
+
         ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq");
         if (ret < 0)
                 goto fail;
@@ -679,6 +661,11 @@ static void pandora_wl1251_init(void)
         if (pandora_wl1251_pdata.irq < 0)
                 goto fail_irq;
 
+        pandora_wl1251_pdata.use_eeprom = true;
+        ret = wl12xx_set_platform_data(&pandora_wl1251_pdata);
+        if (ret < 0)
+                goto fail_irq;
+
         return;
 
 fail_irq:
@@ -691,7 +678,6 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_leds_gpio,
         &pandora_keys_gpio,
         &pandora_dss_device,
-        &pandora_wl1251_data,
         &pandora_vwlan_device,
 };
 
@@ -711,8 +697,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index f25272125413..9df9d9367608 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -584,12 +584,12 @@ static void __init omap3_stalker_init_irq(void)
 {
         omap_board_config = omap3_stalker_config;
         omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
 #endif
-        omap_gpio_init();
 }
 
 static struct platform_device *omap3_stalker_devices[] __initdata = {
@@ -616,8 +616,6 @@ static struct omap_board_mux board_mux[] __initdata = {
                   OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
         {.reg_offset = OMAP_MUX_TERMINATOR},
 };
-#else
-#define board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 41104bb8774c..db1f74fe6c4f 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -413,8 +413,6 @@ static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static void __init omap3_touchbook_init_irq(void)
@@ -422,13 +420,13 @@ static void __init omap3_touchbook_init_irq(void)
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_board_config = omap3_touchbook_config;
         omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
 #endif
-        omap_gpio_init();
 }
 
 static struct platform_device *omap3_touchbook_devices[] __initdata = {
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 1ecd0a6cefb7..3094e2007844 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -40,6 +40,7 @@
 
 #include "hsmmc.h"
 #include "control.h"
+#include "mux.h"
 
 #define GPIO_HUB_POWER          1
 #define GPIO_HUB_NRESET         62
@@ -76,9 +77,9 @@ static struct platform_device *panda_devices[] __initdata = {
 
 static void __init omap4_panda_init_irq(void)
 {
-        omap2_init_common_hw(NULL, NULL);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(NULL, NULL);
         gic_init_irq();
-        omap_gpio_init();
 }
 
 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
@@ -133,15 +134,23 @@ error1:
 
 static struct omap_musb_board_data musb_board_data = {
         .interface_type         = MUSB_INTERFACE_UTMI,
-        .mode                   = MUSB_PERIPHERAL,
+        .mode                   = MUSB_OTG,
         .power                  = 100,
 };
 
+static struct twl4030_usb_data omap4_usbphy_data = {
+        .phy_init       = omap4430_phy_init,
+        .phy_exit       = omap4430_phy_exit,
+        .phy_power      = omap4430_phy_power,
+        .phy_set_clock  = omap4430_phy_set_clk,
+};
+
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
                 .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
         },
         {}      /* Terminator */
 };
@@ -345,6 +354,7 @@ static struct twl4030_platform_data omap4_panda_twldata = {
         .vaux1          = &omap4_panda_vaux1,
         .vaux2          = &omap4_panda_vaux2,
         .vaux3          = &omap4_panda_vaux3,
+        .usb            = &omap4_usbphy_data,
 };
 
 static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = {
@@ -368,8 +378,23 @@ static int __init omap4_panda_i2c_init(void)
         omap_register_i2c_bus(4, 400, NULL, 0);
         return 0;
 }
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux       NULL
+#endif
+
 static void __init omap4_panda_init(void)
 {
+        int package = OMAP_PACKAGE_CBS;
+
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                package = OMAP_PACKAGE_CBL;
+        omap4_mux_init(board_mux, package);
+
         omap4_panda_i2c_init();
         platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
         omap_serial_init();
@@ -377,9 +402,7 @@ static void __init omap4_panda_init(void)
         /* OMAP4 Panda uses internal transceiver so register nop transceiver */
         usb_nop_xceiv_register();
         omap4_ehci_init();
-        /* FIXME: allow multi-omap to boot until musb is updated for omap4 */
-        if (!cpu_is_omap44xx())
-                usb_musb_init(&musb_board_data);
+        usb_musb_init(&musb_board_data);
 }
 
 static void __init omap4_panda_map_io(void)
@@ -391,6 +414,7 @@ static void __init omap4_panda_map_io(void)
 MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
         /* Maintainer: David Anders - Texas Instruments Inc */
         .boot_params    = 0x80000100,
+        .reserve        = omap_reserve,
         .map_io         = omap4_panda_map_io,
         .init_irq       = omap4_panda_init_irq,
         .init_machine   = omap4_panda_init,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 7053bc0b46db..cb26e5d8268d 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -413,10 +413,10 @@ static void __init overo_init_irq(void)
 {
         omap_board_config = overo_config;
         omap_board_config_size = ARRAY_SIZE(overo_config);
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                             mt46h32m32lf6_sdrc_params);
+        omap2_init_common_infrastructure();
+        omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                  mt46h32m32lf6_sdrc_params);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 static struct platform_device *overo_devices[] __initdata = {
@@ -438,8 +438,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
new file mode 100644
index 000000000000..cb77be7ac44f
--- /dev/null
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -0,0 +1,187 @@
+/*
+ * Board support file for Nokia RM-680.
+ *
+ * Copyright (C) 2010 Nokia
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/i2c/twl.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/consumer.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <plat/i2c.h>
+#include <plat/mmc.h>
+#include <plat/usb.h>
+#include <plat/gpmc.h>
+#include <plat/common.h>
+#include <plat/onenand.h>
+
+#include "mux.h"
+#include "hsmmc.h"
+#include "sdram-nokia.h"
+
+static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
+        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
+};
+
+/* Fixed regulator for internal eMMC */
+static struct regulator_init_data rm680_vemmc = {
+        .constraints =  {
+                .name                   = "rm680_vemmc",
+                .min_uV                 = 2900000,
+                .max_uV                 = 2900000,
+                .apply_uV               = 1,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS
+                                        | REGULATOR_CHANGE_MODE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(rm680_vemmc_consumers),
+        .consumer_supplies              = rm680_vemmc_consumers,
+};
+
+static struct fixed_voltage_config rm680_vemmc_config = {
+        .supply_name            = "VEMMC",
+        .microvolts             = 2900000,
+        .gpio                   = 157,
+        .startup_delay          = 150,
+        .enable_high            = 1,
+        .init_data              = &rm680_vemmc,
+};
+
+static struct platform_device rm680_vemmc_device = {
+        .name                   = "reg-fixed-voltage",
+        .dev                    = {
+                .platform_data  = &rm680_vemmc_config,
+        },
+};
+
+static struct platform_device *rm680_peripherals_devices[] __initdata = {
+        &rm680_vemmc_device,
+};
+
+/* TWL */
+static struct twl4030_gpio_platform_data rm680_gpio_data = {
+        .gpio_base              = OMAP_MAX_GPIO_LINES,
+        .irq_base               = TWL4030_GPIO_IRQ_BASE,
+        .irq_end                = TWL4030_GPIO_IRQ_END,
+        .pullups                = BIT(0),
+        .pulldowns              = BIT(1) | BIT(2) | BIT(8) | BIT(15),
+};
+
+static struct twl4030_usb_data rm680_usb_data = {
+        .usb_mode               = T2_USB_MODE_ULPI,
+};
+
+static struct twl4030_platform_data rm680_twl_data = {
+        .irq_base               = TWL4030_IRQ_BASE,
+        .irq_end                = TWL4030_IRQ_END,
+        .gpio                   = &rm680_gpio_data,
+        .usb                    = &rm680_usb_data,
+        /* add rest of the children here */
+};
+
+static struct i2c_board_info __initdata rm680_twl_i2c_board_info[] = {
+        {
+                I2C_BOARD_INFO("twl5031", 0x48),
+                .flags          = I2C_CLIENT_WAKE,
+                .irq            = INT_34XX_SYS_NIRQ,
+                .platform_data  = &rm680_twl_data,
+        },
+};
+
+static void __init rm680_i2c_init(void)
+{
+        omap_register_i2c_bus(1, 2900, rm680_twl_i2c_board_info,
+                                ARRAY_SIZE(rm680_twl_i2c_board_info));
+        omap_register_i2c_bus(2, 400, NULL, 0);
+        omap_register_i2c_bus(3, 400, NULL, 0);
+}
+
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+static struct omap_onenand_platform_data board_onenand_data[] = {
+        {
+                .gpio_irq       = 65,
+                .flags          = ONENAND_SYNC_READWRITE,
+        }
+};
+#endif
+
+/* eMMC */
+static struct omap2_hsmmc_info mmc[] __initdata = {
+        {
+                .name           = "internal",
+                .mmc            = 2,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED,
+                .gpio_cd        = -EINVAL,
+                .gpio_wp        = -EINVAL,
+        },
+        { /* Terminator */ }
+};
+
+static void __init rm680_peripherals_init(void)
+{
+        platform_add_devices(rm680_peripherals_devices,
+                                ARRAY_SIZE(rm680_peripherals_devices));
+        rm680_i2c_init();
+        gpmc_onenand_init(board_onenand_data);
+        omap2_hsmmc_init(mmc);
+}
+
+static void __init rm680_init_irq(void)
+{
+        struct omap_sdrc_params *sdrc_params;
+
+        omap2_init_common_infrastructure();
+        sdrc_params = nokia_get_sdram_timings();
+        omap2_init_common_devices(sdrc_params, sdrc_params);
+        omap_init_irq();
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#endif
+
+static struct omap_musb_board_data rm680_musb_data = {
+        .interface_type = MUSB_INTERFACE_ULPI,
+        .mode           = MUSB_PERIPHERAL,
+        .power          = 100,
+};
+
+static void __init rm680_init(void)
+{
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_serial_init();
+        usb_musb_init(&rm680_musb_data);
+        rm680_peripherals_init();
+}
+
+static void __init rm680_map_io(void)
+{
+        omap2_set_globals_3xxx();
+        omap34xx_map_common_io();
+}
+
+MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
+        .boot_params    = 0x80000100,
+        .map_io         = rm680_map_io,
+        .reserve        = omap_reserve,
+        .init_irq       = rm680_init_irq,
+        .init_machine   = rm680_init,
+        .timer          = &omap_timer,
+MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 3fec4d62a91a..e75e240cad67 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -23,7 +23,6 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
-#include <sound/tlv320aic3x.h>
 
 #include <plat/mcspi.h>
 #include <plat/board.h>
@@ -293,6 +292,8 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 
+static struct omap_mux_partition *partition;
+
 /*
  * Current flows to eMMC when eMMC is off and the data lines are pulled up,
  * so pull them down. N.B. we pull 8 lines because we are using 8 lines.
@@ -300,9 +301,9 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = {
 static void rx51_mmc2_remux(struct device *dev, int slot, int power_on)
 {
         if (power_on)
-                omap_mux_write_array(rx51_mmc2_on_mux);
+                omap_mux_write_array(partition, rx51_mmc2_on_mux);
         else
-                omap_mux_write_array(rx51_mmc2_off_mux);
+                omap_mux_write_array(partition, rx51_mmc2_off_mux);
 }
 
 static struct omap2_hsmmc_info mmc[] __initdata = {
@@ -342,6 +343,8 @@ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
         /* tlv320aic3x analog supplies */
         REGULATOR_SUPPLY("AVDD", "2-0018"),
         REGULATOR_SUPPLY("DRVDD", "2-0018"),
+        REGULATOR_SUPPLY("AVDD", "2-0019"),
+        REGULATOR_SUPPLY("DRVDD", "2-0019"),
         /* tpa6130a2 */
         REGULATOR_SUPPLY("Vdd", "2-0060"),
         /* Keep vmmc as last item. It is not iterated for newer boards */
@@ -352,19 +355,16 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
         /* tlv320aic3x digital supplies */
         REGULATOR_SUPPLY("IOVDD", "2-0018"),
         REGULATOR_SUPPLY("DVDD", "2-0018"),
+        REGULATOR_SUPPLY("IOVDD", "2-0019"),
+        REGULATOR_SUPPLY("DVDD", "2-0019"),
 };
 
-#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
-extern struct platform_device rx51_display_device;
-#endif
-
 static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
-#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
-        {
-                .supply = "vdds_sdi",
-                .dev    = &rx51_display_device.dev,
-        },
-#endif
+        REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
+};
+
+static struct regulator_consumer_supply rx51_vdac_supply[] = {
+        REGULATOR_SUPPLY("vdda_dac", "omapdss"),
 };
 
 static struct regulator_init_data rx51_vaux1 = {
@@ -484,14 +484,17 @@ static struct regulator_init_data rx51_vsim = {
 
 static struct regulator_init_data rx51_vdac = {
         .constraints = {
+                .name                   = "VDAC",
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
+                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = rx51_vdac_supply,
 };
 
 static struct regulator_init_data rx51_vio = {
@@ -717,7 +720,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
         .vio                    = &rx51_vio,
 };
 
-static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata = {
+static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module = {
         .id                     = TPA6130A2,
         .power_gpio             = 98,
 };
@@ -742,11 +745,19 @@ static struct aic3x_pdata rx51_aic3x_data = {
         .gpio_reset = 60,
 };
 
+static struct aic3x_pdata rx51_aic3x_data2 = {
+        .gpio_reset = 60,
+};
+
 static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
         {
                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
                 .platform_data = &rx51_aic3x_data,
         },
+        {
+                I2C_BOARD_INFO("tlv320aic3x", 0x19),
+                .platform_data = &rx51_aic3x_data2,
+        },
 #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
         {
                 I2C_BOARD_INFO("tsl2563", 0x29),
@@ -815,25 +826,15 @@ static struct mtd_partition onenand_partitions[] = {
         },
 };
 
-static struct omap_onenand_platform_data board_onenand_data = {
-        .cs             = 0,
-        .gpio_irq       = 65,
-        .parts          = onenand_partitions,
-        .nr_parts       = ARRAY_SIZE(onenand_partitions),
-        .flags          = ONENAND_SYNC_READWRITE,
+static struct omap_onenand_platform_data board_onenand_data[] = {
+        {
+                .cs             = 0,
+                .gpio_irq       = 65,
+                .parts          = onenand_partitions,
+                .nr_parts       = ARRAY_SIZE(onenand_partitions),
+                .flags          = ONENAND_SYNC_READWRITE,
+        }
 };
-
-static void __init board_onenand_init(void)
-{
-        gpmc_onenand_init(&board_onenand_data);
-}
-
-#else
-
-static inline void board_onenand_init(void)
-{
-}
-
 #endif
 
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
@@ -916,13 +917,17 @@ error:
 void __init rx51_peripherals_init(void)
 {
         rx51_i2c_init();
-        board_onenand_init();
+        gpmc_onenand_init(board_onenand_data);
         board_smc91x_init();
         rx51_add_gpio_keys();
         rx51_init_wl1251();
         spi_register_board_info(rx51_peripherals_spi_board_info,
                                 ARRAY_SIZE(rx51_peripherals_spi_board_info));
-        omap2_hsmmc_init(mmc);
+
+        partition = omap_mux_get("core");
+        if (partition)
+                omap2_hsmmc_init(mmc);
+
         platform_device_register(&rx51_charger_device);
 }
 
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 85503fed4e13..acd670054d9a 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -14,7 +14,6 @@
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
 #include <linux/mm.h>
-
 #include <asm/mach-types.h>
 #include <plat/display.h>
 #include <plat/vram.h>
@@ -49,8 +48,16 @@ static struct omap_dss_device rx51_lcd_device = {
         .platform_disable       = rx51_lcd_disable,
 };
 
+static struct omap_dss_device  rx51_tv_device = {
+        .name                   = "tv",
+        .type                   = OMAP_DISPLAY_TYPE_VENC,
+        .driver_name            = "venc",
+        .phy.venc.type          = OMAP_DSS_VENC_TYPE_COMPOSITE,
+};
+
 static struct omap_dss_device *rx51_dss_devices[] = {
         &rx51_lcd_device,
+        &rx51_tv_device,
 };
 
 static struct omap_dss_board_info rx51_dss_board_info = {
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 36f2cf4efd57..f53fc551c58f 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -32,10 +32,10 @@
 
 #include "mux.h"
 #include "pm.h"
+#include "sdram-nokia.h"
 
 #define RX51_GPIO_SLEEP_IND 162
 
-struct omap_sdrc_params *rx51_get_sdram_timings(void);
 extern void rx51_video_mem_init(void);
 
 static struct gpio_led gpio_leds[] = {
@@ -105,10 +105,10 @@ static void __init rx51_init_irq(void)
         omap_board_config = rx51_config;
         omap_board_config_size = ARRAY_SIZE(rx51_config);
         omap3_pm_init_cpuidle(rx51_cpuidle_params);
-        sdrc_params = rx51_get_sdram_timings();
-        omap2_init_common_hw(sdrc_params, sdrc_params);
+        omap2_init_common_infrastructure();
+        sdrc_params = nokia_get_sdram_timings();
+        omap2_init_common_devices(sdrc_params, sdrc_params);
         omap_init_irq();
-        omap_gpio_init();
 }
 
 extern void __init rx51_peripherals_init(void);
@@ -117,8 +117,6 @@ extern void __init rx51_peripherals_init(void);
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-#else
-#define board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 9db9203667df..3fbd0edd712e 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -196,7 +196,7 @@ struct wl12xx_platform_data omap_zoom_wlan_data __initdata = {
         .board_ref_clock = 1,
 };
 
-static struct omap2_hsmmc_info mmc[] __initdata = {
+static struct omap2_hsmmc_info mmc[] = {
         {
                 .name           = "external",
                 .mmc            = 1,
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom.c
index 5adde12c0395..e041c537ea37 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -1,6 +1,9 @@
 /*
- * Copyright (C) 2009 Texas Instruments Inc.
+ * Copyright (C) 2009-2010 Texas Instruments Inc.
+ * Mikkel Christensen <mlc@ti.com>
+ * Felipe Balbi <balbi@ti.com>
  *
+ * Modified from mach-omap2/board-ldp.c
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,22 +15,55 @@
 #include <linux/platform_device.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/i2c/twl.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/board-zoom.h>
-
 #include <plat/common.h>
 #include <plat/board.h>
 #include <plat/usb.h>
 
+#include <mach/board-zoom.h>
+
 #include "board-flash.h"
 #include "mux.h"
+#include "sdram-micron-mt46h32m32lf-6.h"
 #include "sdram-hynix-h8mbx00u0mer-0em.h"
 
-static struct omap_board_config_kernel zoom_config[] __initdata = {
+#define ZOOM3_EHCI_RESET_GPIO           64
+
+static void __init omap_zoom_init_irq(void)
+{
+        omap2_init_common_infrastructure();
+        if (machine_is_omap_zoom2())
+                omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
+                                          mt46h32m32lf6_sdrc_params);
+        else if (machine_is_omap_zoom3())
+                omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
+                                          h8mbx00u0mer0em_sdrc_params);
+
+        omap_init_irq();
+}
+
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+        /* WLAN IRQ - GPIO 162 */
+        OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN POWER ENABLE - GPIO 101 */
+        OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* WLAN SDIO: MMC3 CMD */
+        OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN SDIO: MMC3 CLK */
+        OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN SDIO: MMC3 DAT[0-3] */
+        OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
+#endif
 
 static struct mtd_partition zoom_nand_partitions[] = {
         /* All the partition sizes are listed in terms of NAND block size */
@@ -70,59 +106,41 @@ static struct mtd_partition zoom_nand_partitions[] = {
         },
 };
 
-static void __init omap_zoom_init_irq(void)
-{
-        omap_board_config = zoom_config;
-        omap_board_config_size = ARRAY_SIZE(zoom_config);
-        omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
-                        h8mbx00u0mer0em_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
-}
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        /* WLAN IRQ - GPIO 162 */
-        OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN POWER ENABLE - GPIO 101 */
-        OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        /* WLAN SDIO: MMC3 CMD */
-        OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC3 CLK */
-        OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC3 DAT[0-3] */
-        OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define board_mux       NULL
-#endif
-
 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
         .port_mode[0]           = EHCI_HCD_OMAP_MODE_UNKNOWN,
         .port_mode[1]           = EHCI_HCD_OMAP_MODE_PHY,
         .port_mode[2]           = EHCI_HCD_OMAP_MODE_UNKNOWN,
         .phy_reset              = true,
         .reset_gpio_port[0]     = -EINVAL,
-        .reset_gpio_port[1]     = 64,
+        .reset_gpio_port[1]     = ZOOM3_EHCI_RESET_GPIO,
         .reset_gpio_port[2]     = -EINVAL,
 };
 
 static void __init omap_zoom_init(void)
 {
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
-        zoom_peripherals_init();
+        if (machine_is_omap_zoom2()) {
+                omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        } else if (machine_is_omap_zoom3()) {
+                omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
+                omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT);
+                usb_ehci_init(&ehci_pdata);
+        }
+
         board_nand_init(zoom_nand_partitions,
-                         ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
+                        ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
         zoom_debugboard_init();
-
-        omap_mux_init_gpio(64, OMAP_PIN_OUTPUT);
-        usb_ehci_init(&ehci_pdata);
+        zoom_peripherals_init();
 }
 
+MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
+        .boot_params    = 0x80000100,
+        .map_io         = omap3_map_io,
+        .reserve        = omap_reserve,
+        .init_irq       = omap_zoom_init_irq,
+        .init_machine   = omap_zoom_init,
+        .timer          = &omap_timer,
+MACHINE_END
+
 MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
         .boot_params    = 0x80000100,
         .map_io         = omap3_map_io,
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
deleted file mode 100644
index 2992a9f3a585..000000000000
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Inc.
- * Mikkel Christensen <mlc@ti.com>
- *
- * Modified from mach-omap2/board-ldp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/gpio.h>
-#include <linux/i2c/twl.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <plat/common.h>
-#include <plat/board.h>
-
-#include <mach/board-zoom.h>
-
-#include "board-flash.h"
-#include "mux.h"
-#include "sdram-micron-mt46h32m32lf-6.h"
-
-static void __init omap_zoom2_init_irq(void)
-{
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
-                                 mt46h32m32lf6_sdrc_params);
-        omap_init_irq();
-        omap_gpio_init();
-}
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        /* WLAN IRQ - GPIO 162 */
-        OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN POWER ENABLE - GPIO 101 */
-        OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        /* WLAN SDIO: MMC3 CMD */
-        OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC3 CLK */
-        OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC3 DAT[0-3] */
-        OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define board_mux       NULL
-#endif
-
-static struct mtd_partition zoom_nand_partitions[] = {
-        /* All the partition sizes are listed in terms of NAND block size */
-        {
-                .name           = "X-Loader-NAND",
-                .offset         = 0,
-                .size           = 4 * (64 * 2048),      /* 512KB, 0x80000 */
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "U-Boot-NAND",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
-                .size           = 10 * (64 * 2048),     /* 1.25MB, 0x140000 */
-                .mask_flags     = MTD_WRITEABLE,        /* force read-only */
-        },
-        {
-                .name           = "Boot Env-NAND",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1c0000 */
-                .size           = 2 * (64 * 2048),      /* 256KB, 0x40000 */
-        },
-        {
-                .name           = "Kernel-NAND",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x0200000*/
-                .size           = 240 * (64 * 2048),    /* 30M, 0x1E00000 */
-        },
-        {
-                .name           = "system",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x2000000 */
-                .size           = 3328 * (64 * 2048),   /* 416M, 0x1A000000 */
-        },
-        {
-                .name           = "userdata",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1C000000*/
-                .size           = 256 * (64 * 2048),    /* 32M, 0x2000000 */
-        },
-        {
-                .name           = "cache",
-                .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x1E000000*/
-                .size           = 256 * (64 * 2048),    /* 32M, 0x2000000 */
-        },
-};
-
-static void __init omap_zoom2_init(void)
-{
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        zoom_peripherals_init();
-        board_nand_init(zoom_nand_partitions,
-                        ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
-        zoom_debugboard_init();
-}
-
-MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
-        .boot_params    = 0x80000100,
-        .map_io         = omap3_map_io,
-        .reserve        = omap_reserve,
-        .init_irq       = omap_zoom2_init_irq,
-        .init_machine   = omap_zoom2_init,
-        .timer          = &omap_timer,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index 66e01acfd585..f51cffd1fc53 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -26,7 +26,7 @@
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 
 /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */
@@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
 
         apll_mask = EN_APLL_LOCKED << clk->enable_bit;
 
-        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 
         if ((cval & apll_mask) == apll_mask)
                 return 0;   /* apll already enabled */
 
         cval &= ~apll_mask;
         cval |= apll_mask;
-        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+        omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 
         omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
                              OMAP24XX_CM_IDLEST_VAL, clk->name);
@@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk)
 {
         u32 cval;
 
-        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+        cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
         cval &= ~(EN_APLL_LOCKED << clk->enable_bit);
-        cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
+        omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 }
 
 /* Public data */
@@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void)
 {
         u32 aplls, srate = 0;
 
-        aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
+        aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 019048434f13..4ae439222085 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -32,7 +32,7 @@
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 
 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
@@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
 
         core_clk = omap2_get_dpll_rate(clk);
 
-        v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
         v &= OMAP24XX_CORE_CLK_SRC_MASK;
 
         if (v == CORE_CLK_SRC_32K)
@@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
 {
         u32 high, low, core_clk_src;
 
-        core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
         core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK;
 
         if (core_clk_src == CORE_CLK_SRC_DPLL) {        /* DPLL clockout */
@@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
         const struct dpll_data *dd;
 
         cur_rate = omap2xxx_clk_get_core_rate(dclk);
-        mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+        mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 
         if ((rate == (cur_rate / 2)) && (mult == 2)) {
@@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
                 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
                                            dd->div1_mask);
                 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
-                tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
+                tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
                 tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK;
                 if (rate > low) {
                         tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2;
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index 2167be84a5bc..df7b80506483 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -27,7 +27,7 @@
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 
 static int omap2_enable_osc_ck(struct clk *clk)
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
index 822b5a79f457..8693cfdac49a 100644
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -26,7 +26,7 @@
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 
 void __iomem *prcm_clksrc_ctrl;
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index aef62918aaf0..39f9d5a58d0c 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -40,7 +40,7 @@
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 
 const struct prcm_config *curr_prcm_set;
@@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
                         done_rate = CORE_CLK_SRC_DPLL;
 
                 /* MPU divider */
-                cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
+                omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL);
 
                 /* dsp + iva1 div(2420), iva2.1(2430) */
-                cm_write_mod_reg(prcm->cm_clksel_dsp,
+                omap2_cm_write_mod_reg(prcm->cm_clksel_dsp,
                                  OMAP24XX_DSP_MOD, CM_CLKSEL);
 
-                cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
+                omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL);
 
                 /* Major subsystem dividers */
-                tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
-                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
+                tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
+                omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
                                  CM_CLKSEL1);
 
                 if (cpu_is_omap2430())
-                        cm_write_mod_reg(prcm->cm_clksel_mdm,
+                        omap2_cm_write_mod_reg(prcm->cm_clksel_mdm,
                                          OMAP2430_MDM_MOD, CM_CLKSEL);
 
                 /* x2 to enter omap2xxx_sdrc_init_params() */
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 6ce512e902c6..337392c3f549 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -24,7 +24,6 @@
 #include <plat/clock.h>
 
 #include "clock.h"
-#include "cm.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index b5babf5440e4..2a2f15213add 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -24,14 +24,12 @@
 #include <linux/bitops.h>
 
 #include <plat/clock.h>
-#include <plat/clockdomain.h>
+#include "clockdomain.h"
 #include <plat/cpu.h>
 #include <plat/prcm.h>
 
 #include "clock.h"
-#include "prm.h"
-#include "prm-regbits-24xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a535c7a2a62a..896584e3c4ab 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -49,7 +49,6 @@
 
 /* DPLL Type and DCO Selection Flags */
 #define DPLL_J_TYPE             0x1
-#define DPLL_NO_DCO_SEL         0x2
 
 int omap2_clk_enable(struct clk *clk);
 void omap2_clk_disable(struct clk *clk);
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 21f856252ad8..0a992bc8d0d8 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -22,8 +22,8 @@
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "prm.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
@@ -812,7 +812,7 @@ static struct clk dss2_fck = {		/* Alt clk used in power management */
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
         .clksel         = dss2_fck_clksel,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
@@ -1862,10 +1862,10 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_242X),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_242X),
-        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_242X),
-        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
+        CLK("omap_i2c.1", "fck",        &i2c1_fck,      CK_242X),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
+        CLK("omap_i2c.2", "fck",        &i2c2_fck,      CK_242X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
@@ -1877,7 +1877,7 @@ static struct omap_clk omap2420_clks[] = {
         CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
-        CLK("musb_hdrc",        "fck",  &osc_ck,        CK_242X),
+        CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c
index 44d0cccc51a9..d87bc9cb2a36 100644
--- a/arch/arm/mach-omap2/clock2430.c
+++ b/arch/arm/mach-omap2/clock2430.c
@@ -25,7 +25,7 @@
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 
 /**
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index e32afcbdfb88..c047dcd007e5 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -22,8 +22,8 @@
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "prm.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
@@ -800,7 +800,7 @@ static struct clk dss2_fck = {		/* Alt clk used in power management */
         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
         .clksel         = dss2_fck_clksel,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
@@ -1969,10 +1969,10 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_243X),
-        CLK("i2c_omap.1", "fck",        &i2chs1_fck,    CK_243X),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_243X),
-        CLK("i2c_omap.2", "fck",        &i2chs2_fck,    CK_243X),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
+        CLK("omap_i2c.1", "fck",        &i2chs1_fck,    CK_243X),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
+        CLK("omap_i2c.2", "fck",        &i2chs2_fck,    CK_243X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
@@ -1983,7 +1983,7 @@ static struct omap_clk omap2430_clks[] = {
         CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
-        CLK("musb_hdrc",        "ick",  &usbhs_ick,     CK_243X),
+        CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
         CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
         CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
         CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6febd5f11e85..287abc480924 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -25,7 +25,7 @@
 
 #include "clock.h"
 #include "clock34xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /**
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
index b496a9305e1c..74116a3cf099 100644
--- a/arch/arm/mach-omap2/clock3517.c
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -25,7 +25,7 @@
 
 #include "clock.h"
 #include "clock3517.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /*
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index a447c4d2c28a..e9f66b6dec18 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -25,9 +25,9 @@
 
 #include "clock.h"
 #include "clock3xxx.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /*
@@ -94,7 +94,7 @@ static int __init omap3xxx_clk_arch_init(void)
 
         ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
         if (!ret)
-                omap2_clk_print_new_rates("osc_sys_ck", "arm_fck", "core_ck");
+                omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
 
         return ret;
 }
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index d85ecd5aebfd..d3ab1c9e50b0 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -28,9 +28,9 @@
 #include "clock36xx.h"
 #include "clock3517.h"
 
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
 #include "control.h"
 
@@ -120,7 +120,7 @@ static const struct clksel_rate osc_sys_13m_rates[] = {
 };
 
 static const struct clksel_rate osc_sys_16_8m_rates[] = {
-        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
         { .div = 0 }
 };
 
@@ -452,35 +452,35 @@ static struct clk dpll3_x2_ck = {
 static const struct clksel_rate div31_dpll3_rates[] = {
         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
-        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
-        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
+        { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
+        { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
         { .div = 0 },
 };
 
@@ -602,6 +602,8 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
+        .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
+        .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
@@ -1558,6 +1560,7 @@ static struct clk mcspi4_fck = {
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
         .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
 };
 
 static struct clk mcspi3_fck = {
@@ -1567,6 +1570,7 @@ static struct clk mcspi3_fck = {
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
         .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
 };
 
 static struct clk mcspi2_fck = {
@@ -1576,6 +1580,7 @@ static struct clk mcspi2_fck = {
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
         .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
 };
 
 static struct clk mcspi1_fck = {
@@ -1585,6 +1590,7 @@ static struct clk mcspi1_fck = {
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
         .recalc         = &followparent_recalc,
+        .clkdm_name     = "core_l4_clkdm",
 };
 
 static struct clk uart2_fck = {
@@ -3044,6 +3050,7 @@ static struct clk sr1_fck = {
         .parent         = &sys_ck,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
@@ -3054,6 +3061,7 @@ static struct clk sr2_fck = {
         .parent         = &sys_ck,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
+        .clkdm_name     = "wkup_clkdm",
         .recalc         = &followparent_recalc,
 };
 
@@ -3201,7 +3209,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
-        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
@@ -3218,8 +3226,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
-        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
-        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
+        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
+        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
         CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
@@ -3248,8 +3256,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
@@ -3257,8 +3265,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
-        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
+        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
+        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
         CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
         CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
         CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
@@ -3267,27 +3275,28 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2 | CK_3517),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2 | CK_3517),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
-        CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
-        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
-        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
+        CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
+        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
-        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2 | CK_AM35XX),
+        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("ehci-omap.0",      "usbtll_fck",   &usbtll_fck,    CK_3430ES2 | CK_AM35XX),
         CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
-        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2 | CK_AM35XX),
+        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_3XXX),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
+        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
         CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_3XXX),
-        CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_3XXX),
-        CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_3XXX),
-        CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_3XXX),
+        CLK("omap_i2c.3", "fck",        &i2c3_fck,      CK_3XXX),
+        CLK("omap_i2c.2", "fck",        &i2c2_fck,      CK_3XXX),
+        CLK("omap_i2c.1", "fck",        &i2c1_fck,      CK_3XXX),
         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_3XXX),
         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_3XXX),
         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
@@ -3301,34 +3310,35 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_3XXX),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
-        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
+        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
+        CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
-        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2 | CK_AM35XX),
-        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
-        CLK("omap-aes", "ick",  &aes2_ick,      CK_343X),
-        CLK("omap-sham",        "ick",  &sha12_ick,     CK_343X),
-        CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
+        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("ehci-omap.0",      "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
+        CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
+        CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
         CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_3XXX),
         CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_3XXX),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
+        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
-        CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_3XXX),
-        CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_3XXX),
-        CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_3XXX),
+        CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
@@ -3336,37 +3346,40 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
-        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
-        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
-        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
-        CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
+        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
+        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
+        CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
+        CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
         CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
-        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
+        CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_3XXX),
         CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_3XXX),
         CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_3XXX),
         CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
-        CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
-        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
-        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2 | CK_AM35XX),
-        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
+        CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
+        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
+        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("ehci-omap.0",      "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("ehci-omap.0",      "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("ehci-omap.0",      "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
         CLK("omap_wdt", "fck",          &wdt2_fck,      CK_3XXX),
-        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
-        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
+        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
+        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
@@ -3424,9 +3437,9 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
-        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
-        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
-        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
+        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
+        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
@@ -3437,8 +3450,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("davinci_emac",     "phy_clk",      &emac_fck,      CK_AM35XX),
         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
-        CLK("musb_hdrc",        "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
-        CLK("musb_hdrc",        "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
+        CLK("musb-am35x",       "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
+        CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
 };
@@ -3447,38 +3460,37 @@ static struct omap_clk omap3xxx_clks[] = {
 int __init omap3xxx_clk_init(void)
 {
         struct omap_clk *c;
-        u32 cpu_clkflg = CK_3XXX;
+        u32 cpu_clkflg = 0;
 
         if (cpu_is_omap3517()) {
-                cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
-                cpu_clkflg |= CK_3517;
+                cpu_mask = RATE_IN_34XX;
+                cpu_clkflg = CK_3517;
         } else if (cpu_is_omap3505()) {
-                cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
-                cpu_clkflg |= CK_3505;
+                cpu_mask = RATE_IN_34XX;
+                cpu_clkflg = CK_3505;
+        } else if (cpu_is_omap3630()) {
+                cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
+                cpu_clkflg = CK_36XX;
         } else if (cpu_is_omap34xx()) {
-                cpu_mask = RATE_IN_3XXX;
-                cpu_clkflg |= CK_343X;
-
-                /*
-                 * Update this if there are further clock changes between ES2
-                 * and production parts
-                 */
                 if (omap_rev() == OMAP3430_REV_ES1_0) {
-                        /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
-                        cpu_clkflg |= CK_3430ES1;
+                        cpu_mask = RATE_IN_3430ES1;
+                        cpu_clkflg = CK_3430ES1;
                 } else {
-                        cpu_mask |= RATE_IN_3430ES2PLUS;
-                        cpu_clkflg |= CK_3430ES2;
+                        /*
+                         * Assume that anything that we haven't matched yet
+                         * has 3430ES2-type clocks.
+                         */
+                        cpu_mask = RATE_IN_3430ES2PLUS;
+                        cpu_clkflg = CK_3430ES2PLUS;
                 }
+        } else {
+                WARN(1, "clock: could not identify OMAP3 variant\n");
         }
 
         if (omap3_has_192mhz_clk())
                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
 
         if (cpu_is_omap3630()) {
-                cpu_mask |= RATE_IN_36XX;
-                cpu_clkflg |= CK_36XX;
-
                 /*
                  * XXX This type of dynamic rewriting of the clock tree is
                  * deprecated and should be revised soon.
@@ -3525,10 +3537,9 @@ int __init omap3xxx_clk_init(void)
 
         recalculate_root_clocks();
 
-        printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
-               "%ld.%01ld/%ld/%ld MHz\n",
-               (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
-               (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
+        pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
+                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
 
         /*
          * Only enable those clocks we will need, let the drivers
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 1599836ba3d9..e8cb32fd7f13 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -30,11 +30,18 @@
 
 #include "clock.h"
 #include "clock44xx.h"
-#include "cm.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
 #include "cm-regbits-44xx.h"
-#include "prm.h"
+#include "prm44xx.h"
+#include "prm44xx.h"
 #include "prm-regbits-44xx.h"
 #include "control.h"
+#include "scrm44xx.h"
+
+/* OMAP4 modulemode control */
+#define OMAP4430_MODULEMODE_HWCTRL                      0
+#define OMAP4430_MODULEMODE_SWCTRL                      1
 
 /* Root clocks */
 
@@ -47,7 +54,9 @@ static struct clk extalt_clkin_ck = {
 static struct clk pad_clks_ck = {
         .name           = "pad_clks_ck",
         .rate           = 12000000,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .enable_bit     = OMAP4430_PAD_CLKS_GATE_SHIFT,
 };
 
 static struct clk pad_slimbus_core_clks_ck = {
@@ -65,7 +74,9 @@ static struct clk secure_32k_clk_src_ck = {
 static struct clk slimbus_clk = {
         .name           = "slimbus_clk",
         .rate           = 12000000,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_CLKSEL_ABE,
+        .enable_bit     = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
 };
 
 static struct clk sys_32k_ck = {
@@ -265,18 +276,71 @@ static struct clk dpll_abe_ck = {
         .set_rate       = &omap3_noncore_dpll_set_rate,
 };
 
+static struct clk dpll_abe_x2_ck = {
+        .name           = "dpll_abe_x2_ck",
+        .parent         = &dpll_abe_ck,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel_rate div31_1to31_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+        { .div = 2, .val = 2, .flags = RATE_IN_4430 },
+        { .div = 3, .val = 3, .flags = RATE_IN_4430 },
+        { .div = 4, .val = 4, .flags = RATE_IN_4430 },
+        { .div = 5, .val = 5, .flags = RATE_IN_4430 },
+        { .div = 6, .val = 6, .flags = RATE_IN_4430 },
+        { .div = 7, .val = 7, .flags = RATE_IN_4430 },
+        { .div = 8, .val = 8, .flags = RATE_IN_4430 },
+        { .div = 9, .val = 9, .flags = RATE_IN_4430 },
+        { .div = 10, .val = 10, .flags = RATE_IN_4430 },
+        { .div = 11, .val = 11, .flags = RATE_IN_4430 },
+        { .div = 12, .val = 12, .flags = RATE_IN_4430 },
+        { .div = 13, .val = 13, .flags = RATE_IN_4430 },
+        { .div = 14, .val = 14, .flags = RATE_IN_4430 },
+        { .div = 15, .val = 15, .flags = RATE_IN_4430 },
+        { .div = 16, .val = 16, .flags = RATE_IN_4430 },
+        { .div = 17, .val = 17, .flags = RATE_IN_4430 },
+        { .div = 18, .val = 18, .flags = RATE_IN_4430 },
+        { .div = 19, .val = 19, .flags = RATE_IN_4430 },
+        { .div = 20, .val = 20, .flags = RATE_IN_4430 },
+        { .div = 21, .val = 21, .flags = RATE_IN_4430 },
+        { .div = 22, .val = 22, .flags = RATE_IN_4430 },
+        { .div = 23, .val = 23, .flags = RATE_IN_4430 },
+        { .div = 24, .val = 24, .flags = RATE_IN_4430 },
+        { .div = 25, .val = 25, .flags = RATE_IN_4430 },
+        { .div = 26, .val = 26, .flags = RATE_IN_4430 },
+        { .div = 27, .val = 27, .flags = RATE_IN_4430 },
+        { .div = 28, .val = 28, .flags = RATE_IN_4430 },
+        { .div = 29, .val = 29, .flags = RATE_IN_4430 },
+        { .div = 30, .val = 30, .flags = RATE_IN_4430 },
+        { .div = 31, .val = 31, .flags = RATE_IN_4430 },
+        { .div = 0 },
+};
+
+static const struct clksel dpll_abe_m2x2_div[] = {
+        { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
 static struct clk dpll_abe_m2x2_ck = {
         .name           = "dpll_abe_m2x2_ck",
-        .parent         = &dpll_abe_ck,
+        .parent         = &dpll_abe_x2_ck,
+        .clksel         = dpll_abe_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
 };
 
 static struct clk abe_24m_fclk = {
         .name           = "abe_24m_fclk",
         .parent         = &dpll_abe_m2x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 8,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel_rate div3_1to4_rates[] = {
@@ -326,50 +390,10 @@ static struct clk aess_fclk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static const struct clksel_rate div31_1to31_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 2, .flags = RATE_IN_4430 },
-        { .div = 3, .val = 3, .flags = RATE_IN_4430 },
-        { .div = 4, .val = 4, .flags = RATE_IN_4430 },
-        { .div = 5, .val = 5, .flags = RATE_IN_4430 },
-        { .div = 6, .val = 6, .flags = RATE_IN_4430 },
-        { .div = 7, .val = 7, .flags = RATE_IN_4430 },
-        { .div = 8, .val = 8, .flags = RATE_IN_4430 },
-        { .div = 9, .val = 9, .flags = RATE_IN_4430 },
-        { .div = 10, .val = 10, .flags = RATE_IN_4430 },
-        { .div = 11, .val = 11, .flags = RATE_IN_4430 },
-        { .div = 12, .val = 12, .flags = RATE_IN_4430 },
-        { .div = 13, .val = 13, .flags = RATE_IN_4430 },
-        { .div = 14, .val = 14, .flags = RATE_IN_4430 },
-        { .div = 15, .val = 15, .flags = RATE_IN_4430 },
-        { .div = 16, .val = 16, .flags = RATE_IN_4430 },
-        { .div = 17, .val = 17, .flags = RATE_IN_4430 },
-        { .div = 18, .val = 18, .flags = RATE_IN_4430 },
-        { .div = 19, .val = 19, .flags = RATE_IN_4430 },
-        { .div = 20, .val = 20, .flags = RATE_IN_4430 },
-        { .div = 21, .val = 21, .flags = RATE_IN_4430 },
-        { .div = 22, .val = 22, .flags = RATE_IN_4430 },
-        { .div = 23, .val = 23, .flags = RATE_IN_4430 },
-        { .div = 24, .val = 24, .flags = RATE_IN_4430 },
-        { .div = 25, .val = 25, .flags = RATE_IN_4430 },
-        { .div = 26, .val = 26, .flags = RATE_IN_4430 },
-        { .div = 27, .val = 27, .flags = RATE_IN_4430 },
-        { .div = 28, .val = 28, .flags = RATE_IN_4430 },
-        { .div = 29, .val = 29, .flags = RATE_IN_4430 },
-        { .div = 30, .val = 30, .flags = RATE_IN_4430 },
-        { .div = 31, .val = 31, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
-static const struct clksel dpll_abe_m3_div[] = {
-        { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-
-static struct clk dpll_abe_m3_ck = {
-        .name           = "dpll_abe_m3_ck",
-        .parent         = &dpll_abe_ck,
-        .clksel         = dpll_abe_m3_div,
+static struct clk dpll_abe_m3x2_ck = {
+        .name           = "dpll_abe_m3x2_ck",
+        .parent         = &dpll_abe_x2_ck,
+        .clksel         = dpll_abe_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
         .ops            = &clkops_null,
@@ -380,7 +404,7 @@ static struct clk dpll_abe_m3_ck = {
 
 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
@@ -424,15 +448,22 @@ static struct clk dpll_core_ck = {
         .recalc         = &omap3_dpll_recalc,
 };
 
-static const struct clksel dpll_core_m6_div[] = {
-        { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+static struct clk dpll_core_x2_ck = {
+        .name           = "dpll_core_x2_ck",
+        .parent         = &dpll_core_ck,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_core_m6x2_div[] = {
+        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
         { .parent = NULL },
 };
 
-static struct clk dpll_core_m6_ck = {
-        .name           = "dpll_core_m6_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+static struct clk dpll_core_m6x2_ck = {
+        .name           = "dpll_core_m6x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
         .ops            = &clkops_null,
@@ -443,7 +474,7 @@ static struct clk dpll_core_m6_ck = {
 
 static const struct clksel dbgclk_mux_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
@@ -454,10 +485,15 @@ static struct clk dbgclk_mux_ck = {
         .recalc         = &followparent_recalc,
 };
 
+static const struct clksel dpll_core_m2_div[] = {
+        { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
 static struct clk dpll_core_m2_ck = {
         .name           = "dpll_core_m2_ck",
         .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+        .clksel         = dpll_core_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
         .ops            = &clkops_null,
@@ -470,13 +506,14 @@ static struct clk ddrphy_ck = {
         .name           = "ddrphy_ck",
         .parent         = &dpll_core_m2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
-static struct clk dpll_core_m5_ck = {
-        .name           = "dpll_core_m5_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+static struct clk dpll_core_m5x2_ck = {
+        .name           = "dpll_core_m5x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
         .ops            = &clkops_null,
@@ -486,13 +523,13 @@ static struct clk dpll_core_m5_ck = {
 };
 
 static const struct clksel div_core_div[] = {
-        { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
+        { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
         { .parent = NULL },
 };
 
 static struct clk div_core_ck = {
         .name           = "div_core_ck",
-        .parent         = &dpll_core_m5_ck,
+        .parent         = &dpll_core_m5x2_ck,
         .clksel         = div_core_div,
         .clksel_reg     = OMAP4430_CM_CLKSEL_CORE,
         .clksel_mask    = OMAP4430_CLKSEL_CORE_MASK,
@@ -511,13 +548,13 @@ static const struct clksel_rate div4_1to8_rates[] = {
 };
 
 static const struct clksel div_iva_hs_clk_div[] = {
-        { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
+        { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
         { .parent = NULL },
 };
 
 static struct clk div_iva_hs_clk = {
         .name           = "div_iva_hs_clk",
-        .parent         = &dpll_core_m5_ck,
+        .parent         = &dpll_core_m5x2_ck,
         .clksel         = div_iva_hs_clk_div,
         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_IVA,
         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
@@ -529,7 +566,7 @@ static struct clk div_iva_hs_clk = {
 
 static struct clk div_mpu_hs_clk = {
         .name           = "div_mpu_hs_clk",
-        .parent         = &dpll_core_m5_ck,
+        .parent         = &dpll_core_m5x2_ck,
         .clksel         = div_iva_hs_clk_div,
         .clksel_reg     = OMAP4430_CM_BYPCLK_DPLL_MPU,
         .clksel_mask    = OMAP4430_CLKSEL_0_1_MASK,
@@ -539,10 +576,10 @@ static struct clk div_mpu_hs_clk = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_core_m4_ck = {
-        .name           = "dpll_core_m4_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+static struct clk dpll_core_m4x2_ck = {
+        .name           = "dpll_core_m4x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
         .ops            = &clkops_null,
@@ -553,15 +590,21 @@ static struct clk dpll_core_m4_ck = {
 
 static struct clk dll_clk_div_ck = {
         .name           = "dll_clk_div_ck",
-        .parent         = &dpll_core_m4_ck,
+        .parent         = &dpll_core_m4x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
+static const struct clksel dpll_abe_m2_div[] = {
+        { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
 };
 
 static struct clk dpll_abe_m2_ck = {
         .name           = "dpll_abe_m2_ck",
         .parent         = &dpll_abe_ck,
-        .clksel         = dpll_abe_m3_div,
+        .clksel         = dpll_abe_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
         .ops            = &clkops_null,
@@ -570,22 +613,24 @@ static struct clk dpll_abe_m2_ck = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_core_m3_ck = {
-        .name           = "dpll_core_m3_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+static struct clk dpll_core_m3x2_ck = {
+        .name           = "dpll_core_m3x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_CORE,
+        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_core_m7_ck = {
-        .name           = "dpll_core_m7_ck",
-        .parent         = &dpll_core_ck,
-        .clksel         = dpll_core_m6_div,
+static struct clk dpll_core_m7x2_ck = {
+        .name           = "dpll_core_m7x2_ck",
+        .parent         = &dpll_core_x2_ck,
+        .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
         .ops            = &clkops_null,
@@ -603,8 +648,12 @@ static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
 static struct clk iva_hsd_byp_clk_mux_ck = {
         .name           = "iva_hsd_byp_clk_mux_ck",
         .parent         = &sys_clkin_ck,
+        .clksel         = iva_hsd_byp_clk_mux_sel,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = OMAP4430_CM_CLKSEL_DPLL_IVA,
+        .clksel_mask    = OMAP4430_DPLL_BYP_CLKSEL_MASK,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 /* DPLL_IVA */
@@ -638,15 +687,22 @@ static struct clk dpll_iva_ck = {
         .set_rate       = &omap3_noncore_dpll_set_rate,
 };
 
-static const struct clksel dpll_iva_m4_div[] = {
-        { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
+static struct clk dpll_iva_x2_ck = {
+        .name           = "dpll_iva_x2_ck",
+        .parent         = &dpll_iva_ck,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_iva_m4x2_div[] = {
+        { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
         { .parent = NULL },
 };
 
-static struct clk dpll_iva_m4_ck = {
-        .name           = "dpll_iva_m4_ck",
-        .parent         = &dpll_iva_ck,
-        .clksel         = dpll_iva_m4_div,
+static struct clk dpll_iva_m4x2_ck = {
+        .name           = "dpll_iva_m4x2_ck",
+        .parent         = &dpll_iva_x2_ck,
+        .clksel         = dpll_iva_m4x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
         .ops            = &clkops_null,
@@ -655,10 +711,10 @@ static struct clk dpll_iva_m4_ck = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_iva_m5_ck = {
-        .name           = "dpll_iva_m5_ck",
-        .parent         = &dpll_iva_ck,
-        .clksel         = dpll_iva_m4_div,
+static struct clk dpll_iva_m5x2_ck = {
+        .name           = "dpll_iva_m5x2_ck",
+        .parent         = &dpll_iva_x2_ck,
+        .clksel         = dpll_iva_m4x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
         .ops            = &clkops_null,
@@ -717,9 +773,10 @@ static struct clk dpll_mpu_m2_ck = {
 
 static struct clk per_hs_clk_div_ck = {
         .name           = "per_hs_clk_div_ck",
-        .parent         = &dpll_abe_m3_ck,
+        .parent         = &dpll_abe_m3x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
@@ -787,29 +844,48 @@ static struct clk dpll_per_m2_ck = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
+static struct clk dpll_per_x2_ck = {
+        .name           = "dpll_per_x2_ck",
+        .parent         = &dpll_per_ck,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+static const struct clksel dpll_per_m2x2_div[] = {
+        { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
 static struct clk dpll_per_m2x2_ck = {
         .name           = "dpll_per_m2x2_ck",
-        .parent         = &dpll_per_ck,
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
+        .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_per_m3_ck = {
-        .name           = "dpll_per_m3_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
+static struct clk dpll_per_m3x2_ck = {
+        .name           = "dpll_per_m3x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_DIV_M3_DPLL_PER,
+        .enable_bit     = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_per_m4_ck = {
-        .name           = "dpll_per_m4_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
+static struct clk dpll_per_m4x2_ck = {
+        .name           = "dpll_per_m4x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
         .ops            = &clkops_null,
@@ -818,10 +894,10 @@ static struct clk dpll_per_m4_ck = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_per_m5_ck = {
-        .name           = "dpll_per_m5_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
+static struct clk dpll_per_m5x2_ck = {
+        .name           = "dpll_per_m5x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
         .ops            = &clkops_null,
@@ -830,10 +906,10 @@ static struct clk dpll_per_m5_ck = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_per_m6_ck = {
-        .name           = "dpll_per_m6_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
+static struct clk dpll_per_m6x2_ck = {
+        .name           = "dpll_per_m6x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
         .ops            = &clkops_null,
@@ -842,10 +918,10 @@ static struct clk dpll_per_m6_ck = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
-static struct clk dpll_per_m7_ck = {
-        .name           = "dpll_per_m7_ck",
-        .parent         = &dpll_per_ck,
-        .clksel         = dpll_per_m2_div,
+static struct clk dpll_per_m7x2_ck = {
+        .name           = "dpll_per_m7x2_ck",
+        .parent         = &dpll_per_x2_ck,
+        .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
         .ops            = &clkops_null,
@@ -868,6 +944,7 @@ static struct dpll_data dpll_unipro_dd = {
         .enable_mask    = OMAP4430_DPLL_EN_MASK,
         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
+        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
         .max_multiplier = OMAP4430_MAX_DPLL_MULT,
         .max_divider    = OMAP4430_MAX_DPLL_DIV,
         .min_divider    = 1,
@@ -885,14 +962,21 @@ static struct clk dpll_unipro_ck = {
         .set_rate       = &omap3_noncore_dpll_set_rate,
 };
 
+static struct clk dpll_unipro_x2_ck = {
+        .name           = "dpll_unipro_x2_ck",
+        .parent         = &dpll_unipro_ck,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
 static const struct clksel dpll_unipro_m2x2_div[] = {
-        { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
+        { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
         { .parent = NULL },
 };
 
 static struct clk dpll_unipro_m2x2_ck = {
         .name           = "dpll_unipro_m2x2_ck",
-        .parent         = &dpll_unipro_ck,
+        .parent         = &dpll_unipro_x2_ck,
         .clksel         = dpll_unipro_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
@@ -904,16 +988,17 @@ static struct clk dpll_unipro_m2x2_ck = {
 
 static struct clk usb_hs_clk_div_ck = {
         .name           = "usb_hs_clk_div_ck",
-        .parent         = &dpll_abe_m3_ck,
+        .parent         = &dpll_abe_m3x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 3,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 /* DPLL_USB */
 static struct dpll_data dpll_usb_dd = {
         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
         .clk_bypass     = &usb_hs_clk_div_ck,
-        .flags          = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
+        .flags          = DPLL_J_TYPE,
         .clk_ref        = &sys_clkin_ck,
         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -967,7 +1052,7 @@ static struct clk dpll_usb_m2_ck = {
 
 static const struct clksel ducati_clk_mux_sel[] = {
         { .parent = &div_core_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
@@ -986,21 +1071,24 @@ static struct clk func_12m_fclk = {
         .name           = "func_12m_fclk",
         .parent         = &dpll_per_m2x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 16,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static struct clk func_24m_clk = {
         .name           = "func_24m_clk",
         .parent         = &dpll_per_m2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static struct clk func_24mc_fclk = {
         .name           = "func_24mc_fclk",
         .parent         = &dpll_per_m2x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 8,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel_rate div2_4to8_rates[] = {
@@ -1030,7 +1118,8 @@ static struct clk func_48mc_fclk = {
         .name           = "func_48mc_fclk",
         .parent         = &dpll_per_m2x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel_rate div2_2to4_rates[] = {
@@ -1040,13 +1129,13 @@ static const struct clksel_rate div2_2to4_rates[] = {
 };
 
 static const struct clksel func_64m_fclk_div[] = {
-        { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
+        { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
         { .parent = NULL },
 };
 
 static struct clk func_64m_fclk = {
         .name           = "func_64m_fclk",
-        .parent         = &dpll_per_m4_ck,
+        .parent         = &dpll_per_m4x2_ck,
         .clksel         = func_64m_fclk_div,
         .clksel_reg     = OMAP4430_CM_SCALE_FCLK,
         .clksel_mask    = OMAP4430_SCALE_FCLK_MASK,
@@ -1147,7 +1236,8 @@ static struct clk lp_clk_div_ck = {
         .name           = "lp_clk_div_ck",
         .parent         = &dpll_abe_m2x2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 16,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel l4_wkup_clk_mux_sel[] = {
@@ -1215,12 +1305,13 @@ static struct clk per_abe_24m_fclk = {
         .name           = "per_abe_24m_fclk",
         .parent         = &dpll_abe_m2_ck,
         .ops            = &clkops_null,
-        .recalc         = &followparent_recalc,
+        .fixed_div      = 4,
+        .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static const struct clksel pmd_stm_clock_mux_sel[] = {
         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
         { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
         { .parent = NULL },
 };
@@ -1354,7 +1445,7 @@ static struct clk dsp_fck = {
         .enable_reg     = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "tesla_clkdm",
-        .parent         = &dpll_iva_m4_ck,
+        .parent         = &dpll_iva_m4x2_ck,
         .recalc         = &followparent_recalc,
 };
 
@@ -1384,7 +1475,7 @@ static struct clk dss_dss_clk = {
         .enable_reg     = OMAP4430_CM_DSS_DSS_CLKCTRL,
         .enable_bit     = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
         .clkdm_name     = "l3_dss_clkdm",
-        .parent         = &dpll_per_m5_ck,
+        .parent         = &dpll_per_m5x2_ck,
         .recalc         = &followparent_recalc,
 };
 
@@ -1441,14 +1532,14 @@ static struct clk emif2_fck = {
 };
 
 static const struct clksel fdif_fclk_div[] = {
-        { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
+        { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
         { .parent = NULL },
 };
 
 /* Merged fdif_fclk into fdif */
 static struct clk fdif_fck = {
         .name           = "fdif_fck",
-        .parent         = &dpll_per_m4_ck,
+        .parent         = &dpll_per_m4x2_ck,
         .clksel         = fdif_fclk_div,
         .clksel_reg     = OMAP4430_CM_CAM_FDIF_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_FCLK_MASK,
@@ -1602,15 +1693,15 @@ static struct clk gpmc_ick = {
 };
 
 static const struct clksel sgx_clk_mux_sel[] = {
-        { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
         { .parent = NULL },
 };
 
 /* Merged sgx_clk_mux into gpu */
 static struct clk gpu_fck = {
         .name           = "gpu_fck",
-        .parent         = &dpll_core_m7_ck,
+        .parent         = &dpll_core_m7x2_ck,
         .clksel         = sgx_clk_mux_sel,
         .init           = &omap2_init_clksel_parent,
         .clksel_reg     = OMAP4430_CM_GFX_GFX_CLKCTRL,
@@ -1729,7 +1820,7 @@ static struct clk iva_fck = {
         .enable_reg     = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "ivahd_clkdm",
-        .parent         = &dpll_iva_m5_ck,
+        .parent         = &dpll_iva_m5x2_ck,
         .recalc         = &followparent_recalc,
 };
 
@@ -1749,6 +1840,7 @@ static struct clk l3_instr_ick = {
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "l3_instr_clkdm",
+        .flags          = ENABLE_ON_INIT,
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
@@ -1759,6 +1851,7 @@ static struct clk l3_main_3_ick = {
         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "l3_instr_clkdm",
+        .flags          = ENABLE_ON_INIT,
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
@@ -2063,6 +2156,7 @@ static struct clk ocp_wp_noc_ick = {
         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "l3_instr_clkdm",
+        .flags          = ENABLE_ON_INIT,
         .parent         = &l3_div_ck,
         .recalc         = &followparent_recalc,
 };
@@ -2093,7 +2187,7 @@ static struct clk sl2if_ick = {
         .enable_reg     = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL,
         .clkdm_name     = "ivahd_clkdm",
-        .parent         = &dpll_iva_m5_ck,
+        .parent         = &dpll_iva_m5x2_ck,
         .recalc         = &followparent_recalc,
 };
 
@@ -2438,36 +2532,6 @@ static struct clk usb_host_fs_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk usb_host_hs_utmi_p3_clk = {
-        .name           = "usb_host_hs_utmi_p3_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &init_60m_fclk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usb_host_hs_hsic60m_p1_clk = {
-        .name           = "usb_host_hs_hsic60m_p1_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &init_60m_fclk,
-        .recalc         = &followparent_recalc,
-};
-
-static struct clk usb_host_hs_hsic60m_p2_clk = {
-        .name           = "usb_host_hs_hsic60m_p2_clk",
-        .ops            = &clkops_omap2_dflt,
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-        .parent         = &init_60m_fclk,
-        .recalc         = &followparent_recalc,
-};
-
 static const struct clksel utmi_p1_gfclk_sel[] = {
         { .parent = &init_60m_fclk, .rates = div_1_0_rates },
         { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
@@ -2522,6 +2586,16 @@ static struct clk usb_host_hs_utmi_p2_clk = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk usb_host_hs_utmi_p3_clk = {
+        .name           = "usb_host_hs_utmi_p3_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk usb_host_hs_hsic480m_p1_clk = {
         .name           = "usb_host_hs_hsic480m_p1_clk",
         .ops            = &clkops_omap2_dflt,
@@ -2532,6 +2606,26 @@ static struct clk usb_host_hs_hsic480m_p1_clk = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk usb_host_hs_hsic60m_p1_clk = {
+        .name           = "usb_host_hs_hsic60m_p1_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk usb_host_hs_hsic60m_p2_clk = {
+        .name           = "usb_host_hs_hsic60m_p2_clk",
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
+        .enable_bit     = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
+        .clkdm_name     = "l3_init_clkdm",
+        .parent         = &init_60m_fclk,
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk usb_host_hs_hsic480m_p2_clk = {
         .name           = "usb_host_hs_hsic480m_p2_clk",
         .ops            = &clkops_omap2_dflt,
@@ -2656,13 +2750,13 @@ static const struct clksel_rate div2_14to18_rates[] = {
 };
 
 static const struct clksel usim_fclk_div[] = {
-        { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
+        { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
         { .parent = NULL },
 };
 
 static struct clk usim_ck = {
         .name           = "usim_ck",
-        .parent         = &dpll_per_m4_ck,
+        .parent         = &dpll_per_m4x2_ck,
         .clksel         = usim_fclk_div,
         .clksel_reg     = OMAP4430_CM_WKUP_USIM_CLKCTRL,
         .clksel_mask    = OMAP4430_CLKSEL_DIV_MASK,
@@ -2747,6 +2841,168 @@ static struct clk trace_clk_div_ck = {
         .set_rate       = &omap2_clksel_set_rate,
 };
 
+/* SCRM aux clk nodes */
+
+static const struct clksel auxclk_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclk0_ck = {
+        .name           = "auxclk0_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK0,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK0,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk1_ck = {
+        .name           = "auxclk1_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK1,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK1,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk2_ck = {
+        .name           = "auxclk2_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK2,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK2,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+static struct clk auxclk3_ck = {
+        .name           = "auxclk3_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK3,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK3,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk4_ck = {
+        .name           = "auxclk4_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK4,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK4,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+
+static struct clk auxclk5_ck = {
+        .name           = "auxclk5_ck",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = auxclk_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLK5,
+        .clksel_mask    = OMAP4_SRCSELECT_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .enable_reg     = OMAP4_SCRM_AUXCLK5,
+        .enable_bit     = OMAP4_ENABLE_SHIFT,
+};
+
+static const struct clksel auxclkreq_sel[] = {
+        { .parent = &auxclk0_ck, .rates = div_1_0_rates },
+        { .parent = &auxclk1_ck, .rates = div_1_1_rates },
+        { .parent = &auxclk2_ck, .rates = div_1_2_rates },
+        { .parent = &auxclk3_ck, .rates = div_1_3_rates },
+        { .parent = &auxclk4_ck, .rates = div_1_4_rates },
+        { .parent = &auxclk5_ck, .rates = div_1_5_rates },
+        { .parent = NULL },
+};
+
+static struct clk auxclkreq0_ck = {
+        .name           = "auxclkreq0_ck",
+        .parent         = &auxclk0_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ0,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq1_ck = {
+        .name           = "auxclkreq1_ck",
+        .parent         = &auxclk1_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ1,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq2_ck = {
+        .name           = "auxclkreq2_ck",
+        .parent         = &auxclk2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ2,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq3_ck = {
+        .name           = "auxclkreq3_ck",
+        .parent         = &auxclk3_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ3,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq4_ck = {
+        .name           = "auxclkreq4_ck",
+        .parent         = &auxclk4_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ4,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk auxclkreq5_ck = {
+        .name           = "auxclkreq5_ck",
+        .parent         = &auxclk5_ck,
+        .init           = &omap2_init_clksel_parent,
+        .ops            = &clkops_null,
+        .clksel         = auxclkreq_sel,
+        .clksel_reg     = OMAP4_SCRM_AUXCLKREQ5,
+        .clksel_mask    = OMAP4_MAPPING_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
 /*
  * clkdev
  */
@@ -2774,43 +3030,48 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
+        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
-        CLK(NULL,       "dpll_abe_m3_ck",               &dpll_abe_m3_ck,        CK_443X),
+        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
-        CLK(NULL,       "dpll_core_m6_ck",              &dpll_core_m6_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
-        CLK(NULL,       "dpll_core_m5_ck",              &dpll_core_m5_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
-        CLK(NULL,       "dpll_core_m4_ck",              &dpll_core_m4_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
-        CLK(NULL,       "dpll_core_m3_ck",              &dpll_core_m3_ck,       CK_443X),
-        CLK(NULL,       "dpll_core_m7_ck",              &dpll_core_m7_ck,       CK_443X),
+        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
+        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
-        CLK(NULL,       "dpll_iva_m4_ck",               &dpll_iva_m4_ck,        CK_443X),
-        CLK(NULL,       "dpll_iva_m5_ck",               &dpll_iva_m5_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
+        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m3_ck",               &dpll_per_m3_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m4_ck",               &dpll_per_m4_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m5_ck",               &dpll_per_m5_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m6_ck",               &dpll_per_m6_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m7_ck",               &dpll_per_m7_ck,        CK_443X),
+        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
+        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
         CLK(NULL,       "dpll_unipro_ck",               &dpll_unipro_ck,        CK_443X),
+        CLK(NULL,       "dpll_unipro_x2_ck",            &dpll_unipro_x2_ck,     CK_443X),
         CLK(NULL,       "dpll_unipro_m2x2_ck",          &dpll_unipro_m2x2_ck,   CK_443X),
         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
@@ -2856,26 +3117,26 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
-        CLK(NULL,       "gpio1_dbck",                   &gpio1_dbclk,   CK_443X),
+        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
-        CLK(NULL,       "gpio2_dbck",                   &gpio2_dbclk,   CK_443X),
+        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
-        CLK(NULL,       "gpio3_dbck",                   &gpio3_dbclk,   CK_443X),
+        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
-        CLK(NULL,       "gpio4_dbck",                   &gpio4_dbclk,   CK_443X),
+        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
-        CLK(NULL,       "gpio5_dbck",                   &gpio5_dbclk,   CK_443X),
+        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
-        CLK(NULL,       "gpio6_dbck",                   &gpio6_dbclk,   CK_443X),
+        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
         CLK("omap2_hdq.0",      "fck",                          &hdq1w_fck,     CK_443X),
         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
-        CLK("i2c_omap.1",       "fck",                          &i2c1_fck,      CK_443X),
-        CLK("i2c_omap.2",       "fck",                          &i2c2_fck,      CK_443X),
-        CLK("i2c_omap.3",       "fck",                          &i2c3_fck,      CK_443X),
-        CLK("i2c_omap.4",       "fck",                          &i2c4_fck,      CK_443X),
+        CLK("omap_i2c.1",       "fck",                          &i2c1_fck,      CK_443X),
+        CLK("omap_i2c.2",       "fck",                          &i2c2_fck,      CK_443X),
+        CLK("omap_i2c.3",       "fck",                          &i2c3_fck,      CK_443X),
+        CLK("omap_i2c.4",       "fck",                          &i2c4_fck,      CK_443X),
         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
@@ -2937,29 +3198,35 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
-        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
+        CLK("ehci-omap.0",      "fs_fck",               &usb_host_fs_fck,       CK_443X),
         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
+        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
+        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
         CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
+        CLK("ehci-omap.0",      "hs_fck",               &usb_host_hs_fck,       CK_443X),
+        CLK("ehci-omap.0",      "usbhost_ick",          &dummy_ck,              CK_443X),
         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
-        CLK("musb_hdrc",        "ick",                          &usb_otg_hs_ick,        CK_443X),
+        CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
+        CLK("ehci-omap.0",      "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK("ehci-omap.0",      "usbtll_fck",           &dummy_ck,      CK_443X),
         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
         CLK("omap_wdt", "fck",                          &wd_timer2_fck, CK_443X),
+        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
@@ -2975,10 +3242,10 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
-        CLK("i2c_omap.1",       "ick",                          &dummy_ck,      CK_443X),
-        CLK("i2c_omap.2",       "ick",                          &dummy_ck,      CK_443X),
-        CLK("i2c_omap.3",       "ick",                          &dummy_ck,      CK_443X),
-        CLK("i2c_omap.4",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
         CLK("mmci-omap-hs.0",   "ick",                          &dummy_ck,      CK_443X),
         CLK("mmci-omap-hs.1",   "ick",                          &dummy_ck,      CK_443X),
         CLK("mmci-omap-hs.2",   "ick",                          &dummy_ck,      CK_443X),
@@ -2997,6 +3264,18 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
+        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
+        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
+        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
+        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
+        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
+        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
+        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
+        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
+        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
+        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
+        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
+        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
 };
 
 int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 6fb61b1a0d46..e20b98636ab4 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -13,7 +13,6 @@
  */
 #undef DEBUG
 
-#include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/device.h>
 #include <linux/list.h>
@@ -27,13 +26,16 @@
 
 #include <linux/bitops.h>
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "cminst44xx.h"
+#include "prcm44xx.h"
 
 #include <plat/clock.h>
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
 #include <plat/prcm.h>
 
 /* clkdm_list contains all registered struct clockdomains */
@@ -141,6 +143,9 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
  * clockdomain is in hardware-supervised mode.  Meant to be called
  * once at clockdomain layer initialization, since these should remain
  * fixed for a particular architecture.  No return value.
+ *
+ * XXX autodeps are deprecated and should be removed at the earliest
+ * opportunity
  */
 static void _autodep_lookup(struct clkdm_autodep *autodep)
 {
@@ -168,6 +173,9 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
  * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
  * in hardware-supervised mode.  Meant to be called from clock framework
  * when a clock inside clockdomain 'clkdm' is enabled.  No return value.
+ *
+ * XXX autodeps are deprecated and should be removed at the earliest
+ * opportunity
  */
 static void _clkdm_add_autodeps(struct clockdomain *clkdm)
 {
@@ -199,6 +207,9 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm)
  * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
  * in hardware-supervised mode.  Meant to be called from clock framework
  * when a clock inside clockdomain 'clkdm' is disabled.  No return value.
+ *
+ * XXX autodeps are deprecated and should be removed at the earliest
+ * opportunity
  */
 static void _clkdm_del_autodeps(struct clockdomain *clkdm)
 {
@@ -223,39 +234,56 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
         }
 }
 
-/*
- * _omap2_clkdm_set_hwsup - set the hwsup idle transition bit
+/**
+ * _enable_hwsup - place a clockdomain into hardware-supervised idle
  * @clkdm: struct clockdomain *
- * @enable: int 0 to disable, 1 to enable
  *
- * Internal helper for actually switching the bit that controls hwsup
- * idle transitions for clkdm.
+ * Place the clockdomain into hardware-supervised idle mode.  No return
+ * value.
+ *
+ * XXX Should this return an error if the clockdomain does not support
+ * hardware-supervised idle mode?
  */
-static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
+static void _enable_hwsup(struct clockdomain *clkdm)
 {
-        u32 bits, v;
-
-        if (cpu_is_omap24xx()) {
-                if (enable)
-                        bits = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
-                else
-                        bits = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
-        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                if (enable)
-                        bits = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
-                else
-                        bits = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
-        } else {
+        if (cpu_is_omap24xx())
+                omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        else if (cpu_is_omap34xx())
+                omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
+        else if (cpu_is_omap44xx())
+                return omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
+                                                       clkdm->cm_inst,
+                                                       clkdm->clkdm_offs);
+        else
                 BUG();
-        }
-
-        bits = bits << __ffs(clkdm->clktrctrl_mask);
-
-        v = __raw_readl(clkdm->clkstctrl_reg);
-        v &= ~(clkdm->clktrctrl_mask);
-        v |= bits;
-        __raw_writel(v, clkdm->clkstctrl_reg);
+}
 
+/**
+ * _disable_hwsup - place a clockdomain into software-supervised idle
+ * @clkdm: struct clockdomain *
+ *
+ * Place the clockdomain @clkdm into software-supervised idle mode.
+ * No return value.
+ *
+ * XXX Should this return an error if the clockdomain does not support
+ * software-supervised idle mode?
+ */
+static void _disable_hwsup(struct clockdomain *clkdm)
+{
+        if (cpu_is_omap24xx())
+                omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+        else if (cpu_is_omap34xx())
+                omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                clkdm->clktrctrl_mask);
+        else if (cpu_is_omap44xx())
+                return omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
+                                                        clkdm->cm_inst,
+                                                        clkdm->clkdm_offs);
+        else
+                BUG();
 }
 
 /* Public functions */
@@ -409,7 +437,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                 pr_debug("clockdomain: hardware will wake up %s when %s wakes "
                          "up\n", clkdm1->name, clkdm2->name);
 
-                prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
                                      clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
         }
 
@@ -444,7 +472,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                 pr_debug("clockdomain: hardware will no longer wake up %s "
                          "after %s wakes up\n", clkdm1->name, clkdm2->name);
 
-                prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
                                        clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
         }
 
@@ -480,7 +508,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
         }
 
         /* XXX It's faster to return the atomic wkdep_usecount */
-        return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
+        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP,
                                        (1 << clkdm2->dep_bit));
 }
 
@@ -514,7 +542,7 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
                 atomic_set(&cd->wkdep_usecount, 0);
         }
 
-        prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
+        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP);
 
         return 0;
 }
@@ -553,7 +581,7 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                 pr_debug("clockdomain: will prevent %s from sleeping if %s "
                          "is active\n", clkdm1->name, clkdm2->name);
 
-                cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
+                omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
                                     clkdm1->pwrdm.ptr->prcm_offs,
                                     OMAP3430_CM_SLEEPDEP);
         }
@@ -596,7 +624,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
                          "sleeping if %s is active\n", clkdm1->name,
                          clkdm2->name);
 
-                cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
+                omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
                                       clkdm1->pwrdm.ptr->prcm_offs,
                                       OMAP3430_CM_SLEEPDEP);
         }
@@ -639,7 +667,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
         }
 
         /* XXX It's faster to return the atomic sleepdep_usecount */
-        return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
+        return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
                                        OMAP3430_CM_SLEEPDEP,
                                        (1 << clkdm2->dep_bit));
 }
@@ -677,35 +705,13 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
                 atomic_set(&cd->sleepdep_usecount, 0);
         }
 
-        prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
+        omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
                                OMAP3430_CM_SLEEPDEP);
 
         return 0;
 }
 
 /**
- * omap2_clkdm_clktrctrl_read - read the clkdm's current state transition mode
- * @clkdm: struct clkdm * of a clockdomain
- *
- * Return the clockdomain @clkdm current state transition mode from the
- * corresponding domain CM_CLKSTCTRL register.  Returns -EINVAL if @clkdm
- * is NULL or the current mode upon success.
- */
-static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm)
-{
-        u32 v;
-
-        if (!clkdm)
-                return -EINVAL;
-
-        v = __raw_readl(clkdm->clkstctrl_reg);
-        v &= clkdm->clktrctrl_mask;
-        v >>= __ffs(clkdm->clktrctrl_mask);
-
-        return v;
-}
-
-/**
  * omap2_clkdm_sleep - force clockdomain sleep transition
  * @clkdm: struct clockdomain *
  *
@@ -729,18 +735,19 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm)
 
         if (cpu_is_omap24xx()) {
 
-                cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+                omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
                             clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
 
-        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+        } else if (cpu_is_omap34xx()) {
+
+                omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+                                              clkdm->clktrctrl_mask);
 
-                u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_SLEEP <<
-                         __ffs(clkdm->clktrctrl_mask));
+        } else if (cpu_is_omap44xx()) {
 
-                u32 v = __raw_readl(clkdm->clkstctrl_reg);
-                v &= ~(clkdm->clktrctrl_mask);
-                v |= bits;
-                __raw_writel(v, clkdm->clkstctrl_reg);
+                omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
+                                               clkdm->cm_inst,
+                                               clkdm->clkdm_offs);
 
         } else {
                 BUG();
@@ -773,18 +780,19 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
 
         if (cpu_is_omap24xx()) {
 
-                cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
+                omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
                               clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL);
 
-        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+        } else if (cpu_is_omap34xx()) {
 
-                u32 bits = (OMAP34XX_CLKSTCTRL_FORCE_WAKEUP <<
-                         __ffs(clkdm->clktrctrl_mask));
+                omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+                                               clkdm->clktrctrl_mask);
 
-                u32 v = __raw_readl(clkdm->clkstctrl_reg);
-                v &= ~(clkdm->clktrctrl_mask);
-                v |= bits;
-                __raw_writel(v, clkdm->clkstctrl_reg);
+        } else if (cpu_is_omap44xx()) {
+
+                omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,
+                                                clkdm->cm_inst,
+                                                clkdm->clkdm_offs);
 
         } else {
                 BUG();
@@ -829,7 +837,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
                         _clkdm_add_autodeps(clkdm);
         }
 
-        _omap2_clkdm_set_hwsup(clkdm, 1);
+        _enable_hwsup(clkdm);
 
         pwrdm_clkdm_state_switch(clkdm);
 }
@@ -857,7 +865,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
         pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
                  clkdm->name);
 
-        _omap2_clkdm_set_hwsup(clkdm, 0);
+        _disable_hwsup(clkdm);
 
         /*
          * XXX This should be removed once TI adds wakeup/sleep
@@ -891,7 +899,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
  */
 int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
 {
-        int v;
+        bool hwsup = false;
 
         /*
          * XXX Rewrite this code to maintain a list of enabled
@@ -909,17 +917,27 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
         pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
                  clk->name);
 
-        if (!clkdm->clkstctrl_reg)
-                return 0;
+        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
 
-        v = omap2_clkdm_clktrctrl_read(clkdm);
+                if (!clkdm->clktrctrl_mask)
+                        return 0;
 
-        if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
-            (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
+                hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                   clkdm->clktrctrl_mask);
+
+        } else if (cpu_is_omap44xx()) {
+
+                hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+                                                       clkdm->cm_inst,
+                                                       clkdm->clkdm_offs);
+
+        }
+
+        if (hwsup) {
                 /* Disable HW transitions when we are changing deps */
-                _omap2_clkdm_set_hwsup(clkdm, 0);
+                _disable_hwsup(clkdm);
                 _clkdm_add_autodeps(clkdm);
-                _omap2_clkdm_set_hwsup(clkdm, 1);
+                _enable_hwsup(clkdm);
         } else {
                 omap2_clkdm_wakeup(clkdm);
         }
@@ -946,7 +964,7 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
  */
 int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
 {
-        int v;
+        bool hwsup = false;
 
         /*
          * XXX Rewrite this code to maintain a list of enabled
@@ -971,17 +989,27 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
         pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
                  clk->name);
 
-        if (!clkdm->clkstctrl_reg)
-                return 0;
+        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
 
-        v = omap2_clkdm_clktrctrl_read(clkdm);
+                if (!clkdm->clktrctrl_mask)
+                        return 0;
+
+                hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                                   clkdm->clktrctrl_mask);
+
+        } else if (cpu_is_omap44xx()) {
+
+                hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
+                                                       clkdm->cm_inst,
+                                                       clkdm->clkdm_offs);
+
+        }
 
-        if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
-            (cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
+        if (hwsup) {
                 /* Disable HW transitions when we are changing deps */
-                _omap2_clkdm_set_hwsup(clkdm, 0);
+                _disable_hwsup(clkdm);
                 _clkdm_del_autodeps(clkdm);
-                _omap2_clkdm_set_hwsup(clkdm, 1);
+                _enable_hwsup(clkdm);
         } else {
                 omap2_clkdm_sleep(clkdm);
         }
diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index ba0a6c07c0fe..de3faa20b46b 100644
--- a/arch/arm/plat-omap/include/plat/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -4,19 +4,21 @@
  * OMAP2/3 clockdomain framework functions
  *
  * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008-2009 Nokia Corporation
+ * Copyright (C) 2008-2010 Nokia Corporation
  *
- * Written by Paul Walmsley
+ * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
-#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H
+#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
+#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
 
-#include <plat/powerdomain.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
@@ -30,16 +32,6 @@
 #define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
 #define CLKDM_CAN_HWSUP_SWSUP   (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP)
 
-/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
-#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO         0x0
-#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO          0x1
-
-/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
-#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO         0x0
-#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP          0x1
-#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP         0x2
-#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO          0x3
-
 /**
  * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode
  * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only
@@ -90,11 +82,20 @@ struct clkdm_dep {
  * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
  * @flags: Clockdomain capability flags
  * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
+ * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
+ * @cm_inst: (OMAP4 only) CM instance register offset
+ * @clkdm_offs: (OMAP4 only) CM clockdomain register offset
  * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up
  * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact
  * @omap_chip: OMAP chip types that this clockdomain is valid on
  * @usecount: Usecount tracking
  * @node: list_head to link all clockdomains together
+ *
+ * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only)
+ * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance
+ *     definitions (OMAP4 only)
+ * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance
+ *     definitions (OMAP4 only)
  */
 struct clockdomain {
         const char *name;
@@ -102,10 +103,14 @@ struct clockdomain {
                 const char *name;
                 struct powerdomain *ptr;
         } pwrdm;
-        void __iomem *clkstctrl_reg;
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
         const u16 clktrctrl_mask;
+#endif
         const u8 flags;
         const u8 dep_bit;
+        const u8 prcm_partition;
+        const s16 cm_inst;
+        const u16 clkdm_offs;
         struct clkdm_dep *wkdep_srcs;
         struct clkdm_dep *sleepdep_srcs;
         const struct omap_chip_id omap_chip;
@@ -138,4 +143,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm);
 int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
 int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
 
+extern void __init omap2_clockdomains_init(void);
+extern void __init omap44xx_clockdomains_init(void);
+
 #endif
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 8fc19ff2cd89..e4a7133ea3b3 100644
--- a/arch/arm/mach-omap2/clockdomains.h
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -4,7 +4,7 @@
  * Copyright (C) 2008-2009 Texas Instruments, Inc.
  * Copyright (C) 2008-2010 Nokia Corporation
  *
- * Written by Paul Walmsley and Jouni Högander
+ * Paul Walmsley, Jouni Högander
  *
  * This file contains clockdomains and clockdomain wakeup/sleep
  * dependencies for the OMAP2/3 chips.  Some notes:
@@ -32,12 +32,17 @@
  *    from the Power domain framework
  */
 
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
+#include <linux/kernel.h>
+#include <linux/io.h>
 
-#include <plat/clockdomain.h>
-#include "cm.h"
-#include "prm.h"
+#include "clockdomain.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
+#include "prm-regbits-24xx.h"
+#include "prm-regbits-34xx.h"
 
 /*
  * Clockdomain dependencies for wkdeps/sleepdeps
@@ -84,8 +89,6 @@ static struct clkdm_dep gfx_sgx_wkdeps[] = {
 
 /* 24XX-specific possible dependencies */
 
-#ifdef CONFIG_ARCH_OMAP2
-
 /* Wakeup dependency source arrays */
 
 /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
@@ -165,8 +168,6 @@ static struct clkdm_dep core_24xx_wkdeps[] = {
         { NULL },
 };
 
-#endif
-
 
 /* 2430-specific possible wakeup dependencies */
 
@@ -425,8 +426,6 @@ static struct clkdm_dep gfx_sgx_sleepdeps[] = {
  * sys_clkout/sys_clkout2.
  */
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-
 /* This is an implicit clockdomain - it is never defined as such in TRM */
 static struct clockdomain wkup_clkdm = {
         .name           = "wkup_clkdm",
@@ -447,8 +446,6 @@ static struct clockdomain cm_clkdm = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
 
-#endif
-
 /*
  * 2420-only clockdomains
  */
@@ -459,7 +456,6 @@ static struct clockdomain mpu_2420_clkdm = {
         .name           = "mpu_clkdm",
         .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = mpu_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -469,8 +465,6 @@ static struct clockdomain iva1_2420_clkdm = {
         .name           = "iva1_clkdm",
         .pwrdm          = { .name = "dsp_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
         .wkdep_srcs     = dsp_24xx_wkdeps,
         .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
@@ -481,8 +475,6 @@ static struct clockdomain dsp_2420_clkdm = {
         .name           = "dsp_clkdm",
         .pwrdm          = { .name = "dsp_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
@@ -491,7 +483,6 @@ static struct clockdomain gfx_2420_clkdm = {
         .name           = "gfx_clkdm",
         .pwrdm          = { .name = "gfx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = gfx_sgx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -501,7 +492,6 @@ static struct clockdomain core_l3_2420_clkdm = {
         .name           = "core_l3_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = core_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -511,7 +501,6 @@ static struct clockdomain core_l4_2420_clkdm = {
         .name           = "core_l4_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = core_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
@@ -521,7 +510,6 @@ static struct clockdomain dss_2420_clkdm = {
         .name           = "dss_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
@@ -539,8 +527,6 @@ static struct clockdomain mpu_2430_clkdm = {
         .name           = "mpu_clkdm",
         .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(MPU_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = mpu_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -551,8 +537,6 @@ static struct clockdomain mdm_clkdm = {
         .name           = "mdm_clkdm",
         .pwrdm          = { .name = "mdm_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
         .wkdep_srcs     = mdm_2430_wkdeps,
         .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
@@ -563,8 +547,6 @@ static struct clockdomain dsp_2430_clkdm = {
         .name           = "dsp_clkdm",
         .pwrdm          = { .name = "dsp_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
         .wkdep_srcs     = dsp_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
@@ -575,7 +557,6 @@ static struct clockdomain gfx_2430_clkdm = {
         .name           = "gfx_clkdm",
         .pwrdm          = { .name = "gfx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = gfx_sgx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
@@ -590,7 +571,6 @@ static struct clockdomain core_l3_2430_clkdm = {
         .name           = "core_l3_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
         .wkdep_srcs     = core_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
@@ -606,7 +586,6 @@ static struct clockdomain core_l4_2430_clkdm = {
         .name           = "core_l4_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
         .wkdep_srcs     = core_24xx_wkdeps,
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
@@ -617,7 +596,6 @@ static struct clockdomain dss_2430_clkdm = {
         .name           = "dss_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
@@ -635,7 +613,6 @@ static struct clockdomain mpu_3xxx_clkdm = {
         .name           = "mpu_clkdm",
         .pwrdm          = { .name = "mpu_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_EN_MPU_SHIFT,
         .wkdep_srcs     = mpu_3xxx_wkdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
@@ -646,8 +623,6 @@ static struct clockdomain neon_clkdm = {
         .name           = "neon_clkdm",
         .pwrdm          = { .name = "neon_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = neon_wkdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -657,8 +632,6 @@ static struct clockdomain iva2_clkdm = {
         .name           = "iva2_clkdm",
         .pwrdm          = { .name = "iva2_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
         .wkdep_srcs     = iva2_wkdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
@@ -669,7 +642,6 @@ static struct clockdomain gfx_3430es1_clkdm = {
         .name           = "gfx_clkdm",
         .pwrdm          = { .name = "gfx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = gfx_sgx_wkdeps,
         .sleepdep_srcs  = gfx_sgx_sleepdeps,
         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
@@ -680,8 +652,6 @@ static struct clockdomain sgx_clkdm = {
         .name           = "sgx_clkdm",
         .pwrdm          = { .name = "sgx_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = gfx_sgx_wkdeps,
         .sleepdep_srcs  = gfx_sgx_sleepdeps,
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
@@ -699,7 +669,6 @@ static struct clockdomain d2d_clkdm = {
         .name           = "d2d_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -713,7 +682,6 @@ static struct clockdomain core_l3_3xxx_clkdm = {
         .name           = "core_l3_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -728,7 +696,6 @@ static struct clockdomain core_l4_3xxx_clkdm = {
         .name           = "core_l4_clkdm",
         .pwrdm          = { .name = "core_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -739,8 +706,6 @@ static struct clockdomain dss_3xxx_clkdm = {
         .name           = "dss_clkdm",
         .pwrdm          = { .name = "dss_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
         .wkdep_srcs     = dss_wkdeps,
         .sleepdep_srcs  = dss_sleepdeps,
@@ -752,8 +717,6 @@ static struct clockdomain cam_clkdm = {
         .name           = "cam_clkdm",
         .pwrdm          = { .name = "cam_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = cam_wkdeps,
         .sleepdep_srcs  = cam_sleepdeps,
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
@@ -764,8 +727,6 @@ static struct clockdomain usbhost_clkdm = {
         .name           = "usbhost_clkdm",
         .pwrdm          = { .name = "usbhost_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .wkdep_srcs     = usbhost_wkdeps,
         .sleepdep_srcs  = usbhost_sleepdeps,
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
@@ -776,8 +737,6 @@ static struct clockdomain per_clkdm = {
         .name           = "per_clkdm",
         .pwrdm          = { .name = "per_pwrdm" },
         .flags          = CLKDM_CAN_HWSUP_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .dep_bit        = OMAP3430_EN_PER_SHIFT,
         .wkdep_srcs     = per_wkdeps,
         .sleepdep_srcs  = per_sleepdeps,
@@ -793,8 +752,6 @@ static struct clockdomain emu_clkdm = {
         .name           = "emu_clkdm",
         .pwrdm          = { .name = "emu_pwrdm" },
         .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
-        .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
-                                                 OMAP2_CM_CLKSTCTRL),
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 };
@@ -831,8 +788,6 @@ static struct clockdomain dpll5_clkdm = {
 
 #endif   /* CONFIG_ARCH_OMAP3 */
 
-#include "clockdomains44xx.h"
-
 /*
  * Clockdomain hwsup dependencies (OMAP3 only)
  */
@@ -851,17 +806,10 @@ static struct clkdm_autodep clkdm_autodeps[] = {
         }
 };
 
-/*
- * List of clockdomain pointers per platform
- */
-
-static struct clockdomain *clockdomains_omap[] = {
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+static struct clockdomain *clockdomains_omap2[] __initdata = {
         &wkup_clkdm,
         &cm_clkdm,
         &prm_clkdm,
-#endif
 
 #ifdef CONFIG_ARCH_OMAP2420
         &mpu_2420_clkdm,
@@ -903,35 +851,10 @@ static struct clockdomain *clockdomains_omap[] = {
         &dpll4_clkdm,
         &dpll5_clkdm,
 #endif
-
-#ifdef CONFIG_ARCH_OMAP4
-        &l4_cefuse_44xx_clkdm,
-        &l4_cfg_44xx_clkdm,
-        &tesla_44xx_clkdm,
-        &l3_gfx_44xx_clkdm,
-        &ivahd_44xx_clkdm,
-        &l4_secure_44xx_clkdm,
-        &l4_per_44xx_clkdm,
-        &abe_44xx_clkdm,
-        &l3_instr_44xx_clkdm,
-        &l3_init_44xx_clkdm,
-        &mpuss_44xx_clkdm,
-        &mpu0_44xx_clkdm,
-        &mpu1_44xx_clkdm,
-        &l3_emif_44xx_clkdm,
-        &l4_ao_44xx_clkdm,
-        &ducati_44xx_clkdm,
-        &l3_2_44xx_clkdm,
-        &l3_1_44xx_clkdm,
-        &l3_d2d_44xx_clkdm,
-        &iss_44xx_clkdm,
-        &l3_dss_44xx_clkdm,
-        &l4_wkup_44xx_clkdm,
-        &emu_sys_44xx_clkdm,
-        &l3_dma_44xx_clkdm,
-#endif
-
         NULL,
 };
 
-#endif
+void __init omap2_clockdomains_init(void)
+{
+        clkdm_init(clockdomains_omap2, clkdm_autodeps);
+}
diff --git a/arch/arm/mach-omap2/clockdomains44xx.h b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 7e5ba0f67925..51920fc7fc52 100644
--- a/arch/arm/mach-omap2/clockdomains44xx.h
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -23,18 +23,27 @@
  * -> Populate the Sleep/Wakeup dependencies for the domains
  */
 
-#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
+#include <linux/kernel.h>
+#include <linux/io.h>
 
-#include <plat/clockdomain.h>
+#include "clockdomain.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+#include "cm-regbits-44xx.h"
+#include "prm44xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu44xx.h"
 
-#if defined(CONFIG_ARCH_OMAP4)
 
 static struct clockdomain l4_cefuse_44xx_clkdm = {
         .name             = "l4_cefuse_clkdm",
         .pwrdm            = { .name = "cefuse_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_CEFUSE_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CEFUSE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -42,8 +51,9 @@ static struct clockdomain l4_cefuse_44xx_clkdm = {
 static struct clockdomain l4_cfg_44xx_clkdm = {
         .name             = "l4_cfg_clkdm",
         .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L4CFG_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -51,8 +61,9 @@ static struct clockdomain l4_cfg_44xx_clkdm = {
 static struct clockdomain tesla_44xx_clkdm = {
         .name             = "tesla_clkdm",
         .pwrdm            = { .name = "tesla_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_TESLA_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM1_PARTITION,
+        .cm_inst          = OMAP4430_CM1_TESLA_INST,
+        .clkdm_offs       = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -60,8 +71,9 @@ static struct clockdomain tesla_44xx_clkdm = {
 static struct clockdomain l3_gfx_44xx_clkdm = {
         .name             = "l3_gfx_clkdm",
         .pwrdm            = { .name = "gfx_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_GFX_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_GFX_INST,
+        .clkdm_offs       = OMAP4430_CM2_GFX_GFX_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -69,8 +81,9 @@ static struct clockdomain l3_gfx_44xx_clkdm = {
 static struct clockdomain ivahd_44xx_clkdm = {
         .name             = "ivahd_clkdm",
         .pwrdm            = { .name = "ivahd_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_IVAHD_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_IVAHD_INST,
+        .clkdm_offs       = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -78,8 +91,9 @@ static struct clockdomain ivahd_44xx_clkdm = {
 static struct clockdomain l4_secure_44xx_clkdm = {
         .name             = "l4_secure_clkdm",
         .pwrdm            = { .name = "l4per_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L4SEC_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_L4PER_INST,
+        .clkdm_offs       = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -87,8 +101,9 @@ static struct clockdomain l4_secure_44xx_clkdm = {
 static struct clockdomain l4_per_44xx_clkdm = {
         .name             = "l4_per_clkdm",
         .pwrdm            = { .name = "l4per_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L4PER_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_L4PER_INST,
+        .clkdm_offs       = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -96,8 +111,9 @@ static struct clockdomain l4_per_44xx_clkdm = {
 static struct clockdomain abe_44xx_clkdm = {
         .name             = "abe_clkdm",
         .pwrdm            = { .name = "abe_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM1_ABE_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM1_PARTITION,
+        .cm_inst          = OMAP4430_CM1_ABE_INST,
+        .clkdm_offs       = OMAP4430_CM1_ABE_ABE_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -105,16 +121,18 @@ static struct clockdomain abe_44xx_clkdm = {
 static struct clockdomain l3_instr_44xx_clkdm = {
         .name             = "l3_instr_clkdm",
         .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L3INSTR_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
 static struct clockdomain l3_init_44xx_clkdm = {
         .name             = "l3_init_clkdm",
         .pwrdm            = { .name = "l3init_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L3INIT_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_L3INIT_INST,
+        .clkdm_offs       = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -122,8 +140,9 @@ static struct clockdomain l3_init_44xx_clkdm = {
 static struct clockdomain mpuss_44xx_clkdm = {
         .name             = "mpuss_clkdm",
         .pwrdm            = { .name = "mpu_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_MPU_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM1_PARTITION,
+        .cm_inst          = OMAP4430_CM1_MPU_INST,
+        .clkdm_offs       = OMAP4430_CM1_MPU_MPU_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -131,8 +150,9 @@ static struct clockdomain mpuss_44xx_clkdm = {
 static struct clockdomain mpu0_44xx_clkdm = {
         .name             = "mpu0_clkdm",
         .pwrdm            = { .name = "cpu0_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_CPU0_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
+        .cm_inst          = OMAP4430_PRCM_MPU_CPU0_INST,
+        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -140,8 +160,9 @@ static struct clockdomain mpu0_44xx_clkdm = {
 static struct clockdomain mpu1_44xx_clkdm = {
         .name             = "mpu1_clkdm",
         .pwrdm            = { .name = "cpu1_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_CPU1_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
+        .cm_inst          = OMAP4430_PRCM_MPU_CPU1_INST,
+        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -149,8 +170,9 @@ static struct clockdomain mpu1_44xx_clkdm = {
 static struct clockdomain l3_emif_44xx_clkdm = {
         .name             = "l3_emif_clkdm",
         .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_MEMIF_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -158,8 +180,9 @@ static struct clockdomain l3_emif_44xx_clkdm = {
 static struct clockdomain l4_ao_44xx_clkdm = {
         .name             = "l4_ao_clkdm",
         .pwrdm            = { .name = "always_on_core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_ALWON_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_ALWAYS_ON_INST,
+        .clkdm_offs       = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -167,8 +190,9 @@ static struct clockdomain l4_ao_44xx_clkdm = {
 static struct clockdomain ducati_44xx_clkdm = {
         .name             = "ducati_clkdm",
         .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_DUCATI_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -176,8 +200,9 @@ static struct clockdomain ducati_44xx_clkdm = {
 static struct clockdomain l3_2_44xx_clkdm = {
         .name             = "l3_2_clkdm",
         .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L3_2_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_L3_2_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -185,8 +210,9 @@ static struct clockdomain l3_2_44xx_clkdm = {
 static struct clockdomain l3_1_44xx_clkdm = {
         .name             = "l3_1_clkdm",
         .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_L3_1_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_L3_1_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -194,8 +220,9 @@ static struct clockdomain l3_1_44xx_clkdm = {
 static struct clockdomain l3_d2d_44xx_clkdm = {
         .name             = "l3_d2d_clkdm",
         .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_D2D_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_D2D_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -203,8 +230,9 @@ static struct clockdomain l3_d2d_44xx_clkdm = {
 static struct clockdomain iss_44xx_clkdm = {
         .name             = "iss_clkdm",
         .pwrdm            = { .name = "cam_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_CAM_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CAM_INST,
+        .clkdm_offs       = OMAP4430_CM2_CAM_CAM_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -212,8 +240,9 @@ static struct clockdomain iss_44xx_clkdm = {
 static struct clockdomain l3_dss_44xx_clkdm = {
         .name             = "l3_dss_clkdm",
         .pwrdm            = { .name = "dss_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_DSS_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_DSS_INST,
+        .clkdm_offs       = OMAP4430_CM2_DSS_DSS_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP_SWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -221,8 +250,9 @@ static struct clockdomain l3_dss_44xx_clkdm = {
 static struct clockdomain l4_wkup_44xx_clkdm = {
         .name             = "l4_wkup_clkdm",
         .pwrdm            = { .name = "wkup_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_WKUP_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
+        .cm_inst          = OMAP4430_PRM_WKUP_CM_INST,
+        .clkdm_offs       = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -230,8 +260,9 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
 static struct clockdomain emu_sys_44xx_clkdm = {
         .name             = "emu_sys_clkdm",
         .pwrdm            = { .name = "emu_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_EMU_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
+        .cm_inst          = OMAP4430_PRM_EMU_CM_INST,
+        .clkdm_offs       = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
         .flags            = CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -239,12 +270,42 @@ static struct clockdomain emu_sys_44xx_clkdm = {
 static struct clockdomain l3_dma_44xx_clkdm = {
         .name             = "l3_dma_clkdm",
         .pwrdm            = { .name = "core_pwrdm" },
-        .clkstctrl_reg    = OMAP4430_CM_SDMA_CLKSTCTRL,
-        .clktrctrl_mask   = OMAP4430_CLKTRCTRL_MASK,
+        .prcm_partition   = OMAP4430_CM2_PARTITION,
+        .cm_inst          = OMAP4430_CM2_CORE_INST,
+        .clkdm_offs       = OMAP4430_CM2_CORE_SDMA_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
-#endif
+static struct clockdomain *clockdomains_omap44xx[] __initdata = {
+        &l4_cefuse_44xx_clkdm,
+        &l4_cfg_44xx_clkdm,
+        &tesla_44xx_clkdm,
+        &l3_gfx_44xx_clkdm,
+        &ivahd_44xx_clkdm,
+        &l4_secure_44xx_clkdm,
+        &l4_per_44xx_clkdm,
+        &abe_44xx_clkdm,
+        &l3_instr_44xx_clkdm,
+        &l3_init_44xx_clkdm,
+        &mpuss_44xx_clkdm,
+        &mpu0_44xx_clkdm,
+        &mpu1_44xx_clkdm,
+        &l3_emif_44xx_clkdm,
+        &l4_ao_44xx_clkdm,
+        &ducati_44xx_clkdm,
+        &l3_2_44xx_clkdm,
+        &l3_1_44xx_clkdm,
+        &l3_d2d_44xx_clkdm,
+        &iss_44xx_clkdm,
+        &l3_dss_44xx_clkdm,
+        &l4_wkup_44xx_clkdm,
+        &emu_sys_44xx_clkdm,
+        &l3_dma_44xx_clkdm,
+        NULL,
+};
 
-#endif
+void __init omap44xx_clockdomains_init(void)
+{
+        clkdm_init(clockdomains_omap44xx, NULL);
+}
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index da51cc3ed7eb..d70660e82fe6 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -14,8 +14,6 @@
  * published by the Free Software Foundation.
  */
 
-#include "cm.h"
-
 /* Bits shared between registers */
 
 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
@@ -126,8 +124,12 @@
 #define OMAP24XX_ST_HDQ_MASK                            (1 << 23)
 #define OMAP2420_ST_I2C2_SHIFT                          20
 #define OMAP2420_ST_I2C2_MASK                           (1 << 20)
+#define OMAP2430_ST_I2CHS1_SHIFT                        19
+#define OMAP2430_ST_I2CHS1_MASK                         (1 << 19)
 #define OMAP2420_ST_I2C1_SHIFT                          19
 #define OMAP2420_ST_I2C1_MASK                           (1 << 19)
+#define OMAP2430_ST_I2CHS2_SHIFT                        20
+#define OMAP2430_ST_I2CHS2_MASK                         (1 << 20)
 #define OMAP24XX_ST_MCBSP2_SHIFT                        16
 #define OMAP24XX_ST_MCBSP2_MASK                         (1 << 16)
 #define OMAP24XX_ST_MCBSP1_SHIFT                        15
@@ -432,4 +434,9 @@
 #define OMAP2430_AUTOSTATE_MDM_SHIFT                    0
 #define OMAP2430_AUTOSTATE_MDM_MASK                     (1 << 0)
 
+/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
+#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO         0x0
+#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO          0x1
+
+
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 4f959a7d881c..b91275908f33 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -14,8 +14,6 @@
  * published by the Free Software Foundation.
  */
 
-#include "cm.h"
-
 /* Bits shared between registers */
 
 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
@@ -800,4 +798,15 @@
 #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT           0
 #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK            (1 << 0)
 
+/*
+ *
+ */
+
+/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
+#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO         0x0
+#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP          0x1
+#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP         0x2
+#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO          0x3
+
+
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 0b72be433776..9d47a05b17b4 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -22,9 +22,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
 
-#include "cm.h"
-
-
 /*
  * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
  * CM_TESLA_DYNAMICDEP
diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c
deleted file mode 100644
index 721c3b66740a..000000000000
--- a/arch/arm/mach-omap2/cm.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * OMAP2/3 CM module functions
- *
- * Copyright (C) 2009 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <asm/atomic.h>
-
-#include <plat/common.h>
-
-#include "cm.h"
-#include "cm-regbits-24xx.h"
-#include "cm-regbits-34xx.h"
-
-static const u8 cm_idlest_offs[] = {
-        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
-};
-
-/**
- * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
- * @prcm_mod: PRCM module offset
- * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
- * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
- *
- * XXX document
- */
-int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
-{
-        int ena = 0, i = 0;
-        u8 cm_idlest_reg;
-        u32 mask;
-
-        if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
-                return -EINVAL;
-
-        cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
-
-        mask = 1 << idlest_shift;
-
-        if (cpu_is_omap24xx())
-                ena = mask;
-        else if (cpu_is_omap34xx())
-                ena = 0;
-        else
-                BUG();
-
-        /* XXX should be OMAP2 CM */
-        omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
-                          MAX_MODULE_READY_TIME, i);
-
-        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
-}
-
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index a02ca30423dc..a7bc096bd407 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -1,8 +1,5 @@
-#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
-#define __ARCH_ASM_MACH_OMAP2_CM_H
-
 /*
- * OMAP2/3 Clock Management (CM) register definitions
+ * OMAP2+ Clock Management prototypes
  *
  * Copyright (C) 2007-2009 Texas Instruments, Inc.
  * Copyright (C) 2007-2009 Nokia Corporation
@@ -13,136 +10,8 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
-#include "prcm-common.h"
-
-#define OMAP2420_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
-#define OMAP2430_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
-#define OMAP34XX_CM_REGADDR(module, reg)                                \
-                        OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
-#define OMAP44XX_CM1_REGADDR(module, reg)                               \
-                        OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
-#define OMAP44XX_CM2_REGADDR(module, reg)                               \
-                        OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
-
-#include "cm44xx.h"
-
-/*
- * Architecture-specific global CM registers
- * Use cm_{read,write}_reg() with these registers.
- * These registers appear once per CM module.
- */
-
-#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
-
-#define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
-#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
-
-/*
- * Module specific CM registers from CM_BASE + domain offset
- * Use cm_{read,write}_mod_reg() with these registers.
- * These register offsets generally appear in more than one PRCM submodule.
- */
-
-/* Common between 24xx and 34xx */
-
-#define CM_FCLKEN                                       0x0000
-#define CM_FCLKEN1                                      CM_FCLKEN
-#define CM_CLKEN                                        CM_FCLKEN
-#define CM_ICLKEN                                       0x0010
-#define CM_ICLKEN1                                      CM_ICLKEN
-#define CM_ICLKEN2                                      0x0014
-#define CM_ICLKEN3                                      0x0018
-#define CM_IDLEST                                       0x0020
-#define CM_IDLEST1                                      CM_IDLEST
-#define CM_IDLEST2                                      0x0024
-#define CM_AUTOIDLE                                     0x0030
-#define CM_AUTOIDLE1                                    CM_AUTOIDLE
-#define CM_AUTOIDLE2                                    0x0034
-#define CM_AUTOIDLE3                                    0x0038
-#define CM_CLKSEL                                       0x0040
-#define CM_CLKSEL1                                      CM_CLKSEL
-#define CM_CLKSEL2                                      0x0044
-#define OMAP2_CM_CLKSTCTRL                              0x0048
-#define OMAP4_CM_CLKSTCTRL                              0x0000
-
-
-/* Architecture-specific registers */
-
-#define OMAP24XX_CM_FCLKEN2                             0x0004
-#define OMAP24XX_CM_ICLKEN4                             0x001c
-#define OMAP24XX_CM_AUTOIDLE4                           0x003c
-
-#define OMAP2430_CM_IDLEST3                             0x0028
-
-#define OMAP3430_CM_CLKEN_PLL                           0x0004
-#define OMAP3430ES2_CM_CLKEN2                           0x0004
-#define OMAP3430ES2_CM_FCLKEN3                          0x0008
-#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
-#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
-#define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
-#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
-#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
-#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
-#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
-#define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
-#define OMAP3430_CM_CLKSTST                             0x004c
-#define OMAP3430ES2_CM_CLKSEL4                          0x004c
-#define OMAP3430ES2_CM_CLKSEL5                          0x0050
-#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
-#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
-
-/* CM2.CEFUSE_CM2 register offsets */
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL                      0
-#define OMAP4430_MODULEMODE_SWCTRL                      1
-
-/* Clock management domain register get/set */
-
-#ifndef __ASSEMBLER__
-
-extern u32 cm_read_mod_reg(s16 module, u16 idx);
-extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
-extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
-
-extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
-                                      u8 idlest_shift);
-extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
-
-static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return cm_rmw_mod_reg_bits(bits, bits, module, idx);
-}
-
-static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
-}
-
-#endif
-
-/* CM register bits shared between 24XX and 3430 */
-
-/* CM_CLKSEL_GFX */
-#define OMAP_CLKSEL_GFX_SHIFT                           0
-#define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
-
-/* CM_ICLKEN_GFX */
-#define OMAP_EN_GFX_SHIFT                               0
-#define OMAP_EN_GFX_MASK                                (1 << 0)
-
-/* CM_IDLEST_GFX */
-#define OMAP_ST_GFX_MASK                                (1 << 0)
-
-
-/* CM_IDLEST indicator */
-#define OMAP24XX_CM_IDLEST_VAL          0
-#define OMAP34XX_CM_IDLEST_VAL          1
+#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
+#define __ARCH_ASM_MACH_OMAP2_CM_H
 
 /*
  * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
new file mode 100644
index 000000000000..e2d7a56b2ad6
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -0,0 +1,261 @@
+/*
+ * OMAP44xx CM1 instance offset macros
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ *     or "OMAP4430".
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
+
+/* CM1 base address */
+#define OMAP4430_CM1_BASE               0x4a004000
+
+#define OMAP44XX_CM1_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
+
+/* CM1 instances */
+#define OMAP4430_CM1_OCP_SOCKET_INST    0x0000
+#define OMAP4430_CM1_CKGEN_INST         0x0100
+#define OMAP4430_CM1_MPU_INST           0x0300
+#define OMAP4430_CM1_TESLA_INST         0x0400
+#define OMAP4430_CM1_ABE_INST           0x0500
+#define OMAP4430_CM1_RESTORE_INST       0x0e00
+#define OMAP4430_CM1_INSTR_INST         0x0f00
+
+/* CM1 clockdomain register offsets (from instance start) */
+#define OMAP4430_CM1_ABE_ABE_CDOFFS             0x0000
+#define OMAP4430_CM1_MPU_MPU_CDOFFS             0x0000
+#define OMAP4430_CM1_TESLA_TESLA_CDOFFS         0x0000
+
+/* CM1 */
+
+/* CM1.OCP_SOCKET_CM1 register offsets */
+#define OMAP4_REVISION_CM1_OFFSET                       0x0000
+#define OMAP4430_REVISION_CM1                           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
+#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET           0x0040
+#define OMAP4430_CM_CM1_PROFILING_CLKCTRL               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
+
+/* CM1.CKGEN_CM1 register offsets */
+#define OMAP4_CM_CLKSEL_CORE_OFFSET                     0x0000
+#define OMAP4430_CM_CLKSEL_CORE                         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
+#define OMAP4_CM_CLKSEL_ABE_OFFSET                      0x0008
+#define OMAP4430_CM_CLKSEL_ABE                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
+#define OMAP4_CM_DLL_CTRL_OFFSET                        0x0010
+#define OMAP4430_CM_DLL_CTRL                            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
+#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET               0x0020
+#define OMAP4430_CM_CLKMODE_DPLL_CORE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
+#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET                0x0024
+#define OMAP4430_CM_IDLEST_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
+#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET              0x0028
+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
+#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET                0x002c
+#define OMAP4430_CM_CLKSEL_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
+#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET                0x0030
+#define OMAP4430_CM_DIV_M2_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
+#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET                0x0034
+#define OMAP4430_CM_DIV_M3_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
+#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET                0x0038
+#define OMAP4430_CM_DIV_M4_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
+#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET                0x003c
+#define OMAP4430_CM_DIV_M5_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
+#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET                0x0040
+#define OMAP4430_CM_DIV_M6_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
+#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET                0x0044
+#define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET        0x0048
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET       0x004c
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
+#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET          0x0050
+#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
+#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET                0x0060
+#define OMAP4430_CM_CLKMODE_DPLL_MPU                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
+#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET                 0x0064
+#define OMAP4430_CM_IDLEST_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
+#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET               0x0068
+#define OMAP4430_CM_AUTOIDLE_DPLL_MPU                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
+#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET                 0x006c
+#define OMAP4430_CM_CLKSEL_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
+#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET                 0x0070
+#define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET         0x0088
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET                0x008c
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
+#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET                 0x009c
+#define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
+#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET                0x00a0
+#define OMAP4430_CM_CLKMODE_DPLL_IVA                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
+#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET                 0x00a4
+#define OMAP4430_CM_IDLEST_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
+#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET               0x00a8
+#define OMAP4430_CM_AUTOIDLE_DPLL_IVA                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
+#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET                 0x00ac
+#define OMAP4430_CM_CLKSEL_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
+#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET                 0x00b8
+#define OMAP4430_CM_DIV_M4_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
+#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET                 0x00bc
+#define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET         0x00c8
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET                0x00cc
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
+#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET                 0x00dc
+#define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
+#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET                0x00e0
+#define OMAP4430_CM_CLKMODE_DPLL_ABE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
+#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET                 0x00e4
+#define OMAP4430_CM_IDLEST_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
+#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET               0x00e8
+#define OMAP4430_CM_AUTOIDLE_DPLL_ABE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
+#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET                 0x00ec
+#define OMAP4430_CM_CLKSEL_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
+#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET                 0x00f0
+#define OMAP4430_CM_DIV_M2_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
+#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET                 0x00f4
+#define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET         0x0108
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET                0x010c
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
+#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET             0x0120
+#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
+#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET              0x0124
+#define OMAP4430_CM_IDLEST_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
+#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET            0x0128
+#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
+#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET              0x012c
+#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
+#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET              0x0130
+#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
+#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET              0x0138
+#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
+#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET              0x013c
+#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
+#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET              0x0140
+#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET      0x0148
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET     0x014c
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET             0x0160
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET             0x0164
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG2                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
+#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET                 0x0170
+#define OMAP4430_CM_DYN_DEP_PRESCAL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
+#define OMAP4_CM_RESTORE_ST_OFFSET                      0x0180
+#define OMAP4430_CM_RESTORE_ST                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
+
+/* CM1.MPU_CM1 register offsets */
+#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET                   0x0000
+#define OMAP4430_CM_MPU_CLKSTCTRL                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
+#define OMAP4_CM_MPU_STATICDEP_OFFSET                   0x0004
+#define OMAP4430_CM_MPU_STATICDEP                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
+#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET                  0x0008
+#define OMAP4430_CM_MPU_DYNAMICDEP                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
+#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET                 0x0020
+#define OMAP4430_CM_MPU_MPU_CLKCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
+
+/* CM1.TESLA_CM1 register offsets */
+#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET                 0x0000
+#define OMAP4430_CM_TESLA_CLKSTCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
+#define OMAP4_CM_TESLA_STATICDEP_OFFSET                 0x0004
+#define OMAP4430_CM_TESLA_STATICDEP                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
+#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET                0x0008
+#define OMAP4430_CM_TESLA_DYNAMICDEP                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
+#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET             0x0020
+#define OMAP4430_CM_TESLA_TESLA_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
+
+/* CM1.ABE_CM1 register offsets */
+#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET                  0x0000
+#define OMAP4430_CM1_ABE_CLKSTCTRL                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
+#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET              0x0020
+#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
+#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET               0x0028
+#define OMAP4430_CM1_ABE_AESS_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
+#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET                0x0030
+#define OMAP4430_CM1_ABE_PDM_CLKCTRL                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
+#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET               0x0038
+#define OMAP4430_CM1_ABE_DMIC_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
+#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET              0x0040
+#define OMAP4430_CM1_ABE_MCASP_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
+#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET             0x0048
+#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
+#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET             0x0050
+#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
+#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET             0x0058
+#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
+#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET            0x0060
+#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
+#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET             0x0068
+#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
+#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET             0x0070
+#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
+#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET             0x0078
+#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
+#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET             0x0080
+#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
+#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
+#define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
+
+/* CM1.RESTORE_CM1 register offsets */
+#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET             0x0000
+#define OMAP4430_CM_CLKSEL_CORE_RESTORE                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
+#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET        0x0004
+#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
+#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET        0x0008
+#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
+#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET        0x000c
+#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
+#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET        0x0010
+#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
+#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET        0x0014
+#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
+#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET        0x0018
+#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
+#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET        0x001c
+#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET        0x0020
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET       0x0024
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
+#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET       0x0028
+#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET     0x002c
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
+#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET     0x0030
+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
+#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET      0x0034
+#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
+#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET           0x0038
+#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
+#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET   0x003c
+#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
+#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET         0x0040
+#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
+
+/* Function prototypes */
+extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
new file mode 100644
index 000000000000..aa4745044065
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -0,0 +1,508 @@
+/*
+ * OMAP44xx CM2 instance offset macros
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ *     or "OMAP4430".
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
+
+/* CM2 base address */
+#define OMAP4430_CM2_BASE               0x4a008000
+
+#define OMAP44XX_CM2_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
+
+/* CM2 instances */
+#define OMAP4430_CM2_OCP_SOCKET_INST    0x0000
+#define OMAP4430_CM2_CKGEN_INST         0x0100
+#define OMAP4430_CM2_ALWAYS_ON_INST     0x0600
+#define OMAP4430_CM2_CORE_INST          0x0700
+#define OMAP4430_CM2_IVAHD_INST         0x0f00
+#define OMAP4430_CM2_CAM_INST           0x1000
+#define OMAP4430_CM2_DSS_INST           0x1100
+#define OMAP4430_CM2_GFX_INST           0x1200
+#define OMAP4430_CM2_L3INIT_INST                0x1300
+#define OMAP4430_CM2_L4PER_INST         0x1400
+#define OMAP4430_CM2_CEFUSE_INST                0x1600
+#define OMAP4430_CM2_RESTORE_INST       0x1e00
+#define OMAP4430_CM2_INSTR_INST         0x1f00
+
+/* CM2 clockdomain register offsets (from instance start) */
+#define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS     0x0000
+#define OMAP4430_CM2_CORE_L3_1_CDOFFS           0x0000
+#define OMAP4430_CM2_CORE_L3_2_CDOFFS           0x0100
+#define OMAP4430_CM2_CORE_DUCATI_CDOFFS         0x0200
+#define OMAP4430_CM2_CORE_SDMA_CDOFFS           0x0300
+#define OMAP4430_CM2_CORE_MEMIF_CDOFFS          0x0400
+#define OMAP4430_CM2_CORE_D2D_CDOFFS            0x0500
+#define OMAP4430_CM2_CORE_L4CFG_CDOFFS          0x0600
+#define OMAP4430_CM2_CORE_L3INSTR_CDOFFS        0x0700
+#define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS         0x0000
+#define OMAP4430_CM2_CAM_CAM_CDOFFS             0x0000
+#define OMAP4430_CM2_DSS_DSS_CDOFFS             0x0000
+#define OMAP4430_CM2_GFX_GFX_CDOFFS             0x0000
+#define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS       0x0000
+#define OMAP4430_CM2_L4PER_L4PER_CDOFFS         0x0000
+#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS         0x0180
+#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS       0x0000
+
+
+/* CM2 */
+
+/* CM2.OCP_SOCKET_CM2 register offsets */
+#define OMAP4_REVISION_CM2_OFFSET                       0x0000
+#define OMAP4430_REVISION_CM2                           OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000)
+#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET           0x0040
+#define OMAP4430_CM_CM2_PROFILING_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040)
+
+/* CM2.CKGEN_CM2 register offsets */
+#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET          0x0000
+#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000)
+#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET                0x0004
+#define OMAP4430_CM_CLKSEL_USB_60MHZ                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004)
+#define OMAP4_CM_SCALE_FCLK_OFFSET                      0x0008
+#define OMAP4430_CM_SCALE_FCLK                          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008)
+#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET                 0x0010
+#define OMAP4430_CM_CORE_DVFS_PERF1                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010)
+#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET                 0x0014
+#define OMAP4430_CM_CORE_DVFS_PERF2                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014)
+#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET                 0x0018
+#define OMAP4430_CM_CORE_DVFS_PERF3                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018)
+#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET                 0x001c
+#define OMAP4430_CM_CORE_DVFS_PERF4                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c)
+#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET               0x0024
+#define OMAP4430_CM_CORE_DVFS_CURRENT                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024)
+#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET             0x0028
+#define OMAP4430_CM_IVA_DVFS_PERF_TESLA                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028)
+#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET             0x002c
+#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c)
+#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET               0x0030
+#define OMAP4430_CM_IVA_DVFS_PERF_ABE                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030)
+#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET                0x0038
+#define OMAP4430_CM_IVA_DVFS_CURRENT                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038)
+#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET                0x0040
+#define OMAP4430_CM_CLKMODE_DPLL_PER                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040)
+#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET                 0x0044
+#define OMAP4430_CM_IDLEST_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044)
+#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET               0x0048
+#define OMAP4430_CM_AUTOIDLE_DPLL_PER                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048)
+#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET                 0x004c
+#define OMAP4430_CM_CLKSEL_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c)
+#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET                 0x0050
+#define OMAP4430_CM_DIV_M2_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050)
+#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET                 0x0054
+#define OMAP4430_CM_DIV_M3_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054)
+#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET                 0x0058
+#define OMAP4430_CM_DIV_M4_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058)
+#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET                 0x005c
+#define OMAP4430_CM_DIV_M5_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c)
+#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET                 0x0060
+#define OMAP4430_CM_DIV_M6_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060)
+#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET                 0x0064
+#define OMAP4430_CM_DIV_M7_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET         0x0068
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET                0x006c
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
+#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET                0x0080
+#define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
+#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET                 0x0084
+#define OMAP4430_CM_IDLEST_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084)
+#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET               0x0088
+#define OMAP4430_CM_AUTOIDLE_DPLL_USB                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088)
+#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET                 0x008c
+#define OMAP4430_CM_CLKSEL_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c)
+#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET                 0x0090
+#define OMAP4430_CM_DIV_M2_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET         0x00a8
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET                0x00ac
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
+#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET              0x00b4
+#define OMAP4430_CM_CLKDCOLDO_DPLL_USB                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
+#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET             0x00c0
+#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0)
+#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET              0x00c4
+#define OMAP4430_CM_IDLEST_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4)
+#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET            0x00c8
+#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8)
+#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET              0x00cc
+#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc)
+#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET              0x00d0
+#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET      0x00e8
+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
+#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET     0x00ec
+#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
+
+/* CM2.ALWAYS_ON_CM2 register offsets */
+#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET                 0x0000
+#define OMAP4430_CM_ALWON_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000)
+#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET           0x0020
+#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020)
+#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET            0x0028
+#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028)
+#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET            0x0030
+#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030)
+#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET           0x0038
+#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038)
+#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET            0x0040
+#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040)
+
+/* CM2.CORE_CM2 register offsets */
+#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET                  0x0000
+#define OMAP4430_CM_L3_1_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000)
+#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET                 0x0008
+#define OMAP4430_CM_L3_1_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008)
+#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET               0x0020
+#define OMAP4430_CM_L3_1_L3_1_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020)
+#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET                  0x0100
+#define OMAP4430_CM_L3_2_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100)
+#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET                 0x0108
+#define OMAP4430_CM_L3_2_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108)
+#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET               0x0120
+#define OMAP4430_CM_L3_2_L3_2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120)
+#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET               0x0128
+#define OMAP4430_CM_L3_2_GPMC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128)
+#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET           0x0130
+#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130)
+#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET                0x0200
+#define OMAP4430_CM_DUCATI_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200)
+#define OMAP4_CM_DUCATI_STATICDEP_OFFSET                0x0204
+#define OMAP4430_CM_DUCATI_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204)
+#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET               0x0208
+#define OMAP4430_CM_DUCATI_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208)
+#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET           0x0220
+#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220)
+#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET                  0x0300
+#define OMAP4430_CM_SDMA_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300)
+#define OMAP4_CM_SDMA_STATICDEP_OFFSET                  0x0304
+#define OMAP4430_CM_SDMA_STATICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304)
+#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET                 0x0308
+#define OMAP4430_CM_SDMA_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308)
+#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET               0x0320
+#define OMAP4430_CM_SDMA_SDMA_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320)
+#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET                 0x0400
+#define OMAP4430_CM_MEMIF_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400)
+#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET               0x0420
+#define OMAP4430_CM_MEMIF_DMM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420)
+#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET           0x0428
+#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428)
+#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET            0x0430
+#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430)
+#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET            0x0438
+#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438)
+#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET               0x0440
+#define OMAP4430_CM_MEMIF_DLL_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440)
+#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET           0x0450
+#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450)
+#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET           0x0458
+#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458)
+#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET             0x0460
+#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460)
+#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET                   0x0500
+#define OMAP4430_CM_D2D_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500)
+#define OMAP4_CM_D2D_STATICDEP_OFFSET                   0x0504
+#define OMAP4430_CM_D2D_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504)
+#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET                  0x0508
+#define OMAP4430_CM_D2D_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
+#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET               0x0520
+#define OMAP4430_CM_D2D_SAD2D_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
+#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET          0x0528
+#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
+#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET            0x0530
+#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
+#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET                 0x0600
+#define OMAP4430_CM_L4CFG_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600)
+#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET                0x0608
+#define OMAP4430_CM_L4CFG_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608)
+#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET            0x0620
+#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620)
+#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET            0x0628
+#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628)
+#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET           0x0630
+#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630)
+#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET           0x0638
+#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638)
+#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET               0x0700
+#define OMAP4430_CM_L3INSTR_CLKSTCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700)
+#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET            0x0720
+#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720)
+#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET        0x0728
+#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728)
+#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET         0x0740
+#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740)
+
+/* CM2.IVAHD_CM2 register offsets */
+#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET                 0x0000
+#define OMAP4430_CM_IVAHD_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000)
+#define OMAP4_CM_IVAHD_STATICDEP_OFFSET                 0x0004
+#define OMAP4430_CM_IVAHD_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004)
+#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET                0x0008
+#define OMAP4430_CM_IVAHD_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008)
+#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET             0x0020
+#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020)
+#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET               0x0028
+#define OMAP4430_CM_IVAHD_SL2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028)
+
+/* CM2.CAM_CM2 register offsets */
+#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET                   0x0000
+#define OMAP4430_CM_CAM_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000)
+#define OMAP4_CM_CAM_STATICDEP_OFFSET                   0x0004
+#define OMAP4430_CM_CAM_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004)
+#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET                  0x0008
+#define OMAP4430_CM_CAM_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008)
+#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET                 0x0020
+#define OMAP4430_CM_CAM_ISS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020)
+#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET                0x0028
+#define OMAP4430_CM_CAM_FDIF_CLKCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028)
+
+/* CM2.DSS_CM2 register offsets */
+#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET                   0x0000
+#define OMAP4430_CM_DSS_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000)
+#define OMAP4_CM_DSS_STATICDEP_OFFSET                   0x0004
+#define OMAP4430_CM_DSS_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004)
+#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET                  0x0008
+#define OMAP4430_CM_DSS_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008)
+#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET                 0x0020
+#define OMAP4430_CM_DSS_DSS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020)
+#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET               0x0028
+#define OMAP4430_CM_DSS_DEISS_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028)
+
+/* CM2.GFX_CM2 register offsets */
+#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET                   0x0000
+#define OMAP4430_CM_GFX_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000)
+#define OMAP4_CM_GFX_STATICDEP_OFFSET                   0x0004
+#define OMAP4430_CM_GFX_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004)
+#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET                  0x0008
+#define OMAP4430_CM_GFX_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008)
+#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET                 0x0020
+#define OMAP4430_CM_GFX_GFX_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020)
+
+/* CM2.L3INIT_CM2 register offsets */
+#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET                0x0000
+#define OMAP4430_CM_L3INIT_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000)
+#define OMAP4_CM_L3INIT_STATICDEP_OFFSET                0x0004
+#define OMAP4430_CM_L3INIT_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004)
+#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET               0x0008
+#define OMAP4430_CM_L3INIT_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008)
+#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET             0x0028
+#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028)
+#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET             0x0030
+#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030)
+#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET              0x0038
+#define OMAP4430_CM_L3INIT_HSI_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038)
+#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET          0x0040
+#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040)
+#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET         0x0058
+#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058)
+#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET          0x0060
+#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060)
+#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET          0x0068
+#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068)
+#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET            0x0078
+#define OMAP4430_CM_L3INIT_P1500_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078)
+#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET             0x0080
+#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080)
+#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET             0x0088
+#define OMAP4430_CM_L3INIT_SATA_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088)
+#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET            0x0090
+#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090)
+#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET           0x0098
+#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098)
+#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET            0x00a8
+#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8)
+#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET             0x00c0
+#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0)
+#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET             0x00c8
+#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8)
+#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET      0x00d0
+#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0)
+#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET    0x00e0
+#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0)
+
+/* CM2.L4PER_CM2 register offsets */
+#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET                 0x0000
+#define OMAP4430_CM_L4PER_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000)
+#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET                0x0008
+#define OMAP4430_CM_L4PER_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008)
+#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET               0x0020
+#define OMAP4430_CM_L4PER_ADC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020)
+#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET         0x0028
+#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028)
+#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET         0x0030
+#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030)
+#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET          0x0038
+#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038)
+#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET          0x0040
+#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040)
+#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET          0x0048
+#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048)
+#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET          0x0050
+#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050)
+#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET               0x0058
+#define OMAP4430_CM_L4PER_ELM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058)
+#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET             0x0060
+#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060)
+#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET             0x0068
+#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068)
+#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET             0x0070
+#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070)
+#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET             0x0078
+#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078)
+#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET             0x0080
+#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080)
+#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET             0x0088
+#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088)
+#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET             0x0090
+#define OMAP4430_CM_L4PER_HECC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090)
+#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET             0x0098
+#define OMAP4430_CM_L4PER_HECC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098)
+#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET              0x00a0
+#define OMAP4430_CM_L4PER_I2C1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0)
+#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET              0x00a8
+#define OMAP4430_CM_L4PER_I2C2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8)
+#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET              0x00b0
+#define OMAP4430_CM_L4PER_I2C3_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0)
+#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET              0x00b8
+#define OMAP4430_CM_L4PER_I2C4_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8)
+#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET             0x00c0
+#define OMAP4430_CM_L4PER_L4PER_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0)
+#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET            0x00d0
+#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0)
+#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET            0x00d8
+#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8)
+#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET            0x00e0
+#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0)
+#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET             0x00e8
+#define OMAP4430_CM_L4PER_MGATE_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8)
+#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET            0x00f0
+#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0)
+#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET            0x00f8
+#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8)
+#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET            0x0100
+#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100)
+#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET            0x0108
+#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108)
+#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET            0x0120
+#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120)
+#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET            0x0128
+#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128)
+#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET           0x0130
+#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130)
+#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET          0x0138
+#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138)
+#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET             0x0140
+#define OMAP4430_CM_L4PER_UART1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140)
+#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET             0x0148
+#define OMAP4430_CM_L4PER_UART2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148)
+#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET             0x0150
+#define OMAP4430_CM_L4PER_UART3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150)
+#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET             0x0158
+#define OMAP4430_CM_L4PER_UART4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158)
+#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET            0x0160
+#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160)
+#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET              0x0168
+#define OMAP4430_CM_L4PER_I2C5_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168)
+#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET                 0x0180
+#define OMAP4430_CM_L4SEC_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180)
+#define OMAP4_CM_L4SEC_STATICDEP_OFFSET                 0x0184
+#define OMAP4430_CM_L4SEC_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184)
+#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET                0x0188
+#define OMAP4430_CM_L4SEC_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188)
+#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET              0x01a0
+#define OMAP4430_CM_L4SEC_AES1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0)
+#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET              0x01a8
+#define OMAP4430_CM_L4SEC_AES2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8)
+#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET           0x01b0
+#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0)
+#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET          0x01b8
+#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8)
+#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET               0x01c0
+#define OMAP4430_CM_L4SEC_RNG_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0)
+#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET          0x01c8
+#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8)
+#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET         0x01d8
+#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8)
+
+/* CM2.CEFUSE_CM2 register offsets */
+#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET                0x0000
+#define OMAP4430_CM_CEFUSE_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000)
+#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
+#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
+
+/* CM2.RESTORE_CM2 register offsets */
+#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET          0x0000
+#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
+#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET          0x0004
+#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
+#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET         0x0008
+#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
+#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET         0x000c
+#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
+#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET         0x0010
+#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
+#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET        0x0014
+#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
+#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET    0x0018
+#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
+#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET        0x001c
+#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
+#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
+#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
+#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET   0x0024
+#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
+#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET           0x0028
+#define OMAP4430_CM_D2D_STATICDEP_RESTORE               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
+#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET         0x002c
+#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
+#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET         0x0030
+#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
+#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET          0x0034
+#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
+#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET        0x0038
+#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
+#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET        0x003c
+#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
+#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET     0x0040
+#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
+#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET     0x0044
+#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
+#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET     0x0048
+#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
+#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET     0x004c
+#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
+#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET     0x0050
+#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
+#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
+#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
+#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET  0x0058
+#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
+#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET          0x005c
+#define OMAP4430_CM_SDMA_STATICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
+
+/* Function prototypes */
+extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
new file mode 100644
index 000000000000..96954aa48671
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -0,0 +1,471 @@
+/*
+ * OMAP2/3 CM module functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+#include "cm-regbits-34xx.h"
+
+static const u8 cm_idlest_offs[] = {
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
+};
+
+u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
+{
+        return __raw_readl(cm_base + module + idx);
+}
+
+void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __raw_writel(val, cm_base + module + idx);
+}
+
+/* Read-modify-write a register in a CM module. Caller must lock */
+u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        omap2_cm_write_mod_reg(v, module, idx);
+
+        return v;
+}
+
+u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
+}
+
+u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
+
+/*
+ *
+ */
+
+static void _write_clktrctrl(u8 c, s16 module, u32 mask)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
+        v &= ~mask;
+        v |= c << __ffs(mask);
+        omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
+}
+
+bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
+{
+        u32 v;
+        bool ret = 0;
+
+        BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
+
+        v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        if (cpu_is_omap24xx())
+                ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
+        else
+                ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
+
+        return ret;
+}
+
+void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
+}
+
+void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
+}
+
+void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
+}
+
+void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
+}
+
+void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
+}
+
+void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
+{
+        _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
+}
+
+
+/*
+ *
+ */
+
+/**
+ * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
+ * @prcm_mod: PRCM module offset
+ * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
+ * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
+ *
+ * XXX document
+ */
+int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
+{
+        int ena = 0, i = 0;
+        u8 cm_idlest_reg;
+        u32 mask;
+
+        if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
+                return -EINVAL;
+
+        cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
+
+        mask = 1 << idlest_shift;
+
+        if (cpu_is_omap24xx())
+                ena = mask;
+        else if (cpu_is_omap34xx())
+                ena = 0;
+        else
+                BUG();
+
+        omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
+                          MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/*
+ * Context save/restore code - OMAP3 only
+ */
+#ifdef CONFIG_ARCH_OMAP3
+struct omap3_cm_regs {
+        u32 iva2_cm_clksel1;
+        u32 iva2_cm_clksel2;
+        u32 cm_sysconfig;
+        u32 sgx_cm_clksel;
+        u32 dss_cm_clksel;
+        u32 cam_cm_clksel;
+        u32 per_cm_clksel;
+        u32 emu_cm_clksel;
+        u32 emu_cm_clkstctrl;
+        u32 pll_cm_autoidle2;
+        u32 pll_cm_clksel4;
+        u32 pll_cm_clksel5;
+        u32 pll_cm_clken2;
+        u32 cm_polctrl;
+        u32 iva2_cm_fclken;
+        u32 iva2_cm_clken_pll;
+        u32 core_cm_fclken1;
+        u32 core_cm_fclken3;
+        u32 sgx_cm_fclken;
+        u32 wkup_cm_fclken;
+        u32 dss_cm_fclken;
+        u32 cam_cm_fclken;
+        u32 per_cm_fclken;
+        u32 usbhost_cm_fclken;
+        u32 core_cm_iclken1;
+        u32 core_cm_iclken2;
+        u32 core_cm_iclken3;
+        u32 sgx_cm_iclken;
+        u32 wkup_cm_iclken;
+        u32 dss_cm_iclken;
+        u32 cam_cm_iclken;
+        u32 per_cm_iclken;
+        u32 usbhost_cm_iclken;
+        u32 iva2_cm_autoidle2;
+        u32 mpu_cm_autoidle2;
+        u32 iva2_cm_clkstctrl;
+        u32 mpu_cm_clkstctrl;
+        u32 core_cm_clkstctrl;
+        u32 sgx_cm_clkstctrl;
+        u32 dss_cm_clkstctrl;
+        u32 cam_cm_clkstctrl;
+        u32 per_cm_clkstctrl;
+        u32 neon_cm_clkstctrl;
+        u32 usbhost_cm_clkstctrl;
+        u32 core_cm_autoidle1;
+        u32 core_cm_autoidle2;
+        u32 core_cm_autoidle3;
+        u32 wkup_cm_autoidle;
+        u32 dss_cm_autoidle;
+        u32 cam_cm_autoidle;
+        u32 per_cm_autoidle;
+        u32 usbhost_cm_autoidle;
+        u32 sgx_cm_sleepdep;
+        u32 dss_cm_sleepdep;
+        u32 cam_cm_sleepdep;
+        u32 per_cm_sleepdep;
+        u32 usbhost_cm_sleepdep;
+        u32 cm_clkout_ctrl;
+};
+
+static struct omap3_cm_regs cm_context;
+
+void omap3_cm_save_context(void)
+{
+        cm_context.iva2_cm_clksel1 =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
+        cm_context.iva2_cm_clksel2 =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
+        cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
+        cm_context.sgx_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
+        cm_context.dss_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
+        cm_context.cam_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
+        cm_context.per_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
+        cm_context.emu_cm_clksel =
+                omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
+        cm_context.emu_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.pll_cm_autoidle2 =
+                omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
+        cm_context.pll_cm_clksel4 =
+                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
+        cm_context.pll_cm_clksel5 =
+                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
+        cm_context.pll_cm_clken2 =
+                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
+        cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
+        cm_context.iva2_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
+        cm_context.iva2_cm_clken_pll =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
+        cm_context.core_cm_fclken1 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        cm_context.core_cm_fclken3 =
+                omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
+        cm_context.sgx_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
+        cm_context.wkup_cm_fclken =
+                omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
+        cm_context.dss_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
+        cm_context.cam_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
+        cm_context.per_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
+        cm_context.usbhost_cm_fclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
+        cm_context.core_cm_iclken1 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
+        cm_context.core_cm_iclken2 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
+        cm_context.core_cm_iclken3 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
+        cm_context.sgx_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
+        cm_context.wkup_cm_iclken =
+                omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
+        cm_context.dss_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
+        cm_context.cam_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
+        cm_context.per_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
+        cm_context.usbhost_cm_iclken =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
+        cm_context.iva2_cm_autoidle2 =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
+        cm_context.mpu_cm_autoidle2 =
+                omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
+        cm_context.iva2_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.mpu_cm_clkstctrl =
+                omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.core_cm_clkstctrl =
+                omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.sgx_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.dss_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.cam_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.per_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.neon_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
+        cm_context.usbhost_cm_clkstctrl =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                      OMAP2_CM_CLKSTCTRL);
+        cm_context.core_cm_autoidle1 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
+        cm_context.core_cm_autoidle2 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
+        cm_context.core_cm_autoidle3 =
+                omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
+        cm_context.wkup_cm_autoidle =
+                omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
+        cm_context.dss_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
+        cm_context.cam_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
+        cm_context.per_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        cm_context.usbhost_cm_autoidle =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
+        cm_context.sgx_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+                                      OMAP3430_CM_SLEEPDEP);
+        cm_context.dss_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
+        cm_context.cam_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
+        cm_context.per_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
+        cm_context.usbhost_cm_sleepdep =
+                omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+                                      OMAP3430_CM_SLEEPDEP);
+        cm_context.cm_clkout_ctrl =
+                omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
+                                      OMAP3_CM_CLKOUT_CTRL_OFFSET);
+}
+
+void omap3_cm_restore_context(void)
+{
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
+                               CM_CLKSEL1);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
+                               CM_CLKSEL2);
+        __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
+                               CM_CLKSEL);
+        omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
+                               CM_CLKSEL1);
+        omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
+                               OMAP3430ES2_CM_CLKSEL4);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
+                               OMAP3430ES2_CM_CLKSEL5);
+        omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
+                               OMAP3430ES2_CM_CLKEN2);
+        __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
+                               OMAP3430_CM_CLKEN_PLL);
+        omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
+                               CM_FCLKEN1);
+        omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
+                               OMAP3430ES2_CM_FCLKEN3);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
+                               CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
+                               OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
+                               CM_ICLKEN1);
+        omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
+                               CM_ICLKEN2);
+        omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
+                               CM_ICLKEN3);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
+                               CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
+                               OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
+                               OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
+                               OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
+        omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
+                               CM_AUTOIDLE1);
+        omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
+                               CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
+                               CM_AUTOIDLE3);
+        omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
+                               CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
+                               OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
+                               OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
+                               OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
+        omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
+                               OMAP3_CM_CLKOUT_CTRL_OFFSET);
+}
+#endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
new file mode 100644
index 000000000000..5e9ea5bd60b9
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -0,0 +1,147 @@
+/*
+ * OMAP2/3 Clock Management (CM) register definitions
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The CM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The CM modules/instances on OMAP4 are quite different, so
+ * they are handled in a separate file.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
+#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
+
+#include "prcm-common.h"
+
+#define OMAP2420_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
+#define OMAP2430_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
+#define OMAP34XX_CM_REGADDR(module, reg)                                \
+                        OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
+
+
+/*
+ * OMAP3-specific global CM registers
+ * Use cm_{read,write}_reg() with these registers.
+ * These registers appear once per CM module.
+ */
+
+#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
+
+#define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
+#define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific CM register offsets from CM_BASE + domain offset
+ * Use cm_{read,write}_mod_reg() with these registers.
+ * These register offsets generally appear in more than one PRCM submodule.
+ */
+
+/* Common between OMAP2 and OMAP3 */
+
+#define CM_FCLKEN                                       0x0000
+#define CM_FCLKEN1                                      CM_FCLKEN
+#define CM_CLKEN                                        CM_FCLKEN
+#define CM_ICLKEN                                       0x0010
+#define CM_ICLKEN1                                      CM_ICLKEN
+#define CM_ICLKEN2                                      0x0014
+#define CM_ICLKEN3                                      0x0018
+#define CM_IDLEST                                       0x0020
+#define CM_IDLEST1                                      CM_IDLEST
+#define CM_IDLEST2                                      0x0024
+#define CM_AUTOIDLE                                     0x0030
+#define CM_AUTOIDLE1                                    CM_AUTOIDLE
+#define CM_AUTOIDLE2                                    0x0034
+#define CM_AUTOIDLE3                                    0x0038
+#define CM_CLKSEL                                       0x0040
+#define CM_CLKSEL1                                      CM_CLKSEL
+#define CM_CLKSEL2                                      0x0044
+#define OMAP2_CM_CLKSTCTRL                              0x0048
+
+/* OMAP2-specific register offsets */
+
+#define OMAP24XX_CM_FCLKEN2                             0x0004
+#define OMAP24XX_CM_ICLKEN4                             0x001c
+#define OMAP24XX_CM_AUTOIDLE4                           0x003c
+
+#define OMAP2430_CM_IDLEST3                             0x0028
+
+/* OMAP3-specific register offsets */
+
+#define OMAP3430_CM_CLKEN_PLL                           0x0004
+#define OMAP3430ES2_CM_CLKEN2                           0x0004
+#define OMAP3430ES2_CM_FCLKEN3                          0x0008
+#define OMAP3430_CM_IDLEST_PLL                          CM_IDLEST2
+#define OMAP3430_CM_AUTOIDLE_PLL                        CM_AUTOIDLE2
+#define OMAP3430ES2_CM_AUTOIDLE2_PLL                    CM_AUTOIDLE2
+#define OMAP3430_CM_CLKSEL1                             CM_CLKSEL
+#define OMAP3430_CM_CLKSEL1_PLL                         CM_CLKSEL
+#define OMAP3430_CM_CLKSEL2_PLL                         CM_CLKSEL2
+#define OMAP3430_CM_SLEEPDEP                            CM_CLKSEL2
+#define OMAP3430_CM_CLKSEL3                             OMAP2_CM_CLKSTCTRL
+#define OMAP3430_CM_CLKSTST                             0x004c
+#define OMAP3430ES2_CM_CLKSEL4                          0x004c
+#define OMAP3430ES2_CM_CLKSEL5                          0x0050
+#define OMAP3430_CM_CLKSEL2_EMU                         0x0050
+#define OMAP3430_CM_CLKSEL3_EMU                         0x0054
+
+
+/* CM_IDLEST bit field values to indicate deasserted IdleReq */
+
+#define OMAP24XX_CM_IDLEST_VAL                          0
+#define OMAP34XX_CM_IDLEST_VAL                          1
+
+
+/* Clock management domain register get/set */
+
+#ifndef __ASSEMBLER__
+
+extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
+extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
+extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+
+extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
+                                      u8 idlest_shift);
+extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
+extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
+
+extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
+extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+
+extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
+extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
+
+#endif
+
+/* CM register bits shared between 24XX and 3430 */
+
+/* CM_CLKSEL_GFX */
+#define OMAP_CLKSEL_GFX_SHIFT                           0
+#define OMAP_CLKSEL_GFX_MASK                            (0x7 << 0)
+
+/* CM_ICLKEN_GFX */
+#define OMAP_EN_GFX_SHIFT                               0
+#define OMAP_EN_GFX_MASK                                (1 << 0)
+
+/* CM_IDLEST_GFX */
+#define OMAP_ST_GFX_MASK                                (1 << 0)
+
+
+/* Function prototypes */
+# ifndef __ASSEMBLER__
+extern void omap3_cm_save_context(void);
+extern void omap3_cm_restore_context(void);
+# endif
+
+#endif
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
new file mode 100644
index 000000000000..e96f53ea01a1
--- /dev/null
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -0,0 +1,52 @@
+/*
+ * OMAP4 CM1, CM2 module low-level functions
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * These functions are intended to be used only by the cminst44xx.c file.
+ * XXX Perhaps we should just move them there and make them static.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "cm.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+#include "cm-regbits-44xx.h"
+
+/* CM1 hardware module low-level functions */
+
+/* Read a register in CM1 */
+u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
+{
+        return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg));
+}
+
+/* Write into a register in CM1 */
+void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg)
+{
+        __raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg));
+}
+
+/* Read a register in CM2 */
+u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg)
+{
+        return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg));
+}
+
+/* Write into a register in CM2 */
+void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg)
+{
+        __raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg));
+}
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 3c35a87cb90c..48fc3f426fbd 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -1,667 +1,31 @@
 /*
- * OMAP44xx CM1 & CM2 instance offset macros
+ * OMAP4 Clock Management (CM) definitions
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
+ * Written by Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
+ *
+ * OMAP4 has two separate CM blocks, CM1 and CM2.  This file contains
+ * macros and function prototypes that are applicable to both.
  */
+#ifndef __ARCH_ASM_MACH_OMAP2_CM44XX_H
+#define __ARCH_ASM_MACH_OMAP2_CM44XX_H
 
-#ifndef __ARCH_ARM_MACH_OMAP2_CM44XX_H
-#define __ARCH_ARM_MACH_OMAP2_CM44XX_H
-
-
-/* CM1 */
-
-/* CM1.OCP_SOCKET_CM1 register offsets */
-#define OMAP4_REVISION_CM1_OFFSET                       0x0000
-#define OMAP4430_REVISION_CM1                           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0000)
-#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET           0x0040
-#define OMAP4430_CM_CM1_PROFILING_CLKCTRL               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0040)
-
-/* CM1.CKGEN_CM1 register offsets */
-#define OMAP4_CM_CLKSEL_CORE_OFFSET                     0x0000
-#define OMAP4430_CM_CLKSEL_CORE                         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0000)
-#define OMAP4_CM_CLKSEL_ABE_OFFSET                      0x0008
-#define OMAP4430_CM_CLKSEL_ABE                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0008)
-#define OMAP4_CM_DLL_CTRL_OFFSET                        0x0010
-#define OMAP4430_CM_DLL_CTRL                            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0010)
-#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET               0x0020
-#define OMAP4430_CM_CLKMODE_DPLL_CORE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0020)
-#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET                0x0024
-#define OMAP4430_CM_IDLEST_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0024)
-#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET              0x0028
-#define OMAP4430_CM_AUTOIDLE_DPLL_CORE                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0028)
-#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET                0x002c
-#define OMAP4430_CM_CLKSEL_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x002c)
-#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET                0x0030
-#define OMAP4430_CM_DIV_M2_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0030)
-#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET                0x0034
-#define OMAP4430_CM_DIV_M3_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0034)
-#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET                0x0038
-#define OMAP4430_CM_DIV_M4_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0038)
-#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET                0x003c
-#define OMAP4430_CM_DIV_M5_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x003c)
-#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET                0x0040
-#define OMAP4430_CM_DIV_M6_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0040)
-#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET                0x0044
-#define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0044)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET        0x0048
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0048)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET        0x004c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x004c)
-#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET          0x0050
-#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0050)
-#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET                0x0060
-#define OMAP4430_CM_CLKMODE_DPLL_MPU                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0060)
-#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET                 0x0064
-#define OMAP4430_CM_IDLEST_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0064)
-#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET               0x0068
-#define OMAP4430_CM_AUTOIDLE_DPLL_MPU                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0068)
-#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET                 0x006c
-#define OMAP4430_CM_CLKSEL_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x006c)
-#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET                 0x0070
-#define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0070)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET         0x0088
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0088)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET         0x008c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x008c)
-#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET                 0x009c
-#define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x009c)
-#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET                0x00a0
-#define OMAP4430_CM_CLKMODE_DPLL_IVA                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a0)
-#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET                 0x00a4
-#define OMAP4430_CM_IDLEST_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a4)
-#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET               0x00a8
-#define OMAP4430_CM_AUTOIDLE_DPLL_IVA                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00a8)
-#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET                 0x00ac
-#define OMAP4430_CM_CLKSEL_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ac)
-#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET                 0x00b8
-#define OMAP4430_CM_DIV_M4_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00b8)
-#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET                 0x00bc
-#define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00bc)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET         0x00c8
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00c8)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET         0x00cc
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00cc)
-#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET                 0x00dc
-#define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00dc)
-#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET                0x00e0
-#define OMAP4430_CM_CLKMODE_DPLL_ABE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e0)
-#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET                 0x00e4
-#define OMAP4430_CM_IDLEST_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e4)
-#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET               0x00e8
-#define OMAP4430_CM_AUTOIDLE_DPLL_ABE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00e8)
-#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET                 0x00ec
-#define OMAP4430_CM_CLKSEL_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00ec)
-#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET                 0x00f0
-#define OMAP4430_CM_DIV_M2_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f0)
-#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET                 0x00f4
-#define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x00f4)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET         0x0108
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0108)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET         0x010c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x010c)
-#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET             0x0120
-#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0120)
-#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET              0x0124
-#define OMAP4430_CM_IDLEST_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0124)
-#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET            0x0128
-#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0128)
-#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET              0x012c
-#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x012c)
-#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET              0x0130
-#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0130)
-#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET              0x0138
-#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0138)
-#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET              0x013c
-#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x013c)
-#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET              0x0140
-#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0140)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET      0x0148
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0148)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET      0x014c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x014c)
-#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET             0x0160
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0160)
-#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET             0x0164
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG2                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0164)
-#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET                 0x0170
-#define OMAP4430_CM_DYN_DEP_PRESCAL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0170)
-#define OMAP4_CM_RESTORE_ST_OFFSET                      0x0180
-#define OMAP4430_CM_RESTORE_ST                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0180)
-
-/* CM1.MPU_CM1 register offsets */
-#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET                   0x0000
-#define OMAP4430_CM_MPU_CLKSTCTRL                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0000)
-#define OMAP4_CM_MPU_STATICDEP_OFFSET                   0x0004
-#define OMAP4430_CM_MPU_STATICDEP                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0004)
-#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET                  0x0008
-#define OMAP4430_CM_MPU_DYNAMICDEP                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0008)
-#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET                 0x0020
-#define OMAP4430_CM_MPU_MPU_CLKCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0020)
-
-/* CM1.TESLA_CM1 register offsets */
-#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET                 0x0000
-#define OMAP4430_CM_TESLA_CLKSTCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0000)
-#define OMAP4_CM_TESLA_STATICDEP_OFFSET                 0x0004
-#define OMAP4430_CM_TESLA_STATICDEP                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0004)
-#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET                0x0008
-#define OMAP4430_CM_TESLA_DYNAMICDEP                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0008)
-#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET             0x0020
-#define OMAP4430_CM_TESLA_TESLA_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_MOD, 0x0020)
-
-/* CM1.ABE_CM1 register offsets */
-#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET                  0x0000
-#define OMAP4430_CM1_ABE_CLKSTCTRL                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0000)
-#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET              0x0020
-#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0020)
-#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET               0x0028
-#define OMAP4430_CM1_ABE_AESS_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0028)
-#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET                0x0030
-#define OMAP4430_CM1_ABE_PDM_CLKCTRL                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0030)
-#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET               0x0038
-#define OMAP4430_CM1_ABE_DMIC_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0038)
-#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET              0x0040
-#define OMAP4430_CM1_ABE_MCASP_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0040)
-#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET             0x0048
-#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0048)
-#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET             0x0050
-#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0050)
-#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET             0x0058
-#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0058)
-#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET            0x0060
-#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0060)
-#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET             0x0068
-#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0068)
-#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET             0x0070
-#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0070)
-#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET             0x0078
-#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0078)
-#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET             0x0080
-#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0080)
-#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
-#define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
-
-/* CM1.RESTORE_CM1 register offsets */
-#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET             0x0000
-#define OMAP4430_CM_CLKSEL_CORE_RESTORE                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
-#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET        0x0004
-#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
-#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET        0x0008
-#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
-#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET        0x000c
-#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
-#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET        0x0010
-#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
-#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET        0x0014
-#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
-#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET        0x0018
-#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
-#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET        0x001c
-#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET        0x0020
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET        0x0024
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
-#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET       0x0028
-#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
-#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET     0x002c
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
-#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET     0x0030
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
-#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET      0x0034
-#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
-#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET           0x0038
-#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038)
-#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET   0x003c
-#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c)
-#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET         0x0040
-#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040)
-
-/* CM2 */
-
-/* CM2.OCP_SOCKET_CM2 register offsets */
-#define OMAP4_REVISION_CM2_OFFSET                       0x0000
-#define OMAP4430_REVISION_CM2                           OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0000)
-#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET           0x0040
-#define OMAP4430_CM_CM2_PROFILING_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0040)
-
-/* CM2.CKGEN_CM2 register offsets */
-#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET          0x0000
-#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0000)
-#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET                0x0004
-#define OMAP4430_CM_CLKSEL_USB_60MHZ                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0004)
-#define OMAP4_CM_SCALE_FCLK_OFFSET                      0x0008
-#define OMAP4430_CM_SCALE_FCLK                          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0008)
-#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET                 0x0010
-#define OMAP4430_CM_CORE_DVFS_PERF1                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0010)
-#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET                 0x0014
-#define OMAP4430_CM_CORE_DVFS_PERF2                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0014)
-#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET                 0x0018
-#define OMAP4430_CM_CORE_DVFS_PERF3                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0018)
-#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET                 0x001c
-#define OMAP4430_CM_CORE_DVFS_PERF4                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x001c)
-#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET               0x0024
-#define OMAP4430_CM_CORE_DVFS_CURRENT                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0024)
-#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET             0x0028
-#define OMAP4430_CM_IVA_DVFS_PERF_TESLA                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0028)
-#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET             0x002c
-#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x002c)
-#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET               0x0030
-#define OMAP4430_CM_IVA_DVFS_PERF_ABE                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0030)
-#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET                0x0038
-#define OMAP4430_CM_IVA_DVFS_CURRENT                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0038)
-#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET                0x0040
-#define OMAP4430_CM_CLKMODE_DPLL_PER                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0040)
-#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET                 0x0044
-#define OMAP4430_CM_IDLEST_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0044)
-#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET               0x0048
-#define OMAP4430_CM_AUTOIDLE_DPLL_PER                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0048)
-#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET                 0x004c
-#define OMAP4430_CM_CLKSEL_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x004c)
-#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET                 0x0050
-#define OMAP4430_CM_DIV_M2_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0050)
-#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET                 0x0054
-#define OMAP4430_CM_DIV_M3_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0054)
-#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET                 0x0058
-#define OMAP4430_CM_DIV_M4_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0058)
-#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET                 0x005c
-#define OMAP4430_CM_DIV_M5_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x005c)
-#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET                 0x0060
-#define OMAP4430_CM_DIV_M6_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0060)
-#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET                 0x0064
-#define OMAP4430_CM_DIV_M7_DPLL_PER                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0064)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET         0x0068
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET         0x006c
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
-#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET                0x0080
-#define OMAP4430_CM_CLKMODE_DPLL_USB                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
-#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET                 0x0084
-#define OMAP4430_CM_IDLEST_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0084)
-#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET               0x0088
-#define OMAP4430_CM_AUTOIDLE_DPLL_USB                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0088)
-#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET                 0x008c
-#define OMAP4430_CM_CLKSEL_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x008c)
-#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET                 0x0090
-#define OMAP4430_CM_DIV_M2_DPLL_USB                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0090)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET         0x00a8
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00a8)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET         0x00ac
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ac)
-#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET              0x00b4
-#define OMAP4430_CM_CLKDCOLDO_DPLL_USB                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00b4)
-#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET             0x00c0
-#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c0)
-#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET              0x00c4
-#define OMAP4430_CM_IDLEST_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c4)
-#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET            0x00c8
-#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00c8)
-#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET              0x00cc
-#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00cc)
-#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET              0x00d0
-#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00d0)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET      0x00e8
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00e8)
-#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET      0x00ec
-#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x00ec)
-
-/* CM2.ALWAYS_ON_CM2 register offsets */
-#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET                 0x0000
-#define OMAP4430_CM_ALWON_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0000)
-#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET           0x0020
-#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0020)
-#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET            0x0028
-#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0028)
-#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET            0x0030
-#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
-#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET           0x0038
-#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
-#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET            0x0040
-#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040)
-
-/* CM2.CORE_CM2 register offsets */
-#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET                  0x0000
-#define OMAP4430_CM_L3_1_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0000)
-#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET                 0x0008
-#define OMAP4430_CM_L3_1_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0008)
-#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET               0x0020
-#define OMAP4430_CM_L3_1_L3_1_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0020)
-#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET                  0x0100
-#define OMAP4430_CM_L3_2_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0100)
-#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET                 0x0108
-#define OMAP4430_CM_L3_2_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0108)
-#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET               0x0120
-#define OMAP4430_CM_L3_2_L3_2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0120)
-#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET               0x0128
-#define OMAP4430_CM_L3_2_GPMC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0128)
-#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET           0x0130
-#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0130)
-#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET                0x0200
-#define OMAP4430_CM_DUCATI_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0200)
-#define OMAP4_CM_DUCATI_STATICDEP_OFFSET                0x0204
-#define OMAP4430_CM_DUCATI_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0204)
-#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET               0x0208
-#define OMAP4430_CM_DUCATI_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0208)
-#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET           0x0220
-#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0220)
-#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET                  0x0300
-#define OMAP4430_CM_SDMA_CLKSTCTRL                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0300)
-#define OMAP4_CM_SDMA_STATICDEP_OFFSET                  0x0304
-#define OMAP4430_CM_SDMA_STATICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0304)
-#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET                 0x0308
-#define OMAP4430_CM_SDMA_DYNAMICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0308)
-#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET               0x0320
-#define OMAP4430_CM_SDMA_SDMA_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0320)
-#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET                 0x0400
-#define OMAP4430_CM_MEMIF_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0400)
-#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET               0x0420
-#define OMAP4430_CM_MEMIF_DMM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0420)
-#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET           0x0428
-#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0428)
-#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET            0x0430
-#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0430)
-#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET            0x0438
-#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0438)
-#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET               0x0440
-#define OMAP4430_CM_MEMIF_DLL_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0440)
-#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET           0x0450
-#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0450)
-#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET           0x0458
-#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0458)
-#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET             0x0460
-#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0460)
-#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET                   0x0500
-#define OMAP4430_CM_D2D_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0500)
-#define OMAP4_CM_D2D_STATICDEP_OFFSET                   0x0504
-#define OMAP4430_CM_D2D_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0504)
-#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET                  0x0508
-#define OMAP4430_CM_D2D_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0508)
-#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET               0x0520
-#define OMAP4430_CM_D2D_SAD2D_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0520)
-#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET           0x0528
-#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0528)
-#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET            0x0530
-#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0530)
-#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET                 0x0600
-#define OMAP4430_CM_L4CFG_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0600)
-#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET                0x0608
-#define OMAP4430_CM_L4CFG_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0608)
-#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET            0x0620
-#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0620)
-#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET            0x0628
-#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0628)
-#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET           0x0630
-#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0630)
-#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET           0x0638
-#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0638)
-#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET               0x0700
-#define OMAP4430_CM_L3INSTR_CLKSTCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0700)
-#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET            0x0720
-#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0720)
-#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET        0x0728
-#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0728)
-#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET         0x0740
-#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0740)
-
-/* CM2.IVAHD_CM2 register offsets */
-#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET                 0x0000
-#define OMAP4430_CM_IVAHD_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0000)
-#define OMAP4_CM_IVAHD_STATICDEP_OFFSET                 0x0004
-#define OMAP4430_CM_IVAHD_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0004)
-#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET                0x0008
-#define OMAP4430_CM_IVAHD_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0008)
-#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET             0x0020
-#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0020)
-#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET               0x0028
-#define OMAP4430_CM_IVAHD_SL2_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0028)
-
-/* CM2.CAM_CM2 register offsets */
-#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET                   0x0000
-#define OMAP4430_CM_CAM_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0000)
-#define OMAP4_CM_CAM_STATICDEP_OFFSET                   0x0004
-#define OMAP4430_CM_CAM_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0004)
-#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET                  0x0008
-#define OMAP4430_CM_CAM_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0008)
-#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET                 0x0020
-#define OMAP4430_CM_CAM_ISS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0020)
-#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET                0x0028
-#define OMAP4430_CM_CAM_FDIF_CLKCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0028)
-
-/* CM2.DSS_CM2 register offsets */
-#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET                   0x0000
-#define OMAP4430_CM_DSS_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0000)
-#define OMAP4_CM_DSS_STATICDEP_OFFSET                   0x0004
-#define OMAP4430_CM_DSS_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0004)
-#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET                  0x0008
-#define OMAP4430_CM_DSS_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0008)
-#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET                 0x0020
-#define OMAP4430_CM_DSS_DSS_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0020)
-#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET               0x0028
-#define OMAP4430_CM_DSS_DEISS_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0028)
 
-/* CM2.GFX_CM2 register offsets */
-#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET                   0x0000
-#define OMAP4430_CM_GFX_CLKSTCTRL                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0000)
-#define OMAP4_CM_GFX_STATICDEP_OFFSET                   0x0004
-#define OMAP4430_CM_GFX_STATICDEP                       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0004)
-#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET                  0x0008
-#define OMAP4430_CM_GFX_DYNAMICDEP                      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0008)
-#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET                 0x0020
-#define OMAP4430_CM_GFX_GFX_CLKCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0020)
+#include "prcm-common.h"
+#include "cm.h"
 
-/* CM2.L3INIT_CM2 register offsets */
-#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET                0x0000
-#define OMAP4430_CM_L3INIT_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0000)
-#define OMAP4_CM_L3INIT_STATICDEP_OFFSET                0x0004
-#define OMAP4430_CM_L3INIT_STATICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0004)
-#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET               0x0008
-#define OMAP4430_CM_L3INIT_DYNAMICDEP                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0008)
-#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET             0x0028
-#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0028)
-#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET             0x0030
-#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0030)
-#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET              0x0038
-#define OMAP4430_CM_L3INIT_HSI_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0038)
-#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET          0x0040
-#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0040)
-#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET         0x0058
-#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0058)
-#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET          0x0060
-#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0060)
-#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET          0x0068
-#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0068)
-#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET            0x0078
-#define OMAP4430_CM_L3INIT_P1500_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0078)
-#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET             0x0080
-#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0080)
-#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET             0x0088
-#define OMAP4430_CM_L3INIT_SATA_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0088)
-#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET            0x0090
-#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0090)
-#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET           0x0098
-#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0098)
-#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET            0x00a8
-#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00a8)
-#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET             0x00c0
-#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c0)
-#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET             0x00c8
-#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00c8)
-#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET      0x00d0
-#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL          OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00d0)
-#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET    0x00e0
-#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x00e0)
+#define OMAP4_CM_CLKSTCTRL                              0x0000
 
-/* CM2.L4PER_CM2 register offsets */
-#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET                 0x0000
-#define OMAP4430_CM_L4PER_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0000)
-#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET                0x0008
-#define OMAP4430_CM_L4PER_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0008)
-#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET               0x0020
-#define OMAP4430_CM_L4PER_ADC_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0020)
-#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET         0x0028
-#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0028)
-#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET         0x0030
-#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0030)
-#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET          0x0038
-#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0038)
-#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET          0x0040
-#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0040)
-#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET          0x0048
-#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0048)
-#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET          0x0050
-#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0050)
-#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET               0x0058
-#define OMAP4430_CM_L4PER_ELM_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0058)
-#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET             0x0060
-#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0060)
-#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET             0x0068
-#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0068)
-#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET             0x0070
-#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0070)
-#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET             0x0078
-#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0078)
-#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET             0x0080
-#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0080)
-#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET             0x0088
-#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0088)
-#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET             0x0090
-#define OMAP4430_CM_L4PER_HECC1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0090)
-#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET             0x0098
-#define OMAP4430_CM_L4PER_HECC2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0098)
-#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET              0x00a0
-#define OMAP4430_CM_L4PER_I2C1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a0)
-#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET              0x00a8
-#define OMAP4430_CM_L4PER_I2C2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00a8)
-#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET              0x00b0
-#define OMAP4430_CM_L4PER_I2C3_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b0)
-#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET              0x00b8
-#define OMAP4430_CM_L4PER_I2C4_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00b8)
-#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET             0x00c0
-#define OMAP4430_CM_L4PER_L4PER_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00c0)
-#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET            0x00d0
-#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d0)
-#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET            0x00d8
-#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00d8)
-#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET            0x00e0
-#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e0)
-#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET             0x00e8
-#define OMAP4430_CM_L4PER_MGATE_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00e8)
-#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET            0x00f0
-#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f0)
-#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET            0x00f8
-#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x00f8)
-#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET            0x0100
-#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0100)
-#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET            0x0108
-#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0108)
-#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET            0x0120
-#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0120)
-#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET            0x0128
-#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0128)
-#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET           0x0130
-#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0130)
-#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET          0x0138
-#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0138)
-#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET             0x0140
-#define OMAP4430_CM_L4PER_UART1_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0140)
-#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET             0x0148
-#define OMAP4430_CM_L4PER_UART2_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0148)
-#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET             0x0150
-#define OMAP4430_CM_L4PER_UART3_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0150)
-#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET             0x0158
-#define OMAP4430_CM_L4PER_UART4_CLKCTRL                 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0158)
-#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET            0x0160
-#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL                OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0160)
-#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET              0x0168
-#define OMAP4430_CM_L4PER_I2C5_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0168)
-#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET                 0x0180
-#define OMAP4430_CM_L4SEC_CLKSTCTRL                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0180)
-#define OMAP4_CM_L4SEC_STATICDEP_OFFSET                 0x0184
-#define OMAP4430_CM_L4SEC_STATICDEP                     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0184)
-#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET                0x0188
-#define OMAP4430_CM_L4SEC_DYNAMICDEP                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0188)
-#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET              0x01a0
-#define OMAP4430_CM_L4SEC_AES1_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a0)
-#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET              0x01a8
-#define OMAP4430_CM_L4SEC_AES2_CLKCTRL                  OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01a8)
-#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET           0x01b0
-#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b0)
-#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET          0x01b8
-#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01b8)
-#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET               0x01c0
-#define OMAP4430_CM_L4SEC_RNG_CLKCTRL                   OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c0)
-#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET          0x01c8
-#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01c8)
-#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET         0x01d8
-#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x01d8)
+/* Function prototypes */
+# ifndef __ASSEMBLER__
 
-/* CM2.CEFUSE_CM2 register offsets */
-#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET                0x0000
-#define OMAP4430_CM_CEFUSE_CLKSTCTRL                    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
-#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
-#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
+extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
 
-/* CM2.RESTORE_CM2 register offsets */
-#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET          0x0000
-#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
-#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET          0x0004
-#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
-#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET         0x0008
-#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
-#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET         0x000c
-#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
-#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET         0x0010
-#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
-#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET        0x0014
-#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
-#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET    0x0018
-#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE        OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
-#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET        0x001c
-#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE    OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
-#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
-#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
-#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET   0x0024
-#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
-#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET           0x0028
-#define OMAP4430_CM_D2D_STATICDEP_RESTORE               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
-#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET         0x002c
-#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
-#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET         0x0030
-#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE             OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
-#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET          0x0034
-#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
-#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET        0x0038
-#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
-#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET        0x003c
-#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE            OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
-#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET     0x0040
-#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
-#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET     0x0044
-#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044)
-#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET     0x0048
-#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048)
-#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET     0x004c
-#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c)
-#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET     0x0050
-#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE         OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050)
-#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
-#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE     OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054)
-#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET  0x0058
-#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE      OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058)
-#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET          0x005c
-#define OMAP4430_CM_SDMA_STATICDEP_RESTORE              OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c)
+# endif
 #endif
diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c
deleted file mode 100644
index f8a660a1a4a6..000000000000
--- a/arch/arm/mach-omap2/cm4xxx.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * OMAP4 CM module functions
- *
- * Copyright (C) 2009 Nokia Corporation
- * Paul Walmsley
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <asm/atomic.h>
-
-#include <plat/common.h>
-
-#include "cm.h"
-#include "cm-regbits-44xx.h"
-
-/**
- * omap4_cm_wait_module_ready - wait for a module to be in 'func' state
- * @clkctrl_reg: CLKCTRL module address
- *
- * Wait for the module IDLEST to be functional. If the idle state is in any
- * the non functional state (trans, idle or disabled), module and thus the
- * sysconfig cannot be accessed and will probably lead to an "imprecise
- * external abort"
- *
- * Module idle state:
- *   0x0 func:     Module is fully functional, including OCP
- *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
- *                 abortion
- *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
- *                 using separate functional clock
- *   0x3 disabled: Module is disabled and cannot be accessed
- *
- */
-int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
-{
-        int i = 0;
-
-        if (!clkctrl_reg)
-                return 0;
-
-        omap_test_timeout((
-                ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
-                 (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
-                  OMAP4430_IDLEST_SHIFT) == 0x2)),
-                MAX_MODULE_READY_TIME, i);
-
-        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
-}
-
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
new file mode 100644
index 000000000000..c04bbbea17a5
--- /dev/null
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -0,0 +1,214 @@
+/*
+ * OMAP4 CM instance functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1,
+ * or CM2 hardware modules.  For example, the EMU_CM CM instance is in
+ * the PRM hardware module.  What a mess...
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "cm.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+#include "cm44xx.h"
+#include "cminst44xx.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
+#include "prcm44xx.h"
+#include "prm44xx.h"
+#include "prcm_mpu44xx.h"
+
+static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
+        [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
+        [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
+        [OMAP4430_CM1_PARTITION]                = OMAP4430_CM1_BASE,
+        [OMAP4430_CM2_PARTITION]                = OMAP4430_CM2_BASE,
+        [OMAP4430_SCRM_PARTITION]               = 0,
+        [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
+};
+
+/* Read a register in a CM instance */
+u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
+{
+        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
+               part == OMAP4430_INVALID_PRCM_PARTITION ||
+               !_cm_bases[part]);
+        return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+}
+
+/* Write into a register in a CM instance */
+void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
+{
+        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
+               part == OMAP4430_INVALID_PRCM_PARTITION ||
+               !_cm_bases[part]);
+        __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+}
+
+/* Read-modify-write a register in CM1. Caller must lock */
+u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
+                                   s16 idx)
+{
+        u32 v;
+
+        v = omap4_cminst_read_inst_reg(part, inst, idx);
+        v &= ~mask;
+        v |= bits;
+        omap4_cminst_write_inst_reg(v, part, inst, idx);
+
+        return v;
+}
+
+/*
+ *
+ */
+
+/**
+ * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
+ * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
+ * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * @c must be the unshifted value for CLKTRCTRL - i.e., this function
+ * will handle the shift itself.
+ */
+static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
+{
+        u32 v;
+
+        v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
+        v &= ~OMAP4430_CLKTRCTRL_MASK;
+        v |= c << OMAP4430_CLKTRCTRL_SHIFT;
+        omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
+}
+
+/**
+ * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
+ * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
+ * is in hardware-supervised idle mode, or 0 otherwise.
+ */
+bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
+{
+        u32 v;
+
+        v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
+        v &= OMAP4430_CLKTRCTRL_MASK;
+        v >>= OMAP4430_CLKTRCTRL_SHIFT;
+
+        return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
+}
+
+/**
+ * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
+ * @part: PRCM partition ID that the clockdomain registers exist in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
+ * hardware-supervised idle mode.  No return value.
+ */
+void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
+}
+
+/**
+ * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
+ * @part: PRCM partition ID that the clockdomain registers exist in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
+ * software-supervised idle mode, i.e., controlled manually by the
+ * Linux OMAP clockdomain code.  No return value.
+ */
+void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
+}
+
+/**
+ * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle
+ * @part: PRCM partition ID that the clockdomain registers exist in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle
+ * No return value.
+ */
+void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
+}
+
+/**
+ * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
+ * @part: PRCM partition ID that the clockdomain registers exist in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
+ * waking it up.  No return value.
+ */
+void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
+}
+
+/*
+ *
+ */
+
+/**
+ * omap4_cm_wait_module_ready - wait for a module to be in 'func' state
+ * @clkctrl_reg: CLKCTRL module address
+ *
+ * Wait for the module IDLEST to be functional. If the idle state is in any
+ * the non functional state (trans, idle or disabled), module and thus the
+ * sysconfig cannot be accessed and will probably lead to an "imprecise
+ * external abort"
+ *
+ * Module idle state:
+ *   0x0 func:     Module is fully functional, including OCP
+ *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
+ *                 abortion
+ *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
+ *                 using separate functional clock
+ *   0x3 disabled: Module is disabled and cannot be accessed
+ *
+ */
+int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
+{
+        int i = 0;
+
+        if (!clkctrl_reg)
+                return 0;
+
+        omap_test_timeout((
+                ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
+                 (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
+                  OMAP4430_IDLEST_SHIFT) == 0x2)),
+                MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
new file mode 100644
index 000000000000..a6abd0a8cb82
--- /dev/null
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -0,0 +1,31 @@
+/*
+ * OMAP4 Clock Management (CM) function prototypes
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
+#define __ARCH_ASM_MACH_OMAP2_CMINST44XX_H
+
+extern bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
+extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
+
+/*
+ * In an ideal world, we would not export these low-level functions,
+ * but this will probably take some time to fix properly
+ */
+extern u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx);
+extern void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
+extern u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
+                                           s16 inst, s16 idx);
+
+extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
+
+#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1fa3294b6048..695279419020 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -20,12 +20,16 @@
 
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
-#include "cm.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
 #include "sdrc.h"
 #include "pm.h"
 #include "control.h"
 
+/* Used by omap3_ctrl_save_padconf() */
+#define START_PADCONF_SAVE              0x2
+#define PADCONF_SAVE_DONE               0x1
+
 static void __iomem *omap2_ctrl_base;
 static void __iomem *omap4_ctrl_pad_base;
 
@@ -134,6 +138,7 @@ struct omap3_control_regs {
         u32 sramldo4;
         u32 sramldo5;
         u32 csi;
+        u32 padconf_sys_nirq;
 };
 
 static struct omap3_control_regs control_context;
@@ -209,6 +214,37 @@ void omap4_ctrl_pad_writel(u32 val, u16 offset)
         __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
 }
 
+#ifdef CONFIG_ARCH_OMAP3
+
+/**
+ * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
+ * @bootmode: 8-bit value to pass to some boot code
+ *
+ * Set the bootmode in the scratchpad RAM.  This is used after the
+ * system restarts.  Not sure what actually uses this - it may be the
+ * bootloader, rather than the boot ROM - contrary to the preserved
+ * comment below.  No return value.
+ */
+void omap3_ctrl_write_boot_mode(u8 bootmode)
+{
+        u32 l;
+
+        l = ('B' << 24) | ('M' << 16) | bootmode;
+
+        /*
+         * Reserve the first word in scratchpad for communicating
+         * with the boot ROM. A pointer to a data structure
+         * describing the boot process can be stored there,
+         * cf. OMAP34xx TRM, Initialization / Software Booting
+         * Configuration.
+         *
+         * XXX This should use some omap_ctrl_writel()-type function
+         */
+        __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
+}
+
+#endif
+
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 /*
  * Clears the scratchpad contents in case of cold boot-
@@ -220,13 +256,13 @@ void omap3_clear_scratchpad_contents(void)
         void __iomem *v_addr;
         u32 offset = 0;
         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
-        if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
+        if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
             OMAP3430_GLOBAL_COLD_RST_MASK) {
                 for ( ; offset <= max_offset; offset += 0x4)
                         __raw_writel(0x0, (v_addr + offset));
-                prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
-                                     OMAP3430_GR_MOD,
-                                     OMAP3_PRM_RSTST_OFFSET);
+                omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
+                                           OMAP3430_GR_MOD,
+                                           OMAP3_PRM_RSTST_OFFSET);
         }
 }
 
@@ -239,9 +275,19 @@ void omap3_save_scratchpad_contents(void)
         struct omap3_scratchpad_prcm_block prcm_block_contents;
         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
 
-        /* Populate the Scratchpad contents */
+        /*
+         * Populate the Scratchpad contents
+         *
+         * The "get_*restore_pointer" functions are used to provide a
+         * physical restore address where the ROM code jumps while waking
+         * up from MPU OFF/OSWR state.
+         * The restore pointer is stored into the scratchpad.
+         */
         scratchpad_contents.boot_config_ptr = 0x0;
-        if (omap_rev() != OMAP3430_REV_ES3_0 &&
+        if (cpu_is_omap3630())
+                scratchpad_contents.public_restore_ptr =
+                        virt_to_phys(get_omap3630_restore_pointer());
+        else if (omap_rev() != OMAP3430_REV_ES3_0 &&
                                         omap_rev() != OMAP3430_REV_ES3_1)
                 scratchpad_contents.public_restore_ptr =
                         virt_to_phys(get_restore_pointer());
@@ -258,32 +304,34 @@ void omap3_save_scratchpad_contents(void)
         scratchpad_contents.sdrc_block_offset = 0x64;
 
         /* Populate the PRCM block contents */
-        prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
-                        OMAP3_PRM_CLKSRC_CTRL_OFFSET);
-        prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
-                        OMAP3_PRM_CLKSEL_OFFSET);
+        prcm_block_contents.prm_clksrc_ctrl =
+                omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
+                                       OMAP3_PRM_CLKSRC_CTRL_OFFSET);
+        prcm_block_contents.prm_clksel =
+                omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
+                                       OMAP3_PRM_CLKSEL_OFFSET);
         prcm_block_contents.cm_clksel_core =
-                        cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
+                        omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
         prcm_block_contents.cm_clksel_wkup =
-                        cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
+                        omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
         prcm_block_contents.cm_clken_pll =
-                        cm_read_mod_reg(PLL_MOD, CM_CLKEN);
+                        omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
         prcm_block_contents.cm_autoidle_pll =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
+                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
         prcm_block_contents.cm_clksel1_pll =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
+                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
         prcm_block_contents.cm_clksel2_pll =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
+                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
         prcm_block_contents.cm_clksel3_pll =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
+                        omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
         prcm_block_contents.cm_clken_pll_mpu =
-                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
+                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
         prcm_block_contents.cm_autoidle_pll_mpu =
-                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
+                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
         prcm_block_contents.cm_clksel1_pll_mpu =
-                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
+                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
         prcm_block_contents.cm_clksel2_pll_mpu =
-                        cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
+                        omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
         prcm_block_contents.prcm_block_size = 0x0;
 
         /* Populate the SDRC block contents */
@@ -416,6 +464,8 @@ void omap3_control_save_context(void)
         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
+        control_context.padconf_sys_nirq =
+                omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
         return;
 }
 
@@ -472,6 +522,43 @@ void omap3_control_restore_context(void)
         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
+        omap_ctrl_writel(control_context.padconf_sys_nirq,
+                         OMAP343X_CONTROL_PADCONF_SYSNIRQ);
         return;
 }
+
+void omap3630_ctrl_disable_rta(void)
+{
+        if (!cpu_is_omap3630())
+                return;
+        omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
+}
+
+/**
+ * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
+ *
+ * Tell the SCM to start saving the padconf registers, then wait for
+ * the process to complete.  Returns 0 unconditionally, although it
+ * should also eventually be able to return -ETIMEDOUT, if the save
+ * does not complete.
+ *
+ * XXX This function is missing a timeout.  What should it be?
+ */
+int omap3_ctrl_save_padconf(void)
+{
+        u32 cpo;
+
+        /* Save the padconf registers */
+        cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
+        cpo |= START_PADCONF_SAVE;
+        omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
+
+        /* wait for the save to complete */
+        while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
+                 & PADCONF_SAVE_DONE))
+                udelay(1);
+
+        return 0;
+}
+
 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b6c6b7c450b3..f0629ae04102 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -148,6 +148,15 @@
 #define OMAP343X_CONTROL_TEST_KEY_11    (OMAP2_CONTROL_GENERAL + 0x00f4)
 #define OMAP343X_CONTROL_TEST_KEY_12    (OMAP2_CONTROL_GENERAL + 0x00f8)
 #define OMAP343X_CONTROL_TEST_KEY_13    (OMAP2_CONTROL_GENERAL + 0x00fc)
+#define OMAP343X_CONTROL_FUSE_OPP1_VDD1 (OMAP2_CONTROL_GENERAL + 0x0110)
+#define OMAP343X_CONTROL_FUSE_OPP2_VDD1 (OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP343X_CONTROL_FUSE_OPP3_VDD1 (OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP343X_CONTROL_FUSE_OPP4_VDD1 (OMAP2_CONTROL_GENERAL + 0x011c)
+#define OMAP343X_CONTROL_FUSE_OPP5_VDD1 (OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP343X_CONTROL_FUSE_OPP1_VDD2 (OMAP2_CONTROL_GENERAL + 0x0124)
+#define OMAP343X_CONTROL_FUSE_OPP2_VDD2 (OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP343X_CONTROL_FUSE_OPP3_VDD2 (OMAP2_CONTROL_GENERAL + 0x012c)
+#define OMAP343X_CONTROL_FUSE_SR        (OMAP2_CONTROL_GENERAL + 0x0130)
 #define OMAP343X_CONTROL_IVA2_BOOTADDR  (OMAP2_CONTROL_GENERAL + 0x0190)
 #define OMAP343X_CONTROL_IVA2_BOOTMOD   (OMAP2_CONTROL_GENERAL + 0x0194)
 #define OMAP343X_CONTROL_DEBOBS(i)      (OMAP2_CONTROL_GENERAL + 0x01B0 \
@@ -164,6 +173,26 @@
 #define OMAP343X_CONTROL_SRAMLDO5       (OMAP2_CONTROL_GENERAL + 0x02C0)
 #define OMAP343X_CONTROL_CSI            (OMAP2_CONTROL_GENERAL + 0x02C4)
 
+/* OMAP3630 only CONTROL_GENERAL register offsets */
+#define OMAP3630_CONTROL_FUSE_OPP1G_VDD1        (OMAP2_CONTROL_GENERAL + 0x0110)
+#define OMAP3630_CONTROL_FUSE_OPP50_VDD1        (OMAP2_CONTROL_GENERAL + 0x0114)
+#define OMAP3630_CONTROL_FUSE_OPP100_VDD1       (OMAP2_CONTROL_GENERAL + 0x0118)
+#define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)
+#define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
+#define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
+
+/* OMAP44xx control efuse offsets */
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP50         0x22C
+#define OMAP44XX_CONTROL_FUSE_IVA_OPP100        0x22F
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO      0x232
+#define OMAP44XX_CONTROL_FUSE_IVA_OPPNITRO      0x235
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP50         0x240
+#define OMAP44XX_CONTROL_FUSE_MPU_OPP100        0x243
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO      0x246
+#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO      0x249
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP50        0x254
+#define OMAP44XX_CONTROL_FUSE_CORE_OPP100       0x257
+
 /* AM35XX only CONTROL_GENERAL register offsets */
 #define AM35XX_CONTROL_MSUSPENDMUX_6    (OMAP2_CONTROL_GENERAL + 0x0038)
 #define AM35XX_CONTROL_DEVCONF2         (OMAP2_CONTROL_GENERAL + 0x0310)
@@ -204,6 +233,10 @@
 #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
 #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
 
+/* 36xx-only RTA - Retention till Accesss control registers and bits */
+#define OMAP36XX_CONTROL_MEM_RTA_CTRL   0x40C
+#define OMAP36XX_RTA_DISABLE            0x0
+
 /* 34xx D2D idle-related pins, handled by PM core */
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
@@ -270,6 +303,8 @@
 #define OMAP343X_SCRATCHPAD_ROM         (OMAP343X_CTRL_BASE + 0x860)
 #define OMAP343X_SCRATCHPAD             (OMAP343X_CTRL_BASE + 0x910)
 #define OMAP343X_SCRATCHPAD_ROM_OFFSET  0x19C
+#define OMAP343X_SCRATCHPAD_REGADDR(reg)        OMAP2_L4_IO_ADDRESS(\
+                                                OMAP343X_SCRATCHPAD + reg)
 
 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
 #define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
@@ -309,7 +344,7 @@
 #define         FEAT_SGX_NONE           2
 
 #define OMAP3_IVA_SHIFT                 12
-#define OMAP3_IVA_MASK                  (1 << OMAP3_SGX_SHIFT)
+#define OMAP3_IVA_MASK                  (1 << OMAP3_IVA_SHIFT)
 #define         FEAT_IVA                0
 #define         FEAT_IVA_NONE           1
 
@@ -347,10 +382,13 @@ extern void omap3_save_scratchpad_contents(void);
 extern void omap3_clear_scratchpad_contents(void);
 extern u32 *get_restore_pointer(void);
 extern u32 *get_es3_restore_pointer(void);
+extern u32 *get_omap3630_restore_pointer(void);
 extern u32 omap3_arm_context[128];
 extern void omap3_control_save_context(void);
 extern void omap3_control_restore_context(void);
-
+extern void omap3_ctrl_write_boot_mode(u8 bootmode);
+extern void omap3630_ctrl_disable_rta(void);
+extern int omap3_ctrl_save_padconf(void);
 #else
 #define omap_ctrl_base_get()            0
 #define omap_ctrl_readb(x)              0
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index f9be4e3078bc..5bdfc443b77d 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -27,8 +27,8 @@
 
 #include <plat/prcm.h>
 #include <plat/irqs.h>
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
 #include <plat/serial.h>
 
 #include "pm.h"
@@ -295,25 +295,26 @@ select_state:
 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 
 /**
- * omap3_cpuidle_update_states - Update the cpuidle states.
+ * omap3_cpuidle_update_states() - Update the cpuidle states
+ * @mpu_deepest_state:  Enable states upto and including this for mpu domain
+ * @core_deepest_state: Enable states upto and including this for core domain
  *
- * Currently, this function toggles the validity of idle states based upon
- * the flag 'enable_off_mode'. When the flag is set all states are valid.
- * Else, states leading to OFF state set to be invalid.
+ * This goes through the list of states available and enables and disables the
+ * validity of C states based on deepest state that can be achieved for the
+ * variable domain
  */
-void omap3_cpuidle_update_states(void)
+void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
 {
         int i;
 
         for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
                 struct omap3_processor_cx *cx = &omap3_power_states[i];
 
-                if (enable_off_mode) {
+                if ((cx->mpu_state >= mpu_deepest_state) &&
+                    (cx->core_state >= core_deepest_state)) {
                         cx->valid = 1;
                 } else {
-                        if ((cx->mpu_state == PWRDM_POWER_OFF) ||
-                                (cx->core_state == PWRDM_POWER_OFF))
-                                cx->valid = 0;
+                        cx->valid = 0;
                 }
         }
 }
@@ -454,6 +455,18 @@ void omap_init_power_states(void)
         omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
         omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
                                 CPUIDLE_FLAG_CHECK_BM;
+
+        /*
+         * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
+         * enable OFF mode in a stable form for previous revisions.
+         * we disable C7 state as a result.
+         */
+        if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
+                omap3_power_states[OMAP3_STATE_C7].valid = 0;
+                cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
+                WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n",
+                                __func__);
+        }
 }
 
 struct cpuidle_driver omap3_idle_driver = {
@@ -506,7 +519,10 @@ int __init omap3_idle_init(void)
                 return -EINVAL;
         dev->state_count = count;
 
-        omap3_cpuidle_update_states();
+        if (enable_off_mode)
+                omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
+        else
+                omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
 
         if (cpuidle_register_device(dev)) {
                 printk(KERN_ERR "%s: CPUidle register device failed\n",
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 5a0c148e23bc..381f4eb92352 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -638,6 +638,7 @@ static struct platform_device dummy_pdev = {
 static void __init omap_hsmmc_reset(void)
 {
         u32 i, nr_controllers;
+        struct clk *iclk, *fclk;
 
         if (cpu_is_omap242x())
                 return;
@@ -647,7 +648,6 @@ static void __init omap_hsmmc_reset(void)
 
         for (i = 0; i < nr_controllers; i++) {
                 u32 v, base = 0;
-                struct clk *iclk, *fclk;
                 struct device *dev = &dummy_pdev.dev;
 
                 switch (i) {
@@ -678,19 +678,16 @@ static void __init omap_hsmmc_reset(void)
                 dummy_pdev.id = i;
                 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
                 iclk = clk_get(dev, "ick");
-                if (iclk && clk_enable(iclk))
-                        iclk = NULL;
+                if (IS_ERR(iclk))
+                        goto err1;
+                if (clk_enable(iclk))
+                        goto err2;
 
                 fclk = clk_get(dev, "fck");
-                if (fclk && clk_enable(fclk))
-                        fclk = NULL;
-
-                if (!iclk || !fclk) {
-                        printk(KERN_WARNING
-                               "%s: Unable to enable clocks for MMC%d, "
-                               "cannot reset.\n",  __func__, i);
-                        break;
-                }
+                if (IS_ERR(fclk))
+                        goto err3;
+                if (clk_enable(fclk))
+                        goto err4;
 
                 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
                 v = omap_readl(base + MMCHS_SYSSTATUS);
@@ -698,15 +695,22 @@ static void __init omap_hsmmc_reset(void)
                          MMCHS_SYSSTATUS_RESETDONE))
                         cpu_relax();
 
-                if (fclk) {
-                        clk_disable(fclk);
-                        clk_put(fclk);
-                }
-                if (iclk) {
-                        clk_disable(iclk);
-                        clk_put(iclk);
-                }
+                clk_disable(fclk);
+                clk_put(fclk);
+                clk_disable(iclk);
+                clk_put(iclk);
         }
+        return;
+
+err4:
+        clk_put(fclk);
+err3:
+        clk_disable(iclk);
+err2:
+        clk_put(iclk);
+err1:
+        printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
+                            "cannot reset.\n",  __func__, i);
 }
 #else
 static inline void omap_hsmmc_reset(void) {}
@@ -951,72 +955,12 @@ static inline void omap_init_vout(void) {}
 
 /*-------------------------------------------------------------------------*/
 
-/*
- * Inorder to avoid any assumptions from bootloader regarding WDT
- * settings, WDT module is reset during init. This enables the watchdog
- * timer. Hence it is required to disable the watchdog after the WDT reset
- * during init. Otherwise the system would reboot as per the default
- * watchdog timer registers settings.
- */
-#define OMAP_WDT_WPS    (0x34)
-#define OMAP_WDT_SPR    (0x48)
-
-static int omap2_disable_wdt(struct omap_hwmod *oh, void *unused)
-{
-        void __iomem *base;
-        int ret;
-
-        if (!oh) {
-                pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
-                return -EINVAL;
-        }
-
-        base = omap_hwmod_get_mpu_rt_va(oh);
-        if (!base) {
-                pr_err("%s: Could not get the base address for %s\n",
-                                oh->name, __func__);
-                return -EINVAL;
-        }
-
-        /* Enable the clocks before accessing the WDT registers */
-        ret = omap_hwmod_enable(oh);
-        if (ret) {
-                pr_err("%s: Could not enable clocks for %s\n",
-                                oh->name, __func__);
-                return ret;
-        }
-
-        /* sequence required to disable watchdog */
-        __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
-        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
-                cpu_relax();
-
-        __raw_writel(0x5555, base + OMAP_WDT_SPR);
-        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
-                cpu_relax();
-
-        ret = omap_hwmod_idle(oh);
-        if (ret)
-                pr_err("%s: Could not disable clocks for %s\n",
-                                oh->name, __func__);
-
-        return ret;
-}
-
-static void __init omap_disable_wdt(void)
-{
-        if (cpu_class_is_omap2())
-                omap_hwmod_for_each_by_class("wd_timer",
-                                                omap2_disable_wdt, NULL);
-        return;
-}
-
 static int __init omap2_init_devices(void)
 {
-        /* please keep these calls, and their implementations above,
+        /*
+         * please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
-        omap_disable_wdt();
         omap_hsmmc_reset();
         omap_init_audio();
         omap_init_camera();
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
new file mode 100644
index 000000000000..d2f15f5cfd36
--- /dev/null
+++ b/arch/arm/mach-omap2/dma.c
@@ -0,0 +1,297 @@
+/*
+ * OMAP2+ DMA driver
+ *
+ * Copyright (C) 2003 - 2008 Nokia Corporation
+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
+ * Graphics DMA and LCD DMA graphics tranformations
+ * by Imre Deak <imre.deak@nokia.com>
+ * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
+ * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Converted DMA library into platform driver
+ *      - G, Manjunath Kondaiah <manjugk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+#include <plat/dma.h>
+
+#define OMAP2_DMA_STRIDE        0x60
+
+static u32 errata;
+static u8 dma_stride;
+
+static struct omap_dma_dev_attr *d;
+
+static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
+
+static u16 reg_map[] = {
+        [REVISION]              = 0x00,
+        [GCR]                   = 0x78,
+        [IRQSTATUS_L0]          = 0x08,
+        [IRQSTATUS_L1]          = 0x0c,
+        [IRQSTATUS_L2]          = 0x10,
+        [IRQSTATUS_L3]          = 0x14,
+        [IRQENABLE_L0]          = 0x18,
+        [IRQENABLE_L1]          = 0x1c,
+        [IRQENABLE_L2]          = 0x20,
+        [IRQENABLE_L3]          = 0x24,
+        [SYSSTATUS]             = 0x28,
+        [OCP_SYSCONFIG]         = 0x2c,
+        [CAPS_0]                = 0x64,
+        [CAPS_2]                = 0x6c,
+        [CAPS_3]                = 0x70,
+        [CAPS_4]                = 0x74,
+
+        /* Common register offsets */
+        [CCR]                   = 0x80,
+        [CLNK_CTRL]             = 0x84,
+        [CICR]                  = 0x88,
+        [CSR]                   = 0x8c,
+        [CSDP]                  = 0x90,
+        [CEN]                   = 0x94,
+        [CFN]                   = 0x98,
+        [CSEI]                  = 0xa4,
+        [CSFI]                  = 0xa8,
+        [CDEI]                  = 0xac,
+        [CDFI]                  = 0xb0,
+        [CSAC]                  = 0xb4,
+        [CDAC]                  = 0xb8,
+
+        /* Channel specific register offsets */
+        [CSSA]                  = 0x9c,
+        [CDSA]                  = 0xa0,
+        [CCEN]                  = 0xbc,
+        [CCFN]                  = 0xc0,
+        [COLOR]                 = 0xc4,
+
+        /* OMAP4 specific registers */
+        [CDP]                   = 0xd0,
+        [CNDP]                  = 0xd4,
+        [CCDN]                  = 0xd8,
+};
+
+static struct omap_device_pm_latency omap2_dma_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+
+static void __iomem *dma_base;
+static inline void dma_write(u32 val, int reg, int lch)
+{
+        u8  stride;
+        u32 offset;
+
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+        __raw_writel(val, dma_base + offset);
+}
+
+static inline u32 dma_read(int reg, int lch)
+{
+        u8 stride;
+        u32 offset, val;
+
+        stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
+        offset = reg_map[reg] + (stride * lch);
+        val = __raw_readl(dma_base + offset);
+        return val;
+}
+
+static inline void omap2_disable_irq_lch(int lch)
+{
+        u32 val;
+
+        val = dma_read(IRQENABLE_L0, lch);
+        val &= ~(1 << lch);
+        dma_write(val, IRQENABLE_L0, lch);
+}
+
+static void omap2_clear_dma(int lch)
+{
+        int i = dma_common_ch_start;
+
+        for (; i <= dma_common_ch_end; i += 1)
+                dma_write(0, i, lch);
+}
+
+static void omap2_show_dma_caps(void)
+{
+        u8 revision = dma_read(REVISION, 0) & 0xff;
+        printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
+                                revision >> 4, revision & 0xf);
+        return;
+}
+
+static u32 configure_dma_errata(void)
+{
+
+        /*
+         * Errata applicable for OMAP2430ES1.0 and all omap2420
+         *
+         * I.
+         * Erratum ID: Not Available
+         * Inter Frame DMA buffering issue DMA will wrongly
+         * buffer elements if packing and bursting is enabled. This might
+         * result in data gets stalled in FIFO at the end of the block.
+         * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
+         * guarantee no data will stay in the DMA FIFO in case inter frame
+         * buffering occurs
+         *
+         * II.
+         * Erratum ID: Not Available
+         * DMA may hang when several channels are used in parallel
+         * In the following configuration, DMA channel hanging can occur:
+         * a. Channel i, hardware synchronized, is enabled
+         * b. Another channel (Channel x), software synchronized, is enabled.
+         * c. Channel i is disabled before end of transfer
+         * d. Channel i is reenabled.
+         * e. Steps 1 to 4 are repeated a certain number of times.
+         * f. A third channel (Channel y), software synchronized, is enabled.
+         * Channel x and Channel y may hang immediately after step 'f'.
+         * Workaround:
+         * For any channel used - make sure NextLCH_ID is set to the value j.
+         */
+        if (cpu_is_omap2420() || (cpu_is_omap2430() &&
+                                (omap_type() == OMAP2430_REV_ES1_0))) {
+
+                SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
+                SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
+        }
+
+        /*
+         * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
+         * after a transaction error.
+         * Workaround: SW should explicitely disable the channel.
+         */
+        if (cpu_class_is_omap2())
+                SET_DMA_ERRATA(DMA_ERRATA_i378);
+
+        /*
+         * Erratum ID: i541: sDMA FIFO draining does not finish
+         * If sDMA channel is disabled on the fly, sDMA enters standby even
+         * through FIFO Drain is still in progress
+         * Workaround: Put sDMA in NoStandby more before a logical channel is
+         * disabled, then put it back to SmartStandby right after the channel
+         * finishes FIFO draining.
+         */
+        if (cpu_is_omap34xx())
+                SET_DMA_ERRATA(DMA_ERRATA_i541);
+
+        /*
+         * Erratum ID: i88 : Special programming model needed to disable DMA
+         * before end of block.
+         * Workaround: software must ensure that the DMA is configured in No
+         * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
+         */
+        if (omap_type() == OMAP3430_REV_ES1_0)
+                SET_DMA_ERRATA(DMA_ERRATA_i88);
+
+        /*
+         * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
+         * read before the DMA controller finished disabling the channel.
+         */
+        SET_DMA_ERRATA(DMA_ERRATA_3_3);
+
+        /*
+         * Erratum ID: Not Available
+         * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+         * after secure sram context save and restore.
+         * Work around: Hence we need to manually clear those IRQs to avoid
+         * spurious interrupts. This affects only secure devices.
+         */
+        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+                SET_DMA_ERRATA(DMA_ROMCODE_BUG);
+
+        return errata;
+}
+
+/* One time initializations */
+static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
+{
+        struct omap_device                      *od;
+        struct omap_system_dma_plat_info        *p;
+        struct resource                         *mem;
+        char                                    *name = "omap_dma_system";
+
+        dma_stride              = OMAP2_DMA_STRIDE;
+        dma_common_ch_start     = CSDP;
+        if (cpu_is_omap3630() || cpu_is_omap4430())
+                dma_common_ch_end = CCDN;
+        else
+                dma_common_ch_end = CCFN;
+
+        p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
+        if (!p) {
+                pr_err("%s: Unable to allocate pdata for %s:%s\n",
+                        __func__, name, oh->name);
+                return -ENOMEM;
+        }
+
+        p->dma_attr             = (struct omap_dma_dev_attr *)oh->dev_attr;
+        p->disable_irq_lch      = omap2_disable_irq_lch;
+        p->show_dma_caps        = omap2_show_dma_caps;
+        p->clear_dma            = omap2_clear_dma;
+        p->dma_write            = dma_write;
+        p->dma_read             = dma_read;
+
+        p->clear_lch_regs       = NULL;
+
+        p->errata               = configure_dma_errata();
+
+        od = omap_device_build(name, 0, oh, p, sizeof(*p),
+                        omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
+        kfree(p);
+        if (IS_ERR(od)) {
+                pr_err("%s: Cant build omap_device for %s:%s.\n",
+                        __func__, name, oh->name);
+                return IS_ERR(od);
+        }
+
+        mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0);
+        if (!mem) {
+                dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__);
+                return -EINVAL;
+        }
+        dma_base = ioremap(mem->start, resource_size(mem));
+        if (!dma_base) {
+                dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__);
+                return -ENOMEM;
+        }
+
+        d = oh->dev_attr;
+        d->chan = kzalloc(sizeof(struct omap_dma_lch) *
+                                        (d->lch_count), GFP_KERNEL);
+
+        if (!d->chan) {
+                dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__);
+                return -ENOMEM;
+        }
+        return 0;
+}
+
+static int __init omap2_system_dma_init(void)
+{
+        return omap_hwmod_for_each_by_class("dma",
+                        omap2_system_dma_init_dev, NULL);
+}
+arch_initcall(omap2_system_dma_init);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index ed8d330522f1..f77022be783d 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -26,15 +26,13 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
+#include <linux/clkdev.h>
 
 #include <plat/cpu.h>
 #include <plat/clock.h>
-#include <asm/clkdev.h>
 
 #include "clock.h"
-#include "prm.h"
-#include "prm-regbits-34xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
@@ -225,10 +223,9 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
 }
 
 /**
- * lookup_dco_sddiv -  Set j-type DPLL4 compensation variables
+ * _lookup_dco - Lookup DCO used by j-type DPLL
  * @clk: pointer to a DPLL struct clk
  * @dco: digital control oscillator selector
- * @sd_div: target sigma-delta divider
  * @m: DPLL multiplier to set
  * @n: DPLL divider to set
  *
@@ -237,11 +234,9 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
  * XXX This code is not needed for 3430/AM35xx; can it be optimized
  * out in non-multi-OMAP builds for those chips?
  */
-static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m,
-                             u8 n)
+static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
 {
-        unsigned long fint, clkinp, sd; /* watch out for overflow */
-        int mod1, mod2;
+        unsigned long fint, clkinp; /* watch out for overflow */
 
         clkinp = clk->parent->rate;
         fint = (clkinp / n) * m;
@@ -250,6 +245,27 @@ static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m,
                 *dco = 2;
         else
                 *dco = 4;
+}
+
+/**
+ * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
+ * @clk: pointer to a DPLL struct clk
+ * @sd_div: target sigma-delta divider
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ *
+ * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
+ *
+ * XXX This code is not needed for 3430/AM35xx; can it be optimized
+ * out in non-multi-OMAP builds for those chips?
+ */
+static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
+{
+        unsigned long clkinp, sd; /* watch out for overflow */
+        int mod1, mod2;
+
+        clkinp = clk->parent->rate;
+
         /*
          * target sigma-delta to near 250MHz
          * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
@@ -278,6 +294,7 @@ static void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m,
 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
 {
         struct dpll_data *dd = clk->dpll_data;
+        u8 dco, sd_div;
         u32 v;
 
         /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
@@ -300,18 +317,16 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
         v |= m << __ffs(dd->mult_mask);
         v |= (n - 1) << __ffs(dd->div1_mask);
 
-        /*
-         * XXX This code is not needed for 3430/AM35XX; can it be optimized
-         * out in non-multi-OMAP builds for those chips?
-         */
-        if ((dd->flags & DPLL_J_TYPE) && !(dd->flags & DPLL_NO_DCO_SEL)) {
-                u8 dco, sd_div;
-                lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
-                /* XXX This probably will need revision for OMAP4 */
-                v &= ~(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK
-                        | OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
-                v |= dco << __ffs(OMAP3630_PERIPH_DPLL_DCO_SEL_MASK);
-                v |= sd_div << __ffs(OMAP3630_PERIPH_DPLL_SD_DIV_MASK);
+        /* Configure dco and sd_div for dplls that have these fields */
+        if (dd->dco_mask) {
+                _lookup_dco(clk, &dco, m, n);
+                v &= ~(dd->dco_mask);
+                v |= dco << __ffs(dd->dco_mask);
+        }
+        if (dd->sddiv_mask) {
+                _lookup_sddiv(clk, &sd_div, m, n);
+                v &= ~(dd->sddiv_mask);
+                v |= sd_div << __ffs(dd->sddiv_mask);
         }
 
         __raw_writel(v, dd->mult_div1_reg);
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 6feeeae6c21b..911cd2e68d46 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -11,9 +11,16 @@
  * published by the Free Software Foundation.
  */
 
+/*
+ * XXX The function pointers to the PRM/CM functions are incorrect and
+ * should be removed.  No device driver should be changing PRM/CM bits
+ * directly; that's a layering violation -- those bits are the responsibility
+ * of the OMAP PM core code.
+ */
+
 #include <linux/platform_device.h>
-#include "prm.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
 #ifdef CONFIG_BRIDGE_DVFS
 #include <plat/omap-pm.h>
 #endif
@@ -31,12 +38,12 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
         .cpu_set_freq = omap_pm_cpu_set_freq,
         .cpu_get_freq = omap_pm_cpu_get_freq,
 #endif
-        .dsp_prm_read = prm_read_mod_reg,
-        .dsp_prm_write = prm_write_mod_reg,
-        .dsp_prm_rmw_bits = prm_rmw_mod_reg_bits,
-        .dsp_cm_read = cm_read_mod_reg,
-        .dsp_cm_write = cm_write_mod_reg,
-        .dsp_cm_rmw_bits = cm_rmw_mod_reg_bits,
+        .dsp_prm_read = omap2_prm_read_mod_reg,
+        .dsp_prm_write = omap2_prm_write_mod_reg,
+        .dsp_prm_rmw_bits = omap2_prm_rmw_mod_reg_bits,
+        .dsp_cm_read = omap2_cm_read_mod_reg,
+        .dsp_cm_write = omap2_cm_write_mod_reg,
+        .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits,
 };
 
 static int __init omap_dsp_init(void)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
new file mode 100644
index 000000000000..413de18c1d2b
--- /dev/null
+++ b/arch/arm/mach-omap2/gpio.c
@@ -0,0 +1,104 @@
+/*
+ * OMAP2+ specific gpio initialization
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author:
+ *      Charulatha V <charu@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
+static struct omap_device_pm_latency omap_gpio_latency[] = {
+        [0] = {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
+
+static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
+{
+        struct omap_device *od;
+        struct omap_gpio_platform_data *pdata;
+        struct omap_gpio_dev_attr *dev_attr;
+        char *name = "omap_gpio";
+        int id;
+
+        /*
+         * extract the device id from name field available in the
+         * hwmod database and use the same for constructing ids for
+         * gpio devices.
+         * CAUTION: Make sure the name in the hwmod database does
+         * not change. If changed, make corresponding change here
+         * or make use of static variable mechanism to handle this.
+         */
+        sscanf(oh->name, "gpio%d", &id);
+
+        pdata = kzalloc(sizeof(struct omap_gpio_platform_data), GFP_KERNEL);
+        if (!pdata) {
+                pr_err("gpio%d: Memory allocation failed\n", id);
+                return -ENOMEM;
+        }
+
+        dev_attr = (struct omap_gpio_dev_attr *)oh->dev_attr;
+        pdata->bank_width = dev_attr->bank_width;
+        pdata->dbck_flag = dev_attr->dbck_flag;
+        pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
+
+        switch (oh->class->rev) {
+        case 0:
+        case 1:
+                pdata->bank_type = METHOD_GPIO_24XX;
+                break;
+        case 2:
+                pdata->bank_type = METHOD_GPIO_44XX;
+                break;
+        default:
+                WARN(1, "Invalid gpio bank_type\n");
+                kfree(pdata);
+                return -EINVAL;
+        }
+
+        od = omap_device_build(name, id - 1, oh, pdata,
+                                sizeof(*pdata), omap_gpio_latency,
+                                ARRAY_SIZE(omap_gpio_latency),
+                                false);
+        kfree(pdata);
+
+        if (IS_ERR(od)) {
+                WARN(1, "Cant build omap_device for %s:%s.\n",
+                                        name, oh->name);
+                return PTR_ERR(od);
+        }
+
+        gpio_bank_count++;
+        return 0;
+}
+
+/*
+ * gpio_init needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence gpio_init is a postcore_initcall.
+ */
+static int __init omap2_gpio_init(void)
+{
+        return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init,
+                                                NULL);
+}
+postcore_initcall(omap2_gpio_init);
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 722209601927..2bb29c160702 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -41,7 +41,7 @@ static int omap2_nand_gpmc_retime(void)
                 return 0;
 
         memset(&t, 0, sizeof(t));
-        t.sync_clk = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->sync_clk);
+        t.sync_clk = gpmc_nand_data->gpmc_t->sync_clk;
         t.cs_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->cs_on);
         t.adv_on = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->adv_on);
 
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 7bb69220adfa..3a7d25fb00ef 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -173,8 +173,17 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         }
 
         switch (freq) {
+        case 104:
+                min_gpmc_clk_period = 9600; /* 104 MHz */
+                t_ces   = 3;
+                t_avds  = 4;
+                t_avdh  = 2;
+                t_ach   = 3;
+                t_aavdh = 6;
+                t_rdyo  = 9;
+                break;
         case 83:
-                min_gpmc_clk_period = 12; /* 83 MHz */
+                min_gpmc_clk_period = 12000; /* 83 MHz */
                 t_ces   = 5;
                 t_avds  = 4;
                 t_avdh  = 2;
@@ -183,7 +192,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 t_rdyo  = 9;
                 break;
         case 66:
-                min_gpmc_clk_period = 15; /* 66 MHz */
+                min_gpmc_clk_period = 15000; /* 66 MHz */
                 t_ces   = 6;
                 t_avds  = 5;
                 t_avdh  = 2;
@@ -192,7 +201,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 t_rdyo  = 11;
                 break;
         default:
-                min_gpmc_clk_period = 18; /* 54 MHz */
+                min_gpmc_clk_period = 18500; /* 54 MHz */
                 t_ces   = 7;
                 t_avds  = 7;
                 t_avdh  = 7;
@@ -271,8 +280,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 t.wr_cycle  = t.rd_cycle;
                 if (cpu_is_omap34xx()) {
                         t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
-                                        gpmc_ns_to_ticks(min_gpmc_clk_period +
-                                        t_rdyo));
+                                        gpmc_ps_to_ticks(min_gpmc_clk_period +
+                                        t_rdyo * 1000));
                         t.wr_access = t.access;
                 }
         } else {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index f46933bc9373..1b7b3e7d02f7 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -168,6 +168,16 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 }
 
+unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
+{
+        unsigned long tick_ps;
+
+        /* Calculate in picosecs to yield more exact results */
+        tick_ps = gpmc_get_fclk_period();
+
+        return (time_ps + tick_ps - 1) / tick_ps;
+}
+
 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 {
         return ticks * gpmc_get_fclk_period() / 1000;
@@ -235,7 +245,7 @@ int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
         int div;
         u32 l;
 
-        l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
+        l = sync_clk + (gpmc_get_fclk_period() - 1);
         div = l / gpmc_get_fclk_period();
         if (div > 4)
                 return -1;
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 06e64e1fc28a..befa321c4c13 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -38,41 +38,27 @@
  */
 
 #ifdef MULTI_OMAP2
+
+/*
+ * We use __glue to avoid errors with multiple definitions of
+ * .globl omap_irq_base as it's included from entry-armv.S but not
+ * from entry-common.S.
+ */
+#ifdef __glue
                 .pushsection .data
-omap_irq_base:  .word   0
+                .globl  omap_irq_base
+omap_irq_base:
+                .word   0
                 .popsection
+#endif
 
-                /* Configure the interrupt base on the first interrupt */
+                /*
+                 * Configure the interrupt base on the first interrupt.
+                 * See also omap_irq_base_init for setting omap_irq_base.
+                 */
                 .macro  get_irqnr_preamble, base, tmp
-9:
                 ldr     \base, =omap_irq_base   @ irq base address
                 ldr     \base, [\base, #0]      @ irq base value
-                cmp     \base, #0               @ already configured?
-                bne     9997f                   @ nothing to do
-
-                mrc     p15, 0, \tmp, c0, c0, 0 @ get processor revision
-                and     \tmp, \tmp, #0x000f0000 @ only check architecture
-                cmp     \tmp, #0x00070000       @ is v6?
-                beq     2400f                   @ found v6 so it's omap24xx
-                mrc     p15, 0, \tmp, c0, c0, 0 @ get processor revision
-                and     \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9
-                cmp     \tmp, #0x00000080       @ cortex A-8?
-                beq     3400f                   @ found A-8 so it's omap34xx
-                cmp     \tmp, #0x00000090       @ cortex A-9?
-                beq     4400f                   @ found A-9 so it's omap44xx
-2400:           ldr     \base, =OMAP2_IRQ_BASE
-                ldr     \tmp, =omap_irq_base
-                str     \base, [\tmp, #0]
-                b       9b
-3400:           ldr     \base, =OMAP3_IRQ_BASE
-                ldr     \tmp, =omap_irq_base
-                str     \base, [\tmp, #0]
-                b       9b
-4400:           ldr     \base, =OMAP4_IRQ_BASE
-                ldr     \tmp, =omap_irq_base
-                str     \base, [\tmp, #0]
-                b       9b
-9997:
                 .endm
 
                 /* Check the pending interrupts. Note that base already set */
@@ -105,6 +91,35 @@ omap_irq_base:	.word	0
 9999:
                 .endm
 
+#ifdef CONFIG_SMP
+                /* We assume that irqstat (the raw value of the IRQ acknowledge
+                 * register) is preserved from the macro above.
+                 * If there is an IPI, we immediately signal end of interrupt
+                 * on the controller, since this requires the original irqstat
+                 * value which we won't easily be able to recreate later.
+                 */
+
+                .macro test_for_ipi, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                cmp     \irqnr, #16
+                it      cc
+                strcc   \irqstat, [\base, #GIC_CPU_EOI]
+                it      cs
+                cmpcs   \irqnr, \irqnr
+                .endm
+
+                /* As above, this assumes that irqstat and base are preserved */
+
+                .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #29
+                itt     eq
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
+                .endm
+#endif  /* CONFIG_SMP */
 
 #else   /* MULTI_OMAP2 */
 
@@ -141,74 +156,16 @@ omap_irq_base:	.word	0
 
 
 #ifdef CONFIG_ARCH_OMAP4
+#define HAVE_GET_IRQNR_PREAMBLE
+#include <asm/hardware/entry-macro-gic.S>
 
                 .macro  get_irqnr_preamble, base, tmp
                 ldr     \base, =OMAP4_IRQ_BASE
                 .endm
 
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an
-                 * interrupt if it's between 30 and 1020.  The test_for_ipi
-                 * routine below will pick up on IPIs.
-                 * A simple read from the controller will tell us the number
-                 * of the highest priority enabled interrupt.
-                 * We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-
-                ldr     \tmp, =1021
-
-                bic     \irqnr, \irqstat, #0x1c00
-
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                .endm
 #endif
-#endif  /* MULTI_OMAP2 */
-
-#ifdef CONFIG_SMP
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt
-                 * on the controller, since this requires the original irqstat
-                 * value which we won't easily be able to recreate later.
-                 */
 
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                it      cc
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                it      cs
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* As above, this assumes that irqstat and base are preserved */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                itt     eq
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
-#endif  /* CONFIG_SMP */
+#endif  /* MULTI_OMAP2 */
 
                 .macro  irq_prio_table
                 .endm
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index 2744dfee1ff4..5b0270b28934 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -24,7 +24,6 @@
 extern void __iomem *l2cache_base;
 #endif
 
-extern void __iomem *gic_cpu_base_addr;
 extern void __iomem *gic_dist_base_addr;
 
 extern void __init gic_init_irq(void);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index a1939b1e6f82..e66687b0b9de 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -39,13 +39,11 @@
 #include "io.h"
 
 #include <plat/omap-pm.h>
-#include <plat/powerdomain.h>
-#include "powerdomains.h"
-
-#include <plat/clockdomain.h>
-#include "clockdomains.h"
+#include "powerdomain.h"
 
+#include "clockdomain.h"
 #include <plat/omap_hwmod.h>
+#include <plat/multi.h>
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -311,24 +309,81 @@ static int __init _omap2_init_reprogram_sdrc(void)
         return v;
 }
 
-void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
-                                 struct omap_sdrc_params *sdrc_cs1)
+static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
+{
+        return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
+}
+
+/*
+ * Initialize asm_irq_base for entry-macro.S
+ */
+static inline void omap_irq_base_init(void)
+{
+        extern void __iomem *omap_irq_base;
+
+#ifdef MULTI_OMAP2
+        if (cpu_is_omap24xx())
+                omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
+        else if (cpu_is_omap34xx())
+                omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
+        else if (cpu_is_omap44xx())
+                omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
+        else
+                pr_err("Could not initialize omap_irq_base\n");
+#endif
+}
+
+void __init omap2_init_common_infrastructure(void)
 {
-        u8 skip_setup_idle = 0;
+        u8 postsetup_state;
 
-        pwrdm_init(powerdomains_omap);
-        clkdm_init(clockdomains_omap, clkdm_autodeps);
-        if (cpu_is_omap242x())
+        if (cpu_is_omap242x()) {
+                omap2xxx_powerdomains_init();
+                omap2_clockdomains_init();
                 omap2420_hwmod_init();
-        else if (cpu_is_omap243x())
+        } else if (cpu_is_omap243x()) {
+                omap2xxx_powerdomains_init();
+                omap2_clockdomains_init();
                 omap2430_hwmod_init();
-        else if (cpu_is_omap34xx())
+        } else if (cpu_is_omap34xx()) {
+                omap3xxx_powerdomains_init();
+                omap2_clockdomains_init();
                 omap3xxx_hwmod_init();
-        else if (cpu_is_omap44xx())
+        } else if (cpu_is_omap44xx()) {
+                omap44xx_powerdomains_init();
+                omap44xx_clockdomains_init();
                 omap44xx_hwmod_init();
+        } else {
+                pr_err("Could not init hwmod data - unknown SoC\n");
+        }
+
+        /* Set the default postsetup state for all hwmods */
+#ifdef CONFIG_PM_RUNTIME
+        postsetup_state = _HWMOD_STATE_IDLE;
+#else
+        postsetup_state = _HWMOD_STATE_ENABLED;
+#endif
+        omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
+
+        /*
+         * Set the default postsetup state for unusual modules (like
+         * MPU WDT).
+         *
+         * The postsetup_state is not actually used until
+         * omap_hwmod_late_init(), so boards that desire full watchdog
+         * coverage of kernel initialization can reprogram the
+         * postsetup_state between the calls to
+         * omap2_init_common_infra() and omap2_init_common_devices().
+         *
+         * XXX ideally we could detect whether the MPU WDT was currently
+         * enabled here and make this conditional
+         */
+        postsetup_state = _HWMOD_STATE_DISABLED;
+        omap_hwmod_for_each_by_class("wd_timer",
+                                     _set_hwmod_postsetup_state,
+                                     &postsetup_state);
 
-        /* The OPP tables have to be registered before a clk init */
-        omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
+        omap_pm_if_early_init();
 
         if (cpu_is_omap2420())
                 omap2420_clk_init();
@@ -339,17 +394,61 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
         else if (cpu_is_omap44xx())
                 omap4xxx_clk_init();
         else
-                pr_err("Could not init clock framework - unknown CPU\n");
+                pr_err("Could not init clock framework - unknown SoC\n");
+}
 
+void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+                                      struct omap_sdrc_params *sdrc_cs1)
+{
         omap_serial_early_init();
 
-#ifndef CONFIG_PM_RUNTIME
-        skip_setup_idle = 1;
-#endif
-        omap_hwmod_late_init(skip_setup_idle);
+        omap_hwmod_late_init();
+
         if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
                 _omap2_init_reprogram_sdrc();
         }
         gpmc_init();
+
+        omap_irq_base_init();
+}
+
+/*
+ * NOTE: Please use ioremap + __raw_read/write where possible instead of these
+ */
+
+u8 omap_readb(u32 pa)
+{
+        return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readb);
+
+u16 omap_readw(u32 pa)
+{
+        return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readw);
+
+u32 omap_readl(u32 pa)
+{
+        return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_readl);
+
+void omap_writeb(u8 v, u32 pa)
+{
+        __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writeb);
+
+void omap_writew(u16 v, u32 pa)
+{
+        __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
+}
+EXPORT_SYMBOL(omap_writew);
+
+void omap_writel(u32 v, u32 pa)
+{
+        __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
 }
+EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 32eeabe9d2ab..85bf8ca95fd3 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -284,7 +284,10 @@ void omap3_intc_suspend(void)
 
 void omap3_intc_prepare_idle(void)
 {
-        /* Disable autoidle as it can stall interrupt controller */
+        /*
+         * Disable autoidle as it can stall interrupt controller,
+         * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
+         */
         intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
 }
 
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 40ddecab93a9..394413dc7deb 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -281,7 +281,7 @@ static struct omap_mbox_ops omap2_mbox_ops = {
 
 /* FIXME: the following structs should be filled automatically by the user id */
 
-#if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420)
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
 /* DSP */
 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
         .tx_fifo = {
@@ -306,7 +306,7 @@ struct omap_mbox mbox_dsp_info = {
 };
 #endif
 
-#if defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_ARCH_OMAP3)
 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
 #endif
 
@@ -394,15 +394,19 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 
         if (false)
                 ;
-#if defined(CONFIG_ARCH_OMAP3430)
-        else if (cpu_is_omap3430()) {
+#if defined(CONFIG_ARCH_OMAP3)
+        else if (cpu_is_omap34xx()) {
                 list = omap3_mboxes;
 
                 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
         }
 #endif
-#if defined(CONFIG_ARCH_OMAP2420)
-        else if (cpu_is_omap2420()) {
+#if defined(CONFIG_ARCH_OMAP2)
+        else if (cpu_is_omap2430()) {
+                list = omap2_mboxes;
+
+                list[0]->irq = platform_get_irq_byname(pdev, "dsp");
+        } else if (cpu_is_omap2420()) {
                 list = omap2_mboxes;
 
                 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
@@ -432,9 +436,8 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
                 iounmap(mbox_base);
                 return ret;
         }
-        return 0;
 
-        return ret;
+        return 0;
 }
 
 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 074536ae401f..17bd6394d224 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,9 +1,9 @@
 /*
  * linux/arch/arm/mach-omap2/mux.c
  *
- * OMAP2 and OMAP3 pin multiplexing configurations
+ * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
  *
- * Copyright (C) 2004 - 2008 Texas Instruments Inc.
+ * Copyright (C) 2004 - 2010 Texas Instruments Inc.
  * Copyright (C) 2003 - 2008 Nokia Corporation
  *
  * Written by Tony Lindgren
@@ -35,65 +35,79 @@
 
 #include <asm/system.h>
 
+#include <plat/omap_hwmod.h>
+
 #include "control.h"
 #include "mux.h"
 
 #define OMAP_MUX_BASE_OFFSET            0x30    /* Offset from CTRL_BASE */
 #define OMAP_MUX_BASE_SZ                0x5ca
-#define MUXABLE_GPIO_MODE3              BIT(0)
 
 struct omap_mux_entry {
         struct omap_mux         mux;
         struct list_head        node;
 };
 
-static unsigned long mux_phys;
-static void __iomem *mux_base;
-static u8 omap_mux_flags;
+static LIST_HEAD(mux_partitions);
+static DEFINE_MUTEX(muxmode_mutex);
+
+struct omap_mux_partition *omap_mux_get(const char *name)
+{
+        struct omap_mux_partition *partition;
+
+        list_for_each_entry(partition, &mux_partitions, node) {
+                if (!strcmp(name, partition->name))
+                        return partition;
+        }
+
+        return NULL;
+}
 
-u16 omap_mux_read(u16 reg)
+u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
 {
-        if (cpu_is_omap24xx())
-                return __raw_readb(mux_base + reg);
+        if (partition->flags & OMAP_MUX_REG_8BIT)
+                return __raw_readb(partition->base + reg);
         else
-                return __raw_readw(mux_base + reg);
+                return __raw_readw(partition->base + reg);
 }
 
-void omap_mux_write(u16 val, u16 reg)
+void omap_mux_write(struct omap_mux_partition *partition, u16 val,
+                           u16 reg)
 {
-        if (cpu_is_omap24xx())
-                __raw_writeb(val, mux_base + reg);
+        if (partition->flags & OMAP_MUX_REG_8BIT)
+                __raw_writeb(val, partition->base + reg);
         else
-                __raw_writew(val, mux_base + reg);
+                __raw_writew(val, partition->base + reg);
 }
 
-void omap_mux_write_array(struct omap_board_mux *board_mux)
+void omap_mux_write_array(struct omap_mux_partition *partition,
+                                 struct omap_board_mux *board_mux)
 {
-        while (board_mux->reg_offset !=  OMAP_MUX_TERMINATOR) {
-                omap_mux_write(board_mux->value, board_mux->reg_offset);
+        while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
+                omap_mux_write(partition, board_mux->value,
+                               board_mux->reg_offset);
                 board_mux++;
         }
 }
 
-static LIST_HEAD(muxmodes);
-static DEFINE_MUTEX(muxmode_mutex);
-
 #ifdef CONFIG_OMAP_MUX
 
 static char *omap_mux_options;
 
-int __init omap_mux_init_gpio(int gpio, int val)
+static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
+                                      int gpio, int val)
 {
         struct omap_mux_entry *e;
         struct omap_mux *gpio_mux = NULL;
         u16 old_mode;
         u16 mux_mode;
         int found = 0;
+        struct list_head *muxmodes = &partition->muxmodes;
 
         if (!gpio)
                 return -EINVAL;
 
-        list_for_each_entry(e, &muxmodes, node) {
+        list_for_each_entry(e, muxmodes, node) {
                 struct omap_mux *m = &e->mux;
                 if (gpio == m->gpio) {
                         gpio_mux = m;
@@ -102,34 +116,52 @@ int __init omap_mux_init_gpio(int gpio, int val)
         }
 
         if (found == 0) {
-                printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
+                pr_err("%s: Could not set gpio%i\n", __func__, gpio);
                 return -ENODEV;
         }
 
         if (found > 1) {
-                printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n",
-                                found, gpio);
+                pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
+                        found, gpio);
                 return -EINVAL;
         }
 
-        old_mode = omap_mux_read(gpio_mux->reg_offset);
+        old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
         mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
-        if (omap_mux_flags & MUXABLE_GPIO_MODE3)
+        if (partition->flags & OMAP_MUX_GPIO_IN_MODE3)
                 mux_mode |= OMAP_MUX_MODE3;
         else
                 mux_mode |= OMAP_MUX_MODE4;
-        printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n",
-                        gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
-        omap_mux_write(mux_mode, gpio_mux->reg_offset);
+        pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
+                 gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
+        omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
 
         return 0;
 }
 
-int __init omap_mux_init_signal(const char *muxname, int val)
+int __init omap_mux_init_gpio(int gpio, int val)
+{
+        struct omap_mux_partition *partition;
+        int ret;
+
+        list_for_each_entry(partition, &mux_partitions, node) {
+                ret = _omap_mux_init_gpio(partition, gpio, val);
+                if (!ret)
+                        return ret;
+        }
+
+        return -ENODEV;
+}
+
+static int __init _omap_mux_get_by_name(struct omap_mux_partition *partition,
+                                        const char *muxname,
+                                        struct omap_mux **found_mux)
 {
+        struct omap_mux *mux = NULL;
         struct omap_mux_entry *e;
         const char *mode_name;
-        int found = 0, mode0_len = 0;
+        int found = 0, found_mode, mode0_len = 0;
+        struct list_head *muxmodes = &partition->muxmodes;
 
         mode_name = strchr(muxname, '.');
         if (mode_name) {
@@ -139,51 +171,200 @@ int __init omap_mux_init_signal(const char *muxname, int val)
                 mode_name = muxname;
         }
 
-        list_for_each_entry(e, &muxmodes, node) {
-                struct omap_mux *m = &e->mux;
-                char *m0_entry = m->muxnames[0];
+        list_for_each_entry(e, muxmodes, node) {
+                char *m0_entry;
                 int i;
 
+                mux = &e->mux;
+                m0_entry = mux->muxnames[0];
+
                 /* First check for full name in mode0.muxmode format */
                 if (mode0_len && strncmp(muxname, m0_entry, mode0_len))
                         continue;
 
                 /* Then check for muxmode only */
                 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
-                        char *mode_cur = m->muxnames[i];
+                        char *mode_cur = mux->muxnames[i];
 
                         if (!mode_cur)
                                 continue;
 
                         if (!strcmp(mode_name, mode_cur)) {
-                                u16 old_mode;
-                                u16 mux_mode;
-
-                                old_mode = omap_mux_read(m->reg_offset);
-                                mux_mode = val | i;
-                                printk(KERN_DEBUG "mux: Setting signal "
-                                        "%s.%s 0x%04x -> 0x%04x\n",
-                                        m0_entry, muxname, old_mode, mux_mode);
-                                omap_mux_write(mux_mode, m->reg_offset);
+                                *found_mux = mux;
                                 found++;
+                                found_mode = i;
                         }
                 }
         }
 
-        if (found == 1)
-                return 0;
+        if (found == 1) {
+                return found_mode;
+        }
 
         if (found > 1) {
-                printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
-                                found, muxname);
+                pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
+                       found, muxname);
                 return -EINVAL;
         }
 
-        printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
+        pr_err("%s: Could not find signal %s\n", __func__, muxname);
 
         return -ENODEV;
 }
 
+static int __init
+omap_mux_get_by_name(const char *muxname,
+                        struct omap_mux_partition **found_partition,
+                        struct omap_mux **found_mux)
+{
+        struct omap_mux_partition *partition;
+
+        list_for_each_entry(partition, &mux_partitions, node) {
+                struct omap_mux *mux = NULL;
+                int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux);
+                if (mux_mode < 0)
+                        continue;
+
+                *found_partition = partition;
+                *found_mux = mux;
+
+                return mux_mode;
+        }
+
+        return -ENODEV;
+}
+
+int __init omap_mux_init_signal(const char *muxname, int val)
+{
+        struct omap_mux_partition *partition = NULL;
+        struct omap_mux *mux = NULL;
+        u16 old_mode;
+        int mux_mode;
+
+        mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
+        if (mux_mode < 0)
+                return mux_mode;
+
+        old_mode = omap_mux_read(partition, mux->reg_offset);
+        mux_mode |= val;
+        pr_debug("%s: Setting signal %s 0x%04x -> 0x%04x\n",
+                         __func__, muxname, old_mode, mux_mode);
+        omap_mux_write(partition, mux_mode, mux->reg_offset);
+
+        return 0;
+}
+
+struct omap_hwmod_mux_info * __init
+omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
+{
+        struct omap_hwmod_mux_info *hmux;
+        int i;
+
+        if (!bpads || nr_pads < 1)
+                return NULL;
+
+        hmux = kzalloc(sizeof(struct omap_hwmod_mux_info), GFP_KERNEL);
+        if (!hmux)
+                goto err1;
+
+        hmux->nr_pads = nr_pads;
+
+        hmux->pads = kzalloc(sizeof(struct omap_device_pad) *
+                                nr_pads, GFP_KERNEL);
+        if (!hmux->pads)
+                goto err2;
+
+        for (i = 0; i < hmux->nr_pads; i++) {
+                struct omap_mux_partition *partition;
+                struct omap_device_pad *bpad = &bpads[i], *pad = &hmux->pads[i];
+                struct omap_mux *mux;
+                int mux_mode;
+
+                mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux);
+                if (mux_mode < 0)
+                        goto err3;
+                if (!pad->partition)
+                        pad->partition = partition;
+                if (!pad->mux)
+                        pad->mux = mux;
+
+                pad->name = kzalloc(strlen(bpad->name) + 1, GFP_KERNEL);
+                if (!pad->name) {
+                        int j;
+
+                        for (j = i - 1; j >= 0; j--)
+                                kfree(hmux->pads[j].name);
+                        goto err3;
+                }
+                strcpy(pad->name, bpad->name);
+
+                pad->flags = bpad->flags;
+                pad->enable = bpad->enable;
+                pad->idle = bpad->idle;
+                pad->off = bpad->off;
+                pr_debug("%s: Initialized %s\n", __func__, pad->name);
+        }
+
+        return hmux;
+
+err3:
+        kfree(hmux->pads);
+err2:
+        kfree(hmux);
+err1:
+        pr_err("%s: Could not allocate device mux entry\n", __func__);
+
+        return NULL;
+}
+
+/* Assumes the calling function takes care of locking */
+void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+{
+        int i;
+
+        for (i = 0; i < hmux->nr_pads; i++) {
+                struct omap_device_pad *pad = &hmux->pads[i];
+                int flags, val = -EINVAL;
+
+                flags = pad->flags;
+
+                switch (state) {
+                case _HWMOD_STATE_ENABLED:
+                        if (flags & OMAP_DEVICE_PAD_ENABLED)
+                                break;
+                        flags |= OMAP_DEVICE_PAD_ENABLED;
+                        val = pad->enable;
+                        pr_debug("%s: Enabling %s %x\n", __func__,
+                                        pad->name, val);
+                        break;
+                case _HWMOD_STATE_IDLE:
+                        if (!(flags & OMAP_DEVICE_PAD_REMUX))
+                                break;
+                        flags &= ~OMAP_DEVICE_PAD_ENABLED;
+                        val = pad->idle;
+                        pr_debug("%s: Idling %s %x\n", __func__,
+                                        pad->name, val);
+                        break;
+                case _HWMOD_STATE_DISABLED:
+                default:
+                        /* Use safe mode unless OMAP_DEVICE_PAD_REMUX */
+                        if (flags & OMAP_DEVICE_PAD_REMUX)
+                                val = pad->off;
+                        else
+                                val = OMAP_MUX_MODE7;
+                        flags &= ~OMAP_DEVICE_PAD_ENABLED;
+                        pr_debug("%s: Disabling %s %x\n", __func__,
+                                        pad->name, val);
+                };
+
+                if (val >= 0) {
+                        omap_mux_write(pad->partition, val,
+                                        pad->mux->reg_offset);
+                        pad->flags = flags;
+                }
+        }
+}
+
 #ifdef CONFIG_DEBUG_FS
 
 #define OMAP_MUX_MAX_NR_FLAGS   10
@@ -248,13 +429,15 @@ static inline void omap_mux_decode(struct seq_file *s, u16 val)
         } while (i-- > 0);
 }
 
-#define OMAP_MUX_DEFNAME_LEN    16
+#define OMAP_MUX_DEFNAME_LEN    32
 
 static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
 {
+        struct omap_mux_partition *partition = s->private;
         struct omap_mux_entry *e;
+        u8 omap_gen = omap_rev() >> 28;
 
-        list_for_each_entry(e, &muxmodes, node) {
+        list_for_each_entry(e, &partition->muxmodes, node) {
                 struct omap_mux *m = &e->mux;
                 char m0_def[OMAP_MUX_DEFNAME_LEN];
                 char *m0_name = m->muxnames[0];
@@ -272,11 +455,16 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
                         }
                         m0_def[i] = toupper(m0_name[i]);
                 }
-                val = omap_mux_read(m->reg_offset);
+                val = omap_mux_read(partition, m->reg_offset);
                 mode = val & OMAP_MUX_MODE7;
-
-                seq_printf(s, "OMAP%i_MUX(%s, ",
-                                        cpu_is_omap34xx() ? 3 : 0, m0_def);
+                if (mode != 0)
+                        seq_printf(s, "/* %s */\n", m->muxnames[mode]);
+
+                /*
+                 * XXX: Might be revisited to support differences accross
+                 * same OMAP generation.
+                 */
+                seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
                 omap_mux_decode(s, val);
                 seq_printf(s, "),\n");
         }
@@ -286,7 +474,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
 
 static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
 {
-        return single_open(file, omap_mux_dbg_board_show, &inode->i_private);
+        return single_open(file, omap_mux_dbg_board_show, inode->i_private);
 }
 
 static const struct file_operations omap_mux_dbg_board_fops = {
@@ -296,19 +484,43 @@ static const struct file_operations omap_mux_dbg_board_fops = {
         .release        = single_release,
 };
 
+static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
+{
+        struct omap_mux_partition *partition;
+
+        list_for_each_entry(partition, &mux_partitions, node) {
+                struct list_head *muxmodes = &partition->muxmodes;
+                struct omap_mux_entry *e;
+
+                list_for_each_entry(e, muxmodes, node) {
+                        struct omap_mux *m = &e->mux;
+
+                        if (m == mux)
+                                return partition;
+                }
+        }
+
+        return NULL;
+}
+
 static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
 {
         struct omap_mux *m = s->private;
+        struct omap_mux_partition *partition;
         const char *none = "NA";
         u16 val;
         int mode;
 
-        val = omap_mux_read(m->reg_offset);
+        partition = omap_mux_get_partition(m);
+        if (!partition)
+                return 0;
+
+        val = omap_mux_read(partition, m->reg_offset);
         mode = val & OMAP_MUX_MODE7;
 
-        seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n",
+        seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
                         m->muxnames[0], m->muxnames[mode],
-                        mux_phys + m->reg_offset, m->reg_offset, val,
+                        partition->phys + m->reg_offset, m->reg_offset, val,
                         m->balls[0] ? m->balls[0] : none,
                         m->balls[1] ? m->balls[1] : none);
         seq_printf(s, "mode: ");
@@ -330,14 +542,15 @@ static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
 #define OMAP_MUX_MAX_ARG_CHAR  7
 
 static ssize_t omap_mux_dbg_signal_write(struct file *file,
-                                                const char __user *user_buf,
-                                                size_t count, loff_t *ppos)
+                                         const char __user *user_buf,
+                                         size_t count, loff_t *ppos)
 {
         char buf[OMAP_MUX_MAX_ARG_CHAR];
         struct seq_file *seqf;
         struct omap_mux *m;
         unsigned long val;
         int buf_size, ret;
+        struct omap_mux_partition *partition;
 
         if (count > OMAP_MUX_MAX_ARG_CHAR)
                 return -EINVAL;
@@ -358,7 +571,11 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file,
         seqf = file->private_data;
         m = seqf->private;
 
-        omap_mux_write((u16)val, m->reg_offset);
+        partition = omap_mux_get_partition(m);
+        if (!partition)
+                return -ENODEV;
+
+        omap_mux_write(partition, (u16)val, m->reg_offset);
         *ppos += count;
 
         return count;
@@ -379,22 +596,38 @@ static const struct file_operations omap_mux_dbg_signal_fops = {
 
 static struct dentry *mux_dbg_dir;
 
-static void __init omap_mux_dbg_init(void)
+static void __init omap_mux_dbg_create_entry(
+                                struct omap_mux_partition *partition,
+                                struct dentry *mux_dbg_dir)
 {
         struct omap_mux_entry *e;
 
+        list_for_each_entry(e, &partition->muxmodes, node) {
+                struct omap_mux *m = &e->mux;
+
+                (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
+                                          m, &omap_mux_dbg_signal_fops);
+        }
+}
+
+static void __init omap_mux_dbg_init(void)
+{
+        struct omap_mux_partition *partition;
+        static struct dentry *mux_dbg_board_dir;
+
         mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
         if (!mux_dbg_dir)
                 return;
 
-        (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir,
-                                        NULL, &omap_mux_dbg_board_fops);
-
-        list_for_each_entry(e, &muxmodes, node) {
-                struct omap_mux *m = &e->mux;
+        mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
+        if (!mux_dbg_board_dir)
+                return;
 
-                (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
-                                        m, &omap_mux_dbg_signal_fops);
+        list_for_each_entry(partition, &mux_partitions, node) {
+                omap_mux_dbg_create_entry(partition, mux_dbg_dir);
+                (void)debugfs_create_file(partition->name, S_IRUGO,
+                                          mux_dbg_board_dir, partition,
+                                          &omap_mux_dbg_board_fops);
         }
 }
 
@@ -421,23 +654,25 @@ static void __init omap_mux_free_names(struct omap_mux *m)
 /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
 static int __init omap_mux_late_init(void)
 {
-        struct omap_mux_entry *e, *tmp;
+        struct omap_mux_partition *partition;
 
-        list_for_each_entry_safe(e, tmp, &muxmodes, node) {
-                struct omap_mux *m = &e->mux;
-                u16 mode = omap_mux_read(m->reg_offset);
+        list_for_each_entry(partition, &mux_partitions, node) {
+                struct omap_mux_entry *e, *tmp;
+                list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
+                        struct omap_mux *m = &e->mux;
+                        u16 mode = omap_mux_read(partition, m->reg_offset);
 
-                if (OMAP_MODE_GPIO(mode))
-                        continue;
+                        if (OMAP_MODE_GPIO(mode))
+                                continue;
 
 #ifndef CONFIG_DEBUG_FS
-                mutex_lock(&muxmode_mutex);
-                list_del(&e->node);
-                mutex_unlock(&muxmode_mutex);
-                omap_mux_free_names(m);
-                kfree(m);
+                        mutex_lock(&muxmode_mutex);
+                        list_del(&e->node);
+                        mutex_unlock(&muxmode_mutex);
+                        omap_mux_free_names(m);
+                        kfree(m);
 #endif
-
+                }
         }
 
         omap_mux_dbg_init();
@@ -462,8 +697,8 @@ static void __init omap_mux_package_fixup(struct omap_mux *p,
                         s++;
                 }
                 if (!found)
-                        printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
-                                        p->reg_offset);
+                        pr_err("%s: Unknown entry offset 0x%x\n", __func__,
+                               p->reg_offset);
                 p++;
         }
 }
@@ -487,8 +722,8 @@ static void __init omap_mux_package_init_balls(struct omap_ball *b,
                         s++;
                 }
                 if (!found)
-                        printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
-                                        b->reg_offset);
+                        pr_err("%s: Unknown ball offset 0x%x\n", __func__,
+                               b->reg_offset);
                 b++;
         }
 }
@@ -554,7 +789,7 @@ static void __init omap_mux_set_cmdline_signals(void)
 }
 
 static int __init omap_mux_copy_names(struct omap_mux *src,
-                                        struct omap_mux *dst)
+                                      struct omap_mux *dst)
 {
         int i;
 
@@ -592,51 +827,63 @@ free:
 
 #endif  /* CONFIG_OMAP_MUX */
 
-static u16 omap_mux_get_by_gpio(int gpio)
+static struct omap_mux *omap_mux_get_by_gpio(
+                                struct omap_mux_partition *partition,
+                                int gpio)
 {
         struct omap_mux_entry *e;
-        u16 offset = OMAP_MUX_TERMINATOR;
+        struct omap_mux *ret = NULL;
 
-        list_for_each_entry(e, &muxmodes, node) {
+        list_for_each_entry(e, &partition->muxmodes, node) {
                 struct omap_mux *m = &e->mux;
                 if (m->gpio == gpio) {
-                        offset = m->reg_offset;
+                        ret = m;
                         break;
                 }
         }
 
-        return offset;
+        return ret;
 }
 
 /* Needed for dynamic muxing of GPIO pins for off-idle */
 u16 omap_mux_get_gpio(int gpio)
 {
-        u16 offset;
+        struct omap_mux_partition *partition;
+        struct omap_mux *m;
 
-        offset = omap_mux_get_by_gpio(gpio);
-        if (offset == OMAP_MUX_TERMINATOR) {
-                printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
-                return offset;
+        list_for_each_entry(partition, &mux_partitions, node) {
+                m = omap_mux_get_by_gpio(partition, gpio);
+                if (m)
+                        return omap_mux_read(partition, m->reg_offset);
         }
 
-        return omap_mux_read(offset);
+        if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
+                pr_err("%s: Could not get gpio%i\n", __func__, gpio);
+
+        return OMAP_MUX_TERMINATOR;
 }
 
 /* Needed for dynamic muxing of GPIO pins for off-idle */
 void omap_mux_set_gpio(u16 val, int gpio)
 {
-        u16 offset;
+        struct omap_mux_partition *partition;
+        struct omap_mux *m = NULL;
 
-        offset = omap_mux_get_by_gpio(gpio);
-        if (offset == OMAP_MUX_TERMINATOR) {
-                printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
-                return;
+        list_for_each_entry(partition, &mux_partitions, node) {
+                m = omap_mux_get_by_gpio(partition, gpio);
+                if (m) {
+                        omap_mux_write(partition, val, m->reg_offset);
+                        return;
+                }
         }
 
-        omap_mux_write(val, offset);
+        if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
+                pr_err("%s: Could not set gpio%i\n", __func__, gpio);
 }
 
-static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
+static struct omap_mux * __init omap_mux_list_add(
+                                        struct omap_mux_partition *partition,
+                                        struct omap_mux *src)
 {
         struct omap_mux_entry *entry;
         struct omap_mux *m;
@@ -656,7 +903,7 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
 #endif
 
         mutex_lock(&muxmode_mutex);
-        list_add_tail(&entry->node, &muxmodes);
+        list_add_tail(&entry->node, &partition->muxmodes);
         mutex_unlock(&muxmode_mutex);
 
         return m;
@@ -667,7 +914,8 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
  * the GPIO to mux offset mapping that is needed for dynamic muxing
  * of GPIO pins for off-idle.
  */
-static void __init omap_mux_init_list(struct omap_mux *superset)
+static void __init omap_mux_init_list(struct omap_mux_partition *partition,
+                                      struct omap_mux *superset)
 {
         while (superset->reg_offset !=  OMAP_MUX_TERMINATOR) {
                 struct omap_mux *entry;
@@ -679,15 +927,16 @@ static void __init omap_mux_init_list(struct omap_mux *superset)
                 }
 #else
                 /* Skip pins that are not muxed as GPIO by bootloader */
-                if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
+                if (!OMAP_MODE_GPIO(omap_mux_read(partition,
+                                    superset->reg_offset))) {
                         superset++;
                         continue;
                 }
 #endif
 
-                entry = omap_mux_list_add(superset);
+                entry = omap_mux_list_add(partition, superset);
                 if (!entry) {
-                        printk(KERN_ERR "mux: Could not add entry\n");
+                        pr_err("%s: Could not add entry\n", __func__);
                         return;
                 }
                 superset++;
@@ -706,10 +955,11 @@ static void omap_mux_init_package(struct omap_mux *superset,
                 omap_mux_package_init_balls(package_balls, superset);
 }
 
-static void omap_mux_init_signals(struct omap_board_mux *board_mux)
+static void omap_mux_init_signals(struct omap_mux_partition *partition,
+                                  struct omap_board_mux *board_mux)
 {
         omap_mux_set_cmdline_signals();
-        omap_mux_write_array(board_mux);
+        omap_mux_write_array(partition, board_mux);
 }
 
 #else
@@ -720,34 +970,49 @@ static void omap_mux_init_package(struct omap_mux *superset,
 {
 }
 
-static void omap_mux_init_signals(struct omap_board_mux *board_mux)
+static void omap_mux_init_signals(struct omap_mux_partition *partition,
+                                  struct omap_board_mux *board_mux)
 {
 }
 
 #endif
 
-int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
-                                struct omap_mux *superset,
-                                struct omap_mux *package_subset,
-                                struct omap_board_mux *board_mux,
-                                struct omap_ball *package_balls)
-{
-        if (mux_base)
-                return -EBUSY;
+static u32 mux_partitions_cnt;
 
-        mux_phys = mux_pbase;
-        mux_base = ioremap(mux_pbase, mux_size);
-        if (!mux_base) {
-                printk(KERN_ERR "mux: Could not ioremap\n");
+int __init omap_mux_init(const char *name, u32 flags,
+                         u32 mux_pbase, u32 mux_size,
+                         struct omap_mux *superset,
+                         struct omap_mux *package_subset,
+                         struct omap_board_mux *board_mux,
+                         struct omap_ball *package_balls)
+{
+        struct omap_mux_partition *partition;
+
+        partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
+        if (!partition)
+                return -ENOMEM;
+
+        partition->name = name;
+        partition->flags = flags;
+        partition->size = mux_size;
+        partition->phys = mux_pbase;
+        partition->base = ioremap(mux_pbase, mux_size);
+        if (!partition->base) {
+                pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
+                        __func__, partition->phys);
                 return -ENODEV;
         }
 
-        if (cpu_is_omap24xx())
-                omap_mux_flags = MUXABLE_GPIO_MODE3;
+        INIT_LIST_HEAD(&partition->muxmodes);
+
+        list_add_tail(&partition->node, &mux_partitions);
+        mux_partitions_cnt++;
+        pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
+                mux_partitions_cnt, partition->name, partition->flags);
 
         omap_mux_init_package(superset, package_subset, package_balls);
-        omap_mux_init_list(superset);
-        omap_mux_init_signals(board_mux);
+        omap_mux_init_list(partition, superset);
+        omap_mux_init_signals(partition, board_mux);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 350c04f27383..a4ab17a737a6 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2009 Nokia
- * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2009-2010 Texas Instruments
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -10,6 +10,7 @@
 #include "mux2420.h"
 #include "mux2430.h"
 #include "mux34xx.h"
+#include "mux44xx.h"
 
 #define OMAP_MUX_TERMINATOR     0xffff
 
@@ -37,6 +38,9 @@
 #define OMAP_OFF_PULL_UP                (1 << 13)
 #define OMAP_WAKEUP_EN                  (1 << 14)
 
+/* 44xx specific mux bit defines */
+#define OMAP_WAKEUP_EVENT               (1 << 15)
+
 /* Active pin states */
 #define OMAP_PIN_OUTPUT                 0
 #define OMAP_PIN_INPUT                  OMAP_INPUT_EN
@@ -56,8 +60,10 @@
 
 #define OMAP_MODE_GPIO(x)       (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
 
-/* Flags for omap_mux_init */
+/* Flags for omapX_mux_init */
 #define OMAP_PACKAGE_MASK               0xffff
+#define OMAP_PACKAGE_CBS                8               /* 547-pin 0.40 0.40 */
+#define OMAP_PACKAGE_CBL                7               /* 547-pin 0.40 0.40 */
 #define OMAP_PACKAGE_CBP                6               /* 515-pin 0.40 0.50 */
 #define OMAP_PACKAGE_CUS                5               /* 423-pin 0.65 */
 #define OMAP_PACKAGE_CBB                4               /* 515-pin 0.40 0.50 */
@@ -66,14 +72,61 @@
 #define OMAP_PACKAGE_ZAF                1               /* 2420 447-pin SIP */
 
 
-#define OMAP_MUX_NR_MODES       8                       /* Available modes */
-#define OMAP_MUX_NR_SIDES       2                       /* Bottom & top */
+#define OMAP_MUX_NR_MODES               8               /* Available modes */
+#define OMAP_MUX_NR_SIDES               2               /* Bottom & top */
+
+/*
+ * omap_mux_init flags definition:
+ *
+ * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
+ * The default value is 16 bits.
+ * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3.
+ * The default is mode4.
+ */
+#define OMAP_MUX_REG_8BIT               (1 << 0)
+#define OMAP_MUX_GPIO_IN_MODE3          (1 << 1)
+
+/**
+ * struct omap_board_data - board specific device data
+ * @id: instance id
+ * @flags: additional flags for platform init code
+ * @pads: array of device specific pads
+ * @pads_cnt: ARRAY_SIZE() of pads
+ */
+struct omap_board_data {
+        int                     id;
+        u32                     flags;
+        struct omap_device_pad  *pads;
+        int                     pads_cnt;
+};
+
+/**
+ * struct mux_partition - contain partition related information
+ * @name: name of the current partition
+ * @flags: flags specific to this partition
+ * @phys: physical address
+ * @size: partition size
+ * @base: virtual address after ioremap
+ * @muxmodes: list of nodes that belong to a partition
+ * @node: list node for the partitions linked list
+ */
+struct omap_mux_partition {
+        const char              *name;
+        u32                     flags;
+        u32                     phys;
+        u32                     size;
+        void __iomem            *base;
+        struct list_head        muxmodes;
+        struct list_head        node;
+};
 
 /**
  * struct omap_mux - data for omap mux register offset and it's value
  * @reg_offset: mux register offset from the mux base
  * @gpio:       GPIO number
  * @muxnames:   available signal modes for a ball
+ * @balls:      available balls on the package
+ * @partition:  mux partition
  */
 struct omap_mux {
         u16     reg_offset;
@@ -106,6 +159,34 @@ struct omap_board_mux {
         u16     value;
 };
 
+#define OMAP_DEVICE_PAD_ENABLED         BIT(7)  /* Not needed for board-*.c */
+#define OMAP_DEVICE_PAD_REMUX           BIT(1)  /* Dynamically remux a pad,
+                                                   needs enable, idle and off
+                                                   values */
+#define OMAP_DEVICE_PAD_WAKEUP          BIT(0)  /* Pad is wake-up capable */
+
+/**
+ * struct omap_device_pad - device specific pad configuration
+ * @name:               signal name
+ * @flags:              pad specific runtime flags
+ * @enable:             runtime value for a pad
+ * @idle:               idle value for a pad
+ * @off:                off value for a pad, defaults to safe mode
+ * @partition:          mux partition
+ * @mux:                mux register
+ */
+struct omap_device_pad {
+        char                            *name;
+        u8                              flags;
+        u16                             enable;
+        u16                             idle;
+        u16                             off;
+        struct omap_mux_partition       *partition;
+        struct omap_mux                 *mux;
+};
+
+struct omap_hwmod_mux_info;
+
 #if defined(CONFIG_OMAP_MUX)
 
 /**
@@ -122,6 +203,23 @@ int omap_mux_init_gpio(int gpio, int val);
  */
 int omap_mux_init_signal(const char *muxname, int val);
 
+/**
+ * omap_hwmod_mux_init - initialize hwmod specific mux data
+ * @bpads:              Board specific device signal names
+ * @nr_pads:            Number of signal names for the device
+ */
+extern struct omap_hwmod_mux_info *
+omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads);
+
+/**
+ * omap_hwmod_mux - omap hwmod specific pin muxing
+ * @hmux:               Pads for a hwmod
+ * @state:              Desired _HWMOD_STATE
+ *
+ * Called only from omap_hwmod.c, do not use.
+ */
+void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state);
+
 #else
 
 static inline int omap_mux_init_gpio(int gpio, int val)
@@ -133,6 +231,18 @@ static inline int omap_mux_init_signal(char *muxname, int val)
         return 0;
 }
 
+static inline struct omap_hwmod_mux_info *
+omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
+{
+        return NULL;
+}
+
+static inline void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
+{
+}
+
+static struct omap_board_mux *board_mux __initdata __maybe_unused;
+
 #endif
 
 /**
@@ -151,28 +261,39 @@ u16 omap_mux_get_gpio(int gpio);
 void omap_mux_set_gpio(u16 val, int gpio);
 
 /**
+ * omap_mux_get() - get a mux partition by name
+ * @name:               Name of the mux partition
+ *
+ */
+struct omap_mux_partition *omap_mux_get(const char *name);
+
+/**
  * omap_mux_read() - read mux register
+ * @partition:          Mux partition
  * @mux_offset:         Offset of the mux register
  *
  */
-u16 omap_mux_read(u16 mux_offset);
+u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
 
 /**
  * omap_mux_write() - write mux register
+ * @partition:          Mux partition
  * @val:                New mux register value
  * @mux_offset:         Offset of the mux register
  *
  * This should be only needed for dynamic remuxing of non-gpio signals.
  */
-void omap_mux_write(u16 val, u16 mux_offset);
+void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
 
 /**
  * omap_mux_write_array() - write an array of mux registers
+ * @partition:          Mux partition
  * @board_mux:          Array of mux registers terminated by MAP_MUX_TERMINATOR
  *
  * This should be only needed for dynamic remuxing of non-gpio signals.
  */
-void omap_mux_write_array(struct omap_board_mux *board_mux);
+void omap_mux_write_array(struct omap_mux_partition *p,
+                          struct omap_board_mux *board_mux);
 
 /**
  * omap2420_mux_init() - initialize mux system with board specific set
@@ -196,10 +317,19 @@ int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
 int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
 
 /**
+ * omap4_mux_init() - initialize mux system with board specific set
+ * @board_mux:          Board specific mux table
+ * @flags:              OMAP package type used for the board
+ */
+int omap4_mux_init(struct omap_board_mux *board_mux, int flags);
+
+/**
  * omap_mux_init - private mux init function, do not call
  */
-int omap_mux_init(u32 mux_pbase, u32 mux_size,
-                                struct omap_mux *superset,
-                                struct omap_mux *package_subset,
-                                struct omap_board_mux *board_mux,
-                                struct omap_ball *package_balls);
+int omap_mux_init(const char *name, u32 flags,
+                  u32 mux_pbase, u32 mux_size,
+                  struct omap_mux *superset,
+                  struct omap_mux *package_subset,
+                  struct omap_board_mux *board_mux,
+                  struct omap_ball *package_balls);
+
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
index 414af5434456..cf6de0971c6c 100644
--- a/arch/arm/mach-omap2/mux2420.c
+++ b/arch/arm/mach-omap2/mux2420.c
@@ -678,11 +678,13 @@ int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags)
         case OMAP_PACKAGE_ZAF:
                 /* REVISIT: Please add data */
         default:
-                pr_warning("mux: No ball data available for omap2420 package\n");
+                pr_warning("%s: No ball data available for omap2420 package\n",
+                                __func__);
         }
 
-        return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE,
+        return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
+                             OMAP2420_CONTROL_PADCONF_MUX_PBASE,
                              OMAP2420_CONTROL_PADCONF_MUX_SIZE,
-                                omap2420_muxmodes, NULL, board_subset,
-                                package_balls);
+                             omap2420_muxmodes, NULL, board_subset,
+                             package_balls);
 }
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
index 84d2c5a7ecd7..4185f92553db 100644
--- a/arch/arm/mach-omap2/mux2430.c
+++ b/arch/arm/mach-omap2/mux2430.c
@@ -781,11 +781,13 @@ int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags)
                 package_balls = omap2430_pop_ball;
                 break;
         default:
-                pr_warning("mux: No ball data available for omap2420 package\n");
+                pr_warning("%s: No ball data available for omap2420 package\n",
+                                __func__);
         }
 
-        return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE,
+        return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
+                             OMAP2430_CONTROL_PADCONF_MUX_PBASE,
                              OMAP2430_CONTROL_PADCONF_MUX_SIZE,
-                                omap2430_muxmodes, NULL, board_subset,
-                                package_balls);
+                             omap2430_muxmodes, NULL, board_subset,
+                             package_balls);
 }
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index 574e54ea3ab7..440c98e9a510 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -2049,12 +2049,13 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
                 package_balls = omap36xx_cbp_ball;
                 break;
         default:
-                printk(KERN_ERR "mux: Unknown omap package, mux disabled\n");
+                pr_err("%s Unknown omap package, mux disabled\n", __func__);
                 return -EINVAL;
         }
 
-        return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE,
+        return omap_mux_init("core", 0,
+                             OMAP3_CONTROL_PADCONF_MUX_PBASE,
                              OMAP3_CONTROL_PADCONF_MUX_SIZE,
-                                omap3_muxmodes, package_subset, board_subset,
-                                package_balls);
+                             omap3_muxmodes, package_subset, board_subset,
+                             package_balls);
 }
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
new file mode 100644
index 000000000000..980f11d45c79
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.c
@@ -0,0 +1,1625 @@
+/*
+ * OMAP44xx ES1.0 pin mux definition
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com>
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)  \
+{                                                                       \
+        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
+        .gpio           = (g),                                          \
+        .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
+}
+
+#else
+
+#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)  \
+{                                                                       \
+        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
+        .gpio           = (g),                                          \
+}
+
+#endif
+
+#define _OMAP4_BALLENTRY(M0, bb, bt)                            \
+{                                                                       \
+        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
+        .balls          = { bb, bt },                                   \
+}
+
+/*
+ * Superset of all mux modes for omap4 ES1.0
+ */
+static struct omap_mux __initdata omap4_core_muxmodes[] = {
+        _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
+                        "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
+                        "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
+                        "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
+                        "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
+                        "gpio_32", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
+                        "gpio_33", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
+                        "gpio_34", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
+                        "gpio_35", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
+                        "gpio_36", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
+                        "gpio_37", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
+                        "gpio_38", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
+                        "gpio_39", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
+                        "gpio_40", "venc_656_data0", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
+                        "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
+                        "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
+                        "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
+                        "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
+                        "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
+                        "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
+                        "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
+                        "gpio_48", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
+                        "gpio_49", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
+                        "sys_ndmareq0", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
+                        "gpio_51", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
+                        "gpio_52", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
+                        "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
+                        "sys_ndmareq1", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
+                        "sys_ndmareq2", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
+                        "gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
+                        "gpio_59", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
+                        "gpio_60", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
+                        "gpio_61", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
+                        "gpio_62", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
+                        "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
+                        "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
+                        "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
+                        "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
+                        "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
+                        "gpio_65", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
+                        "gpio_66", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
+                        "gpio_83", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
+                        "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
+                        NULL, "hw_dbg20", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
+                        "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
+                        "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
+                        "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
+                        "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
+                        "hsi1_acready", "mcbsp4_fsx", "gpio_87",
+                        "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
+                        "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
+                        "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
+                        "hsi1_acdata", "mcbsp4_dx", "gpio_89",
+                        "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
+                        "hsi1_acflag", "mcbsp4_dr", "gpio_90",
+                        "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
+                        "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
+                        "usbb1_mm_txen", "hw_dbg27", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
+                        "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
+                        "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
+                        "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
+                        "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
+                        "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
+                        "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
+                        "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
+                        "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
+                        "gpio_96", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
+                        NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
+                        "gpio_98", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
+                        "gpio_99", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
+                        "gpio_100", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
+                        "gpio_101", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
+                        "gpio_102", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
+                        "gpio_103", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
+                        "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
+                        "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
+                        "gpio_106", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
+                        "gpio_107", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
+                        "gpio_108", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
+                        "gpio_109", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
+                        "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
+                        "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
+                        "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
+                        "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
+                        "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
+                        "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
+                        "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
+                        "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
+                        "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
+                        "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
+                        NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
+                        NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
+                        "gpio_119", "usbb2_mm_txse0", NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
+                        "gpio_120", "usbb2_mm_txdat", NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
+                        NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
+                        "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
+                        "gpio_123", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
+                        "gpio_124", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
+                        "gpio_125", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
+                        "gpio_126", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
+                        "gpio_127", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
+                        "gpio_128", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
+                        "gpio_129", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
+                        "gpio_135", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
+                        "gpio_136", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
+                        "gpio_138", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
+                        "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
+                        "slimbus2_data", "gpio_140", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
+                        NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
+                        "gpio_142", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
+                        "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
+                        "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
+                        "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
+                        "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
+                        "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
+                        "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
+                        "gpio_149", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
+                        "gpio_150", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
+                        "gpio_151", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
+                        "gpio_152", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
+                        "gpio_153", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
+                        "gpio_154", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
+                        "gpio_155", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
+                        "gpio_156", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
+                        "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
+                        "hsi2_cawake", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
+                        "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
+                        "hsi2_cadata", "dispc2_data23", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
+                        "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
+                        "hsi2_caflag", "dispc2_data22", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
+                        "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
+                        "hsi2_acready", "dispc2_data21", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
+                        "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
+                        "hsi2_acwake", "dispc2_data20", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
+                        "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
+                        "hsi2_acdata", "dispc2_data19", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
+                        "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
+                        "hsi2_acflag", "dispc2_data18", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
+                        "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
+                        "hsi2_caready", "dispc2_data15", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
+                        "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
+                        "mcspi3_somi", "dispc2_data14", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
+                        "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
+                        "mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
+                        "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
+                        "mcspi3_simo", "dispc2_data12", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
+                        "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
+                        "mcspi3_clk", "dispc2_data11", NULL, "reserved"),
+        _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
+                        "gpio_169", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
+                        NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
+                        "gpio_171", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
+                        "gpio_172", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
+                        "gpio_173", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
+                        "gpio_174", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
+                        "gpio_0", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
+                        "gpio_1", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
+                        "gpi_175", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
+                        "gpi_176", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
+                        "gpi_177", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
+                        "gpi_178", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
+                        "gpi_2", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
+                        "gpi_3", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
+                        "uart2_rx", "gpio_179", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
+                        "uart2_tx", "gpio_180", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
+                        "gpio_181", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
+                        "gpio_182", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
+                        NULL, "hw_dbg0", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
+                        NULL, "hw_dbg1", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
+                        "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
+                        "gpio_14", NULL, "dispc2_data10", "hw_dbg3",
+                        "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
+                        "gpio_15", NULL, "dispc2_data9", "hw_dbg4",
+                        "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
+                        "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
+                        "hw_dbg5", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
+                        "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
+                        "dispc2_data17", "hw_dbg6", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
+                        "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
+                        "dispc2_hsync", "hw_dbg7", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
+                        "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
+                        "hw_dbg8", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
+                        "uart3_cts_rctx", "gpio_20", "rfbi_we",
+                        "dispc2_vsync", "hw_dbg9", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
+                        NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
+                        "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
+                        NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
+                        "hw_dbg11", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
+                        NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
+                        "hw_dbg12", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
+                        NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
+                        "hw_dbg13", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
+                        "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
+                        "hw_dbg14", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
+                        NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
+                        "hw_dbg15", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
+                        "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
+                        "hw_dbg16", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
+                        "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
+                        "hw_dbg17", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
+                        "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
+                        "hw_dbg18", "reserved"),
+        _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
+                        "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
+                        "hw_dbg19", "reserved"),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBL package
+ * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ *                                0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined(CONFIG_OMAP_PACKAGE_CBL)
+struct omap_ball __initdata omap4_core_cbl_ball[] = {
+        _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
+        _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
+        _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
+        _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
+        _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
+        _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
+        _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
+        _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
+        _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
+        _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
+        _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
+        _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
+        _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
+        _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
+        _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
+        _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
+        _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
+        _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
+        _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
+        _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
+        _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
+        _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
+        _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
+        _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
+        _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
+        _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
+        _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
+        _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
+        _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
+        _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
+        _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
+        _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
+        _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
+        _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
+        _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
+        _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
+        _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
+        _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
+        _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
+        _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
+        _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
+        _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
+        _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
+        _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
+        _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
+        _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
+        _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
+        _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
+        _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
+        _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
+        _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
+        _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
+        _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
+        _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
+        _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
+        _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
+        _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
+        _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
+        _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
+        _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
+        _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
+        _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_core_cbl_ball  NULL
+#endif
+
+/*
+ * Superset of all mux modes for omap4 ES2.0
+ */
+static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
+        _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
+                        "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
+                        "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
+                        "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
+                        "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
+                        "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
+                        "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
+                        "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
+                        "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
+                        "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
+                        "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
+                        "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
+                        "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
+                        "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
+                        "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
+                        "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
+                        "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
+                        "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
+                        "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
+                        "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
+                        "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
+                        "gpio_48", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
+                        "gpio_49", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
+                        "sys_ndmareq0", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
+                        "gpio_51", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
+                        "c2c_dataout7", "gpio_52", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
+                        "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
+                        "sys_ndmareq1", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
+                        "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
+                        "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
+                        "gpio_59", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
+                        "gpio_60", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
+                        "gpio_61", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
+                        "gpio_62", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
+                        "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0",
+                        "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1",
+                        "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0",
+                        "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
+                        "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
+                        "gpio_65", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
+                        "gpio_66", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
+                        "gpio_83", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
+                        "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
+                        NULL, "hw_dbg20", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
+                        "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
+                        "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
+                        "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
+                        "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
+                        "hsi1_acready", "mcbsp4_fsx", "gpio_87",
+                        "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
+                        "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
+                        "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
+                        "hsi1_acdata", "mcbsp4_dx", "gpio_89",
+                        "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
+                        "hsi1_acflag", "mcbsp4_dr", "gpio_90",
+                        "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
+                        "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
+                        "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
+                        "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
+                        "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
+                        "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
+                        "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
+                        "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
+                        "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
+                        "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
+                        "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
+                        "gpio_96", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
+                        NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
+                        "gpio_98", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
+                        "gpio_99", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
+                        "gpio_100", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
+                        "gpio_101", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
+                        "gpio_102", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
+                        "gpio_103", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
+                        "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
+                        "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
+                        "gpio_106", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
+                        "gpio_107", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
+                        "gpio_108", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
+                        "gpio_109", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
+                        "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
+                        "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
+                        "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
+                        "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
+                        "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
+                        "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
+                        "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
+                        "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
+                        "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
+                        "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
+                        NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
+                        NULL, NULL, NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
+                        "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
+                        "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
+                        "abe_mcasp_axr", "gpio_121", NULL,
+                        "dmtimer11_pwm_evt", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
+                        "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
+                        "gpio_123", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
+                        "gpio_124", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
+                        "gpio_125", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
+                        "gpio_126", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
+                        "gpio_127", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
+                        "gpio_128", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
+                        "gpio_129", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
+                        "gpio_135", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
+                        "gpio_136", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
+                        "gpio_138", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
+                        "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
+                        "slimbus2_data", "gpio_140", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
+                        NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
+                        "gpio_142", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
+                        "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
+                        "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
+                        "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
+                        "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd",
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
+                        "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0",
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
+                        "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1",
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
+                        "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
+                        "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk",
+                        "kpd_col6", "gpio_151", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd",
+                        "kpd_col7", "gpio_152", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0",
+                        "kpd_row6", "gpio_153", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3",
+                        "kpd_row7", "gpio_154", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8",
+                        "gpio_155", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
+                        "gpio_156", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
+                        "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
+                        "hsi2_cawake", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
+                        "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
+                        "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
+                        "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
+                        "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
+                        "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
+                        "hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
+                        "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
+                        "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
+                        "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
+                        "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
+                        "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
+                        "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
+                        "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
+                        "hsi2_caready", "dispc2_data15", "rfbi_data15",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
+                        "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
+                        "mcspi3_somi", "dispc2_data14", "rfbi_data14",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
+                        "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
+                        "mcspi3_cs0", "dispc2_data13", "rfbi_data13",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
+                        "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
+                        "mcspi3_simo", "dispc2_data12", "rfbi_data12",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
+                        "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
+                        "mcspi3_clk", "dispc2_data11", "rfbi_data11",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
+                        "gpio_169", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
+                        NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
+                        "gpio_171", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
+                        "gpio_172", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL,
+                        "gpio_173", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL,
+                        "gpio_174", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL,
+                        "gpio_175", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL,
+                        "gpio_176", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL,
+                        "gpio_177", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL,
+                        "gpio_178", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
+                        "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
+                        "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
+                        "gpio_181", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
+                        "gpio_182", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
+                        NULL, "hw_dbg0", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
+                        NULL, "hw_dbg1", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
+                        "gpio_13", NULL, "dispc2_fid", "hw_dbg2",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
+                        "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
+                        "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
+                        "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
+                        "hw_dbg5", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
+                        "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
+                        "dispc2_data17", "hw_dbg6", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
+                        "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
+                        "dispc2_hsync", "hw_dbg7", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
+                        "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
+                        "hw_dbg8", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
+                        "uart3_cts_rctx", "gpio_20", "rfbi_we",
+                        "dispc2_vsync", "hw_dbg9", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
+                        NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
+                        NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
+                        "hw_dbg11", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
+                        NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
+                        "hw_dbg12", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
+                        NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
+                        "hw_dbg13", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
+                        "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
+                        "hw_dbg14", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
+                        NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
+                        "hw_dbg15", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
+                        "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
+                        "hw_dbg16", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
+                        "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
+                        "hw_dbg17", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
+                        "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
+                        "hw_dbg18", "safe_mode"),
+        _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
+                        "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
+                        "hw_dbg19", "safe_mode"),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBS package
+ * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ *                                0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined(CONFIG_OMAP_PACKAGE_CBS)
+struct omap_ball __initdata omap4_core_cbs_ball[] = {
+        _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
+        _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
+        _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
+        _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
+        _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
+        _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
+        _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
+        _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
+        _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
+        _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
+        _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
+        _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
+        _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
+        _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
+        _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
+        _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
+        _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
+        _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
+        _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
+        _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL),
+        _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL),
+        _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
+        _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
+        _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
+        _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
+        _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
+        _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
+        _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
+        _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
+        _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
+        _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
+        _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
+        _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
+        _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
+        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
+        _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
+        _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
+        _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
+        _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
+        _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
+        _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
+        _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
+        _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
+        _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
+        _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
+        _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
+        _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
+        _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
+        _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
+        _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
+        _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
+        _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
+        _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
+        _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
+        _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
+        _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
+        _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
+        _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
+        _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
+        _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
+        _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
+        _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
+        _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
+        _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
+        _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
+        _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
+        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
+        _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
+        _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
+        _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL),
+        _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL),
+        _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL),
+        _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL),
+        _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL),
+        _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
+        _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
+        _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
+        _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
+        _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
+        _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_core_cbs_ball  NULL
+#endif
+
+/*
+ * Superset of all mux modes for omap4
+ */
+static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
+        _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
+                        "c2c_wakereqin", NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
+                        "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
+                        "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
+                        "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
+                        "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
+                        NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
+                        NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
+                        "gpio_wk8", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
+                        NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
+                        NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
+                        NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
+                        "gpio_wk9", "c2c_wakereqout", NULL, NULL,
+                        "safe_mode"),
+        _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
+                        "gpio_wk10", NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
+                        NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
+                        NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
+                        NULL, NULL, NULL),
+        _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
+                        NULL, NULL, NULL, "safe_mode"),
+        _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
+                        NULL, NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 44XX CBL & CBS package - wakeup partition
+ * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
+ *                                0.40mm Ball Pitch (Bottom)
+ */
+#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
+                && defined(CONFIG_OMAP_PACKAGE_CBL)
+struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = {
+        _OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
+        _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
+        _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
+        _OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
+        _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
+        _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
+        _OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
+        _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
+        _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
+        _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
+        _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
+        _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
+        _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
+        _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
+        _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
+        _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
+        _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
+        _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
+        _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
+        _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
+        _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
+        _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap4_wkup_cbl_cbs_ball  NULL
+#endif
+
+int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
+{
+        struct omap_ball *package_balls_core;
+        struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
+        struct omap_mux *core_muxmodes;
+        int ret;
+
+        switch (flags & OMAP_PACKAGE_MASK) {
+        case OMAP_PACKAGE_CBL:
+                pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__);
+                package_balls_core = omap4_core_cbl_ball;
+                core_muxmodes = omap4_core_muxmodes;
+                break;
+        case OMAP_PACKAGE_CBS:
+                pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
+                package_balls_core = omap4_core_cbs_ball;
+                core_muxmodes = omap4_es2_core_muxmodes;
+                break;
+        default:
+                pr_err("%s: Unknown omap package, mux disabled\n", __func__);
+                return -EINVAL;
+        }
+
+        ret = omap_mux_init("core",
+                            OMAP_MUX_GPIO_IN_MODE3,
+                            OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
+                            OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
+                            core_muxmodes, NULL, board_subset,
+                            package_balls_core);
+        if (ret)
+                return ret;
+
+        ret = omap_mux_init("wkup",
+                            OMAP_MUX_GPIO_IN_MODE3,
+                            OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
+                            OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
+                            omap4_wkup_muxmodes, NULL, board_subset,
+                            package_balls_wkup);
+
+        return ret;
+}
+
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
new file mode 100644
index 000000000000..c635026cd7e9
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.h
@@ -0,0 +1,298 @@
+/*
+ * OMAP44xx MUX registers and bitfields
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
+
+#define OMAP4_MUX(M0, mux_value)                                        \
+{                                                                       \
+        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
+        .value          = (mux_value),                                  \
+}
+
+/* ctrl_module_pad_core base address */
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE                    0x4a100000
+
+/* ctrl_module_pad_core registers offset */
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET                   0x0040
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET                   0x0042
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET                   0x0044
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET                   0x0046
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET                   0x0048
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET                   0x004a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET                   0x004c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET                   0x004e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET                   0x0050
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET                   0x0052
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET                  0x0054
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET                  0x0056
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET                  0x0058
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET                  0x005a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET                  0x005c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET                  0x005e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET                   0x0060
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET                   0x0062
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET                   0x0064
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET                   0x0066
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET                   0x0068
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET                   0x006a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET                   0x006c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET                   0x006e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET                   0x0070
+#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET                   0x0072
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET                  0x0074
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET                  0x0076
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET                  0x0078
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET                  0x007a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET                   0x007c
+#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET                   0x007e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET              0x0080
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET                   0x0082
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET                   0x0084
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET              0x0086
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET                  0x0088
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET                 0x008a
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET                 0x008c
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET                 0x008e
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET                 0x0090
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET                 0x0092
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET                 0x0094
+#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET                 0x0096
+#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET                   0x0098
+#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET                   0x009a
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET               0x009c
+#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET               0x009e
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET                  0x00a0
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET                  0x00a2
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET                  0x00a4
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET                  0x00a6
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET                  0x00a8
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET                  0x00aa
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET                  0x00ac
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET                  0x00ae
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET                  0x00b0
+#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET                  0x00b2
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET                  0x00b4
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET                  0x00b6
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET                  0x00b8
+#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET                  0x00ba
+#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET                0x00bc
+#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET                 0x00be
+#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET            0x00c0
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET          0x00c2
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET          0x00c4
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET          0x00c6
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET          0x00c8
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET         0x00ca
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET         0x00cc
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET         0x00ce
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET         0x00d0
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET         0x00d2
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET         0x00d4
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET         0x00d6
+#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET         0x00d8
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET            0x00da
+#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET          0x00dc
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET             0x00de
+#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET             0x00e0
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET                 0x00e2
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET                 0x00e4
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET                0x00e6
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET                0x00e8
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET                0x00ea
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET                0x00ec
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET                0x00ee
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET                0x00f0
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET                0x00f2
+#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET                0x00f4
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET            0x00f6
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET              0x00f8
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET              0x00fa
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET             0x00fc
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET            0x00fe
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET              0x0100
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET              0x0102
+#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET             0x0104
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET            0x0106
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET            0x0108
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET              0x010a
+#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET             0x010c
+#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET                   0x010e
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET              0x0110
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET              0x0112
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET              0x0114
+#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET              0x0116
+#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET                  0x0118
+#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET                  0x011a
+#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET                   0x011c
+#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET                   0x011e
+#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET                    0x0120
+#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET                   0x0122
+#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET                   0x0124
+#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET                   0x0126
+#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET                   0x0128
+#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET                   0x012a
+#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET                   0x012c
+#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET                   0x012e
+#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET                   0x0130
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET                 0x0132
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET                0x0134
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET                0x0136
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET                 0x0138
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET                 0x013a
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET                 0x013c
+#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET                 0x013e
+#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET             0x0140
+#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET               0x0142
+#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET              0x0144
+#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET              0x0146
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET                 0x0148
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET                 0x014a
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET                0x014c
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET                0x014e
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET                0x0150
+#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET                0x0152
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET                 0x0154
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET                0x0156
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET                0x0158
+#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET                 0x015a
+#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET                   0x015c
+#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET                   0x015e
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET          0x0160
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET          0x0162
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET          0x0164
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET          0x0166
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET         0x0168
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET         0x016a
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET         0x016c
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET         0x016e
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET         0x0170
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET         0x0172
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET         0x0174
+#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET         0x0176
+#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET            0x0178
+#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET          0x017a
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET                 0x017c
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET                 0x017e
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET                 0x0180
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET                 0x0182
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET                 0x0184
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET                 0x0186
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET                 0x0188
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET                 0x018a
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET                 0x018c
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET                 0x018e
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET                 0x0190
+#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET                 0x0192
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET               0x0194
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET               0x0196
+#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET               0x0198
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET              0x019a
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET              0x019c
+#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET                  0x019e
+#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET                  0x01a0
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET                  0x01a2
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET                  0x01a4
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET                  0x01a6
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET                  0x01a8
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET                  0x01aa
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET                  0x01ac
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET                   0x01ae
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET                   0x01b0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET                   0x01b2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET                   0x01b4
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET                   0x01b6
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET                   0x01b8
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET                   0x01ba
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET                   0x01bc
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET                   0x01be
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET                   0x01c0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET                  0x01c2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET                  0x01c4
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET                  0x01c6
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET                  0x01c8
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET                  0x01ca
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET                  0x01cc
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET                  0x01ce
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET                  0x01d0
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET                  0x01d2
+#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET                  0x01d4
+
+/* ES2.0 only */
+#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET                 0x008e
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET                  0x0090
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET                  0x0092
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET                  0x0094
+#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET                  0x0096
+
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET                   0x017c
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET                   0x017e
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET                   0x0180
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET                   0x0182
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET                   0x0184
+#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET                   0x0186
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET                   0x0188
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET                   0x018a
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET                   0x018c
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET                   0x018e
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET                   0x0190
+#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET                   0x0192
+
+
+#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE                     \
+                (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET         \
+                 - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
+
+/* ctrl_module_pad_wkup base address */
+#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE                    0x4a31e000
+
+/* ctrl_module_pad_wkup registers offset */
+#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET                     0x0040
+#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET                    0x0042
+#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET                  0x0044
+#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET                     0x0046
+#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET                0x0048
+#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET                     0x004a
+#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET                     0x004c
+#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET               0x004e
+#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET             0x0050
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET             0x0052
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET              0x0054
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET              0x0056
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET              0x0058
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET              0x005a
+#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET              0x005c
+#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET                    0x005e
+#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET              0x0060
+#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET               0x0062
+#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET                0x0064
+#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET        0x0066
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET                  0x0068
+#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET                  0x006a
+#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET                 0x006c
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET                   0x006e
+#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET                  0x0070
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET              0x0072
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET                   0x0074
+#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET                   0x0076
+
+#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE                     \
+                (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET          \
+                 - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
+
+#endif
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 6cee456ca542..4976b9393e49 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -17,16 +17,13 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
-#include <linux/completion.h>
 
 #include <asm/cacheflush.h>
 #include <mach/omap4-common.h>
 
-static DECLARE_COMPLETION(cpu_killed);
-
 int platform_cpu_kill(unsigned int cpu)
 {
-        return wait_for_completion_timeout(&cpu_killed, 5000);
+        return 1;
 }
 
 /*
@@ -35,15 +32,6 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-        unsigned int this_cpu = hard_smp_processor_id();
-
-        if (cpu != this_cpu) {
-                pr_crit("platform_cpu_die running on %u, should be %u\n",
-                           this_cpu, cpu);
-                BUG();
-        }
-        pr_notice("CPU%u: shutdown\n", cpu);
-        complete(&cpu_killed);
         flush_cache_all();
         dsb();
 
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index f5a1aad1a5c0..3fc5dc7233da 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -33,9 +33,11 @@ static struct iommu_device omap3_devices[] = {
                         .name = "isp",
                         .nr_tlb_entries = 8,
                         .clk_name = "cam_ick",
+                        .da_start = 0x0,
+                        .da_end = 0xFFFFF000,
                 },
         },
-#if defined(CONFIG_MPU_BRIDGE_IOMMU)
+#if defined(CONFIG_OMAP_IOMMU_IVA2)
         {
                 .base = 0x5d000000,
                 .irq = 28,
@@ -43,6 +45,8 @@ static struct iommu_device omap3_devices[] = {
                         .name = "iva2",
                         .nr_tlb_entries = 32,
                         .clk_name = "iva2_ck",
+                        .da_start = 0x11000000,
+                        .da_end = 0xFFFFF000,
                 },
         },
 #endif
@@ -64,6 +68,8 @@ static struct iommu_device omap4_devices[] = {
                         .name = "ducati",
                         .nr_tlb_entries = 32,
                         .clk_name = "ducati_ick",
+                        .da_start = 0x0,
+                        .da_end = 0xFFFFF000,
                 },
         },
 #if defined(CONFIG_MPU_TESLA_IOMMU)
@@ -74,6 +80,8 @@ static struct iommu_device omap4_devices[] = {
                         .name = "tesla",
                         .nr_tlb_entries = 32,
                         .clk_name = "tesla_ick",
+                        .da_start = 0x0,
+                        .da_end = 0xFFFFF000,
                 },
         },
 #endif
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 9e9f70e18e3c..b66cfe8bc464 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/localtimer.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -29,28 +28,16 @@
 /* SCU base address */
 static void __iomem *scu_base;
 
-/*
- * Use SCU config register to count number of cores
- */
-static inline unsigned int get_core_count(void)
-{
-        if (scu_base)
-                return scu_get_core_count(scu_base);
-        return 1;
-}
-
 static DEFINE_SPINLOCK(boot_lock);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        trace_hardirqs_off();
-
         /*
          * If any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_secondary_init(0);
 
         /*
          * Synchronise with the boot thread.
@@ -76,7 +63,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         omap_modify_auxcoreboot0(0x200, 0xfffffdff);
         flush_cache_all();
         smp_wmb();
-        smp_cross_call(cpumask_of(cpu));
+        smp_cross_call(cpumask_of(cpu), 1);
 
         /*
          * Now the secondary core is starting up let it run its
@@ -118,25 +105,9 @@ void __init smp_init_cpus(void)
         scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
         BUG_ON(!scu_base);
 
-        ncores = get_core_count();
-
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
-        unsigned int ncores = get_core_count();
-        unsigned int cpu = smp_processor_id();
-        int i;
+        ncores = scu_get_core_count(scu_base);
 
         /* sanity check */
-        if (ncores == 0) {
-                printk(KERN_ERR
-                       "OMAP4: strange core count of 0? Default to 1\n");
-                ncores = 1;
-        }
-
         if (ncores > NR_CPUS) {
                 printk(KERN_WARNING
                        "OMAP4: no. of cores (%d) greater than configured "
@@ -144,13 +115,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                        ncores, NR_CPUS);
                 ncores = NR_CPUS;
         }
-        smp_store_cpu_info(cpu);
 
-        /*
-         * are we trying to boot more cores than exist?
-         */
-        if (max_cpus > ncores)
-                max_cpus = ncores;
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
 
         /*
          * Initialise the present map, which describes the set of CPUs
@@ -159,18 +131,10 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
-        if (max_cpus > 1) {
-                /*
-                 * Enable the local timer or broadcast device for the
-                 * boot CPU, but only if we have more than one CPU.
-                 */
-                percpu_timer_setup();
-
-                /*
-                 * Initialise the SCU and wake up the secondary core using
-                 * wakeup_secondary().
-                 */
-                scu_enable(scu_base);
-                wakeup_secondary();
-        }
+        /*
+         * Initialise the SCU and wake up the secondary core using
+         * wakeup_secondary().
+         */
+        scu_enable(scu_base);
+        wakeup_secondary();
 }
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 2f895553e6a8..19268647ce36 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -26,21 +26,22 @@
 void __iomem *l2cache_base;
 #endif
 
-void __iomem *gic_cpu_base_addr;
 void __iomem *gic_dist_base_addr;
 
 
 void __init gic_init_irq(void)
 {
+        void __iomem *gic_cpu_base;
+
         /* Static mapping, never released */
         gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
         BUG_ON(!gic_dist_base_addr);
-        gic_dist_init(0, gic_dist_base_addr, 29);
 
         /* Static mapping, never released */
-        gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
-        BUG_ON(!gic_cpu_base_addr);
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
+        BUG_ON(!gic_cpu_base);
+
+        gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
 }
 
 #ifdef CONFIG_CACHE_L2X0
@@ -53,6 +54,8 @@ static void omap4_l2x0_disable(void)
 
 static int __init omap_l2_cache_init(void)
 {
+        u32 aux_ctrl = 0;
+
         /*
          * To avoid code running on other OMAPs in
          * multi-omap builds
@@ -64,18 +67,32 @@ static int __init omap_l2_cache_init(void)
         l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
         BUG_ON(!l2cache_base);
 
-        /* Enable PL310 L2 Cache controller */
-        omap_smc1(0x102, 0x1);
-
         /*
          * 16-way associativity, parity disabled
          * Way size - 32KB (es1.0)
          * Way size - 64KB (es2.0 +)
          */
-        if (omap_rev() == OMAP4430_REV_ES1_0)
-                l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
-        else
-                l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
+        aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
+                        (0x1 << 25) |
+                        (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
+                        (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
+
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
+        } else {
+                aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
+                        (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
+                        (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+                        (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+                        (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
+        }
+        if (omap_rev() != OMAP4430_REV_ES1_0)
+                omap_smc1(0x109, aux_ctrl);
+
+        /* Enable PL310 L2 Cache controller */
+        omap_smc1(0x102, 0x1);
+
+        l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
 
         /*
          * Override default outer_cache.disable with a OMAP4
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 5a30658444d0..e282e35769fd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -116,7 +116,6 @@
  * - Open Core Protocol Specification 2.2
  *
  * To do:
- * - pin mux handling
  * - handle IO mapping
  * - bus throughput & module latency measurement code
  *
@@ -135,17 +134,21 @@
 #include <linux/err.h>
 #include <linux/list.h>
 #include <linux/mutex.h>
+#include <linux/spinlock.h>
 
 #include <plat/common.h>
 #include <plat/cpu.h>
-#include <plat/clockdomain.h>
-#include <plat/powerdomain.h>
+#include "clockdomain.h"
+#include "powerdomain.h"
 #include <plat/clock.h>
 #include <plat/omap_hwmod.h>
 #include <plat/prcm.h>
 
-#include "cm.h"
-#include "prm.h"
+#include "cm2xxx_3xxx.h"
+#include "cm44xx.h"
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+#include "mux.h"
 
 /* Maximum microseconds to wait for OMAP module to softreset */
 #define MAX_MODULE_SOFTRESET_WAIT       10000
@@ -156,8 +159,6 @@
 /* omap_hwmod_list contains all registered struct omap_hwmods */
 static LIST_HEAD(omap_hwmod_list);
 
-static DEFINE_MUTEX(omap_hwmod_mutex);
-
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
 
@@ -209,10 +210,9 @@ static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
 
         /* XXX ensure module interface clock is up */
 
-        if (oh->_sysc_cache != v) {
-                oh->_sysc_cache = v;
-                omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
-        }
+        /* Module might have lost context, always update cache and register */
+        oh->_sysc_cache = v;
+        omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
 }
 
 /**
@@ -388,12 +388,13 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
  * Allow the hardware module @oh to send wakeups.  Returns -EINVAL
  * upon error or 0 upon success.
  */
-static int _enable_wakeup(struct omap_hwmod *oh)
+static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
 {
-        u32 v, wakeup_mask;
+        u32 wakeup_mask;
 
         if (!oh->class->sysc ||
-            !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
+            !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
+              (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
                 return -EINVAL;
 
         if (!oh->class->sysc->sysc_fields) {
@@ -403,9 +404,10 @@ static int _enable_wakeup(struct omap_hwmod *oh)
 
         wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
 
-        v = oh->_sysc_cache;
-        v |= wakeup_mask;
-        _write_sysconfig(v, oh);
+        *v |= wakeup_mask;
+
+        if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+                _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
@@ -421,12 +423,13 @@ static int _enable_wakeup(struct omap_hwmod *oh)
  * Prevent the hardware module @oh to send wakeups.  Returns -EINVAL
  * upon error or 0 upon success.
  */
-static int _disable_wakeup(struct omap_hwmod *oh)
+static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
 {
-        u32 v, wakeup_mask;
+        u32 wakeup_mask;
 
         if (!oh->class->sysc ||
-            !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
+            !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
+              (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
                 return -EINVAL;
 
         if (!oh->class->sysc->sysc_fields) {
@@ -436,9 +439,10 @@ static int _disable_wakeup(struct omap_hwmod *oh)
 
         wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
 
-        v = oh->_sysc_cache;
-        v &= ~wakeup_mask;
-        _write_sysconfig(v, oh);
+        *v &= ~wakeup_mask;
+
+        if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+                _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
@@ -675,7 +679,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
  * Returns the array index of the OCP slave port that the MPU
  * addresses the device on, or -EINVAL upon error or not found.
  */
-static int _find_mpu_port_index(struct omap_hwmod *oh)
+static int __init _find_mpu_port_index(struct omap_hwmod *oh)
 {
         int i;
         int found = 0;
@@ -709,7 +713,7 @@ static int _find_mpu_port_index(struct omap_hwmod *oh)
  * Return the virtual address of the base of the register target of
  * device @oh, or NULL on error.
  */
-static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
+static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
 {
         struct omap_hwmod_ocp_if *os;
         struct omap_hwmod_addr_space *mem;
@@ -786,11 +790,11 @@ static void _enable_sysc(struct omap_hwmod *oh)
             (sf & SYSC_HAS_CLOCKACTIVITY))
                 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
 
-        _write_sysconfig(v, oh);
-
         /* If slave is in SMARTIDLE, also enable wakeup */
         if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
-                _enable_wakeup(oh);
+                _enable_wakeup(oh, &v);
+
+        _write_sysconfig(v, oh);
 
         /*
          * Set the autoidle bit only after setting the smartidle bit
@@ -836,6 +840,10 @@ static void _idle_sysc(struct omap_hwmod *oh)
                 _set_master_standbymode(oh, idlemode, &v);
         }
 
+        /* If slave is in SMARTIDLE, also enable wakeup */
+        if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
+                _enable_wakeup(oh, &v);
+
         _write_sysconfig(v, oh);
 }
 
@@ -874,7 +882,6 @@ static void _shutdown_sysc(struct omap_hwmod *oh)
  * @name: find an omap_hwmod by name
  *
  * Return a pointer to an omap_hwmod by name, or NULL if not found.
- * Caller must hold omap_hwmod_mutex.
  */
 static struct omap_hwmod *_lookup(const char *name)
 {
@@ -1089,7 +1096,7 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 }
 
 /**
- * _reset - reset an omap_hwmod
+ * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
  * @oh: struct omap_hwmod *
  *
  * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit.  hwmod must be
@@ -1098,12 +1105,13 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
  * the module did not reset in time, or 0 upon success.
  *
  * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
- * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead
+ * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
  * use the SYSCONFIG softreset bit to provide the status.
  *
- * Note that some IP like McBSP does have a reset control but no reset status.
+ * Note that some IP like McBSP do have reset control but don't have
+ * reset status.
  */
-static int _reset(struct omap_hwmod *oh)
+static int _ocp_softreset(struct omap_hwmod *oh)
 {
         u32 v;
         int c = 0;
@@ -1124,7 +1132,7 @@ static int _reset(struct omap_hwmod *oh)
         if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
                 _enable_optional_clocks(oh);
 
-        pr_debug("omap_hwmod: %s: resetting\n", oh->name);
+        pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name);
 
         v = oh->_sysc_cache;
         ret = _set_softreset(oh, &v);
@@ -1164,17 +1172,41 @@ dis_opt_clks:
 }
 
 /**
- * _omap_hwmod_enable - enable an omap_hwmod
+ * _reset - reset an omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Resets an omap_hwmod @oh.  The default software reset mechanism for
+ * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET
+ * bit.  However, some hwmods cannot be reset via this method: some
+ * are not targets and therefore have no OCP header registers to
+ * access; others (like the IVA) have idiosyncratic reset sequences.
+ * So for these relatively rare cases, custom reset code can be
+ * supplied in the struct omap_hwmod_class .reset function pointer.
+ * Passes along the return value from either _reset() or the custom
+ * reset function - these must return -EINVAL if the hwmod cannot be
+ * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
+ * the module did not reset in time, or 0 upon success.
+ */
+static int _reset(struct omap_hwmod *oh)
+{
+        int ret;
+
+        pr_debug("omap_hwmod: %s: resetting\n", oh->name);
+
+        ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
+
+        return ret;
+}
+
+/**
+ * _enable - enable an omap_hwmod
  * @oh: struct omap_hwmod *
  *
  * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
- * register target.  (This function has a full name --
- * _omap_hwmod_enable() rather than simply _enable() -- because it is
- * currently required by the pm34xx.c idle loop.)  Returns -EINVAL if
- * the hwmod is in the wrong state or passes along the return value of
- * _wait_target_ready().
+ * register target.  Returns -EINVAL if the hwmod is in the wrong
+ * state or passes along the return value of _wait_target_ready().
  */
-int _omap_hwmod_enable(struct omap_hwmod *oh)
+static int _enable(struct omap_hwmod *oh)
 {
         int r;
 
@@ -1197,7 +1229,9 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
              oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
                 _deassert_hardreset(oh, oh->rst_lines[0].name);
 
-        /* XXX mux balls */
+        /* Mux pins for device runtime if populated */
+        if (oh->mux)
+                omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
 
         _add_initiator_dep(oh, mpu_oh);
         _enable_clocks(oh);
@@ -1213,6 +1247,7 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
                         _enable_sysc(oh);
                 }
         } else {
+                _disable_clocks(oh);
                 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
                          oh->name, r);
         }
@@ -1221,16 +1256,14 @@ int _omap_hwmod_enable(struct omap_hwmod *oh)
 }
 
 /**
- * _omap_hwmod_idle - idle an omap_hwmod
+ * _idle - idle an omap_hwmod
  * @oh: struct omap_hwmod *
  *
  * Idles an omap_hwmod @oh.  This should be called once the hwmod has
- * no further work.  (This function has a full name --
- * _omap_hwmod_idle() rather than simply _idle() -- because it is
- * currently required by the pm34xx.c idle loop.)  Returns -EINVAL if
- * the hwmod is in the wrong state or returns 0.
+ * no further work.  Returns -EINVAL if the hwmod is in the wrong
+ * state or returns 0.
  */
-int _omap_hwmod_idle(struct omap_hwmod *oh)
+static int _idle(struct omap_hwmod *oh)
 {
         if (oh->_state != _HWMOD_STATE_ENABLED) {
                 WARN(1, "omap_hwmod: %s: idle state can only be entered from "
@@ -1245,6 +1278,10 @@ int _omap_hwmod_idle(struct omap_hwmod *oh)
         _del_initiator_dep(oh, mpu_oh);
         _disable_clocks(oh);
 
+        /* Mux pins for device idle if populated */
+        if (oh->mux)
+                omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+
         oh->_state = _HWMOD_STATE_IDLE;
 
         return 0;
@@ -1261,6 +1298,9 @@ int _omap_hwmod_idle(struct omap_hwmod *oh)
  */
 static int _shutdown(struct omap_hwmod *oh)
 {
+        int ret;
+        u8 prev_state;
+
         if (oh->_state != _HWMOD_STATE_IDLE &&
             oh->_state != _HWMOD_STATE_ENABLED) {
                 WARN(1, "omap_hwmod: %s: disabled state can only be entered "
@@ -1270,6 +1310,18 @@ static int _shutdown(struct omap_hwmod *oh)
 
         pr_debug("omap_hwmod: %s: disabling\n", oh->name);
 
+        if (oh->class->pre_shutdown) {
+                prev_state = oh->_state;
+                if (oh->_state == _HWMOD_STATE_IDLE)
+                        _enable(oh);
+                ret = oh->class->pre_shutdown(oh);
+                if (ret) {
+                        if (prev_state == _HWMOD_STATE_IDLE)
+                                _idle(oh);
+                        return ret;
+                }
+        }
+
         if (oh->class->sysc)
                 _shutdown_sysc(oh);
 
@@ -1288,7 +1340,9 @@ static int _shutdown(struct omap_hwmod *oh)
         }
         /* XXX Should this code also force-disable the optional clocks? */
 
-        /* XXX mux any associated balls to safe mode */
+        /* Mux pins to safe mode or use populated off mode values */
+        if (oh->mux)
+                omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
 
         oh->_state = _HWMOD_STATE_DISABLED;
 
@@ -1298,23 +1352,15 @@ static int _shutdown(struct omap_hwmod *oh)
 /**
  * _setup - do initial configuration of omap_hwmod
  * @oh: struct omap_hwmod *
- * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1
  *
  * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  @skip_setup_idle is intended to be used on
- * a system that will not call omap_hwmod_enable() to enable devices
- * (e.g., a system without PM runtime).  Returns -EINVAL if the hwmod
- * is in the wrong state or returns 0.
+ * OCP_SYSCONFIG register.  Returns -EINVAL if the hwmod is in the
+ * wrong state or returns 0.
  */
 static int _setup(struct omap_hwmod *oh, void *data)
 {
         int i, r;
-        u8 skip_setup_idle;
-
-        if (!oh || !data)
-                return -EINVAL;
-
-        skip_setup_idle = *(u8 *)data;
+        u8 postsetup_state;
 
         /* Set iclk autoidle mode */
         if (oh->slaves_cnt > 0) {
@@ -1334,7 +1380,6 @@ static int _setup(struct omap_hwmod *oh, void *data)
                 }
         }
 
-        mutex_init(&oh->_mutex);
         oh->_state = _HWMOD_STATE_INITIALIZED;
 
         /*
@@ -1347,7 +1392,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
         if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
                 return 0;
 
-        r = _omap_hwmod_enable(oh);
+        r = _enable(oh);
         if (r) {
                 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
                            oh->name, oh->_state);
@@ -1359,7 +1404,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
 
                 /*
                  * OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
-                 * The _omap_hwmod_enable() function should be split to
+                 * The _enable() function should be split to
                  * avoid the rewrite of the OCP_SYSCONFIG register.
                  */
                 if (oh->class->sysc) {
@@ -1368,12 +1413,77 @@ static int _setup(struct omap_hwmod *oh, void *data)
                 }
         }
 
-        if (!(oh->flags & HWMOD_INIT_NO_IDLE) && !skip_setup_idle)
-                _omap_hwmod_idle(oh);
+        postsetup_state = oh->_postsetup_state;
+        if (postsetup_state == _HWMOD_STATE_UNKNOWN)
+                postsetup_state = _HWMOD_STATE_ENABLED;
+
+        /*
+         * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
+         * it should be set by the core code as a runtime flag during startup
+         */
+        if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
+            (postsetup_state == _HWMOD_STATE_IDLE))
+                postsetup_state = _HWMOD_STATE_ENABLED;
+
+        if (postsetup_state == _HWMOD_STATE_IDLE)
+                _idle(oh);
+        else if (postsetup_state == _HWMOD_STATE_DISABLED)
+                _shutdown(oh);
+        else if (postsetup_state != _HWMOD_STATE_ENABLED)
+                WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
+                     oh->name, postsetup_state);
 
         return 0;
 }
 
+/**
+ * _register - register a struct omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Registers the omap_hwmod @oh.  Returns -EEXIST if an omap_hwmod
+ * already has been registered by the same name; -EINVAL if the
+ * omap_hwmod is in the wrong state, if @oh is NULL, if the
+ * omap_hwmod's class field is NULL; if the omap_hwmod is missing a
+ * name, or if the omap_hwmod's class is missing a name; or 0 upon
+ * success.
+ *
+ * XXX The data should be copied into bootmem, so the original data
+ * should be marked __initdata and freed after init.  This would allow
+ * unneeded omap_hwmods to be freed on multi-OMAP configurations.  Note
+ * that the copy process would be relatively complex due to the large number
+ * of substructures.
+ */
+static int __init _register(struct omap_hwmod *oh)
+{
+        int ret, ms_id;
+
+        if (!oh || !oh->name || !oh->class || !oh->class->name ||
+            (oh->_state != _HWMOD_STATE_UNKNOWN))
+                return -EINVAL;
+
+        pr_debug("omap_hwmod: %s: registering\n", oh->name);
+
+        if (_lookup(oh->name))
+                return -EEXIST;
+
+        ms_id = _find_mpu_port_index(oh);
+        if (!IS_ERR_VALUE(ms_id)) {
+                oh->_mpu_port_index = ms_id;
+                oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
+        } else {
+                oh->_int_flags |= _HWMOD_NO_MPU_PORT;
+        }
+
+        list_add_tail(&oh->node, &omap_hwmod_list);
+
+        spin_lock_init(&oh->_lock);
+
+        oh->_state = _HWMOD_STATE_REGISTERED;
+
+        ret = 0;
+
+        return ret;
+}
 
 
 /* Public functions */
@@ -1427,59 +1537,6 @@ int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
 }
 
 /**
- * omap_hwmod_register - register a struct omap_hwmod
- * @oh: struct omap_hwmod *
- *
- * Registers the omap_hwmod @oh.  Returns -EEXIST if an omap_hwmod
- * already has been registered by the same name; -EINVAL if the
- * omap_hwmod is in the wrong state, if @oh is NULL, if the
- * omap_hwmod's class field is NULL; if the omap_hwmod is missing a
- * name, or if the omap_hwmod's class is missing a name; or 0 upon
- * success.
- *
- * XXX The data should be copied into bootmem, so the original data
- * should be marked __initdata and freed after init.  This would allow
- * unneeded omap_hwmods to be freed on multi-OMAP configurations.  Note
- * that the copy process would be relatively complex due to the large number
- * of substructures.
- */
-int omap_hwmod_register(struct omap_hwmod *oh)
-{
-        int ret, ms_id;
-
-        if (!oh || !oh->name || !oh->class || !oh->class->name ||
-            (oh->_state != _HWMOD_STATE_UNKNOWN))
-                return -EINVAL;
-
-        mutex_lock(&omap_hwmod_mutex);
-
-        pr_debug("omap_hwmod: %s: registering\n", oh->name);
-
-        if (_lookup(oh->name)) {
-                ret = -EEXIST;
-                goto ohr_unlock;
-        }
-
-        ms_id = _find_mpu_port_index(oh);
-        if (!IS_ERR_VALUE(ms_id)) {
-                oh->_mpu_port_index = ms_id;
-                oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
-        } else {
-                oh->_int_flags |= _HWMOD_NO_MPU_PORT;
-        }
-
-        list_add_tail(&oh->node, &omap_hwmod_list);
-
-        oh->_state = _HWMOD_STATE_REGISTERED;
-
-        ret = 0;
-
-ohr_unlock:
-        mutex_unlock(&omap_hwmod_mutex);
-        return ret;
-}
-
-/**
  * omap_hwmod_lookup - look up a registered omap_hwmod by name
  * @name: name of the omap_hwmod to look up
  *
@@ -1493,9 +1550,7 @@ struct omap_hwmod *omap_hwmod_lookup(const char *name)
         if (!name)
                 return NULL;
 
-        mutex_lock(&omap_hwmod_mutex);
         oh = _lookup(name);
-        mutex_unlock(&omap_hwmod_mutex);
 
         return oh;
 }
@@ -1521,13 +1576,11 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
         if (!fn)
                 return -EINVAL;
 
-        mutex_lock(&omap_hwmod_mutex);
         list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
                 ret = (*fn)(temp_oh, data);
                 if (ret)
                         break;
         }
-        mutex_unlock(&omap_hwmod_mutex);
 
         return ret;
 }
@@ -1542,7 +1595,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
  * listed in @ohs that are valid for this chip.  Returns -EINVAL if
  * omap_hwmod_init() has already been called or 0 otherwise.
  */
-int omap_hwmod_init(struct omap_hwmod **ohs)
+int __init omap_hwmod_init(struct omap_hwmod **ohs)
 {
         struct omap_hwmod *oh;
         int r;
@@ -1558,8 +1611,8 @@ int omap_hwmod_init(struct omap_hwmod **ohs)
         oh = *ohs;
         while (oh) {
                 if (omap_chip_is(oh->omap_chip)) {
-                        r = omap_hwmod_register(oh);
-                        WARN(r, "omap_hwmod: %s: omap_hwmod_register returned "
+                        r = _register(oh);
+                        WARN(r, "omap_hwmod: %s: _register returned "
                              "%d\n", oh->name, r);
                 }
                 oh = *++ohs;
@@ -1570,13 +1623,12 @@ int omap_hwmod_init(struct omap_hwmod **ohs)
 
 /**
  * omap_hwmod_late_init - do some post-clock framework initialization
- * @skip_setup_idle: if 1, do not idle hwmods in _setup()
  *
  * Must be called after omap2_clk_init().  Resolves the struct clk names
  * to struct clk pointers for each registered omap_hwmod.  Also calls
  * _setup() on each hwmod.  Returns 0.
  */
-int omap_hwmod_late_init(u8 skip_setup_idle)
+int omap_hwmod_late_init(void)
 {
         int r;
 
@@ -1588,36 +1640,7 @@ int omap_hwmod_late_init(u8 skip_setup_idle)
         WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
              MPU_INITIATOR_NAME);
 
-        if (skip_setup_idle)
-                pr_debug("omap_hwmod: will leave hwmods enabled during setup\n");
-
-        omap_hwmod_for_each(_setup, &skip_setup_idle);
-
-        return 0;
-}
-
-/**
- * omap_hwmod_unregister - unregister an omap_hwmod
- * @oh: struct omap_hwmod *
- *
- * Unregisters a previously-registered omap_hwmod @oh.  There's probably
- * no use case for this, so it is likely to be removed in a later version.
- *
- * XXX Free all of the bootmem-allocated structures here when that is
- * implemented.  Make it clear that core code is the only code that is
- * expected to unregister modules.
- */
-int omap_hwmod_unregister(struct omap_hwmod *oh)
-{
-        if (!oh)
-                return -EINVAL;
-
-        pr_debug("omap_hwmod: %s: unregistering\n", oh->name);
-
-        mutex_lock(&omap_hwmod_mutex);
-        iounmap(oh->_mpu_rt_va);
-        list_del(&oh->node);
-        mutex_unlock(&omap_hwmod_mutex);
+        omap_hwmod_for_each(_setup, NULL);
 
         return 0;
 }
@@ -1632,18 +1655,18 @@ int omap_hwmod_unregister(struct omap_hwmod *oh)
 int omap_hwmod_enable(struct omap_hwmod *oh)
 {
         int r;
+        unsigned long flags;
 
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&oh->_mutex);
-        r = _omap_hwmod_enable(oh);
-        mutex_unlock(&oh->_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
+        r = _enable(oh);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return r;
 }
 
-
 /**
  * omap_hwmod_idle - idle an omap_hwmod
  * @oh: struct omap_hwmod *
@@ -1653,12 +1676,14 @@ int omap_hwmod_enable(struct omap_hwmod *oh)
  */
 int omap_hwmod_idle(struct omap_hwmod *oh)
 {
+        unsigned long flags;
+
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&oh->_mutex);
-        _omap_hwmod_idle(oh);
-        mutex_unlock(&oh->_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
+        _idle(oh);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -1673,12 +1698,14 @@ int omap_hwmod_idle(struct omap_hwmod *oh)
  */
 int omap_hwmod_shutdown(struct omap_hwmod *oh)
 {
+        unsigned long flags;
+
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&oh->_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
         _shutdown(oh);
-        mutex_unlock(&oh->_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -1691,9 +1718,11 @@ int omap_hwmod_shutdown(struct omap_hwmod *oh)
  */
 int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
 {
-        mutex_lock(&oh->_mutex);
+        unsigned long flags;
+
+        spin_lock_irqsave(&oh->_lock, flags);
         _enable_clocks(oh);
-        mutex_unlock(&oh->_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -1706,9 +1735,11 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
  */
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
 {
-        mutex_lock(&oh->_mutex);
+        unsigned long flags;
+
+        spin_lock_irqsave(&oh->_lock, flags);
         _disable_clocks(oh);
-        mutex_unlock(&oh->_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -1752,13 +1783,14 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
 int omap_hwmod_reset(struct omap_hwmod *oh)
 {
         int r;
+        unsigned long flags;
 
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&oh->_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
         r = _reset(oh);
-        mutex_unlock(&oh->_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return r;
 }
@@ -1955,13 +1987,18 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
  */
 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
 {
+        unsigned long flags;
+        u32 v;
+
         if (!oh->class->sysc ||
             !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
                 return -EINVAL;
 
-        mutex_lock(&oh->_mutex);
-        _enable_wakeup(oh);
-        mutex_unlock(&oh->_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
+        v = oh->_sysc_cache;
+        _enable_wakeup(oh, &v);
+        _write_sysconfig(v, oh);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -1980,13 +2017,18 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
  */
 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
 {
+        unsigned long flags;
+        u32 v;
+
         if (!oh->class->sysc ||
             !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
                 return -EINVAL;
 
-        mutex_lock(&oh->_mutex);
-        _disable_wakeup(oh);
-        mutex_unlock(&oh->_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
+        v = oh->_sysc_cache;
+        _disable_wakeup(oh, &v);
+        _write_sysconfig(v, oh);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return 0;
 }
@@ -2006,13 +2048,14 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
 int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
 {
         int ret;
+        unsigned long flags;
 
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&oh->_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
         ret = _assert_hardreset(oh, name);
-        mutex_unlock(&oh->_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return ret;
 }
@@ -2032,13 +2075,14 @@ int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
 int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
 {
         int ret;
+        unsigned long flags;
 
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&oh->_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
         ret = _deassert_hardreset(oh, name);
-        mutex_unlock(&oh->_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return ret;
 }
@@ -2057,13 +2101,14 @@ int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
 int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
 {
         int ret;
+        unsigned long flags;
 
         if (!oh)
                 return -EINVAL;
 
-        mutex_lock(&oh->_mutex);
+        spin_lock_irqsave(&oh->_lock, flags);
         ret = _read_hardreset(oh, name);
-        mutex_unlock(&oh->_mutex);
+        spin_unlock_irqrestore(&oh->_lock, flags);
 
         return ret;
 }
@@ -2075,9 +2120,8 @@ int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
  * @fn: callback function pointer to call for each hwmod in class @classname
  * @user: arbitrary context data to pass to the callback function
  *
- * For each omap_hwmod of class @classname, call @fn.  Takes
- * omap_hwmod_mutex to prevent the hwmod list from changing during the
- * iteration.  If the callback function returns something other than
+ * For each omap_hwmod of class @classname, call @fn.
+ * If the callback function returns something other than
  * zero, the iterator is terminated, and the callback function's return
  * value is passed back to the caller.  Returns 0 upon success, -EINVAL
  * if @classname or @fn are NULL, or passes back the error code from @fn.
@@ -2096,8 +2140,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
         pr_debug("omap_hwmod: %s: looking for modules of class %s\n",
                  __func__, classname);
 
-        mutex_lock(&omap_hwmod_mutex);
-
         list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
                 if (!strcmp(temp_oh->class->name, classname)) {
                         pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
@@ -2108,8 +2150,6 @@ int omap_hwmod_for_each_by_class(const char *classname,
                 }
         }
 
-        mutex_unlock(&omap_hwmod_mutex);
-
         if (ret)
                 pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
                          __func__, ret);
@@ -2117,3 +2157,64 @@ int omap_hwmod_for_each_by_class(const char *classname,
         return ret;
 }
 
+/**
+ * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod
+ * @oh: struct omap_hwmod *
+ * @state: state that _setup() should leave the hwmod in
+ *
+ * Sets the hwmod state that @oh will enter at the end of _setup() (called by
+ * omap_hwmod_late_init()).  Only valid to call between calls to
+ * omap_hwmod_init() and omap_hwmod_late_init().  Returns 0 upon success or
+ * -EINVAL if there is a problem with the arguments or if the hwmod is
+ * in the wrong state.
+ */
+int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
+{
+        int ret;
+        unsigned long flags;
+
+        if (!oh)
+                return -EINVAL;
+
+        if (state != _HWMOD_STATE_DISABLED &&
+            state != _HWMOD_STATE_ENABLED &&
+            state != _HWMOD_STATE_IDLE)
+                return -EINVAL;
+
+        spin_lock_irqsave(&oh->_lock, flags);
+
+        if (oh->_state != _HWMOD_STATE_REGISTERED) {
+                ret = -EINVAL;
+                goto ohsps_unlock;
+        }
+
+        oh->_postsetup_state = state;
+        ret = 0;
+
+ohsps_unlock:
+        spin_unlock_irqrestore(&oh->_lock, flags);
+
+        return ret;
+}
+
+/**
+ * omap_hwmod_get_context_loss_count - get lost context count
+ * @oh: struct omap_hwmod *
+ *
+ * Query the powerdomain of of @oh to get the context loss
+ * count for this device.
+ *
+ * Returns the context loss count of the powerdomain assocated with @oh
+ * upon success, or zero if no powerdomain exists for @oh.
+ */
+u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
+{
+        struct powerdomain *pwrdm;
+        int ret = 0;
+
+        pwrdm = omap_hwmod_get_pwrdm(oh);
+        if (pwrdm)
+                ret = pwrdm_get_context_loss_count(pwrdm);
+
+        return ret;
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index adf6e3632a2b..b85c630b64d6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,11 +16,14 @@
 #include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
+#include <plat/i2c.h>
+#include <plat/gpio.h>
 
 #include "omap_hwmod_common_data.h"
 
-#include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
+#include "wd_timer.h"
 
 /*
  * OMAP2420 hardware module integration data
@@ -36,6 +39,11 @@ static struct omap_hwmod omap2420_iva_hwmod;
 static struct omap_hwmod omap2420_l3_main_hwmod;
 static struct omap_hwmod omap2420_l4_core_hwmod;
 static struct omap_hwmod omap2420_wd_timer2_hwmod;
+static struct omap_hwmod omap2420_gpio1_hwmod;
+static struct omap_hwmod omap2420_gpio2_hwmod;
+static struct omap_hwmod omap2420_gpio3_hwmod;
+static struct omap_hwmod omap2420_gpio4_hwmod;
+static struct omap_hwmod omap2420_dma_system_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@@ -77,6 +85,8 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod;
 static struct omap_hwmod omap2420_uart1_hwmod;
 static struct omap_hwmod omap2420_uart2_hwmod;
 static struct omap_hwmod omap2420_uart3_hwmod;
+static struct omap_hwmod omap2420_i2c1_hwmod;
+static struct omap_hwmod omap2420_i2c2_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
@@ -139,6 +149,45 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN                128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_i2c1_hwmod,
+        .clk            = "i2c1_ick",
+        .addr           = omap2420_i2c1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_i2c1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_i2c2_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap2420_i2c2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_i2c2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
         &omap2420_l3_main__l4_core,
@@ -150,6 +199,8 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
         &omap2_l4_core__uart1,
         &omap2_l4_core__uart2,
         &omap2_l4_core__uart3,
+        &omap2420_l4_core__i2c1,
+        &omap2420_l4_core__i2c2
 };
 
 /* L4 CORE */
@@ -262,8 +313,9 @@ static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
 };
 
 static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
-        .name = "wd_timer",
-        .sysc = &omap2420_wd_timer_sysc,
+        .name           = "wd_timer",
+        .sysc           = &omap2420_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable
 };
 
 /* wd_timer2 */
@@ -418,6 +470,400 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x20,
+        .syss_offs      = 0x10,
+        .sysc_flags     = SYSC_HAS_SOFTRESET,
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+        .name           = "i2c",
+        .sysc           = &i2c_sysc,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr;
+
+/* I2C1 */
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
+        &omap2420_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap2420_i2c1_hwmod = {
+        .name           = "i2c1",
+        .mpu_irqs       = i2c1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
+        .sdma_reqs      = i2c1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
+        .main_clk       = "i2c1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2420_EN_I2C1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_i2c1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_16BIT_REG,
+};
+
+/* I2C2 */
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
+        &omap2420_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap2420_i2c2_hwmod = {
+        .name           = "i2c2",
+        .mpu_irqs       = i2c2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
+        .sdma_reqs      = i2c2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
+        .main_clk       = "i2c2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2420_EN_I2C2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_i2c2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_16BIT_REG,
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
+        {
+                .pa_start       = 0x48018000,
+                .pa_end         = 0x480181ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_gpio1_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2420_gpio1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_gpio1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio2 */
+static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
+        {
+                .pa_start       = 0x4801a000,
+                .pa_end         = 0x4801a1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_gpio2_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2420_gpio2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_gpio2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio3 */
+static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
+        {
+                .pa_start       = 0x4801c000,
+                .pa_end         = 0x4801c1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_gpio3_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2420_gpio3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_gpio3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio4 */
+static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
+        {
+                .pa_start       = 0x4801e000,
+                .pa_end         = 0x4801e1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_gpio4_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2420_gpio4_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2420_gpio4_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width = 32,
+        .dbck_flag = false,
+};
+
+static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
+        .name = "gpio",
+        .sysc = &omap242x_gpio_sysc,
+        .rev = 0,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
+        { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
+        &omap2420_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod omap2420_gpio1_hwmod = {
+        .name           = "gpio1",
+        .mpu_irqs       = omap242x_gpio1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio1_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2420_gpio1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
+        .class          = &omap242x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
+        { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
+        &omap2420_l4_wkup__gpio2,
+};
+
+static struct omap_hwmod omap2420_gpio2_hwmod = {
+        .name           = "gpio2",
+        .mpu_irqs       = omap242x_gpio2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio2_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2420_gpio2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
+        .class          = &omap242x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
+        { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
+        &omap2420_l4_wkup__gpio3,
+};
+
+static struct omap_hwmod omap2420_gpio3_hwmod = {
+        .name           = "gpio3",
+        .mpu_irqs       = omap242x_gpio3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio3_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2420_gpio3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
+        .class          = &omap242x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
+        { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
+        &omap2420_l4_wkup__gpio4,
+};
+
+static struct omap_hwmod omap2420_gpio4_hwmod = {
+        .name           = "gpio4",
+        .mpu_irqs       = omap242x_gpio4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap242x_gpio4_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2420_gpio4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
+        .class          = &omap242x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* system dma */
+static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_dma_hwmod_class = {
+        .name = "dma",
+        .sysc = &omap2420_dma_sysc,
+};
+
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                                IS_CSSA_32 | IS_CDSA_32,
+        .lch_count = 32,
+};
+
+static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+};
+
+static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x4a0560ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
+        .master         = &omap2420_dma_system_hwmod,
+        .slave          = &omap2420_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
+        &omap2420_dma_system__l3,
+};
+
+/* l4_core -> dma_system */
+static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_dma_system_hwmod,
+        .clk            = "sdma_ick",
+        .addr           = omap2420_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
+        &omap2420_l4_core__dma_system,
+};
+
+static struct omap_hwmod omap2420_dma_system_hwmod = {
+        .name           = "dma",
+        .class          = &omap2420_dma_hwmod_class,
+        .mpu_irqs       = omap2420_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_dma_system_irqs),
+        .main_clk       = "core_l3_ck",
+        .slaves         = omap2420_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
+        .masters        = omap2420_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
+        .dev_attr       = &dma_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
         &omap2420_l3_main_hwmod,
         &omap2420_l4_core_hwmod,
@@ -428,6 +874,17 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
         &omap2420_uart1_hwmod,
         &omap2420_uart2_hwmod,
         &omap2420_uart3_hwmod,
+        &omap2420_i2c1_hwmod,
+        &omap2420_i2c2_hwmod,
+
+        /* gpio class */
+        &omap2420_gpio1_hwmod,
+        &omap2420_gpio2_hwmod,
+        &omap2420_gpio3_hwmod,
+        &omap2420_gpio4_hwmod,
+
+        /* dma_system class*/
+        &omap2420_dma_system_hwmod,
         NULL,
 };
 
@@ -435,5 +892,3 @@ int __init omap2420_hwmod_init(void)
 {
         return omap_hwmod_init(omap2420_hwmods);
 }
-
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 12d939e456cf..8ecfbcde13ba 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -16,11 +16,14 @@
 #include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
+#include <plat/i2c.h>
+#include <plat/gpio.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
+#include "wd_timer.h"
 
 /*
  * OMAP2430 hardware module integration data
@@ -36,6 +39,12 @@ static struct omap_hwmod omap2430_iva_hwmod;
 static struct omap_hwmod omap2430_l3_main_hwmod;
 static struct omap_hwmod omap2430_l4_core_hwmod;
 static struct omap_hwmod omap2430_wd_timer2_hwmod;
+static struct omap_hwmod omap2430_gpio1_hwmod;
+static struct omap_hwmod omap2430_gpio2_hwmod;
+static struct omap_hwmod omap2430_gpio3_hwmod;
+static struct omap_hwmod omap2430_gpio4_hwmod;
+static struct omap_hwmod omap2430_gpio5_hwmod;
+static struct omap_hwmod omap2430_dma_system_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -77,6 +86,47 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod;
 static struct omap_hwmod omap2430_uart1_hwmod;
 static struct omap_hwmod omap2430_uart2_hwmod;
 static struct omap_hwmod omap2430_uart3_hwmod;
+static struct omap_hwmod omap2430_i2c1_hwmod;
+static struct omap_hwmod omap2430_i2c2_hwmod;
+
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN                128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_i2c1_hwmod,
+        .clk            = "i2c1_ick",
+        .addr           = omap2430_i2c1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_i2c1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_i2c2_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap2430_i2c2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_i2c2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -262,8 +312,9 @@ static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
 };
 
 static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
-        .name = "wd_timer",
-        .sysc = &omap2430_wd_timer_sysc,
+        .name           = "wd_timer",
+        .sysc           = &omap2430_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable
 };
 
 /* wd_timer2 */
@@ -418,6 +469,456 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 };
 
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x20,
+        .syss_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class i2c_class = {
+        .name           = "i2c",
+        .sysc           = &i2c_sysc,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .fifo_depth     = 8, /* bytes */
+};
+
+/* I2C1 */
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
+        &omap2430_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap2430_i2c1_hwmod = {
+        .name           = "i2c1",
+        .mpu_irqs       = i2c1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
+        .sdma_reqs      = i2c1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
+        .main_clk       = "i2chs1_fck",
+        .prcm           = {
+                .omap2 = {
+                        /*
+                         * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
+                         * I2CHS IP's do not follow the usual pattern.
+                         * prcm_reg_id alone cannot be used to program
+                         * the iclk and fclk. Needs to be handled using
+                         * additonal flags when clk handling is moved
+                         * to hwmod framework.
+                         */
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_i2c1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* I2C2 */
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
+        &omap2430_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap2430_i2c2_hwmod = {
+        .name           = "i2c2",
+        .mpu_irqs       = i2c2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
+        .sdma_reqs      = i2c2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
+        .main_clk       = "i2chs2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_i2c2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
+        {
+                .pa_start       = 0x4900C000,
+                .pa_end         = 0x4900C1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_gpio1_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_gpio1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio2 */
+static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
+        {
+                .pa_start       = 0x4900E000,
+                .pa_end         = 0x4900E1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_gpio2_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_gpio2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio3 */
+static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
+        {
+                .pa_start       = 0x49010000,
+                .pa_end         = 0x490101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_gpio3_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_gpio3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio4 */
+static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
+        {
+                .pa_start       = 0x49012000,
+                .pa_end         = 0x490121ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_gpio4_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio4_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_gpio4_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_core -> gpio5 */
+static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
+        {
+                .pa_start       = 0x480B6000,
+                .pa_end         = 0x480B61ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_gpio5_hwmod,
+        .clk            = "gpio5_ick",
+        .addr           = omap2430_gpio5_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_gpio5_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width = 32,
+        .dbck_flag = false,
+};
+
+static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
+        .name = "gpio",
+        .sysc = &omap243x_gpio_sysc,
+        .rev = 0,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
+        { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
+        &omap2430_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod omap2430_gpio1_hwmod = {
+        .name           = "gpio1",
+        .mpu_irqs       = omap243x_gpio1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio1_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2430_gpio1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
+        .class          = &omap243x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
+        { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
+        &omap2430_l4_wkup__gpio2,
+};
+
+static struct omap_hwmod omap2430_gpio2_hwmod = {
+        .name           = "gpio2",
+        .mpu_irqs       = omap243x_gpio2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio2_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2430_gpio2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
+        .class          = &omap243x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
+        { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
+        &omap2430_l4_wkup__gpio3,
+};
+
+static struct omap_hwmod omap2430_gpio3_hwmod = {
+        .name           = "gpio3",
+        .mpu_irqs       = omap243x_gpio3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio3_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2430_gpio3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
+        .class          = &omap243x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
+        { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
+        &omap2430_l4_wkup__gpio4,
+};
+
+static struct omap_hwmod omap2430_gpio4_hwmod = {
+        .name           = "gpio4",
+        .mpu_irqs       = omap243x_gpio4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio4_irqs),
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .slaves         = omap2430_gpio4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
+        .class          = &omap243x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* gpio5 */
+static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
+        { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
+        &omap2430_l4_core__gpio5,
+};
+
+static struct omap_hwmod omap2430_gpio5_hwmod = {
+        .name           = "gpio5",
+        .mpu_irqs       = omap243x_gpio5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap243x_gpio5_irqs),
+        .main_clk       = "gpio5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP2430_EN_GPIO5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
+                },
+        },
+        .slaves         = omap2430_gpio5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
+        .class          = &omap243x_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* dma_system */
+static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_dma_hwmod_class = {
+        .name = "dma",
+        .sysc = &omap2430_dma_sysc,
+};
+
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count = 32,
+};
+
+static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+};
+
+static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x4a0560ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
+        .master         = &omap2430_dma_system_hwmod,
+        .slave          = &omap2430_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
+        &omap2430_dma_system__l3,
+};
+
+/* l4_core -> dma_system */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_dma_system_hwmod,
+        .clk            = "sdma_ick",
+        .addr           = omap2430_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
+        &omap2430_l4_core__dma_system,
+};
+
+static struct omap_hwmod omap2430_dma_system_hwmod = {
+        .name           = "dma",
+        .class          = &omap2430_dma_hwmod_class,
+        .mpu_irqs       = omap2430_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_dma_system_irqs),
+        .main_clk       = "core_l3_ck",
+        .slaves         = omap2430_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
+        .masters        = omap2430_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
+        .dev_attr       = &dma_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         &omap2430_l3_main_hwmod,
         &omap2430_l4_core_hwmod,
@@ -428,6 +929,18 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         &omap2430_uart1_hwmod,
         &omap2430_uart2_hwmod,
         &omap2430_uart3_hwmod,
+        &omap2430_i2c1_hwmod,
+        &omap2430_i2c2_hwmod,
+
+        /* gpio class */
+        &omap2430_gpio1_hwmod,
+        &omap2430_gpio2_hwmod,
+        &omap2430_gpio3_hwmod,
+        &omap2430_gpio4_hwmod,
+        &omap2430_gpio5_hwmod,
+
+        /* dma_system class*/
+        &omap2430_dma_system_hwmod,
         NULL,
 };
 
@@ -435,5 +948,3 @@ int __init omap2430_hwmod_init(void)
 {
         return omap_hwmod_init(omap2430_hwmods);
 }
-
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index cb97ecf0a3f6..8d8181334f86 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -18,11 +18,16 @@
 #include <plat/cpu.h>
 #include <plat/dma.h>
 #include <plat/serial.h>
+#include <plat/l4_3xxx.h>
+#include <plat/i2c.h>
+#include <plat/gpio.h>
+#include <plat/smartreflex.h>
 
 #include "omap_hwmod_common_data.h"
 
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
+#include "wd_timer.h"
 
 /*
  * OMAP3xxx hardware module integration data
@@ -39,6 +44,19 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod;
 static struct omap_hwmod omap3xxx_l4_core_hwmod;
 static struct omap_hwmod omap3xxx_l4_per_hwmod;
 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
+static struct omap_hwmod omap3xxx_i2c1_hwmod;
+static struct omap_hwmod omap3xxx_i2c2_hwmod;
+static struct omap_hwmod omap3xxx_i2c3_hwmod;
+static struct omap_hwmod omap3xxx_gpio1_hwmod;
+static struct omap_hwmod omap3xxx_gpio2_hwmod;
+static struct omap_hwmod omap3xxx_gpio3_hwmod;
+static struct omap_hwmod omap3xxx_gpio4_hwmod;
+static struct omap_hwmod omap3xxx_gpio5_hwmod;
+static struct omap_hwmod omap3xxx_gpio6_hwmod;
+static struct omap_hwmod omap34xx_sr1_hwmod;
+static struct omap_hwmod omap34xx_sr2_hwmod;
+
+static struct omap_hwmod omap3xxx_dma_system_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -169,9 +187,125 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* I2C IP block address space length (in bytes) */
+#define OMAP2_I2C_AS_LEN                128
+
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c1_hwmod,
+        .clk            = "i2c1_ick",
+        .addr           = omap3xxx_i2c1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
+                        .l4_prot_group = 7,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c2_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap3xxx_i2c2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
+                        .l4_prot_group = 7,
+                        .flags = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> I2C3 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
+        {
+                .pa_start       = 0x48060000,
+                .pa_end         = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c3_hwmod,
+        .clk            = "i2c3_ick",
+        .addr           = omap3xxx_i2c3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
+                        .l4_prot_group = 7,
+                        .flags = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
+        {
+                .pa_start       = OMAP34XX_SR1_BASE,
+                .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_sr1_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3_sr1_addr_space),
+        .user           = OCP_USER_MPU,
+};
+
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
+        {
+                .pa_start       = OMAP34XX_SR2_BASE,
+                .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_sr2_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3_sr2_addr_space),
+        .user           = OCP_USER_MPU,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
         &omap3xxx_l3_main__l4_core,
+        &omap3_l4_core__sr1,
+        &omap3_l4_core__sr2,
 };
 
 /* Master interfaces on the L4_CORE interconnect */
@@ -179,6 +313,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
         &omap3xxx_l4_core__l4_wkup,
         &omap3_l4_core__uart1,
         &omap3_l4_core__uart2,
+        &omap3_l4_core__i2c1,
+        &omap3_l4_core__i2c2,
+        &omap3_l4_core__i2c3,
 };
 
 /* L4 CORE */
@@ -315,9 +452,22 @@ static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
         .sysc_fields    = &omap_hwmod_sysc_type1,
 };
 
+/* I2C common */
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
+        .rev_offs       = 0x00,
+        .sysc_offs      = 0x20,
+        .syss_offs      = 0x10,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
-        .name = "wd_timer",
-        .sysc = &omap3xxx_wd_timer_sysc,
+        .name           = "wd_timer",
+        .sysc           = &omap3xxx_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable
 };
 
 /* wd_timer2 */
@@ -509,6 +659,703 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 
+static struct omap_hwmod_class i2c_class = {
+        .name = "i2c",
+        .sysc = &i2c_sysc,
+};
+
+/* I2C1 */
+
+static struct omap_i2c_dev_attr i2c1_dev_attr = {
+        .fifo_depth     = 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C1_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
+        &omap3_l4_core__i2c1,
+};
+
+static struct omap_hwmod omap3xxx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .mpu_irqs       = i2c1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
+        .sdma_reqs      = i2c1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
+        .main_clk       = "i2c1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_I2C1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_i2c1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c1_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* I2C2 */
+
+static struct omap_i2c_dev_attr i2c2_dev_attr = {
+        .fifo_depth     = 8, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
+        { .irq = INT_24XX_I2C2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
+        &omap3_l4_core__i2c2,
+};
+
+static struct omap_hwmod omap3xxx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .mpu_irqs       = i2c2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
+        .sdma_reqs      = i2c2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
+        .main_clk       = "i2c2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_I2C2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_i2c2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c2_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* I2C3 */
+
+static struct omap_i2c_dev_attr i2c3_dev_attr = {
+        .fifo_depth     = 64, /* bytes */
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+        { .irq = INT_34XX_I2C3_IRQ, },
+};
+
+static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
+        { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
+        &omap3_l4_core__i2c3,
+};
+
+static struct omap_hwmod omap3xxx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .mpu_irqs       = i2c3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
+        .sdma_reqs      = i2c3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
+        .main_clk       = "i2c3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_I2C3_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_i2c3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
+        .class          = &i2c_class,
+        .dev_attr       = &i2c3_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x48310000,
+                .pa_end         = 0x483101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_gpio1_hwmod,
+        .addr           = omap3xxx_gpio1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x49050000,
+                .pa_end         = 0x490501ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio2_hwmod,
+        .addr           = omap3xxx_gpio2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x49052000,
+                .pa_end         = 0x490521ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio3_hwmod,
+        .addr           = omap3xxx_gpio3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
+        {
+                .pa_start       = 0x49054000,
+                .pa_end         = 0x490541ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio4_hwmod,
+        .addr           = omap3xxx_gpio4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
+        {
+                .pa_start       = 0x49056000,
+                .pa_end         = 0x490561ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio5_hwmod,
+        .addr           = omap3xxx_gpio5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
+        {
+                .pa_start       = 0x49058000,
+                .pa_end         = 0x490581ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio6_hwmod,
+        .addr           = omap3xxx_gpio6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
+        .name = "gpio",
+        .sysc = &omap3xxx_gpio_sysc,
+        .rev = 1,
+};
+
+/* gpio_dev_attr*/
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width = 32,
+        .dbck_flag = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
+        { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
+        &omap3xxx_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod omap3xxx_gpio1_hwmod = {
+        .name           = "gpio1",
+        .mpu_irqs       = omap3xxx_gpio1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
+        .main_clk       = "gpio1_ick",
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
+        { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
+        &omap3xxx_l4_per__gpio2,
+};
+
+static struct omap_hwmod omap3xxx_gpio2_hwmod = {
+        .name           = "gpio2",
+        .mpu_irqs       = omap3xxx_gpio2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
+        .main_clk       = "gpio2_ick",
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO2_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
+        { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
+        &omap3xxx_l4_per__gpio3,
+};
+
+static struct omap_hwmod omap3xxx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .mpu_irqs       = omap3xxx_gpio3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
+        .main_clk       = "gpio3_ick",
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO3_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
+        { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio4_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
+        &omap3xxx_l4_per__gpio4,
+};
+
+static struct omap_hwmod omap3xxx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .mpu_irqs       = omap3xxx_gpio4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
+        .main_clk       = "gpio4_ick",
+        .opt_clks       = gpio4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO4_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio5 */
+static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
+        { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
+};
+
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio5_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
+        &omap3xxx_l4_per__gpio5,
+};
+
+static struct omap_hwmod omap3xxx_gpio5_hwmod = {
+        .name           = "gpio5",
+        .mpu_irqs       = omap3xxx_gpio5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
+        .main_clk       = "gpio5_ick",
+        .opt_clks       = gpio5_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO5_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* gpio6 */
+static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
+        { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
+};
+
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio6_dbck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
+        &omap3xxx_l4_per__gpio6,
+};
+
+static struct omap_hwmod omap3xxx_gpio6_hwmod = {
+        .name           = "gpio6",
+        .mpu_irqs       = omap3xxx_gpio6_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
+        .main_clk       = "gpio6_ick",
+        .opt_clks       = gpio6_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPIO6_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_gpio6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
+        .class          = &omap3xxx_gpio_hwmod_class,
+        .dev_attr       = &gpio_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
+        .master         = &omap3xxx_dma_system_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma attributes */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count = 32,
+};
+
+static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
+        .name = "dma",
+        .sysc = &omap3xxx_dma_sysc,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+        { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+        { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+        { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+};
+
+static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x4a0560ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
+        &omap3xxx_dma_system__l3,
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dma_system_hwmod,
+        .clk            = "core_l4_ick",
+        .addr           = omap3xxx_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
+        &omap3xxx_l4_core__dma_system,
+};
+
+static struct omap_hwmod omap3xxx_dma_system_hwmod = {
+        .name           = "dma",
+        .class          = &omap3xxx_dma_hwmod_class,
+        .mpu_irqs       = omap3xxx_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
+        .main_clk       = "core_l3_ick",
+        .prcm = {
+                .omap2 = {
+                        .module_offs            = CORE_MOD,
+                        .prcm_reg_id            = 1,
+                        .module_bit             = OMAP3430_ST_SDMA_SHIFT,
+                        .idlest_reg_id          = 1,
+                        .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
+        .masters        = omap3xxx_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
+        .dev_attr       = &dma_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/* SR common */
+static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
+        .clkact_shift   = 20,
+};
+
+static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
+        .sysc_offs      = 0x24,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
+        .clockact       = CLOCKACT_TEST_ICLK,
+        .sysc_fields    = &omap34xx_sr_sysc_fields,
+};
+
+static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
+        .name = "smartreflex",
+        .sysc = &omap34xx_sr_sysc,
+        .rev  = 1,
+};
+
+static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
+        .sidle_shift    = 24,
+        .enwkup_shift   = 26
+};
+
+static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
+        .sysc_offs      = 0x38,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                        SYSC_NO_CACHE),
+        .sysc_fields    = &omap36xx_sr_sysc_fields,
+};
+
+static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
+        .name = "smartreflex",
+        .sysc = &omap36xx_sr_sysc,
+        .rev  = 2,
+};
+
+/* SR1 */
+static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
+        &omap3_l4_core__sr1,
+};
+
+static struct omap_hwmod omap34xx_sr1_hwmod = {
+        .name           = "sr1_hwmod",
+        .class          = &omap34xx_smartreflex_hwmod_class,
+        .main_clk       = "sr1_fck",
+        .vdd_name       = "mpu",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SR1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
+                },
+        },
+        .slaves         = omap3_sr1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
+                                        CHIP_IS_OMAP3430ES3_0 |
+                                        CHIP_IS_OMAP3430ES3_1),
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+};
+
+static struct omap_hwmod omap36xx_sr1_hwmod = {
+        .name           = "sr1_hwmod",
+        .class          = &omap36xx_smartreflex_hwmod_class,
+        .main_clk       = "sr1_fck",
+        .vdd_name       = "mpu",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SR1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
+                },
+        },
+        .slaves         = omap3_sr1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
+/* SR2 */
+static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
+        &omap3_l4_core__sr2,
+};
+
+static struct omap_hwmod omap34xx_sr2_hwmod = {
+        .name           = "sr2_hwmod",
+        .class          = &omap34xx_smartreflex_hwmod_class,
+        .main_clk       = "sr2_fck",
+        .vdd_name       = "core",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SR2_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
+                },
+        },
+        .slaves         = omap3_sr2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
+                                        CHIP_IS_OMAP3430ES3_0 |
+                                        CHIP_IS_OMAP3430ES3_1),
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+};
+
+static struct omap_hwmod omap36xx_sr2_hwmod = {
+        .name           = "sr2_hwmod",
+        .class          = &omap36xx_smartreflex_hwmod_class,
+        .main_clk       = "sr2_fck",
+        .vdd_name       = "core",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SR2_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
+                },
+        },
+        .slaves         = omap3_sr2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l3_main_hwmod,
         &omap3xxx_l4_core_hwmod,
@@ -521,6 +1368,25 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_uart2_hwmod,
         &omap3xxx_uart3_hwmod,
         &omap3xxx_uart4_hwmod,
+        &omap3xxx_i2c1_hwmod,
+        &omap3xxx_i2c2_hwmod,
+        &omap3xxx_i2c3_hwmod,
+        &omap34xx_sr1_hwmod,
+        &omap34xx_sr2_hwmod,
+        &omap36xx_sr1_hwmod,
+        &omap36xx_sr2_hwmod,
+
+
+        /* gpio class */
+        &omap3xxx_gpio1_hwmod,
+        &omap3xxx_gpio2_hwmod,
+        &omap3xxx_gpio3_hwmod,
+        &omap3xxx_gpio4_hwmod,
+        &omap3xxx_gpio5_hwmod,
+        &omap3xxx_gpio6_hwmod,
+
+        /* dma_system class*/
+        &omap3xxx_dma_system_hwmod,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7274db4de487..c2806bd11fbf 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,11 +22,16 @@
 
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
+#include <plat/gpio.h>
+#include <plat/dma.h>
 
 #include "omap_hwmod_common_data.h"
 
-#include "cm.h"
+#include "cm1_44xx.h"
+#include "cm2_44xx.h"
+#include "prm44xx.h"
 #include "prm-regbits-44xx.h"
+#include "wd_timer.h"
 
 /* Base offset for all OMAP4 interrupts external to MPUSS */
 #define OMAP44XX_IRQ_GIC_START  32
@@ -35,8 +40,11 @@
 #define OMAP44XX_DMA_REQ_START  1
 
 /* Backward references (IPs with Bus Master capability) */
+static struct omap_hwmod omap44xx_dma_system_hwmod;
 static struct omap_hwmod omap44xx_dmm_hwmod;
+static struct omap_hwmod omap44xx_dsp_hwmod;
 static struct omap_hwmod omap44xx_emif_fw_hwmod;
+static struct omap_hwmod omap44xx_iva_hwmod;
 static struct omap_hwmod omap44xx_l3_instr_hwmod;
 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
@@ -58,7 +66,7 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod;
  * instance(s): dmm
  */
 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
-        .name = "dmm",
+        .name   = "dmm",
 };
 
 /* dmm interface data */
@@ -67,7 +75,15 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
         .master         = &omap44xx_l3_main_1_hwmod,
         .slave          = &omap44xx_dmm_hwmod,
         .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .user           = OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
+        {
+                .pa_start       = 0x4e000000,
+                .pa_end         = 0x4e0007ff,
+                .flags          = ADDR_TYPE_RT
+        },
 };
 
 /* mpu -> dmm */
@@ -75,7 +91,9 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
         .master         = &omap44xx_mpu_hwmod,
         .slave          = &omap44xx_dmm_hwmod,
         .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .addr           = omap44xx_dmm_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
+        .user           = OCP_USER_MPU,
 };
 
 /* dmm slave ports */
@@ -103,7 +121,7 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
  * instance(s): emif_fw
  */
 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
-        .name = "emif_fw",
+        .name   = "emif_fw",
 };
 
 /* emif_fw interface data */
@@ -115,12 +133,22 @@ static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
+        {
+                .pa_start       = 0x4a20c000,
+                .pa_end         = 0x4a20c0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
 /* l4_cfg -> emif_fw */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_emif_fw_hwmod,
         .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .addr           = omap44xx_emif_fw_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
+        .user           = OCP_USER_MPU,
 };
 
 /* emif_fw slave ports */
@@ -142,10 +170,18 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  */
 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
-        .name = "l3",
+        .name   = "l3",
 };
 
 /* l3_instr interface data */
+/* iva -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
+        .master         = &omap44xx_iva_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l3_main_3 -> l3_instr */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
         .master         = &omap44xx_l3_main_3_hwmod,
@@ -156,6 +192,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 
 /* l3_instr slave ports */
 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
+        &omap44xx_iva__l3_instr,
         &omap44xx_l3_main_3__l3_instr,
 };
 
@@ -167,6 +204,15 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
+/* l3_main_1 interface data */
+/* dsp -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l3_main_2 -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
         .master         = &omap44xx_l3_main_2_hwmod,
@@ -193,6 +239,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 
 /* l3_main_1 slave ports */
 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
+        &omap44xx_dsp__l3_main_1,
         &omap44xx_l3_main_2__l3_main_1,
         &omap44xx_l4_cfg__l3_main_1,
         &omap44xx_mpu__l3_main_1,
@@ -207,6 +254,22 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 };
 
 /* l3_main_2 interface data */
+/* dma_system -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
+        .master         = &omap44xx_dma_system_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* iva -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
+        .master         = &omap44xx_iva_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l3_main_1 -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
         .master         = &omap44xx_l3_main_1_hwmod,
@@ -225,6 +288,8 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 
 /* l3_main_2 slave ports */
 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
+        &omap44xx_dma_system__l3_main_2,
+        &omap44xx_iva__l3_main_2,
         &omap44xx_l3_main_1__l3_main_2,
         &omap44xx_l4_cfg__l3_main_2,
 };
@@ -282,10 +347,18 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
  */
 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
-        .name = "l4",
+        .name   = "l4",
 };
 
 /* l4_abe interface data */
+/* dsp -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* l3_main_1 -> l4_abe */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
         .master         = &omap44xx_l3_main_1_hwmod,
@@ -304,6 +377,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 
 /* l4_abe slave ports */
 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
+        &omap44xx_dsp__l4_abe,
         &omap44xx_l3_main_1__l4_abe,
         &omap44xx_mpu__l4_abe,
 };
@@ -387,7 +461,7 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
  * instance(s): mpu_private
  */
 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
-        .name = "mpu_bus",
+        .name   = "mpu_bus",
 };
 
 /* mpu_private interface data */
@@ -413,12 +487,960 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 };
 
 /*
+ * Modules omap_hwmod structures
+ *
+ * The following IPs are excluded for the moment because:
+ * - They do not need an explicit SW control using omap_hwmod API.
+ * - They still need to be validated with the driver
+ *   properly adapted to omap_hwmod / omap_device
+ *
+ *  aess
+ *  bandgap
+ *  c2c
+ *  c2c_target_fw
+ *  cm_core
+ *  cm_core_aon
+ *  counter_32k
+ *  ctrl_module_core
+ *  ctrl_module_pad_core
+ *  ctrl_module_pad_wkup
+ *  ctrl_module_wkup
+ *  debugss
+ *  dmic
+ *  dss
+ *  dss_dispc
+ *  dss_dsi1
+ *  dss_dsi2
+ *  dss_hdmi
+ *  dss_rfbi
+ *  dss_venc
+ *  efuse_ctrl_cust
+ *  efuse_ctrl_std
+ *  elm
+ *  emif1
+ *  emif2
+ *  fdif
+ *  gpmc
+ *  gpu
+ *  hdq1w
+ *  hsi
+ *  ipu
+ *  iss
+ *  kbd
+ *  mailbox
+ *  mcasp
+ *  mcbsp1
+ *  mcbsp2
+ *  mcbsp3
+ *  mcbsp4
+ *  mcpdm
+ *  mcspi1
+ *  mcspi2
+ *  mcspi3
+ *  mcspi4
+ *  mmc1
+ *  mmc2
+ *  mmc3
+ *  mmc4
+ *  mmc5
+ *  mpu_c0
+ *  mpu_c1
+ *  ocmc_ram
+ *  ocp2scp_usb_phy
+ *  ocp_wp_noc
+ *  prcm
+ *  prcm_mpu
+ *  prm
+ *  scrm
+ *  sl2if
+ *  slimbus1
+ *  slimbus2
+ *  spinlock
+ *  timer1
+ *  timer10
+ *  timer11
+ *  timer2
+ *  timer3
+ *  timer4
+ *  timer5
+ *  timer6
+ *  timer7
+ *  timer8
+ *  timer9
+ *  usb_host_fs
+ *  usb_host_hs
+ *  usb_otg_hs
+ *  usb_phy_cm
+ *  usb_tll_hs
+ *  usim
+ */
+
+/*
+ * 'dma' class
+ * dma controller for data exchange between memory to memory (i.e. internal or
+ * external memory) and gp peripherals to memory or memory to gp peripherals
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
+        .name   = "dma",
+        .sysc   = &omap44xx_dma_sysc,
+};
+
+/* dma dev_attr */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                          IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count      = 32,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
+        { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
+        { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
+        { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
+};
+
+/* dma_system master ports */
+static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
+        &omap44xx_dma_system__l3_main_2,
+};
+
+static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x4a056000,
+                .pa_end         = 0x4a0560ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_dma_system_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dma_system_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dma_system slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
+        &omap44xx_l4_cfg__dma_system,
+};
+
+static struct omap_hwmod omap44xx_dma_system_hwmod = {
+        .name           = "dma_system",
+        .class          = &omap44xx_dma_hwmod_class,
+        .mpu_irqs       = omap44xx_dma_system_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
+        .main_clk       = "l3_div_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
+                },
+        },
+        .dev_attr       = &dma_dev_attr,
+        .slaves         = omap44xx_dma_system_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
+        .masters        = omap44xx_dma_system_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'dsp' class
+ * dsp sub-system
+ */
+
+static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
+        .name   = "dsp",
+};
+
+/* dsp */
+static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
+        { .irq = 28 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
+        { .name = "dsp", .rst_shift = 0 },
+};
+
+/* dsp -> iva */
+static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_iva_hwmod,
+        .clk            = "dpll_iva_m5x2_ck",
+};
+
+/* dsp master ports */
+static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
+        &omap44xx_dsp__l3_main_1,
+        &omap44xx_dsp__l4_abe,
+        &omap44xx_dsp__iva,
+};
+
+/* l4_cfg -> dsp */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_dsp_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* dsp slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
+        &omap44xx_l4_cfg__dsp,
+};
+
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
+        .name           = "dsp_c0",
+        .class          = &omap44xx_dsp_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .rst_lines      = omap44xx_dsp_c0_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
+        .prcm = {
+                .omap4 = {
+                        .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+                },
+        },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct omap_hwmod omap44xx_dsp_hwmod = {
+        .name           = "dsp",
+        .class          = &omap44xx_dsp_hwmod_class,
+        .mpu_irqs       = omap44xx_dsp_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
+        .rst_lines      = omap44xx_dsp_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
+        .main_clk       = "dsp_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
+                        .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+                },
+        },
+        .slaves         = omap44xx_dsp_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
+        .masters        = omap44xx_dsp_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
+        .name   = "gpio",
+        .sysc   = &omap44xx_gpio_sysc,
+        .rev    = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width     = 32,
+        .dbck_flag      = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod omap44xx_gpio1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
+        { .irq = 29 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x4a310000,
+                .pa_end         = 0x4a3101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_gpio1_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_gpio1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
+        &omap44xx_l4_wkup__gpio1,
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio1_hwmod = {
+        .name           = "gpio1",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .mpu_irqs       = omap44xx_gpio1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
+        .main_clk       = "gpio1_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio2 */
+static struct omap_hwmod omap44xx_gpio2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
+        { .irq = 30 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x48055000,
+                .pa_end         = 0x480551ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
+        &omap44xx_l4_per__gpio2,
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio2_hwmod = {
+        .name           = "gpio2",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap44xx_gpio2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
+        .main_clk       = "gpio2_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio3 */
+static struct omap_hwmod omap44xx_gpio3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
+        { .irq = 31 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x48057000,
+                .pa_end         = 0x480571ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
+        &omap44xx_l4_per__gpio3,
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap44xx_gpio3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
+        .main_clk       = "gpio3_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio4 */
+static struct omap_hwmod omap44xx_gpio4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
+        { .irq = 32 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
+        {
+                .pa_start       = 0x48059000,
+                .pa_end         = 0x480591ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
+        &omap44xx_l4_per__gpio4,
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap44xx_gpio4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
+        .main_clk       = "gpio4_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio5 */
+static struct omap_hwmod omap44xx_gpio5_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
+        { .irq = 33 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
+        {
+                .pa_start       = 0x4805b000,
+                .pa_end         = 0x4805b1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio5_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio5 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
+        &omap44xx_l4_per__gpio5,
+};
+
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio5_hwmod = {
+        .name           = "gpio5",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap44xx_gpio5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
+        .main_clk       = "gpio5_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio5_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* gpio6 */
+static struct omap_hwmod omap44xx_gpio6_hwmod;
+static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
+        { .irq = 34 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
+        {
+                .pa_start       = 0x4805d000,
+                .pa_end         = 0x4805d1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio6_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* gpio6 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
+        &omap44xx_l4_per__gpio6,
+};
+
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio6_dbclk" },
+};
+
+static struct omap_hwmod omap44xx_gpio6_hwmod = {
+        .name           = "gpio6",
+        .class          = &omap44xx_gpio_hwmod_class,
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap44xx_gpio6_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
+        .main_clk       = "gpio6_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+                },
+        },
+        .opt_clks       = gpio6_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+        .slaves         = omap44xx_gpio6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'i2c' class
+ * multimaster high-speed i2c controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0090,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
+        .name   = "i2c",
+        .sysc   = &omap44xx_i2c_sysc,
+};
+
+/* i2c1 */
+static struct omap_hwmod omap44xx_i2c1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
+        { .irq = 56 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x480700ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
+        &omap44xx_l4_per__i2c1,
+};
+
+static struct omap_hwmod omap44xx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .class          = &omap44xx_i2c_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_i2c1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
+        .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
+        .main_clk       = "i2c1_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_i2c1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c2 */
+static struct omap_hwmod omap44xx_i2c2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
+        { .irq = 57 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x480720ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
+        &omap44xx_l4_per__i2c2,
+};
+
+static struct omap_hwmod omap44xx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .class          = &omap44xx_i2c_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_i2c2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
+        .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
+        .main_clk       = "i2c2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_i2c2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c3 */
+static struct omap_hwmod omap44xx_i2c3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
+        { .irq = 61 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
+        {
+                .pa_start       = 0x48060000,
+                .pa_end         = 0x480600ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
+        &omap44xx_l4_per__i2c3,
+};
+
+static struct omap_hwmod omap44xx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .class          = &omap44xx_i2c_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_i2c3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
+        .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
+        .main_clk       = "i2c3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_i2c3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* i2c4 */
+static struct omap_hwmod omap44xx_i2c4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
+        { .irq = 62 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
+        {
+                .pa_start       = 0x48350000,
+                .pa_end         = 0x483500ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* i2c4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
+        &omap44xx_l4_per__i2c4,
+};
+
+static struct omap_hwmod omap44xx_i2c4_hwmod = {
+        .name           = "i2c4",
+        .class          = &omap44xx_i2c_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_i2c4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
+        .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
+        .main_clk       = "i2c4_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_i2c4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'iva' class
+ * multi-standard video encoder/decoder hardware accelerator
+ */
+
+static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
+        .name   = "iva",
+};
+
+/* iva */
+static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
+        { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
+        { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
+        { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
+        { .name = "logic", .rst_shift = 2 },
+};
+
+static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
+        { .name = "seq0", .rst_shift = 0 },
+};
+
+static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
+        { .name = "seq1", .rst_shift = 1 },
+};
+
+/* iva master ports */
+static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
+        &omap44xx_iva__l3_main_2,
+        &omap44xx_iva__l3_instr,
+};
+
+static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
+        {
+                .pa_start       = 0x5a000000,
+                .pa_end         = 0x5a07ffff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l3_main_2 -> iva */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_iva_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_iva_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* iva slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
+        &omap44xx_dsp__iva,
+        &omap44xx_l3_main_2__iva,
+};
+
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
+        .name           = "iva_seq0",
+        .class          = &omap44xx_iva_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .rst_lines      = omap44xx_iva_seq0_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
+        .prcm = {
+                .omap4 = {
+                        .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+                },
+        },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* Pseudo hwmod for reset control purpose only */
+static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
+        .name           = "iva_seq1",
+        .class          = &omap44xx_iva_hwmod_class,
+        .flags          = HWMOD_INIT_NO_RESET,
+        .rst_lines      = omap44xx_iva_seq1_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
+        .prcm = {
+                .omap4 = {
+                        .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+                },
+        },
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+static struct omap_hwmod omap44xx_iva_hwmod = {
+        .name           = "iva",
+        .class          = &omap44xx_iva_hwmod_class,
+        .mpu_irqs       = omap44xx_iva_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
+        .rst_lines      = omap44xx_iva_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
+        .main_clk       = "iva_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
+                        .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+                },
+        },
+        .slaves         = omap44xx_iva_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
+        .masters        = omap44xx_iva_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
  * 'mpu' class
  * mpu sub-system
  */
 
 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
-        .name = "mpu",
+        .name   = "mpu",
 };
 
 /* mpu */
@@ -453,58 +1475,189 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
 };
 
 /*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
+ * 'smartreflex' class
+ * smartreflex module (monitor silicon performance and outputs a measure of
+ * performance error)
  */
 
-static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
-                           SYSC_HAS_SOFTRESET),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
+        .sidle_shift    = 24,
+        .enwkup_shift   = 26,
 };
 
-/*
- * 'uart' class
- * universal asynchronous receiver/transmitter (uart)
- */
+static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
+        .sysc_offs      = 0x0038,
+        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
+};
 
-static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
-        .rev_offs       = 0x0050,
-        .sysc_offs      = 0x0054,
-        .syss_offs      = 0x0058,
-        .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
+static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
+        .name   = "smartreflex",
+        .sysc   = &omap44xx_smartreflex_sysc,
+        .rev    = 2,
 };
 
-static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
-        .name = "wd_timer",
-        .sysc = &omap44xx_wd_timer_sysc,
+/* smartreflex_core */
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
+        { .irq = 19 + OMAP44XX_IRQ_GIC_START },
 };
 
-/* wd_timer2 */
-static struct omap_hwmod omap44xx_wd_timer2_hwmod;
-static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
-        { .irq = 80 + OMAP44XX_IRQ_GIC_START },
+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+        {
+                .pa_start       = 0x4a0dd000,
+                .pa_end         = 0x4a0dd03f,
+                .flags          = ADDR_TYPE_RT
+        },
 };
 
-static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_core_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_core_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_core slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
+        &omap44xx_l4_cfg__smartreflex_core,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
+        .name           = "smartreflex_core",
+        .class          = &omap44xx_smartreflex_hwmod_class,
+        .mpu_irqs       = omap44xx_smartreflex_core_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
+        .main_clk       = "smartreflex_core_fck",
+        .vdd_name       = "core",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_smartreflex_core_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_iva */
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
+        { .irq = 102 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
         {
-                .pa_start       = 0x4a314000,
-                .pa_end         = 0x4a31407f,
+                .pa_start       = 0x4a0db000,
+                .pa_end         = 0x4a0db03f,
                 .flags          = ADDR_TYPE_RT
         },
 };
 
+/* l4_cfg -> smartreflex_iva */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_iva_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_iva_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_iva slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
+        &omap44xx_l4_cfg__smartreflex_iva,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
+        .name           = "smartreflex_iva",
+        .class          = &omap44xx_smartreflex_hwmod_class,
+        .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
+        .main_clk       = "smartreflex_iva_fck",
+        .vdd_name       = "iva",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_smartreflex_iva_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* smartreflex_mpu */
+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
+        { .irq = 18 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
+        {
+                .pa_start       = 0x4a0d9000,
+                .pa_end         = 0x4a0d903f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_mpu_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_mpu_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* smartreflex_mpu slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
+        &omap44xx_l4_cfg__smartreflex_mpu,
+};
+
+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
+        .name           = "smartreflex_mpu",
+        .class          = &omap44xx_smartreflex_hwmod_class,
+        .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
+        .main_clk       = "smartreflex_mpu_fck",
+        .vdd_name       = "mpu",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_smartreflex_mpu_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
+        .rev_offs       = 0x0050,
+        .sysc_offs      = 0x0054,
+        .syss_offs      = 0x0058,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
-        .name = "uart",
-        .sysc = &omap44xx_uart_sysc,
+        .name   = "uart",
+        .sysc   = &omap44xx_uart_sysc,
 };
 
 /* uart1 */
@@ -578,51 +1731,6 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
         },
 };
 
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_wd_timer2_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_wd_timer2_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* wd_timer2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
-        &omap44xx_l4_wkup__wd_timer2,
-};
-
-static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
-        .name           = "wd_timer2",
-        .class          = &omap44xx_wd_timer_hwmod_class,
-        .mpu_irqs       = omap44xx_wd_timer2_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
-        .main_clk       = "wd_timer2_fck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
-                },
-        },
-        .slaves         = omap44xx_wd_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
-/* wd_timer3 */
-static struct omap_hwmod omap44xx_wd_timer3_hwmod;
-static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
-        { .irq = 36 + OMAP44XX_IRQ_GIC_START },
-};
-
-static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
-        {
-                .pa_start       = 0x40130000,
-                .pa_end         = 0x4013007f,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_per -> uart2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
         .master         = &omap44xx_l4_per_hwmod,
@@ -675,25 +1783,6 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
         },
 };
 
-/* l4_abe -> wd_timer3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_wd_timer3_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_wd_timer3_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
-        .user           = OCP_USER_MPU,
-};
-
-/* l4_abe -> wd_timer3 (dma) */
-static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
-        {
-                .pa_start       = 0x49030000,
-                .pa_end         = 0x4903007f,
-                .flags          = ADDR_TYPE_RT
-        },
-};
-
 /* l4_per -> uart3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
         .master         = &omap44xx_l4_per_hwmod,
@@ -747,37 +1836,6 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
         },
 };
 
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_wd_timer3_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_wd_timer3_dma_addrs,
-        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
-        .user           = OCP_USER_SDMA,
-};
-
-/* wd_timer3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
-        &omap44xx_l4_abe__wd_timer3,
-        &omap44xx_l4_abe__wd_timer3_dma,
-};
-
-static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
-        .name           = "wd_timer3",
-        .class          = &omap44xx_wd_timer_hwmod_class,
-        .mpu_irqs       = omap44xx_wd_timer3_irqs,
-        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
-        .main_clk       = "wd_timer3_fck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
-                },
-        },
-        .slaves         = omap44xx_wd_timer3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
-        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
 /* l4_per -> uart4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
         .master         = &omap44xx_l4_per_hwmod,
@@ -811,35 +1869,205 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &omap44xx_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod omap44xx_wd_timer2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
+        { .irq = 80 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4a314000,
+                .pa_end         = 0x4a31407f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_wd_timer2_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_wd_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* wd_timer2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
+        &omap44xx_l4_wkup__wd_timer2,
+};
+
+static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap44xx_wd_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_wd_timer2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
+        .main_clk       = "wd_timer2_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_wd_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* wd_timer3 */
+static struct omap_hwmod omap44xx_wd_timer3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
+        { .irq = 36 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
+        {
+                .pa_start       = 0x40130000,
+                .pa_end         = 0x4013007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> wd_timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_wd_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
+        {
+                .pa_start       = 0x49030000,
+                .pa_end         = 0x4903007f,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_abe -> wd_timer3 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_wd_timer3_dma_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
+        .user           = OCP_USER_SDMA,
+};
+
+/* wd_timer3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
+        &omap44xx_l4_abe__wd_timer3,
+        &omap44xx_l4_abe__wd_timer3_dma,
+};
+
+static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+        .name           = "wd_timer3",
+        .class          = &omap44xx_wd_timer_hwmod_class,
+        .mpu_irqs       = omap44xx_wd_timer3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
+        .main_clk       = "wd_timer3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+                },
+        },
+        .slaves         = omap44xx_wd_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+
         /* dmm class */
         &omap44xx_dmm_hwmod,
+
         /* emif_fw class */
         &omap44xx_emif_fw_hwmod,
+
         /* l3 class */
         &omap44xx_l3_instr_hwmod,
         &omap44xx_l3_main_1_hwmod,
         &omap44xx_l3_main_2_hwmod,
         &omap44xx_l3_main_3_hwmod,
+
         /* l4 class */
         &omap44xx_l4_abe_hwmod,
         &omap44xx_l4_cfg_hwmod,
         &omap44xx_l4_per_hwmod,
         &omap44xx_l4_wkup_hwmod,
+
         /* mpu_bus class */
         &omap44xx_mpu_private_hwmod,
 
+        /* dma class */
+        &omap44xx_dma_system_hwmod,
+
+        /* dsp class */
+        &omap44xx_dsp_hwmod,
+        &omap44xx_dsp_c0_hwmod,
+
+        /* gpio class */
+        &omap44xx_gpio1_hwmod,
+        &omap44xx_gpio2_hwmod,
+        &omap44xx_gpio3_hwmod,
+        &omap44xx_gpio4_hwmod,
+        &omap44xx_gpio5_hwmod,
+        &omap44xx_gpio6_hwmod,
+
+        /* i2c class */
+        &omap44xx_i2c1_hwmod,
+        &omap44xx_i2c2_hwmod,
+        &omap44xx_i2c3_hwmod,
+        &omap44xx_i2c4_hwmod,
+
+        /* iva class */
+        &omap44xx_iva_hwmod,
+        &omap44xx_iva_seq0_hwmod,
+        &omap44xx_iva_seq1_hwmod,
+
         /* mpu class */
         &omap44xx_mpu_hwmod,
-        /* wd_timer class */
-        &omap44xx_wd_timer2_hwmod,
-        &omap44xx_wd_timer3_hwmod,
+
+        /* smartreflex class */
+        &omap44xx_smartreflex_core_hwmod,
+        &omap44xx_smartreflex_iva_hwmod,
+        &omap44xx_smartreflex_mpu_hwmod,
 
         /* uart class */
         &omap44xx_uart1_hwmod,
         &omap44xx_uart2_hwmod,
         &omap44xx_uart3_hwmod,
         &omap44xx_uart4_hwmod,
+
+        /* wd_timer class */
+        &omap44xx_wd_timer2_hwmod,
+        &omap44xx_wd_timer3_hwmod,
+
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h
new file mode 100644
index 000000000000..46ac27dd6c84
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_opp_data.h
@@ -0,0 +1,72 @@
+/*
+ * OMAP SoC specific OPP Data helpers
+ *
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
+#define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
+
+#include <plat/omap_hwmod.h>
+
+/*
+ * *BIG FAT WARNING*:
+ * USE the following ONLY in opp data initialization common to an SoC.
+ * DO NOT USE these in board files/pm core etc.
+ */
+
+/**
+ * struct omap_opp_def - OMAP OPP Definition
+ * @hwmod_name: Name of the hwmod for this domain
+ * @freq:       Frequency in hertz corresponding to this OPP
+ * @u_volt:     Nominal voltage in microvolts corresponding to this OPP
+ * @default_available:  True/false - is this OPP available by default
+ *
+ * OMAP SOCs have a standard set of tuples consisting of frequency and voltage
+ * pairs that the device will support per voltage domain. This is called
+ * Operating Points or OPP. The actual definitions of OMAP Operating Points
+ * varies over silicon within the same family of devices. For a specific
+ * domain, you can have a set of {frequency, voltage} pairs and this is denoted
+ * by an array of omap_opp_def. As the kernel boots and more information is
+ * available, a set of these are activated based on the precise nature of
+ * device the kernel boots up on. It is interesting to remember that each IP
+ * which belongs to a voltage domain may define their own set of OPPs on top
+ * of this - but this is handled by the appropriate driver.
+ */
+struct omap_opp_def {
+        char *hwmod_name;
+
+        unsigned long freq;
+        unsigned long u_volt;
+
+        bool default_available;
+};
+
+/*
+ * Initialization wrapper used to define an OPP for OMAP variants.
+ */
+#define OPP_INITIALIZER(_hwmod_name, _enabled, _freq, _uv)      \
+{                                                               \
+        .hwmod_name     = _hwmod_name,                          \
+        .default_available      = _enabled,                     \
+        .freq           = _freq,                                \
+        .u_volt         = _uv,                                  \
+}
+
+/* Use this to initialize the default table */
+extern int __init omap_init_opp_table(struct omap_opp_def *opp_def,
+                u32 opp_def_size);
+
+#endif          /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
new file mode 100644
index 000000000000..745252c60e32
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -0,0 +1,149 @@
+/*
+  * This file configures the internal USB PHY in OMAP4430. Used
+  * with TWL6030 transceiver and MUSB on OMAP4430.
+  *
+  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * Author: Hema HK <hemahk@ti.com>
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  *
+  */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/usb.h>
+
+#include <plat/usb.h>
+
+/* OMAP control module register for UTMI PHY */
+#define CONTROL_DEV_CONF                0x300
+#define PHY_PD                          0x1
+
+#define USBOTGHS_CONTROL                0x33c
+#define AVALID                          BIT(0)
+#define BVALID                          BIT(1)
+#define VBUSVALID                       BIT(2)
+#define SESSEND                         BIT(3)
+#define IDDIG                           BIT(4)
+
+static struct clk *phyclk, *clk48m, *clk32k;
+static void __iomem *ctrl_base;
+
+int omap4430_phy_init(struct device *dev)
+{
+        ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
+        if (!ctrl_base) {
+                dev_err(dev, "control module ioremap failed\n");
+                return -ENOMEM;
+        }
+        /* Power down the phy */
+        __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+        phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
+
+        if (IS_ERR(phyclk)) {
+                dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
+                iounmap(ctrl_base);
+                return PTR_ERR(phyclk);
+        }
+
+        clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
+        if (IS_ERR(clk48m)) {
+                dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
+                clk_put(phyclk);
+                iounmap(ctrl_base);
+                return PTR_ERR(clk48m);
+        }
+
+        clk32k = clk_get(dev, "usb_phy_cm_clk32k");
+        if (IS_ERR(clk32k)) {
+                dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
+                clk_put(phyclk);
+                clk_put(clk48m);
+                iounmap(ctrl_base);
+                return PTR_ERR(clk32k);
+        }
+        return 0;
+}
+
+int omap4430_phy_set_clk(struct device *dev, int on)
+{
+        static int state;
+
+        if (on && !state) {
+                /* Enable the phy clocks */
+                clk_enable(phyclk);
+                clk_enable(clk48m);
+                clk_enable(clk32k);
+                state = 1;
+        } else if (state) {
+                /* Disable the phy clocks */
+                clk_disable(phyclk);
+                clk_disable(clk48m);
+                clk_disable(clk32k);
+                state = 0;
+        }
+        return 0;
+}
+
+int omap4430_phy_power(struct device *dev, int ID, int on)
+{
+        if (on) {
+                /* enabled the clocks */
+                omap4430_phy_set_clk(dev, 1);
+                /* power on the phy */
+                if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
+                        __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+                        mdelay(200);
+                }
+                if (ID)
+                        /* enable VBUS valid, IDDIG groung */
+                        __raw_writel(AVALID | VBUSVALID, ctrl_base +
+                                                        USBOTGHS_CONTROL);
+                else
+                        /*
+                         * Enable VBUS Valid, AValid and IDDIG
+                         * high impedence
+                         */
+                        __raw_writel(IDDIG | AVALID | VBUSVALID,
+                                                ctrl_base + USBOTGHS_CONTROL);
+        } else {
+                /* Enable session END and IDIG to high impedence. */
+                __raw_writel(SESSEND | IDDIG, ctrl_base +
+                                        USBOTGHS_CONTROL);
+                /* Disable the clocks */
+                omap4430_phy_set_clk(dev, 0);
+                /* Power down the phy */
+                __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+        }
+
+        return 0;
+}
+
+int omap4430_phy_exit(struct device *dev)
+{
+        if (ctrl_base)
+                iounmap(ctrl_base);
+        if (phyclk)
+                clk_put(phyclk);
+        if (clk48m)
+                clk_put(clk48m);
+        if (clk32k)
+                clk_put(clk32k);
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
new file mode 100644
index 000000000000..15f8c6c1bb0f
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -0,0 +1,277 @@
+/**
+ * OMAP and TWL PMIC specific intializations.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated.
+ * Thara Gopinath
+ * Copyright (C) 2009 Texas Instruments Incorporated.
+ * Nishanth Menon
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/i2c/twl.h>
+
+#include <plat/voltage.h>
+
+#define OMAP3_SRI2C_SLAVE_ADDR          0x12
+#define OMAP3_VDD_MPU_SR_CONTROL_REG    0x00
+#define OMAP3_VDD_CORE_SR_CONTROL_REG   0x01
+#define OMAP3_VP_CONFIG_ERROROFFSET     0x00
+#define OMAP3_VP_VSTEPMIN_VSTEPMIN      0x1
+#define OMAP3_VP_VSTEPMAX_VSTEPMAX      0x04
+#define OMAP3_VP_VLIMITTO_TIMEOUT_US    200
+
+#define OMAP3430_VP1_VLIMITTO_VDDMIN    0x14
+#define OMAP3430_VP1_VLIMITTO_VDDMAX    0x42
+#define OMAP3430_VP2_VLIMITTO_VDDMIN    0x18
+#define OMAP3430_VP2_VLIMITTO_VDDMAX    0x2c
+
+#define OMAP3630_VP1_VLIMITTO_VDDMIN    0x18
+#define OMAP3630_VP1_VLIMITTO_VDDMAX    0x3c
+#define OMAP3630_VP2_VLIMITTO_VDDMIN    0x18
+#define OMAP3630_VP2_VLIMITTO_VDDMAX    0x30
+
+#define OMAP4_SRI2C_SLAVE_ADDR          0x12
+#define OMAP4_VDD_MPU_SR_VOLT_REG       0x55
+#define OMAP4_VDD_IVA_SR_VOLT_REG       0x5B
+#define OMAP4_VDD_CORE_SR_VOLT_REG      0x61
+
+#define OMAP4_VP_CONFIG_ERROROFFSET     0x00
+#define OMAP4_VP_VSTEPMIN_VSTEPMIN      0x01
+#define OMAP4_VP_VSTEPMAX_VSTEPMAX      0x04
+#define OMAP4_VP_VLIMITTO_TIMEOUT_US    200
+
+#define OMAP4_VP_MPU_VLIMITTO_VDDMIN    0xA
+#define OMAP4_VP_MPU_VLIMITTO_VDDMAX    0x39
+#define OMAP4_VP_IVA_VLIMITTO_VDDMIN    0xA
+#define OMAP4_VP_IVA_VLIMITTO_VDDMAX    0x2D
+#define OMAP4_VP_CORE_VLIMITTO_VDDMIN   0xA
+#define OMAP4_VP_CORE_VLIMITTO_VDDMAX   0x28
+
+static bool is_offset_valid;
+static u8 smps_offset;
+
+#define REG_SMPS_OFFSET         0xE0
+
+unsigned long twl4030_vsel_to_uv(const u8 vsel)
+{
+        return (((vsel * 125) + 6000)) * 100;
+}
+
+u8 twl4030_uv_to_vsel(unsigned long uv)
+{
+        return DIV_ROUND_UP(uv - 600000, 12500);
+}
+
+unsigned long twl6030_vsel_to_uv(const u8 vsel)
+{
+        /*
+         * In TWL6030 depending on the value of SMPS_OFFSET
+         * efuse register the voltage range supported in
+         * standard mode can be either between 0.6V - 1.3V or
+         * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+         * is programmed to all 0's where as starting from
+         * TWL6030 ES1.1 the efuse is programmed to 1
+         */
+        if (!is_offset_valid) {
+                twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
+                                REG_SMPS_OFFSET);
+                is_offset_valid = true;
+        }
+
+        /*
+         * There is no specific formula for voltage to vsel
+         * conversion above 1.3V. There are special hardcoded
+         * values for voltages above 1.3V. Currently we are
+         * hardcoding only for 1.35 V which is used for 1GH OPP for
+         * OMAP4430.
+         */
+        if (vsel == 0x3A)
+                return 1350000;
+
+        if (smps_offset & 0x8)
+                return ((((vsel - 1) * 125) + 7000)) * 100;
+        else
+                return ((((vsel - 1) * 125) + 6000)) * 100;
+}
+
+u8 twl6030_uv_to_vsel(unsigned long uv)
+{
+        /*
+         * In TWL6030 depending on the value of SMPS_OFFSET
+         * efuse register the voltage range supported in
+         * standard mode can be either between 0.6V - 1.3V or
+         * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
+         * is programmed to all 0's where as starting from
+         * TWL6030 ES1.1 the efuse is programmed to 1
+         */
+        if (!is_offset_valid) {
+                twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
+                                REG_SMPS_OFFSET);
+                is_offset_valid = true;
+        }
+
+        /*
+         * There is no specific formula for voltage to vsel
+         * conversion above 1.3V. There are special hardcoded
+         * values for voltages above 1.3V. Currently we are
+         * hardcoding only for 1.35 V which is used for 1GH OPP for
+         * OMAP4430.
+         */
+        if (uv == 1350000)
+                return 0x3A;
+
+        if (smps_offset & 0x8)
+                return DIV_ROUND_UP(uv - 700000, 12500) + 1;
+        else
+                return DIV_ROUND_UP(uv - 600000, 12500) + 1;
+}
+
+static struct omap_volt_pmic_info omap3_mpu_volt_info = {
+        .slew_rate              = 4000,
+        .step_size              = 12500,
+        .on_volt                = 1200000,
+        .onlp_volt              = 1000000,
+        .ret_volt               = 975000,
+        .off_volt               = 600000,
+        .volt_setup_time        = 0xfff,
+        .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
+        .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
+        .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
+        .vp_vddmin              = OMAP3430_VP1_VLIMITTO_VDDMIN,
+        .vp_vddmax              = OMAP3430_VP1_VLIMITTO_VDDMAX,
+        .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
+        .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
+        .pmic_reg               = OMAP3_VDD_MPU_SR_CONTROL_REG,
+        .vsel_to_uv             = twl4030_vsel_to_uv,
+        .uv_to_vsel             = twl4030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap3_core_volt_info = {
+        .slew_rate              = 4000,
+        .step_size              = 12500,
+        .on_volt                = 1200000,
+        .onlp_volt              = 1000000,
+        .ret_volt               = 975000,
+        .off_volt               = 600000,
+        .volt_setup_time        = 0xfff,
+        .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
+        .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
+        .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
+        .vp_vddmin              = OMAP3430_VP2_VLIMITTO_VDDMIN,
+        .vp_vddmax              = OMAP3430_VP2_VLIMITTO_VDDMAX,
+        .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
+        .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
+        .pmic_reg               = OMAP3_VDD_CORE_SR_CONTROL_REG,
+        .vsel_to_uv             = twl4030_vsel_to_uv,
+        .uv_to_vsel             = twl4030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap4_mpu_volt_info = {
+        .slew_rate              = 4000,
+        .step_size              = 12500,
+        .on_volt                = 1350000,
+        .onlp_volt              = 1350000,
+        .ret_volt               = 837500,
+        .off_volt               = 600000,
+        .volt_setup_time        = 0,
+        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
+        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+        .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+        .vp_vddmin              = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
+        .vp_vddmax              = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
+        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
+        .pmic_reg               = OMAP4_VDD_MPU_SR_VOLT_REG,
+        .vsel_to_uv             = twl6030_vsel_to_uv,
+        .uv_to_vsel             = twl6030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap4_iva_volt_info = {
+        .slew_rate              = 4000,
+        .step_size              = 12500,
+        .on_volt                = 1100000,
+        .onlp_volt              = 1100000,
+        .ret_volt               = 837500,
+        .off_volt               = 600000,
+        .volt_setup_time        = 0,
+        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
+        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+        .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+        .vp_vddmin              = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
+        .vp_vddmax              = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
+        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
+        .pmic_reg               = OMAP4_VDD_IVA_SR_VOLT_REG,
+        .vsel_to_uv             = twl6030_vsel_to_uv,
+        .uv_to_vsel             = twl6030_uv_to_vsel,
+};
+
+static struct omap_volt_pmic_info omap4_core_volt_info = {
+        .slew_rate              = 4000,
+        .step_size              = 12500,
+        .on_volt                = 1100000,
+        .onlp_volt              = 1100000,
+        .ret_volt               = 837500,
+        .off_volt               = 600000,
+        .volt_setup_time        = 0,
+        .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
+        .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
+        .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
+        .vp_vddmin              = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
+        .vp_vddmax              = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
+        .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
+        .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
+        .pmic_reg               = OMAP4_VDD_CORE_SR_VOLT_REG,
+        .vsel_to_uv             = twl6030_vsel_to_uv,
+        .uv_to_vsel             = twl6030_uv_to_vsel,
+};
+
+int __init omap4_twl_init(void)
+{
+        struct voltagedomain *voltdm;
+
+        if (!cpu_is_omap44xx())
+                return -ENODEV;
+
+        voltdm = omap_voltage_domain_lookup("mpu");
+        omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info);
+
+        voltdm = omap_voltage_domain_lookup("iva");
+        omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info);
+
+        voltdm = omap_voltage_domain_lookup("core");
+        omap_voltage_register_pmic(voltdm, &omap4_core_volt_info);
+
+        return 0;
+}
+
+int __init omap3_twl_init(void)
+{
+        struct voltagedomain *voltdm;
+
+        if (!cpu_is_omap34xx())
+                return -ENODEV;
+
+        if (cpu_is_omap3630()) {
+                omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
+                omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
+                omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
+                omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
+        }
+
+        voltdm = omap_voltage_domain_lookup("mpu");
+        omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
+
+        voltdm = omap_voltage_domain_lookup("core");
+        omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
new file mode 100644
index 000000000000..ab8b35b780b5
--- /dev/null
+++ b/arch/arm/mach-omap2/opp.c
@@ -0,0 +1,93 @@
+/*
+ * OMAP SoC specific OPP wrapper function
+ *
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+#include <linux/opp.h>
+
+#include <plat/omap_device.h>
+
+#include "omap_opp_data.h"
+
+/* Temp variable to allow multiple calls */
+static u8 __initdata omap_table_init;
+
+/**
+ * omap_init_opp_table() - Initialize opp table as per the CPU type
+ * @opp_def:            opp default list for this silicon
+ * @opp_def_size:       number of opp entries for this silicon
+ *
+ * Register the initial OPP table with the OPP library based on the CPU
+ * type. This is meant to be used only by SoC specific registration.
+ */
+int __init omap_init_opp_table(struct omap_opp_def *opp_def,
+                u32 opp_def_size)
+{
+        int i, r;
+
+        if (!opp_def || !opp_def_size) {
+                pr_err("%s: invalid params!\n", __func__);
+                return -EINVAL;
+        }
+
+        /*
+         * Initialize only if not already initialized even if the previous
+         * call failed, because, no reason we'd succeed again.
+         */
+        if (omap_table_init)
+                return -EEXIST;
+        omap_table_init = 1;
+
+        /* Lets now register with OPP library */
+        for (i = 0; i < opp_def_size; i++) {
+                struct omap_hwmod *oh;
+                struct device *dev;
+
+                if (!opp_def->hwmod_name) {
+                        pr_err("%s: NULL name of omap_hwmod, failing [%d].\n",
+                                __func__, i);
+                        return -EINVAL;
+                }
+                oh = omap_hwmod_lookup(opp_def->hwmod_name);
+                if (!oh || !oh->od) {
+                        pr_warn("%s: no hwmod or odev for %s, [%d] "
+                                "cannot add OPPs.\n", __func__,
+                                opp_def->hwmod_name, i);
+                        return -EINVAL;
+                }
+                dev = &oh->od->pdev.dev;
+
+                r = opp_add(dev, opp_def->freq, opp_def->u_volt);
+                if (r) {
+                        dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
+                                "result=%d\n",
+                               __func__, opp_def->freq,
+                               opp_def->hwmod_name, i, r);
+                } else {
+                        if (!opp_def->default_available)
+                                r = opp_disable(dev, opp_def->freq);
+                        if (r)
+                                dev_err(dev, "%s: disable %ld failed for %s "
+                                        "[%d] result=%d\n",
+                                        __func__, opp_def->freq,
+                                        opp_def->hwmod_name, i, r);
+                }
+                opp_def++;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c
new file mode 100644
index 000000000000..0486fce8a92c
--- /dev/null
+++ b/arch/arm/mach-omap2/opp3xxx_data.c
@@ -0,0 +1,107 @@
+/*
+ * OMAP3 OPP table definitions.
+ *
+ * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+
+#include <plat/cpu.h>
+
+#include "omap_opp_data.h"
+
+static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
+        /* MPU OPP1 */
+        OPP_INITIALIZER("mpu", true, 125000000, 975000),
+        /* MPU OPP2 */
+        OPP_INITIALIZER("mpu", true, 250000000, 1075000),
+        /* MPU OPP3 */
+        OPP_INITIALIZER("mpu", true, 500000000, 1200000),
+        /* MPU OPP4 */
+        OPP_INITIALIZER("mpu", true, 550000000, 1270000),
+        /* MPU OPP5 */
+        OPP_INITIALIZER("mpu", true, 600000000, 1350000),
+
+        /*
+         * L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
+         * almost the same than the one at 83MHz thus providing very little
+         * gain for the power point of view. In term of energy it will even
+         * increase the consumption due to the very negative performance
+         * impact that frequency will do to the MPU and the whole system in
+         * general.
+         */
+        OPP_INITIALIZER("l3_main", false, 41500000, 975000),
+        /* L3 OPP2 */
+        OPP_INITIALIZER("l3_main", true, 83000000, 1050000),
+        /* L3 OPP3 */
+        OPP_INITIALIZER("l3_main", true, 166000000, 1150000),
+
+        /* DSP OPP1 */
+        OPP_INITIALIZER("iva", true, 90000000, 975000),
+        /* DSP OPP2 */
+        OPP_INITIALIZER("iva", true, 180000000, 1075000),
+        /* DSP OPP3 */
+        OPP_INITIALIZER("iva", true, 360000000, 1200000),
+        /* DSP OPP4 */
+        OPP_INITIALIZER("iva", true, 400000000, 1270000),
+        /* DSP OPP5 */
+        OPP_INITIALIZER("iva", true, 430000000, 1350000),
+};
+
+static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
+        /* MPU OPP1 - OPP50 */
+        OPP_INITIALIZER("mpu", true,  300000000, 1012500),
+        /* MPU OPP2 - OPP100 */
+        OPP_INITIALIZER("mpu", true,  600000000, 1200000),
+        /* MPU OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("mpu", false, 800000000, 1325000),
+        /* MPU OPP4 - OPP-SB */
+        OPP_INITIALIZER("mpu", false, 1000000000, 1375000),
+
+        /* L3 OPP1 - OPP50 */
+        OPP_INITIALIZER("l3_main", true, 100000000, 1000000),
+        /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+        OPP_INITIALIZER("l3_main", true, 200000000, 1200000),
+
+        /* DSP OPP1 - OPP50 */
+        OPP_INITIALIZER("iva", true,  260000000, 1012500),
+        /* DSP OPP2 - OPP100 */
+        OPP_INITIALIZER("iva", true,  520000000, 1200000),
+        /* DSP OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("iva", false, 660000000, 1325000),
+        /* DSP OPP4 - OPP-SB */
+        OPP_INITIALIZER("iva", false, 800000000, 1375000),
+};
+
+/**
+ * omap3_opp_init() - initialize omap3 opp table
+ */
+static int __init omap3_opp_init(void)
+{
+        int r = -ENODEV;
+
+        if (!cpu_is_omap34xx())
+                return r;
+
+        if (cpu_is_omap3630())
+                r = omap_init_opp_table(omap36xx_opp_def_list,
+                        ARRAY_SIZE(omap36xx_opp_def_list));
+        else
+                r = omap_init_opp_table(omap34xx_opp_def_list,
+                        ARRAY_SIZE(omap34xx_opp_def_list));
+
+        return r;
+}
+device_initcall(omap3_opp_init);
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
new file mode 100644
index 000000000000..a11fa566d8ee
--- /dev/null
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -0,0 +1,57 @@
+/*
+ * OMAP4 OPP table definitions.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Nishanth Menon
+ *      Kevin Hilman
+ *      Thara Gopinath
+ * Copyright (C) 2010 Nokia Corporation.
+ *      Eduardo Valentin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/module.h>
+
+#include <plat/cpu.h>
+
+#include "omap_opp_data.h"
+
+static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
+        /* MPU OPP1 - OPP50 */
+        OPP_INITIALIZER("mpu", true, 300000000, 1100000),
+        /* MPU OPP2 - OPP100 */
+        OPP_INITIALIZER("mpu", true, 600000000, 1200000),
+        /* MPU OPP3 - OPP-Turbo */
+        OPP_INITIALIZER("mpu", false, 800000000, 1260000),
+        /* MPU OPP4 - OPP-SB */
+        OPP_INITIALIZER("mpu", false, 1008000000, 1350000),
+        /* L3 OPP1 - OPP50 */
+        OPP_INITIALIZER("l3_main_1", true, 100000000, 930000),
+        /* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
+        OPP_INITIALIZER("l3_main_1", true, 200000000, 1100000),
+        /* TODO: add IVA, DSP, aess, fdif, gpu */
+};
+
+/**
+ * omap4_opp_init() - initialize omap4 opp table
+ */
+static int __init omap4_opp_init(void)
+{
+        int r = -ENODEV;
+
+        if (!cpu_is_omap44xx())
+                return r;
+
+        r = omap_init_opp_table(omap44xx_opp_def_list,
+                        ARRAY_SIZE(omap44xx_opp_def_list));
+
+        return r;
+}
+device_initcall(omap4_opp_init);
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index a8afb610c7d8..125f56591fb5 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -29,12 +29,13 @@
 
 #include <plat/clock.h>
 #include <plat/board.h>
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
 #include <plat/dmtimer.h>
+#include <plat/omap-pm.h>
 
-#include "prm.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
 #include "pm.h"
 
 int omap2_pm_debug;
@@ -45,10 +46,10 @@ u32 wakeup_timer_milliseconds;
 
 #define DUMP_PRM_MOD_REG(mod, reg)    \
         regs[reg_count].name = #mod "." #reg; \
-        regs[reg_count++].val = prm_read_mod_reg(mod, reg)
+        regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
 #define DUMP_CM_MOD_REG(mod, reg)     \
         regs[reg_count].name = #mod "." #reg; \
-        regs[reg_count++].val = cm_read_mod_reg(mod, reg)
+        regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
 #define DUMP_PRM_REG(reg) \
         regs[reg_count].name = #reg; \
         regs[reg_count++].val = __raw_readl(reg)
@@ -328,10 +329,10 @@ static void pm_dbg_regset_store(u32 *ptr)
                 for (j = pm_dbg_reg_modules[i].low;
                         j <= pm_dbg_reg_modules[i].high; j += 4) {
                         if (pm_dbg_reg_modules[i].type == MOD_CM)
-                                val = cm_read_mod_reg(
+                                val = omap2_cm_read_mod_reg(
                                         pm_dbg_reg_modules[i].offset, j);
                         else
-                                val = prm_read_mod_reg(
+                                val = omap2_prm_read_mod_reg(
                                         pm_dbg_reg_modules[i].offset, j);
                         *(ptr++) = val;
                 }
@@ -581,6 +582,10 @@ static int option_set(void *data, u64 val)
         *option = val;
 
         if (option == &enable_off_mode) {
+                if (val)
+                        omap_pm_enable_off_mode();
+                else
+                        omap_pm_disable_off_mode();
                 if (cpu_is_omap34xx())
                         omap3_pm_off_mode_enable(val);
         }
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 59ca03b0e691..d5a102c71989 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -13,13 +13,16 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/err.h>
+#include <linux/opp.h>
 
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
 #include <plat/common.h>
+#include <plat/voltage.h>
 
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
+#include "pm.h"
 
 static struct omap_device_pm_latency *pm_lats;
 
@@ -89,10 +92,13 @@ static void omap2_init_processor_devices(void)
         }
 }
 
+/* Types of sleep_switch used in omap_set_pwrdm_state */
+#define FORCEWAKEUP_SWITCH      0
+#define LOWPOWERSTATE_SWITCH    1
+
 /*
  * This sets pwrdm state (other than mpu & core. Currently only ON &
- * RET are supported. Function is assuming that clkdm doesn't have
- * hw_sup mode enabled.
+ * RET are supported.
  */
 int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 {
@@ -114,9 +120,14 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
                 return ret;
 
         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
-                omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
-                sleep_switch = 1;
-                pwrdm_wait_transition(pwrdm);
+                if ((pwrdm_read_pwrst(pwrdm) > state) &&
+                        (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
+                        sleep_switch = LOWPOWERSTATE_SWITCH;
+                } else {
+                        omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
+                        pwrdm_wait_transition(pwrdm);
+                        sleep_switch = FORCEWAKEUP_SWITCH;
+                }
         }
 
         ret = pwrdm_set_next_pwrst(pwrdm, state);
@@ -126,16 +137,106 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
                 goto err;
         }
 
-        if (sleep_switch) {
-                omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
-                pwrdm_wait_transition(pwrdm);
-                pwrdm_state_switch(pwrdm);
+        switch (sleep_switch) {
+        case FORCEWAKEUP_SWITCH:
+                if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO)
+                        omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
+                else
+                        omap2_clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
+                break;
+        case LOWPOWERSTATE_SWITCH:
+                pwrdm_set_lowpwrstchange(pwrdm);
+                break;
+        default:
+                return ret;
         }
 
+        pwrdm_wait_transition(pwrdm);
+        pwrdm_state_switch(pwrdm);
 err:
         return ret;
 }
 
+/*
+ * This API is to be called during init to put the various voltage
+ * domains to the voltage as per the opp table. Typically we boot up
+ * at the nominal voltage. So this function finds out the rate of
+ * the clock associated with the voltage domain, finds out the correct
+ * opp entry and puts the voltage domain to the voltage specifies
+ * in the opp entry
+ */
+static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
+                                                struct device *dev)
+{
+        struct voltagedomain *voltdm;
+        struct clk *clk;
+        struct opp *opp;
+        unsigned long freq, bootup_volt;
+
+        if (!vdd_name || !clk_name || !dev) {
+                printk(KERN_ERR "%s: Invalid parameters!\n", __func__);
+                goto exit;
+        }
+
+        voltdm = omap_voltage_domain_lookup(vdd_name);
+        if (IS_ERR(voltdm)) {
+                printk(KERN_ERR "%s: Unable to get vdd pointer for vdd_%s\n",
+                        __func__, vdd_name);
+                goto exit;
+        }
+
+        clk =  clk_get(NULL, clk_name);
+        if (IS_ERR(clk)) {
+                printk(KERN_ERR "%s: unable to get clk %s\n",
+                        __func__, clk_name);
+                goto exit;
+        }
+
+        freq = clk->rate;
+        clk_put(clk);
+
+        opp = opp_find_freq_ceil(dev, &freq);
+        if (IS_ERR(opp)) {
+                printk(KERN_ERR "%s: unable to find boot up OPP for vdd_%s\n",
+                        __func__, vdd_name);
+                goto exit;
+        }
+
+        bootup_volt = opp_get_voltage(opp);
+        if (!bootup_volt) {
+                printk(KERN_ERR "%s: unable to find voltage corresponding"
+                        "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
+                goto exit;
+        }
+
+        omap_voltage_scale_vdd(voltdm, bootup_volt);
+        return 0;
+
+exit:
+        printk(KERN_ERR "%s: Unable to put vdd_%s to its init voltage\n\n",
+                __func__, vdd_name);
+        return -EINVAL;
+}
+
+static void __init omap3_init_voltages(void)
+{
+        if (!cpu_is_omap34xx())
+                return;
+
+        omap2_set_init_voltage("mpu", "dpll1_ck", mpu_dev);
+        omap2_set_init_voltage("core", "l3_ick", l3_dev);
+}
+
+static void __init omap4_init_voltages(void)
+{
+        if (!cpu_is_omap44xx())
+                return;
+
+        omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev);
+        omap2_set_init_voltage("core", "l3_div_ck", l3_dev);
+        omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev);
+}
+
 static int __init omap2_common_pm_init(void)
 {
         omap2_init_processor_devices();
@@ -143,5 +244,24 @@ static int __init omap2_common_pm_init(void)
 
         return 0;
 }
-device_initcall(omap2_common_pm_init);
+postcore_initcall(omap2_common_pm_init);
+
+static int __init omap2_common_pm_late_init(void)
+{
+        /* Init the OMAP TWL parameters */
+        omap3_twl_init();
+        omap4_twl_init();
+
+        /* Init the voltage layer */
+        omap_voltage_late_init();
 
+        /* Initialize the voltages */
+        omap3_init_voltages();
+        omap4_init_voltages();
+
+        /* Smartreflex device init */
+        omap_devinit_smartreflex();
+
+        return 0;
+}
+late_initcall(omap2_common_pm_late_init);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0d75bfd1fdbe..1c1b0ab5b978 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -11,7 +11,9 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
 #define __ARCH_ARM_MACH_OMAP2_PM_H
 
-#include <plat/powerdomain.h>
+#include <linux/err.h>
+
+#include "powerdomain.h"
 
 extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
@@ -20,6 +22,20 @@ extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
 
+#if defined(CONFIG_PM_OPP)
+extern int omap3_opp_init(void);
+extern int omap4_opp_init(void);
+#else
+static inline int omap3_opp_init(void)
+{
+        return -EINVAL;
+}
+static inline int omap4_opp_init(void)
+{
+        return -EINVAL;
+}
+#endif
+
 struct cpuidle_params {
         u8  valid;
         u32 sleep_latency;
@@ -58,7 +74,7 @@ extern u32 sleep_while_idle;
 #endif
 
 #if defined(CONFIG_CPU_IDLE)
-extern void omap3_cpuidle_update_states(void);
+extern void omap3_cpuidle_update_states(u32, u32);
 #endif
 
 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
@@ -80,9 +96,46 @@ extern void save_secure_ram_context(u32 *addr);
 extern void omap3_save_scratchpad_contents(void);
 
 extern unsigned int omap24xx_idle_loop_suspend_sz;
-extern unsigned int omap34xx_suspend_sz;
 extern unsigned int save_secure_ram_context_sz;
 extern unsigned int omap24xx_cpu_suspend_sz;
 extern unsigned int omap34xx_cpu_suspend_sz;
 
+#define PM_RTA_ERRATUM_i608             (1 << 0)
+#define PM_SDRC_WAKEUP_ERRATUM_i583     (1 << 1)
+
+#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
+extern u16 pm34xx_errata;
+#define IS_PM34XX_ERRATUM(id)           (pm34xx_errata & (id))
+extern void enable_omap3630_toggle_l2_on_restore(void);
+#else
+#define IS_PM34XX_ERRATUM(id)           0
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
+#endif          /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
+
+#ifdef CONFIG_OMAP_SMARTREFLEX
+extern int omap_devinit_smartreflex(void);
+extern void omap_enable_smartreflex_on_init(void);
+#else
+static inline int omap_devinit_smartreflex(void)
+{
+        return -EINVAL;
+}
+
+static inline void omap_enable_smartreflex_on_init(void) {}
+#endif
+
+#ifdef CONFIG_TWL4030_CORE
+extern int omap3_twl_init(void);
+extern int omap4_twl_init(void);
+#else
+static inline int omap3_twl_init(void)
+{
+        return -EINVAL;
+}
+static inline int omap4_twl_init(void)
+{
+        return -EINVAL;
+}
+#endif
+
 #endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index aaeea49b9bdd..dac2d1d9987d 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -42,16 +42,16 @@
 #include <plat/dma.h>
 #include <plat/board.h>
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 #include "pm.h"
 #include "control.h"
 
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
 
 #ifdef CONFIG_SUSPEND
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
@@ -79,8 +79,8 @@ static int omap2_fclks_active(void)
 {
         u32 f1, f2;
 
-        f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-        f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+        f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 
         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
         f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
@@ -105,9 +105,9 @@ static void omap2_enter_full_retention(void)
 
         /* Clear old wake-up events */
         /* REVISIT: These write to reserved bits? */
-        prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
-        prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+        omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 
         /*
          * Set MPU powerdomain's next power state to RETENTION;
@@ -120,7 +120,7 @@ static void omap2_enter_full_retention(void)
         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 
-        omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);
+        omap2_gpio_prepare_for_idle(0);
 
         if (omap2_pm_debug) {
                 omap2_pm_dump(0, 0, 0);
@@ -167,30 +167,30 @@ no_sleep:
         clk_enable(osc_ck);
 
         /* clear CORE wake-up events */
-        prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 
         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
-        prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
+        omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 
         /* MPU domain wake events */
-        l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
         if (l & 0x01)
-                prm_write_mod_reg(0x01, OCP_MOD,
+                omap2_prm_write_mod_reg(0x01, OCP_MOD,
                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
         if (l & 0x20)
-                prm_write_mod_reg(0x20, OCP_MOD,
+                omap2_prm_write_mod_reg(0x20, OCP_MOD,
                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 
         /* Mask future PRCM-to-MPU interrupts */
-        prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 }
 
 static int omap2_i2c_active(void)
 {
         u32 l;
 
-        l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 }
 
@@ -201,13 +201,13 @@ static int omap2_allow_mpu_retention(void)
         u32 l;
 
         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
-        l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
+        l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
                 return 0;
         /* Check for UART3. */
-        l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
+        l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
         if (l & OMAP24XX_EN_UART3_MASK)
                 return 0;
         if (sti_console_enabled)
@@ -230,18 +230,18 @@ static void omap2_enter_mpu_retention(void)
          * it is in retention mode. */
         if (omap2_allow_mpu_retention()) {
                 /* REVISIT: These write to reserved bits? */
-                prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
-                prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
-                prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
+                omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
+                omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
+                omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 
                 /* Try to enter MPU retention */
-                prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
+                omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
                                   OMAP_LOGICRETSTATE_MASK,
                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
         } else {
                 /* Block MPU retention */
 
-                prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
+                omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
                                                  OMAP2_PM_PWSTCTRL);
                 only_idle = 1;
         }
@@ -299,16 +299,11 @@ out:
         local_irq_enable();
 }
 
+#ifdef CONFIG_SUSPEND
 static int omap2_pm_begin(suspend_state_t state)
 {
-        suspend_state = state;
-        return 0;
-}
-
-static int omap2_pm_prepare(void)
-{
-        /* We cannot sleep in idle until we have resumed */
         disable_hlt();
+        suspend_state = state;
         return 0;
 }
 
@@ -316,9 +311,9 @@ static int omap2_pm_suspend(void)
 {
         u32 wken_wkup, mir1;
 
-        wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+        wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
         wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
-        prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
+        omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 
         /* Mask GPT1 */
         mir1 = omap_readl(0x480fe0a4);
@@ -328,7 +323,7 @@ static int omap2_pm_suspend(void)
         omap2_enter_full_retention();
 
         omap_writel(mir1, 0x480fe0a4);
-        prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
+        omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 
         return 0;
 }
@@ -349,24 +344,21 @@ static int omap2_pm_enter(suspend_state_t state)
         return ret;
 }
 
-static void omap2_pm_finish(void)
-{
-        enable_hlt();
-}
-
 static void omap2_pm_end(void)
 {
         suspend_state = PM_SUSPEND_ON;
+        enable_hlt();
 }
 
 static struct platform_suspend_ops omap_pm_ops = {
         .begin          = omap2_pm_begin,
-        .prepare        = omap2_pm_prepare,
         .enter          = omap2_pm_enter,
-        .finish         = omap2_pm_finish,
         .end            = omap2_pm_end,
         .valid          = suspend_valid_only_mem,
 };
+#else
+static const struct platform_suspend_ops __initdata omap_pm_ops;
+#endif /* CONFIG_SUSPEND */
 
 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
@@ -388,7 +380,7 @@ static void __init prcm_setup_regs(void)
         struct powerdomain *pwrdm;
 
         /* Enable autoidle */
-        prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
+        omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 
         /*
@@ -427,87 +419,87 @@ static void __init prcm_setup_regs(void)
         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 
         /* Enable clock autoidle for all domains */
-        cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
-                         OMAP24XX_AUTO_MAILBOXES_MASK |
-                         OMAP24XX_AUTO_WDT4_MASK |
-                         OMAP2420_AUTO_WDT3_MASK |
-                         OMAP24XX_AUTO_MSPRO_MASK |
-                         OMAP2420_AUTO_MMC_MASK |
-                         OMAP24XX_AUTO_FAC_MASK |
-                         OMAP2420_AUTO_EAC_MASK |
-                         OMAP24XX_AUTO_HDQ_MASK |
-                         OMAP24XX_AUTO_UART2_MASK |
-                         OMAP24XX_AUTO_UART1_MASK |
-                         OMAP24XX_AUTO_I2C2_MASK |
-                         OMAP24XX_AUTO_I2C1_MASK |
-                         OMAP24XX_AUTO_MCSPI2_MASK |
-                         OMAP24XX_AUTO_MCSPI1_MASK |
-                         OMAP24XX_AUTO_MCBSP2_MASK |
-                         OMAP24XX_AUTO_MCBSP1_MASK |
-                         OMAP24XX_AUTO_GPT12_MASK |
-                         OMAP24XX_AUTO_GPT11_MASK |
-                         OMAP24XX_AUTO_GPT10_MASK |
-                         OMAP24XX_AUTO_GPT9_MASK |
-                         OMAP24XX_AUTO_GPT8_MASK |
-                         OMAP24XX_AUTO_GPT7_MASK |
-                         OMAP24XX_AUTO_GPT6_MASK |
-                         OMAP24XX_AUTO_GPT5_MASK |
-                         OMAP24XX_AUTO_GPT4_MASK |
-                         OMAP24XX_AUTO_GPT3_MASK |
-                         OMAP24XX_AUTO_GPT2_MASK |
-                         OMAP2420_AUTO_VLYNQ_MASK |
-                         OMAP24XX_AUTO_DSS_MASK,
-                         CORE_MOD, CM_AUTOIDLE1);
-        cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
-                         OMAP24XX_AUTO_SSI_MASK |
-                         OMAP24XX_AUTO_USB_MASK,
-                         CORE_MOD, CM_AUTOIDLE2);
-        cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
-                         OMAP24XX_AUTO_GPMC_MASK |
-                         OMAP24XX_AUTO_SDMA_MASK,
-                         CORE_MOD, CM_AUTOIDLE3);
-        cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
-                         OMAP24XX_AUTO_AES_MASK |
-                         OMAP24XX_AUTO_RNG_MASK |
-                         OMAP24XX_AUTO_SHA_MASK |
-                         OMAP24XX_AUTO_DES_MASK,
-                         CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
-
-        cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
-                         CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
+                               OMAP24XX_AUTO_MAILBOXES_MASK |
+                               OMAP24XX_AUTO_WDT4_MASK |
+                               OMAP2420_AUTO_WDT3_MASK |
+                               OMAP24XX_AUTO_MSPRO_MASK |
+                               OMAP2420_AUTO_MMC_MASK |
+                               OMAP24XX_AUTO_FAC_MASK |
+                               OMAP2420_AUTO_EAC_MASK |
+                               OMAP24XX_AUTO_HDQ_MASK |
+                               OMAP24XX_AUTO_UART2_MASK |
+                               OMAP24XX_AUTO_UART1_MASK |
+                               OMAP24XX_AUTO_I2C2_MASK |
+                               OMAP24XX_AUTO_I2C1_MASK |
+                               OMAP24XX_AUTO_MCSPI2_MASK |
+                               OMAP24XX_AUTO_MCSPI1_MASK |
+                               OMAP24XX_AUTO_MCBSP2_MASK |
+                               OMAP24XX_AUTO_MCBSP1_MASK |
+                               OMAP24XX_AUTO_GPT12_MASK |
+                               OMAP24XX_AUTO_GPT11_MASK |
+                               OMAP24XX_AUTO_GPT10_MASK |
+                               OMAP24XX_AUTO_GPT9_MASK |
+                               OMAP24XX_AUTO_GPT8_MASK |
+                               OMAP24XX_AUTO_GPT7_MASK |
+                               OMAP24XX_AUTO_GPT6_MASK |
+                               OMAP24XX_AUTO_GPT5_MASK |
+                               OMAP24XX_AUTO_GPT4_MASK |
+                               OMAP24XX_AUTO_GPT3_MASK |
+                               OMAP24XX_AUTO_GPT2_MASK |
+                               OMAP2420_AUTO_VLYNQ_MASK |
+                               OMAP24XX_AUTO_DSS_MASK,
+                               CORE_MOD, CM_AUTOIDLE1);
+        omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
+                               OMAP24XX_AUTO_SSI_MASK |
+                               OMAP24XX_AUTO_USB_MASK,
+                               CORE_MOD, CM_AUTOIDLE2);
+        omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
+                               OMAP24XX_AUTO_GPMC_MASK |
+                               OMAP24XX_AUTO_SDMA_MASK,
+                               CORE_MOD, CM_AUTOIDLE3);
+        omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
+                               OMAP24XX_AUTO_AES_MASK |
+                               OMAP24XX_AUTO_RNG_MASK |
+                               OMAP24XX_AUTO_SHA_MASK |
+                               OMAP24XX_AUTO_DES_MASK,
+                               CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
+
+        omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
+                               CM_AUTOIDLE);
 
         /* Put DPLL and both APLLs into autoidle mode */
-        cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
-                         (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
-                         (0x03 << OMAP24XX_AUTO_54M_SHIFT),
-                         PLL_MOD, CM_AUTOIDLE);
-
-        cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
-                         OMAP24XX_AUTO_WDT1_MASK |
-                         OMAP24XX_AUTO_MPU_WDT_MASK |
-                         OMAP24XX_AUTO_GPIOS_MASK |
-                         OMAP24XX_AUTO_32KSYNC_MASK |
-                         OMAP24XX_AUTO_GPT1_MASK,
-                         WKUP_MOD, CM_AUTOIDLE);
+        omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
+                               (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
+                               (0x03 << OMAP24XX_AUTO_54M_SHIFT),
+                               PLL_MOD, CM_AUTOIDLE);
+
+        omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
+                               OMAP24XX_AUTO_WDT1_MASK |
+                               OMAP24XX_AUTO_MPU_WDT_MASK |
+                               OMAP24XX_AUTO_GPIOS_MASK |
+                               OMAP24XX_AUTO_32KSYNC_MASK |
+                               OMAP24XX_AUTO_GPT1_MASK,
+                               WKUP_MOD, CM_AUTOIDLE);
 
         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
          * stabilisation */
-        prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
-                          OMAP2_PRCM_CLKSSETUP_OFFSET);
+        omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+                                OMAP2_PRCM_CLKSSETUP_OFFSET);
 
         /* Configure automatic voltage transition */
-        prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
-                          OMAP2_PRCM_VOLTSETUP_OFFSET);
-        prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
-                          (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
-                          OMAP24XX_MEMRETCTRL_MASK |
-                          (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
-                          (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
-                          OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
+        omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
+                                OMAP2_PRCM_VOLTSETUP_OFFSET);
+        omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
+                                (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
+                                OMAP24XX_MEMRETCTRL_MASK |
+                                (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
+                                (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
+                                OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 
         /* Enable wake-up events */
-        prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
-                          WKUP_MOD, PM_WKEN);
+        omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
+                                WKUP_MOD, PM_WKEN);
 }
 
 static int __init omap2_pm_init(void)
@@ -518,7 +510,7 @@ static int __init omap2_pm_init(void)
                 return -ENODEV;
 
         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
-        l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
+        l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 
         /* Look up important powerdomains */
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 648b8c50d024..5b323f28da2d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -31,8 +31,8 @@
 #include <linux/console.h>
 
 #include <plat/sram.h>
-#include <plat/clockdomain.h>
-#include <plat/powerdomain.h>
+#include "clockdomain.h"
+#include "powerdomain.h"
 #include <plat/serial.h>
 #include <plat/sdrc.h>
 #include <plat/prcm.h>
@@ -41,11 +41,11 @@
 
 #include <asm/tlbflush.h>
 
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "pm.h"
 #include "sdrc.h"
 #include "control.h"
@@ -68,6 +68,9 @@ static inline bool is_suspending(void)
 #define OMAP343X_TABLE_VALUE_OFFSET        0xc0
 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
 
+/* pm34xx errata defined in pm.h */
+u16 pm34xx_errata;
+
 struct power_state {
         struct powerdomain *pwrdm;
         u32 next_state;
@@ -102,12 +105,12 @@ static void omap3_enable_io_chain(void)
         int timeout = 0;
 
         if (omap_rev() >= OMAP3430_REV_ES3_1) {
-                prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
                                      PM_WKEN);
                 /* Do a readback to assure write has been done */
-                prm_read_mod_reg(WKUP_MOD, PM_WKEN);
+                omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 
-                while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
+                while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
                          OMAP3430_ST_IO_CHAIN_MASK)) {
                         timeout++;
                         if (timeout > 1000) {
@@ -115,7 +118,7 @@ static void omap3_enable_io_chain(void)
                                        "activation failed.\n");
                                 return;
                         }
-                        prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
+                        omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
                                              WKUP_MOD, PM_WKEN);
                 }
         }
@@ -124,26 +127,17 @@ static void omap3_enable_io_chain(void)
 static void omap3_disable_io_chain(void)
 {
         if (omap_rev() >= OMAP3430_REV_ES3_1)
-                prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
                                        PM_WKEN);
 }
 
 static void omap3_core_save_context(void)
 {
-        u32 control_padconf_off;
-
-        /* Save the padconf registers */
-        control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
-        control_padconf_off |= START_PADCONF_SAVE;
-        omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
-        /* wait for the save to complete */
-        while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
-                        & PADCONF_SAVE_DONE))
-                udelay(1);
+        omap3_ctrl_save_padconf();
 
         /*
          * Force write last pad into memory, as this can fail in some
-         * cases according to erratas 1.157, 1.185
+         * cases according to errata 1.157, 1.185
          */
         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
@@ -218,27 +212,27 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
         int c = 0;
 
-        wkst = prm_read_mod_reg(module, wkst_off);
-        wkst &= prm_read_mod_reg(module, grpsel_off);
+        wkst = omap2_prm_read_mod_reg(module, wkst_off);
+        wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
         if (wkst) {
-                iclk = cm_read_mod_reg(module, iclk_off);
-                fclk = cm_read_mod_reg(module, fclk_off);
+                iclk = omap2_cm_read_mod_reg(module, iclk_off);
+                fclk = omap2_cm_read_mod_reg(module, fclk_off);
                 while (wkst) {
                         clken = wkst;
-                        cm_set_mod_reg_bits(clken, module, iclk_off);
+                        omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
                         /*
                          * For USBHOST, we don't know whether HOST1 or
                          * HOST2 woke us up, so enable both f-clocks
                          */
                         if (module == OMAP3430ES2_USBHOST_MOD)
                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
-                        cm_set_mod_reg_bits(clken, module, fclk_off);
-                        prm_write_mod_reg(wkst, module, wkst_off);
-                        wkst = prm_read_mod_reg(module, wkst_off);
+                        omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
+                        omap2_prm_write_mod_reg(wkst, module, wkst_off);
+                        wkst = omap2_prm_read_mod_reg(module, wkst_off);
                         c++;
                 }
-                cm_write_mod_reg(iclk, module, iclk_off);
-                cm_write_mod_reg(fclk, module, fclk_off);
+                omap2_cm_write_mod_reg(iclk, module, iclk_off);
+                omap2_cm_write_mod_reg(fclk, module, fclk_off);
         }
 
         return c;
@@ -281,9 +275,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
         u32 irqenable_mpu, irqstatus_mpu;
         int c = 0;
 
-        irqenable_mpu = prm_read_mod_reg(OCP_MOD,
+        irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-        irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
+        irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
         irqstatus_mpu &= irqenable_mpu;
 
@@ -304,10 +298,10 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
                              "no code to handle it (%08x)\n", irqstatus_mpu);
                 }
 
-                prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
+                omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-                irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
+                irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
                 irqstatus_mpu &= irqenable_mpu;
 
@@ -357,6 +351,7 @@ void omap_sram_idle(void)
         int mpu_next_state = PWRDM_POWER_ON;
         int per_next_state = PWRDM_POWER_ON;
         int core_next_state = PWRDM_POWER_ON;
+        int per_going_off;
         int core_prev_state, per_prev_state;
         u32 sdrc_pwr = 0;
 
@@ -395,7 +390,7 @@ void omap_sram_idle(void)
         if (omap3_has_io_wakeup() &&
             (per_next_state < PWRDM_POWER_ON ||
              core_next_state < PWRDM_POWER_ON)) {
-                prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
+                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
                 omap3_enable_io_chain();
         }
 
@@ -408,9 +403,10 @@ void omap_sram_idle(void)
 
         /* PER */
         if (per_next_state < PWRDM_POWER_ON) {
+                per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
                 omap_uart_prepare_idle(2);
                 omap_uart_prepare_idle(3);
-                omap2_gpio_prepare_for_idle(per_next_state);
+                omap2_gpio_prepare_for_idle(per_going_off);
                 if (per_next_state == PWRDM_POWER_OFF)
                                 omap3_per_save_context();
         }
@@ -421,7 +417,7 @@ void omap_sram_idle(void)
                 omap_uart_prepare_idle(1);
                 if (core_next_state == PWRDM_POWER_OFF) {
                         omap3_core_save_context();
-                        omap3_prcm_save_context();
+                        omap3_cm_save_context();
                 }
         }
 
@@ -430,7 +426,7 @@ void omap_sram_idle(void)
         /*
         * On EMU/HS devices ROM code restores a SRDC value
         * from scratchpad which has automatic self refresh on timeout
-        * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
+        * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
         * Hence store/restore the SDRC_POWER register here.
         */
         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
@@ -461,14 +457,14 @@ void omap_sram_idle(void)
                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
                 if (core_prev_state == PWRDM_POWER_OFF) {
                         omap3_core_restore_context();
-                        omap3_prcm_restore_context();
+                        omap3_cm_restore_context();
                         omap3_sram_restore_context();
                         omap2_sms_restore_context();
                 }
                 omap_uart_resume_idle(0);
                 omap_uart_resume_idle(1);
                 if (core_next_state == PWRDM_POWER_OFF)
-                        prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
+                        omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
                                                OMAP3430_GR_MOD,
                                                OMAP3_PRM_VOLTCTRL_OFFSET);
         }
@@ -492,7 +488,8 @@ console_still_active:
         if (omap3_has_io_wakeup() &&
             (per_next_state < PWRDM_POWER_ON ||
              core_next_state < PWRDM_POWER_ON)) {
-                prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
+                omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+                                             PM_WKEN);
                 omap3_disable_io_chain();
         }
 
@@ -529,12 +526,6 @@ out:
 }
 
 #ifdef CONFIG_SUSPEND
-static int omap3_pm_prepare(void)
-{
-        disable_hlt();
-        return 0;
-}
-
 static int omap3_pm_suspend(void)
 {
         struct power_state *pwrst;
@@ -597,14 +588,10 @@ static int omap3_pm_enter(suspend_state_t unused)
         return ret;
 }
 
-static void omap3_pm_finish(void)
-{
-        enable_hlt();
-}
-
 /* Hooks to enable / disable UART interrupts during suspend */
 static int omap3_pm_begin(suspend_state_t state)
 {
+        disable_hlt();
         suspend_state = state;
         omap_uart_enable_irqs(0);
         return 0;
@@ -614,15 +601,14 @@ static void omap3_pm_end(void)
 {
         suspend_state = PM_SUSPEND_ON;
         omap_uart_enable_irqs(1);
+        enable_hlt();
         return;
 }
 
 static struct platform_suspend_ops omap_pm_ops = {
         .begin          = omap3_pm_begin,
         .end            = omap3_pm_end,
-        .prepare        = omap3_pm_prepare,
         .enter          = omap3_pm_enter,
-        .finish         = omap3_pm_finish,
         .valid          = suspend_valid_only_mem,
 };
 #endif /* CONFIG_SUSPEND */
@@ -641,21 +627,21 @@ static struct platform_suspend_ops omap_pm_ops = {
 static void __init omap3_iva_idle(void)
 {
         /* ensure IVA2 clock is disabled */
-        cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* if no clock activity, nothing else to do */
-        if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
+        if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
               OMAP3430_CLKACTIVITY_IVA2_MASK))
                 return;
 
         /* Reset IVA2 */
-        prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
                           OMAP3430_RST2_IVA2_MASK |
                           OMAP3430_RST3_IVA2_MASK,
                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
         /* Enable IVA2 clock */
-        cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
+        omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* Set IVA2 boot mode to 'idle' */
@@ -663,13 +649,13 @@ static void __init omap3_iva_idle(void)
                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 
         /* Un-reset IVA2 */
-        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
+        omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 
         /* Disable IVA2 clock */
-        cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
+        omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 
         /* Reset IVA2 */
-        prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
                           OMAP3430_RST2_IVA2_MASK |
                           OMAP3430_RST3_IVA2_MASK,
                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
@@ -693,10 +679,10 @@ static void __init omap3_d2d_idle(void)
         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 
         /* reset modem */
-        prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
                           CORE_MOD, OMAP2_RM_RSTCTRL);
-        prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
+        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 }
 
 static void __init prcm_setup_regs(void)
@@ -711,23 +697,23 @@ static void __init prcm_setup_regs(void)
 
         /* XXX Reset all wkdeps. This should be done when initializing
          * powerdomains */
-        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
-        prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
+        omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
         if (omap_rev() > OMAP3430_REV_ES1_0) {
-                prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
-                prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
+                omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
+                omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
         } else
-                prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+                omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 
         /*
          * Enable interface clock autoidle for all modules.
          * Note that in the long run this should be done by clockfw
          */
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 OMAP3430_AUTO_MODEM_MASK |
                 OMAP3430ES2_AUTO_MMC3_MASK |
                 OMAP3430ES2_AUTO_ICR_MASK |
@@ -760,7 +746,7 @@ static void __init prcm_setup_regs(void)
                 OMAP3430_AUTO_SSI_MASK,
                 CORE_MOD, CM_AUTOIDLE1);
 
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 OMAP3430_AUTO_PKA_MASK |
                 OMAP3430_AUTO_AES1_MASK |
                 OMAP3430_AUTO_RNG_MASK |
@@ -769,13 +755,13 @@ static void __init prcm_setup_regs(void)
                 CORE_MOD, CM_AUTOIDLE2);
 
         if (omap_rev() > OMAP3430_REV_ES1_0) {
-                cm_write_mod_reg(
+                omap2_cm_write_mod_reg(
                         OMAP3430_AUTO_MAD2D_MASK |
                         OMAP3430ES2_AUTO_USBTLL_MASK,
                         CORE_MOD, CM_AUTOIDLE3);
         }
 
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 OMAP3430_AUTO_WDT2_MASK |
                 OMAP3430_AUTO_WDT1_MASK |
                 OMAP3430_AUTO_GPIO1_MASK |
@@ -784,17 +770,17 @@ static void __init prcm_setup_regs(void)
                 OMAP3430_AUTO_GPT1_MASK,
                 WKUP_MOD, CM_AUTOIDLE);
 
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 OMAP3430_AUTO_DSS_MASK,
                 OMAP3430_DSS_MOD,
                 CM_AUTOIDLE);
 
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 OMAP3430_AUTO_CAM_MASK,
                 OMAP3430_CAM_MOD,
                 CM_AUTOIDLE);
 
-        cm_write_mod_reg(
+        omap2_cm_write_mod_reg(
                 omap3630_auto_uart4_mask |
                 OMAP3430_AUTO_GPIO6_MASK |
                 OMAP3430_AUTO_GPIO5_MASK |
@@ -818,7 +804,7 @@ static void __init prcm_setup_regs(void)
                 CM_AUTOIDLE);
 
         if (omap_rev() > OMAP3430_REV_ES1_0) {
-                cm_write_mod_reg(
+                omap2_cm_write_mod_reg(
                         OMAP3430ES2_AUTO_USBHOST_MASK,
                         OMAP3430ES2_USBHOST_MOD,
                         CM_AUTOIDLE);
@@ -830,16 +816,16 @@ static void __init prcm_setup_regs(void)
          * Set all plls to autoidle. This is needed until autoidle is
          * enabled by clockfw
          */
-        cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
+        omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-        cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
+        omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
                          MPU_MOD,
                          CM_AUTOIDLE2);
-        cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
+        omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
                          PLL_MOD,
                          CM_AUTOIDLE);
-        cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
+        omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
                          PLL_MOD,
                          CM_AUTOIDLE2);
 
@@ -848,31 +834,31 @@ static void __init prcm_setup_regs(void)
          * sys_clkreq. In the long run clock framework should
          * take care of this.
          */
-        prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
+        omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
                              OMAP3430_GR_MOD,
                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 
         /* setup wakup source */
-        prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
                           WKUP_MOD, PM_WKEN);
         /* No need to write EN_IO, that is always enabled */
-        prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
+        omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
                           OMAP3430_GRPSEL_GPT1_MASK |
                           OMAP3430_GRPSEL_GPT12_MASK,
                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
         /* For some reason IO doesn't generate wakeup event even if
          * it is selected to mpu wakeup goup */
-        prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
+        omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 
         /* Enable PM_WKEN to support DSS LPR */
-        prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
+        omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
                                 OMAP3430_DSS_MOD, PM_WKEN);
 
         /* Enable wakeups in PER */
-        prm_write_mod_reg(omap3630_en_uart4_mask |
+        omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
@@ -880,7 +866,7 @@ static void __init prcm_setup_regs(void)
                           OMAP3430_EN_MCBSP4_MASK,
                           OMAP3430_PER_MOD, PM_WKEN);
         /* and allow them to wake up MPU */
-        prm_write_mod_reg(omap3630_grpsel_uart4_mask |
+        omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
                           OMAP3430_GRPSEL_GPIO2_MASK |
                           OMAP3430_GRPSEL_GPIO3_MASK |
                           OMAP3430_GRPSEL_GPIO4_MASK |
@@ -893,22 +879,22 @@ static void __init prcm_setup_regs(void)
                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 
         /* Don't attach IVA interrupts */
-        prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
-        prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
-        prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
-        prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
+        omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+        omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 
         /* Clear any pending 'reset' flags */
-        prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
-        prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
+        omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 
         /* Clear any pending PRCM interrupts */
-        prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
         omap3_iva_idle();
         omap3_d2d_idle();
@@ -925,12 +911,29 @@ void omap3_pm_off_mode_enable(int enable)
                 state = PWRDM_POWER_RET;
 
 #ifdef CONFIG_CPU_IDLE
-        omap3_cpuidle_update_states();
+        /*
+         * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
+         * enable OFF mode in a stable form for previous revisions, restrict
+         * instead to RET
+         */
+        if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+                omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
+        else
+                omap3_cpuidle_update_states(state, state);
 #endif
 
         list_for_each_entry(pwrst, &pwrst_list, node) {
-                pwrst->next_state = state;
-                omap_set_pwrdm_state(pwrst->pwrdm, state);
+                if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
+                                pwrst->pwrdm == core_pwrdm &&
+                                state == PWRDM_POWER_OFF) {
+                        pwrst->next_state = PWRDM_POWER_RET;
+                        WARN_ONCE(1,
+                                "%s: Core OFF disabled due to errata i583\n",
+                                __func__);
+                } else {
+                        pwrst->next_state = state;
+                }
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
         }
 }
 
@@ -1002,6 +1005,17 @@ void omap_push_sram_idle(void)
                                 save_secure_ram_context_sz);
 }
 
+static void __init pm_errata_configure(void)
+{
+        if (cpu_is_omap3630()) {
+                pm34xx_errata |= PM_RTA_ERRATUM_i608;
+                /* Enable the l2 cache toggling in sleep logic */
+                enable_omap3630_toggle_l2_on_restore();
+                if (omap_rev() < OMAP3630_REV_ES1_2)
+                        pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
+        }
+}
+
 static int __init omap3_pm_init(void)
 {
         struct power_state *pwrst, *tmp;
@@ -1011,6 +1025,8 @@ static int __init omap3_pm_init(void)
         if (!cpu_is_omap34xx())
                 return -ENODEV;
 
+        pm_errata_configure();
+
         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 
         /* XXX prcm_setup_regs needs to be before enabling hw
@@ -1058,6 +1074,14 @@ static int __init omap3_pm_init(void)
         pm_idle = omap3_pm_idle;
         omap3_idle_init();
 
+        /*
+         * RTA is disabled during initialization as per erratum i608
+         * it is safer to disable RTA by the bootloader, but we would like
+         * to be doubly sure here and prevent any mishaps.
+         */
+        if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
+                omap3630_ctrl_disable_rta();
+
         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
                 omap3_secure_ram_storage =
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 54544b4fc76b..e9f4862c4de4 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -16,7 +16,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
 #include <mach/omap4-common.h>
 
 struct power_state {
@@ -31,12 +31,6 @@ struct power_state {
 static LIST_HEAD(pwrst_list);
 
 #ifdef CONFIG_SUSPEND
-static int omap4_pm_prepare(void)
-{
-        disable_hlt();
-        return 0;
-}
-
 static int omap4_pm_suspend(void)
 {
         do_wfi();
@@ -59,28 +53,22 @@ static int omap4_pm_enter(suspend_state_t suspend_state)
         return ret;
 }
 
-static void omap4_pm_finish(void)
-{
-        enable_hlt();
-        return;
-}
-
 static int omap4_pm_begin(suspend_state_t state)
 {
+        disable_hlt();
         return 0;
 }
 
 static void omap4_pm_end(void)
 {
+        enable_hlt();
         return;
 }
 
 static struct platform_suspend_ops omap_pm_ops = {
         .begin          = omap4_pm_begin,
         .end            = omap4_pm_end,
-        .prepare        = omap4_pm_prepare,
         .enter          = omap4_pm_enter,
-        .finish         = omap4_pm_finish,
         .valid          = suspend_valid_only_mem,
 };
 #endif /* CONFIG_SUSPEND */
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
new file mode 100644
index 000000000000..171fccd208c7
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -0,0 +1,110 @@
+/*
+ *  linux/arch/arm/mach-omap2/powerdomain-common.c
+ *  Contains common powerdomain framework functions
+ *
+ *  Copyright (C) 2010 Texas Instruments, Inc.
+ *  Copyright (C) 2010 Nokia Corporation
+ *
+ * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include "pm.h"
+#include "cm.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
+#include "prm-regbits-34xx.h"
+#include "prm-regbits-44xx.h"
+
+/*
+ * OMAP3 and OMAP4 specific register bit initialisations
+ * Notice that the names here are not according to each power
+ * domain but the bit mapping used applies to all of them
+ */
+/* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
+#define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
+#define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
+#define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
+#define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
+#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
+
+/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
+#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
+#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
+#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
+#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
+#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
+
+/* OMAP3 and OMAP4 Memory Status bits */
+#define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
+#define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
+#define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
+#define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
+#define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
+
+/* Common Internal functions used across OMAP rev's*/
+u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP_MEM0_ONSTATE_MASK;
+        case 1:
+                return OMAP_MEM1_ONSTATE_MASK;
+        case 2:
+                return OMAP_MEM2_ONSTATE_MASK;
+        case 3:
+                return OMAP_MEM3_ONSTATE_MASK;
+        case 4:
+                return OMAP_MEM4_ONSTATE_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+
+u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP_MEM0_RETSTATE_MASK;
+        case 1:
+                return OMAP_MEM1_RETSTATE_MASK;
+        case 2:
+                return OMAP_MEM2_RETSTATE_MASK;
+        case 3:
+                return OMAP_MEM3_RETSTATE_MASK;
+        case 4:
+                return OMAP_MEM4_RETSTATE_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+
+u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP_MEM0_STATEST_MASK;
+        case 1:
+                return OMAP_MEM1_STATEST_MASK;
+        case 2:
+                return OMAP_MEM2_STATEST_MASK;
+        case 3:
+                return OMAP_MEM3_STATEST_MASK;
+        case 4:
+                return OMAP_MEM4_STATEST_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 6527ec30dc17..eaed0df16699 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -15,27 +15,19 @@
 #undef DEBUG
 
 #include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/spinlock.h>
 #include <linux/list.h>
 #include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <asm/atomic.h>
-
-#include "cm.h"
-#include "cm-regbits-34xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm.h"
-#include "prm-regbits-34xx.h"
-#include "prm-regbits-44xx.h"
+#include <linux/string.h>
+#include "cm2xxx_3xxx.h"
+#include "prcm44xx.h"
+#include "cm44xx.h"
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
 
 #include <plat/cpu.h>
-#include <plat/powerdomain.h>
-#include <plat/clockdomain.h>
+#include "powerdomain.h"
+#include "clockdomain.h"
 #include <plat/prcm.h>
 
 #include "pm.h"
@@ -45,41 +37,12 @@ enum {
         PWRDM_STATE_PREV,
 };
 
-/* Variable holding value of the CPU dependent PWRSTCTRL Register Offset */
-static u16 pwrstctrl_reg_offs;
-
-/* Variable holding value of the CPU dependent PWRSTST Register Offset */
-static u16 pwrstst_reg_offs;
-
-/* OMAP3 and OMAP4 specific register bit initialisations
- * Notice that the names here are not according to each power
- * domain but the bit mapping used applies to all of them
- */
-
-/* OMAP3 and OMAP4 Memory Onstate Masks (common across all power domains) */
-#define OMAP_MEM0_ONSTATE_MASK OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK
-#define OMAP_MEM1_ONSTATE_MASK OMAP3430_L1FLATMEMONSTATE_MASK
-#define OMAP_MEM2_ONSTATE_MASK OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK
-#define OMAP_MEM3_ONSTATE_MASK OMAP3430_L2FLATMEMONSTATE_MASK
-#define OMAP_MEM4_ONSTATE_MASK OMAP4430_OCP_NRET_BANK_ONSTATE_MASK
-
-/* OMAP3 and OMAP4 Memory Retstate Masks (common across all power domains) */
-#define OMAP_MEM0_RETSTATE_MASK OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK
-#define OMAP_MEM1_RETSTATE_MASK OMAP3430_L1FLATMEMRETSTATE_MASK
-#define OMAP_MEM2_RETSTATE_MASK OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK
-#define OMAP_MEM3_RETSTATE_MASK OMAP3430_L2FLATMEMRETSTATE_MASK
-#define OMAP_MEM4_RETSTATE_MASK OMAP4430_OCP_NRET_BANK_RETSTATE_MASK
-
-/* OMAP3 and OMAP4 Memory Status bits */
-#define OMAP_MEM0_STATEST_MASK OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK
-#define OMAP_MEM1_STATEST_MASK OMAP3430_L1FLATMEMSTATEST_MASK
-#define OMAP_MEM2_STATEST_MASK OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK
-#define OMAP_MEM3_STATEST_MASK OMAP3430_L2FLATMEMSTATEST_MASK
-#define OMAP_MEM4_STATEST_MASK OMAP4430_OCP_NRET_BANK_STATEST_MASK
 
 /* pwrdm_list contains all registered struct powerdomains */
 static LIST_HEAD(pwrdm_list);
 
+static struct pwrdm_ops *arch_pwrdm;
+
 /* Private functions */
 
 static struct powerdomain *_pwrdm_lookup(const char *name)
@@ -110,12 +73,19 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
 {
         int i;
 
-        if (!pwrdm)
+        if (!pwrdm || !pwrdm->name)
                 return -EINVAL;
 
         if (!omap_chip_is(pwrdm->omap_chip))
                 return -EINVAL;
 
+        if (cpu_is_omap44xx() &&
+            pwrdm->prcm_partition == OMAP4430_INVALID_PRCM_PARTITION) {
+                pr_err("powerdomain: %s: missing OMAP4 PRCM partition ID\n",
+                       pwrdm->name);
+                return -EINVAL;
+        }
+
         if (_pwrdm_lookup(pwrdm->name))
                 return -EEXIST;
 
@@ -211,6 +181,7 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
 /**
  * pwrdm_init - set up the powerdomain layer
  * @pwrdm_list: array of struct powerdomain pointers to register
+ * @custom_funcs: func pointers for arch specfic implementations
  *
  * Loop through the array of powerdomains @pwrdm_list, registering all
  * that are available on the current CPU. If pwrdm_list is supplied
@@ -218,21 +189,14 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
  * registered.  No return value.  XXX pwrdm_list is not really a
  * "list"; it is an array.  Rename appropriately.
  */
-void pwrdm_init(struct powerdomain **pwrdm_list)
+void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs)
 {
         struct powerdomain **p = NULL;
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                pwrstctrl_reg_offs = OMAP2_PM_PWSTCTRL;
-                pwrstst_reg_offs = OMAP2_PM_PWSTST;
-        } else if (cpu_is_omap44xx()) {
-                pwrstctrl_reg_offs = OMAP4_PM_PWSTCTRL;
-                pwrstst_reg_offs = OMAP4_PM_PWSTST;
-        } else {
-                printk(KERN_ERR "Power Domain struct not supported for " \
-                                                        "this CPU\n");
-                return;
-        }
+        if (!custom_funcs)
+                WARN(1, "powerdomain: No custom pwrdm functions registered\n");
+        else
+                arch_pwrdm = custom_funcs;
 
         if (pwrdm_list) {
                 for (p = pwrdm_list; *p; p++)
@@ -431,6 +395,8 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm)
  */
 int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
@@ -440,11 +406,10 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
         pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
                  pwrdm->name, pwrst);
 
-        prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
-                             (pwrst << OMAP_POWERSTATE_SHIFT),
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst)
+                ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -457,11 +422,15 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
  */
 int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                 pwrstctrl_reg_offs, OMAP_POWERSTATE_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_next_pwrst)
+                ret = arch_pwrdm->pwrdm_read_next_pwrst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -474,11 +443,15 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                 pwrstst_reg_offs, OMAP_POWERSTATEST_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_pwrst)
+                ret = arch_pwrdm->pwrdm_read_pwrst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -491,11 +464,15 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
-                                        OMAP3430_LASTPOWERSTATEENTERED_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_pwrst)
+                ret = arch_pwrdm->pwrdm_read_prev_pwrst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -511,7 +488,7 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 {
-        u32 v;
+        int ret = -EINVAL;
 
         if (!pwrdm)
                 return -EINVAL;
@@ -522,17 +499,10 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
         pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
                  pwrdm->name, pwrst);
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
-        prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
+                ret = arch_pwrdm->pwrdm_set_logic_retst(pwrdm, pwrst);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -552,7 +522,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
  */
 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
 {
-        u32 m;
+        int ret = -EINVAL;
 
         if (!pwrdm)
                 return -EINVAL;
@@ -566,37 +536,10 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
         pr_debug("powerdomain: setting next memory powerstate for domain %s "
                  "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        switch (bank) {
-        case 0:
-                m = OMAP_MEM0_ONSTATE_MASK;
-                break;
-        case 1:
-                m = OMAP_MEM1_ONSTATE_MASK;
-                break;
-        case 2:
-                m = OMAP_MEM2_ONSTATE_MASK;
-                break;
-        case 3:
-                m = OMAP_MEM3_ONSTATE_MASK;
-                break;
-        case 4:
-                m = OMAP_MEM4_ONSTATE_MASK;
-                break;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
+                ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
 
-        prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)),
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
-
-        return 0;
+        return ret;
 }
 
 /**
@@ -617,7 +560,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
  */
 int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
 {
-        u32 m;
+        int ret = -EINVAL;
 
         if (!pwrdm)
                 return -EINVAL;
@@ -631,37 +574,10 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
         pr_debug("powerdomain: setting next memory powerstate for domain %s "
                  "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        switch (bank) {
-        case 0:
-                m = OMAP_MEM0_RETSTATE_MASK;
-                break;
-        case 1:
-                m = OMAP_MEM1_RETSTATE_MASK;
-                break;
-        case 2:
-                m = OMAP_MEM2_RETSTATE_MASK;
-                break;
-        case 3:
-                m = OMAP_MEM3_RETSTATE_MASK;
-                break;
-        case 4:
-                m = OMAP_MEM4_RETSTATE_MASK;
-                break;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
-
-        prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
-                             pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
+                ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -675,11 +591,15 @@ int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst)
  */
 int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstst_reg_offs,
-                                       OMAP3430_LOGICSTATEST_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_pwrst)
+                ret = arch_pwrdm->pwrdm_read_logic_pwrst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -692,17 +612,15 @@ int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST,
-                                        OMAP3430_LASTLOGICSTATEENTERED_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_logic_pwrst)
+                ret = arch_pwrdm->pwrdm_read_prev_logic_pwrst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -715,17 +633,15 @@ int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_logic_retst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs, pwrstctrl_reg_offs,
-                                       OMAP3430_LOGICSTATEST_MASK);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_logic_retst)
+                ret = arch_pwrdm->pwrdm_read_logic_retst(pwrdm);
+
+        return ret;
 }
 
 /**
@@ -740,46 +656,21 @@ int pwrdm_read_logic_retst(struct powerdomain *pwrdm)
  */
 int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 {
-        u32 m;
+        int ret = -EINVAL;
 
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         if (pwrdm->banks < (bank + 1))
-                return -EEXIST;
+                return ret;
 
         if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
                 bank = 1;
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        switch (bank) {
-        case 0:
-                m = OMAP_MEM0_STATEST_MASK;
-                break;
-        case 1:
-                m = OMAP_MEM1_STATEST_MASK;
-                break;
-        case 2:
-                m = OMAP_MEM2_STATEST_MASK;
-                break;
-        case 3:
-                m = OMAP_MEM3_STATEST_MASK;
-                break;
-        case 4:
-                m = OMAP_MEM4_STATEST_MASK;
-                break;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_pwrst)
+                ret = arch_pwrdm->pwrdm_read_mem_pwrst(pwrdm, bank);
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                         pwrstst_reg_offs, m);
+        return ret;
 }
 
 /**
@@ -795,43 +686,21 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
  */
 int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 {
-        u32 m;
+        int ret = -EINVAL;
 
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         if (pwrdm->banks < (bank + 1))
-                return -EEXIST;
+                return ret;
 
         if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
                 bank = 1;
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        switch (bank) {
-        case 0:
-                m = OMAP3430_LASTMEM1STATEENTERED_MASK;
-                break;
-        case 1:
-                m = OMAP3430_LASTMEM2STATEENTERED_MASK;
-                break;
-        case 2:
-                m = OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
-                break;
-        case 3:
-                m = OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
-                break;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_prev_mem_pwrst)
+                ret = arch_pwrdm->pwrdm_read_prev_mem_pwrst(pwrdm, bank);
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                        OMAP3430_PM_PREPWSTST, m);
+        return ret;
 }
 
 /**
@@ -846,43 +715,18 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
  */
 int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
 {
-        u32 m;
+        int ret = -EINVAL;
 
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         if (pwrdm->banks < (bank + 1))
-                return -EEXIST;
+                return ret;
 
-        /*
-         * The register bit names below may not correspond to the
-         * actual names of the bits in each powerdomain's register,
-         * but the type of value returned is the same for each
-         * powerdomain.
-         */
-        switch (bank) {
-        case 0:
-                m = OMAP_MEM0_RETSTATE_MASK;
-                break;
-        case 1:
-                m = OMAP_MEM1_RETSTATE_MASK;
-                break;
-        case 2:
-                m = OMAP_MEM2_RETSTATE_MASK;
-                break;
-        case 3:
-                m = OMAP_MEM3_RETSTATE_MASK;
-                break;
-        case 4:
-                m = OMAP_MEM4_RETSTATE_MASK;
-                break;
-        default:
-                WARN_ON(1); /* should never happen */
-                return -EEXIST;
-        }
+        if (arch_pwrdm && arch_pwrdm->pwrdm_read_mem_retst)
+                ret = arch_pwrdm->pwrdm_read_mem_retst(pwrdm, bank);
 
-        return prm_read_mod_bits_shift(pwrdm->prcm_offs,
-                                        pwrstctrl_reg_offs, m);
+        return ret;
 }
 
 /**
@@ -896,8 +740,10 @@ int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
  */
 int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         /*
          * XXX should get the powerdomain's current state here;
@@ -907,9 +753,10 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
         pr_debug("powerdomain: clearing previous power state reg for %s\n",
                  pwrdm->name);
 
-        prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
+                ret = arch_pwrdm->pwrdm_clear_all_prev_pwrst(pwrdm);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -925,19 +772,21 @@ int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
  */
 int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
-                return -EINVAL;
+                return ret;
 
         pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
                  pwrdm->name);
 
-        prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
+                ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -953,19 +802,21 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
  */
 int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
-                return -EINVAL;
+                return ret;
 
         if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
-                return -EINVAL;
+                return ret;
 
         pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
                  pwrdm->name);
 
-        prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0,
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
+                ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -992,6 +843,8 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
  */
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
 {
+        int ret = -EINVAL;
+
         if (!pwrdm)
                 return -EINVAL;
 
@@ -1001,11 +854,10 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
         pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n",
                  pwrdm->name);
 
-        prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
-                             (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
-                             pwrdm->prcm_offs, pwrstctrl_reg_offs);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_set_lowpwrstchange)
+                ret = arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm);
 
-        return 0;
+        return ret;
 }
 
 /**
@@ -1020,32 +872,15 @@ int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
  */
 int pwrdm_wait_transition(struct powerdomain *pwrdm)
 {
-        u32 c = 0;
+        int ret = -EINVAL;
 
         if (!pwrdm)
                 return -EINVAL;
 
-        /*
-         * REVISIT: pwrdm_wait_transition() may be better implemented
-         * via a callback and a periodic timer check -- how long do we expect
-         * powerdomain transitions to take?
-         */
-
-        /* XXX Is this udelay() value meaningful? */
-        while ((prm_read_mod_reg(pwrdm->prcm_offs, pwrstst_reg_offs) &
-                OMAP_INTRANSITION_MASK) &&
-               (c++ < PWRDM_TRANSITION_BAILOUT))
-                        udelay(1);
-
-        if (c > PWRDM_TRANSITION_BAILOUT) {
-                printk(KERN_ERR "powerdomain: waited too long for "
-                       "powerdomain %s to complete transition\n", pwrdm->name);
-                return -EAGAIN;
-        }
-
-        pr_debug("powerdomain: completed transition in %d loops\n", c);
+        if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition)
+                ret = arch_pwrdm->pwrdm_wait_transition(pwrdm);
 
-        return 0;
+        return ret;
 }
 
 int pwrdm_state_switch(struct powerdomain *pwrdm)
@@ -1075,3 +910,31 @@ int pwrdm_post_transition(void)
         return 0;
 }
 
+/**
+ * pwrdm_get_context_loss_count - get powerdomain's context loss count
+ * @pwrdm: struct powerdomain * to wait for
+ *
+ * Context loss count is the sum of powerdomain off-mode counter, the
+ * logic off counter and the per-bank memory off counter.  Returns 0
+ * (and WARNs) upon error, otherwise, returns the context loss count.
+ */
+u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
+{
+        int i, count;
+
+        if (!pwrdm) {
+                WARN(1, "powerdomain: %s: pwrdm is null\n", __func__);
+                return 0;
+        }
+
+        count = pwrdm->state_counter[PWRDM_POWER_OFF];
+        count += pwrdm->ret_logic_off_counter;
+
+        for (i = 0; i < pwrdm->banks; i++)
+                count += pwrdm->ret_mem_off_counter[i];
+
+        pr_debug("powerdomain: %s: context loss count = %u\n",
+                 pwrdm->name, count);
+
+        return count;
+}
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 9ca420dcd2f8..c66431edfeb7 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -1,27 +1,29 @@
 /*
- * OMAP2/3 powerdomain control
+ * OMAP2/3/4 powerdomain control
  *
- * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010 Nokia Corporation
  *
- * Written by Paul Walmsley
+ * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
+ *
+ * XXX This should be moved to the mach-omap2/ directory at the earliest
+ * opportunity.
  */
 
-#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
-#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
+#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
+#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
 
 #include <linux/types.h>
 #include <linux/list.h>
 
-#include <asm/atomic.h>
+#include <linux/atomic.h>
 
 #include <plat/cpu.h>
 
-
 /* Powerdomain basic power states */
 #define PWRDM_POWER_OFF         0x0
 #define PWRDM_POWER_RET         0x1
@@ -81,6 +83,7 @@ struct powerdomain;
  * @name: Powerdomain name
  * @omap_chip: represents the OMAP chip types containing this pwrdm
  * @prcm_offs: the address offset from CM_BASE/PRM_BASE
+ * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
  * @pwrsts: Possible powerdomain power states
  * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
  * @flags: Powerdomain flags
@@ -93,6 +96,8 @@ struct powerdomain;
  * @state_counter:
  * @timer:
  * @state_timer:
+ *
+ * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
  */
 struct powerdomain {
         const char *name;
@@ -104,6 +109,7 @@ struct powerdomain {
         const u8 banks;
         const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
         const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
+        const u8 prcm_partition;
         struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
         struct list_head node;
         int state;
@@ -117,8 +123,50 @@ struct powerdomain {
 #endif
 };
 
+/**
+ * struct pwrdm_ops - Arch specfic function implementations
+ * @pwrdm_set_next_pwrst: Set the target power state for a pd
+ * @pwrdm_read_next_pwrst: Read the target power state set for a pd
+ * @pwrdm_read_pwrst: Read the current power state of a pd
+ * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
+ * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
+ * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
+ * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
+ * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
+ * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
+ * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
+ * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
+ * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
+ * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
+ * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
+ * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
+ * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
+ * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
+ * @pwrdm_wait_transition: Wait for a pd state transition to complete
+ */
+struct pwrdm_ops {
+        int     (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
+        int     (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
+        int     (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+        int     (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
+        int     (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
+        int     (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
+        int     (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
+        int     (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
+        int     (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
+        int     (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
+        int     (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
+        int     (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+};
 
-void pwrdm_init(struct powerdomain **pwrdm_list);
+void pwrdm_fw_init(void);
+void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs);
 
 struct powerdomain *pwrdm_lookup(const char *name);
 
@@ -163,5 +211,23 @@ int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
 int pwrdm_pre_transition(void);
 int pwrdm_post_transition(void);
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
+u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
+
+extern void omap2xxx_powerdomains_init(void);
+extern void omap3xxx_powerdomains_init(void);
+extern void omap44xx_powerdomains_init(void);
+
+extern struct pwrdm_ops omap2_pwrdm_operations;
+extern struct pwrdm_ops omap3_pwrdm_operations;
+extern struct pwrdm_ops omap4_pwrdm_operations;
+
+/* Common Internal functions used across OMAP rev's */
+extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
+extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
+extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
+
+extern struct powerdomain wkup_omap2_pwrdm;
+extern struct powerdomain gfx_omap2_pwrdm;
+
 
 #endif
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
new file mode 100644
index 000000000000..d5233890370c
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -0,0 +1,242 @@
+/*
+ * OMAP2 and OMAP3 powerdomain control
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <plat/prcm.h>
+
+#include "powerdomain.h"
+#include "prm-regbits-34xx.h"
+#include "prm.h"
+#include "prm-regbits-24xx.h"
+#include "prm-regbits-34xx.h"
+
+
+/* Common functions across OMAP2 and OMAP3 */
+static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
+                                (pwrst << OMAP_POWERSTATE_SHIFT),
+                                pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+        return 0;
+}
+
+static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL,
+                                             OMAP_POWERSTATE_MASK);
+}
+
+static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTST,
+                                             OMAP_POWERSTATEST_MASK);
+}
+
+static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                                                u8 pwrst)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+
+        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                                                u8 pwrst)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+
+        omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs,
+                                   OMAP2_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST,
+                                             m);
+}
+
+static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL, m);
+}
+
+static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 v;
+
+        v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK);
+        omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v,
+                                   pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+
+        /* XXX Is this udelay() value meaningful? */
+        while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) &
+                OMAP_INTRANSITION_MASK) &&
+                (c++ < PWRDM_TRANSITION_BAILOUT))
+                        udelay(1);
+
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                printk(KERN_ERR "powerdomain: waited too long for "
+                        "powerdomain %s to complete transition\n", pwrdm->name);
+                return -EAGAIN;
+        }
+
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+        return 0;
+}
+
+/* Applicable only for OMAP3. Not supported on OMAP2 */
+static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP3430_PM_PREPWSTST,
+                                             OMAP3430_LASTPOWERSTATEENTERED_MASK);
+}
+
+static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTST,
+                                             OMAP3430_LOGICSTATEST_MASK);
+}
+
+static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP2_PM_PWSTCTRL,
+                                             OMAP3430_LOGICSTATEST_MASK);
+}
+
+static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                             OMAP3430_PM_PREPWSTST,
+                                             OMAP3430_LASTLOGICSTATEENTERED_MASK);
+}
+
+static int omap3_get_mem_bank_lastmemst_mask(u8 bank)
+{
+        switch (bank) {
+        case 0:
+                return OMAP3430_LASTMEM1STATEENTERED_MASK;
+        case 1:
+                return OMAP3430_LASTMEM2STATEENTERED_MASK;
+        case 2:
+                return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK;
+        case 3:
+                return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK;
+        default:
+                WARN_ON(1); /* should never happen */
+                return -EEXIST;
+        }
+        return 0;
+}
+
+static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m;
+
+        m = omap3_get_mem_bank_lastmemst_mask(bank);
+
+        return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
+                                OMAP3430_PM_PREPWSTST, m);
+}
+
+static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST);
+        return 0;
+}
+
+static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return omap2_prm_rmw_mod_reg_bits(0,
+                                          1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                                          pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
+}
+
+static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm)
+{
+        return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT,
+                                          0, pwrdm->prcm_offs,
+                                          OMAP2_PM_PWSTCTRL);
+}
+
+struct pwrdm_ops omap2_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
+        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
+        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
+        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
+        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
+};
+
+struct pwrdm_ops omap3_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap2_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap2_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap2_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst  = omap3_pwrdm_read_prev_pwrst,
+        .pwrdm_set_logic_retst  = omap2_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst,
+        .pwrdm_read_prev_logic_pwrst    = omap3_pwrdm_read_prev_logic_pwrst,
+        .pwrdm_set_mem_onst     = omap2_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap2_pwrdm_set_mem_retst,
+        .pwrdm_read_mem_pwrst   = omap2_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap2_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap3_pwrdm_read_prev_mem_pwrst,
+        .pwrdm_clear_all_prev_pwrst     = omap3_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_enable_hdwr_sar  = omap3_pwrdm_enable_hdwr_sar,
+        .pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar,
+        .pwrdm_wait_transition  = omap2_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
new file mode 100644
index 000000000000..a7880af4b3d9
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -0,0 +1,225 @@
+/*
+ * OMAP4 powerdomain control
+ *
+ * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009 Nokia Corporation
+ *
+ * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include "powerdomain.h"
+#include <plat/prcm.h>
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+#include "prminst44xx.h"
+#include "prm-regbits-44xx.h"
+
+static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
+                                        (pwrst << OMAP_POWERSTATE_SHIFT),
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+
+static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= OMAP_POWERSTATE_MASK;
+        v >>= OMAP_POWERSTATE_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP_POWERSTATEST_MASK;
+        v >>= OMAP_POWERSTATEST_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
+        v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
+                                        (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
+        return 0;
+}
+
+static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
+                                        OMAP4430_LASTPOWERSTATEENTERED_MASK,
+                                        pwrdm->prcm_partition,
+                                        pwrdm->prcm_offs, OMAP4_PM_PWSTST);
+        return 0;
+}
+
+static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 v;
+
+        v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
+        omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                                    u8 pwrst)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
+
+        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                     u8 pwrst)
+{
+        u32 m;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+
+        omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
+                                        pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+
+        return 0;
+}
+
+static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= OMAP4430_LOGICSTATEST_MASK;
+        v >>= OMAP4430_LOGICSTATEST_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= OMAP4430_LOGICRETSTATE_MASK;
+        v >>= OMAP4430_LOGICRETSTATE_SHIFT;
+
+        return v;
+}
+
+static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTST);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
+
+        v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
+                                        OMAP4_PM_PWSTCTRL);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+
+        /* XXX Is this udelay() value meaningful? */
+        while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
+                                            pwrdm->prcm_offs,
+                                            OMAP4_PM_PWSTST) &
+                OMAP_INTRANSITION_MASK) &&
+               (c++ < PWRDM_TRANSITION_BAILOUT))
+                udelay(1);
+
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                printk(KERN_ERR "powerdomain: waited too long for "
+                       "powerdomain %s to complete transition\n", pwrdm->name);
+                return -EAGAIN;
+        }
+
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+        return 0;
+}
+
+struct pwrdm_ops omap4_pwrdm_operations = {
+        .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
+        .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
+        .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
+        .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
+        .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
+        .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 105cbcaefd3b..5b4dd971320a 100644
--- a/arch/arm/mach-omap2/powerdomains.h
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -2,10 +2,9 @@
  * OMAP2/3 common powerdomain definitions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2010 Nokia Corporation
  *
- * Written by Paul Walmsley
- * Debugging and integration fixes by Jouni Högander
+ * Paul Walmsley, Jouni Högander
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -18,9 +17,6 @@
  *    Clock Domain Framework
  */
 
-#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS
-#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS
-
 /*
  * This file contains all of the powerdomains that have some element
  * of software control for the OMAP24xx and OMAP34xx chips.
@@ -49,24 +45,18 @@
  * address offset is different between the C55 and C64 DSPs.
  */
 
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
 
 #include "prcm-common.h"
 #include "prm.h"
-#include "cm.h"
-#include "powerdomains24xx.h"
-#include "powerdomains34xx.h"
-#include "powerdomains44xx.h"
 
 /* OMAP2/3-common powerdomains */
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-
 /*
  * The GFX powerdomain is not present on 3430ES2, but currently we do not
  * have a macro to filter it out at compile-time.
  */
-static struct powerdomain gfx_omap2_pwrdm = {
+struct powerdomain gfx_omap2_pwrdm = {
         .name             = "gfx_pwrdm",
         .prcm_offs        = GFX_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
@@ -82,72 +72,8 @@ static struct powerdomain gfx_omap2_pwrdm = {
         },
 };
 
-static struct powerdomain wkup_omap2_pwrdm = {
+struct powerdomain wkup_omap2_pwrdm = {
         .name           = "wkup_pwrdm",
         .prcm_offs      = WKUP_MOD,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 };
-
-#endif
-
-
-/* As powerdomains are added or removed above, this list must also be changed */
-static struct powerdomain *powerdomains_omap[] __initdata = {
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        &wkup_omap2_pwrdm,
-        &gfx_omap2_pwrdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-        &dsp_pwrdm,
-        &mpu_24xx_pwrdm,
-        &core_24xx_pwrdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2430
-        &mdm_pwrdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-        &iva2_pwrdm,
-        &mpu_3xxx_pwrdm,
-        &neon_pwrdm,
-        &core_3xxx_pre_es3_1_pwrdm,
-        &core_3xxx_es3_1_pwrdm,
-        &cam_pwrdm,
-        &dss_pwrdm,
-        &per_pwrdm,
-        &emu_pwrdm,
-        &sgx_pwrdm,
-        &usbhost_pwrdm,
-        &dpll1_pwrdm,
-        &dpll2_pwrdm,
-        &dpll3_pwrdm,
-        &dpll4_pwrdm,
-        &dpll5_pwrdm,
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-        &core_44xx_pwrdm,
-        &gfx_44xx_pwrdm,
-        &abe_44xx_pwrdm,
-        &dss_44xx_pwrdm,
-        &tesla_44xx_pwrdm,
-        &wkup_44xx_pwrdm,
-        &cpu0_44xx_pwrdm,
-        &cpu1_44xx_pwrdm,
-        &emu_44xx_pwrdm,
-        &mpu_44xx_pwrdm,
-        &ivahd_44xx_pwrdm,
-        &cam_44xx_pwrdm,
-        &l3init_44xx_pwrdm,
-        &l4per_44xx_pwrdm,
-        &always_on_core_44xx_pwrdm,
-        &cefuse_44xx_pwrdm,
-#endif
-        NULL
-};
-
-
-#endif
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h
new file mode 100644
index 000000000000..fa311669d53d
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h
@@ -0,0 +1,22 @@
+/*
+ * OMAP2/3 common powerdomains - prototypes
+ *
+ * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
+#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H
+
+#include "powerdomain.h"
+
+extern struct powerdomain gfx_omap2_pwrdm;
+extern struct powerdomain wkup_omap2_pwrdm;
+
+#endif
diff --git a/arch/arm/mach-omap2/powerdomains24xx.h b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 775093add9b6..9b1a33500577 100644
--- a/arch/arm/mach-omap2/powerdomains24xx.h
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -1,37 +1,28 @@
 /*
- * OMAP24XX powerdomain definitions
+ * OMAP2XXX powerdomain definitions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2010 Nokia Corporation
  *
- * Written by Paul Walmsley
- * Debugging and integration fixes by Jouni Högander
+ * Paul Walmsley, Jouni Högander
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
-#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS24XX
+#include <linux/kernel.h>
+#include <linux/init.h>
 
-/*
- * N.B. If powerdomains are added or removed from this file, update
- * the array in mach-omap2/powerdomains.h.
- */
-
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
+#include "powerdomains2xxx_3xxx_data.h"
 
 #include "prcm-common.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
-#include "cm.h"
-#include "cm-regbits-24xx.h"
 
 /* 24XX powerdomains and dependencies */
 
-#ifdef CONFIG_ARCH_OMAP2
-
 /* Powerdomains */
 
 static struct powerdomain dsp_pwrdm = {
@@ -82,9 +73,6 @@ static struct powerdomain core_24xx_pwrdm = {
         },
 };
 
-#endif     /* CONFIG_ARCH_OMAP2 */
-
-
 
 /*
  * 2430-specific powerdomains
@@ -111,5 +99,25 @@ static struct powerdomain mdm_pwrdm = {
 
 #endif     /* CONFIG_ARCH_OMAP2430 */
 
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap2xxx[] __initdata = {
 
+        &wkup_omap2_pwrdm,
+        &gfx_omap2_pwrdm,
+
+#ifdef CONFIG_ARCH_OMAP2
+        &dsp_pwrdm,
+        &mpu_24xx_pwrdm,
+        &core_24xx_pwrdm,
 #endif
+
+#ifdef CONFIG_ARCH_OMAP2430
+        &mdm_pwrdm,
+#endif
+        NULL
+};
+
+void __init omap2xxx_powerdomains_init(void)
+{
+        pwrdm_init(powerdomains_omap2xxx, &omap2_pwrdm_operations);
+}
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index fa904861668b..e1bec562625b 100644
--- a/arch/arm/mach-omap2/powerdomains34xx.h
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -4,28 +4,23 @@
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
  * Copyright (C) 2007-2010 Nokia Corporation
  *
- * Written by Paul Walmsley
- * Debugging and integration fixes by Jouni Högander
+ * Paul Walmsley, Jouni Högander
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
-#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
+#include <linux/kernel.h>
+#include <linux/init.h>
 
-/*
- * N.B. If powerdomains are added or removed from this file, update
- * the array in mach-omap2/powerdomains.h.
- */
-
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
+#include "powerdomains2xxx_3xxx_data.h"
 
 #include "prcm-common.h"
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 
 /*
@@ -80,6 +75,10 @@ static struct powerdomain mpu_3xxx_pwrdm = {
  * 3430s upto ES3.0 and 3630ES1.0. Hence this feature
  * needs to be disabled on these chips.
  * Refer: 3430 errata ID i459 and 3630 errata ID i579
+ *
+ * Note: setting the SAR flag could help for errata ID i478
+ *  which applies to 3430 <= ES3.1, but since the SAR feature
+ *  is broken, do not use it.
  */
 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
         .name             = "core_pwrdm",
@@ -108,6 +107,10 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
                                           CHIP_GE_OMAP3630ES1_1),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        /*
+         * Setting the SAR flag for errata ID i478 which applies
+         *  to 3430 <= ES3.1
+         */
         .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
         .banks            = 2,
         .pwrsts_mem_ret   = {
@@ -252,8 +255,33 @@ static struct powerdomain dpll5_pwrdm = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 };
 
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap3xxx[] __initdata = {
 
-#endif    /* CONFIG_ARCH_OMAP3 */
+        &wkup_omap2_pwrdm,
+        &gfx_omap2_pwrdm,
+        &iva2_pwrdm,
+        &mpu_3xxx_pwrdm,
+        &neon_pwrdm,
+        &core_3xxx_pre_es3_1_pwrdm,
+        &core_3xxx_es3_1_pwrdm,
+        &cam_pwrdm,
+        &dss_pwrdm,
+        &per_pwrdm,
+        &emu_pwrdm,
+        &sgx_pwrdm,
+        &usbhost_pwrdm,
+        &dpll1_pwrdm,
+        &dpll2_pwrdm,
+        &dpll3_pwrdm,
+        &dpll4_pwrdm,
+        &dpll5_pwrdm,
+#endif
+        NULL
+};
 
 
-#endif
+void __init omap3xxx_powerdomains_init(void)
+{
+        pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations);
+}
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 9c01b55d6102..26d7641076d7 100644
--- a/arch/arm/mach-omap2/powerdomains44xx.h
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -19,23 +19,22 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
-#define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS44XX_H
+#include <linux/kernel.h>
+#include <linux/init.h>
 
-#include <plat/powerdomain.h>
+#include "powerdomain.h"
 
 #include "prcm-common.h"
-#include "cm.h"
-#include "cm-regbits-44xx.h"
-#include "prm.h"
+#include "prcm44xx.h"
 #include "prm-regbits-44xx.h"
-
-#if defined(CONFIG_ARCH_OMAP4)
+#include "prm44xx.h"
+#include "prcm_mpu44xx.h"
 
 /* core_44xx_pwrdm: CORE power domain */
 static struct powerdomain core_44xx_pwrdm = {
         .name             = "core_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_CORE_MOD,
+        .prcm_offs        = OMAP4430_PRM_CORE_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -60,7 +59,8 @@ static struct powerdomain core_44xx_pwrdm = {
 /* gfx_44xx_pwrdm: 3D accelerator power domain */
 static struct powerdomain gfx_44xx_pwrdm = {
         .name             = "gfx_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_GFX_MOD,
+        .prcm_offs        = OMAP4430_PRM_GFX_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
@@ -76,7 +76,8 @@ static struct powerdomain gfx_44xx_pwrdm = {
 /* abe_44xx_pwrdm: Audio back end power domain */
 static struct powerdomain abe_44xx_pwrdm = {
         .name             = "abe_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_ABE_MOD,
+        .prcm_offs        = OMAP4430_PRM_ABE_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRDM_POWER_OFF,
@@ -95,7 +96,8 @@ static struct powerdomain abe_44xx_pwrdm = {
 /* dss_44xx_pwrdm: Display subsystem power domain */
 static struct powerdomain dss_44xx_pwrdm = {
         .name             = "dss_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_DSS_MOD,
+        .prcm_offs        = OMAP4430_PRM_DSS_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF,
@@ -112,7 +114,8 @@ static struct powerdomain dss_44xx_pwrdm = {
 /* tesla_44xx_pwrdm: Tesla processor power domain */
 static struct powerdomain tesla_44xx_pwrdm = {
         .name             = "tesla_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_TESLA_MOD,
+        .prcm_offs        = OMAP4430_PRM_TESLA_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -133,7 +136,8 @@ static struct powerdomain tesla_44xx_pwrdm = {
 /* wkup_44xx_pwrdm: Wake-up power domain */
 static struct powerdomain wkup_44xx_pwrdm = {
         .name             = "wkup_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_WKUP_MOD,
+        .prcm_offs        = OMAP4430_PRM_WKUP_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_ON,
         .banks            = 1,
@@ -148,7 +152,8 @@ static struct powerdomain wkup_44xx_pwrdm = {
 /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
 static struct powerdomain cpu0_44xx_pwrdm = {
         .name             = "cpu0_pwrdm",
-        .prcm_offs        = OMAP4430_PRCM_MPU_CPU0_MOD,
+        .prcm_offs        = OMAP4430_PRCM_MPU_CPU0_INST,
+        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -164,7 +169,8 @@ static struct powerdomain cpu0_44xx_pwrdm = {
 /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
 static struct powerdomain cpu1_44xx_pwrdm = {
         .name             = "cpu1_pwrdm",
-        .prcm_offs        = OMAP4430_PRCM_MPU_CPU1_MOD,
+        .prcm_offs        = OMAP4430_PRCM_MPU_CPU1_INST,
+        .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -180,7 +186,8 @@ static struct powerdomain cpu1_44xx_pwrdm = {
 /* emu_44xx_pwrdm: Emulation power domain */
 static struct powerdomain emu_44xx_pwrdm = {
         .name             = "emu_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_EMU_MOD,
+        .prcm_offs        = OMAP4430_PRM_EMU_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
@@ -195,7 +202,8 @@ static struct powerdomain emu_44xx_pwrdm = {
 /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
 static struct powerdomain mpu_44xx_pwrdm = {
         .name             = "mpu_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_MPU_MOD,
+        .prcm_offs        = OMAP4430_PRM_MPU_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
@@ -215,7 +223,8 @@ static struct powerdomain mpu_44xx_pwrdm = {
 /* ivahd_44xx_pwrdm: IVA-HD power domain */
 static struct powerdomain ivahd_44xx_pwrdm = {
         .name             = "ivahd_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_IVAHD_MOD,
+        .prcm_offs        = OMAP4430_PRM_IVAHD_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
         .pwrsts_logic_ret = PWRDM_POWER_OFF,
@@ -238,7 +247,8 @@ static struct powerdomain ivahd_44xx_pwrdm = {
 /* cam_44xx_pwrdm: Camera subsystem power domain */
 static struct powerdomain cam_44xx_pwrdm = {
         .name             = "cam_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_CAM_MOD,
+        .prcm_offs        = OMAP4430_PRM_CAM_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
@@ -254,9 +264,10 @@ static struct powerdomain cam_44xx_pwrdm = {
 /* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
 static struct powerdomain l3init_44xx_pwrdm = {
         .name             = "l3init_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_L3INIT_MOD,
+        .prcm_offs        = OMAP4430_PRM_L3INIT_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
         .pwrsts_mem_ret = {
@@ -271,9 +282,10 @@ static struct powerdomain l3init_44xx_pwrdm = {
 /* l4per_44xx_pwrdm: Target peripherals power domain */
 static struct powerdomain l4per_44xx_pwrdm = {
         .name             = "l4per_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_L4PER_MOD,
+        .prcm_offs        = OMAP4430_PRM_L4PER_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts           = PWRSTS_RET_ON,
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 2,
         .pwrsts_mem_ret = {
@@ -293,7 +305,8 @@ static struct powerdomain l4per_44xx_pwrdm = {
  */
 static struct powerdomain always_on_core_44xx_pwrdm = {
         .name             = "always_on_core_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_MOD,
+        .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_ON,
 };
@@ -301,7 +314,8 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
 /* cefuse_44xx_pwrdm: Customer efuse controller power domain */
 static struct powerdomain cefuse_44xx_pwrdm = {
         .name             = "cefuse_pwrdm",
-        .prcm_offs        = OMAP4430_PRM_CEFUSE_MOD,
+        .prcm_offs        = OMAP4430_PRM_CEFUSE_INST,
+        .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_ON,
 };
@@ -314,6 +328,28 @@ static struct powerdomain cefuse_44xx_pwrdm = {
  * stdefuse
  */
 
-#endif
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap44xx[] __initdata = {
+        &core_44xx_pwrdm,
+        &gfx_44xx_pwrdm,
+        &abe_44xx_pwrdm,
+        &dss_44xx_pwrdm,
+        &tesla_44xx_pwrdm,
+        &wkup_44xx_pwrdm,
+        &cpu0_44xx_pwrdm,
+        &cpu1_44xx_pwrdm,
+        &emu_44xx_pwrdm,
+        &mpu_44xx_pwrdm,
+        &ivahd_44xx_pwrdm,
+        &cam_44xx_pwrdm,
+        &l3init_44xx_pwrdm,
+        &l4per_44xx_pwrdm,
+        &always_on_core_44xx_pwrdm,
+        &cefuse_44xx_pwrdm,
+        NULL
+};
 
-#endif
+void __init omap44xx_powerdomains_init(void)
+{
+        pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations);
+}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index f81acee4738d..87486f559784 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -8,15 +8,12 @@
  * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
- * OMAP4 defines in this file are automatically generated from the OMAP hardware
- * databases.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-
 /* Module offsets from both CM_BASE & PRM_BASE */
 
 /*
@@ -51,75 +48,6 @@
 #define OMAP3430_NEON_MOD                               0xb00
 #define OMAP3430ES2_USBHOST_MOD                         0xc00
 
-#define BITS(n_bit)     \
-        (((1 << n_bit) - 1) | (1 << n_bit))
-
-#define BITFIELD(l_bit, u_bit)  \
-        (BITS(u_bit) & ~((BITS(l_bit)) >> 1))
-
-/* OMAP44XX specific module offsets */
-
-/* CM1 instances */
-
-#define OMAP4430_CM1_OCP_SOCKET_MOD     0x0000
-#define OMAP4430_CM1_CKGEN_MOD          0x0100
-#define OMAP4430_CM1_MPU_MOD            0x0300
-#define OMAP4430_CM1_TESLA_MOD          0x0400
-#define OMAP4430_CM1_ABE_MOD            0x0500
-#define OMAP4430_CM1_RESTORE_MOD        0x0e00
-#define OMAP4430_CM1_INSTR_MOD          0x0f00
-
-/* CM2 instances */
-
-#define OMAP4430_CM2_OCP_SOCKET_MOD     0x0000
-#define OMAP4430_CM2_CKGEN_MOD          0x0100
-#define OMAP4430_CM2_ALWAYS_ON_MOD      0x0600
-#define OMAP4430_CM2_CORE_MOD           0x0700
-#define OMAP4430_CM2_IVAHD_MOD          0x0f00
-#define OMAP4430_CM2_CAM_MOD            0x1000
-#define OMAP4430_CM2_DSS_MOD            0x1100
-#define OMAP4430_CM2_GFX_MOD            0x1200
-#define OMAP4430_CM2_L3INIT_MOD         0x1300
-#define OMAP4430_CM2_L4PER_MOD          0x1400
-#define OMAP4430_CM2_CEFUSE_MOD         0x1600
-#define OMAP4430_CM2_RESTORE_MOD        0x1e00
-#define OMAP4430_CM2_INSTR_MOD          0x1f00
-
-/* PRM instances */
-
-#define OMAP4430_PRM_OCP_SOCKET_MOD     0x0000
-#define OMAP4430_PRM_CKGEN_MOD          0x0100
-#define OMAP4430_PRM_MPU_MOD            0x0300
-#define OMAP4430_PRM_TESLA_MOD          0x0400
-#define OMAP4430_PRM_ABE_MOD            0x0500
-#define OMAP4430_PRM_ALWAYS_ON_MOD      0x0600
-#define OMAP4430_PRM_CORE_MOD           0x0700
-#define OMAP4430_PRM_IVAHD_MOD          0x0f00
-#define OMAP4430_PRM_CAM_MOD            0x1000
-#define OMAP4430_PRM_DSS_MOD            0x1100
-#define OMAP4430_PRM_GFX_MOD            0x1200
-#define OMAP4430_PRM_L3INIT_MOD         0x1300
-#define OMAP4430_PRM_L4PER_MOD          0x1400
-#define OMAP4430_PRM_CEFUSE_MOD         0x1600
-#define OMAP4430_PRM_WKUP_MOD           0x1700
-#define OMAP4430_PRM_WKUP_CM_MOD        0x1800
-#define OMAP4430_PRM_EMU_MOD            0x1900
-#define OMAP4430_PRM_EMU_CM_MOD         0x1a00
-#define OMAP4430_PRM_DEVICE_MOD         0x1b00
-#define OMAP4430_PRM_INSTR_MOD          0x1f00
-
-/* SCRM instances */
-
-#define OMAP4430_SCRM_SCRM_MOD  0x0000
-
-/* PRCM_MPU instances */
-
-#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD   0x0000
-#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD        0x0200
-#define OMAP4430_PRCM_MPU_CPU0_MOD              0x0400
-#define OMAP4430_PRCM_MPU_CPU1_MOD              0x0800
-
-
 /* 24XX register bits shared between CM & PRM registers */
 
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
@@ -461,5 +389,18 @@
 #define OMAP3430_EN_CORE_SHIFT                          0
 #define OMAP3430_EN_CORE_MASK                           (1 << 0)
 
+
+/*
+ * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
+ * submodule to exit hardreset
+ */
+#define MAX_MODULE_HARDRESET_WAIT               10000
+
+# ifndef __ASSEMBLER__
+extern void __iomem *prm_base;
+extern void __iomem *cm_base;
+extern void __iomem *cm2_base;
+# endif
+
 #endif
 
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index a51846e3a6fa..679bcd28576e 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,7 +17,8 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#include <linux/module.h>
+
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
@@ -29,105 +30,27 @@
 
 #include "clock.h"
 #include "clock2xxx.h"
-#include "cm.h"
-#include "prm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+#include "prminst44xx.h"
 #include "prm-regbits-24xx.h"
 #include "prm-regbits-44xx.h"
 #include "control.h"
 
-static void __iomem *prm_base;
-static void __iomem *cm_base;
-static void __iomem *cm2_base;
+void __iomem *prm_base;
+void __iomem *cm_base;
+void __iomem *cm2_base;
 
 #define MAX_MODULE_ENABLE_WAIT          100000
 
-struct omap3_prcm_regs {
-        u32 control_padconf_sys_nirq;
-        u32 iva2_cm_clksel1;
-        u32 iva2_cm_clksel2;
-        u32 cm_sysconfig;
-        u32 sgx_cm_clksel;
-        u32 dss_cm_clksel;
-        u32 cam_cm_clksel;
-        u32 per_cm_clksel;
-        u32 emu_cm_clksel;
-        u32 emu_cm_clkstctrl;
-        u32 pll_cm_autoidle2;
-        u32 pll_cm_clksel4;
-        u32 pll_cm_clksel5;
-        u32 pll_cm_clken2;
-        u32 cm_polctrl;
-        u32 iva2_cm_fclken;
-        u32 iva2_cm_clken_pll;
-        u32 core_cm_fclken1;
-        u32 core_cm_fclken3;
-        u32 sgx_cm_fclken;
-        u32 wkup_cm_fclken;
-        u32 dss_cm_fclken;
-        u32 cam_cm_fclken;
-        u32 per_cm_fclken;
-        u32 usbhost_cm_fclken;
-        u32 core_cm_iclken1;
-        u32 core_cm_iclken2;
-        u32 core_cm_iclken3;
-        u32 sgx_cm_iclken;
-        u32 wkup_cm_iclken;
-        u32 dss_cm_iclken;
-        u32 cam_cm_iclken;
-        u32 per_cm_iclken;
-        u32 usbhost_cm_iclken;
-        u32 iva2_cm_autiidle2;
-        u32 mpu_cm_autoidle2;
-        u32 iva2_cm_clkstctrl;
-        u32 mpu_cm_clkstctrl;
-        u32 core_cm_clkstctrl;
-        u32 sgx_cm_clkstctrl;
-        u32 dss_cm_clkstctrl;
-        u32 cam_cm_clkstctrl;
-        u32 per_cm_clkstctrl;
-        u32 neon_cm_clkstctrl;
-        u32 usbhost_cm_clkstctrl;
-        u32 core_cm_autoidle1;
-        u32 core_cm_autoidle2;
-        u32 core_cm_autoidle3;
-        u32 wkup_cm_autoidle;
-        u32 dss_cm_autoidle;
-        u32 cam_cm_autoidle;
-        u32 per_cm_autoidle;
-        u32 usbhost_cm_autoidle;
-        u32 sgx_cm_sleepdep;
-        u32 dss_cm_sleepdep;
-        u32 cam_cm_sleepdep;
-        u32 per_cm_sleepdep;
-        u32 usbhost_cm_sleepdep;
-        u32 cm_clkout_ctrl;
-        u32 prm_clkout_ctrl;
-        u32 sgx_pm_wkdep;
-        u32 dss_pm_wkdep;
-        u32 cam_pm_wkdep;
-        u32 per_pm_wkdep;
-        u32 neon_pm_wkdep;
-        u32 usbhost_pm_wkdep;
-        u32 core_pm_mpugrpsel1;
-        u32 iva2_pm_ivagrpsel1;
-        u32 core_pm_mpugrpsel3;
-        u32 core_pm_ivagrpsel3;
-        u32 wkup_pm_mpugrpsel;
-        u32 wkup_pm_ivagrpsel;
-        u32 per_pm_mpugrpsel;
-        u32 per_pm_ivagrpsel;
-        u32 wkup_pm_wken;
-};
-
-static struct omap3_prcm_regs prcm_context;
-
 u32 omap_prcm_get_reset_sources(void)
 {
         /* XXX This presumably needs modification for 34XX */
         if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
+                return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
         if (cpu_is_omap44xx())
-                return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
+                return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
 
         return 0;
 }
@@ -143,126 +66,46 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
 
                 prcm_offs = WKUP_MOD;
         } else if (cpu_is_omap34xx()) {
-                u32 l;
-
                 prcm_offs = OMAP3430_GR_MOD;
-                l = ('B' << 24) | ('M' << 16) | (cmd ? (u8)*cmd : 0);
-                /* Reserve the first word in scratchpad for communicating
-                 * with the boot ROM. A pointer to a data structure
-                 * describing the boot process can be stored there,
-                 * cf. OMAP34xx TRM, Initialization / Software Booting
-                 * Configuration. */
-                omap_writel(l, OMAP343X_SCRATCHPAD + 4);
-        } else if (cpu_is_omap44xx())
-                prcm_offs = OMAP4430_PRM_DEVICE_MOD;
-        else
+                omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
+        } else if (cpu_is_omap44xx()) {
+                omap4_prm_global_warm_sw_reset(); /* never returns */
+        } else {
                 WARN_ON(1);
+        }
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
-                                                 OMAP2_RM_RSTCTRL);
-        if (cpu_is_omap44xx())
-                prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
-                                     prcm_offs, OMAP4_RM_RSTCTRL);
-}
-
-static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
-{
-        BUG_ON(!base);
-        return __raw_readl(base + module + reg);
-}
-
-static inline void __omap_prcm_write(u32 value, void __iomem *base,
-                                                s16 module, u16 reg)
-{
-        BUG_ON(!base);
-        __raw_writel(value, base + module + reg);
-}
-
-/* Read a register in a PRM module */
-u32 prm_read_mod_reg(s16 module, u16 idx)
-{
-        return __omap_prcm_read(prm_base, module, idx);
-}
-
-/* Write into a register in a PRM module */
-void prm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-        __omap_prcm_write(val, prm_base, module, idx);
-}
-
-/* Read-modify-write a register in a PRM module. Caller must lock */
-u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
-{
-        u32 v;
-
-        v = prm_read_mod_reg(module, idx);
-        v &= ~mask;
-        v |= bits;
-        prm_write_mod_reg(v, module, idx);
-
-        return v;
-}
-
-/* Read a PRM register, AND it, and shift the result down to bit 0 */
-u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
-{
-        u32 v;
-
-        v = prm_read_mod_reg(domain, idx);
-        v &= mask;
-        v >>= __ffs(mask);
-
-        return v;
-}
-
-/* Read a PRM register, AND it, and shift the result down to bit 0 */
-u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
-{
-        u32 v;
-
-        v = __raw_readl(reg);
-        v &= mask;
-        v >>= __ffs(mask);
-
-        return v;
-}
-
-/* Read-modify-write a register in a PRM module. Caller must lock */
-u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
-{
-        u32 v;
-
-        v = __raw_readl(reg);
-        v &= ~mask;
-        v |= bits;
-        __raw_writel(v, reg);
-
-        return v;
-}
-/* Read a register in a CM module */
-u32 cm_read_mod_reg(s16 module, u16 idx)
-{
-        return __omap_prcm_read(cm_base, module, idx);
-}
-
-/* Write into a register in a CM module */
-void cm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-        __omap_prcm_write(val, cm_base, module, idx);
-}
-
-/* Read-modify-write a register in a CM module. Caller must lock */
-u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
-{
-        u32 v;
-
-        v = cm_read_mod_reg(module, idx);
-        v &= ~mask;
-        v |= bits;
-        cm_write_mod_reg(v, module, idx);
-
-        return v;
+        /*
+         * As per Errata i520, in some cases, user will not be able to
+         * access DDR memory after warm-reset.
+         * This situation occurs while the warm-reset happens during a read
+         * access to DDR memory. In that particular condition, DDR memory
+         * does not respond to a corrupted read command due to the warm
+         * reset occurrence but SDRC is waiting for read completion.
+         * SDRC is not sensitive to the warm reset, but the interconnect is
+         * reset on the fly, thus causing a misalignment between SDRC logic,
+         * interconnect logic and DDR memory state.
+         * WORKAROUND:
+         * Steps to perform before a Warm reset is trigged:
+         * 1. enable self-refresh on idle request
+         * 2. put SDRC in idle
+         * 3. wait until SDRC goes to idle
+         * 4. generate SW reset (Global SW reset)
+         *
+         * Steps to be performed after warm reset occurs (in bootloader):
+         * if HW warm reset is the source, apply below steps before any
+         * accesses to SDRAM:
+         * 1. Reset SMS and SDRC and wait till reset is complete
+         * 2. Re-initialize SMS, SDRC and memory
+         *
+         * NOTE: Above work around is required only if arch reset is implemented
+         * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
+         * the WA since it resets SDRC as well as part of cold reset.
+         */
+
+        /* XXX should be moved to some OMAP2/3 specific code */
+        omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
+                                   OMAP2_RM_RSTCTRL);
+        omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
 }
 
 /**
@@ -274,6 +117,9 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
  *
  * Returns 1 if the module indicated readiness in time, or 0 if it
  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
+ *
+ * XXX This function is deprecated.  It should be removed once the
+ * hwmod conversion is complete.
  */
 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
                                 const char *name)
@@ -316,303 +162,3 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
                 WARN_ON(!cm2_base);
         }
 }
-
-#ifdef CONFIG_ARCH_OMAP3
-void omap3_prcm_save_context(void)
-{
-        prcm_context.control_padconf_sys_nirq =
-                         omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
-        prcm_context.iva2_cm_clksel1 =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
-        prcm_context.iva2_cm_clksel2 =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
-        prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
-        prcm_context.sgx_cm_clksel =
-                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
-        prcm_context.dss_cm_clksel =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
-        prcm_context.cam_cm_clksel =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
-        prcm_context.per_cm_clksel =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
-        prcm_context.emu_cm_clksel =
-                         cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
-        prcm_context.emu_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.pll_cm_autoidle2 =
-                         cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
-        prcm_context.pll_cm_clksel4 =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
-        prcm_context.pll_cm_clksel5 =
-                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
-        prcm_context.pll_cm_clken2 =
-                        cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
-        prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
-        prcm_context.iva2_cm_fclken =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
-        prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
-                        OMAP3430_CM_CLKEN_PLL);
-        prcm_context.core_cm_fclken1 =
-                         cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
-        prcm_context.core_cm_fclken3 =
-                         cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
-        prcm_context.sgx_cm_fclken =
-                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
-        prcm_context.wkup_cm_fclken =
-                         cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
-        prcm_context.dss_cm_fclken =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
-        prcm_context.cam_cm_fclken =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
-        prcm_context.per_cm_fclken =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
-        prcm_context.usbhost_cm_fclken =
-                         cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
-        prcm_context.core_cm_iclken1 =
-                         cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
-        prcm_context.core_cm_iclken2 =
-                         cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
-        prcm_context.core_cm_iclken3 =
-                         cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
-        prcm_context.sgx_cm_iclken =
-                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
-        prcm_context.wkup_cm_iclken =
-                         cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
-        prcm_context.dss_cm_iclken =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
-        prcm_context.cam_cm_iclken =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
-        prcm_context.per_cm_iclken =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
-        prcm_context.usbhost_cm_iclken =
-                         cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
-        prcm_context.iva2_cm_autiidle2 =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-        prcm_context.mpu_cm_autoidle2 =
-                         cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
-        prcm_context.iva2_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.mpu_cm_clkstctrl =
-                         cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.core_cm_clkstctrl =
-                         cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.sgx_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
-                                                OMAP2_CM_CLKSTCTRL);
-        prcm_context.dss_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.cam_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.per_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.neon_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
-        prcm_context.usbhost_cm_clkstctrl =
-                         cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
-                                                OMAP2_CM_CLKSTCTRL);
-        prcm_context.core_cm_autoidle1 =
-                         cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
-        prcm_context.core_cm_autoidle2 =
-                         cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
-        prcm_context.core_cm_autoidle3 =
-                         cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
-        prcm_context.wkup_cm_autoidle =
-                         cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
-        prcm_context.dss_cm_autoidle =
-                         cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
-        prcm_context.cam_cm_autoidle =
-                         cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
-        prcm_context.per_cm_autoidle =
-                         cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
-        prcm_context.usbhost_cm_autoidle =
-                         cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
-        prcm_context.sgx_cm_sleepdep =
-                 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
-        prcm_context.dss_cm_sleepdep =
-                 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
-        prcm_context.cam_cm_sleepdep =
-                 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
-        prcm_context.per_cm_sleepdep =
-                 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
-        prcm_context.usbhost_cm_sleepdep =
-                 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
-        prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
-                 OMAP3_CM_CLKOUT_CTRL_OFFSET);
-        prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
-                OMAP3_PRM_CLKOUT_CTRL_OFFSET);
-        prcm_context.sgx_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
-        prcm_context.dss_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
-        prcm_context.cam_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
-        prcm_context.per_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
-        prcm_context.neon_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
-        prcm_context.usbhost_pm_wkdep =
-                 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
-        prcm_context.core_pm_mpugrpsel1 =
-                 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
-        prcm_context.iva2_pm_ivagrpsel1 =
-                 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
-        prcm_context.core_pm_mpugrpsel3 =
-                 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
-        prcm_context.core_pm_ivagrpsel3 =
-                 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
-        prcm_context.wkup_pm_mpugrpsel =
-                 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
-        prcm_context.wkup_pm_ivagrpsel =
-                 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
-        prcm_context.per_pm_mpugrpsel =
-                 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
-        prcm_context.per_pm_ivagrpsel =
-                 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
-        prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
-        return;
-}
-
-void omap3_prcm_restore_context(void)
-{
-        omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
-                                         OMAP343X_CONTROL_PADCONF_SYSNIRQ);
-        cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
-                                         CM_CLKSEL1);
-        cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
-                                         CM_CLKSEL2);
-        __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
-        cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
-                                         CM_CLKSEL);
-        cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
-                                         CM_CLKSEL);
-        cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
-                                         CM_CLKSEL);
-        cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
-                                         CM_CLKSEL);
-        cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
-                                         CM_CLKSEL1);
-        cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
-                                         OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
-                                         CM_AUTOIDLE2);
-        cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
-                                        OMAP3430ES2_CM_CLKSEL4);
-        cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
-                                         OMAP3430ES2_CM_CLKSEL5);
-        cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
-                                        OMAP3430ES2_CM_CLKEN2);
-        __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
-        cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
-                                         CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
-                                        OMAP3430_CM_CLKEN_PLL);
-        cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
-        cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
-                                         OMAP3430ES2_CM_FCLKEN3);
-        cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
-                                         CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
-                                         CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
-                                         CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
-                                         CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
-                                         OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
-        cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
-        cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
-        cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
-        cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
-                                        CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
-                                        CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
-                                        CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
-                                        CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
-                                        OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
-        cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
-                                        CM_AUTOIDLE2);
-        cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
-        cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
-                                        OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
-                                OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
-        cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
-                                        CM_AUTOIDLE1);
-        cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
-                                        CM_AUTOIDLE2);
-        cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
-                                        CM_AUTOIDLE3);
-        cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
-        cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
-                                        CM_AUTOIDLE);
-        cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
-                                        CM_AUTOIDLE);
-        cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
-                                        CM_AUTOIDLE);
-        cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
-                                        OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
-        cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
-                                        OMAP3430_CM_SLEEPDEP);
-        cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
-                                        OMAP3430_CM_SLEEPDEP);
-        cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
-                                        OMAP3430_CM_SLEEPDEP);
-        cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
-                                        OMAP3430_CM_SLEEPDEP);
-        cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
-                                OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
-        cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
-                                        OMAP3_CM_CLKOUT_CTRL_OFFSET);
-        prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
-                                        OMAP3_PRM_CLKOUT_CTRL_OFFSET);
-        prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
-                                        PM_WKDEP);
-        prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
-                                        PM_WKDEP);
-        prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
-                                        PM_WKDEP);
-        prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
-                                        PM_WKDEP);
-        prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
-                                        PM_WKDEP);
-        prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
-                                        OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
-        prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
-                                        OMAP3430_PM_MPUGRPSEL1);
-        prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
-                                        OMAP3430_PM_IVAGRPSEL1);
-        prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
-                                        OMAP3430ES2_PM_MPUGRPSEL3);
-        prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
-                                        OMAP3430ES2_PM_IVAGRPSEL3);
-        prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
-                                        OMAP3430_PM_MPUGRPSEL);
-        prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
-                                        OMAP3430_PM_IVAGRPSEL);
-        prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
-                                        OMAP3430_PM_MPUGRPSEL);
-        prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
-                                         OMAP3430_PM_IVAGRPSEL);
-        prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
-        return;
-}
-#endif
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
new file mode 100644
index 000000000000..7334ffb9d2c1
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -0,0 +1,42 @@
+/*
+ * OMAP4 PRCM definitions
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains macros and functions that are common to all of
+ * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
+ * PRCM_MPU, SCRM
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM44XX_H
+
+/*
+ * OMAP4 PRCM partition IDs
+ *
+ * The numbers and order are arbitrary, but 0 is reserved for the
+ * 'invalid' partition in case someone forgets to add a
+ * .prcm_partition field.
+ */
+#define OMAP4430_INVALID_PRCM_PARTITION         0
+#define OMAP4430_PRM_PARTITION                  1
+#define OMAP4430_CM1_PARTITION                  2
+#define OMAP4430_CM2_PARTITION                  3
+#define OMAP4430_SCRM_PARTITION                 4
+#define OMAP4430_PRCM_MPU_PARTITION             5
+
+/*
+ * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
+ * IDs, plus one
+ */
+#define OMAP4_MAX_PRCM_PARTITIONS               6
+
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
new file mode 100644
index 000000000000..171fe171a749
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -0,0 +1,45 @@
+/*
+ * OMAP4 PRCM_MPU module functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "prcm_mpu44xx.h"
+#include "cm-regbits-44xx.h"
+
+/* PRCM_MPU low-level functions */
+
+u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
+{
+        return __raw_readl(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
+}
+
+void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
+{
+        __raw_writel(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
+}
+
+u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
+{
+        u32 v;
+
+        v = omap4_prcm_mpu_read_inst_reg(inst, reg);
+        v &= ~mask;
+        v |= bits;
+        omap4_prcm_mpu_write_inst_reg(v, inst, reg);
+
+        return v;
+}
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
new file mode 100644
index 000000000000..729a644ce852
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -0,0 +1,104 @@
+/*
+ * OMAP44xx PRCM MPU instance offset macros
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ *     or "OMAP4430".
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
+
+#define OMAP4430_PRCM_MPU_BASE                  0x48243000
+
+#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)                            \
+        OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
+
+/* PRCM_MPU instances */
+
+#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST  0x0000
+#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST       0x0200
+#define OMAP4430_PRCM_MPU_CPU0_INST             0x0400
+#define OMAP4430_PRCM_MPU_CPU1_INST             0x0800
+
+/* PRCM_MPU clockdomain register offsets (from instance start) */
+#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS       0x0000
+#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS       0x0000
+
+
+/*
+ * PRCM_MPU
+ *
+ * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
+ * point of view the PRCM_MPU is a single entity. It shares the same
+ * programming model as the global PRCM and thus can be assimilate as two new
+ * MOD inside the PRCM
+ */
+
+/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
+#define OMAP4_REVISION_PRCM_OFFSET                      0x0000
+#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
+
+/* PRCM_MPU.DEVICE_PRM register offsets */
+#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET                 0x0000
+#define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
+#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET           0x0004
+#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT               OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
+
+/* PRCM_MPU.CPU0 register offsets */
+#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET                  0x0000
+#define OMAP4430_PM_CPU0_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
+#define OMAP4_PM_CPU0_PWRSTST_OFFSET                    0x0004
+#define OMAP4430_PM_CPU0_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
+#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET               0x0008
+#define OMAP4430_RM_CPU0_CPU0_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
+#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET               0x000c
+#define OMAP4430_RM_CPU0_CPU0_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
+#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET                 0x0010
+#define OMAP4430_RM_CPU0_CPU0_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
+#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET               0x0014
+#define OMAP4430_CM_CPU0_CPU0_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
+#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET                  0x0018
+#define OMAP4430_CM_CPU0_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
+
+/* PRCM_MPU.CPU1 register offsets */
+#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET                  0x0000
+#define OMAP4430_PM_CPU1_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
+#define OMAP4_PM_CPU1_PWRSTST_OFFSET                    0x0004
+#define OMAP4430_PM_CPU1_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
+#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET               0x0008
+#define OMAP4430_RM_CPU1_CPU1_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
+#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET               0x000c
+#define OMAP4430_RM_CPU1_CPU1_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
+#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET                 0x0010
+#define OMAP4430_RM_CPU1_CPU1_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
+#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET               0x0014
+#define OMAP4430_CM_CPU1_CPU1_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
+#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET                  0x0018
+#define OMAP4430_CM_CPU1_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
+
+/* Function prototypes */
+# ifndef __ASSEMBLER__
+extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
+                                            s16 idx);
+# endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 0b188ffa710e..6ac966103f34 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -14,7 +14,7 @@
  * published by the Free Software Foundation.
  */
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 
 /* Bits shared between registers */
 
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 9e63cb743a97..64c087af6a8b 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -1,6 +1,3 @@
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
-#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
-
 /*
  * OMAP3430 Power/Reset Management register bits
  *
@@ -13,8 +10,11 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
+
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 
 /* Shared register bits */
 
@@ -101,8 +101,11 @@
 #define OMAP3430_GRPSEL_MCSPI3_MASK                     (1 << 20)
 #define OMAP3430_GRPSEL_MCSPI2_MASK                     (1 << 19)
 #define OMAP3430_GRPSEL_MCSPI1_MASK                     (1 << 18)
+#define OMAP3430_GRPSEL_I2C3_SHIFT                      17
 #define OMAP3430_GRPSEL_I2C3_MASK                       (1 << 17)
+#define OMAP3430_GRPSEL_I2C2_SHIFT                      16
 #define OMAP3430_GRPSEL_I2C2_MASK                       (1 << 16)
+#define OMAP3430_GRPSEL_I2C1_SHIFT                      15
 #define OMAP3430_GRPSEL_I2C1_MASK                       (1 << 15)
 #define OMAP3430_GRPSEL_UART2_MASK                      (1 << 14)
 #define OMAP3430_GRPSEL_UART1_MASK                      (1 << 13)
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 25b19b610177..6d2776f6fc08 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -22,8 +22,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
 
-#include "prm.h"
-
 
 /*
  * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 7be040b2fdab..39d562169d18 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -1,321 +1,20 @@
-#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
-#define __ARCH_ARM_MACH_OMAP2_PRM_H
-
 /*
- * OMAP2/3 Power/Reset Management (PRM) register definitions
+ * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
  *
  * Copyright (C) 2007-2009 Texas Instruments, Inc.
  * Copyright (C) 2010 Nokia Corporation
  *
- * Written by Paul Walmsley
+ * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_H
 
 #include "prcm-common.h"
 
-#define OMAP2420_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
-#define OMAP2430_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
-#define OMAP34XX_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
-#define OMAP44XX_PRM_REGADDR(module, reg)                               \
-                OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))
-#define OMAP44XX_PRCM_MPU_REGADDR(module, reg)                          \
-                OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
-
-#include "prm44xx.h"
-
-/*
- * Architecture-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * PRCM_* on 24xx, and PRM_* on 34xx.  (The exceptions are the
- * IRQSTATUS and IRQENABLE bits.)
- *
- */
-
-#define OMAP2_PRCM_REVISION_OFFSET      0x0000
-#define OMAP2420_PRCM_REVISION          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2_PRCM_SYSCONFIG_OFFSET     0x0010
-#define OMAP2420_PRCM_SYSCONFIG         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
-
-#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
-#define OMAP2420_PRCM_IRQSTATUS_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
-#define OMAP2420_PRCM_IRQENABLE_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
-
-#define OMAP2_PRCM_VOLTCTRL_OFFSET      0x0050
-#define OMAP2420_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2_PRCM_VOLTST_OFFSET        0x0054
-#define OMAP2420_PRCM_VOLTST            OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
-#define OMAP2420_PRCM_CLKSRC_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
-#define OMAP2420_PRCM_CLKOUT_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
-#define OMAP2420_PRCM_CLKEMUL_CTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
-#define OMAP2420_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
-#define OMAP2420_PRCM_CLKCFG_STATUS     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2_PRCM_VOLTSETUP_OFFSET     0x0090
-#define OMAP2420_PRCM_VOLTSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2_PRCM_CLKSSETUP_OFFSET     0x0094
-#define OMAP2420_PRCM_CLKSSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2_PRCM_POLCTRL_OFFSET       0x0098
-#define OMAP2420_PRCM_POLCTRL           OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
-
-#define OMAP2430_PRCM_REVISION          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP2430_PRCM_SYSCONFIG         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
-
-#define OMAP2430_PRCM_IRQSTATUS_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP2430_PRCM_IRQENABLE_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
-
-#define OMAP2430_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
-#define OMAP2430_PRCM_VOLTST            OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
-#define OMAP2430_PRCM_CLKSRC_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
-#define OMAP2430_PRCM_CLKOUT_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
-#define OMAP2430_PRCM_CLKEMUL_CTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
-#define OMAP2430_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
-#define OMAP2430_PRCM_CLKCFG_STATUS     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
-#define OMAP2430_PRCM_VOLTSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
-#define OMAP2430_PRCM_CLKSSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
-#define OMAP2430_PRCM_POLCTRL           OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
-
-#define OMAP3_PRM_REVISION_OFFSET       0x0004
-#define OMAP3430_PRM_REVISION           OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
-#define OMAP3_PRM_SYSCONFIG_OFFSET      0x0014
-#define OMAP3430_PRM_SYSCONFIG          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
-
-#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
-#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
-#define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
-#define OMAP3430_PRM_IRQENABLE_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
-
-
-#define OMAP3_PRM_VC_SMPS_SA_OFFSET     0x0020
-#define OMAP3430_PRM_VC_SMPS_SA         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
-#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
-#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
-#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
-#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
-#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
-#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
-#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
-#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
-#define OMAP3_PRM_VC_CH_CONF_OFFSET     0x0034
-#define OMAP3430_PRM_VC_CH_CONF         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
-#define OMAP3_PRM_VC_I2C_CFG_OFFSET     0x0038
-#define OMAP3430_PRM_VC_I2C_CFG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
-#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
-#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
-#define OMAP3_PRM_RSTCTRL_OFFSET        0x0050
-#define OMAP3430_PRM_RSTCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
-#define OMAP3_PRM_RSTTIME_OFFSET        0x0054
-#define OMAP3430_PRM_RSTTIME            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
-#define OMAP3_PRM_RSTST_OFFSET  0x0058
-#define OMAP3430_PRM_RSTST              OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
-#define OMAP3_PRM_VOLTCTRL_OFFSET       0x0060
-#define OMAP3430_PRM_VOLTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
-#define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
-#define OMAP3430_PRM_SRAM_PCHARGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
-#define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
-#define OMAP3430_PRM_CLKSRC_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
-#define OMAP3_PRM_VOLTSETUP1_OFFSET     0x0090
-#define OMAP3430_PRM_VOLTSETUP1         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
-#define OMAP3_PRM_VOLTOFFSET_OFFSET     0x0094
-#define OMAP3430_PRM_VOLTOFFSET         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
-#define OMAP3_PRM_CLKSETUP_OFFSET       0x0098
-#define OMAP3430_PRM_CLKSETUP           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
-#define OMAP3_PRM_POLCTRL_OFFSET        0x009c
-#define OMAP3430_PRM_POLCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
-#define OMAP3_PRM_VOLTSETUP2_OFFSET     0x00a0
-#define OMAP3430_PRM_VOLTSETUP2         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
-#define OMAP3_PRM_VP1_CONFIG_OFFSET     0x00b0
-#define OMAP3430_PRM_VP1_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
-#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
-#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
-#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
-#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
-#define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
-#define OMAP3430_PRM_VP1_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
-#define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
-#define OMAP3430_PRM_VP1_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
-#define OMAP3_PRM_VP1_STATUS_OFFSET     0x00c4
-#define OMAP3430_PRM_VP1_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
-#define OMAP3_PRM_VP2_CONFIG_OFFSET     0x00d0
-#define OMAP3430_PRM_VP2_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
-#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
-#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
-#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
-#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
-#define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
-#define OMAP3430_PRM_VP2_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
-#define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
-#define OMAP3430_PRM_VP2_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
-#define OMAP3_PRM_VP2_STATUS_OFFSET     0x00e4
-#define OMAP3430_PRM_VP2_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
-
-#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
-#define OMAP3430_PRM_CLKSEL             OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
-#define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
-#define OMAP3430_PRM_CLKOUT_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
-
-/*
- * Module specific PRM registers from PRM_BASE + domain offset
- *
- * Use prm_{read,write}_mod_reg() with these registers.
- *
- * With a few exceptions, these are the register names beginning with
- * {PM,RM}_* on both architectures.  (The exceptions are the IRQSTATUS
- * and IRQENABLE bits.)
- *
- */
-
-/* Registers appearing on both 24xx and 34xx */
-
-#define OMAP2_RM_RSTCTRL                                0x0050
-#define OMAP2_RM_RSTTIME                                0x0054
-#define OMAP2_RM_RSTST                                  0x0058
-#define OMAP2_PM_PWSTCTRL                               0x00e0
-#define OMAP2_PM_PWSTST                                 0x00e4
-
-#define PM_WKEN                                         0x00a0
-#define PM_WKEN1                                        PM_WKEN
-#define PM_WKST                                         0x00b0
-#define PM_WKST1                                        PM_WKST
-#define PM_WKDEP                                        0x00c8
-#define PM_EVGENCTRL                                    0x00d4
-#define PM_EVGENONTIM                                   0x00d8
-#define PM_EVGENOFFTIM                                  0x00dc
-
-/* Omap2 specific registers */
-#define OMAP24XX_PM_WKEN2                               0x00a4
-#define OMAP24XX_PM_WKST2                               0x00b4
-
-#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
-#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
-#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
-#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
-
-/* Omap3 specific registers */
-#define OMAP3430ES2_PM_WKEN3                            0x00f0
-#define OMAP3430ES2_PM_WKST3                            0x00b8
-
-#define OMAP3430_PM_MPUGRPSEL                           0x00a4
-#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
-#define OMAP3430ES2_PM_MPUGRPSEL3                       0x00f8
-
-#define OMAP3430_PM_IVAGRPSEL                           0x00a8
-#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
-#define OMAP3430ES2_PM_IVAGRPSEL3                       0x00f4
-
-#define OMAP3430_PM_PREPWSTST                           0x00e8
-
-#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
-#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
-
-/* Omap4 specific registers */
-#define OMAP4_RM_RSTCTRL                                0x0000
-#define OMAP4_RM_RSTTIME                                0x0004
-#define OMAP4_RM_RSTST                                  0x0008
-#define OMAP4_PM_PWSTCTRL                               0x0000
-#define OMAP4_PM_PWSTST                                 0x0004
-
-
-#ifndef __ASSEMBLER__
-
-/* Power/reset management domain register get/set */
-extern u32 prm_read_mod_reg(s16 module, u16 idx);
-extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
-extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
-
-/* Read-modify-write bits in a PRM register (by domain) */
-static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return prm_rmw_mod_reg_bits(bits, bits, module, idx);
-}
-
-static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
-}
-
-/* These omap2_ PRM functions apply to both OMAP2 and 3 */
-int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
-int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
-int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
-
-int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
-int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
-int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
-
-#endif
-
-/*
- * Bits common to specific registers
- *
- * The 3430 register and bit names are generally used,
- * since they tend to make more sense
- */
-
-/* PM_EVGENONTIM_MPU */
-/* Named PM_EVEGENONTIM_MPU on the 24XX */
-#define OMAP_ONTIMEVAL_SHIFT                            0
-#define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
-
-/* PM_EVGENOFFTIM_MPU */
-/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
-#define OMAP_OFFTIMEVAL_SHIFT                           0
-#define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
-
-/* PRM_CLKSETUP and PRCM_VOLTSETUP */
-/* Named PRCM_CLKSSETUP on the 24XX */
-#define OMAP_SETUP_TIME_SHIFT                           0
-#define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
-
-/* PRM_CLKSRC_CTRL */
-/* Named PRCM_CLKSRC_CTRL on the 24XX */
-#define OMAP_SYSCLKDIV_SHIFT                            6
-#define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
-#define OMAP_AUTOEXTCLKMODE_SHIFT                       3
-#define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
-#define OMAP_SYSCLKSEL_SHIFT                            0
-#define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
-
-/* PM_EVGENCTRL_MPU */
-#define OMAP_OFFLOADMODE_SHIFT                          3
-#define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
-#define OMAP_ONLOADMODE_SHIFT                           1
-#define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
-#define OMAP_ENABLE_MASK                                (1 << 0)
-
-/* PRM_RSTTIME */
-/* Named RM_RSTTIME_WKUP on the 24xx */
-#define OMAP_RSTTIME2_SHIFT                             8
-#define OMAP_RSTTIME2_MASK                              (0x1f << 8)
-#define OMAP_RSTTIME1_SHIFT                             0
-#define OMAP_RSTTIME1_MASK                              (0xff << 0)
-
-/* PRM_RSTCTRL */
-/* Named RM_RSTCTRL_WKUP on the 24xx */
-/* 2420 calls RST_DPLL3 'RST_DPLL' */
-#define OMAP_RST_DPLL3_MASK                             (1 << 2)
-#define OMAP_RST_GS_MASK                                (1 << 1)
-
-
-/*
- * Bits common to module-shared registers
- *
- * Not all registers of a particular type support all of these bits -
- * check TRM if you are unsure
- */
-
 /*
  * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
  *
@@ -341,59 +40,6 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
 #define OMAP_POWERSTATEST_MASK                          (0x3 << 0)
 
 /*
- * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
- *       called 'COREWKUP_RST'
- *
- * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
- *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
- */
-#define OMAP_COREDOMAINWKUP_RST_MASK                    (1 << 3)
-
-/*
- * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
- *
- * 2430: RM_RSTST_MDM
- *
- * 3430: RM_RSTST_CORE, RM_RSTST_EMU
- */
-#define OMAP_DOMAINWKUP_RST_MASK                        (1 << 2)
-
-/*
- * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
- *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
- *
- * 2430: RM_RSTST_MDM
- *
- * 3430: RM_RSTST_CORE, RM_RSTST_EMU
- */
-#define OMAP_GLOBALWARM_RST_MASK                        (1 << 1)
-#define OMAP_GLOBALCOLD_RST_MASK                        (1 << 0)
-
-/*
- * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
- *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
- *
- * 2430: PM_WKDEP_MDM
- *
- * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
- *       PM_WKDEP_PER
- */
-#define OMAP_EN_WKUP_SHIFT                              4
-#define OMAP_EN_WKUP_MASK                               (1 << 4)
-
-/*
- * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
- *       PM_PWSTCTRL_DSP
- *
- * 2430: PM_PWSTCTRL_MDM
- *
- * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
- *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
- *       PM_PWSTCTRL_NEON
- */
-#define OMAP_LOGICRETSTATE_MASK                         (1 << 2)
-
-/*
  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
  *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
  *
@@ -407,11 +53,4 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
 #define OMAP_POWERSTATE_MASK                            (0x3 << 0)
 
 
-/*
- * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
- * submodule to exit hardreset
- */
-#define MAX_MODULE_HARDRESET_WAIT               10000
-
-
 #endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 421771eee450..ec0362574b5e 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -12,18 +12,65 @@
  */
 
 #include <linux/kernel.h>
-#include <linux/delay.h>
 #include <linux/errno.h>
 #include <linux/err.h>
+#include <linux/io.h>
 
 #include <plat/common.h>
 #include <plat/cpu.h>
 #include <plat/prcm.h>
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 #include "prm-regbits-34xx.h"
 
+u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
+{
+        return __raw_readl(prm_base + module + idx);
+}
+
+void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        __raw_writel(val, prm_base + module + idx);
+}
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
+{
+        u32 v;
+
+        v = omap2_prm_read_mod_reg(module, idx);
+        v &= ~mask;
+        v |= bits;
+        omap2_prm_write_mod_reg(v, module, idx);
+
+        return v;
+}
+
+/* Read a PRM register, AND it, and shift the result down to bit 0 */
+u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+        u32 v;
+
+        v = omap2_prm_read_mod_reg(domain, idx);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
+}
+
+u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
+}
+
+
 /**
  * omap2_prm_is_hardreset_asserted - read the HW reset line state of
  * submodules contained in the hwmod module
@@ -39,7 +86,7 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
         if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
                 return -EINVAL;
 
-        return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
+        return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
                                        (1 << shift));
 }
 
@@ -63,7 +110,7 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
                 return -EINVAL;
 
         mask = 1 << shift;
-        prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
+        omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
 
         return 0;
 }
@@ -93,18 +140,17 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift)
         mask = 1 << shift;
 
         /* Check the current status to avoid de-asserting the line twice */
-        if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0)
+        if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0)
                 return -EEXIST;
 
         /* Clear the reset status by writing 1 to the status bit */
-        prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST);
+        omap2_prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST);
         /* de-assert the reset control line */
-        prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL);
+        omap2_prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL);
         /* wait the status to be set */
-        omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
+        omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
                                                   mask),
                           MAX_MODULE_HARDRESET_WAIT, c);
 
         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 }
-
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
new file mode 100644
index 000000000000..53d44f6e3736
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -0,0 +1,367 @@
+/*
+ * OMAP2/3 Power/Reset Management (PRM) register definitions
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * The PRM hardware modules on the OMAP2/3 are quite similar to each
+ * other.  The PRM on OMAP4 has a new register layout, and is handled
+ * in a separate file.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+
+#define OMAP2420_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
+#define OMAP2430_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
+#define OMAP34XX_PRM_REGADDR(module, reg)                               \
+                OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
+
+
+/*
+ * OMAP2-specific global PRM registers
+ * Use __raw_{read,write}l() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ * bits.)
+ *
+ */
+
+#define OMAP2_PRCM_REVISION_OFFSET      0x0000
+#define OMAP2420_PRCM_REVISION          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2_PRCM_SYSCONFIG_OFFSET     0x0010
+#define OMAP2420_PRCM_SYSCONFIG         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
+#define OMAP2420_PRCM_IRQSTATUS_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
+#define OMAP2420_PRCM_IRQENABLE_MPU     OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP2_PRCM_VOLTCTRL_OFFSET      0x0050
+#define OMAP2420_PRCM_VOLTCTRL          OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2_PRCM_VOLTST_OFFSET        0x0054
+#define OMAP2420_PRCM_VOLTST            OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET   0x0060
+#define OMAP2420_PRCM_CLKSRC_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET   0x0070
+#define OMAP2420_PRCM_CLKOUT_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET  0x0078
+#define OMAP2420_PRCM_CLKEMUL_CTRL      OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET   0x0080
+#define OMAP2420_PRCM_CLKCFG_CTRL       OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
+#define OMAP2420_PRCM_CLKCFG_STATUS     OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2_PRCM_VOLTSETUP_OFFSET     0x0090
+#define OMAP2420_PRCM_VOLTSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2_PRCM_CLKSSETUP_OFFSET     0x0094
+#define OMAP2420_PRCM_CLKSSETUP         OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP2_PRCM_POLCTRL_OFFSET       0x0098
+#define OMAP2420_PRCM_POLCTRL           OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
+
+#define OMAP2430_PRCM_REVISION          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP2430_PRCM_SYSCONFIG         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
+
+#define OMAP2430_PRCM_IRQSTATUS_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP2430_PRCM_IRQENABLE_MPU     OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
+
+#define OMAP2430_PRCM_VOLTCTRL          OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
+#define OMAP2430_PRCM_VOLTST            OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
+#define OMAP2430_PRCM_CLKSRC_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
+#define OMAP2430_PRCM_CLKOUT_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
+#define OMAP2430_PRCM_CLKEMUL_CTRL      OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
+#define OMAP2430_PRCM_CLKCFG_CTRL       OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
+#define OMAP2430_PRCM_CLKCFG_STATUS     OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
+#define OMAP2430_PRCM_VOLTSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
+#define OMAP2430_PRCM_CLKSSETUP         OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
+#define OMAP2430_PRCM_POLCTRL           OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
+
+/*
+ * OMAP3-specific global PRM registers
+ * Use __raw_{read,write}l() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
+ * bits.)
+ */
+
+#define OMAP3_PRM_REVISION_OFFSET       0x0004
+#define OMAP3430_PRM_REVISION           OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
+#define OMAP3_PRM_SYSCONFIG_OFFSET      0x0014
+#define OMAP3430_PRM_SYSCONFIG          OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
+
+#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET  0x0018
+#define OMAP3430_PRM_IRQSTATUS_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
+#define OMAP3_PRM_IRQENABLE_MPU_OFFSET  0x001c
+#define OMAP3430_PRM_IRQENABLE_MPU      OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
+
+
+#define OMAP3_PRM_VC_SMPS_SA_OFFSET     0x0020
+#define OMAP3430_PRM_VC_SMPS_SA         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
+#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
+#define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
+#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
+#define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
+#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET   0x002c
+#define OMAP3430_PRM_VC_CMD_VAL_0       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
+#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET   0x0030
+#define OMAP3430_PRM_VC_CMD_VAL_1       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
+#define OMAP3_PRM_VC_CH_CONF_OFFSET     0x0034
+#define OMAP3430_PRM_VC_CH_CONF         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
+#define OMAP3_PRM_VC_I2C_CFG_OFFSET     0x0038
+#define OMAP3430_PRM_VC_I2C_CFG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
+#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET  0x003c
+#define OMAP3430_PRM_VC_BYPASS_VAL      OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
+#define OMAP3_PRM_RSTCTRL_OFFSET        0x0050
+#define OMAP3430_PRM_RSTCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
+#define OMAP3_PRM_RSTTIME_OFFSET        0x0054
+#define OMAP3430_PRM_RSTTIME            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
+#define OMAP3_PRM_RSTST_OFFSET  0x0058
+#define OMAP3430_PRM_RSTST              OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
+#define OMAP3_PRM_VOLTCTRL_OFFSET       0x0060
+#define OMAP3430_PRM_VOLTCTRL           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
+#define OMAP3_PRM_SRAM_PCHARGE_OFFSET   0x0064
+#define OMAP3430_PRM_SRAM_PCHARGE       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
+#define OMAP3_PRM_CLKSRC_CTRL_OFFSET    0x0070
+#define OMAP3430_PRM_CLKSRC_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
+#define OMAP3_PRM_VOLTSETUP1_OFFSET     0x0090
+#define OMAP3430_PRM_VOLTSETUP1         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
+#define OMAP3_PRM_VOLTOFFSET_OFFSET     0x0094
+#define OMAP3430_PRM_VOLTOFFSET         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
+#define OMAP3_PRM_CLKSETUP_OFFSET       0x0098
+#define OMAP3430_PRM_CLKSETUP           OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
+#define OMAP3_PRM_POLCTRL_OFFSET        0x009c
+#define OMAP3430_PRM_POLCTRL            OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
+#define OMAP3_PRM_VOLTSETUP2_OFFSET     0x00a0
+#define OMAP3430_PRM_VOLTSETUP2         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
+#define OMAP3_PRM_VP1_CONFIG_OFFSET     0x00b0
+#define OMAP3430_PRM_VP1_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
+#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET   0x00b4
+#define OMAP3430_PRM_VP1_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
+#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET   0x00b8
+#define OMAP3430_PRM_VP1_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
+#define OMAP3_PRM_VP1_VLIMITTO_OFFSET   0x00bc
+#define OMAP3430_PRM_VP1_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
+#define OMAP3_PRM_VP1_VOLTAGE_OFFSET    0x00c0
+#define OMAP3430_PRM_VP1_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
+#define OMAP3_PRM_VP1_STATUS_OFFSET     0x00c4
+#define OMAP3430_PRM_VP1_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
+#define OMAP3_PRM_VP2_CONFIG_OFFSET     0x00d0
+#define OMAP3430_PRM_VP2_CONFIG         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
+#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET   0x00d4
+#define OMAP3430_PRM_VP2_VSTEPMIN       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
+#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET   0x00d8
+#define OMAP3430_PRM_VP2_VSTEPMAX       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
+#define OMAP3_PRM_VP2_VLIMITTO_OFFSET   0x00dc
+#define OMAP3430_PRM_VP2_VLIMITTO       OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
+#define OMAP3_PRM_VP2_VOLTAGE_OFFSET    0x00e0
+#define OMAP3430_PRM_VP2_VOLTAGE        OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
+#define OMAP3_PRM_VP2_STATUS_OFFSET     0x00e4
+#define OMAP3430_PRM_VP2_STATUS         OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
+
+#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
+#define OMAP3430_PRM_CLKSEL             OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
+#define OMAP3_PRM_CLKOUT_CTRL_OFFSET    0x0070
+#define OMAP3430_PRM_CLKOUT_CTRL        OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+
+/*
+ * Module specific PRM register offsets from PRM_BASE + domain offset
+ *
+ * Use prm_{read,write}_mod_reg() with these registers.
+ *
+ * With a few exceptions, these are the register names beginning with
+ * {PM,RM}_* on both OMAP2/3 SoC families..  (The exceptions are the
+ * IRQSTATUS and IRQENABLE bits.)
+ */
+
+/* Register offsets appearing on both OMAP2 and OMAP3 */
+
+#define OMAP2_RM_RSTCTRL                                0x0050
+#define OMAP2_RM_RSTTIME                                0x0054
+#define OMAP2_RM_RSTST                                  0x0058
+#define OMAP2_PM_PWSTCTRL                               0x00e0
+#define OMAP2_PM_PWSTST                                 0x00e4
+
+#define PM_WKEN                                         0x00a0
+#define PM_WKEN1                                        PM_WKEN
+#define PM_WKST                                         0x00b0
+#define PM_WKST1                                        PM_WKST
+#define PM_WKDEP                                        0x00c8
+#define PM_EVGENCTRL                                    0x00d4
+#define PM_EVGENONTIM                                   0x00d8
+#define PM_EVGENOFFTIM                                  0x00dc
+
+/* OMAP2xxx specific register offsets */
+#define OMAP24XX_PM_WKEN2                               0x00a4
+#define OMAP24XX_PM_WKST2                               0x00b4
+
+#define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
+#define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
+#define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
+#define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
+
+/* OMAP3 specific register offsets */
+#define OMAP3430ES2_PM_WKEN3                            0x00f0
+#define OMAP3430ES2_PM_WKST3                            0x00b8
+
+#define OMAP3430_PM_MPUGRPSEL                           0x00a4
+#define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
+#define OMAP3430ES2_PM_MPUGRPSEL3                       0x00f8
+
+#define OMAP3430_PM_IVAGRPSEL                           0x00a8
+#define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
+#define OMAP3430ES2_PM_IVAGRPSEL3                       0x00f4
+
+#define OMAP3430_PM_PREPWSTST                           0x00e8
+
+#define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
+#define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
+
+
+#ifndef __ASSEMBLER__
+
+/* Power/reset management domain register get/set */
+extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
+extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
+extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
+extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
+extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
+
+/* These omap2_ PRM functions apply to both OMAP2 and 3 */
+extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
+extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
+extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift);
+
+#endif
+
+/*
+ * Bits common to specific registers
+ *
+ * The 3430 register and bit names are generally used,
+ * since they tend to make more sense
+ */
+
+/* PM_EVGENONTIM_MPU */
+/* Named PM_EVEGENONTIM_MPU on the 24XX */
+#define OMAP_ONTIMEVAL_SHIFT                            0
+#define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
+
+/* PM_EVGENOFFTIM_MPU */
+/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
+#define OMAP_OFFTIMEVAL_SHIFT                           0
+#define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
+
+/* PRM_CLKSETUP and PRCM_VOLTSETUP */
+/* Named PRCM_CLKSSETUP on the 24XX */
+#define OMAP_SETUP_TIME_SHIFT                           0
+#define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
+
+/* PRM_CLKSRC_CTRL */
+/* Named PRCM_CLKSRC_CTRL on the 24XX */
+#define OMAP_SYSCLKDIV_SHIFT                            6
+#define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
+#define OMAP_AUTOEXTCLKMODE_SHIFT                       3
+#define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
+#define OMAP_SYSCLKSEL_SHIFT                            0
+#define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
+
+/* PM_EVGENCTRL_MPU */
+#define OMAP_OFFLOADMODE_SHIFT                          3
+#define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
+#define OMAP_ONLOADMODE_SHIFT                           1
+#define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
+#define OMAP_ENABLE_MASK                                (1 << 0)
+
+/* PRM_RSTTIME */
+/* Named RM_RSTTIME_WKUP on the 24xx */
+#define OMAP_RSTTIME2_SHIFT                             8
+#define OMAP_RSTTIME2_MASK                              (0x1f << 8)
+#define OMAP_RSTTIME1_SHIFT                             0
+#define OMAP_RSTTIME1_MASK                              (0xff << 0)
+
+/* PRM_RSTCTRL */
+/* Named RM_RSTCTRL_WKUP on the 24xx */
+/* 2420 calls RST_DPLL3 'RST_DPLL' */
+#define OMAP_RST_DPLL3_MASK                             (1 << 2)
+#define OMAP_RST_GS_MASK                                (1 << 1)
+
+
+/*
+ * Bits common to module-shared registers
+ *
+ * Not all registers of a particular type support all of these bits -
+ * check TRM if you are unsure
+ */
+
+/*
+ * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
+ *       called 'COREWKUP_RST'
+ *
+ * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
+ *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
+ */
+#define OMAP_COREDOMAINWKUP_RST_MASK                    (1 << 3)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_DOMAINWKUP_RST_MASK                        (1 << 2)
+
+/*
+ * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
+ *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
+ *
+ * 2430: RM_RSTST_MDM
+ *
+ * 3430: RM_RSTST_CORE, RM_RSTST_EMU
+ */
+#define OMAP_GLOBALWARM_RST_MASK                        (1 << 1)
+#define OMAP_GLOBALCOLD_RST_MASK                        (1 << 0)
+
+/*
+ * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
+ *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
+ *
+ * 2430: PM_WKDEP_MDM
+ *
+ * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
+ *       PM_WKDEP_PER
+ */
+#define OMAP_EN_WKUP_SHIFT                              4
+#define OMAP_EN_WKUP_MASK                               (1 << 4)
+
+/*
+ * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSP
+ *
+ * 2430: PM_PWSTCTRL_MDM
+ *
+ * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
+ *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
+ *       PM_PWSTCTRL_NEON
+ */
+#define OMAP_LOGICRETSTATE_MASK                         (1 << 2)
+
+
+/*
+ * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
+ * submodule to exit hardreset
+ */
+#define MAX_MODULE_HARDRESET_WAIT               10000
+
+
+#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a1ff918d9bed..a2a04bfa9628 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -15,12 +15,13 @@
 #include <linux/delay.h>
 #include <linux/errno.h>
 #include <linux/err.h>
+#include <linux/io.h>
 
 #include <plat/common.h>
 #include <plat/cpu.h>
 #include <plat/prcm.h>
 
-#include "prm.h"
+#include "prm44xx.h"
 #include "prm-regbits-44xx.h"
 
 /*
@@ -29,6 +30,70 @@
  */
 #define OMAP4_RST_CTRL_ST_OFFSET                4
 
+/* PRM low-level functions */
+
+/* Read a register in a CM/PRM instance in the PRM module */
+u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
+{
+        return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
+}
+
+/* Write into a register in a CM/PRM instance in the PRM module */
+void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
+{
+        __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
+}
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
+{
+        u32 v;
+
+        v = omap4_prm_read_inst_reg(inst, reg);
+        v &= ~mask;
+        v |= bits;
+        omap4_prm_write_inst_reg(v, inst, reg);
+
+        return v;
+}
+
+/* Read a PRM register, AND it, and shift the result down to bit 0 */
+/* XXX deprecated */
+u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
+{
+        u32 v;
+
+        v = __raw_readl(reg);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+/* Read-modify-write a register in a PRM module. Caller must lock */
+/* XXX deprecated */
+u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
+{
+        u32 v;
+
+        v = __raw_readl(reg);
+        v &= ~mask;
+        v |= bits;
+        __raw_writel(v, reg);
+
+        return v;
+}
+
+u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 reg)
+{
+        return omap4_prm_rmw_inst_reg_bits(bits, bits, inst, reg);
+}
+
+u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
+{
+        return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
+}
+
 /**
  * omap4_prm_is_hardreset_asserted - read the HW reset line state of
  * submodules contained in the hwmod module
@@ -114,3 +179,17 @@ int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
         return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
 }
 
+void omap4_prm_global_warm_sw_reset(void)
+{
+        u32 v;
+
+        v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_RM_RSTCTRL);
+        v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
+        omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_RM_RSTCTRL);
+
+        /* OCP barrier */
+        v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_RM_RSTCTRL);
+}
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 59839dbabd84..67a0d3feb3f6 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -17,736 +17,762 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
+ *
+ * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
+ *     or "OMAP4430".
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 
+#include "prcm-common.h"
+#include "prm.h"
+
+#define OMAP4430_PRM_BASE               0x4a306000
+
+#define OMAP44XX_PRM_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define OMAP4430_PRM_OCP_SOCKET_INST    0x0000
+#define OMAP4430_PRM_CKGEN_INST         0x0100
+#define OMAP4430_PRM_MPU_INST           0x0300
+#define OMAP4430_PRM_TESLA_INST         0x0400
+#define OMAP4430_PRM_ABE_INST           0x0500
+#define OMAP4430_PRM_ALWAYS_ON_INST     0x0600
+#define OMAP4430_PRM_CORE_INST          0x0700
+#define OMAP4430_PRM_IVAHD_INST         0x0f00
+#define OMAP4430_PRM_CAM_INST           0x1000
+#define OMAP4430_PRM_DSS_INST           0x1100
+#define OMAP4430_PRM_GFX_INST           0x1200
+#define OMAP4430_PRM_L3INIT_INST                0x1300
+#define OMAP4430_PRM_L4PER_INST         0x1400
+#define OMAP4430_PRM_CEFUSE_INST                0x1600
+#define OMAP4430_PRM_WKUP_INST          0x1700
+#define OMAP4430_PRM_WKUP_CM_INST       0x1800
+#define OMAP4430_PRM_EMU_INST           0x1900
+#define OMAP4430_PRM_EMU_CM_INST                0x1a00
+#define OMAP4430_PRM_DEVICE_INST                0x1b00
+#define OMAP4430_PRM_INSTR_INST         0x1f00
+
+/* PRM clockdomain register offsets (from instance start) */
+#define OMAP4430_PRM_MPU_MPU_CDOFFS             0x0000
+#define OMAP4430_PRM_TESLA_TESLA_CDOFFS         0x0000
+#define OMAP4430_PRM_ABE_ABE_CDOFFS             0x0000
+#define OMAP4430_PRM_CORE_CORE_CDOFFS           0x0000
+#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS         0x0000
+#define OMAP4430_PRM_CAM_CAM_CDOFFS             0x0000
+#define OMAP4430_PRM_DSS_DSS_CDOFFS             0x0000
+#define OMAP4430_PRM_GFX_GFX_CDOFFS             0x0000
+#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS       0x0000
+#define OMAP4430_PRM_L4PER_L4PER_CDOFFS         0x0000
+#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS       0x0000
+#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS        0x0000
+#define OMAP4430_PRM_EMU_EMU_CDOFFS             0x0000
+#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS          0x0000
+
+/* OMAP4 specific register offsets */
+#define OMAP4_RM_RSTCTRL                                0x0000
+#define OMAP4_RM_RSTTIME                                0x0004
+#define OMAP4_RM_RSTST                                  0x0008
+#define OMAP4_PM_PWSTCTRL                               0x0000
+#define OMAP4_PM_PWSTST                                 0x0004
+
 
 /* PRM */
 
 /* PRM.OCP_SOCKET_PRM register offsets */
 #define OMAP4_REVISION_PRM_OFFSET                       0x0000
-#define OMAP4430_REVISION_PRM                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0000)
+#define OMAP4430_REVISION_PRM                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000)
 #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET                  0x0010
-#define OMAP4430_PRM_IRQSTATUS_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0010)
+#define OMAP4430_PRM_IRQSTATUS_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
 #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET                0x0014
-#define OMAP4430_PRM_IRQSTATUS_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0014)
+#define OMAP4430_PRM_IRQSTATUS_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014)
 #define OMAP4_PRM_IRQENABLE_MPU_OFFSET                  0x0018
-#define OMAP4430_PRM_IRQENABLE_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0018)
+#define OMAP4430_PRM_IRQENABLE_MPU                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
 #define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET                0x001c
-#define OMAP4430_PRM_IRQENABLE_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x001c)
+#define OMAP4430_PRM_IRQENABLE_MPU_2                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c)
 #define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET               0x0020
-#define OMAP4430_PRM_IRQSTATUS_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0020)
+#define OMAP4430_PRM_IRQSTATUS_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020)
 #define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET               0x0028
-#define OMAP4430_PRM_IRQENABLE_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0028)
+#define OMAP4430_PRM_IRQENABLE_DUCATI                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028)
 #define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET                0x0030
-#define OMAP4430_PRM_IRQSTATUS_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
+#define OMAP4430_PRM_IRQSTATUS_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030)
 #define OMAP4_PRM_IRQENABLE_TESLA_OFFSET                0x0038
-#define OMAP4430_PRM_IRQENABLE_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
+#define OMAP4430_PRM_IRQENABLE_TESLA                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038)
 #define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET           0x0040
-#define OMAP4430_CM_PRM_PROFILING_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
+#define OMAP4430_CM_PRM_PROFILING_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040)
 
 /* PRM.CKGEN_PRM register offsets */
 #define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET              0x0000
-#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
+#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000)
 #define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET                  0x0008
-#define OMAP4430_CM_L4_WKUP_CLKSEL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
+#define OMAP4430_CM_L4_WKUP_CLKSEL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008)
 #define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET              0x000c
-#define OMAP4430_CM_ABE_PLL_REF_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x000c)
+#define OMAP4430_CM_ABE_PLL_REF_CLKSEL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c)
 #define OMAP4_CM_SYS_CLKSEL_OFFSET                      0x0010
-#define OMAP4430_CM_SYS_CLKSEL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0010)
+#define OMAP4430_CM_SYS_CLKSEL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010)
 
 /* PRM.MPU_PRM register offsets */
 #define OMAP4_PM_MPU_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_MPU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0000)
+#define OMAP4430_PM_MPU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000)
 #define OMAP4_PM_MPU_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_MPU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0004)
+#define OMAP4430_PM_MPU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004)
 #define OMAP4_RM_MPU_RSTST_OFFSET                       0x0014
-#define OMAP4430_RM_MPU_RSTST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0014)
+#define OMAP4430_RM_MPU_RSTST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014)
 #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET                 0x0024
-#define OMAP4430_RM_MPU_MPU_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_MOD, 0x0024)
+#define OMAP4430_RM_MPU_MPU_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024)
 
 /* PRM.TESLA_PRM register offsets */
 #define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET                 0x0000
-#define OMAP4430_PM_TESLA_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0000)
+#define OMAP4430_PM_TESLA_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000)
 #define OMAP4_PM_TESLA_PWRSTST_OFFSET                   0x0004
-#define OMAP4430_PM_TESLA_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0004)
+#define OMAP4430_PM_TESLA_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004)
 #define OMAP4_RM_TESLA_RSTCTRL_OFFSET                   0x0010
-#define OMAP4430_RM_TESLA_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0010)
+#define OMAP4430_RM_TESLA_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010)
 #define OMAP4_RM_TESLA_RSTST_OFFSET                     0x0014
-#define OMAP4430_RM_TESLA_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0014)
+#define OMAP4430_RM_TESLA_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014)
 #define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET             0x0024
-#define OMAP4430_RM_TESLA_TESLA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_MOD, 0x0024)
+#define OMAP4430_RM_TESLA_TESLA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024)
 
 /* PRM.ABE_PRM register offsets */
 #define OMAP4_PM_ABE_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_ABE_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0000)
+#define OMAP4430_PM_ABE_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000)
 #define OMAP4_PM_ABE_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_ABE_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0004)
+#define OMAP4430_PM_ABE_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004)
 #define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET                0x002c
-#define OMAP4430_RM_ABE_AESS_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x002c)
+#define OMAP4430_RM_ABE_AESS_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c)
 #define OMAP4_PM_ABE_PDM_WKDEP_OFFSET                   0x0030
-#define OMAP4430_PM_ABE_PDM_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0030)
+#define OMAP4430_PM_ABE_PDM_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030)
 #define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET                 0x0034
-#define OMAP4430_RM_ABE_PDM_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0034)
+#define OMAP4430_RM_ABE_PDM_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034)
 #define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET                  0x0038
-#define OMAP4430_PM_ABE_DMIC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0038)
+#define OMAP4430_PM_ABE_DMIC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038)
 #define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET                0x003c
-#define OMAP4430_RM_ABE_DMIC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x003c)
+#define OMAP4430_RM_ABE_DMIC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c)
 #define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET                 0x0040
-#define OMAP4430_PM_ABE_MCASP_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0040)
+#define OMAP4430_PM_ABE_MCASP_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040)
 #define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET               0x0044
-#define OMAP4430_RM_ABE_MCASP_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0044)
+#define OMAP4430_RM_ABE_MCASP_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044)
 #define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET                0x0048
-#define OMAP4430_PM_ABE_MCBSP1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0048)
+#define OMAP4430_PM_ABE_MCBSP1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048)
 #define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET              0x004c
-#define OMAP4430_RM_ABE_MCBSP1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x004c)
+#define OMAP4430_RM_ABE_MCBSP1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c)
 #define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET                0x0050
-#define OMAP4430_PM_ABE_MCBSP2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0050)
+#define OMAP4430_PM_ABE_MCBSP2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050)
 #define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET              0x0054
-#define OMAP4430_RM_ABE_MCBSP2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0054)
+#define OMAP4430_RM_ABE_MCBSP2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054)
 #define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET                0x0058
-#define OMAP4430_PM_ABE_MCBSP3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0058)
+#define OMAP4430_PM_ABE_MCBSP3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058)
 #define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET              0x005c
-#define OMAP4430_RM_ABE_MCBSP3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x005c)
+#define OMAP4430_RM_ABE_MCBSP3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c)
 #define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET               0x0060
-#define OMAP4430_PM_ABE_SLIMBUS_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0060)
+#define OMAP4430_PM_ABE_SLIMBUS_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060)
 #define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET             0x0064
-#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0064)
+#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064)
 #define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET                0x0068
-#define OMAP4430_PM_ABE_TIMER5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0068)
+#define OMAP4430_PM_ABE_TIMER5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068)
 #define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET              0x006c
-#define OMAP4430_RM_ABE_TIMER5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x006c)
+#define OMAP4430_RM_ABE_TIMER5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c)
 #define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET                0x0070
-#define OMAP4430_PM_ABE_TIMER6_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0070)
+#define OMAP4430_PM_ABE_TIMER6_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070)
 #define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET              0x0074
-#define OMAP4430_RM_ABE_TIMER6_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0074)
+#define OMAP4430_RM_ABE_TIMER6_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074)
 #define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET                0x0078
-#define OMAP4430_PM_ABE_TIMER7_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0078)
+#define OMAP4430_PM_ABE_TIMER7_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078)
 #define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET              0x007c
-#define OMAP4430_RM_ABE_TIMER7_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x007c)
+#define OMAP4430_RM_ABE_TIMER7_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c)
 #define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET                0x0080
-#define OMAP4430_PM_ABE_TIMER8_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0080)
+#define OMAP4430_PM_ABE_TIMER8_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080)
 #define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET              0x0084
-#define OMAP4430_RM_ABE_TIMER8_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0084)
+#define OMAP4430_RM_ABE_TIMER8_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084)
 #define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET                  0x0088
-#define OMAP4430_PM_ABE_WDT3_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x0088)
+#define OMAP4430_PM_ABE_WDT3_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088)
 #define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET                0x008c
-#define OMAP4430_RM_ABE_WDT3_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_MOD, 0x008c)
+#define OMAP4430_RM_ABE_WDT3_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c)
 
 /* PRM.ALWAYS_ON_PRM register offsets */
 #define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET           0x0024
-#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0024)
+#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024)
 #define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET              0x0028
-#define OMAP4430_PM_ALWON_SR_MPU_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0028)
+#define OMAP4430_PM_ALWON_SR_MPU_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028)
 #define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET            0x002c
-#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x002c)
+#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c)
 #define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET              0x0030
-#define OMAP4430_PM_ALWON_SR_IVA_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0030)
+#define OMAP4430_PM_ALWON_SR_IVA_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030)
 #define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET            0x0034
-#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0034)
+#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034)
 #define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET             0x0038
-#define OMAP4430_PM_ALWON_SR_CORE_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x0038)
+#define OMAP4430_PM_ALWON_SR_CORE_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038)
 #define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET           0x003c
-#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_MOD, 0x003c)
+#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c)
 
 /* PRM.CORE_PRM register offsets */
 #define OMAP4_PM_CORE_PWRSTCTRL_OFFSET                  0x0000
-#define OMAP4430_PM_CORE_PWRSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0000)
+#define OMAP4430_PM_CORE_PWRSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000)
 #define OMAP4_PM_CORE_PWRSTST_OFFSET                    0x0004
-#define OMAP4430_PM_CORE_PWRSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0004)
+#define OMAP4430_PM_CORE_PWRSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004)
 #define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET               0x0024
-#define OMAP4430_RM_L3_1_L3_1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0024)
+#define OMAP4430_RM_L3_1_L3_1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024)
 #define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET               0x0124
-#define OMAP4430_RM_L3_2_L3_2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0124)
+#define OMAP4430_RM_L3_2_L3_2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124)
 #define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET               0x012c
-#define OMAP4430_RM_L3_2_GPMC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x012c)
+#define OMAP4430_RM_L3_2_GPMC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c)
 #define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET           0x0134
-#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0134)
+#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134)
 #define OMAP4_RM_DUCATI_RSTCTRL_OFFSET                  0x0210
-#define OMAP4430_RM_DUCATI_RSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0210)
+#define OMAP4430_RM_DUCATI_RSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210)
 #define OMAP4_RM_DUCATI_RSTST_OFFSET                    0x0214
-#define OMAP4430_RM_DUCATI_RSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0214)
+#define OMAP4430_RM_DUCATI_RSTST                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214)
 #define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET           0x0224
-#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0224)
+#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224)
 #define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET               0x0324
-#define OMAP4430_RM_SDMA_SDMA_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0324)
+#define OMAP4430_RM_SDMA_SDMA_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324)
 #define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET               0x0424
-#define OMAP4430_RM_MEMIF_DMM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0424)
+#define OMAP4430_RM_MEMIF_DMM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424)
 #define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET           0x042c
-#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x042c)
+#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c)
 #define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET            0x0434
-#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0434)
+#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434)
 #define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET            0x043c
-#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x043c)
+#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c)
 #define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET               0x0444
-#define OMAP4430_RM_MEMIF_DLL_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0444)
+#define OMAP4430_RM_MEMIF_DLL_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444)
 #define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET           0x0454
-#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0454)
+#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454)
 #define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET           0x045c
-#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x045c)
+#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c)
 #define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET             0x0464
-#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0464)
+#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
 #define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET               0x0524
-#define OMAP4430_RM_D2D_SAD2D_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0524)
-#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET           0x052c
-#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x052c)
+#define OMAP4430_RM_D2D_SAD2D_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
+#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET          0x052c
+#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
 #define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET            0x0534
-#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0534)
+#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
 #define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET            0x0624
-#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0624)
+#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624)
 #define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET            0x062c
-#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x062c)
+#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c)
 #define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET           0x0634
-#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0634)
+#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634)
 #define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET           0x063c
-#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x063c)
+#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c)
 #define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET            0x0724
-#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0724)
+#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724)
 #define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET        0x072c
-#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x072c)
+#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c)
 #define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET         0x0744
-#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_MOD, 0x0744)
+#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744)
 
 /* PRM.IVAHD_PRM register offsets */
 #define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET                 0x0000
-#define OMAP4430_PM_IVAHD_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0000)
+#define OMAP4430_PM_IVAHD_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000)
 #define OMAP4_PM_IVAHD_PWRSTST_OFFSET                   0x0004
-#define OMAP4430_PM_IVAHD_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0004)
+#define OMAP4430_PM_IVAHD_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004)
 #define OMAP4_RM_IVAHD_RSTCTRL_OFFSET                   0x0010
-#define OMAP4430_RM_IVAHD_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0010)
+#define OMAP4430_RM_IVAHD_RSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010)
 #define OMAP4_RM_IVAHD_RSTST_OFFSET                     0x0014
-#define OMAP4430_RM_IVAHD_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0014)
+#define OMAP4430_RM_IVAHD_RSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014)
 #define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET             0x0024
-#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x0024)
+#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024)
 #define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET               0x002c
-#define OMAP4430_RM_IVAHD_SL2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_MOD, 0x002c)
+#define OMAP4430_RM_IVAHD_SL2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c)
 
 /* PRM.CAM_PRM register offsets */
 #define OMAP4_PM_CAM_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_CAM_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0000)
+#define OMAP4430_PM_CAM_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000)
 #define OMAP4_PM_CAM_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_CAM_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0004)
+#define OMAP4430_PM_CAM_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004)
 #define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET                 0x0024
-#define OMAP4430_RM_CAM_ISS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x0024)
+#define OMAP4430_RM_CAM_ISS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024)
 #define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET                0x002c
-#define OMAP4430_RM_CAM_FDIF_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_MOD, 0x002c)
+#define OMAP4430_RM_CAM_FDIF_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c)
 
 /* PRM.DSS_PRM register offsets */
 #define OMAP4_PM_DSS_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_DSS_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0000)
+#define OMAP4430_PM_DSS_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000)
 #define OMAP4_PM_DSS_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_DSS_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0004)
+#define OMAP4430_PM_DSS_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004)
 #define OMAP4_PM_DSS_DSS_WKDEP_OFFSET                   0x0020
-#define OMAP4430_PM_DSS_DSS_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0020)
+#define OMAP4430_PM_DSS_DSS_WKDEP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020)
 #define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET                 0x0024
-#define OMAP4430_RM_DSS_DSS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x0024)
+#define OMAP4430_RM_DSS_DSS_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024)
 #define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET               0x002c
-#define OMAP4430_RM_DSS_DEISS_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_MOD, 0x002c)
+#define OMAP4430_RM_DSS_DEISS_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c)
 
 /* PRM.GFX_PRM register offsets */
 #define OMAP4_PM_GFX_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_GFX_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0000)
+#define OMAP4430_PM_GFX_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000)
 #define OMAP4_PM_GFX_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_GFX_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0004)
+#define OMAP4430_PM_GFX_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004)
 #define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET                 0x0024
-#define OMAP4430_RM_GFX_GFX_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_MOD, 0x0024)
+#define OMAP4430_RM_GFX_GFX_CONTEXT                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024)
 
 /* PRM.L3INIT_PRM register offsets */
 #define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET                0x0000
-#define OMAP4430_PM_L3INIT_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0000)
+#define OMAP4430_PM_L3INIT_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000)
 #define OMAP4_PM_L3INIT_PWRSTST_OFFSET                  0x0004
-#define OMAP4430_PM_L3INIT_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0004)
+#define OMAP4430_PM_L3INIT_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004)
 #define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET               0x0028
-#define OMAP4430_PM_L3INIT_MMC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0028)
+#define OMAP4430_PM_L3INIT_MMC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028)
 #define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET             0x002c
-#define OMAP4430_RM_L3INIT_MMC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x002c)
+#define OMAP4430_RM_L3INIT_MMC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c)
 #define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET               0x0030
-#define OMAP4430_PM_L3INIT_MMC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0030)
+#define OMAP4430_PM_L3INIT_MMC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030)
 #define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET             0x0034
-#define OMAP4430_RM_L3INIT_MMC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0034)
+#define OMAP4430_RM_L3INIT_MMC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034)
 #define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET                0x0038
-#define OMAP4430_PM_L3INIT_HSI_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0038)
+#define OMAP4430_PM_L3INIT_HSI_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038)
 #define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET              0x003c
-#define OMAP4430_RM_L3INIT_HSI_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x003c)
+#define OMAP4430_RM_L3INIT_HSI_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c)
 #define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET            0x0040
-#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0040)
+#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040)
 #define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET          0x0044
-#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0044)
+#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044)
 #define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET           0x0058
-#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0058)
+#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058)
 #define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET         0x005c
-#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x005c)
+#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c)
 #define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET            0x0060
-#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0060)
+#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060)
 #define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET          0x0064
-#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0064)
+#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064)
 #define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET            0x0068
-#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0068)
+#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068)
 #define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET          0x006c
-#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x006c)
+#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c)
 #define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET            0x007c
-#define OMAP4430_RM_L3INIT_P1500_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x007c)
+#define OMAP4430_RM_L3INIT_P1500_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c)
 #define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET             0x0084
-#define OMAP4430_RM_L3INIT_EMAC_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0084)
+#define OMAP4430_RM_L3INIT_EMAC_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084)
 #define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET               0x0088
-#define OMAP4430_PM_L3INIT_SATA_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0088)
+#define OMAP4430_PM_L3INIT_SATA_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088)
 #define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET             0x008c
-#define OMAP4430_RM_L3INIT_SATA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x008c)
+#define OMAP4430_RM_L3INIT_SATA_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c)
 #define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET            0x0094
-#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0094)
+#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094)
 #define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET             0x0098
-#define OMAP4430_PM_L3INIT_PCIESS_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x0098)
+#define OMAP4430_PM_L3INIT_PCIESS_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098)
 #define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET           0x009c
-#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x009c)
+#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c)
 #define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET            0x00ac
-#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00ac)
+#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac)
 #define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET               0x00c0
-#define OMAP4430_PM_L3INIT_XHPI_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c0)
+#define OMAP4430_PM_L3INIT_XHPI_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0)
 #define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET             0x00c4
-#define OMAP4430_RM_L3INIT_XHPI_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c4)
+#define OMAP4430_RM_L3INIT_XHPI_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4)
 #define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET               0x00c8
-#define OMAP4430_PM_L3INIT_MMC6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00c8)
+#define OMAP4430_PM_L3INIT_MMC6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8)
 #define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET             0x00cc
-#define OMAP4430_RM_L3INIT_MMC6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00cc)
+#define OMAP4430_RM_L3INIT_MMC6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc)
 #define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET        0x00d0
-#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d0)
+#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0)
 #define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET      0x00d4
-#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00d4)
+#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4)
 #define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET    0x00e4
-#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_MOD, 0x00e4)
+#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4)
 
 /* PRM.L4PER_PRM register offsets */
 #define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET                 0x0000
-#define OMAP4430_PM_L4PER_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0000)
+#define OMAP4430_PM_L4PER_PWRSTCTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000)
 #define OMAP4_PM_L4PER_PWRSTST_OFFSET                   0x0004
-#define OMAP4430_PM_L4PER_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0004)
+#define OMAP4430_PM_L4PER_PWRSTST                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004)
 #define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET               0x0024
-#define OMAP4430_RM_L4PER_ADC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0024)
+#define OMAP4430_RM_L4PER_ADC_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024)
 #define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET           0x0028
-#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0028)
+#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028)
 #define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET         0x002c
-#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x002c)
+#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c)
 #define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET           0x0030
-#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0030)
+#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030)
 #define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET         0x0034
-#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0034)
+#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034)
 #define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET            0x0038
-#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0038)
+#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038)
 #define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET          0x003c
-#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x003c)
+#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c)
 #define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET            0x0040
-#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0040)
+#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040)
 #define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET          0x0044
-#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0044)
+#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044)
 #define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET            0x0048
-#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0048)
+#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048)
 #define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET          0x004c
-#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x004c)
+#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c)
 #define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET            0x0050
-#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0050)
+#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050)
 #define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET          0x0054
-#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0054)
+#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054)
 #define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET               0x005c
-#define OMAP4430_RM_L4PER_ELM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x005c)
+#define OMAP4430_RM_L4PER_ELM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c)
 #define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET               0x0060
-#define OMAP4430_PM_L4PER_GPIO2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0060)
+#define OMAP4430_PM_L4PER_GPIO2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060)
 #define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET             0x0064
-#define OMAP4430_RM_L4PER_GPIO2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0064)
+#define OMAP4430_RM_L4PER_GPIO2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064)
 #define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET               0x0068
-#define OMAP4430_PM_L4PER_GPIO3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0068)
+#define OMAP4430_PM_L4PER_GPIO3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068)
 #define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET             0x006c
-#define OMAP4430_RM_L4PER_GPIO3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x006c)
+#define OMAP4430_RM_L4PER_GPIO3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c)
 #define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET               0x0070
-#define OMAP4430_PM_L4PER_GPIO4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0070)
+#define OMAP4430_PM_L4PER_GPIO4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070)
 #define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET             0x0074
-#define OMAP4430_RM_L4PER_GPIO4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0074)
+#define OMAP4430_RM_L4PER_GPIO4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074)
 #define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET               0x0078
-#define OMAP4430_PM_L4PER_GPIO5_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0078)
+#define OMAP4430_PM_L4PER_GPIO5_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078)
 #define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET             0x007c
-#define OMAP4430_RM_L4PER_GPIO5_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x007c)
+#define OMAP4430_RM_L4PER_GPIO5_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c)
 #define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET               0x0080
-#define OMAP4430_PM_L4PER_GPIO6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0080)
+#define OMAP4430_PM_L4PER_GPIO6_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080)
 #define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET             0x0084
-#define OMAP4430_RM_L4PER_GPIO6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0084)
+#define OMAP4430_RM_L4PER_GPIO6_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084)
 #define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET             0x008c
-#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x008c)
+#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c)
 #define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET               0x0090
-#define OMAP4430_PM_L4PER_HECC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0090)
+#define OMAP4430_PM_L4PER_HECC1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090)
 #define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET             0x0094
-#define OMAP4430_RM_L4PER_HECC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0094)
+#define OMAP4430_RM_L4PER_HECC1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094)
 #define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET               0x0098
-#define OMAP4430_PM_L4PER_HECC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0098)
+#define OMAP4430_PM_L4PER_HECC2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098)
 #define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET             0x009c
-#define OMAP4430_RM_L4PER_HECC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x009c)
+#define OMAP4430_RM_L4PER_HECC2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c)
 #define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET                0x00a0
-#define OMAP4430_PM_L4PER_I2C1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a0)
+#define OMAP4430_PM_L4PER_I2C1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0)
 #define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET              0x00a4
-#define OMAP4430_RM_L4PER_I2C1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a4)
+#define OMAP4430_RM_L4PER_I2C1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4)
 #define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET                0x00a8
-#define OMAP4430_PM_L4PER_I2C2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00a8)
+#define OMAP4430_PM_L4PER_I2C2_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8)
 #define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET              0x00ac
-#define OMAP4430_RM_L4PER_I2C2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ac)
+#define OMAP4430_RM_L4PER_I2C2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac)
 #define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET                0x00b0
-#define OMAP4430_PM_L4PER_I2C3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b0)
+#define OMAP4430_PM_L4PER_I2C3_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0)
 #define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET              0x00b4
-#define OMAP4430_RM_L4PER_I2C3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b4)
+#define OMAP4430_RM_L4PER_I2C3_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4)
 #define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET                0x00b8
-#define OMAP4430_PM_L4PER_I2C4_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00b8)
+#define OMAP4430_PM_L4PER_I2C4_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8)
 #define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET              0x00bc
-#define OMAP4430_RM_L4PER_I2C4_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00bc)
+#define OMAP4430_RM_L4PER_I2C4_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc)
 #define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET            0x00c0
-#define OMAP4430_RM_L4PER_L4_PER_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00c0)
+#define OMAP4430_RM_L4PER_L4_PER_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0)
 #define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET              0x00d0
-#define OMAP4430_PM_L4PER_MCASP2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d0)
+#define OMAP4430_PM_L4PER_MCASP2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0)
 #define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET            0x00d4
-#define OMAP4430_RM_L4PER_MCASP2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d4)
+#define OMAP4430_RM_L4PER_MCASP2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4)
 #define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET              0x00d8
-#define OMAP4430_PM_L4PER_MCASP3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00d8)
+#define OMAP4430_PM_L4PER_MCASP3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8)
 #define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET            0x00dc
-#define OMAP4430_RM_L4PER_MCASP3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00dc)
+#define OMAP4430_RM_L4PER_MCASP3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc)
 #define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET              0x00e0
-#define OMAP4430_PM_L4PER_MCBSP4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e0)
+#define OMAP4430_PM_L4PER_MCBSP4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0)
 #define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET            0x00e4
-#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00e4)
+#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4)
 #define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET             0x00ec
-#define OMAP4430_RM_L4PER_MGATE_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00ec)
+#define OMAP4430_RM_L4PER_MGATE_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec)
 #define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET              0x00f0
-#define OMAP4430_PM_L4PER_MCSPI1_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f0)
+#define OMAP4430_PM_L4PER_MCSPI1_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0)
 #define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET            0x00f4
-#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f4)
+#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4)
 #define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET              0x00f8
-#define OMAP4430_PM_L4PER_MCSPI2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00f8)
+#define OMAP4430_PM_L4PER_MCSPI2_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8)
 #define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET            0x00fc
-#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x00fc)
+#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc)
 #define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET              0x0100
-#define OMAP4430_PM_L4PER_MCSPI3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0100)
+#define OMAP4430_PM_L4PER_MCSPI3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100)
 #define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET            0x0104
-#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0104)
+#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104)
 #define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET              0x0108
-#define OMAP4430_PM_L4PER_MCSPI4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0108)
+#define OMAP4430_PM_L4PER_MCSPI4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108)
 #define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET            0x010c
-#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x010c)
+#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c)
 #define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET              0x0120
-#define OMAP4430_PM_L4PER_MMCSD3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0120)
+#define OMAP4430_PM_L4PER_MMCSD3_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120)
 #define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET            0x0124
-#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0124)
+#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124)
 #define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET              0x0128
-#define OMAP4430_PM_L4PER_MMCSD4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0128)
+#define OMAP4430_PM_L4PER_MMCSD4_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128)
 #define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET            0x012c
-#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x012c)
+#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c)
 #define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET           0x0134
-#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0134)
+#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134)
 #define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET            0x0138
-#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0138)
+#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138)
 #define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET          0x013c
-#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x013c)
+#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c)
 #define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET               0x0140
-#define OMAP4430_PM_L4PER_UART1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0140)
+#define OMAP4430_PM_L4PER_UART1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140)
 #define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET             0x0144
-#define OMAP4430_RM_L4PER_UART1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0144)
+#define OMAP4430_RM_L4PER_UART1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144)
 #define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET               0x0148
-#define OMAP4430_PM_L4PER_UART2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0148)
+#define OMAP4430_PM_L4PER_UART2_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148)
 #define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET             0x014c
-#define OMAP4430_RM_L4PER_UART2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x014c)
+#define OMAP4430_RM_L4PER_UART2_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c)
 #define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET               0x0150
-#define OMAP4430_PM_L4PER_UART3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0150)
+#define OMAP4430_PM_L4PER_UART3_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150)
 #define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET             0x0154
-#define OMAP4430_RM_L4PER_UART3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0154)
+#define OMAP4430_RM_L4PER_UART3_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154)
 #define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET               0x0158
-#define OMAP4430_PM_L4PER_UART4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0158)
+#define OMAP4430_PM_L4PER_UART4_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158)
 #define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET             0x015c
-#define OMAP4430_RM_L4PER_UART4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x015c)
+#define OMAP4430_RM_L4PER_UART4_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c)
 #define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET              0x0160
-#define OMAP4430_PM_L4PER_MMCSD5_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0160)
+#define OMAP4430_PM_L4PER_MMCSD5_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160)
 #define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET            0x0164
-#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0164)
+#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164)
 #define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET                0x0168
-#define OMAP4430_PM_L4PER_I2C5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x0168)
+#define OMAP4430_PM_L4PER_I2C5_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168)
 #define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET              0x016c
-#define OMAP4430_RM_L4PER_I2C5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x016c)
+#define OMAP4430_RM_L4PER_I2C5_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c)
 #define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET              0x01a4
-#define OMAP4430_RM_L4SEC_AES1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01a4)
+#define OMAP4430_RM_L4SEC_AES1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4)
 #define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET              0x01ac
-#define OMAP4430_RM_L4SEC_AES2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01ac)
+#define OMAP4430_RM_L4SEC_AES2_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac)
 #define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET           0x01b4
-#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01b4)
+#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4)
 #define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET          0x01bc
-#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01bc)
+#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc)
 #define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET               0x01c4
-#define OMAP4430_RM_L4SEC_RNG_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01c4)
+#define OMAP4430_RM_L4SEC_RNG_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4)
 #define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET          0x01cc
-#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01cc)
+#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc)
 #define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET         0x01dc
-#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_MOD, 0x01dc)
+#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT             OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc)
 
 /* PRM.CEFUSE_PRM register offsets */
 #define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET                0x0000
-#define OMAP4430_PM_CEFUSE_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0000)
+#define OMAP4430_PM_CEFUSE_PWRSTCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000)
 #define OMAP4_PM_CEFUSE_PWRSTST_OFFSET                  0x0004
-#define OMAP4430_PM_CEFUSE_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0004)
+#define OMAP4430_PM_CEFUSE_PWRSTST                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004)
 #define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET           0x0024
-#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_MOD, 0x0024)
+#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024)
 
 /* PRM.WKUP_PRM register offsets */
 #define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET             0x0024
-#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0024)
+#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024)
 #define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET               0x002c
-#define OMAP4430_RM_WKUP_WDT1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x002c)
+#define OMAP4430_RM_WKUP_WDT1_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c)
 #define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET                 0x0030
-#define OMAP4430_PM_WKUP_WDT2_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0030)
+#define OMAP4430_PM_WKUP_WDT2_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030)
 #define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET               0x0034
-#define OMAP4430_RM_WKUP_WDT2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0034)
+#define OMAP4430_RM_WKUP_WDT2_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034)
 #define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET                0x0038
-#define OMAP4430_PM_WKUP_GPIO1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0038)
+#define OMAP4430_PM_WKUP_GPIO1_WKDEP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038)
 #define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET              0x003c
-#define OMAP4430_RM_WKUP_GPIO1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x003c)
+#define OMAP4430_RM_WKUP_GPIO1_CONTEXT                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c)
 #define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET               0x0040
-#define OMAP4430_PM_WKUP_TIMER1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0040)
+#define OMAP4430_PM_WKUP_TIMER1_WKDEP                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040)
 #define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET             0x0044
-#define OMAP4430_RM_WKUP_TIMER1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0044)
+#define OMAP4430_RM_WKUP_TIMER1_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044)
 #define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET              0x0048
-#define OMAP4430_PM_WKUP_TIMER12_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0048)
+#define OMAP4430_PM_WKUP_TIMER12_WKDEP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048)
 #define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET            0x004c
-#define OMAP4430_RM_WKUP_TIMER12_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x004c)
+#define OMAP4430_RM_WKUP_TIMER12_CONTEXT                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c)
 #define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET          0x0054
-#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0054)
+#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054)
 #define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET                 0x0058
-#define OMAP4430_PM_WKUP_USIM_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0058)
+#define OMAP4430_PM_WKUP_USIM_WKDEP                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058)
 #define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET               0x005c
-#define OMAP4430_RM_WKUP_USIM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x005c)
+#define OMAP4430_RM_WKUP_USIM_CONTEXT                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c)
 #define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET             0x0064
-#define OMAP4430_RM_WKUP_SARRAM_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0064)
+#define OMAP4430_RM_WKUP_SARRAM_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064)
 #define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET             0x0078
-#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0078)
+#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078)
 #define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET           0x007c
-#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x007c)
+#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c)
 #define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET                  0x0080
-#define OMAP4430_PM_WKUP_RTC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0080)
+#define OMAP4430_PM_WKUP_RTC_WKDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080)
 #define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET                0x0084
-#define OMAP4430_RM_WKUP_RTC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_MOD, 0x0084)
+#define OMAP4430_RM_WKUP_RTC_CONTEXT                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084)
 
 /* PRM.WKUP_CM register offsets */
 #define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET                  0x0000
-#define OMAP4430_CM_WKUP_CLKSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0000)
+#define OMAP4430_CM_WKUP_CLKSTCTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000)
 #define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET             0x0020
-#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0020)
+#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020)
 #define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET               0x0028
-#define OMAP4430_CM_WKUP_WDT1_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0028)
+#define OMAP4430_CM_WKUP_WDT1_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028)
 #define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET               0x0030
-#define OMAP4430_CM_WKUP_WDT2_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0030)
+#define OMAP4430_CM_WKUP_WDT2_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030)
 #define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET              0x0038
-#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0038)
+#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038)
 #define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET             0x0040
-#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0040)
+#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040)
 #define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET            0x0048
-#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0048)
+#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048)
 #define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET          0x0050
-#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0050)
+#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050)
 #define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET               0x0058
-#define OMAP4430_CM_WKUP_USIM_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0058)
+#define OMAP4430_CM_WKUP_USIM_CLKCTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058)
 #define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET             0x0060
-#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0060)
+#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060)
 #define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET           0x0078
-#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0078)
+#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078)
 #define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET                0x0080
-#define OMAP4430_CM_WKUP_RTC_CLKCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0080)
+#define OMAP4430_CM_WKUP_RTC_CLKCTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080)
 #define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET            0x0088
-#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_MOD, 0x0088)
+#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088)
 
 /* PRM.EMU_PRM register offsets */
 #define OMAP4_PM_EMU_PWRSTCTRL_OFFSET                   0x0000
-#define OMAP4430_PM_EMU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0000)
+#define OMAP4430_PM_EMU_PWRSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000)
 #define OMAP4_PM_EMU_PWRSTST_OFFSET                     0x0004
-#define OMAP4430_PM_EMU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0004)
+#define OMAP4430_PM_EMU_PWRSTST                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004)
 #define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET             0x0024
-#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_MOD, 0x0024)
+#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024)
 
 /* PRM.EMU_CM register offsets */
 #define OMAP4_CM_EMU_CLKSTCTRL_OFFSET                   0x0000
-#define OMAP4430_CM_EMU_CLKSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0000)
+#define OMAP4430_CM_EMU_CLKSTCTRL                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000)
 #define OMAP4_CM_EMU_DYNAMICDEP_OFFSET                  0x0008
-#define OMAP4430_CM_EMU_DYNAMICDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0008)
+#define OMAP4430_CM_EMU_DYNAMICDEP                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008)
 #define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET             0x0020
-#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_MOD, 0x0020)
+#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020)
 
 /* PRM.DEVICE_PRM register offsets */
 #define OMAP4_PRM_RSTCTRL_OFFSET                        0x0000
-#define OMAP4430_PRM_RSTCTRL                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0000)
+#define OMAP4430_PRM_RSTCTRL                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000)
 #define OMAP4_PRM_RSTST_OFFSET                          0x0004
-#define OMAP4430_PRM_RSTST                              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0004)
+#define OMAP4430_PRM_RSTST                              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004)
 #define OMAP4_PRM_RSTTIME_OFFSET                        0x0008
-#define OMAP4430_PRM_RSTTIME                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0008)
+#define OMAP4430_PRM_RSTTIME                            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008)
 #define OMAP4_PRM_CLKREQCTRL_OFFSET                     0x000c
-#define OMAP4430_PRM_CLKREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x000c)
+#define OMAP4430_PRM_CLKREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c)
 #define OMAP4_PRM_VOLTCTRL_OFFSET                       0x0010
-#define OMAP4430_PRM_VOLTCTRL                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0010)
+#define OMAP4430_PRM_VOLTCTRL                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010)
 #define OMAP4_PRM_PWRREQCTRL_OFFSET                     0x0014
-#define OMAP4430_PRM_PWRREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0014)
+#define OMAP4430_PRM_PWRREQCTRL                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014)
 #define OMAP4_PRM_PSCON_COUNT_OFFSET                    0x0018
-#define OMAP4430_PRM_PSCON_COUNT                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0018)
+#define OMAP4430_PRM_PSCON_COUNT                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018)
 #define OMAP4_PRM_IO_COUNT_OFFSET                       0x001c
-#define OMAP4430_PRM_IO_COUNT                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x001c)
+#define OMAP4430_PRM_IO_COUNT                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c)
 #define OMAP4_PRM_IO_PMCTRL_OFFSET                      0x0020
-#define OMAP4430_PRM_IO_PMCTRL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0020)
+#define OMAP4430_PRM_IO_PMCTRL                          OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020)
 #define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET            0x0024
-#define OMAP4430_PRM_VOLTSETUP_WARMRESET                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0024)
+#define OMAP4430_PRM_VOLTSETUP_WARMRESET                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024)
 #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET             0x0028
-#define OMAP4430_PRM_VOLTSETUP_CORE_OFF                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0028)
+#define OMAP4430_PRM_VOLTSETUP_CORE_OFF                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028)
 #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET              0x002c
-#define OMAP4430_PRM_VOLTSETUP_MPU_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x002c)
+#define OMAP4430_PRM_VOLTSETUP_MPU_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c)
 #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET              0x0030
-#define OMAP4430_PRM_VOLTSETUP_IVA_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0030)
+#define OMAP4430_PRM_VOLTSETUP_IVA_OFF                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030)
 #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET       0x0034
-#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0034)
+#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034)
 #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET        0x0038
-#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0038)
+#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038)
 #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET        0x003c
-#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x003c)
+#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP            OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c)
 #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET                 0x0040
-#define OMAP4430_PRM_VP_CORE_CONFIG                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0040)
+#define OMAP4430_PRM_VP_CORE_CONFIG                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040)
 #define OMAP4_PRM_VP_CORE_STATUS_OFFSET                 0x0044
-#define OMAP4430_PRM_VP_CORE_STATUS                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0044)
+#define OMAP4430_PRM_VP_CORE_STATUS                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044)
 #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET               0x0048
-#define OMAP4430_PRM_VP_CORE_VLIMITTO                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0048)
+#define OMAP4430_PRM_VP_CORE_VLIMITTO                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048)
 #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET                0x004c
-#define OMAP4430_PRM_VP_CORE_VOLTAGE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x004c)
+#define OMAP4430_PRM_VP_CORE_VOLTAGE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c)
 #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET               0x0050
-#define OMAP4430_PRM_VP_CORE_VSTEPMAX                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0050)
+#define OMAP4430_PRM_VP_CORE_VSTEPMAX                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050)
 #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET               0x0054
-#define OMAP4430_PRM_VP_CORE_VSTEPMIN                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0054)
+#define OMAP4430_PRM_VP_CORE_VSTEPMIN                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054)
 #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET                  0x0058
-#define OMAP4430_PRM_VP_MPU_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0058)
+#define OMAP4430_PRM_VP_MPU_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058)
 #define OMAP4_PRM_VP_MPU_STATUS_OFFSET                  0x005c
-#define OMAP4430_PRM_VP_MPU_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x005c)
+#define OMAP4430_PRM_VP_MPU_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c)
 #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET                0x0060
-#define OMAP4430_PRM_VP_MPU_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0060)
+#define OMAP4430_PRM_VP_MPU_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060)
 #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET                 0x0064
-#define OMAP4430_PRM_VP_MPU_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0064)
+#define OMAP4430_PRM_VP_MPU_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064)
 #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET                0x0068
-#define OMAP4430_PRM_VP_MPU_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0068)
+#define OMAP4430_PRM_VP_MPU_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068)
 #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET                0x006c
-#define OMAP4430_PRM_VP_MPU_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x006c)
+#define OMAP4430_PRM_VP_MPU_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c)
 #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET                  0x0070
-#define OMAP4430_PRM_VP_IVA_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0070)
+#define OMAP4430_PRM_VP_IVA_CONFIG                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070)
 #define OMAP4_PRM_VP_IVA_STATUS_OFFSET                  0x0074
-#define OMAP4430_PRM_VP_IVA_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0074)
+#define OMAP4430_PRM_VP_IVA_STATUS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074)
 #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET                0x0078
-#define OMAP4430_PRM_VP_IVA_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0078)
+#define OMAP4430_PRM_VP_IVA_VLIMITTO                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078)
 #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET                 0x007c
-#define OMAP4430_PRM_VP_IVA_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x007c)
+#define OMAP4430_PRM_VP_IVA_VOLTAGE                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c)
 #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET                0x0080
-#define OMAP4430_PRM_VP_IVA_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0080)
+#define OMAP4430_PRM_VP_IVA_VSTEPMAX                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080)
 #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET                0x0084
-#define OMAP4430_PRM_VP_IVA_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0084)
+#define OMAP4430_PRM_VP_IVA_VSTEPMIN                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084)
 #define OMAP4_PRM_VC_SMPS_SA_OFFSET                     0x0088
-#define OMAP4430_PRM_VC_SMPS_SA                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0088)
+#define OMAP4430_PRM_VC_SMPS_SA                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088)
 #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET             0x008c
-#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x008c)
+#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c)
 #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET             0x0090
-#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0090)
+#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET          0x0094
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0094)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L              OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET           0x0098
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x0098)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098)
 #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET           0x009c
-#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x009c)
+#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L               OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c)
 #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET                  0x00a0
-#define OMAP4430_PRM_VC_VAL_BYPASS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a0)
+#define OMAP4430_PRM_VC_VAL_BYPASS                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
 #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET                 0x00a4
-#define OMAP4430_PRM_VC_CFG_CHANNEL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a4)
-#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET                0x00a8
-#define OMAP4430_PRM_VC_CFG_I2C_MODE                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00a8)
+#define OMAP4430_PRM_VC_CFG_CHANNEL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
+#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET               0x00a8
+#define OMAP4430_PRM_VC_CFG_I2C_INSTE                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
 #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET                 0x00ac
-#define OMAP4430_PRM_VC_CFG_I2C_CLK                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ac)
+#define OMAP4430_PRM_VC_CFG_I2C_CLK                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
 #define OMAP4_PRM_SRAM_COUNT_OFFSET                     0x00b0
-#define OMAP4430_PRM_SRAM_COUNT                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b0)
+#define OMAP4430_PRM_SRAM_COUNT                         OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0)
 #define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET                0x00b4
-#define OMAP4430_PRM_SRAM_WKUP_SETUP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b4)
+#define OMAP4430_PRM_SRAM_WKUP_SETUP                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4)
 #define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET            0x00b8
-#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00b8)
+#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP                OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8)
 #define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET             0x00bc
-#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00bc)
+#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc)
 #define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET             0x00c0
-#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c0)
+#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0)
 #define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET              0x00c4
-#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c4)
+#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4)
 #define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET             0x00c8
-#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00c8)
+#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP                 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8)
 #define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET              0x00cc
-#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00cc)
+#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc)
 #define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET              0x00d0
-#define OMAP4430_PRM_LDO_ABB_MPU_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d0)
+#define OMAP4430_PRM_LDO_ABB_MPU_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0)
 #define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET               0x00d4
-#define OMAP4430_PRM_LDO_ABB_MPU_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d4)
+#define OMAP4430_PRM_LDO_ABB_MPU_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4)
 #define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET              0x00d8
-#define OMAP4430_PRM_LDO_ABB_IVA_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
+#define OMAP4430_PRM_LDO_ABB_IVA_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8)
 #define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET               0x00dc
-#define OMAP4430_PRM_LDO_ABB_IVA_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
+#define OMAP4430_PRM_LDO_ABB_IVA_CTRL                   OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc)
 #define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET              0x00e0
-#define OMAP4430_PRM_LDO_BANDGAP_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
+#define OMAP4430_PRM_LDO_BANDGAP_SETUP                  OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0)
 #define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET                0x00e4
-#define OMAP4430_PRM_DEVICE_OFF_CTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
+#define OMAP4430_PRM_DEVICE_OFF_CTRL                    OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4)
 #define OMAP4_PRM_PHASE1_CNDP_OFFSET                    0x00e8
-#define OMAP4430_PRM_PHASE1_CNDP                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e8)
+#define OMAP4430_PRM_PHASE1_CNDP                        OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8)
 #define OMAP4_PRM_PHASE2A_CNDP_OFFSET                   0x00ec
-#define OMAP4430_PRM_PHASE2A_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00ec)
+#define OMAP4430_PRM_PHASE2A_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
 #define OMAP4_PRM_PHASE2B_CNDP_OFFSET                   0x00f0
-#define OMAP4430_PRM_PHASE2B_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
-#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET                  0x00f4
-#define OMAP4430_PRM_MODEM_IF_CTRL                      OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
+#define OMAP4430_PRM_PHASE2B_CNDP                       OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
+#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET                 0x00f4
+#define OMAP4430_PRM_INSTEM_IF_CTRL                     OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
 #define OMAP4_PRM_VC_ERRST_OFFSET                       0x00f8
-#define OMAP4430_PRM_VC_ERRST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8)
+#define OMAP4430_PRM_VC_ERRST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
 
-/*
- * PRCM_MPU
- *
- * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
- * point of view the PRCM_MPU is a single entity. It shares the same
- * programming model as the global PRCM and thus can be assimilate as two new
- * MOD inside the PRCM
- */
+/* Function prototypes */
+# ifndef __ASSEMBLER__
+
+extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
+extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
+extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
+
+extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
+extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
+extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
+
+extern void omap4_prm_global_warm_sw_reset(void);
+
+# endif
 
-/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
-#define OMAP4_REVISION_PRCM_OFFSET                      0x0000
-#define OMAP4430_REVISION_PRCM                          OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)
-
-/* PRCM_MPU.DEVICE_PRM register offsets */
-#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET                 0x0000
-#define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
-#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET           0x0004
-#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT               OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
-
-/* PRCM_MPU.CPU0 register offsets */
-#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET                  0x0000
-#define OMAP4430_PM_CPU0_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)
-#define OMAP4_PM_CPU0_PWRSTST_OFFSET                    0x0004
-#define OMAP4430_PM_CPU0_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)
-#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET               0x0008
-#define OMAP4430_RM_CPU0_CPU0_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)
-#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET               0x000c
-#define OMAP4430_RM_CPU0_CPU0_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)
-#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET                 0x0010
-#define OMAP4430_RM_CPU0_CPU0_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)
-#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET               0x0014
-#define OMAP4430_CM_CPU0_CPU0_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)
-#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET                  0x0018
-#define OMAP4430_CM_CPU0_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)
-
-/* PRCM_MPU.CPU1 register offsets */
-#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET                  0x0000
-#define OMAP4430_PM_CPU1_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)
-#define OMAP4_PM_CPU1_PWRSTST_OFFSET                    0x0004
-#define OMAP4430_PM_CPU1_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)
-#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET               0x0008
-#define OMAP4430_RM_CPU1_CPU1_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)
-#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET               0x000c
-#define OMAP4430_RM_CPU1_CPU1_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)
-#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET                 0x0010
-#define OMAP4430_RM_CPU1_CPU1_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)
-#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET               0x0014
-#define OMAP4430_CM_CPU1_CPU1_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)
-#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET                  0x0018
-#define OMAP4430_CM_CPU1_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)
 #endif
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
new file mode 100644
index 000000000000..a30324297278
--- /dev/null
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -0,0 +1,66 @@
+/*
+ * OMAP4 PRM instance functions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "prm44xx.h"
+#include "prminst44xx.h"
+#include "prm-regbits-44xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu44xx.h"
+
+static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
+        [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
+        [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
+        [OMAP4430_CM1_PARTITION]                = 0,
+        [OMAP4430_CM2_PARTITION]                = 0,
+        [OMAP4430_SCRM_PARTITION]               = 0,
+        [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
+};
+
+/* Read a register in a PRM instance */
+u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
+{
+        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
+               part == OMAP4430_INVALID_PRCM_PARTITION ||
+               !_prm_bases[part]);
+        return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst +
+                                               idx));
+}
+
+/* Write into a register in a PRM instance */
+void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
+{
+        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
+               part == OMAP4430_INVALID_PRCM_PARTITION ||
+               !_prm_bases[part]);
+        __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx));
+}
+
+/* Read-modify-write a register in PRM. Caller must lock */
+u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
+                                   s16 idx)
+{
+        u32 v;
+
+        v = omap4_prminst_read_inst_reg(part, inst, idx);
+        v &= ~mask;
+        v |= bits;
+        omap4_prminst_write_inst_reg(v, part, inst, idx);
+
+        return v;
+}
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
new file mode 100644
index 000000000000..02dd66ddda8b
--- /dev/null
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -0,0 +1,25 @@
+/*
+ * OMAP4 Power/Reset Management (PRM) function prototypes
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
+#define __ARCH_ASM_MACH_OMAP2_PRMINST44XX_H
+
+/*
+ * In an ideal world, we would not export these low-level functions,
+ * but this will probably take some time to fix properly
+ */
+extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
+extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
+extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
+                                           s16 inst, s16 idx);
+
+extern void omap4_prm_global_warm_sw_reset(void);
+
+#endif
diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h
new file mode 100644
index 000000000000..701bf2d32949
--- /dev/null
+++ b/arch/arm/mach-omap2/scrm44xx.h
@@ -0,0 +1,175 @@
+/*
+ * OMAP44xx SCRM registers and bitfields
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
+#define __ARCH_ARM_MACH_OMAP2_SCRM_44XX_H
+
+#define OMAP4_SCRM_BASE                         0x4a30a000
+
+#define OMAP44XX_SCRM_REGADDR(reg)      \
+                OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg))
+
+/* Registers offset */
+#define OMAP4_SCRM_REVISION_SCRM_OFFSET         0x0000
+#define OMAP4_SCRM_REVISION_SCRM                OMAP44XX_SCRM_REGADDR(0x0000)
+#define OMAP4_SCRM_CLKSETUPTIME_OFFSET          0x0100
+#define OMAP4_SCRM_CLKSETUPTIME                 OMAP44XX_SCRM_REGADDR(0x0100)
+#define OMAP4_SCRM_PMICSETUPTIME_OFFSET         0x0104
+#define OMAP4_SCRM_PMICSETUPTIME                OMAP44XX_SCRM_REGADDR(0x0104)
+#define OMAP4_SCRM_ALTCLKSRC_OFFSET             0x0110
+#define OMAP4_SCRM_ALTCLKSRC                    OMAP44XX_SCRM_REGADDR(0x0110)
+#define OMAP4_SCRM_MODEMCLKM_OFFSET             0x0118
+#define OMAP4_SCRM_MODEMCLKM                    OMAP44XX_SCRM_REGADDR(0x0118)
+#define OMAP4_SCRM_D2DCLKM_OFFSET               0x011c
+#define OMAP4_SCRM_D2DCLKM                      OMAP44XX_SCRM_REGADDR(0x011c)
+#define OMAP4_SCRM_EXTCLKREQ_OFFSET             0x0200
+#define OMAP4_SCRM_EXTCLKREQ                    OMAP44XX_SCRM_REGADDR(0x0200)
+#define OMAP4_SCRM_ACCCLKREQ_OFFSET             0x0204
+#define OMAP4_SCRM_ACCCLKREQ                    OMAP44XX_SCRM_REGADDR(0x0204)
+#define OMAP4_SCRM_PWRREQ_OFFSET                0x0208
+#define OMAP4_SCRM_PWRREQ                       OMAP44XX_SCRM_REGADDR(0x0208)
+#define OMAP4_SCRM_AUXCLKREQ0_OFFSET            0x0210
+#define OMAP4_SCRM_AUXCLKREQ0                   OMAP44XX_SCRM_REGADDR(0x0210)
+#define OMAP4_SCRM_AUXCLKREQ1_OFFSET            0x0214
+#define OMAP4_SCRM_AUXCLKREQ1                   OMAP44XX_SCRM_REGADDR(0x0214)
+#define OMAP4_SCRM_AUXCLKREQ2_OFFSET            0x0218
+#define OMAP4_SCRM_AUXCLKREQ2                   OMAP44XX_SCRM_REGADDR(0x0218)
+#define OMAP4_SCRM_AUXCLKREQ3_OFFSET            0x021c
+#define OMAP4_SCRM_AUXCLKREQ3                   OMAP44XX_SCRM_REGADDR(0x021c)
+#define OMAP4_SCRM_AUXCLKREQ4_OFFSET            0x0220
+#define OMAP4_SCRM_AUXCLKREQ4                   OMAP44XX_SCRM_REGADDR(0x0220)
+#define OMAP4_SCRM_AUXCLKREQ5_OFFSET            0x0224
+#define OMAP4_SCRM_AUXCLKREQ5                   OMAP44XX_SCRM_REGADDR(0x0224)
+#define OMAP4_SCRM_D2DCLKREQ_OFFSET             0x0234
+#define OMAP4_SCRM_D2DCLKREQ                    OMAP44XX_SCRM_REGADDR(0x0234)
+#define OMAP4_SCRM_AUXCLK0_OFFSET               0x0310
+#define OMAP4_SCRM_AUXCLK0                      OMAP44XX_SCRM_REGADDR(0x0310)
+#define OMAP4_SCRM_AUXCLK1_OFFSET               0x0314
+#define OMAP4_SCRM_AUXCLK1                      OMAP44XX_SCRM_REGADDR(0x0314)
+#define OMAP4_SCRM_AUXCLK2_OFFSET               0x0318
+#define OMAP4_SCRM_AUXCLK2                      OMAP44XX_SCRM_REGADDR(0x0318)
+#define OMAP4_SCRM_AUXCLK3_OFFSET               0x031c
+#define OMAP4_SCRM_AUXCLK3                      OMAP44XX_SCRM_REGADDR(0x031c)
+#define OMAP4_SCRM_AUXCLK4_OFFSET               0x0320
+#define OMAP4_SCRM_AUXCLK4                      OMAP44XX_SCRM_REGADDR(0x0320)
+#define OMAP4_SCRM_AUXCLK5_OFFSET               0x0324
+#define OMAP4_SCRM_AUXCLK5                      OMAP44XX_SCRM_REGADDR(0x0324)
+#define OMAP4_SCRM_RSTTIME_OFFSET               0x0400
+#define OMAP4_SCRM_RSTTIME                      OMAP44XX_SCRM_REGADDR(0x0400)
+#define OMAP4_SCRM_MODEMRSTCTRL_OFFSET          0x0418
+#define OMAP4_SCRM_MODEMRSTCTRL                 OMAP44XX_SCRM_REGADDR(0x0418)
+#define OMAP4_SCRM_D2DRSTCTRL_OFFSET            0x041c
+#define OMAP4_SCRM_D2DRSTCTRL                   OMAP44XX_SCRM_REGADDR(0x041c)
+#define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET       0x0420
+#define OMAP4_SCRM_EXTPWRONRSTCTRL              OMAP44XX_SCRM_REGADDR(0x0420)
+#define OMAP4_SCRM_EXTWARMRSTST_OFFSET          0x0510
+#define OMAP4_SCRM_EXTWARMRSTST                 OMAP44XX_SCRM_REGADDR(0x0510)
+#define OMAP4_SCRM_APEWARMRSTST_OFFSET          0x0514
+#define OMAP4_SCRM_APEWARMRSTST                 OMAP44XX_SCRM_REGADDR(0x0514)
+#define OMAP4_SCRM_MODEMWARMRSTST_OFFSET        0x0518
+#define OMAP4_SCRM_MODEMWARMRSTST               OMAP44XX_SCRM_REGADDR(0x0518)
+#define OMAP4_SCRM_D2DWARMRSTST_OFFSET          0x051c
+#define OMAP4_SCRM_D2DWARMRSTST                 OMAP44XX_SCRM_REGADDR(0x051c)
+
+/* Registers shifts and masks */
+
+/* REVISION_SCRM */
+#define OMAP4_REV_SHIFT                         0
+#define OMAP4_REV_MASK                          (0xff << 0)
+
+/* CLKSETUPTIME */
+#define OMAP4_DOWNTIME_SHIFT                    16
+#define OMAP4_DOWNTIME_MASK                     (0x3f << 16)
+#define OMAP4_SETUPTIME_SHIFT                   0
+#define OMAP4_SETUPTIME_MASK                    (0xfff << 0)
+
+/* PMICSETUPTIME */
+#define OMAP4_WAKEUPTIME_SHIFT                  16
+#define OMAP4_WAKEUPTIME_MASK                   (0x3f << 16)
+#define OMAP4_SLEEPTIME_SHIFT                   0
+#define OMAP4_SLEEPTIME_MASK                    (0x3f << 0)
+
+/* ALTCLKSRC */
+#define OMAP4_ENABLE_EXT_SHIFT                  3
+#define OMAP4_ENABLE_EXT_MASK                   (1 << 3)
+#define OMAP4_ENABLE_INT_SHIFT                  2
+#define OMAP4_ENABLE_INT_MASK                   (1 << 2)
+#define OMAP4_ALTCLKSRC_MODE_SHIFT              0
+#define OMAP4_ALTCLKSRC_MODE_MASK               (0x3 << 0)
+
+/* MODEMCLKM */
+#define OMAP4_CLK_32KHZ_SHIFT                   0
+#define OMAP4_CLK_32KHZ_MASK                    (1 << 0)
+
+/* D2DCLKM */
+#define OMAP4_SYSCLK_SHIFT                      1
+#define OMAP4_SYSCLK_MASK                       (1 << 1)
+
+/* EXTCLKREQ */
+#define OMAP4_POLARITY_SHIFT                    0
+#define OMAP4_POLARITY_MASK                     (1 << 0)
+
+/* AUXCLKREQ0 */
+#define OMAP4_MAPPING_SHIFT                     2
+#define OMAP4_MAPPING_MASK                      (0x7 << 2)
+#define OMAP4_ACCURACY_SHIFT                    1
+#define OMAP4_ACCURACY_MASK                     (1 << 1)
+
+/* AUXCLK0 */
+#define OMAP4_CLKDIV_SHIFT                      16
+#define OMAP4_CLKDIV_MASK                       (0xf << 16)
+#define OMAP4_DISABLECLK_SHIFT                  9
+#define OMAP4_DISABLECLK_MASK                   (1 << 9)
+#define OMAP4_ENABLE_SHIFT                      8
+#define OMAP4_ENABLE_MASK                       (1 << 8)
+#define OMAP4_SRCSELECT_SHIFT                   1
+#define OMAP4_SRCSELECT_MASK                    (0x3 << 1)
+
+/* RSTTIME */
+#define OMAP4_RSTTIME_SHIFT                     0
+#define OMAP4_RSTTIME_MASK                      (0xf << 0)
+
+/* MODEMRSTCTRL */
+#define OMAP4_WARMRST_SHIFT                     1
+#define OMAP4_WARMRST_MASK                      (1 << 1)
+#define OMAP4_COLDRST_SHIFT                     0
+#define OMAP4_COLDRST_MASK                      (1 << 0)
+
+/* EXTPWRONRSTCTRL */
+#define OMAP4_PWRONRST_SHIFT                    1
+#define OMAP4_PWRONRST_MASK                     (1 << 1)
+#define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT      0
+#define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK       (1 << 0)
+
+/* EXTWARMRSTST */
+#define OMAP4_EXTWARMRSTST_SHIFT                0
+#define OMAP4_EXTWARMRSTST_MASK                 (1 << 0)
+
+/* APEWARMRSTST */
+#define OMAP4_APEWARMRSTST_SHIFT                1
+#define OMAP4_APEWARMRSTST_MASK                 (1 << 1)
+
+/* MODEMWARMRSTST */
+#define OMAP4_MODEMWARMRSTST_SHIFT              2
+#define OMAP4_MODEMWARMRSTST_MASK               (1 << 2)
+
+/* D2DWARMRSTST */
+#define OMAP4_D2DWARMRSTST_SHIFT                3
+#define OMAP4_D2DWARMRSTST_MASK                 (1 << 3)
+
+#endif
diff --git a/arch/arm/mach-omap2/board-rx51-sdram.c b/arch/arm/mach-omap2/sdram-nokia.c
index a43b2c5c838b..14caa228bc0d 100644
--- a/arch/arm/mach-omap2/board-rx51-sdram.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -1,7 +1,7 @@
 /*
- * SDRC register values for RX51
+ * SDRC register values for Nokia boards
  *
- * Copyright (C) 2008 Nokia Corporation
+ * Copyright (C) 2008, 2010 Nokia Corporation
  *
  * Lauri Leukkunen <lauri.leukkunen@nokia.com>
  *
@@ -22,6 +22,7 @@
 #include <plat/clock.h>
 #include <plat/sdrc.h>
 
+#include "sdram-nokia.h"
 
 /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
 struct sdram_timings {
@@ -43,9 +44,28 @@ struct sdram_timings {
         u32 tWTR;
 };
 
-static struct omap_sdrc_params rx51_sdrc_params[4];
+static const struct sdram_timings nokia_97dot6mhz_timings[] = {
+        {
+                .casl = 3,
+                .tDAL = 30725,
+                .tDPL = 15362,
+                .tRRD = 10241,
+                .tRCD = 20483,
+                .tRP = 15362,
+                .tRAS = 40967,
+                .tRC = 56330,
+                .tRFC = 138266,
+                .tXSR = 204839,
+
+                .tREF = 7798,
+
+                .tXP = 2,
+                .tCKE = 4,
+                .tWTR = 2,
+        },
+};
 
-static const struct sdram_timings rx51_timings[] = {
+static const struct sdram_timings nokia_166mhz_timings[] = {
         {
                 .casl = 3,
                 .tDAL = 33000,
@@ -66,6 +86,38 @@ static const struct sdram_timings rx51_timings[] = {
         },
 };
 
+static const struct sdram_timings nokia_195dot2mhz_timings[] = {
+        {
+                .casl = 3,
+                .tDAL = 30725,
+                .tDPL = 15362,
+                .tRRD = 10241,
+                .tRCD = 20483,
+                .tRP = 15362,
+                .tRAS = 40967,
+                .tRC = 56330,
+                .tRFC = 138266,
+                .tXSR = 204839,
+
+                .tREF = 7752,
+
+                .tXP = 2,
+                .tCKE = 4,
+                .tWTR = 2,
+        },
+};
+
+static const struct {
+        long rate;
+        struct sdram_timings const *data;
+} nokia_timings[] = {
+        { 83000000, nokia_166mhz_timings },
+        { 97600000, nokia_97dot6mhz_timings },
+        { 166000000, nokia_166mhz_timings },
+        { 195200000, nokia_195dot2mhz_timings },
+};
+static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
+
 static unsigned long sdrc_get_fclk_period(long rate)
 {
         /* In picoseconds */
@@ -110,12 +162,12 @@ static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
 #ifdef DEBUG
 #define SDRC_SET_ONE(reg, st, end, field, rate) \
         if (set_sdrc_timing_regval((reg), (st), (end), \
-                        rx51_timings->field, (rate), #field) < 0) \
+                        memory_timings->field, (rate), #field) < 0) \
                 err = -1;
 #else
 #define SDRC_SET_ONE(reg, st, end, field, rate) \
         if (set_sdrc_timing_regval((reg), (st), (end), \
-                        rx51_timings->field) < 0) \
+                        memory_timings->field) < 0) \
                 err = -1;
 #endif
 
@@ -148,18 +200,19 @@ static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
 #ifdef DEBUG
 #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
         if (set_sdrc_timing_regval_ps((reg), (st), (end), \
-                        rx51_timings->field, \
+                        memory_timings->field, \
                         (rate), #field) < 0) \
                 err = -1;
 
 #else
 #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
         if (set_sdrc_timing_regval_ps((reg), (st), (end), \
-                        rx51_timings->field, (rate)) < 0) \
+                        memory_timings->field, (rate)) < 0) \
                 err = -1;
 #endif
 
-static int sdrc_timings(int id, long rate)
+static int sdrc_timings(int id, long rate,
+                        const struct sdram_timings *memory_timings)
 {
         u32 ticks_per_ms;
         u32 rfr, l;
@@ -184,7 +237,7 @@ static int sdrc_timings(int id, long rate)
         SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate);
 
         ticks_per_ms = l3_rate;
-        rfr = rx51_timings[0].tREF * ticks_per_ms / 1000000;
+        rfr = memory_timings[0].tREF * ticks_per_ms / 1000000;
         if (rfr > 65535 + 50)
                 rfr = 65535;
         else
@@ -197,25 +250,30 @@ static int sdrc_timings(int id, long rate)
         l = rfr << 8;
         rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */
 
-        rx51_sdrc_params[id].rate = rate;
-        rx51_sdrc_params[id].actim_ctrla = actim_ctrla;
-        rx51_sdrc_params[id].actim_ctrlb = actim_ctrlb;
-        rx51_sdrc_params[id].rfr_ctrl = rfr_ctrl;
-        rx51_sdrc_params[id].mr = 0x32;
+        nokia_sdrc_params[id].rate = rate;
+        nokia_sdrc_params[id].actim_ctrla = actim_ctrla;
+        nokia_sdrc_params[id].actim_ctrlb = actim_ctrlb;
+        nokia_sdrc_params[id].rfr_ctrl = rfr_ctrl;
+        nokia_sdrc_params[id].mr = 0x32;
 
-        rx51_sdrc_params[id + 1].rate = 0;
+        nokia_sdrc_params[id + 1].rate = 0;
 
         return err;
 }
 
-struct omap_sdrc_params *rx51_get_sdram_timings(void)
+struct omap_sdrc_params *nokia_get_sdram_timings(void)
 {
-        int err;
+        int err = 0;
+        int i;
 
-        err = sdrc_timings(0, 41500000);
-        err |= sdrc_timings(1, 83000000);
-        err |= sdrc_timings(2, 166000000);
+        for (i = 0; i < ARRAY_SIZE(nokia_timings); i++) {
+                err |= sdrc_timings(i, nokia_timings[i].rate,
+                                       nokia_timings[i].data);
+                if (err)
+                        pr_err("%s: error with rate %ld: %d\n", __func__,
+                               nokia_timings[i].rate, err);
+        }
 
-        return &rx51_sdrc_params[0];
+        return err ? NULL : nokia_sdrc_params;
 }
 
diff --git a/arch/arm/mach-omap2/sdram-nokia.h b/arch/arm/mach-omap2/sdram-nokia.h
new file mode 100644
index 000000000000..ee63da5f8df0
--- /dev/null
+++ b/arch/arm/mach-omap2/sdram-nokia.h
@@ -0,0 +1,12 @@
+/*
+ * SDRC register values for Nokia boards
+ *
+ * Copyright (C) 2010 Nokia
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+struct omap_sdrc_params *nokia_get_sdram_timings(void);
+
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 4c65f5628b39..da6f3a63b5d5 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -27,8 +27,6 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 
-#include "prm.h"
-
 #include <plat/sdrc.h>
 #include "sdrc.h"
 
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 68f57bb67fc5..b3f83799e6cf 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -74,5 +74,4 @@ static inline u32 sms_read_reg(u16 reg)
  */
 #define SDRC_MPURATE_LOOPS              96
 
-
 #endif
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 0f4d27aef44d..ccdb010f169d 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -28,7 +28,7 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "clock.h"
 #include <plat/sdrc.h>
 #include "sdrc.h"
@@ -99,6 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
         m_type = omap2xxx_sdrc_get_type();
 
         local_irq_save(flags);
+        /*
+         * XXX These calls should be abstracted out through a
+         * prm2xxx.c function
+         */
         if (cpu_is_omap2420())
                 __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
         else
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index d17960a1be25..c64578853a8d 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -40,11 +40,12 @@
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 
-#include "prm.h"
+#include "prm2xxx_3xxx.h"
 #include "pm.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 #include "prm-regbits-34xx.h"
 #include "control.h"
+#include "mux.h"
 
 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
@@ -106,21 +107,16 @@ struct omap_uart_state {
 static LIST_HEAD(uart_list);
 static u8 num_uarts;
 
-/*
- * Since these idle/enable hooks are used in the idle path itself
- * which has interrupts disabled, use the non-locking versions of
- * the hwmod enable/disable functions.
- */
 static int uart_idle_hwmod(struct omap_device *od)
 {
-        _omap_hwmod_idle(od->hwmods[0]);
+        omap_hwmod_idle(od->hwmods[0]);
 
         return 0;
 }
 
 static int uart_enable_hwmod(struct omap_device *od)
 {
-        _omap_hwmod_enable(od->hwmods[0]);
+        omap_hwmod_enable(od->hwmods[0]);
 
         return 0;
 }
@@ -169,9 +165,9 @@ static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
 
 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 {
-        serial_write_reg(uart, UART_OMAP_MDR1, 0x07);
+        serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
         serial_write_reg(uart, UART_OMAP_SCR, 0x08);
-        serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
+        serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
 }
 
 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
@@ -219,7 +215,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
                 return;
 
         lcr = serial_read_reg(uart, UART_LCR);
-        serial_write_reg(uart, UART_LCR, 0xBF);
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
         uart->dll = serial_read_reg(uart, UART_DLL);
         uart->dlh = serial_read_reg(uart, UART_DLM);
         serial_write_reg(uart, UART_LCR, lcr);
@@ -227,7 +223,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
         uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
         uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
         uart->wer = serial_read_reg(uart, UART_OMAP_WER);
-        serial_write_reg(uart, UART_LCR, 0x80);
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
         uart->mcr = serial_read_reg(uart, UART_MCR);
         serial_write_reg(uart, UART_LCR, lcr);
 
@@ -247,32 +243,35 @@ static void omap_uart_restore_context(struct omap_uart_state *uart)
         uart->context_valid = 0;
 
         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
-                omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
+                omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
         else
-                serial_write_reg(uart, UART_OMAP_MDR1, 0x7);
-        serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+                serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
         efr = serial_read_reg(uart, UART_EFR);
         serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
         serial_write_reg(uart, UART_IER, 0x0);
-        serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
         serial_write_reg(uart, UART_DLL, uart->dll);
         serial_write_reg(uart, UART_DLM, uart->dlh);
         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
         serial_write_reg(uart, UART_IER, uart->ier);
-        serial_write_reg(uart, UART_LCR, 0x80);
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
         serial_write_reg(uart, UART_MCR, uart->mcr);
-        serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */
+        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
         serial_write_reg(uart, UART_EFR, efr);
         serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
         serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
         serial_write_reg(uart, UART_OMAP_WER, uart->wer);
         serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
+
         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
-                omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
+                omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
         else
                 /* UART 16x mode */
-                serial_write_reg(uart, UART_OMAP_MDR1, 0x00);
+                serial_write_reg(uart, UART_OMAP_MDR1,
+                                UART_OMAP_MDR1_16X_MODE);
 }
 #else
 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
@@ -492,6 +491,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 u32 wk_mask = 0;
                 u32 padconf = 0;
 
+                /* XXX These PRM accesses do not belong here */
                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
                 switch (uart->num) {
@@ -695,16 +695,16 @@ void __init omap_serial_early_init(void)
 
 /**
  * omap_serial_init_port() - initialize single serial port
- * @port: serial port number (0-3)
+ * @bdata: port specific board data pointer
  *
- * This function initialies serial driver for given @port only.
+ * This function initialies serial driver for given port only.
  * Platforms can call this function instead of omap_serial_init()
  * if they don't plan to use all available UARTs as serial ports.
  *
  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
  * use only one of the two.
  */
-void __init omap_serial_init_port(int port)
+void __init omap_serial_init_port(struct omap_board_data *bdata)
 {
         struct omap_uart_state *uart;
         struct omap_hwmod *oh;
@@ -722,13 +722,15 @@ void __init omap_serial_init_port(int port)
         struct omap_uart_port_info omap_up;
 #endif
 
-        if (WARN_ON(port < 0))
+        if (WARN_ON(!bdata))
+                return;
+        if (WARN_ON(bdata->id < 0))
                 return;
-        if (WARN_ON(port >= num_uarts))
+        if (WARN_ON(bdata->id >= num_uarts))
                 return;
 
         list_for_each_entry(uart, &uart_list, node)
-                if (port == uart->num)
+                if (bdata->id == uart->num)
                         break;
 
         oh = uart->oh;
@@ -800,6 +802,8 @@ void __init omap_serial_init_port(int port)
         WARN(IS_ERR(od), "Could not build omap_device for %s: %s.\n",
              name, oh->name);
 
+        oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
+
         uart->irq = oh->mpu_irqs[0].irq;
         uart->regshift = 2;
         uart->mapbase = oh->slaves[0]->addr->pa_start;
@@ -857,7 +861,14 @@ void __init omap_serial_init_port(int port)
 void __init omap_serial_init(void)
 {
         struct omap_uart_state *uart;
+        struct omap_board_data bdata;
 
-        list_for_each_entry(uart, &uart_list, node)
-                omap_serial_init_port(uart->num);
+        list_for_each_entry(uart, &uart_list, node) {
+                bdata.id = uart->num;
+                bdata.flags = 0;
+                bdata.pads = NULL;
+                bdata.pads_cnt = 0;
+                omap_serial_init_port(&bdata);
+
+        }
 }
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 2fb205a7f285..98d8232808b8 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -1,6 +1,4 @@
 /*
- * linux/arch/arm/mach-omap2/sleep.S
- *
  * (C) Copyright 2007
  * Texas Instruments
  * Karthik Dasu <karthik-dp@ti.com>
@@ -26,28 +24,35 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#include <plat/sram.h>
 #include <mach/io.h>
 
-#include "cm.h"
-#include "prm.h"
+#include "cm2xxx_3xxx.h"
+#include "prm2xxx_3xxx.h"
 #include "sdrc.h"
 #include "control.h"
 
-#define SDRC_SCRATCHPAD_SEM_V   0xfa00291c
-
-#define PM_PREPWSTST_CORE_V     OMAP34XX_PRM_REGADDR(CORE_MOD, \
-                                OMAP3430_PM_PREPWSTST)
-#define PM_PREPWSTST_CORE_P     0x48306AE8
-#define PM_PREPWSTST_MPU_V      OMAP34XX_PRM_REGADDR(MPU_MOD, \
-                                OMAP3430_PM_PREPWSTST)
+/*
+ * Registers access definitions
+ */
+#define SDRC_SCRATCHPAD_SEM_OFFS        0xc
+#define SDRC_SCRATCHPAD_SEM_V   OMAP343X_SCRATCHPAD_REGADDR\
+                                        (SDRC_SCRATCHPAD_SEM_OFFS)
+#define PM_PREPWSTST_CORE_P     OMAP3430_PRM_BASE + CORE_MOD +\
+                                        OMAP3430_PM_PREPWSTST
 #define PM_PWSTCTRL_MPU_P       OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
 #define CM_IDLEST1_CORE_V       OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
-#define SRAM_BASE_P             0x40200000
-#define CONTROL_STAT            0x480022F0
-#define SCRATCHPAD_MEM_OFFS     0x310 /* Move this as correct place is
-                                       * available */
-#define SCRATCHPAD_BASE_P       (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
-                                                + SCRATCHPAD_MEM_OFFS)
+#define CM_IDLEST_CKGEN_V       OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
+#define SRAM_BASE_P             OMAP3_SRAM_PA
+#define CONTROL_STAT            OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
+#define CONTROL_MEM_RTA_CTRL    (OMAP343X_CTRL_BASE +\
+                                        OMAP36XX_CONTROL_MEM_RTA_CTRL)
+
+/* Move this as correct place is available */
+#define SCRATCHPAD_MEM_OFFS     0x310
+#define SCRATCHPAD_BASE_P       (OMAP343X_CTRL_BASE +\
+                                        OMAP343X_CONTROL_MEM_WKUP +\
+                                        SCRATCHPAD_MEM_OFFS)
 #define SDRC_POWER_V            OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 #define SDRC_SYSCONFIG_P        (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
 #define SDRC_MR_0_P             (OMAP343X_SDRC_BASE + SDRC_MR_0)
@@ -59,48 +64,38 @@
 #define SDRC_DLLA_STATUS_V      OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 #define SDRC_DLLA_CTRL_V        OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 
-        .text
-/* Function to acquire the semaphore in scratchpad */
-ENTRY(lock_scratchpad_sem)
-        stmfd   sp!, {lr}       @ save registers on stack
-wait_sem:
-        mov     r0,#1
-        ldr     r1, sdrc_scratchpad_sem
-wait_loop:
-        ldr     r2, [r1]        @ load the lock value
-        cmp     r2, r0          @ is the lock free ?
-        beq     wait_loop       @ not free...
-        swp     r2, r0, [r1]    @ semaphore free so lock it and proceed
-        cmp     r2, r0          @ did we succeed ?
-        beq     wait_sem        @ no - try again
-        ldmfd   sp!, {pc}       @ restore regs and return
-sdrc_scratchpad_sem:
-        .word SDRC_SCRATCHPAD_SEM_V
-ENTRY(lock_scratchpad_sem_sz)
-        .word   . - lock_scratchpad_sem
-
-        .text
-/* Function to release the scratchpad semaphore */
-ENTRY(unlock_scratchpad_sem)
-        stmfd   sp!, {lr}       @ save registers on stack
-        ldr     r3, sdrc_scratchpad_sem
-        mov     r2,#0
-        str     r2,[r3]
-        ldmfd   sp!, {pc}       @ restore regs and return
-ENTRY(unlock_scratchpad_sem_sz)
-        .word   . - unlock_scratchpad_sem
+
+/*
+ * API functions
+ */
+
+/*
+ * The "get_*restore_pointer" functions are used to provide a
+ * physical restore address where the ROM code jumps while waking
+ * up from MPU OFF/OSWR state.
+ * The restore pointer is stored into the scratchpad.
+ */
 
         .text
 /* Function call to get the restore pointer for resume from OFF */
 ENTRY(get_restore_pointer)
-        stmfd   sp!, {lr}     @ save registers on stack
+        stmfd   sp!, {lr}       @ save registers on stack
         adr     r0, restore
-        ldmfd   sp!, {pc}     @ restore regs and return
+        ldmfd   sp!, {pc}       @ restore regs and return
 ENTRY(get_restore_pointer_sz)
-        .word   . - get_restore_pointer
+        .word   . - get_restore_pointer
 
         .text
-/* Function call to get the restore pointer for for ES3 to resume from OFF */
+/* Function call to get the restore pointer for 3630 resume from OFF */
+ENTRY(get_omap3630_restore_pointer)
+        stmfd   sp!, {lr}       @ save registers on stack
+        adr     r0, restore_3630
+        ldmfd   sp!, {pc}       @ restore regs and return
+ENTRY(get_omap3630_restore_pointer_sz)
+        .word   . - get_omap3630_restore_pointer
+
+        .text
+/* Function call to get the restore pointer for ES3 to resume from OFF */
 ENTRY(get_es3_restore_pointer)
         stmfd   sp!, {lr}       @ save registers on stack
         adr     r0, restore_es3
@@ -108,54 +103,23 @@ ENTRY(get_es3_restore_pointer)
 ENTRY(get_es3_restore_pointer_sz)
         .word   . - get_es3_restore_pointer
 
-ENTRY(es3_sdrc_fix)
-        ldr     r4, sdrc_syscfg         @ get config addr
-        ldr     r5, [r4]                @ get value
-        tst     r5, #0x100              @ is part access blocked
-        it      eq
-        biceq   r5, r5, #0x100          @ clear bit if set
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_mr_0           @ get config addr
-        ldr     r5, [r4]                @ get value
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_emr2_0         @ get config addr
-        ldr     r5, [r4]                @ get value
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_manual_0       @ get config addr
-        mov     r5, #0x2                @ autorefresh command
-        str     r5, [r4]                @ kick off refreshes
-        ldr     r4, sdrc_mr_1           @ get config addr
-        ldr     r5, [r4]                @ get value
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_emr2_1         @ get config addr
-        ldr     r5, [r4]                @ get value
-        str     r5, [r4]                @ write back change
-        ldr     r4, sdrc_manual_1       @ get config addr
-        mov     r5, #0x2                @ autorefresh command
-        str     r5, [r4]                @ kick off refreshes
-        bx      lr
-sdrc_syscfg:
-        .word   SDRC_SYSCONFIG_P
-sdrc_mr_0:
-        .word   SDRC_MR_0_P
-sdrc_emr2_0:
-        .word   SDRC_EMR2_0_P
-sdrc_manual_0:
-        .word   SDRC_MANUAL_0_P
-sdrc_mr_1:
-        .word   SDRC_MR_1_P
-sdrc_emr2_1:
-        .word   SDRC_EMR2_1_P
-sdrc_manual_1:
-        .word   SDRC_MANUAL_1_P
-ENTRY(es3_sdrc_fix_sz)
-        .word   . - es3_sdrc_fix
+        .text
+/*
+ * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
+ * This function sets up a flag that will allow for this toggling to take
+ * place on 3630. Hopefully some version in the future may not need this.
+ */
+ENTRY(enable_omap3630_toggle_l2_on_restore)
+        stmfd   sp!, {lr}       @ save registers on stack
+        /* Setup so that we will disable and enable l2 */
+        mov     r1, #0x1
+        str     r1, l2dis_3630
+        ldmfd   sp!, {pc}       @ restore regs and return
 
+        .text
 /* Function to call rom code to save secure ram context */
 ENTRY(save_secure_ram_context)
         stmfd   sp!, {r1-r12, lr}       @ save registers on stack
-save_secure_ram_debug:
-        /* b save_secure_ram_debug */   @ enable to debug save code
         adr     r3, api_params          @ r3 points to parameters
         str     r0, [r3,#0x4]           @ r0 has sdram address
         ldr     r12, high_mask
@@ -185,35 +149,162 @@ ENTRY(save_secure_ram_context_sz)
         .word   . - save_secure_ram_context
 
 /*
+ * ======================
+ * == Idle entry point ==
+ * ======================
+ */
+
+/*
  * Forces OMAP into idle state
  *
- * omap34xx_suspend() - This bit of code just executes the WFI
- * for normal idles.
+ * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
+ * and executes the WFI instruction. Calling WFI effectively changes the
+ * power domains states to the desired target power states.
+ *
  *
- * Note: This code get's copied to internal SRAM at boot. When the OMAP
- *       wakes up it continues execution at the point it went to sleep.
+ * Notes:
+ * - this code gets copied to internal SRAM at boot and after wake-up
+ *   from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
+ * - when the OMAP wakes up it continues at different execution points
+ *   depending on the low power mode (non-OFF vs OFF modes),
+ *   cf. 'Resume path for xxx mode' comments.
  */
 ENTRY(omap34xx_cpu_suspend)
-        stmfd   sp!, {r0-r12, lr}               @ save registers on stack
-loop:
-        /*b     loop*/  @Enable to debug by stepping through code
-        /* r0 contains restore pointer in sdram */
-        /* r1 contains information about saving context */
-        ldr     r4, sdrc_power          @ read the SDRC_POWER register
-        ldr     r5, [r4]                @ read the contents of SDRC_POWER
-        orr     r5, r5, #0x40           @ enable self refresh on idle req
-        str     r5, [r4]                @ write back to SDRC_POWER register
+        stmfd   sp!, {r0-r12, lr}       @ save registers on stack
 
+        /*
+         * r0 contains restore pointer in sdram
+         * r1 contains information about saving context:
+         *   0 - No context lost
+         *   1 - Only L1 and logic lost
+         *   2 - Only L2 lost
+         *   3 - Both L1 and L2 lost
+         */
+
+        /* Directly jump to WFI is the context save is not required */
         cmp     r1, #0x0
-        /* If context save is required, do that and execute wfi */
-        bne     save_context_wfi
+        beq     omap3_do_wfi
+
+        /* Otherwise fall through to the save context code */
+save_context_wfi:
+        mov     r8, r0                  @ Store SDRAM address in r8
+        mrc     p15, 0, r5, c1, c0, 1   @ Read Auxiliary Control Register
+        mov     r4, #0x1                @ Number of parameters for restore call
+        stmia   r8!, {r4-r5}            @ Push parameters for restore call
+        mrc     p15, 1, r5, c9, c0, 2   @ Read L2 AUX ctrl register
+        stmia   r8!, {r4-r5}            @ Push parameters for restore call
+
+        /* Check what that target sleep state is from r1 */
+        cmp     r1, #0x2                @ Only L2 lost, no need to save context
+        beq     clean_caches
+
+l1_logic_lost:
+        /* Store sp and spsr to SDRAM */
+        mov     r4, sp
+        mrs     r5, spsr
+        mov     r6, lr
+        stmia   r8!, {r4-r6}
+        /* Save all ARM registers */
+        /* Coprocessor access control register */
+        mrc     p15, 0, r6, c1, c0, 2
+        stmia   r8!, {r6}
+        /* TTBR0, TTBR1 and Translation table base control */
+        mrc     p15, 0, r4, c2, c0, 0
+        mrc     p15, 0, r5, c2, c0, 1
+        mrc     p15, 0, r6, c2, c0, 2
+        stmia   r8!, {r4-r6}
+        /*
+         * Domain access control register, data fault status register,
+         * and instruction fault status register
+         */
+        mrc     p15, 0, r4, c3, c0, 0
+        mrc     p15, 0, r5, c5, c0, 0
+        mrc     p15, 0, r6, c5, c0, 1
+        stmia   r8!, {r4-r6}
+        /*
+         * Data aux fault status register, instruction aux fault status,
+         * data fault address register and instruction fault address register
+         */
+        mrc     p15, 0, r4, c5, c1, 0
+        mrc     p15, 0, r5, c5, c1, 1
+        mrc     p15, 0, r6, c6, c0, 0
+        mrc     p15, 0, r7, c6, c0, 2
+        stmia   r8!, {r4-r7}
+        /*
+         * user r/w thread and process ID, user r/o thread and process ID,
+         * priv only thread and process ID, cache size selection
+         */
+        mrc     p15, 0, r4, c13, c0, 2
+        mrc     p15, 0, r5, c13, c0, 3
+        mrc     p15, 0, r6, c13, c0, 4
+        mrc     p15, 2, r7, c0, c0, 0
+        stmia   r8!, {r4-r7}
+        /* Data TLB lockdown, instruction TLB lockdown registers */
+        mrc     p15, 0, r5, c10, c0, 0
+        mrc     p15, 0, r6, c10, c0, 1
+        stmia   r8!, {r5-r6}
+        /* Secure or non secure vector base address, FCSE PID, Context PID*/
+        mrc     p15, 0, r4, c12, c0, 0
+        mrc     p15, 0, r5, c13, c0, 0
+        mrc     p15, 0, r6, c13, c0, 1
+        stmia   r8!, {r4-r6}
+        /* Primary remap, normal remap registers */
+        mrc     p15, 0, r4, c10, c2, 0
+        mrc     p15, 0, r5, c10, c2, 1
+        stmia   r8!,{r4-r5}
+
+        /* Store current cpsr*/
+        mrs     r2, cpsr
+        stmia   r8!, {r2}
+
+        mrc     p15, 0, r4, c1, c0, 0
+        /* save control register */
+        stmia   r8!, {r4}
+
+clean_caches:
+        /*
+         * Clean Data or unified cache to POU
+         * How to invalidate only L1 cache???? - #FIX_ME#
+         * mcr  p15, 0, r11, c7, c11, 1
+         */
+        cmp     r1, #0x1                @ Check whether L2 inval is required
+        beq     omap3_do_wfi
+
+clean_l2:
+        /*
+         * jump out to kernel flush routine
+         *  - reuse that code is better
+         *  - it executes in a cached space so is faster than refetch per-block
+         *  - should be faster and will change with kernel
+         *  - 'might' have to copy address, load and jump to it
+         */
+        ldr     r1, kernel_flush
+        mov     lr, pc
+        bx      r1
+
+omap3_do_wfi:
+        ldr     r4, sdrc_power          @ read the SDRC_POWER register
+        ldr     r5, [r4]                @ read the contents of SDRC_POWER
+        orr     r5, r5, #0x40           @ enable self refresh on idle req
+        str     r5, [r4]                @ write back to SDRC_POWER register
+
         /* Data memory barrier and Data sync barrier */
         mov     r1, #0
         mcr     p15, 0, r1, c7, c10, 4
         mcr     p15, 0, r1, c7, c10, 5
 
+/*
+ * ===================================
+ * == WFI instruction => Enter idle ==
+ * ===================================
+ */
         wfi                             @ wait for interrupt
 
+/*
+ * ===================================
+ * == Resume path for non-OFF modes ==
+ * ===================================
+ */
         nop
         nop
         nop
@@ -226,9 +317,30 @@ loop:
         nop
         bl wait_sdrc_ok
 
-        ldmfd   sp!, {r0-r12, pc}               @ restore regs and return
+/*
+ * ===================================
+ * == Exit point from non-OFF modes ==
+ * ===================================
+ */
+        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
+
+
+/*
+ * ==============================
+ * == Resume path for OFF mode ==
+ * ==============================
+ */
+
+/*
+ * The restore_* functions are called by the ROM code
+ *  when back from WFI in OFF mode.
+ * Cf. the get_*restore_pointer functions.
+ *
+ *  restore_es3: applies to 34xx >= ES3.0
+ *  restore_3630: applies to 36xx
+ *  restore: common code for 3xxx
+ */
 restore_es3:
-        /*b restore_es3*/               @ Enable to debug restore code
         ldr     r5, pm_prepwstst_core_p
         ldr     r4, [r5]
         and     r4, r4, #0x3
@@ -245,82 +357,117 @@ copy_to_sram:
         bne     copy_to_sram
         ldr     r1, sram_base
         blx     r1
+        b       restore
+
+restore_3630:
+        ldr     r1, pm_prepwstst_core_p
+        ldr     r2, [r1]
+        and     r2, r2, #0x3
+        cmp     r2, #0x0        @ Check if previous power state of CORE is OFF
+        bne     restore
+        /* Disable RTA before giving control */
+        ldr     r1, control_mem_rta
+        mov     r2, #OMAP36XX_RTA_DISABLE
+        str     r2, [r1]
+
+        /* Fall through to common code for the remaining logic */
+
 restore:
-        /* b restore*/  @ Enable to debug restore code
-        /* Check what was the reason for mpu reset and store the reason in r9*/
-        /* 1 - Only L1 and logic lost */
-        /* 2 - Only L2 lost - In this case, we wont be here */
-        /* 3 - Both L1 and L2 lost */
-        ldr     r1, pm_pwstctrl_mpu
+        /*
+         * Check what was the reason for mpu reset and store the reason in r9:
+         *  0 - No context lost
+         *  1 - Only L1 and logic lost
+         *  2 - Only L2 lost - In this case, we wont be here
+         *  3 - Both L1 and L2 lost
+         */
+        ldr     r1, pm_pwstctrl_mpu
         ldr     r2, [r1]
-        and     r2, r2, #0x3
-        cmp     r2, #0x0        @ Check if target power state was OFF or RET
-        moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
+        and     r2, r2, #0x3
+        cmp     r2, #0x0        @ Check if target power state was OFF or RET
+        moveq   r9, #0x3        @ MPU OFF => L1 and L2 lost
         movne   r9, #0x1        @ Only L1 and L2 lost => avoid L2 invalidation
         bne     logic_l1_restore
+
+        ldr     r0, l2dis_3630
+        cmp     r0, #0x1        @ should we disable L2 on 3630?
+        bne     skipl2dis
+        mrc     p15, 0, r0, c1, c0, 1
+        bic     r0, r0, #2      @ disable L2 cache
+        mcr     p15, 0, r0, c1, c0, 1
+skipl2dis:
         ldr     r0, control_stat
         ldr     r1, [r0]
         and     r1, #0x700
         cmp     r1, #0x300
         beq     l2_inv_gp
-        mov     r0, #40         @ set service ID for PPA
-        mov     r12, r0         @ copy secure Service ID in r12
-        mov     r1, #0          @ set task id for ROM code in r1
-        mov     r2, #4          @ set some flags in r2, r6
+        mov     r0, #40                 @ set service ID for PPA
+        mov     r12, r0                 @ copy secure Service ID in r12
+        mov     r1, #0                  @ set task id for ROM code in r1
+        mov     r2, #4                  @ set some flags in r2, r6
         mov     r6, #0xff
         adr     r3, l2_inv_api_params   @ r3 points to dummy parameters
         mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
         mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
         .word   0xE1600071              @ call SMI monitor (smi #1)
         /* Write to Aux control register to set some bits */
-        mov     r0, #42         @ set service ID for PPA
-        mov     r12, r0         @ copy secure Service ID in r12
-        mov     r1, #0          @ set task id for ROM code in r1
-        mov     r2, #4          @ set some flags in r2, r6
+        mov     r0, #42                 @ set service ID for PPA
+        mov     r12, r0                 @ copy secure Service ID in r12
+        mov     r1, #0                  @ set task id for ROM code in r1
+        mov     r2, #4                  @ set some flags in r2, r6
         mov     r6, #0xff
         ldr     r4, scratchpad_base
-        ldr     r3, [r4, #0xBC] @ r3 points to parameters
+        ldr     r3, [r4, #0xBC]         @ r3 points to parameters
         mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
         mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
         .word   0xE1600071              @ call SMI monitor (smi #1)
 
 #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
         /* Restore L2 aux control register */
-        @ set service ID for PPA
+                                        @ set service ID for PPA
         mov     r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
-        mov     r12, r0         @ copy service ID in r12
-        mov     r1, #0          @ set task ID for ROM code in r1
-        mov     r2, #4          @ set some flags in r2, r6
+        mov     r12, r0                 @ copy service ID in r12
+        mov     r1, #0                  @ set task ID for ROM code in r1
+        mov     r2, #4                  @ set some flags in r2, r6
         mov     r6, #0xff
         ldr     r4, scratchpad_base
         ldr     r3, [r4, #0xBC]
-        adds    r3, r3, #8      @ r3 points to parameters
+        adds    r3, r3, #8              @ r3 points to parameters
         mcr     p15, 0, r0, c7, c10, 4  @ data write barrier
         mcr     p15, 0, r0, c7, c10, 5  @ data memory barrier
         .word   0xE1600071              @ call SMI monitor (smi #1)
 #endif
         b       logic_l1_restore
+
 l2_inv_api_params:
-        .word   0x1, 0x00
+        .word   0x1, 0x00
 l2_inv_gp:
         /* Execute smi to invalidate L2 cache */
-        mov r12, #0x1                         @ set up to invalide L2
-smi:    .word 0xE1600070                @ Call SMI monitor (smieq)
+        mov r12, #0x1                   @ set up to invalidate L2
+        .word 0xE1600070                @ Call SMI monitor (smieq)
         /* Write to Aux control register to set some bits */
         ldr     r4, scratchpad_base
         ldr     r3, [r4,#0xBC]
         ldr     r0, [r3,#4]
         mov     r12, #0x3
-        .word 0xE1600070        @ Call SMI monitor (smieq)
+        .word   0xE1600070              @ Call SMI monitor (smieq)
         ldr     r4, scratchpad_base
         ldr     r3, [r4,#0xBC]
         ldr     r0, [r3,#12]
         mov     r12, #0x2
-        .word 0xE1600070        @ Call SMI monitor (smieq)
+        .word   0xE1600070              @ Call SMI monitor (smieq)
 logic_l1_restore:
+        ldr     r1, l2dis_3630
+        cmp     r1, #0x1                @ Test if L2 re-enable needed on 3630
+        bne     skipl2reen
+        mrc     p15, 0, r1, c1, c0, 1
+        orr     r1, r1, #2              @ re-enable L2 cache
+        mcr     p15, 0, r1, c1, c0, 1
+skipl2reen:
         mov     r1, #0
-        /* Invalidate all instruction caches to PoU
-         * and flush branch target cache */
+        /*
+         * Invalidate all instruction caches to PoU
+         * and flush branch target cache
+         */
         mcr     p15, 0, r1, c7, c5, 0
 
         ldr     r4, scratchpad_base
@@ -341,33 +488,33 @@ logic_l1_restore:
         MCR p15, 0, r6, c2, c0, 1
         /* Translation table base control register */
         MCR p15, 0, r7, c2, c0, 2
-        /*domain access Control Register */
+        /* Domain access Control Register */
         MCR p15, 0, r8, c3, c0, 0
-        /* data fault status Register */
+        /* Data fault status Register */
         MCR p15, 0, r9, c5, c0, 0
 
-        ldmia  r3!,{r4-r8}
-        /* instruction fault status Register */
+        ldmia   r3!,{r4-r8}
+        /* Instruction fault status Register */
         MCR p15, 0, r4, c5, c0, 1
-        /*Data Auxiliary Fault Status Register */
+        /* Data Auxiliary Fault Status Register */
         MCR p15, 0, r5, c5, c1, 0
-        /*Instruction Auxiliary Fault Status Register*/
+        /* Instruction Auxiliary Fault Status Register*/
         MCR p15, 0, r6, c5, c1, 1
-        /*Data Fault Address Register */
+        /* Data Fault Address Register */
         MCR p15, 0, r7, c6, c0, 0
-        /*Instruction Fault Address Register*/
+        /* Instruction Fault Address Register*/
         MCR p15, 0, r8, c6, c0, 2
-        ldmia  r3!,{r4-r7}
+        ldmia   r3!,{r4-r7}
 
-        /* user r/w thread and process ID */
+        /* User r/w thread and process ID */
         MCR p15, 0, r4, c13, c0, 2
-        /* user ro thread and process ID */
+        /* User ro thread and process ID */
         MCR p15, 0, r5, c13, c0, 3
-        /*Privileged only thread and process ID */
+        /* Privileged only thread and process ID */
         MCR p15, 0, r6, c13, c0, 4
-        /* cache size selection */
+        /* Cache size selection */
         MCR p15, 2, r7, c0, c0, 0
-        ldmia  r3!,{r4-r8}
+        ldmia   r3!,{r4-r8}
         /* Data TLB lockdown registers */
         MCR p15, 0, r4, c10, c0, 0
         /* Instruction TLB lockdown registers */
@@ -379,26 +526,27 @@ logic_l1_restore:
         /* Context PID */
         MCR p15, 0, r8, c13, c0, 1
 
-        ldmia  r3!,{r4-r5}
-        /* primary memory remap register */
+        ldmia   r3!,{r4-r5}
+        /* Primary memory remap register */
         MCR p15, 0, r4, c10, c2, 0
-        /*normal memory remap register */
+        /* Normal memory remap register */
         MCR p15, 0, r5, c10, c2, 1
 
         /* Restore cpsr */
-        ldmia   r3!,{r4}        /*load CPSR from SDRAM*/
-        msr     cpsr, r4        /*store cpsr */
+        ldmia   r3!,{r4}                @ load CPSR from SDRAM
+        msr     cpsr, r4                @ store cpsr
 
         /* Enabling MMU here */
-        mrc     p15, 0, r7, c2, c0, 2 /* Read TTBRControl */
-        /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/
+        mrc     p15, 0, r7, c2, c0, 2   @ Read TTBRControl
+        /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
         and     r7, #0x7
         cmp     r7, #0x0
         beq     usettbr0
 ttbr_error:
-        /* More work needs to be done to support N[0:2] value other than 0
-        * So looping here so that the error can be detected
-        */
+        /*
+         * More work needs to be done to support N[0:2] value other than 0
+         * So looping here so that the error can be detected
+         */
         b       ttbr_error
 usettbr0:
         mrc     p15, 0, r2, c2, c0, 0
@@ -406,21 +554,25 @@ usettbr0:
         and     r2, r5
         mov     r4, pc
         ldr     r5, table_index_mask
-        and     r4, r5 /* r4 = 31 to 20 bits of pc */
+        and     r4, r5                  @ r4 = 31 to 20 bits of pc
         /* Extract the value to be written to table entry */
         ldr     r1, table_entry
-        add     r1, r1, r4 /* r1 has value to be written to table entry*/
+        /* r1 has the value to be written to table entry*/
+        add     r1, r1, r4
         /* Getting the address of table entry to modify */
         lsr     r4, #18
-        add     r2, r4 /* r2 has the location which needs to be modified */
+        /* r2 has the location which needs to be modified */
+        add     r2, r4
         /* Storing previous entry of location being modified */
         ldr     r5, scratchpad_base
         ldr     r4, [r2]
         str     r4, [r5, #0xC0]
         /* Modify the table entry */
         str     r1, [r2]
-        /* Storing address of entry being modified
-         * - will be restored after enabling MMU */
+        /*
+         * Storing address of entry being modified
+         * - will be restored after enabling MMU
+         */
         ldr     r5, scratchpad_base
         str     r2, [r5, #0xC4]
 
@@ -429,8 +581,11 @@ usettbr0:
         mcr     p15, 0, r0, c7, c5, 6   @ Invalidate branch predictor array
         mcr     p15, 0, r0, c8, c5, 0   @ Invalidate instruction TLB
         mcr     p15, 0, r0, c8, c6, 0   @ Invalidate data TLB
-        /* Restore control register  but dont enable caches here*/
-        /* Caches will be enabled after restoring MMU table entry */
+        /*
+         * Restore control register. This enables the MMU.
+         * The caches and prediction are not enabled here, they
+         * will be enabled after restoring the MMU table entry.
+         */
         ldmia   r3!, {r4}
         /* Store previous value of control register in scratchpad */
         str     r4, [r5, #0xC8]
@@ -438,212 +593,144 @@ usettbr0:
         and     r4, r2
         mcr     p15, 0, r4, c1, c0, 0
 
-        ldmfd   sp!, {r0-r12, pc}               @ restore regs and return
-save_context_wfi:
-        /*b     save_context_wfi*/      @ enable to debug save code
-        mov     r8, r0 /* Store SDRAM address in r8 */
-        mrc     p15, 0, r5, c1, c0, 1   @ Read Auxiliary Control Register
-        mov     r4, #0x1                @ Number of parameters for restore call
-        stmia   r8!, {r4-r5}            @ Push parameters for restore call
-        mrc     p15, 1, r5, c9, c0, 2   @ Read L2 AUX ctrl register
-        stmia   r8!, {r4-r5}            @ Push parameters for restore call
-        /* Check what that target sleep state is:stored in r1*/
-        /* 1 - Only L1 and logic lost */
-        /* 2 - Only L2 lost */
-        /* 3 - Both L1 and L2 lost */
-        cmp     r1, #0x2 /* Only L2 lost */
-        beq     clean_l2
-        cmp     r1, #0x1 /* L2 retained */
-        /* r9 stores whether to clean L2 or not*/
-        moveq   r9, #0x0 /* Dont Clean L2 */
-        movne   r9, #0x1 /* Clean L2 */
-l1_logic_lost:
-        /* Store sp and spsr to SDRAM */
-        mov     r4, sp
-        mrs     r5, spsr
-        mov     r6, lr
-        stmia   r8!, {r4-r6}
-        /* Save all ARM registers */
-        /* Coprocessor access control register */
-        mrc     p15, 0, r6, c1, c0, 2
-        stmia   r8!, {r6}
-        /* TTBR0, TTBR1 and Translation table base control */
-        mrc     p15, 0, r4, c2, c0, 0
-        mrc     p15, 0, r5, c2, c0, 1
-        mrc     p15, 0, r6, c2, c0, 2
-        stmia   r8!, {r4-r6}
-        /* Domain access control register, data fault status register,
-        and instruction fault status register */
-        mrc     p15, 0, r4, c3, c0, 0
-        mrc     p15, 0, r5, c5, c0, 0
-        mrc     p15, 0, r6, c5, c0, 1
-        stmia   r8!, {r4-r6}
-        /* Data aux fault status register, instruction aux fault status,
-        datat fault address register and instruction fault address register*/
-        mrc     p15, 0, r4, c5, c1, 0
-        mrc     p15, 0, r5, c5, c1, 1
-        mrc     p15, 0, r6, c6, c0, 0
-        mrc     p15, 0, r7, c6, c0, 2
-        stmia   r8!, {r4-r7}
-        /* user r/w thread and process ID, user r/o thread and process ID,
-        priv only thread and process ID, cache size selection */
-        mrc     p15, 0, r4, c13, c0, 2
-        mrc     p15, 0, r5, c13, c0, 3
-        mrc     p15, 0, r6, c13, c0, 4
-        mrc     p15, 2, r7, c0, c0, 0
-        stmia   r8!, {r4-r7}
-        /* Data TLB lockdown, instruction TLB lockdown registers */
-        mrc     p15, 0, r5, c10, c0, 0
-        mrc     p15, 0, r6, c10, c0, 1
-        stmia   r8!, {r5-r6}
-        /* Secure or non secure vector base address, FCSE PID, Context PID*/
-        mrc     p15, 0, r4, c12, c0, 0
-        mrc     p15, 0, r5, c13, c0, 0
-        mrc     p15, 0, r6, c13, c0, 1
-        stmia   r8!, {r4-r6}
-        /* Primary remap, normal remap registers */
-        mrc     p15, 0, r4, c10, c2, 0
-        mrc     p15, 0, r5, c10, c2, 1
-        stmia   r8!,{r4-r5}
+/*
+ * ==============================
+ * == Exit point from OFF mode ==
+ * ==============================
+ */
+        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
 
-        /* Store current cpsr*/
-        mrs     r2, cpsr
-        stmia   r8!, {r2}
 
-        mrc     p15, 0, r4, c1, c0, 0
-        /* save control register */
-        stmia   r8!, {r4}
-clean_caches:
-        /* Clean Data or unified cache to POU*/
-        /* How to invalidate only L1 cache???? - #FIX_ME# */
-        /* mcr  p15, 0, r11, c7, c11, 1 */
-        cmp     r9, #1 /* Check whether L2 inval is required or not*/
-        bne     skip_l2_inval
-clean_l2:
-        /* read clidr */
-        mrc     p15, 1, r0, c0, c0, 1
-        /* extract loc from clidr */
-        ands    r3, r0, #0x7000000
-        /* left align loc bit field */
-        mov     r3, r3, lsr #23
-        /* if loc is 0, then no need to clean */
-        beq     finished
-        /* start clean at cache level 0 */
-        mov     r10, #0
-loop1:
-        /* work out 3x current cache level */
-        add     r2, r10, r10, lsr #1
-        /* extract cache type bits from clidr*/
-        mov     r1, r0, lsr r2
-        /* mask of the bits for current cache only */
-        and     r1, r1, #7
-        /* see what cache we have at this level */
-        cmp     r1, #2
-        /* skip if no cache, or just i-cache */
-        blt     skip
-        /* select current cache level in cssr */
-        mcr     p15, 2, r10, c0, c0, 0
-        /* isb to sych the new cssr&csidr */
-        isb
-        /* read the new csidr */
-        mrc     p15, 1, r1, c0, c0, 0
-        /* extract the length of the cache lines */
-        and     r2, r1, #7
-        /* add 4 (line length offset) */
-        add     r2, r2, #4
-        ldr     r4, assoc_mask
-        /* find maximum number on the way size */
-        ands    r4, r4, r1, lsr #3
-        /* find bit position of way size increment */
-        clz     r5, r4
-        ldr     r7, numset_mask
-        /* extract max number of the index size*/
-        ands    r7, r7, r1, lsr #13
-loop2:
-        mov     r9, r4
-        /* create working copy of max way size*/
-loop3:
-        /* factor way and cache number into r11 */
-        orr     r11, r10, r9, lsl r5
-        /* factor index number into r11 */
-        orr     r11, r11, r7, lsl r2
-        /*clean & invalidate by set/way */
-        mcr     p15, 0, r11, c7, c10, 2
-        /* decrement the way*/
-        subs    r9, r9, #1
-        bge     loop3
-        /*decrement the index */
-        subs    r7, r7, #1
-        bge     loop2
-skip:
-        add     r10, r10, #2
-        /* increment cache number */
-        cmp     r3, r10
-        bgt     loop1
-finished:
-        /*swith back to cache level 0 */
-        mov     r10, #0
-        /* select current cache level in cssr */
-        mcr     p15, 2, r10, c0, c0, 0
-        isb
-skip_l2_inval:
-        /* Data memory barrier and Data sync barrier */
-        mov     r1, #0
-        mcr     p15, 0, r1, c7, c10, 4
-        mcr     p15, 0, r1, c7, c10, 5
+/*
+ * Internal functions
+ */
 
-        wfi                             @ wait for interrupt
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        nop
-        bl wait_sdrc_ok
-        /* restore regs and return */
-        ldmfd   sp!, {r0-r12, pc}
+/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
+        .text
+ENTRY(es3_sdrc_fix)
+        ldr     r4, sdrc_syscfg         @ get config addr
+        ldr     r5, [r4]                @ get value
+        tst     r5, #0x100              @ is part access blocked
+        it      eq
+        biceq   r5, r5, #0x100          @ clear bit if set
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_mr_0           @ get config addr
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_emr2_0         @ get config addr
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_manual_0       @ get config addr
+        mov     r5, #0x2                @ autorefresh command
+        str     r5, [r4]                @ kick off refreshes
+        ldr     r4, sdrc_mr_1           @ get config addr
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_emr2_1         @ get config addr
+        ldr     r5, [r4]                @ get value
+        str     r5, [r4]                @ write back change
+        ldr     r4, sdrc_manual_1       @ get config addr
+        mov     r5, #0x2                @ autorefresh command
+        str     r5, [r4]                @ kick off refreshes
+        bx      lr
+
+sdrc_syscfg:
+        .word   SDRC_SYSCONFIG_P
+sdrc_mr_0:
+        .word   SDRC_MR_0_P
+sdrc_emr2_0:
+        .word   SDRC_EMR2_0_P
+sdrc_manual_0:
+        .word   SDRC_MANUAL_0_P
+sdrc_mr_1:
+        .word   SDRC_MR_1_P
+sdrc_emr2_1:
+        .word   SDRC_EMR2_1_P
+sdrc_manual_1:
+        .word   SDRC_MANUAL_1_P
+ENTRY(es3_sdrc_fix_sz)
+        .word   . - es3_sdrc_fix
+
+/*
+ * This function implements the erratum ID i581 WA:
+ *  SDRC state restore before accessing the SDRAM
+ *
+ * Only used at return from non-OFF mode. For OFF
+ * mode the ROM code configures the SDRC and
+ * the DPLL before calling the restore code directly
+ * from DDR.
+ */
 
 /* Make sure SDRC accesses are ok */
 wait_sdrc_ok:
-        ldr     r4, cm_idlest1_core
-        ldr     r5, [r4]
-        and     r5, r5, #0x2
-        cmp     r5, #0
-        bne     wait_sdrc_ok
-        ldr     r4, sdrc_power
-        ldr     r5, [r4]
-        bic     r5, r5, #0x40
-        str     r5, [r4]
+
+/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
+        ldr     r4, cm_idlest_ckgen
+wait_dpll3_lock:
+        ldr     r5, [r4]
+        tst     r5, #1
+        beq     wait_dpll3_lock
+
+        ldr     r4, cm_idlest1_core
+wait_sdrc_ready:
+        ldr     r5, [r4]
+        tst     r5, #0x2
+        bne     wait_sdrc_ready
+        /* allow DLL powerdown upon hw idle req */
+        ldr     r4, sdrc_power
+        ldr     r5, [r4]
+        bic     r5, r5, #0x40
+        str     r5, [r4]
+
+is_dll_in_lock_mode:
+        /* Is dll in lock mode? */
+        ldr     r4, sdrc_dlla_ctrl
+        ldr     r5, [r4]
+        tst     r5, #0x4
+        bxne    lr                      @ Return if locked
+        /* wait till dll locks */
+wait_dll_lock_timed:
+        ldr     r4, wait_dll_lock_counter
+        add     r4, r4, #1
+        str     r4, wait_dll_lock_counter
+        ldr     r4, sdrc_dlla_status
+        /* Wait 20uS for lock */
+        mov     r6, #8
 wait_dll_lock:
-        /* Is dll in lock mode? */
-        ldr     r4, sdrc_dlla_ctrl
-        ldr     r5, [r4]
-        tst     r5, #0x4
-        bxne    lr
-        /* wait till dll locks */
-        ldr     r4, sdrc_dlla_status
-        ldr     r5, [r4]
-        and     r5, r5, #0x4
-        cmp     r5, #0x4
-        bne     wait_dll_lock
-        bx      lr
+        subs    r6, r6, #0x1
+        beq     kick_dll
+        ldr     r5, [r4]
+        and     r5, r5, #0x4
+        cmp     r5, #0x4
+        bne     wait_dll_lock
+        bx      lr                      @ Return when locked
+
+        /* disable/reenable DLL if not locked */
+kick_dll:
+        ldr     r4, sdrc_dlla_ctrl
+        ldr     r5, [r4]
+        mov     r6, r5
+        bic     r6, #(1<<3)             @ disable dll
+        str     r6, [r4]
+        dsb
+        orr     r6, r6, #(1<<3)         @ enable dll
+        str     r6, [r4]
+        dsb
+        ldr     r4, kick_counter
+        add     r4, r4, #1
+        str     r4, kick_counter
+        b       wait_dll_lock_timed
 
 cm_idlest1_core:
         .word   CM_IDLEST1_CORE_V
+cm_idlest_ckgen:
+        .word   CM_IDLEST_CKGEN_V
 sdrc_dlla_status:
         .word   SDRC_DLLA_STATUS_V
 sdrc_dlla_ctrl:
         .word   SDRC_DLLA_CTRL_V
-pm_prepwstst_core:
-        .word   PM_PREPWSTST_CORE_V
 pm_prepwstst_core_p:
         .word   PM_PREPWSTST_CORE_P
-pm_prepwstst_mpu:
-        .word   PM_PREPWSTST_MPU_V
 pm_pwstctrl_mpu:
         .word   PM_PWSTCTRL_MPU_P
 scratchpad_base:
@@ -651,13 +738,7 @@ scratchpad_base:
 sram_base:
         .word   SRAM_BASE_P + 0x8000
 sdrc_power:
-        .word SDRC_POWER_V
-clk_stabilize_delay:
-        .word 0x000001FF
-assoc_mask:
-        .word   0x3ff
-numset_mask:
-        .word   0x7fff
+        .word   SDRC_POWER_V
 ttbrbit_mask:
         .word   0xFFFFC000
 table_index_mask:
@@ -668,5 +749,20 @@ cache_pred_disable_mask:
         .word   0xFFFFE7FB
 control_stat:
         .word   CONTROL_STAT
+control_mem_rta:
+        .word   CONTROL_MEM_RTA_CTRL
+kernel_flush:
+        .word   v7_flush_dcache_all
+l2dis_3630:
+        .word   0
+        /*
+         * When exporting to userspace while the counters are in SRAM,
+         * these 2 words need to be at the end to facilitate retrival!
+         */
+kick_counter:
+        .word   0
+wait_dll_lock_counter:
+        .word   0
+
 ENTRY(omap34xx_cpu_suspend_sz)
         .word   . - omap34xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
new file mode 100644
index 000000000000..60e70552b4c5
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -0,0 +1,59 @@
+/*
+ * Smart reflex Class 3 specific implementations
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/smartreflex.h>
+
+static int sr_class3_enable(struct voltagedomain *voltdm)
+{
+        unsigned long volt = omap_voltage_get_nom_volt(voltdm);
+
+        if (!volt) {
+                pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
+                                __func__, voltdm->name);
+                return -ENODATA;
+        }
+
+        omap_vp_enable(voltdm);
+        return sr_enable(voltdm, volt);
+}
+
+static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
+{
+        omap_vp_disable(voltdm);
+        sr_disable(voltdm);
+        if (is_volt_reset)
+                omap_voltage_reset(voltdm);
+
+        return 0;
+}
+
+static int sr_class3_configure(struct voltagedomain *voltdm)
+{
+        return sr_configure_errgen(voltdm);
+}
+
+/* SR class3 structure */
+static struct omap_sr_class_data class3_data = {
+        .enable = sr_class3_enable,
+        .disable = sr_class3_disable,
+        .configure = sr_class3_configure,
+        .class_type = SR_CLASS3,
+};
+
+/* Smartreflex Class3 init API to be called from board file */
+static int __init sr_class3_init(void)
+{
+        pr_info("SmartReflex Class3 initialized\n");
+        return sr_register_class(&class3_data);
+}
+late_initcall(sr_class3_init);
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
new file mode 100644
index 000000000000..77ecebf3fae2
--- /dev/null
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -0,0 +1,1029 @@
+/*
+ * OMAP SmartReflex Voltage Control
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
+
+#include <plat/common.h>
+#include <plat/smartreflex.h>
+
+#include "pm.h"
+
+#define SMARTREFLEX_NAME_LEN    16
+#define NVALUE_NAME_LEN         40
+#define SR_DISABLE_TIMEOUT      200
+
+struct omap_sr {
+        int                             srid;
+        int                             ip_type;
+        int                             nvalue_count;
+        bool                            autocomp_active;
+        u32                             clk_length;
+        u32                             err_weight;
+        u32                             err_minlimit;
+        u32                             err_maxlimit;
+        u32                             accum_data;
+        u32                             senn_avgweight;
+        u32                             senp_avgweight;
+        u32                             senp_mod;
+        u32                             senn_mod;
+        unsigned int                    irq;
+        void __iomem                    *base;
+        struct platform_device          *pdev;
+        struct list_head                node;
+        struct omap_sr_nvalue_table     *nvalue_table;
+        struct voltagedomain            *voltdm;
+};
+
+/* sr_list contains all the instances of smartreflex module */
+static LIST_HEAD(sr_list);
+
+static struct omap_sr_class_data *sr_class;
+static struct omap_sr_pmic_data *sr_pmic_data;
+
+static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
+{
+        __raw_writel(value, (sr->base + offset));
+}
+
+static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
+                                        u32 value)
+{
+        u32 reg_val;
+        u32 errconfig_offs = 0, errconfig_mask = 0;
+
+        reg_val = __raw_readl(sr->base + offset);
+        reg_val &= ~mask;
+
+        /*
+         * Smartreflex error config register is special as it contains
+         * certain status bits which if written a 1 into means a clear
+         * of those bits. So in order to make sure no accidental write of
+         * 1 happens to those status bits, do a clear of them in the read
+         * value. This mean this API doesn't rewrite values in these bits
+         * if they are currently set, but does allow the caller to write
+         * those bits.
+         */
+        if (sr->ip_type == SR_TYPE_V1) {
+                errconfig_offs = ERRCONFIG_V1;
+                errconfig_mask = ERRCONFIG_STATUS_V1_MASK;
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                errconfig_offs = ERRCONFIG_V2;
+                errconfig_mask = ERRCONFIG_VPBOUNDINTST_V2;
+        }
+
+        if (offset == errconfig_offs)
+                reg_val &= ~errconfig_mask;
+
+        reg_val |= value;
+
+        __raw_writel(reg_val, (sr->base + offset));
+}
+
+static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
+{
+        return __raw_readl(sr->base + offset);
+}
+
+static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr_info;
+
+        if (!voltdm) {
+                pr_err("%s: Null voltage domain passed!\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        list_for_each_entry(sr_info, &sr_list, node) {
+                if (voltdm == sr_info->voltdm)
+                        return sr_info;
+        }
+
+        return ERR_PTR(-ENODATA);
+}
+
+static irqreturn_t sr_interrupt(int irq, void *data)
+{
+        struct omap_sr *sr_info = (struct omap_sr *)data;
+        u32 status = 0;
+
+        if (sr_info->ip_type == SR_TYPE_V1) {
+                /* Read the status bits */
+                status = sr_read_reg(sr_info, ERRCONFIG_V1);
+
+                /* Clear them by writing back */
+                sr_write_reg(sr_info, ERRCONFIG_V1, status);
+        } else if (sr_info->ip_type == SR_TYPE_V2) {
+                /* Read the status bits */
+                sr_read_reg(sr_info, IRQSTATUS);
+
+                /* Clear them by writing back */
+                sr_write_reg(sr_info, IRQSTATUS, status);
+        }
+
+        if (sr_class->class_type == SR_CLASS2 && sr_class->notify)
+                sr_class->notify(sr_info->voltdm, status);
+
+        return IRQ_HANDLED;
+}
+
+static void sr_set_clk_length(struct omap_sr *sr)
+{
+        struct clk *sys_ck;
+        u32 sys_clk_speed;
+
+        if (cpu_is_omap34xx())
+                sys_ck = clk_get(NULL, "sys_ck");
+        else
+                sys_ck = clk_get(NULL, "sys_clkin_ck");
+
+        if (IS_ERR(sys_ck)) {
+                dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
+                        __func__);
+                return;
+        }
+        sys_clk_speed = clk_get_rate(sys_ck);
+        clk_put(sys_ck);
+
+        switch (sys_clk_speed) {
+        case 12000000:
+                sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
+                break;
+        case 13000000:
+                sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
+                break;
+        case 19200000:
+                sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
+                break;
+        case 26000000:
+                sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
+                break;
+        case 38400000:
+                sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
+                break;
+        default:
+                dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n",
+                        __func__, sys_clk_speed);
+                break;
+        }
+}
+
+static void sr_set_regfields(struct omap_sr *sr)
+{
+        /*
+         * For time being these values are defined in smartreflex.h
+         * and populated during init. May be they can be moved to board
+         * file or pmic specific data structure. In that case these structure
+         * fields will have to be populated using the pdata or pmic structure.
+         */
+        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                sr->err_weight = OMAP3430_SR_ERRWEIGHT;
+                sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
+                sr->accum_data = OMAP3430_SR_ACCUMDATA;
+                if (!(strcmp(sr->voltdm->name, "mpu"))) {
+                        sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
+                        sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
+                } else {
+                        sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
+                        sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
+                }
+        }
+}
+
+static void sr_start_vddautocomp(struct omap_sr *sr)
+{
+        if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+                dev_warn(&sr->pdev->dev,
+                        "%s: smartreflex class driver not registered\n",
+                        __func__);
+                return;
+        }
+
+        if (!sr_class->enable(sr->voltdm))
+                sr->autocomp_active = true;
+}
+
+static void sr_stop_vddautocomp(struct omap_sr *sr)
+{
+        if (!sr_class || !(sr_class->disable)) {
+                dev_warn(&sr->pdev->dev,
+                        "%s: smartreflex class driver not registered\n",
+                        __func__);
+                return;
+        }
+
+        if (sr->autocomp_active) {
+                sr_class->disable(sr->voltdm, 1);
+                sr->autocomp_active = false;
+        }
+}
+
+/*
+ * This function handles the intializations which have to be done
+ * only when both sr device and class driver regiter has
+ * completed. This will be attempted to be called from both sr class
+ * driver register and sr device intializtion API's. Only one call
+ * will ultimately succeed.
+ *
+ * Currenly this function registers interrrupt handler for a particular SR
+ * if smartreflex class driver is already registered and has
+ * requested for interrupts and the SR interrupt line in present.
+ */
+static int sr_late_init(struct omap_sr *sr_info)
+{
+        char *name;
+        struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
+        struct resource *mem;
+        int ret = 0;
+
+        if (sr_class->class_type == SR_CLASS2 &&
+                sr_class->notify_flags && sr_info->irq) {
+
+                name = kzalloc(SMARTREFLEX_NAME_LEN + 1, GFP_KERNEL);
+                strcpy(name, "sr_");
+                strcat(name, sr_info->voltdm->name);
+                ret = request_irq(sr_info->irq, sr_interrupt,
+                                0, name, (void *)sr_info);
+                if (ret)
+                        goto error;
+        }
+
+        if (pdata && pdata->enable_on_init)
+                sr_start_vddautocomp(sr_info);
+
+        return ret;
+
+error:
+                iounmap(sr_info->base);
+                mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
+                release_mem_region(mem->start, resource_size(mem));
+                list_del(&sr_info->node);
+                dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
+                        "interrupt handler. Smartreflex will"
+                        "not function as desired\n", __func__);
+                kfree(sr_info);
+                return ret;
+}
+
+static void sr_v1_disable(struct omap_sr *sr)
+{
+        int timeout = 0;
+
+        /* Enable MCUDisableAcknowledge interrupt */
+        sr_modify_reg(sr, ERRCONFIG_V1,
+                        ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
+
+        /* SRCONFIG - disable SR */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+        /* Disable all other SR interrupts and clear the status */
+        sr_modify_reg(sr, ERRCONFIG_V1,
+                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+                        ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
+                        (ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
+                        ERRCONFIG_MCUBOUNDINTST |
+                        ERRCONFIG_VPBOUNDINTST_V1));
+
+        /*
+         * Wait for SR to be disabled.
+         * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
+         */
+        omap_test_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
+                        ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
+                        timeout);
+
+        if (timeout >= SR_DISABLE_TIMEOUT)
+                dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+                        __func__);
+
+        /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+        sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
+                        ERRCONFIG_MCUDISACKINTST);
+}
+
+static void sr_v2_disable(struct omap_sr *sr)
+{
+        int timeout = 0;
+
+        /* Enable MCUDisableAcknowledge interrupt */
+        sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
+
+        /* SRCONFIG - disable SR */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
+
+        /* Disable all other SR interrupts and clear the status */
+        sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
+                        ERRCONFIG_VPBOUNDINTST_V2);
+        sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
+                        IRQENABLE_MCUVALIDINT |
+                        IRQENABLE_MCUBOUNDSINT));
+        sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
+                        IRQSTATUS_MCVALIDINT |
+                        IRQSTATUS_MCBOUNDSINT));
+
+        /*
+         * Wait for SR to be disabled.
+         * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
+         */
+        omap_test_timeout((sr_read_reg(sr, IRQSTATUS) &
+                        IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
+                        timeout);
+
+        if (timeout >= SR_DISABLE_TIMEOUT)
+                dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
+                        __func__);
+
+        /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
+        sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
+        sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
+}
+
+static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
+{
+        int i;
+
+        if (!sr->nvalue_table) {
+                dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
+                        __func__);
+                return 0;
+        }
+
+        for (i = 0; i < sr->nvalue_count; i++) {
+                if (sr->nvalue_table[i].efuse_offs == efuse_offs)
+                        return sr->nvalue_table[i].nvalue;
+        }
+
+        return 0;
+}
+
+/* Public Functions */
+
+/**
+ * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
+ *                       error generator module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the error generator module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_errgen(struct voltagedomain *voltdm)
+{
+        u32 sr_config, sr_errconfig, errconfig_offs, vpboundint_en;
+        u32 vpboundint_st, senp_en = 0, senn_en = 0;
+        u8 senp_shift, senn_shift;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+
+        if (!sr->clk_length)
+                sr_set_clk_length(sr);
+
+        senp_en = sr->senp_mod;
+        senn_en = sr->senn_mod;
+
+        sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
+
+        if (sr->ip_type == SR_TYPE_V1) {
+                sr_config |= SRCONFIG_DELAYCTRL;
+                senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+                errconfig_offs = ERRCONFIG_V1;
+                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
+                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+                errconfig_offs = ERRCONFIG_V2;
+                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
+                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
+        } else {
+                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+                        "module without specifying the ip\n", __func__);
+                return -EINVAL;
+        }
+
+        sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+        sr_write_reg(sr, SRCONFIG, sr_config);
+        sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
+                (sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
+                (sr->err_minlimit <<  ERRCONFIG_ERRMINLIMIT_SHIFT);
+        sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
+                SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+                sr_errconfig);
+
+        /* Enabling the interrupts if the ERROR module is used */
+        sr_modify_reg(sr, errconfig_offs,
+                vpboundint_en, (vpboundint_en | vpboundint_st));
+
+        return 0;
+}
+
+/**
+ * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the
+ *                       minmaxavg module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * configure the minmaxavg module inside the smartreflex module.
+ * SR settings if using the ERROR module inside Smartreflex.
+ * SR CLASS 3 by default uses only the ERROR module where as
+ * SR CLASS 2 can choose between ERROR module and MINMAXAVG
+ * module. Returns 0 on success and error value in case of failure.
+ */
+int sr_configure_minmax(struct voltagedomain *voltdm)
+{
+        u32 sr_config, sr_avgwt;
+        u32 senp_en = 0, senn_en = 0;
+        u8 senp_shift, senn_shift;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+
+        if (!sr->clk_length)
+                sr_set_clk_length(sr);
+
+        senp_en = sr->senp_mod;
+        senn_en = sr->senn_mod;
+
+        sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
+                SRCONFIG_SENENABLE |
+                (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
+
+        if (sr->ip_type == SR_TYPE_V1) {
+                sr_config |= SRCONFIG_DELAYCTRL;
+                senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
+                senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
+        } else {
+                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
+                        "module without specifying the ip\n", __func__);
+                return -EINVAL;
+        }
+
+        sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
+        sr_write_reg(sr, SRCONFIG, sr_config);
+        sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
+                (sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
+        sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
+
+        /*
+         * Enabling the interrupts if MINMAXAVG module is used.
+         * TODO: check if all the interrupts are mandatory
+         */
+        if (sr->ip_type == SR_TYPE_V1) {
+                sr_modify_reg(sr, ERRCONFIG_V1,
+                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
+                        ERRCONFIG_MCUBOUNDINTEN),
+                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
+                         ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
+                         ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
+        } else if (sr->ip_type == SR_TYPE_V2) {
+                sr_write_reg(sr, IRQSTATUS,
+                        IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
+                        IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
+                sr_write_reg(sr, IRQENABLE_SET,
+                        IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
+                        IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
+        }
+
+        return 0;
+}
+
+/**
+ * sr_enable() - Enables the smartreflex module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ * @volt:       The voltage at which the Voltage domain associated with
+ *              the smartreflex module is operating at.
+ *              This is required only to program the correct Ntarget value.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * enable a smartreflex module. Returns 0 on success. Returns error
+ * value if the voltage passed is wrong or if ntarget value is wrong.
+ */
+int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
+{
+        u32 nvalue_reciprocal;
+        struct omap_volt_data *volt_data;
+        struct omap_sr *sr = _sr_lookup(voltdm);
+        int ret;
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return -EINVAL;
+        }
+
+        volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
+
+        if (IS_ERR(volt_data)) {
+                dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table"
+                        "for nominal voltage %ld\n", __func__, volt);
+                return -ENODATA;
+        }
+
+        nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs);
+
+        if (!nvalue_reciprocal) {
+                dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n",
+                        __func__, volt);
+                return -ENODATA;
+        }
+
+        /* errminlimit is opp dependent and hence linked to voltage */
+        sr->err_minlimit = volt_data->sr_errminlimit;
+
+        pm_runtime_get_sync(&sr->pdev->dev);
+
+        /* Check if SR is already enabled. If yes do nothing */
+        if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
+                return 0;
+
+        /* Configure SR */
+        ret = sr_class->configure(voltdm);
+        if (ret)
+                return ret;
+
+        sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
+
+        /* SRCONFIG - enable SR */
+        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
+        return 0;
+}
+
+/**
+ * sr_disable() - Disables the smartreflex module.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the smartreflex class driver to
+ * disable a smartreflex module.
+ */
+void sr_disable(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        /* Check if SR clocks are already disabled. If yes do nothing */
+        if (pm_runtime_suspended(&sr->pdev->dev))
+                return;
+
+        /*
+         * Disable SR if only it is indeed enabled. Else just
+         * disable the clocks.
+         */
+        if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
+                if (sr->ip_type == SR_TYPE_V1)
+                        sr_v1_disable(sr);
+                else if (sr->ip_type == SR_TYPE_V2)
+                        sr_v2_disable(sr);
+        }
+
+        pm_runtime_put_sync(&sr->pdev->dev);
+}
+
+/**
+ * sr_register_class() - API to register a smartreflex class parameters.
+ * @class_data: The structure containing various sr class specific data.
+ *
+ * This API is to be called by the smartreflex class driver to register itself
+ * with the smartreflex driver during init. Returns 0 on success else the
+ * error value.
+ */
+int sr_register_class(struct omap_sr_class_data *class_data)
+{
+        struct omap_sr *sr_info;
+
+        if (!class_data) {
+                pr_warning("%s:, Smartreflex class data passed is NULL\n",
+                        __func__);
+                return -EINVAL;
+        }
+
+        if (sr_class) {
+                pr_warning("%s: Smartreflex class driver already registered\n",
+                        __func__);
+                return -EBUSY;
+        }
+
+        sr_class = class_data;
+
+        /*
+         * Call into late init to do intializations that require
+         * both sr driver and sr class driver to be initiallized.
+         */
+        list_for_each_entry(sr_info, &sr_list, node)
+                sr_late_init(sr_info);
+
+        return 0;
+}
+
+/**
+ * omap_sr_enable() -  API to enable SR clocks and to call into the
+ *                      registered smartreflex class enable API.
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to enable
+ * a particular smartreflex module. This API will do the initial
+ * configurations to turn on the smartreflex module and in turn call
+ * into the registered smartreflex class enable API.
+ */
+void omap_sr_enable(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        if (!sr->autocomp_active)
+                return;
+
+        if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
+                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+                        "registered\n", __func__);
+                return;
+        }
+
+        sr_class->enable(voltdm);
+}
+
+/**
+ * omap_sr_disable() - API to disable SR without resetting the voltage
+ *                      processor voltage
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable not to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        if (!sr->autocomp_active)
+                return;
+
+        if (!sr_class || !(sr_class->disable)) {
+                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+                        "registered\n", __func__);
+                return;
+        }
+
+        sr_class->disable(voltdm, 0);
+}
+
+/**
+ * omap_sr_disable_reset_volt() - API to disable SR and reset the
+ *                              voltage processor voltage
+ * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
+ *
+ * This API is to be called from the kernel in order to disable
+ * a particular smartreflex module. This API will in turn call
+ * into the registered smartreflex class disable API. This API will tell
+ * the smartreflex class disable to reset the VP voltage after
+ * disabling smartreflex.
+ */
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
+{
+        struct omap_sr *sr = _sr_lookup(voltdm);
+
+        if (IS_ERR(sr)) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        if (!sr->autocomp_active)
+                return;
+
+        if (!sr_class || !(sr_class->disable)) {
+                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
+                        "registered\n", __func__);
+                return;
+        }
+
+        sr_class->disable(voltdm, 1);
+}
+
+/**
+ * omap_sr_register_pmic() - API to register pmic specific info.
+ * @pmic_data:  The structure containing pmic specific data.
+ *
+ * This API is to be called from the PMIC specific code to register with
+ * smartreflex driver pmic specific info. Currently the only info required
+ * is the smartreflex init on the PMIC side.
+ */
+void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
+{
+        if (!pmic_data) {
+                pr_warning("%s: Trying to register NULL PMIC data structure"
+                        "with smartreflex\n", __func__);
+                return;
+        }
+
+        sr_pmic_data = pmic_data;
+}
+
+/* PM Debug Fs enteries to enable disable smartreflex. */
+static int omap_sr_autocomp_show(void *data, u64 *val)
+{
+        struct omap_sr *sr_info = (struct omap_sr *) data;
+
+        if (!sr_info) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, sr_info->voltdm->name);
+                return -EINVAL;
+        }
+
+        *val = sr_info->autocomp_active;
+
+        return 0;
+}
+
+static int omap_sr_autocomp_store(void *data, u64 val)
+{
+        struct omap_sr *sr_info = (struct omap_sr *) data;
+
+        if (!sr_info) {
+                pr_warning("%s: omap_sr struct for sr_%s not found\n",
+                        __func__, sr_info->voltdm->name);
+                return -EINVAL;
+        }
+
+        /* Sanity check */
+        if (val && (val != 1)) {
+                pr_warning("%s: Invalid argument %lld\n", __func__, val);
+                return -EINVAL;
+        }
+
+        if (!val)
+                sr_stop_vddautocomp(sr_info);
+        else
+                sr_start_vddautocomp(sr_info);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
+                omap_sr_autocomp_store, "%llu\n");
+
+static int __init omap_sr_probe(struct platform_device *pdev)
+{
+        struct omap_sr *sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
+        struct omap_sr_data *pdata = pdev->dev.platform_data;
+        struct resource *mem, *irq;
+        struct dentry *vdd_dbg_dir, *dbg_dir, *nvalue_dir;
+        struct omap_volt_data *volt_data;
+        int i, ret = 0;
+
+        if (!sr_info) {
+                dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
+                        __func__);
+                return -ENOMEM;
+        }
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+                return -EINVAL;
+        }
+
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!mem) {
+                dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
+                ret = -ENODEV;
+                goto err_free_devinfo;
+        }
+
+        irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+        pm_runtime_enable(&pdev->dev);
+
+        sr_info->pdev = pdev;
+        sr_info->srid = pdev->id;
+        sr_info->voltdm = pdata->voltdm;
+        sr_info->nvalue_table = pdata->nvalue_table;
+        sr_info->nvalue_count = pdata->nvalue_count;
+        sr_info->senn_mod = pdata->senn_mod;
+        sr_info->senp_mod = pdata->senp_mod;
+        sr_info->autocomp_active = false;
+        sr_info->ip_type = pdata->ip_type;
+        sr_info->base = ioremap(mem->start, resource_size(mem));
+        if (!sr_info->base) {
+                dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
+                ret = -ENOMEM;
+                goto err_release_region;
+        }
+
+        if (irq)
+                sr_info->irq = irq->start;
+
+        sr_set_clk_length(sr_info);
+        sr_set_regfields(sr_info);
+
+        list_add(&sr_info->node, &sr_list);
+
+        /*
+         * Call into late init to do intializations that require
+         * both sr driver and sr class driver to be initiallized.
+         */
+        if (sr_class) {
+                ret = sr_late_init(sr_info);
+                if (ret) {
+                        pr_warning("%s: Error in SR late init\n", __func__);
+                        return ret;
+                }
+        }
+
+        dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
+
+        /*
+         * If the voltage domain debugfs directory is not created, do
+         * not try to create rest of the debugfs entries.
+         */
+        vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
+        if (!vdd_dbg_dir)
+                return -EINVAL;
+
+        dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
+        if (IS_ERR(dbg_dir)) {
+                dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
+                        __func__);
+                return PTR_ERR(dbg_dir);
+        }
+
+        (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir,
+                                (void *)sr_info, &pm_sr_fops);
+        (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir,
+                        &sr_info->err_weight);
+        (void) debugfs_create_x32("errmaxlimit", S_IRUGO, dbg_dir,
+                        &sr_info->err_maxlimit);
+        (void) debugfs_create_x32("errminlimit", S_IRUGO, dbg_dir,
+                        &sr_info->err_minlimit);
+
+        nvalue_dir = debugfs_create_dir("nvalue", dbg_dir);
+        if (IS_ERR(nvalue_dir)) {
+                dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
+                        "for n-values\n", __func__);
+                return PTR_ERR(nvalue_dir);
+        }
+
+        omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
+        if (!volt_data) {
+                dev_warn(&pdev->dev, "%s: No Voltage table for the"
+                        " corresponding vdd vdd_%s. Cannot create debugfs"
+                        "entries for n-values\n",
+                        __func__, sr_info->voltdm->name);
+                return -ENODATA;
+        }
+
+        for (i = 0; i < sr_info->nvalue_count; i++) {
+                char *name;
+                char volt_name[32];
+
+                name = kzalloc(NVALUE_NAME_LEN + 1, GFP_KERNEL);
+                if (!name) {
+                        dev_err(&pdev->dev, "%s: Unable to allocate memory"
+                                " for n-value directory name\n",  __func__);
+                        return -ENOMEM;
+                }
+
+                strcpy(name, "volt_");
+                sprintf(volt_name, "%d", volt_data[i].volt_nominal);
+                strcat(name, volt_name);
+                (void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir,
+                                &(sr_info->nvalue_table[i].nvalue));
+        }
+
+        return ret;
+
+err_release_region:
+        release_mem_region(mem->start, resource_size(mem));
+err_free_devinfo:
+        kfree(sr_info);
+
+        return ret;
+}
+
+static int __devexit omap_sr_remove(struct platform_device *pdev)
+{
+        struct omap_sr_data *pdata = pdev->dev.platform_data;
+        struct omap_sr *sr_info;
+        struct resource *mem;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+                return -EINVAL;
+        }
+
+        sr_info = _sr_lookup(pdata->voltdm);
+        if (!sr_info) {
+                dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
+                        __func__);
+                return -EINVAL;
+        }
+
+        if (sr_info->autocomp_active)
+                sr_stop_vddautocomp(sr_info);
+
+        list_del(&sr_info->node);
+        iounmap(sr_info->base);
+        kfree(sr_info);
+        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        release_mem_region(mem->start, resource_size(mem));
+
+        return 0;
+}
+
+static struct platform_driver smartreflex_driver = {
+        .remove         = omap_sr_remove,
+        .driver         = {
+                .name   = "smartreflex",
+        },
+};
+
+static int __init sr_init(void)
+{
+        int ret = 0;
+
+        /*
+         * sr_init is a late init. If by then a pmic specific API is not
+         * registered either there is no need for anything to be done on
+         * the PMIC side or somebody has forgotten to register a PMIC
+         * handler. Warn for the second condition.
+         */
+        if (sr_pmic_data && sr_pmic_data->sr_pmic_init)
+                sr_pmic_data->sr_pmic_init();
+        else
+                pr_warning("%s: No PMIC hook to init smartreflex\n", __func__);
+
+        ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe);
+        if (ret) {
+                pr_err("%s: platform driver register failed for SR\n",
+                        __func__);
+                return ret;
+        }
+
+        return 0;
+}
+
+static void __exit sr_exit(void)
+{
+        platform_driver_unregister(&smartreflex_driver);
+}
+late_initcall(sr_init);
+module_exit(sr_exit);
+
+MODULE_DESCRIPTION("OMAP Smartreflex Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
new file mode 100644
index 000000000000..786d685c09a9
--- /dev/null
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -0,0 +1,146 @@
+/*
+ * OMAP3/OMAP4 smartreflex device file
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Based originally on code from smartreflex.c
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+#include <plat/omap_device.h>
+#include <plat/smartreflex.h>
+#include <plat/voltage.h>
+
+#include "control.h"
+
+static bool sr_enable_on_init;
+
+static struct omap_device_pm_latency omap_sr_latency[] = {
+        {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST
+        },
+};
+
+/* Read EFUSE values from control registers for OMAP3430 */
+static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
+                                struct omap_sr_data *sr_data)
+{
+        struct omap_sr_nvalue_table *nvalue_table;
+        int i, count = 0;
+
+        while (volt_data[count].volt_nominal)
+                count++;
+
+        nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count,
+                        GFP_KERNEL);
+
+        for (i = 0; i < count; i++) {
+                u32 v;
+                /*
+                 * In OMAP4 the efuse registers are 24 bit aligned.
+                 * A __raw_readl will fail for non-32 bit aligned address
+                 * and hence the 8-bit read and shift.
+                 */
+                if (cpu_is_omap44xx()) {
+                        u16 offset = volt_data[i].sr_efuse_offs;
+
+                        v = omap_ctrl_readb(offset) |
+                                omap_ctrl_readb(offset + 1) << 8 |
+                                omap_ctrl_readb(offset + 2) << 16;
+                } else {
+                         v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+                }
+
+                nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
+                nvalue_table[i].nvalue = v;
+        }
+
+        sr_data->nvalue_table = nvalue_table;
+        sr_data->nvalue_count = count;
+}
+
+static int sr_dev_init(struct omap_hwmod *oh, void *user)
+{
+        struct omap_sr_data *sr_data;
+        struct omap_device *od;
+        struct omap_volt_data *volt_data;
+        char *name = "smartreflex";
+        static int i;
+
+        sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL);
+        if (!sr_data) {
+                pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n",
+                        __func__, oh->name);
+                return -ENOMEM;
+        }
+
+        if (!oh->vdd_name) {
+                pr_err("%s: No voltage domain specified for %s."
+                        "Cannot initialize\n", __func__, oh->name);
+                goto exit;
+        }
+
+        sr_data->ip_type = oh->class->rev;
+        sr_data->senn_mod = 0x1;
+        sr_data->senp_mod = 0x1;
+
+        sr_data->voltdm = omap_voltage_domain_lookup(oh->vdd_name);
+        if (IS_ERR(sr_data->voltdm)) {
+                pr_err("%s: Unable to get voltage domain pointer for VDD %s\n",
+                        __func__, oh->vdd_name);
+                goto exit;
+        }
+
+        omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
+        if (!volt_data) {
+                pr_warning("%s: No Voltage table registerd fo VDD%d."
+                        "Something really wrong\n\n", __func__, i + 1);
+                goto exit;
+        }
+
+        sr_set_nvalues(volt_data, sr_data);
+
+        sr_data->enable_on_init = sr_enable_on_init;
+
+        od = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
+                               omap_sr_latency,
+                               ARRAY_SIZE(omap_sr_latency), 0);
+        if (IS_ERR(od))
+                pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
+                        __func__, name, oh->name);
+exit:
+        i++;
+        kfree(sr_data);
+        return 0;
+}
+
+/*
+ * API to be called from board files to enable smartreflex
+ * autocompensation at init.
+ */
+void __init omap_enable_smartreflex_on_init(void)
+{
+        sr_enable_on_init = true;
+}
+
+int __init omap_devinit_smartreflex(void)
+{
+        return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL);
+}
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 92e6e1a12af8..055310cc77de 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -21,14 +21,20 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
+ *
+ * Richard Woodruff notes that any changes to this code must be carefully
+ * audited and tested to ensure that they don't cause a TLB miss while
+ * the SDRAM is inaccessible.  Such a situation will crash the system
+ * since it will cause the ARM MMU to attempt to walk the page tables.
+ * These crashes may be intermittent.
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/io.h>
 #include <mach/hardware.h>
 
-#include "prm.h"
-#include "cm.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
 #include "sdrc.h"
 
         .text
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index ab4973695c71..f9007580aea3 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -21,14 +21,20 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
+ *
+ * Richard Woodruff notes that any changes to this code must be carefully
+ * audited and tested to ensure that they don't cause a TLB miss while
+ * the SDRAM is inaccessible.  Such a situation will crash the system
+ * since it will cause the ARM MMU to attempt to walk the page tables.
+ * These crashes may be intermittent.
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/io.h>
 #include <mach/hardware.h>
 
-#include "prm.h"
-#include "cm.h"
+#include "prm2xxx_3xxx.h"
+#include "cm2xxx_3xxx.h"
 #include "sdrc.h"
 
         .text
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 3637274af5be..7f893a29d500 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -32,7 +32,7 @@
 #include <mach/io.h>
 
 #include "sdrc.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 
         .text
 
@@ -104,6 +104,12 @@
  * touching the SDRAM.  Until that time, users who know that their use case
  * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
  * option.
+ *
+ * Richard Woodruff notes that any changes to this code must be carefully
+ * audited and tested to ensure that they don't cause a TLB miss while
+ * the SDRAM is inaccessible.  Such a situation will crash the system
+ * since it will cause the ARM MMU to attempt to walk the page tables.
+ * These crashes may be intermittent.
  */
 ENTRY(omap3_sram_configure_core_dpll)
         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index e13c29eecf2b..4e48e786bec7 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -195,7 +195,6 @@ static struct clocksource clocksource_gpt = {
         .rating         = 300,
         .read           = clocksource_read_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 24,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -203,7 +202,7 @@ static struct clocksource clocksource_gpt = {
 static void __init omap2_gp_clocksource_init(void)
 {
         static struct omap_dm_timer *gpt;
-        u32 tick_rate, tick_period;
+        u32 tick_rate;
         static char err1[] __initdata = KERN_ERR
                 "%s: failed to request dm-timer\n";
         static char err2[] __initdata = KERN_ERR
@@ -216,13 +215,10 @@ static void __init omap2_gp_clocksource_init(void)
 
         omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
-        tick_period = (tick_rate / HZ) - 1;
 
         omap_dm_timer_set_load_start(gpt, 1, 0);
 
-        clocksource_gpt.mult =
-                clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
-        if (clocksource_register(&clocksource_gpt))
+        if (clocksource_register_hz(&clocksource_gpt, tick_rate))
                 printk(err2, clocksource_gpt.name);
 }
 #endif
diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
index b11bf385d360..25eeadabc39b 100644
--- a/arch/arm/mach-omap2/usb-ehci.c
+++ b/arch/arm/mach-omap2/usb-ehci.c
@@ -34,22 +34,15 @@
 
 static struct resource ehci_resources[] = {
         {
-                .start  = OMAP34XX_EHCI_BASE,
-                .end    = OMAP34XX_EHCI_BASE + SZ_1K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = OMAP34XX_UHH_CONFIG_BASE,
-                .end    = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = OMAP34XX_USBTLL_BASE,
-                .end    = OMAP34XX_USBTLL_BASE + SZ_4K - 1,
                 .flags  = IORESOURCE_MEM,
         },
         {         /* general IRQ */
-                .start   = INT_34XX_EHCI_IRQ,
                 .flags   = IORESOURCE_IRQ,
         }
 };
@@ -214,13 +207,148 @@ static void setup_ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode)
         return;
 }
 
+static void setup_4430ehci_io_mux(const enum ehci_hcd_omap_mode *port_mode)
+{
+        switch (port_mode[0]) {
+        case EHCI_HCD_OMAP_MODE_PHY:
+                omap_mux_init_signal("usbb1_ulpiphy_stp",
+                        OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("usbb1_ulpiphy_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpiphy_dat7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                        break;
+        case EHCI_HCD_OMAP_MODE_TLL:
+                omap_mux_init_signal("usbb1_ulpitll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("usbb1_ulpitll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb1_ulpitll_dat7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                        break;
+        case EHCI_HCD_OMAP_MODE_UNKNOWN:
+        default:
+                        break;
+        }
+        switch (port_mode[1]) {
+        case EHCI_HCD_OMAP_MODE_PHY:
+                omap_mux_init_signal("usbb2_ulpiphy_stp",
+                        OMAP_PIN_OUTPUT);
+                omap_mux_init_signal("usbb2_ulpiphy_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpiphy_dat7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                        break;
+        case EHCI_HCD_OMAP_MODE_TLL:
+                omap_mux_init_signal("usbb2_ulpitll_stp",
+                        OMAP_PIN_INPUT_PULLUP);
+                omap_mux_init_signal("usbb2_ulpitll_clk",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dir",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_nxt",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat0",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat1",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat2",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat3",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat4",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat5",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat6",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                omap_mux_init_signal("usbb2_ulpitll_dat7",
+                        OMAP_PIN_INPUT_PULLDOWN);
+                        break;
+        case EHCI_HCD_OMAP_MODE_UNKNOWN:
+        default:
+                        break;
+        }
+}
+
 void __init usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata)
 {
         platform_device_add_data(&ehci_device, pdata, sizeof(*pdata));
 
         /* Setup Pin IO MUX for EHCI */
-        if (cpu_is_omap34xx())
+        if (cpu_is_omap34xx()) {
+                ehci_resources[0].start = OMAP34XX_EHCI_BASE;
+                ehci_resources[0].end   = OMAP34XX_EHCI_BASE + SZ_1K - 1;
+                ehci_resources[1].start = OMAP34XX_UHH_CONFIG_BASE;
+                ehci_resources[1].end   = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1;
+                ehci_resources[2].start = OMAP34XX_USBTLL_BASE;
+                ehci_resources[2].end   = OMAP34XX_USBTLL_BASE + SZ_4K - 1;
+                ehci_resources[3].start = INT_34XX_EHCI_IRQ;
                 setup_ehci_io_mux(pdata->port_mode);
+        } else if (cpu_is_omap44xx()) {
+                ehci_resources[0].start = OMAP44XX_HSUSB_EHCI_BASE;
+                ehci_resources[0].end   = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1;
+                ehci_resources[1].start = OMAP44XX_UHH_CONFIG_BASE;
+                ehci_resources[1].end   = OMAP44XX_UHH_CONFIG_BASE + SZ_2K - 1;
+                ehci_resources[2].start = OMAP44XX_USBTLL_BASE;
+                ehci_resources[2].end   = OMAP44XX_USBTLL_BASE + SZ_4K - 1;
+                ehci_resources[3].start = OMAP44XX_IRQ_EHCI;
+                setup_4430ehci_io_mux(pdata->port_mode);
+        }
 
         if (platform_device_register(&ehci_device) < 0) {
                 printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 72605584bfff..5298949d4b11 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -30,8 +30,101 @@
 #include <mach/irqs.h>
 #include <mach/am35xx.h>
 #include <plat/usb.h>
+#include "control.h"
 
-#ifdef CONFIG_USB_MUSB_SOC
+#if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X)
+
+static void am35x_musb_reset(void)
+{
+        u32     regval;
+
+        /* Reset the musb interface */
+        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+
+        regval |= AM35XX_USBOTGSS_SW_RST;
+        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+
+        regval &= ~AM35XX_USBOTGSS_SW_RST;
+        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+}
+
+static void am35x_musb_phy_power(u8 on)
+{
+        unsigned long timeout = jiffies + msecs_to_jiffies(100);
+        u32 devconf2;
+
+        if (on) {
+                /*
+                 * Start the on-chip PHY and its PLL.
+                 */
+                devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+                devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN);
+                devconf2 |= CONF2_PHY_PLLON;
+
+                omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+
+                pr_info(KERN_INFO "Waiting for PHY clock good...\n");
+                while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2)
+                                & CONF2_PHYCLKGD)) {
+                        cpu_relax();
+
+                        if (time_after(jiffies, timeout)) {
+                                pr_err(KERN_ERR "musb PHY clock good timed out\n");
+                                break;
+                        }
+                }
+        } else {
+                /*
+                 * Power down the on-chip PHY.
+                 */
+                devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+                devconf2 &= ~CONF2_PHY_PLLON;
+                devconf2 |=  CONF2_PHYPWRDN | CONF2_OTGPWRDN;
+                omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+        }
+}
+
+static void am35x_musb_clear_irq(void)
+{
+        u32 regval;
+
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval |= AM35XX_USBOTGSS_INT_CLR;
+        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+}
+
+static void am35x_musb_set_mode(u8 musb_mode)
+{
+        u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
+
+        devconf2 &= ~CONF2_OTGMODE;
+        switch (musb_mode) {
+#ifdef  CONFIG_USB_MUSB_HDRC_HCD
+        case MUSB_HOST:         /* Force VBUS valid, ID = 0 */
+                devconf2 |= CONF2_FORCE_HOST;
+                break;
+#endif
+#ifdef  CONFIG_USB_GADGET_MUSB_HDRC
+        case MUSB_PERIPHERAL:   /* Force VBUS valid, ID = 1 */
+                devconf2 |= CONF2_FORCE_DEVICE;
+                break;
+#endif
+#ifdef  CONFIG_USB_MUSB_OTG
+        case MUSB_OTG:          /* Don't override the VBUS/ID comparators */
+                devconf2 |= CONF2_NO_OVERRIDE;
+                break;
+#endif
+        default:
+                pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
+        }
+
+        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
+}
 
 static struct resource musb_resources[] = {
         [0] = { /* start and end set dynamically */
@@ -40,10 +133,12 @@ static struct resource musb_resources[] = {
         [1] = { /* general IRQ */
                 .start  = INT_243X_HS_USB_MC,
                 .flags  = IORESOURCE_IRQ,
+                .name   = "mc",
         },
         [2] = { /* DMA IRQ */
                 .start  = INT_243X_HS_USB_DMA,
                 .flags  = IORESOURCE_IRQ,
+                .name   = "dma",
         },
 };
 
@@ -75,7 +170,7 @@ static struct musb_hdrc_platform_data musb_plat = {
 static u64 musb_dmamask = DMA_BIT_MASK(32);
 
 static struct platform_device musb_device = {
-        .name           = "musb_hdrc",
+        .name           = "musb-omap2430",
         .id             = -1,
         .dev = {
                 .dma_mask               = &musb_dmamask,
@@ -91,8 +186,13 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
         if (cpu_is_omap243x()) {
                 musb_resources[0].start = OMAP243X_HS_BASE;
         } else if (cpu_is_omap3517() || cpu_is_omap3505()) {
+                musb_device.name = "musb-am35x";
                 musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE;
                 musb_resources[1].start = INT_35XX_USBOTG_IRQ;
+                board_data->set_phy_power = am35x_musb_phy_power;
+                board_data->clear_irq = am35x_musb_clear_irq;
+                board_data->set_mode = am35x_musb_set_mode;
+                board_data->reset = am35x_musb_reset;
         } else if (cpu_is_omap34xx()) {
                 musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE;
         } else if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 64a0112b70a5..8a3c05f3c1d6 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -120,8 +120,8 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
         t.adv_on = next_clk(t.cs_on, t_scsnh_advnh - 7000, fclk_ps);
 
         /* GPMC_CLK rate = fclk rate / div */
-        t.sync_clk = 12 /* 11.1 nsec */;
-        tmp = (t.sync_clk * 1000 + fclk_ps - 1) / fclk_ps;
+        t.sync_clk = 11100 /* 11.1 nsec */;
+        tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
         if (tmp > 4)
                 return -ERANGE;
         if (tmp <= 0)
@@ -216,6 +216,7 @@ static struct resource tusb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         { /* IRQ */
+                .name   = "mc",
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -223,7 +224,7 @@ static struct resource tusb_resources[] = {
 static u64 tusb_dmamask = ~(u32)0;
 
 static struct platform_device tusb_device = {
-        .name           = "musb_hdrc",
+        .name           = "musb-tusb",
         .id             = -1,
         .dev = {
                 .dma_mask               = &tusb_dmamask,
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
new file mode 100644
index 000000000000..ed6079c94c57
--- /dev/null
+++ b/arch/arm/mach-omap2/voltage.c
@@ -0,0 +1,1571 @@
+/*
+ * OMAP3/OMAP4 Voltage Management Routines
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Rajendra Nayak <rnayak@ti.com>
+ * Lesly A M <x0080970@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+
+#include <plat/common.h>
+#include <plat/voltage.h>
+
+#include "prm-regbits-34xx.h"
+#include "prm-regbits-44xx.h"
+#include "prm44xx.h"
+#include "prcm44xx.h"
+#include "prminst44xx.h"
+#include "control.h"
+
+#define VP_IDLE_TIMEOUT         200
+#define VP_TRANXDONE_TIMEOUT    300
+#define VOLTAGE_DIR_SIZE        16
+
+/* Voltage processor register offsets */
+struct vp_reg_offs {
+        u8 vpconfig;
+        u8 vstepmin;
+        u8 vstepmax;
+        u8 vlimitto;
+        u8 vstatus;
+        u8 voltage;
+};
+
+/* Voltage Processor bit field values, shifts and masks */
+struct vp_reg_val {
+        /* PRM module */
+        u16 prm_mod;
+        /* VPx_VPCONFIG */
+        u32 vpconfig_erroroffset;
+        u16 vpconfig_errorgain;
+        u32 vpconfig_errorgain_mask;
+        u8 vpconfig_errorgain_shift;
+        u32 vpconfig_initvoltage_mask;
+        u8 vpconfig_initvoltage_shift;
+        u32 vpconfig_timeouten;
+        u32 vpconfig_initvdd;
+        u32 vpconfig_forceupdate;
+        u32 vpconfig_vpenable;
+        /* VPx_VSTEPMIN */
+        u8 vstepmin_stepmin;
+        u16 vstepmin_smpswaittimemin;
+        u8 vstepmin_stepmin_shift;
+        u8 vstepmin_smpswaittimemin_shift;
+        /* VPx_VSTEPMAX */
+        u8 vstepmax_stepmax;
+        u16 vstepmax_smpswaittimemax;
+        u8 vstepmax_stepmax_shift;
+        u8 vstepmax_smpswaittimemax_shift;
+        /* VPx_VLIMITTO */
+        u8 vlimitto_vddmin;
+        u8 vlimitto_vddmax;
+        u16 vlimitto_timeout;
+        u8 vlimitto_vddmin_shift;
+        u8 vlimitto_vddmax_shift;
+        u8 vlimitto_timeout_shift;
+        /* PRM_IRQSTATUS*/
+        u32 tranxdone_status;
+};
+
+/* Voltage controller registers and offsets */
+struct vc_reg_info {
+        /* PRM module */
+        u16 prm_mod;
+        /* VC register offsets */
+        u8 smps_sa_reg;
+        u8 smps_volra_reg;
+        u8 bypass_val_reg;
+        u8 cmdval_reg;
+        u8 voltsetup_reg;
+        /*VC_SMPS_SA*/
+        u8 smps_sa_shift;
+        u32 smps_sa_mask;
+        /* VC_SMPS_VOL_RA */
+        u8 smps_volra_shift;
+        u32 smps_volra_mask;
+        /* VC_BYPASS_VAL */
+        u8 data_shift;
+        u8 slaveaddr_shift;
+        u8 regaddr_shift;
+        u32 valid;
+        /* VC_CMD_VAL */
+        u8 cmd_on_shift;
+        u8 cmd_onlp_shift;
+        u8 cmd_ret_shift;
+        u8 cmd_off_shift;
+        u32 cmd_on_mask;
+        /* PRM_VOLTSETUP */
+        u8 voltsetup_shift;
+        u32 voltsetup_mask;
+};
+
+/**
+ * omap_vdd_info - Per Voltage Domain info
+ *
+ * @volt_data           : voltage table having the distinct voltages supported
+ *                        by the domain and other associated per voltage data.
+ * @pmic_info           : pmic specific parameters which should be populted by
+ *                        the pmic drivers.
+ * @vp_offs             : structure containing the offsets for various
+ *                        vp registers
+ * @vp_reg              : the register values, shifts, masks for various
+ *                        vp registers
+ * @vc_reg              : structure containing various various vc registers,
+ *                        shifts, masks etc.
+ * @voltdm              : pointer to the voltage domain structure
+ * @debug_dir           : debug directory for this voltage domain.
+ * @curr_volt           : current voltage for this vdd.
+ * @ocp_mod             : The prm module for accessing the prm irqstatus reg.
+ * @prm_irqst_reg       : prm irqstatus register.
+ * @vp_enabled          : flag to keep track of whether vp is enabled or not
+ * @volt_scale          : API to scale the voltage of the vdd.
+ */
+struct omap_vdd_info {
+        struct omap_volt_data *volt_data;
+        struct omap_volt_pmic_info *pmic_info;
+        struct vp_reg_offs vp_offs;
+        struct vp_reg_val vp_reg;
+        struct vc_reg_info vc_reg;
+        struct voltagedomain voltdm;
+        struct dentry *debug_dir;
+        u32 curr_volt;
+        u16 ocp_mod;
+        u8 prm_irqst_reg;
+        bool vp_enabled;
+        u32 (*read_reg) (u16 mod, u8 offset);
+        void (*write_reg) (u32 val, u16 mod, u8 offset);
+        int (*volt_scale) (struct omap_vdd_info *vdd,
+                unsigned long target_volt);
+};
+
+static struct omap_vdd_info *vdd_info;
+/*
+ * Number of scalable voltage domains.
+ */
+static int nr_scalable_vdd;
+
+/* OMAP3 VDD sturctures */
+static struct omap_vdd_info omap3_vdd_info[] = {
+        {
+                .vp_offs = {
+                        .vpconfig = OMAP3_PRM_VP1_CONFIG_OFFSET,
+                        .vstepmin = OMAP3_PRM_VP1_VSTEPMIN_OFFSET,
+                        .vstepmax = OMAP3_PRM_VP1_VSTEPMAX_OFFSET,
+                        .vlimitto = OMAP3_PRM_VP1_VLIMITTO_OFFSET,
+                        .vstatus = OMAP3_PRM_VP1_STATUS_OFFSET,
+                        .voltage = OMAP3_PRM_VP1_VOLTAGE_OFFSET,
+                },
+                .voltdm = {
+                        .name = "mpu",
+                },
+        },
+        {
+                .vp_offs = {
+                        .vpconfig = OMAP3_PRM_VP2_CONFIG_OFFSET,
+                        .vstepmin = OMAP3_PRM_VP2_VSTEPMIN_OFFSET,
+                        .vstepmax = OMAP3_PRM_VP2_VSTEPMAX_OFFSET,
+                        .vlimitto = OMAP3_PRM_VP2_VLIMITTO_OFFSET,
+                        .vstatus = OMAP3_PRM_VP2_STATUS_OFFSET,
+                        .voltage = OMAP3_PRM_VP2_VOLTAGE_OFFSET,
+                },
+                .voltdm = {
+                        .name = "core",
+                },
+        },
+};
+
+#define OMAP3_NR_SCALABLE_VDD ARRAY_SIZE(omap3_vdd_info)
+
+/* OMAP4 VDD sturctures */
+static struct omap_vdd_info omap4_vdd_info[] = {
+        {
+                .vp_offs = {
+                        .vpconfig = OMAP4_PRM_VP_MPU_CONFIG_OFFSET,
+                        .vstepmin = OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET,
+                        .vstepmax = OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET,
+                        .vlimitto = OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET,
+                        .vstatus = OMAP4_PRM_VP_MPU_STATUS_OFFSET,
+                        .voltage = OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET,
+                },
+                .voltdm = {
+                        .name = "mpu",
+                },
+        },
+        {
+                .vp_offs = {
+                        .vpconfig = OMAP4_PRM_VP_IVA_CONFIG_OFFSET,
+                        .vstepmin = OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET,
+                        .vstepmax = OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET,
+                        .vlimitto = OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET,
+                        .vstatus = OMAP4_PRM_VP_IVA_STATUS_OFFSET,
+                        .voltage = OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET,
+                },
+                .voltdm = {
+                        .name = "iva",
+                },
+        },
+        {
+                .vp_offs = {
+                        .vpconfig = OMAP4_PRM_VP_CORE_CONFIG_OFFSET,
+                        .vstepmin = OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET,
+                        .vstepmax = OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET,
+                        .vlimitto = OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET,
+                        .vstatus = OMAP4_PRM_VP_CORE_STATUS_OFFSET,
+                        .voltage = OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET,
+                },
+                .voltdm = {
+                        .name = "core",
+                },
+        },
+};
+
+#define OMAP4_NR_SCALABLE_VDD ARRAY_SIZE(omap4_vdd_info)
+
+/*
+ * Structures containing OMAP3430/OMAP3630 voltage supported and various
+ * voltage dependent data for each VDD.
+ */
+#define VOLT_DATA_DEFINE(_v_nom, _efuse_offs, _errminlimit, _errgain)   \
+{                                                                       \
+        .volt_nominal   = _v_nom,                                       \
+        .sr_efuse_offs  = _efuse_offs,                                  \
+        .sr_errminlimit = _errminlimit,                                 \
+        .vp_errgain     = _errgain                                      \
+}
+
+/* VDD1 */
+static struct omap_volt_data omap34xx_vddmpu_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD1, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD1, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD1, 0xf9, 0x18),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP4_UV, OMAP343X_CONTROL_FUSE_OPP4_VDD1, 0xf9, 0x18),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_MPU_OPP5_UV, OMAP343X_CONTROL_FUSE_OPP5_VDD1, 0xf9, 0x18),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+static struct omap_volt_data omap36xx_vddmpu_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD1, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD1, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP120_UV, OMAP3630_CONTROL_FUSE_OPP120_VDD1, 0xfa, 0x23),
+        VOLT_DATA_DEFINE(OMAP3630_VDD_MPU_OPP1G_UV, OMAP3630_CONTROL_FUSE_OPP1G_VDD1, 0xfa, 0x27),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+/* VDD2 */
+static struct omap_volt_data omap34xx_vddcore_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP1_UV, OMAP343X_CONTROL_FUSE_OPP1_VDD2, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP2_UV, OMAP343X_CONTROL_FUSE_OPP2_VDD2, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3430_VDD_CORE_OPP3_UV, OMAP343X_CONTROL_FUSE_OPP3_VDD2, 0xf9, 0x18),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+static struct omap_volt_data omap36xx_vddcore_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP50_UV, OMAP3630_CONTROL_FUSE_OPP50_VDD2, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP3630_VDD_CORE_OPP100_UV, OMAP3630_CONTROL_FUSE_OPP100_VDD2, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+/*
+ * Structures containing OMAP4430 voltage supported and various
+ * voltage dependent data for each VDD.
+ */
+static struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+static struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+static struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
+        VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
+        VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
+        VOLT_DATA_DEFINE(0, 0, 0, 0),
+};
+
+static struct dentry *voltage_dir;
+
+/* Init function pointers */
+static void (*vc_init) (struct omap_vdd_info *vdd);
+static int (*vdd_data_configure) (struct omap_vdd_info *vdd);
+
+static u32 omap3_voltage_read_reg(u16 mod, u8 offset)
+{
+        return omap2_prm_read_mod_reg(mod, offset);
+}
+
+static void omap3_voltage_write_reg(u32 val, u16 mod, u8 offset)
+{
+        omap2_prm_write_mod_reg(val, mod, offset);
+}
+
+static u32 omap4_voltage_read_reg(u16 mod, u8 offset)
+{
+        return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                                        mod, offset);
+}
+
+static void omap4_voltage_write_reg(u32 val, u16 mod, u8 offset)
+{
+        omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, mod, offset);
+}
+
+/* Voltage debugfs support */
+static int vp_volt_debug_get(void *data, u64 *val)
+{
+        struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
+        u8 vsel;
+
+        if (!vdd) {
+                pr_warning("Wrong paramater passed\n");
+                return -EINVAL;
+        }
+
+        vsel = vdd->read_reg(vdd->vp_reg.prm_mod, vdd->vp_offs.voltage);
+        pr_notice("curr_vsel = %x\n", vsel);
+
+        if (!vdd->pmic_info->vsel_to_uv) {
+                pr_warning("PMIC function to convert vsel to voltage"
+                        "in uV not registerd\n");
+                return -EINVAL;
+        }
+
+        *val = vdd->pmic_info->vsel_to_uv(vsel);
+        return 0;
+}
+
+static int nom_volt_debug_get(void *data, u64 *val)
+{
+        struct omap_vdd_info *vdd = (struct omap_vdd_info *) data;
+
+        if (!vdd) {
+                pr_warning("Wrong paramater passed\n");
+                return -EINVAL;
+        }
+
+        *val = omap_voltage_get_nom_volt(&vdd->voltdm);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(vp_volt_debug_fops, vp_volt_debug_get, NULL, "%llu\n");
+DEFINE_SIMPLE_ATTRIBUTE(nom_volt_debug_fops, nom_volt_debug_get, NULL,
+                                                                "%llu\n");
+static void vp_latch_vsel(struct omap_vdd_info *vdd)
+{
+        u32 vpconfig;
+        u16 mod;
+        unsigned long uvdc;
+        char vsel;
+
+        uvdc = omap_voltage_get_nom_volt(&vdd->voltdm);
+        if (!uvdc) {
+                pr_warning("%s: unable to find current voltage for vdd_%s\n",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+
+        if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+                pr_warning("%s: PMIC function to convert voltage in uV to"
+                        " vsel not registered\n", __func__);
+                return;
+        }
+
+        mod = vdd->vp_reg.prm_mod;
+
+        vsel = vdd->pmic_info->uv_to_vsel(uvdc);
+
+        vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
+        vpconfig &= ~(vdd->vp_reg.vpconfig_initvoltage_mask |
+                        vdd->vp_reg.vpconfig_initvdd);
+        vpconfig |= vsel << vdd->vp_reg.vpconfig_initvoltage_shift;
+
+        vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+
+        /* Trigger initVDD value copy to voltage processor */
+        vdd->write_reg((vpconfig | vdd->vp_reg.vpconfig_initvdd), mod,
+                        vdd->vp_offs.vpconfig);
+
+        /* Clear initVDD copy trigger bit */
+        vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+}
+
+/* Generic voltage init functions */
+static void __init vp_init(struct omap_vdd_info *vdd)
+{
+        u32 vp_val;
+        u16 mod;
+
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+
+        mod = vdd->vp_reg.prm_mod;
+
+        vp_val = vdd->vp_reg.vpconfig_erroroffset |
+                (vdd->vp_reg.vpconfig_errorgain <<
+                vdd->vp_reg.vpconfig_errorgain_shift) |
+                vdd->vp_reg.vpconfig_timeouten;
+        vdd->write_reg(vp_val, mod, vdd->vp_offs.vpconfig);
+
+        vp_val = ((vdd->vp_reg.vstepmin_smpswaittimemin <<
+                vdd->vp_reg.vstepmin_smpswaittimemin_shift) |
+                (vdd->vp_reg.vstepmin_stepmin <<
+                vdd->vp_reg.vstepmin_stepmin_shift));
+        vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmin);
+
+        vp_val = ((vdd->vp_reg.vstepmax_smpswaittimemax <<
+                vdd->vp_reg.vstepmax_smpswaittimemax_shift) |
+                (vdd->vp_reg.vstepmax_stepmax <<
+                vdd->vp_reg.vstepmax_stepmax_shift));
+        vdd->write_reg(vp_val, mod, vdd->vp_offs.vstepmax);
+
+        vp_val = ((vdd->vp_reg.vlimitto_vddmax <<
+                vdd->vp_reg.vlimitto_vddmax_shift) |
+                (vdd->vp_reg.vlimitto_vddmin <<
+                vdd->vp_reg.vlimitto_vddmin_shift) |
+                (vdd->vp_reg.vlimitto_timeout <<
+                vdd->vp_reg.vlimitto_timeout_shift));
+        vdd->write_reg(vp_val, mod, vdd->vp_offs.vlimitto);
+}
+
+static void __init vdd_debugfs_init(struct omap_vdd_info *vdd)
+{
+        char *name;
+
+        name = kzalloc(VOLTAGE_DIR_SIZE, GFP_KERNEL);
+        if (!name) {
+                pr_warning("%s: Unable to allocate memory for debugfs"
+                        " directory name for vdd_%s",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+        strcpy(name, "vdd_");
+        strcat(name, vdd->voltdm.name);
+
+        vdd->debug_dir = debugfs_create_dir(name, voltage_dir);
+        if (IS_ERR(vdd->debug_dir)) {
+                pr_warning("%s: Unable to create debugfs directory for"
+                        " vdd_%s\n", __func__, vdd->voltdm.name);
+                vdd->debug_dir = NULL;
+                return;
+        }
+
+        (void) debugfs_create_x16("vp_errorgain", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_reg.vpconfig_errorgain));
+        (void) debugfs_create_x16("vp_smpswaittimemin", S_IRUGO,
+                                vdd->debug_dir,
+                                &(vdd->vp_reg.vstepmin_smpswaittimemin));
+        (void) debugfs_create_x8("vp_stepmin", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_reg.vstepmin_stepmin));
+        (void) debugfs_create_x16("vp_smpswaittimemax", S_IRUGO,
+                                vdd->debug_dir,
+                                &(vdd->vp_reg.vstepmax_smpswaittimemax));
+        (void) debugfs_create_x8("vp_stepmax", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_reg.vstepmax_stepmax));
+        (void) debugfs_create_x8("vp_vddmax", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_reg.vlimitto_vddmax));
+        (void) debugfs_create_x8("vp_vddmin", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_reg.vlimitto_vddmin));
+        (void) debugfs_create_x16("vp_timeout", S_IRUGO, vdd->debug_dir,
+                                &(vdd->vp_reg.vlimitto_timeout));
+        (void) debugfs_create_file("curr_vp_volt", S_IRUGO, vdd->debug_dir,
+                                (void *) vdd, &vp_volt_debug_fops);
+        (void) debugfs_create_file("curr_nominal_volt", S_IRUGO,
+                                vdd->debug_dir, (void *) vdd,
+                                &nom_volt_debug_fops);
+}
+
+/* Voltage scale and accessory APIs */
+static int _pre_volt_scale(struct omap_vdd_info *vdd,
+                unsigned long target_volt, u8 *target_vsel, u8 *current_vsel)
+{
+        struct omap_volt_data *volt_data;
+        u32 vc_cmdval, vp_errgain_val;
+        u16 vp_mod, vc_mod;
+
+        /* Check if suffiecient pmic info is available for this vdd */
+        if (!vdd->pmic_info) {
+                pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
+                        __func__, vdd->voltdm.name);
+                return -EINVAL;
+        }
+
+        if (!vdd->pmic_info->uv_to_vsel) {
+                pr_err("%s: PMIC function to convert voltage in uV to"
+                        "vsel not registered. Hence unable to scale voltage"
+                        "for vdd_%s\n", __func__, vdd->voltdm.name);
+                return -ENODATA;
+        }
+
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, vdd->voltdm.name);
+                return -EINVAL;
+        }
+
+        vp_mod = vdd->vp_reg.prm_mod;
+        vc_mod = vdd->vc_reg.prm_mod;
+
+        /* Get volt_data corresponding to target_volt */
+        volt_data = omap_voltage_get_voltdata(&vdd->voltdm, target_volt);
+        if (IS_ERR(volt_data))
+                volt_data = NULL;
+
+        *target_vsel = vdd->pmic_info->uv_to_vsel(target_volt);
+        *current_vsel = vdd->read_reg(vp_mod, vdd->vp_offs.voltage);
+
+        /* Setting the ON voltage to the new target voltage */
+        vc_cmdval = vdd->read_reg(vc_mod, vdd->vc_reg.cmdval_reg);
+        vc_cmdval &= ~vdd->vc_reg.cmd_on_mask;
+        vc_cmdval |= (*target_vsel << vdd->vc_reg.cmd_on_shift);
+        vdd->write_reg(vc_cmdval, vc_mod, vdd->vc_reg.cmdval_reg);
+
+        /* Setting vp errorgain based on the voltage */
+        if (volt_data) {
+                vp_errgain_val = vdd->read_reg(vp_mod,
+                                vdd->vp_offs.vpconfig);
+                vdd->vp_reg.vpconfig_errorgain = volt_data->vp_errgain;
+                vp_errgain_val &= ~vdd->vp_reg.vpconfig_errorgain_mask;
+                vp_errgain_val |= vdd->vp_reg.vpconfig_errorgain <<
+                                vdd->vp_reg.vpconfig_errorgain_shift;
+                vdd->write_reg(vp_errgain_val, vp_mod,
+                                vdd->vp_offs.vpconfig);
+        }
+
+        return 0;
+}
+
+static void _post_volt_scale(struct omap_vdd_info *vdd,
+                unsigned long target_volt, u8 target_vsel, u8 current_vsel)
+{
+        u32 smps_steps = 0, smps_delay = 0;
+
+        smps_steps = abs(target_vsel - current_vsel);
+        /* SMPS slew rate / step size. 2us added as buffer. */
+        smps_delay = ((smps_steps * vdd->pmic_info->step_size) /
+                        vdd->pmic_info->slew_rate) + 2;
+        udelay(smps_delay);
+
+        vdd->curr_volt = target_volt;
+}
+
+/* vc_bypass_scale_voltage - VC bypass method of voltage scaling */
+static int vc_bypass_scale_voltage(struct omap_vdd_info *vdd,
+                unsigned long target_volt)
+{
+        u32 loop_cnt = 0, retries_cnt = 0;
+        u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
+        u16 mod;
+        u8 target_vsel, current_vsel;
+        int ret;
+
+        ret = _pre_volt_scale(vdd, target_volt, &target_vsel, &current_vsel);
+        if (ret)
+                return ret;
+
+        mod = vdd->vc_reg.prm_mod;
+
+        vc_valid = vdd->vc_reg.valid;
+        vc_bypass_val_reg = vdd->vc_reg.bypass_val_reg;
+        vc_bypass_value = (target_vsel << vdd->vc_reg.data_shift) |
+                        (vdd->pmic_info->pmic_reg <<
+                        vdd->vc_reg.regaddr_shift) |
+                        (vdd->pmic_info->i2c_slave_addr <<
+                        vdd->vc_reg.slaveaddr_shift);
+
+        vdd->write_reg(vc_bypass_value, mod, vc_bypass_val_reg);
+        vdd->write_reg(vc_bypass_value | vc_valid, mod, vc_bypass_val_reg);
+
+        vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg);
+        /*
+         * Loop till the bypass command is acknowledged from the SMPS.
+         * NOTE: This is legacy code. The loop count and retry count needs
+         * to be revisited.
+         */
+        while (!(vc_bypass_value & vc_valid)) {
+                loop_cnt++;
+
+                if (retries_cnt > 10) {
+                        pr_warning("%s: Retry count exceeded\n", __func__);
+                        return -ETIMEDOUT;
+                }
+
+                if (loop_cnt > 50) {
+                        retries_cnt++;
+                        loop_cnt = 0;
+                        udelay(10);
+                }
+                vc_bypass_value = vdd->read_reg(mod, vc_bypass_val_reg);
+        }
+
+        _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
+        return 0;
+}
+
+/* VP force update method of voltage scaling */
+static int vp_forceupdate_scale_voltage(struct omap_vdd_info *vdd,
+                unsigned long target_volt)
+{
+        u32 vpconfig;
+        u16 mod, ocp_mod;
+        u8 target_vsel, current_vsel, prm_irqst_reg;
+        int ret, timeout = 0;
+
+        ret = _pre_volt_scale(vdd, target_volt, &target_vsel, &current_vsel);
+        if (ret)
+                return ret;
+
+        mod = vdd->vp_reg.prm_mod;
+        ocp_mod = vdd->ocp_mod;
+        prm_irqst_reg = vdd->prm_irqst_reg;
+
+        /*
+         * Clear all pending TransactionDone interrupt/status. Typical latency
+         * is <3us
+         */
+        while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+                vdd->write_reg(vdd->vp_reg.tranxdone_status,
+                                ocp_mod, prm_irqst_reg);
+                if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) &
+                                vdd->vp_reg.tranxdone_status))
+                                break;
+                udelay(1);
+        }
+        if (timeout >= VP_TRANXDONE_TIMEOUT) {
+                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
+                        "Voltage change aborted", __func__, vdd->voltdm.name);
+                return -ETIMEDOUT;
+        }
+
+        /* Configure for VP-Force Update */
+        vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
+        vpconfig &= ~(vdd->vp_reg.vpconfig_initvdd |
+                        vdd->vp_reg.vpconfig_forceupdate |
+                        vdd->vp_reg.vpconfig_initvoltage_mask);
+        vpconfig |= ((target_vsel <<
+                        vdd->vp_reg.vpconfig_initvoltage_shift));
+        vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+
+        /* Trigger initVDD value copy to voltage processor */
+        vpconfig |= vdd->vp_reg.vpconfig_initvdd;
+        vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+
+        /* Force update of voltage */
+        vpconfig |= vdd->vp_reg.vpconfig_forceupdate;
+        vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+
+        /*
+         * Wait for TransactionDone. Typical latency is <200us.
+         * Depends on SMPSWAITTIMEMIN/MAX and voltage change
+         */
+        timeout = 0;
+        omap_test_timeout((vdd->read_reg(ocp_mod, prm_irqst_reg) &
+                        vdd->vp_reg.tranxdone_status),
+                        VP_TRANXDONE_TIMEOUT, timeout);
+        if (timeout >= VP_TRANXDONE_TIMEOUT)
+                pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
+                        "TRANXDONE never got set after the voltage update\n",
+                        __func__, vdd->voltdm.name);
+
+        _post_volt_scale(vdd, target_volt, target_vsel, current_vsel);
+
+        /*
+         * Disable TransactionDone interrupt , clear all status, clear
+         * control registers
+         */
+        timeout = 0;
+        while (timeout++ < VP_TRANXDONE_TIMEOUT) {
+                vdd->write_reg(vdd->vp_reg.tranxdone_status,
+                                ocp_mod, prm_irqst_reg);
+                if (!(vdd->read_reg(ocp_mod, prm_irqst_reg) &
+                                vdd->vp_reg.tranxdone_status))
+                                break;
+                udelay(1);
+        }
+
+        if (timeout >= VP_TRANXDONE_TIMEOUT)
+                pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
+                        "to clear the TRANXDONE status\n",
+                        __func__, vdd->voltdm.name);
+
+        vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
+        /* Clear initVDD copy trigger bit */
+        vpconfig &= ~vdd->vp_reg.vpconfig_initvdd;;
+        vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+        /* Clear force bit */
+        vpconfig &= ~vdd->vp_reg.vpconfig_forceupdate;
+        vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+
+        return 0;
+}
+
+/* OMAP3 specific voltage init functions */
+
+/*
+ * Intializes the voltage controller registers with the PMIC and board
+ * specific parameters and voltage setup times for OMAP3.
+ */
+static void __init omap3_vc_init(struct omap_vdd_info *vdd)
+{
+        u32 vc_val;
+        u16 mod;
+        u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
+        static bool is_initialized;
+
+        if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+                pr_err("%s: PMIC info requried to configure vc for"
+                        "vdd_%s not populated.Hence cannot initialize vc\n",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+
+        mod = vdd->vc_reg.prm_mod;
+
+        /* Set up the SMPS_SA(i2c slave address in VC */
+        vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg);
+        vc_val &= ~vdd->vc_reg.smps_sa_mask;
+        vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift;
+        vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
+
+        /* Setup the VOLRA(pmic reg addr) in VC */
+        vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg);
+        vc_val &= ~vdd->vc_reg.smps_volra_mask;
+        vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift;
+        vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
+
+        /*Configure the setup times */
+        vc_val = vdd->read_reg(mod, vdd->vc_reg.voltsetup_reg);
+        vc_val &= ~vdd->vc_reg.voltsetup_mask;
+        vc_val |= vdd->pmic_info->volt_setup_time <<
+                        vdd->vc_reg.voltsetup_shift;
+        vdd->write_reg(vc_val, mod, vdd->vc_reg.voltsetup_reg);
+
+        /* Set up the on, inactive, retention and off voltage */
+        on_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->on_volt);
+        onlp_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->onlp_volt);
+        ret_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->ret_volt);
+        off_vsel = vdd->pmic_info->uv_to_vsel(vdd->pmic_info->off_volt);
+        vc_val  = ((on_vsel << vdd->vc_reg.cmd_on_shift) |
+                (onlp_vsel << vdd->vc_reg.cmd_onlp_shift) |
+                (ret_vsel << vdd->vc_reg.cmd_ret_shift) |
+                (off_vsel << vdd->vc_reg.cmd_off_shift));
+        vdd->write_reg(vc_val, mod, vdd->vc_reg.cmdval_reg);
+
+        if (is_initialized)
+                return;
+
+        /* Generic VC parameters init */
+        vdd->write_reg(OMAP3430_CMD1_MASK | OMAP3430_RAV1_MASK, mod,
+                        OMAP3_PRM_VC_CH_CONF_OFFSET);
+        vdd->write_reg(OMAP3430_MCODE_SHIFT | OMAP3430_HSEN_MASK, mod,
+                        OMAP3_PRM_VC_I2C_CFG_OFFSET);
+        vdd->write_reg(OMAP3_CLKSETUP, mod, OMAP3_PRM_CLKSETUP_OFFSET);
+        vdd->write_reg(OMAP3_VOLTOFFSET, mod, OMAP3_PRM_VOLTOFFSET_OFFSET);
+        vdd->write_reg(OMAP3_VOLTSETUP2, mod, OMAP3_PRM_VOLTSETUP2_OFFSET);
+        is_initialized = true;
+}
+
+/* Sets up all the VDD related info for OMAP3 */
+static int __init omap3_vdd_data_configure(struct omap_vdd_info *vdd)
+{
+        struct clk *sys_ck;
+        u32 sys_clk_speed, timeout_val, waittime;
+
+        if (!vdd->pmic_info) {
+                pr_err("%s: PMIC info requried to configure vdd_%s not"
+                        "populated.Hence cannot initialize vdd_%s\n",
+                        __func__, vdd->voltdm.name, vdd->voltdm.name);
+                return -EINVAL;
+        }
+
+        if (!strcmp(vdd->voltdm.name, "mpu")) {
+                if (cpu_is_omap3630())
+                        vdd->volt_data = omap36xx_vddmpu_volt_data;
+                else
+                        vdd->volt_data = omap34xx_vddmpu_volt_data;
+
+                vdd->vp_reg.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK;
+                vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET;
+                vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT;
+                vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK;
+                vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA0_SHIFT;
+                vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA0_MASK;
+                vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME1_SHIFT;
+                vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME1_MASK;
+        } else if (!strcmp(vdd->voltdm.name, "core")) {
+                if (cpu_is_omap3630())
+                        vdd->volt_data = omap36xx_vddcore_volt_data;
+                else
+                        vdd->volt_data = omap34xx_vddcore_volt_data;
+
+                vdd->vp_reg.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK;
+                vdd->vc_reg.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET;
+                vdd->vc_reg.smps_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT;
+                vdd->vc_reg.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK;
+                vdd->vc_reg.smps_volra_shift = OMAP3430_VOLRA1_SHIFT;
+                vdd->vc_reg.smps_volra_mask = OMAP3430_VOLRA1_MASK;
+                vdd->vc_reg.voltsetup_shift = OMAP3430_SETUP_TIME2_SHIFT;
+                vdd->vc_reg.voltsetup_mask = OMAP3430_SETUP_TIME2_MASK;
+        } else {
+                pr_warning("%s: vdd_%s does not exisit in OMAP3\n",
+                        __func__, vdd->voltdm.name);
+                return -EINVAL;
+        }
+
+        /*
+         * Sys clk rate is require to calculate vp timeout value and
+         * smpswaittimemin and smpswaittimemax.
+         */
+        sys_ck = clk_get(NULL, "sys_ck");
+        if (IS_ERR(sys_ck)) {
+                pr_warning("%s: Could not get the sys clk to calculate"
+                        "various vdd_%s params\n", __func__, vdd->voltdm.name);
+                return -EINVAL;
+        }
+        sys_clk_speed = clk_get_rate(sys_ck);
+        clk_put(sys_ck);
+        /* Divide to avoid overflow */
+        sys_clk_speed /= 1000;
+
+        /* Generic voltage parameters */
+        vdd->curr_volt = 1200000;
+        vdd->ocp_mod = OCP_MOD;
+        vdd->prm_irqst_reg = OMAP3_PRM_IRQSTATUS_MPU_OFFSET;
+        vdd->read_reg = omap3_voltage_read_reg;
+        vdd->write_reg = omap3_voltage_write_reg;
+        vdd->volt_scale = vp_forceupdate_scale_voltage;
+        vdd->vp_enabled = false;
+
+        /* VC parameters */
+        vdd->vc_reg.prm_mod = OMAP3430_GR_MOD;
+        vdd->vc_reg.smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET;
+        vdd->vc_reg.smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET;
+        vdd->vc_reg.bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET;
+        vdd->vc_reg.voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET;
+        vdd->vc_reg.data_shift = OMAP3430_DATA_SHIFT;
+        vdd->vc_reg.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT;
+        vdd->vc_reg.regaddr_shift = OMAP3430_REGADDR_SHIFT;
+        vdd->vc_reg.valid = OMAP3430_VALID_MASK;
+        vdd->vc_reg.cmd_on_shift = OMAP3430_VC_CMD_ON_SHIFT;
+        vdd->vc_reg.cmd_on_mask = OMAP3430_VC_CMD_ON_MASK;
+        vdd->vc_reg.cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT;
+        vdd->vc_reg.cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT;
+        vdd->vc_reg.cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT;
+
+        vdd->vp_reg.prm_mod = OMAP3430_GR_MOD;
+
+        /* VPCONFIG bit fields */
+        vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset <<
+                                 OMAP3430_ERROROFFSET_SHIFT);
+        vdd->vp_reg.vpconfig_errorgain_mask = OMAP3430_ERRORGAIN_MASK;
+        vdd->vp_reg.vpconfig_errorgain_shift = OMAP3430_ERRORGAIN_SHIFT;
+        vdd->vp_reg.vpconfig_initvoltage_shift = OMAP3430_INITVOLTAGE_SHIFT;
+        vdd->vp_reg.vpconfig_initvoltage_mask = OMAP3430_INITVOLTAGE_MASK;
+        vdd->vp_reg.vpconfig_timeouten = OMAP3430_TIMEOUTEN_MASK;
+        vdd->vp_reg.vpconfig_initvdd = OMAP3430_INITVDD_MASK;
+        vdd->vp_reg.vpconfig_forceupdate = OMAP3430_FORCEUPDATE_MASK;
+        vdd->vp_reg.vpconfig_vpenable = OMAP3430_VPENABLE_MASK;
+
+        /* VSTEPMIN VSTEPMAX bit fields */
+        waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
+                                sys_clk_speed) / 1000;
+        vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
+        vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
+        vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
+        vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
+        vdd->vp_reg.vstepmin_smpswaittimemin_shift =
+                                OMAP3430_SMPSWAITTIMEMIN_SHIFT;
+        vdd->vp_reg.vstepmax_smpswaittimemax_shift =
+                                OMAP3430_SMPSWAITTIMEMAX_SHIFT;
+        vdd->vp_reg.vstepmin_stepmin_shift = OMAP3430_VSTEPMIN_SHIFT;
+        vdd->vp_reg.vstepmax_stepmax_shift = OMAP3430_VSTEPMAX_SHIFT;
+
+        /* VLIMITTO bit fields */
+        timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
+        vdd->vp_reg.vlimitto_timeout = timeout_val;
+        vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
+        vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
+        vdd->vp_reg.vlimitto_vddmin_shift = OMAP3430_VDDMIN_SHIFT;
+        vdd->vp_reg.vlimitto_vddmax_shift = OMAP3430_VDDMAX_SHIFT;
+        vdd->vp_reg.vlimitto_timeout_shift = OMAP3430_TIMEOUT_SHIFT;
+
+        return 0;
+}
+
+/* OMAP4 specific voltage init functions */
+static void __init omap4_vc_init(struct omap_vdd_info *vdd)
+{
+        u32 vc_val;
+        u16 mod;
+        static bool is_initialized;
+
+        if (!vdd->pmic_info || !vdd->pmic_info->uv_to_vsel) {
+                pr_err("%s: PMIC info requried to configure vc for"
+                        "vdd_%s not populated.Hence cannot initialize vc\n",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, vdd->voltdm.name);
+                return;
+        }
+
+        mod = vdd->vc_reg.prm_mod;
+
+        /* Set up the SMPS_SA(i2c slave address in VC */
+        vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_sa_reg);
+        vc_val &= ~vdd->vc_reg.smps_sa_mask;
+        vc_val |= vdd->pmic_info->i2c_slave_addr << vdd->vc_reg.smps_sa_shift;
+        vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_sa_reg);
+
+        /* Setup the VOLRA(pmic reg addr) in VC */
+        vc_val = vdd->read_reg(mod, vdd->vc_reg.smps_volra_reg);
+        vc_val &= ~vdd->vc_reg.smps_volra_mask;
+        vc_val |= vdd->pmic_info->pmic_reg << vdd->vc_reg.smps_volra_shift;
+        vdd->write_reg(vc_val, mod, vdd->vc_reg.smps_volra_reg);
+
+        /* TODO: Configure setup times and CMD_VAL values*/
+
+        if (is_initialized)
+                return;
+
+        /* Generic VC parameters init */
+        vc_val = (OMAP4430_RAV_VDD_MPU_L_MASK | OMAP4430_CMD_VDD_MPU_L_MASK |
+                OMAP4430_RAV_VDD_IVA_L_MASK | OMAP4430_CMD_VDD_IVA_L_MASK |
+                OMAP4430_RAV_VDD_CORE_L_MASK | OMAP4430_CMD_VDD_CORE_L_MASK);
+        vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_CHANNEL_OFFSET);
+
+        vc_val = (0x60 << OMAP4430_SCLL_SHIFT | 0x26 << OMAP4430_SCLH_SHIFT);
+        vdd->write_reg(vc_val, mod, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
+
+        is_initialized = true;
+}
+
+/* Sets up all the VDD related info for OMAP4 */
+static int __init omap4_vdd_data_configure(struct omap_vdd_info *vdd)
+{
+        struct clk *sys_ck;
+        u32 sys_clk_speed, timeout_val, waittime;
+
+        if (!vdd->pmic_info) {
+                pr_err("%s: PMIC info requried to configure vdd_%s not"
+                        "populated.Hence cannot initialize vdd_%s\n",
+                        __func__, vdd->voltdm.name, vdd->voltdm.name);
+                return -EINVAL;
+        }
+
+        if (!strcmp(vdd->voltdm.name, "mpu")) {
+                vdd->volt_data = omap44xx_vdd_mpu_volt_data;
+                vdd->vp_reg.tranxdone_status =
+                                OMAP4430_VP_MPU_TRANXDONE_ST_MASK;
+                vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET;
+                vdd->vc_reg.smps_sa_shift =
+                                OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT;
+                vdd->vc_reg.smps_sa_mask =
+                                OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK;
+                vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_MPU_L_SHIFT;
+                vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK;
+                vdd->vc_reg.voltsetup_reg =
+                                OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET;
+                vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET;
+        } else if (!strcmp(vdd->voltdm.name, "core")) {
+                vdd->volt_data = omap44xx_vdd_core_volt_data;
+                vdd->vp_reg.tranxdone_status =
+                                OMAP4430_VP_CORE_TRANXDONE_ST_MASK;
+                vdd->vc_reg.cmdval_reg =
+                                OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET;
+                vdd->vc_reg.smps_sa_shift = OMAP4430_SA_VDD_CORE_L_0_6_SHIFT;
+                vdd->vc_reg.smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK;
+                vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_CORE_L_SHIFT;
+                vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK;
+                vdd->vc_reg.voltsetup_reg =
+                                OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET;
+                vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
+        } else if (!strcmp(vdd->voltdm.name, "iva")) {
+                vdd->volt_data = omap44xx_vdd_iva_volt_data;
+                vdd->vp_reg.tranxdone_status =
+                                OMAP4430_VP_IVA_TRANXDONE_ST_MASK;
+                vdd->vc_reg.cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET;
+                vdd->vc_reg.smps_sa_shift =
+                                OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT;
+                vdd->vc_reg.smps_sa_mask =
+                                OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK;
+                vdd->vc_reg.smps_volra_shift = OMAP4430_VOLRA_VDD_IVA_L_SHIFT;
+                vdd->vc_reg.smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK;
+                vdd->vc_reg.voltsetup_reg =
+                                OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET;
+                vdd->prm_irqst_reg = OMAP4_PRM_IRQSTATUS_MPU_OFFSET;
+        } else {
+                pr_warning("%s: vdd_%s does not exisit in OMAP4\n",
+                        __func__, vdd->voltdm.name);
+                return -EINVAL;
+        }
+
+        /*
+         * Sys clk rate is require to calculate vp timeout value and
+         * smpswaittimemin and smpswaittimemax.
+         */
+        sys_ck = clk_get(NULL, "sys_clkin_ck");
+        if (IS_ERR(sys_ck)) {
+                pr_warning("%s: Could not get the sys clk to calculate"
+                        "various vdd_%s params\n", __func__, vdd->voltdm.name);
+                return -EINVAL;
+        }
+        sys_clk_speed = clk_get_rate(sys_ck);
+        clk_put(sys_ck);
+        /* Divide to avoid overflow */
+        sys_clk_speed /= 1000;
+
+        /* Generic voltage parameters */
+        vdd->curr_volt = 1200000;
+        vdd->ocp_mod = OMAP4430_PRM_OCP_SOCKET_INST;
+        vdd->read_reg = omap4_voltage_read_reg;
+        vdd->write_reg = omap4_voltage_write_reg;
+        vdd->volt_scale = vp_forceupdate_scale_voltage;
+        vdd->vp_enabled = false;
+
+        /* VC parameters */
+        vdd->vc_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
+        vdd->vc_reg.smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET;
+        vdd->vc_reg.smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET;
+        vdd->vc_reg.bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET;
+        vdd->vc_reg.data_shift = OMAP4430_DATA_SHIFT;
+        vdd->vc_reg.slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT;
+        vdd->vc_reg.regaddr_shift = OMAP4430_REGADDR_SHIFT;
+        vdd->vc_reg.valid = OMAP4430_VALID_MASK;
+        vdd->vc_reg.cmd_on_shift = OMAP4430_ON_SHIFT;
+        vdd->vc_reg.cmd_on_mask = OMAP4430_ON_MASK;
+        vdd->vc_reg.cmd_onlp_shift = OMAP4430_ONLP_SHIFT;
+        vdd->vc_reg.cmd_ret_shift = OMAP4430_RET_SHIFT;
+        vdd->vc_reg.cmd_off_shift = OMAP4430_OFF_SHIFT;
+
+        vdd->vp_reg.prm_mod = OMAP4430_PRM_DEVICE_INST;
+
+        /* VPCONFIG bit fields */
+        vdd->vp_reg.vpconfig_erroroffset = (vdd->pmic_info->vp_erroroffset <<
+                                 OMAP4430_ERROROFFSET_SHIFT);
+        vdd->vp_reg.vpconfig_errorgain_mask = OMAP4430_ERRORGAIN_MASK;
+        vdd->vp_reg.vpconfig_errorgain_shift = OMAP4430_ERRORGAIN_SHIFT;
+        vdd->vp_reg.vpconfig_initvoltage_shift = OMAP4430_INITVOLTAGE_SHIFT;
+        vdd->vp_reg.vpconfig_initvoltage_mask = OMAP4430_INITVOLTAGE_MASK;
+        vdd->vp_reg.vpconfig_timeouten = OMAP4430_TIMEOUTEN_MASK;
+        vdd->vp_reg.vpconfig_initvdd = OMAP4430_INITVDD_MASK;
+        vdd->vp_reg.vpconfig_forceupdate = OMAP4430_FORCEUPDATE_MASK;
+        vdd->vp_reg.vpconfig_vpenable = OMAP4430_VPENABLE_MASK;
+
+        /* VSTEPMIN VSTEPMAX bit fields */
+        waittime = ((vdd->pmic_info->step_size / vdd->pmic_info->slew_rate) *
+                                sys_clk_speed) / 1000;
+        vdd->vp_reg.vstepmin_smpswaittimemin = waittime;
+        vdd->vp_reg.vstepmax_smpswaittimemax = waittime;
+        vdd->vp_reg.vstepmin_stepmin = vdd->pmic_info->vp_vstepmin;
+        vdd->vp_reg.vstepmax_stepmax = vdd->pmic_info->vp_vstepmax;
+        vdd->vp_reg.vstepmin_smpswaittimemin_shift =
+                        OMAP4430_SMPSWAITTIMEMIN_SHIFT;
+        vdd->vp_reg.vstepmax_smpswaittimemax_shift =
+                        OMAP4430_SMPSWAITTIMEMAX_SHIFT;
+        vdd->vp_reg.vstepmin_stepmin_shift = OMAP4430_VSTEPMIN_SHIFT;
+        vdd->vp_reg.vstepmax_stepmax_shift = OMAP4430_VSTEPMAX_SHIFT;
+
+        /* VLIMITTO bit fields */
+        timeout_val = (sys_clk_speed * vdd->pmic_info->vp_timeout_us) / 1000;
+        vdd->vp_reg.vlimitto_timeout = timeout_val;
+        vdd->vp_reg.vlimitto_vddmin = vdd->pmic_info->vp_vddmin;
+        vdd->vp_reg.vlimitto_vddmax = vdd->pmic_info->vp_vddmax;
+        vdd->vp_reg.vlimitto_vddmin_shift = OMAP4430_VDDMIN_SHIFT;
+        vdd->vp_reg.vlimitto_vddmax_shift = OMAP4430_VDDMAX_SHIFT;
+        vdd->vp_reg.vlimitto_timeout_shift = OMAP4430_TIMEOUT_SHIFT;
+
+        return 0;
+}
+
+/* Public functions */
+/**
+ * omap_voltage_get_nom_volt() - Gets the current non-auto-compensated voltage
+ * @voltdm:     pointer to the VDD for which current voltage info is needed
+ *
+ * API to get the current non-auto-compensated voltage for a VDD.
+ * Returns 0 in case of error else returns the current voltage for the VDD.
+ */
+unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return 0;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        return vdd->curr_volt;
+}
+
+/**
+ * omap_vp_get_curr_volt() - API to get the current vp voltage.
+ * @voltdm:     pointer to the VDD.
+ *
+ * This API returns the current voltage for the specified voltage processor
+ */
+unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm)
+{
+        struct omap_vdd_info *vdd;
+        u8 curr_vsel;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return 0;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        if (!vdd->read_reg) {
+                pr_err("%s: No read API for reading vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return 0;
+        }
+
+        curr_vsel = vdd->read_reg(vdd->vp_reg.prm_mod,
+                        vdd->vp_offs.voltage);
+
+        if (!vdd->pmic_info || !vdd->pmic_info->vsel_to_uv) {
+                pr_warning("%s: PMIC function to convert vsel to voltage"
+                        "in uV not registerd\n", __func__);
+                return 0;
+        }
+
+        return vdd->pmic_info->vsel_to_uv(curr_vsel);
+}
+
+/**
+ * omap_vp_enable() - API to enable a particular VP
+ * @voltdm:     pointer to the VDD whose VP is to be enabled.
+ *
+ * This API enables a particular voltage processor. Needed by the smartreflex
+ * class drivers.
+ */
+void omap_vp_enable(struct voltagedomain *voltdm)
+{
+        struct omap_vdd_info *vdd;
+        u32 vpconfig;
+        u16 mod;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        mod = vdd->vp_reg.prm_mod;
+
+        /* If VP is already enabled, do nothing. Return */
+        if (vdd->vp_enabled)
+                return;
+
+        vp_latch_vsel(vdd);
+
+        /* Enable VP */
+        vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
+        vpconfig |= vdd->vp_reg.vpconfig_vpenable;
+        vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+        vdd->vp_enabled = true;
+}
+
+/**
+ * omap_vp_disable() - API to disable a particular VP
+ * @voltdm:     pointer to the VDD whose VP is to be disabled.
+ *
+ * This API disables a particular voltage processor. Needed by the smartreflex
+ * class drivers.
+ */
+void omap_vp_disable(struct voltagedomain *voltdm)
+{
+        struct omap_vdd_info *vdd;
+        u32 vpconfig;
+        u16 mod;
+        int timeout;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+        if (!vdd->read_reg || !vdd->write_reg) {
+                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        mod = vdd->vp_reg.prm_mod;
+
+        /* If VP is already disabled, do nothing. Return */
+        if (!vdd->vp_enabled) {
+                pr_warning("%s: Trying to disable VP for vdd_%s when"
+                        "it is already disabled\n", __func__, voltdm->name);
+                return;
+        }
+
+        /* Disable VP */
+        vpconfig = vdd->read_reg(mod, vdd->vp_offs.vpconfig);
+        vpconfig &= ~vdd->vp_reg.vpconfig_vpenable;
+        vdd->write_reg(vpconfig, mod, vdd->vp_offs.vpconfig);
+
+        /*
+         * Wait for VP idle Typical latency is <2us. Maximum latency is ~100us
+         */
+        omap_test_timeout((vdd->read_reg(mod, vdd->vp_offs.vstatus)),
+                                VP_IDLE_TIMEOUT, timeout);
+
+        if (timeout >= VP_IDLE_TIMEOUT)
+                pr_warning("%s: vdd_%s idle timedout\n",
+                        __func__, voltdm->name);
+
+        vdd->vp_enabled = false;
+
+        return;
+}
+
+/**
+ * omap_voltage_scale_vdd() - API to scale voltage of a particular
+ *                              voltage domain.
+ * @voltdm:     pointer to the VDD which is to be scaled.
+ * @target_volt:        The target voltage of the voltage domain
+ *
+ * This API should be called by the kernel to do the voltage scaling
+ * for a particular voltage domain during dvfs or any other situation.
+ */
+int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+                unsigned long target_volt)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return -EINVAL;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        if (!vdd->volt_scale) {
+                pr_err("%s: No voltage scale API registered for vdd_%s\n",
+                        __func__, voltdm->name);
+                return -ENODATA;
+        }
+
+        return vdd->volt_scale(vdd, target_volt);
+}
+
+/**
+ * omap_voltage_reset() - Resets the voltage of a particular voltage domain
+ *                      to that of the current OPP.
+ * @voltdm:     pointer to the VDD whose voltage is to be reset.
+ *
+ * This API finds out the correct voltage the voltage domain is supposed
+ * to be at and resets the voltage to that level. Should be used expecially
+ * while disabling any voltage compensation modules.
+ */
+void omap_voltage_reset(struct voltagedomain *voltdm)
+{
+        unsigned long target_uvdc;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+
+        target_uvdc = omap_voltage_get_nom_volt(voltdm);
+        if (!target_uvdc) {
+                pr_err("%s: unable to find current voltage for vdd_%s\n",
+                        __func__, voltdm->name);
+                return;
+        }
+
+        omap_voltage_scale_vdd(voltdm, target_uvdc);
+}
+
+/**
+ * omap_voltage_get_volttable() - API to get the voltage table associated with a
+ *                              particular voltage domain.
+ * @voltdm:     pointer to the VDD for which the voltage table is required
+ * @volt_data:  the voltage table for the particular vdd which is to be
+ *              populated by this API
+ *
+ * This API populates the voltage table associated with a VDD into the
+ * passed parameter pointer. Returns the count of distinct voltages
+ * supported by this vdd.
+ *
+ */
+void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+                struct omap_volt_data **volt_data)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        *volt_data = vdd->volt_data;
+}
+
+/**
+ * omap_voltage_get_voltdata() - API to get the voltage table entry for a
+ *                              particular voltage
+ * @voltdm:     pointer to the VDD whose voltage table has to be searched
+ * @volt:       the voltage to be searched in the voltage table
+ *
+ * This API searches through the voltage table for the required voltage
+ * domain and tries to find a matching entry for the passed voltage volt.
+ * If a matching entry is found volt_data is populated with that entry.
+ * This API searches only through the non-compensated voltages int the
+ * voltage table.
+ * Returns pointer to the voltage table entry corresponding to volt on
+ * sucess. Returns -ENODATA if no voltage table exisits for the passed voltage
+ * domain or if there is no matching entry.
+ */
+struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+                unsigned long volt)
+{
+        struct omap_vdd_info *vdd;
+        int i;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        if (!vdd->volt_data) {
+                pr_warning("%s: voltage table does not exist for vdd_%s\n",
+                        __func__, voltdm->name);
+                return ERR_PTR(-ENODATA);
+        }
+
+        for (i = 0; vdd->volt_data[i].volt_nominal != 0; i++) {
+                if (vdd->volt_data[i].volt_nominal == volt)
+                        return &vdd->volt_data[i];
+        }
+
+        pr_notice("%s: Unable to match the current voltage with the voltage"
+                "table for vdd_%s\n", __func__, voltdm->name);
+
+        return ERR_PTR(-ENODATA);
+}
+
+/**
+ * omap_voltage_register_pmic() - API to register PMIC specific data
+ * @voltdm:     pointer to the VDD for which the PMIC specific data is
+ *              to be registered
+ * @pmic_info:  the structure containing pmic info
+ *
+ * This API is to be called by the SOC/PMIC file to specify the
+ * pmic specific info as present in omap_volt_pmic_info structure.
+ */
+int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+                struct omap_volt_pmic_info *pmic_info)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return -EINVAL;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        vdd->pmic_info = pmic_info;
+
+        return 0;
+}
+
+/**
+ * omap_voltage_get_dbgdir() - API to get pointer to the debugfs directory
+ *                              corresponding to a voltage domain.
+ *
+ * @voltdm:     pointer to the VDD whose debug directory is required.
+ *
+ * This API returns pointer to the debugfs directory corresponding
+ * to the voltage domain. Should be used by drivers requiring to
+ * add any debug entry for a particular voltage domain. Returns NULL
+ * in case of error.
+ */
+struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return NULL;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        return vdd->debug_dir;
+}
+
+/**
+ * omap_change_voltscale_method() - API to change the voltage scaling method.
+ * @voltdm:     pointer to the VDD whose voltage scaling method
+ *              has to be changed.
+ * @voltscale_method:   the method to be used for voltage scaling.
+ *
+ * This API can be used by the board files to change the method of voltage
+ * scaling between vpforceupdate and vcbypass. The parameter values are
+ * defined in voltage.h
+ */
+void omap_change_voltscale_method(struct voltagedomain *voltdm,
+                int voltscale_method)
+{
+        struct omap_vdd_info *vdd;
+
+        if (!voltdm || IS_ERR(voltdm)) {
+                pr_warning("%s: VDD specified does not exist!\n", __func__);
+                return;
+        }
+
+        vdd = container_of(voltdm, struct omap_vdd_info, voltdm);
+
+        switch (voltscale_method) {
+        case VOLTSCALE_VPFORCEUPDATE:
+                vdd->volt_scale = vp_forceupdate_scale_voltage;
+                return;
+        case VOLTSCALE_VCBYPASS:
+                vdd->volt_scale = vc_bypass_scale_voltage;
+                return;
+        default:
+                pr_warning("%s: Trying to change the method of voltage scaling"
+                        "to an unsupported one!\n", __func__);
+        }
+}
+
+/**
+ * omap_voltage_domain_lookup() - API to get the voltage domain pointer
+ * @name:       Name of the voltage domain
+ *
+ * This API looks up in the global vdd_info struct for the
+ * existence of voltage domain <name>. If it exists, the API returns
+ * a pointer to the voltage domain structure corresponding to the
+ * VDD<name>. Else retuns error pointer.
+ */
+struct voltagedomain *omap_voltage_domain_lookup(char *name)
+{
+        int i;
+
+        if (!vdd_info) {
+                pr_err("%s: Voltage driver init not yet happened.Faulting!\n",
+                        __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        if (!name) {
+                pr_err("%s: No name to get the votage domain!\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
+
+        for (i = 0; i < nr_scalable_vdd; i++) {
+                if (!(strcmp(name, vdd_info[i].voltdm.name)))
+                        return &vdd_info[i].voltdm;
+        }
+
+        return ERR_PTR(-EINVAL);
+}
+
+/**
+ * omap_voltage_late_init() - Init the various voltage parameters
+ *
+ * This API is to be called in the later stages of the
+ * system boot to init the voltage controller and
+ * voltage processors.
+ */
+int __init omap_voltage_late_init(void)
+{
+        int i;
+
+        if (!vdd_info) {
+                pr_err("%s: Voltage driver support not added\n",
+                        __func__);
+                return -EINVAL;
+        }
+
+        voltage_dir = debugfs_create_dir("voltage", NULL);
+        if (IS_ERR(voltage_dir))
+                pr_err("%s: Unable to create voltage debugfs main dir\n",
+                        __func__);
+        for (i = 0; i < nr_scalable_vdd; i++) {
+                if (vdd_data_configure(&vdd_info[i]))
+                        continue;
+                vc_init(&vdd_info[i]);
+                vp_init(&vdd_info[i]);
+                vdd_debugfs_init(&vdd_info[i]);
+        }
+
+        return 0;
+}
+
+/**
+ * omap_voltage_early_init()- Volatage driver early init
+ */
+static int __init omap_voltage_early_init(void)
+{
+        if (cpu_is_omap34xx()) {
+                vdd_info = omap3_vdd_info;
+                nr_scalable_vdd = OMAP3_NR_SCALABLE_VDD;
+                vc_init = omap3_vc_init;
+                vdd_data_configure = omap3_vdd_data_configure;
+        } else if (cpu_is_omap44xx()) {
+                vdd_info = omap4_vdd_info;
+                nr_scalable_vdd = OMAP4_NR_SCALABLE_VDD;
+                vc_init = omap4_vc_init;
+                vdd_data_configure = omap4_vdd_data_configure;
+        } else {
+                pr_warning("%s: voltage driver support not added\n", __func__);
+        }
+
+        return 0;
+}
+core_initcall(omap_voltage_early_init);
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
new file mode 100644
index 000000000000..b0c4907ab3ca
--- /dev/null
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -0,0 +1,54 @@
+/*
+ * OMAP2+ MPU WD_TIMER-specific code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include <plat/omap_hwmod.h>
+
+/*
+ * In order to avoid any assumptions from bootloader regarding WDT
+ * settings, WDT module is reset during init. This enables the watchdog
+ * timer. Hence it is required to disable the watchdog after the WDT reset
+ * during init. Otherwise the system would reboot as per the default
+ * watchdog timer registers settings.
+ */
+#define OMAP_WDT_WPS            0x34
+#define OMAP_WDT_SPR            0x48
+
+
+int omap2_wd_timer_disable(struct omap_hwmod *oh)
+{
+        void __iomem *base;
+
+        if (!oh) {
+                pr_err("%s: Could not look up wdtimer_hwmod\n", __func__);
+                return -EINVAL;
+        }
+
+        base = omap_hwmod_get_mpu_rt_va(oh);
+        if (!base) {
+                pr_err("%s: Could not get the base address for %s\n",
+                                oh->name, __func__);
+                return -EINVAL;
+        }
+
+        /* sequence required to disable watchdog */
+        __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
+        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+                cpu_relax();
+
+        __raw_writel(0x5555, base + OMAP_WDT_SPR);
+        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+                cpu_relax();
+
+        return 0;
+}
+
diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h
new file mode 100644
index 000000000000..e0054a2d5505
--- /dev/null
+++ b/arch/arm/mach-omap2/wd_timer.h
@@ -0,0 +1,17 @@
+/*
+ * OMAP2+ MPU WD_TIMER-specific function prototypes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
+#define __ARCH_ARM_MACH_OMAP2_WD_TIMER_H
+
+#include <plat/omap_hwmod.h>
+
+extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
+
+#endif
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index c897e03e413d..6604fc6ca58a 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -51,6 +51,13 @@ config MACH_LINKSTATION_PRO
           Buffalo Linkstation Pro/Live platform. Both v1 and
           v2 devices are supported.
 
+config MACH_LINKSTATION_LSCHL
+        bool "Buffalo Linkstation Live v3 (LS-CHL)"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          Buffalo Linkstation Live v3 (LS-CHL) platform.
+
 config MACH_LINKSTATION_MINI
         bool "Buffalo Linkstation Mini"
         select I2C_BOARDINFO
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index eb6eabcb41e4..7f18cdacd487 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_WNR854T)	+= wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)        += rd88f5181l-ge-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_FXO)       += rd88f5181l-fxo-setup.o
 obj-$(CONFIG_MACH_RD88F6183AP_GE)       += rd88f6183ap-ge-setup.o
+obj-$(CONFIG_MACH_LINKSTATION_LSCHL)    += ls-chl-setup.o
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
index c47b033bd999..c5196101a237 100644
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ b/arch/arm/mach-orion5x/include/mach/io.h
@@ -38,8 +38,8 @@ __arch_iounmap(void __iomem *addr)
                 __iounmap(addr);
 }
 
-#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
-#define __arch_iounmap(a)       __arch_iounmap(a)
+#define __arch_ioremap          __arch_ioremap
+#define __arch_iounmap          __arch_iounmap
 #define __io(a)                 __typesafe_io(a)
 #define __mem_pci(a)            (a)
 
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
new file mode 100644
index 000000000000..20a9b66cbafa
--- /dev/null
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -0,0 +1,327 @@
+/*
+ * arch/arm/mach-orion5x/ls-chl-setup.c
+ *
+ * Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio-fan.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/system.h>
+#include <mach/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * Linkstation LS-CHL Info
+ ****************************************************************************/
+
+/*
+ * 256K NOR flash Device bus boot chip select
+ */
+
+#define LSCHL_NOR_BOOT_BASE     0xf4000000
+#define LSCHL_NOR_BOOT_SIZE     SZ_256K
+
+/*****************************************************************************
+ * 256KB NOR Flash on BOOT Device
+ ****************************************************************************/
+
+static struct physmap_flash_data lschl_nor_flash_data = {
+        .width = 1,
+};
+
+static struct resource lschl_nor_flash_resource = {
+        .flags  = IORESOURCE_MEM,
+        .start  = LSCHL_NOR_BOOT_BASE,
+        .end    = LSCHL_NOR_BOOT_BASE + LSCHL_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device lschl_nor_flash = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data  = &lschl_nor_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &lschl_nor_flash_resource,
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data lschl_eth_data = {
+        .phy_addr = MV643XX_ETH_PHY_ADDR(8),
+};
+
+/*****************************************************************************
+ * RTC 5C372a on I2C bus
+ ****************************************************************************/
+
+static struct i2c_board_info __initdata lschl_i2c_rtc = {
+        I2C_BOARD_INFO("rs5c372a", 0x32),
+};
+
+/*****************************************************************************
+ * LEDs attached to GPIO
+ ****************************************************************************/
+
+#define LSCHL_GPIO_LED_ALARM    2
+#define LSCHL_GPIO_LED_INFO     3
+#define LSCHL_GPIO_LED_FUNC     17
+#define LSCHL_GPIO_LED_PWR      0
+
+static struct gpio_led lschl_led_pins[] = {
+        {
+                .name = "alarm:red",
+                .gpio = LSCHL_GPIO_LED_ALARM,
+                .active_low = 1,
+        }, {
+                .name = "info:amber",
+                .gpio = LSCHL_GPIO_LED_INFO,
+                .active_low = 1,
+        }, {
+                .name = "func:blue:top",
+                .gpio = LSCHL_GPIO_LED_FUNC,
+                .active_low = 1,
+        }, {
+                .name = "power:blue:bottom",
+                .gpio = LSCHL_GPIO_LED_PWR,
+        },
+};
+
+static struct gpio_led_platform_data lschl_led_data = {
+        .leds = lschl_led_pins,
+        .num_leds = ARRAY_SIZE(lschl_led_pins),
+};
+
+static struct platform_device lschl_leds = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev = {
+                .platform_data = &lschl_led_data,
+        },
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct mv_sata_platform_data lschl_sata_data = {
+        .n_ports = 2,
+};
+
+/*****************************************************************************
+ * LS-CHL specific power off method: reboot
+ ****************************************************************************/
+/*
+ * On the LS-CHL, the shutdown process is following:
+ * - Userland monitors key events until the power switch goes to off position
+ * - The board reboots
+ * - U-boot starts and goes into an idle mode waiting for the user
+ *   to move the switch to ON position
+ *
+ */
+
+static void lschl_power_off(void)
+{
+        arm_machine_restart('h', NULL);
+}
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+#define LSCHL_GPIO_USB_POWER    9
+#define LSCHL_GPIO_AUTO_POWER   17
+#define LSCHL_GPIO_POWER        18
+
+/****************************************************************************
+ * GPIO Attached Keys
+ ****************************************************************************/
+#define LSCHL_GPIO_KEY_FUNC             15
+#define LSCHL_GPIO_KEY_POWER            8
+#define LSCHL_GPIO_KEY_AUTOPOWER        10
+#define LSCHL_SW_POWER          0x00
+#define LSCHL_SW_AUTOPOWER      0x01
+#define LSCHL_SW_FUNC           0x02
+
+static struct gpio_keys_button lschl_buttons[] = {
+        {
+                .type = EV_SW,
+                .code = LSCHL_SW_POWER,
+                .gpio = LSCHL_GPIO_KEY_POWER,
+                .desc = "Power-on Switch",
+                .active_low = 1,
+        }, {
+                .type = EV_SW,
+                .code = LSCHL_SW_AUTOPOWER,
+                .gpio = LSCHL_GPIO_KEY_AUTOPOWER,
+                .desc = "Power-auto Switch",
+                .active_low = 1,
+        }, {
+                .type = EV_SW,
+                .code = LSCHL_SW_FUNC,
+                .gpio = LSCHL_GPIO_KEY_FUNC,
+                .desc = "Function Switch",
+                .active_low = 1,
+        },
+};
+
+static struct gpio_keys_platform_data lschl_button_data = {
+        .buttons = lschl_buttons,
+        .nbuttons = ARRAY_SIZE(lschl_buttons),
+};
+
+static struct platform_device lschl_button_device = {
+        .name = "gpio-keys",
+        .id = -1,
+        .num_resources = 0,
+        .dev = {
+                .platform_data = &lschl_button_data,
+        },
+};
+
+#define LSCHL_GPIO_HDD_POWER    1
+
+/****************************************************************************
+ * GPIO Fan
+ ****************************************************************************/
+
+#define LSCHL_GPIO_FAN_LOW      16
+#define LSCHL_GPIO_FAN_HIGH     14
+#define LSCHL_GPIO_FAN_LOCK     6
+
+static struct gpio_fan_alarm lschl_alarm = {
+        .gpio = LSCHL_GPIO_FAN_LOCK,
+};
+
+static struct gpio_fan_speed lschl_speeds[] = {
+        {
+                .rpm = 0,
+                .ctrl_val = 3,
+        }, {
+                .rpm = 1500,
+                .ctrl_val = 2,
+        }, {
+                .rpm = 3250,
+                .ctrl_val = 1,
+        }, {
+                .rpm = 5000,
+                .ctrl_val = 0,
+        },
+};
+
+static int lschl_gpio_list[] = {
+        LSCHL_GPIO_FAN_HIGH, LSCHL_GPIO_FAN_LOW,
+};
+
+static struct gpio_fan_platform_data lschl_fan_data = {
+        .num_ctrl = ARRAY_SIZE(lschl_gpio_list),
+        .ctrl = lschl_gpio_list,
+        .alarm = &lschl_alarm,
+        .num_speed = ARRAY_SIZE(lschl_speeds),
+        .speed = lschl_speeds,
+};
+
+static struct platform_device lschl_fan_device = {
+        .name = "gpio-fan",
+        .id = -1,
+        .num_resources = 0,
+        .dev = {
+                .platform_data = &lschl_fan_data,
+        },
+};
+
+/****************************************************************************
+ * GPIO Data
+ ****************************************************************************/
+
+static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO }, /* LED POWER */
+        {  1, MPP_GPIO }, /* HDD POWER */
+        {  2, MPP_GPIO }, /* LED ALARM */
+        {  3, MPP_GPIO }, /* LED INFO */
+        {  4, MPP_UNUSED },
+        {  5, MPP_UNUSED },
+        {  6, MPP_GPIO }, /* FAN LOCK */
+        {  7, MPP_GPIO }, /* SW INIT */
+        {  8, MPP_GPIO }, /* SW POWER */
+        {  9, MPP_GPIO }, /* USB POWER */
+        { 10, MPP_GPIO }, /* SW AUTO POWER */
+        { 11, MPP_UNUSED },
+        { 12, MPP_UNUSED },
+        { 13, MPP_UNUSED },
+        { 14, MPP_GPIO }, /* FAN HIGH */
+        { 15, MPP_GPIO }, /* SW FUNC */
+        { 16, MPP_GPIO }, /* FAN LOW */
+        { 17, MPP_GPIO }, /* LED FUNC */
+        { 18, MPP_UNUSED },
+        { 19, MPP_UNUSED },
+        { -1 },
+};
+
+static void __init lschl_init(void)
+{
+        /*
+         * Setup basic Orion functions. Needs to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(lschl_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&lschl_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&lschl_sata_data);
+        orion5x_uart0_init();
+        orion5x_xor_init();
+
+        orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE,
+                                   LSCHL_NOR_BOOT_SIZE);
+        platform_device_register(&lschl_nor_flash);
+
+        platform_device_register(&lschl_leds);
+
+        platform_device_register(&lschl_button_device);
+
+        platform_device_register(&lschl_fan_device);
+
+        i2c_register_board_info(0, &lschl_i2c_rtc, 1);
+
+        /* usb power on */
+        gpio_set_value(LSCHL_GPIO_USB_POWER, 1);
+
+        /* register power-off method */
+        pm_power_off = lschl_power_off;
+
+        pr_info("%s: finished\n", __func__);
+}
+
+MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
+        /* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */
+        .boot_params    = 0x00000100,
+        .init_machine   = lschl_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
index 9d1975fa4d9f..a4a3819c96cb 100644
--- a/arch/arm/mach-pnx4008/clock.c
+++ b/arch/arm/mach-pnx4008/clock.c
@@ -21,8 +21,7 @@
 #include <linux/err.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 #include <mach/hardware.h>
 #include <mach/clock.h>
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index c93e73d54dd1..2fc9f94cdd29 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -50,6 +50,10 @@ config MACH_SAAR
         select PXA3xx
         select CPU_PXA930
 
+config MACH_SAARB
+        bool "PXA955 Handheld Platform (aka SAARB)"
+        select CPU_PXA955
+
 comment "Third Party Dev Platforms (sorted by vendor name)"
 
 config ARCH_PXA_IDP
@@ -94,6 +98,7 @@ config MACH_ARMCORE
         select PXA27x
         select IWMMXT
         select PXA25x
+        select MIGHT_HAVE_PCI
 
 config MACH_EM_X270
         bool "CompuLab EM-x270 platform"
@@ -232,10 +237,6 @@ config MACH_COLIBRI
         bool "Toradex Colibri PXA270"
         select PXA27x
 
-config MACH_COLIBRI_PXA270_EVALBOARD
-        bool "Toradex Colibri Evaluation Carrier Board support (PXA270)"
-        depends on MACH_COLIBRI
-
 config MACH_COLIBRI_PXA270_INCOME
         bool "Income s.r.o. PXA270 SBC"
         depends on MACH_COLIBRI
@@ -253,6 +254,10 @@ config MACH_COLIBRI320
         select PXA3xx
         select CPU_PXA320
 
+config MACH_COLIBRI_EVALBOARD
+        bool "Toradex Colibri Evaluation Carrier Board support"
+        depends on MACH_COLIBRI || MACH_COLIBRI300 || MACH_COLIBRI320
+
 config MACH_VPAC270
         bool "Voipac PXA270"
         select PXA27x
@@ -652,11 +657,17 @@ config CPU_PXA935
         help
           PXA935 (codename Tavor-P65)
 
-config CPU_PXA950
+config PXA95x
         bool
-        select CPU_PXA930
+        select CPU_PJ4
+        help
+          Select code specific to PXA95x variants
+
+config CPU_PXA955
+        bool
+        select PXA95x
         help
-          PXA950 (codename Tavor-PV2)
+          PXA950 (codename MG1)
 
 config PXA_SHARP_C7xx
         bool
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index e2f89c2c6f49..cc39d17b2e07 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -16,9 +16,10 @@ endif
 # Generic drivers that other drivers may depend upon
 
 # SoC-specific code
-obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa2xx.o pxa25x.o
-obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o pxa2xx.o pxa27x.o
-obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
+obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
+obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
+obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
+obj-$(CONFIG_PXA95x)            += mfp-pxa3xx.o clock-pxa3xx.o pxa95x.o smemc.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 obj-$(CONFIG_CPU_PXA930)        += pxa930.o
@@ -34,6 +35,7 @@ obj-$(CONFIG_MACH_LITTLETON)	+= littleton.o
 obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
 obj-$(CONFIG_MACH_TAVOREVB3)    += tavorevb3.o
 obj-$(CONFIG_MACH_SAAR)         += saar.o
+obj-$(CONFIG_MACH_SAARB)        += saarb.o
 
 # 3rd Party Dev Platforms
 obj-$(CONFIG_ARCH_PXA_IDP)      += idp.o
@@ -60,7 +62,7 @@ obj-$(CONFIG_MACH_LOGICPD_PXA270)	+= lpd270.o
 obj-$(CONFIG_MACH_PCM027)               += pcm027.o
 obj-$(CONFIG_MACH_PCM990_BASEBOARD)     += pcm990-baseboard.o
 obj-$(CONFIG_MACH_COLIBRI)                      += colibri-pxa270.o
-obj-$(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD)     += colibri-pxa270-evalboard.o
+obj-$(CONFIG_MACH_COLIBRI_EVALBOARD)    += colibri-evalboard.o
 obj-$(CONFIG_MACH_COLIBRI_PXA270_INCOME)        += colibri-pxa270-income.o
 obj-$(CONFIG_MACH_COLIBRI300)   += colibri-pxa3xx.o colibri-pxa300.o
 obj-$(CONFIG_MACH_COLIBRI320)   += colibri-pxa3xx.o colibri-pxa320.o
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 21e188901935..ccb2d0cebcc3 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -567,27 +567,29 @@ static inline void balloon3_i2c_init(void) {}
  * NAND
  ******************************************************************************/
 #if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
-static uint16_t balloon3_ctl =
-        BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
-        BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
-        BALLOON3_NAND_CONTROL_FLWP;
-
 static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
         struct nand_chip *this = mtd->priv;
+        uint8_t balloon3_ctl_set = 0, balloon3_ctl_clr = 0;
 
         if (ctrl & NAND_CTRL_CHANGE) {
                 if (ctrl & NAND_CLE)
-                        balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCLE;
+                        balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLCLE;
                 else
-                        balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLCLE;
+                        balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLCLE;
 
                 if (ctrl & NAND_ALE)
-                        balloon3_ctl |= BALLOON3_NAND_CONTROL_FLALE;
+                        balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLALE;
                 else
-                        balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLALE;
-
-                __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
+                        balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLALE;
+
+                if (balloon3_ctl_clr)
+                        __raw_writel(balloon3_ctl_clr,
+                                BALLOON3_NAND_CONTROL_REG);
+                if (balloon3_ctl_set)
+                        __raw_writel(balloon3_ctl_set,
+                                BALLOON3_NAND_CONTROL_REG |
+                                BALLOON3_FPGA_SETnCLR);
         }
 
         if (cmd != NAND_CMD_NONE)
@@ -599,28 +601,33 @@ static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip)
         if (chip < 0 || chip > 3)
                 return;
 
-        balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCE0 |
-                        BALLOON3_NAND_CONTROL_FLCE1 |
-                        BALLOON3_NAND_CONTROL_FLCE2 |
-                        BALLOON3_NAND_CONTROL_FLCE3;
+        /* Assert all nCE lines */
+        __raw_writew(
+                BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
+                BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3,
+                BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
 
         /* Deassert correct nCE line */
-        balloon3_ctl &= ~(BALLOON3_NAND_CONTROL_FLCE0 << chip);
+        __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip,
+                BALLOON3_NAND_CONTROL_REG);
+}
 
-        __raw_writew(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
+static int balloon3_nand_dev_ready(struct mtd_info *mtd)
+{
+        return __raw_readl(BALLOON3_NAND_STAT_REG) & BALLOON3_NAND_STAT_RNB;
 }
 
 static int balloon3_nand_probe(struct platform_device *pdev)
 {
-        void __iomem *temp_map;
         uint16_t ver;
         int ret;
 
-        __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, BALLOON3_NAND_CONTROL2_REG);
+        __raw_writew(BALLOON3_NAND_CONTROL2_16BIT,
+                BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR);
 
         ver = __raw_readw(BALLOON3_FPGA_VER);
-        if (ver > 0x0201)
-                pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. "
+        if (ver < 0x4f08)
+                pr_warn("The FPGA code, version 0x%04x, is too old. "
                         "NAND support might be broken in this version!", ver);
 
         /* Power up the NAND chips */
@@ -635,7 +642,11 @@ static int balloon3_nand_probe(struct platform_device *pdev)
         gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1);
 
         /* Deassert all nCE lines and write protect line */
-        __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
+        __raw_writel(
+                BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
+                BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
+                BALLOON3_NAND_CONTROL_FLWP,
+                BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
         return 0;
 
 err2:
@@ -677,7 +688,7 @@ struct platform_nand_data balloon3_nand_pdata = {
         },
         .ctrl = {
                 .hwcontrol      = 0,
-                .dev_ready      = 0,
+                .dev_ready      = balloon3_nand_dev_ready,
                 .select_chip    = balloon3_nand_select_chip,
                 .cmd_ctrl       = balloon3_nand_cmd_ctl,
                 .probe          = balloon3_nand_probe,
@@ -802,7 +813,7 @@ static struct map_desc balloon3_io_desc[] __initdata = {
 
 static void __init balloon3_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc));
 }
 
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index 4bd7a3cda48c..4284513f396a 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -149,7 +149,7 @@ static void __init capc7117_init(void)
 MACHINE_START(CAPC7117,
               "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM")
         .boot_params = 0xa0000100,
-        .map_io = pxa_map_io,
+        .map_io = pxa3xx_map_io,
         .init_irq = pxa3xx_init_irq,
         .timer = &pxa_timer,
         .init_machine = capc7117_init
diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c
new file mode 100644
index 000000000000..1ce090448493
--- /dev/null
+++ b/arch/arm/mach-pxa/clock-pxa2xx.c
@@ -0,0 +1,64 @@
+/*
+ * linux/arch/arm/mach-pxa/clock-pxa2xx.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+
+#include <mach/pxa2xx-regs.h>
+
+#include "clock.h"
+
+void clk_pxa2xx_cken_enable(struct clk *clk)
+{
+        CKEN |= 1 << clk->cken;
+}
+
+void clk_pxa2xx_cken_disable(struct clk *clk)
+{
+        CKEN &= ~(1 << clk->cken);
+}
+
+const struct clkops clk_pxa2xx_cken_ops = {
+        .enable         = clk_pxa2xx_cken_enable,
+        .disable        = clk_pxa2xx_cken_disable,
+};
+
+#ifdef CONFIG_PM
+static uint32_t saved_cken;
+
+static int pxa2xx_clock_suspend(struct sys_device *d, pm_message_t state)
+{
+        saved_cken = CKEN;
+        return 0;
+}
+
+static int pxa2xx_clock_resume(struct sys_device *d)
+{
+        CKEN = saved_cken;
+        return 0;
+}
+#else
+#define pxa2xx_clock_suspend    NULL
+#define pxa2xx_clock_resume     NULL
+#endif
+
+struct sysdev_class pxa2xx_clock_sysclass = {
+        .name           = "pxa2xx-clock",
+        .suspend        = pxa2xx_clock_suspend,
+        .resume         = pxa2xx_clock_resume,
+};
+
+static int __init pxa2xx_clock_init(void)
+{
+        if (cpu_is_pxa2xx())
+                return sysdev_class_register(&pxa2xx_clock_sysclass);
+        return 0;
+}
+postcore_initcall(pxa2xx_clock_init);
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
new file mode 100644
index 000000000000..1b08a34ab234
--- /dev/null
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -0,0 +1,218 @@
+/*
+ * linux/arch/arm/mach-pxa/clock-pxa3xx.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <mach/smemc.h>
+#include <mach/pxa3xx-regs.h>
+
+#include "clock.h"
+
+/* Crystal clock: 13MHz */
+#define BASE_CLK        13000000
+
+/* Ring Oscillator Clock: 60MHz */
+#define RO_CLK          60000000
+
+#define ACCR_D0CS       (1 << 26)
+#define ACCR_PCCE       (1 << 11)
+
+/* crystal frequency to HSIO bus frequency multiplier (HSS) */
+static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
+
+/*
+ * Get the clock frequency as reflected by CCSR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
+ */
+unsigned int pxa3xx_get_clk_frequency_khz(int info)
+{
+        unsigned long acsr, xclkcfg;
+        unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
+
+        /* Read XCLKCFG register turbo bit */
+        __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
+        t = xclkcfg & 0x1;
+
+        acsr = ACSR;
+
+        xl  = acsr & 0x1f;
+        xn  = (acsr >> 8) & 0x7;
+        hss = (acsr >> 14) & 0x3;
+
+        XL = xl * BASE_CLK;
+        XN = xn * XL;
+
+        ro = acsr & ACCR_D0CS;
+
+        CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
+        HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
+
+        if (info) {
+                pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
+                        RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
+                        (ro) ? "" : "in");
+                pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
+                        XL / 1000000, (XL % 1000000) / 10000, xl);
+                pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
+                        XN / 1000000, (XN % 1000000) / 10000, xn,
+                        (t) ? "" : "in");
+                pr_info("HSIO bus clock: %d.%02dMHz\n",
+                        HSS / 1000000, (HSS % 1000000) / 10000);
+        }
+
+        return CLK / 1000;
+}
+
+/*
+ * Return the current AC97 clock frequency.
+ */
+static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
+{
+        unsigned long rate = 312000000;
+        unsigned long ac97_div;
+
+        ac97_div = AC97_DIV;
+
+        /* This may loose precision for some rates but won't for the
+         * standard 24.576MHz.
+         */
+        rate /= (ac97_div >> 12) & 0x7fff;
+        rate *= (ac97_div & 0xfff);
+
+        return rate;
+}
+
+/*
+ * Return the current HSIO bus clock frequency
+ */
+static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
+{
+        unsigned long acsr;
+        unsigned int hss, hsio_clk;
+
+        acsr = ACSR;
+
+        hss = (acsr >> 14) & 0x3;
+        hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
+
+        return hsio_clk;
+}
+
+/* crystal frequency to static memory controller multiplier (SMCFS) */
+static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
+static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
+
+static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
+{
+        unsigned long acsr = ACSR;
+        unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
+        unsigned int smcfs = (acsr >> 23) & 0x7;
+
+        return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] /
+                        df_clkdiv[(memclkcfg >> 16) & 0x3];
+}
+
+void clk_pxa3xx_cken_enable(struct clk *clk)
+{
+        unsigned long mask = 1ul << (clk->cken & 0x1f);
+
+        if (clk->cken < 32)
+                CKENA |= mask;
+        else
+                CKENB |= mask;
+}
+
+void clk_pxa3xx_cken_disable(struct clk *clk)
+{
+        unsigned long mask = 1ul << (clk->cken & 0x1f);
+
+        if (clk->cken < 32)
+                CKENA &= ~mask;
+        else
+                CKENB &= ~mask;
+}
+
+const struct clkops clk_pxa3xx_cken_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+};
+
+const struct clkops clk_pxa3xx_hsio_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+        .getrate        = clk_pxa3xx_hsio_getrate,
+};
+
+const struct clkops clk_pxa3xx_ac97_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+        .getrate        = clk_pxa3xx_ac97_getrate,
+};
+
+const struct clkops clk_pxa3xx_smemc_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+        .getrate        = clk_pxa3xx_smemc_getrate,
+};
+
+static void clk_pout_enable(struct clk *clk)
+{
+        OSCC |= OSCC_PEN;
+}
+
+static void clk_pout_disable(struct clk *clk)
+{
+        OSCC &= ~OSCC_PEN;
+}
+
+const struct clkops clk_pxa3xx_pout_ops = {
+        .enable         = clk_pout_enable,
+        .disable        = clk_pout_disable,
+};
+
+#ifdef CONFIG_PM
+static uint32_t cken[2];
+static uint32_t accr;
+
+static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state)
+{
+        cken[0] = CKENA;
+        cken[1] = CKENB;
+        accr = ACCR;
+        return 0;
+}
+
+static int pxa3xx_clock_resume(struct sys_device *d)
+{
+        ACCR = accr;
+        CKENA = cken[0];
+        CKENB = cken[1];
+        return 0;
+}
+#else
+#define pxa3xx_clock_suspend    NULL
+#define pxa3xx_clock_resume     NULL
+#endif
+
+struct sysdev_class pxa3xx_clock_sysclass = {
+        .name           = "pxa3xx-clock",
+        .suspend        = pxa3xx_clock_suspend,
+        .resume         = pxa3xx_clock_resume,
+};
+
+static int __init pxa3xx_clock_init(void)
+{
+        if (cpu_is_pxa3xx() || cpu_is_pxa95x())
+                return sysdev_class_register(&pxa3xx_clock_sysclass);
+        return 0;
+}
+postcore_initcall(pxa3xx_clock_init);
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index abba0089a2ae..d5152220ce94 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -3,21 +3,11 @@
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
 #include <linux/clk.h>
 #include <linux/spinlock.h>
-#include <linux/platform_device.h>
 #include <linux/delay.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/hardware.h>
-
-#include "devices.h"
-#include "generic.h"
 #include "clock.h"
 
 static DEFINE_SPINLOCK(clocks_lock);
@@ -63,18 +53,19 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
-
-void clk_cken_enable(struct clk *clk)
+void clk_dummy_enable(struct clk *clk)
 {
-        CKEN |= 1 << clk->cken;
 }
 
-void clk_cken_disable(struct clk *clk)
+void clk_dummy_disable(struct clk *clk)
 {
-        CKEN &= ~(1 << clk->cken);
 }
 
-const struct clkops clk_cken_ops = {
-        .enable         = clk_cken_enable,
-        .disable        = clk_cken_disable,
+const struct clkops clk_dummy_ops = {
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable,
+};
+
+struct clk clk_dummy = {
+        .ops            = &clk_dummy_ops,
 };
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index d8488742b807..f9f349a21b54 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -1,4 +1,5 @@
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
+#include <linux/sysdev.h>
 
 struct clkops {
         void                    (*enable)(struct clk *);
@@ -14,6 +15,12 @@ struct clk {
         unsigned int            enabled;
 };
 
+void clk_dummy_enable(struct clk *);
+void clk_dummy_disable(struct clk *);
+
+extern const struct clkops clk_dummy_ops;
+extern struct clk clk_dummy;
+
 #define INIT_CLKREG(_clk,_devname,_conname)             \
         {                                               \
                 .clk            = _clk,                 \
@@ -21,14 +28,6 @@ struct clk {
                 .con_id         = _conname,             \
         }
 
-#define DEFINE_CKEN(_name, _cken, _rate, _delay)        \
-struct clk clk_##_name = {                              \
-                .ops    = &clk_cken_ops,                \
-                .rate   = _rate,                        \
-                .cken   = CKEN_##_cken,                 \
-                .delay  = _delay,                       \
-        }
-
 #define DEFINE_CK(_name, _cken, _ops)                   \
 struct clk clk_##_name = {                              \
                 .ops    = _ops,                         \
@@ -42,28 +41,38 @@ struct clk clk_##_name = {				\
                 .delay  = _delay,                       \
         }
 
-extern const struct clkops clk_cken_ops;
-
-void clk_cken_enable(struct clk *clk);
-void clk_cken_disable(struct clk *clk);
-
-#ifdef CONFIG_PXA3xx
-#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay)   \
+#define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay)   \
 struct clk clk_##_name = {                              \
-                .ops    = &clk_pxa3xx_cken_ops,         \
+                .ops    = &clk_pxa2xx_cken_ops,         \
                 .rate   = _rate,                        \
                 .cken   = CKEN_##_cken,                 \
                 .delay  = _delay,                       \
         }
 
-#define DEFINE_PXA3_CK(_name, _cken, _ops)              \
+extern const struct clkops clk_pxa2xx_cken_ops;
+
+void clk_pxa2xx_cken_enable(struct clk *clk);
+void clk_pxa2xx_cken_disable(struct clk *clk);
+
+extern struct sysdev_class pxa2xx_clock_sysclass;
+
+#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay)   \
 struct clk clk_##_name = {                              \
-                .ops    = _ops,                         \
+                .ops    = &clk_pxa3xx_cken_ops,         \
+                .rate   = _rate,                        \
                 .cken   = CKEN_##_cken,                 \
+                .delay  = _delay,                       \
         }
 
 extern const struct clkops clk_pxa3xx_cken_ops;
+extern const struct clkops clk_pxa3xx_hsio_ops;
+extern const struct clkops clk_pxa3xx_ac97_ops;
+extern const struct clkops clk_pxa3xx_pout_ops;
+extern const struct clkops clk_pxa3xx_smemc_ops;
+
 extern void clk_pxa3xx_cken_enable(struct clk *);
 extern void clk_pxa3xx_cken_disable(struct clk *);
-#endif
 
+extern struct sysdev_class pxa3xx_clock_sysclass;
+#endif
diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c
index f1a7703d771b..93f59f877fc6 100644
--- a/arch/arm/mach-pxa/cm-x255.c
+++ b/arch/arm/mach-pxa/cm-x255.c
@@ -17,13 +17,13 @@
 #include <linux/mtd/nand-gpio.h>
 
 #include <linux/spi/spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 
 #include <mach/pxa25x.h>
-#include <mach/pxa2xx_spi.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index a9926bb75922..b88d601a8090 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -19,12 +19,12 @@
 #include <video/mbxfb.h>
 
 #include <linux/spi/spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/spi/libertas_spi.h>
 
 #include <mach/pxa27x.h>
 #include <mach/ohci.h>
 #include <mach/mmc.h>
-#include <mach/pxa2xx_spi.h>
 
 #include "generic.h"
 
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index d34b99febeb9..b734d8468168 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -24,6 +24,7 @@
 #include <mach/pxa2xx-regs.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
+#include <mach/smemc.h>
 
 #include <asm/hardware/it8152.h>
 
@@ -392,9 +393,9 @@ static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state)
         cmx2xx_pci_suspend();
 
         /* save MSC registers */
-        sleep_save_msc[0] = MSC0;
-        sleep_save_msc[1] = MSC1;
-        sleep_save_msc[2] = MSC2;
+        sleep_save_msc[0] = __raw_readl(MSC0);
+        sleep_save_msc[1] = __raw_readl(MSC1);
+        sleep_save_msc[2] = __raw_readl(MSC2);
 
         /* setup power saving mode registers */
         PCFR = 0x0;
@@ -416,9 +417,9 @@ static int cmx2xx_resume(struct sys_device *dev)
         cmx2xx_pci_resume();
 
         /* restore MSC registers */
-        MSC0 = sleep_save_msc[0];
-        MSC1 = sleep_save_msc[1];
-        MSC2 = sleep_save_msc[2];
+        __raw_writel(sleep_save_msc[0], MSC0);
+        __raw_writel(sleep_save_msc[1], MSC1);
+        __raw_writel(sleep_save_msc[2], MSC2);
 
         return 0;
 }
@@ -498,7 +499,12 @@ static struct map_desc cmx2xx_io_desc[] __initdata = {
 
 static void __init cmx2xx_map_io(void)
 {
-        pxa_map_io();
+        if (cpu_is_pxa25x())
+                pxa25x_map_io();
+
+        if (cpu_is_pxa27x())
+                pxa27x_map_io();
+
         iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc));
 
         it8152_base_address = CMX2XX_IT8152_VIRT;
@@ -506,7 +512,11 @@ static void __init cmx2xx_map_io(void)
 #else
 static void __init cmx2xx_map_io(void)
 {
-        pxa_map_io();
+        if (cpu_is_pxa25x())
+                pxa25x_map_io();
+
+        if (cpu_is_pxa27x())
+                pxa27x_map_io();
 }
 #endif
 
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 922b1075b9de..7984268508b6 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -857,7 +857,7 @@ static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags,
 
 MACHINE_START(CM_X300, "CM-X300 module")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = cm_x300_init,
diff --git a/arch/arm/mach-pxa/colibri-pxa270-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c
index 0f3b632c3b14..6b2c800a1133 100644
--- a/arch/arm/mach-pxa/colibri-pxa270-evalboard.c
+++ b/arch/arm/mach-pxa/colibri-evalboard.c
@@ -1,7 +1,7 @@
 /*
- *  linux/arch/arm/mach-pxa/colibri-pxa270-evalboard.c
+ *  linux/arch/arm/mach-pxa/colibri-evalboard.c
  *
- *  Support for Toradex PXA270 based Colibri Evaluation Carrier Board
+ *  Support for Toradex Colibri Evaluation Carrier Board
  *  Daniel Mack <daniel@caiaq.de>
  *  Marek Vasut <marek.vasut@gmail.com>
  *
@@ -19,6 +19,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <asm/mach/arch.h>
+#include <linux/i2c.h>
 
 #include <mach/pxa27x.h>
 #include <mach/colibri.h>
@@ -26,86 +27,95 @@
 #include <mach/ohci.h>
 #include <mach/pxa27x-udc.h>
 
+#include <plat/i2c.h>
+
 #include "generic.h"
 #include "devices.h"
 
 /******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {
-        /* MMC */
-        GPIO32_MMC_CLK,
-        GPIO92_MMC_DAT_0,
-        GPIO109_MMC_DAT_1,
-        GPIO110_MMC_DAT_2,
-        GPIO111_MMC_DAT_3,
-        GPIO112_MMC_CMD,
-        GPIO0_GPIO,     /* SD detect */
-
-        /* FFUART */
-        GPIO39_FFUART_TXD,
-        GPIO34_FFUART_RXD,
-
-        /* UHC */
-        GPIO88_USBH1_PWR,
-        GPIO89_USBH1_PEN,
-        GPIO119_USBH2_PWR,
-        GPIO120_USBH2_PEN,
-};
-
-/******************************************************************************
  * SD/MMC card controller
  ******************************************************************************/
 #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static struct pxamci_platform_data colibri_pxa270_mci_platform_data = {
+static struct pxamci_platform_data colibri_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .gpio_power             = -1,
-        .gpio_card_detect       = GPIO0_COLIBRI_PXA270_SD_DETECT,
         .gpio_card_ro           = -1,
         .detect_delay_ms        = 200,
 };
 
-static void __init colibri_pxa270_mmc_init(void)
+static void __init colibri_mmc_init(void)
 {
-        pxa_set_mci_info(&colibri_pxa270_mci_platform_data);
+        if (machine_is_colibri())       /* PXA270 Colibri */
+                colibri_mci_platform_data.gpio_card_detect =
+                        GPIO0_COLIBRI_PXA270_SD_DETECT;
+        if (machine_is_colibri300())    /* PXA300 Colibri */
+                colibri_mci_platform_data.gpio_card_detect =
+                        GPIO39_COLIBRI_PXA300_SD_DETECT;
+        else                            /* PXA320 Colibri */
+                colibri_mci_platform_data.gpio_card_detect =
+                        GPIO28_COLIBRI_PXA320_SD_DETECT;
+
+        pxa_set_mci_info(&colibri_mci_platform_data);
 }
 #else
-static inline void colibri_pxa270_mmc_init(void) {}
+static inline void colibri_mmc_init(void) {}
 #endif
 
 /******************************************************************************
  * USB Host
  ******************************************************************************/
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static int colibri_pxa270_ohci_init(struct device *dev)
+static int colibri_ohci_init(struct device *dev)
 {
         UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
         return 0;
 }
 
-static struct pxaohci_platform_data colibri_pxa270_ohci_info = {
+static struct pxaohci_platform_data colibri_ohci_info = {
         .port_mode      = PMM_PERPORT_MODE,
-        .flags          = ENABLE_PORT1 | ENABLE_PORT2 |
+        .flags          = ENABLE_PORT1 |
                           POWER_CONTROL_LOW | POWER_SENSE_LOW,
-        .init           = colibri_pxa270_ohci_init,
+        .init           = colibri_ohci_init,
 };
 
-static void __init colibri_pxa270_uhc_init(void)
+static void __init colibri_uhc_init(void)
 {
-        pxa_set_ohci_info(&colibri_pxa270_ohci_info);
+        /* Colibri PXA270 has two usb ports, TBA for 320 */
+        if (machine_is_colibri())
+                colibri_ohci_info.flags |= ENABLE_PORT2;
+
+        pxa_set_ohci_info(&colibri_ohci_info);
 }
 #else
-static inline void colibri_pxa270_uhc_init(void) {}
+static inline void colibri_uhc_init(void) {}
 #endif
 
-void __init colibri_pxa270_evalboard_init(void)
+/******************************************************************************
+ * I2C RTC
+ ******************************************************************************/
+#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE)
+static struct i2c_board_info __initdata colibri_i2c_devs[] = {
+        {
+                I2C_BOARD_INFO("m41t00", 0x68),
+        },
+};
+
+static void __init colibri_rtc_init(void)
+{
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(colibri_i2c_devs));
+}
+#else
+static inline void colibri_rtc_init(void) {}
+#endif
+
+void __init colibri_evalboard_init(void)
 {
-        pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_evalboard_pin_config));
         pxa_set_ffuart_info(NULL);
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
 
-        colibri_pxa270_mmc_init();
-        colibri_pxa270_uhc_init();
+        colibri_mmc_init();
+        colibri_uhc_init();
+        colibri_rtc_init();
 }
-
diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c
index 37f0f3ed7c61..07b62a096f17 100644
--- a/arch/arm/mach-pxa/colibri-pxa270-income.c
+++ b/arch/arm/mach-pxa/colibri-pxa270-income.c
@@ -46,52 +46,6 @@
 #define GPIO113_INCOME_TS_IRQ   (113)
 
 /******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static mfp_cfg_t income_pin_config[] __initdata = {
-        /* MMC */
-        GPIO32_MMC_CLK,
-        GPIO92_MMC_DAT_0,
-        GPIO109_MMC_DAT_1,
-        GPIO110_MMC_DAT_2,
-        GPIO111_MMC_DAT_3,
-        GPIO112_MMC_CMD,
-        GPIO0_GPIO,     /* SD detect */
-        GPIO1_GPIO,     /* SD read-only */
-
-        /* FFUART */
-        GPIO39_FFUART_TXD,
-        GPIO34_FFUART_RXD,
-
-        /* BFUART */
-        GPIO42_BTUART_RXD,
-        GPIO43_BTUART_TXD,
-        GPIO45_BTUART_RTS,
-
-        /* STUART */
-        GPIO46_STUART_RXD,
-        GPIO47_STUART_TXD,
-
-        /* UHC */
-        GPIO88_USBH1_PWR,
-        GPIO89_USBH1_PEN,
-
-        /* LCD */
-        GPIOxx_LCD_TFT_16BPP,
-
-        /* PWM */
-        GPIO16_PWM0_OUT,
-
-        /* I2C */
-        GPIO117_I2C_SCL,
-        GPIO118_I2C_SDA,
-
-        /* LED */
-        GPIO54_GPIO,    /* LED A */
-        GPIO55_GPIO,    /* LED B */
-};
-
-/******************************************************************************
  * SD/MMC card controller
  ******************************************************************************/
 #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
@@ -257,7 +211,6 @@ static inline void income_pwm_init(void) {}
 
 void __init colibri_pxa270_income_boardinit(void)
 {
-        pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config));
         pxa_set_ffuart_info(NULL);
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index bc045100ec15..6fc5d328ba7f 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -33,6 +33,103 @@
 #include "generic.h"
 
 /******************************************************************************
+ * Evaluation board MFP
+ ******************************************************************************/
+#ifdef   CONFIG_MACH_COLIBRI_EVALBOARD
+static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO0_GPIO,     /* SD detect */
+
+        /* FFUART */
+        GPIO39_FFUART_TXD,
+        GPIO34_FFUART_RXD,
+
+        /* UHC */
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+        GPIO119_USBH2_PWR,
+        GPIO120_USBH2_PEN,
+
+        /* PCMCIA */
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO55_nPREG,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO49_nPWE,
+        GPIO48_nPOE,
+        GPIO57_nIOIS16,
+        GPIO56_nPWAIT,
+        GPIO104_PSKTSEL,
+        GPIO53_GPIO,    /* RESET */
+        GPIO83_GPIO,    /* BVD1 */
+        GPIO82_GPIO,    /* BVD2 */
+        GPIO1_GPIO,     /* READY */
+        GPIO84_GPIO,    /* DETECT */
+        GPIO107_GPIO,   /* PPEN */
+
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+};
+#else
+static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {};
+#endif
+
+#ifdef  CONFIG_MACH_COLIBRI_PXA270_INCOME
+static mfp_cfg_t income_pin_config[] __initdata = {
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO0_GPIO,     /* SD detect */
+        GPIO1_GPIO,     /* SD read-only */
+
+        /* FFUART */
+        GPIO39_FFUART_TXD,
+        GPIO34_FFUART_RXD,
+
+        /* BFUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO45_BTUART_RTS,
+
+        /* STUART */
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+
+        /* UHC */
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+
+        /* LCD */
+        GPIOxx_LCD_TFT_16BPP,
+
+        /* PWM */
+        GPIO16_PWM0_OUT,
+
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+
+        /* LED */
+        GPIO54_GPIO,    /* LED A */
+        GPIO55_GPIO,    /* LED B */
+};
+#else
+static mfp_cfg_t income_pin_config[] __initdata = {};
+#endif
+
+/******************************************************************************
  * Pin configuration
  ******************************************************************************/
 static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = {
@@ -184,10 +281,13 @@ static void __init colibri_pxa270_init(void)
         colibri_pxa270_tsc_init();
 
         switch (colibri_pxa270_baseboard) {
-        case COLIBRI_PXA270_EVALBOARD:
-                colibri_pxa270_evalboard_init();
+        case COLIBRI_EVALBOARD:
+                pxa2xx_mfp_config(ARRAY_AND_SIZE(
+                        colibri_pxa270_evalboard_pin_config));
+                colibri_evalboard_init();
                 break;
         case COLIBRI_PXA270_INCOME:
+                pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config));
                 colibri_pxa270_income_boardinit();
                 break;
         default:
@@ -209,7 +309,7 @@ static void __init colibri_pxa270_income_init(void)
 MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
         .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
         .init_machine   = colibri_pxa270_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
@@ -217,7 +317,7 @@ MACHINE_END
 MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
         .boot_params    = 0xa0000100,
         .init_machine   = colibri_pxa270_income_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index a70b256591e6..fddb16d07eb0 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -31,9 +31,38 @@
 #include "generic.h"
 #include "devices.h"
 
+
+#ifdef CONFIG_MACH_COLIBRI_EVALBOARD
+static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {
+        /* MMC */
+        GPIO7_MMC1_CLK,
+        GPIO14_MMC1_CMD,
+        GPIO3_MMC1_DAT0,
+        GPIO4_MMC1_DAT1,
+        GPIO5_MMC1_DAT2,
+        GPIO6_MMC1_DAT3,
+        GPIO39_GPIO,    /* SD detect */
+
+        /* UHC */
+        GPIO0_2_USBH_PEN,
+        GPIO1_2_USBH_PWR,
+        GPIO77_USB_P3_1,
+        GPIO78_USB_P3_2,
+        GPIO79_USB_P3_3,
+        GPIO80_USB_P3_4,
+        GPIO81_USB_P3_5,
+        GPIO82_USB_P3_6,
+
+        /* I2C */
+        GPIO21_I2C_SCL,
+        GPIO22_I2C_SDA,
+};
+#else
+static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {};
+#endif
+
 #if defined(CONFIG_AX88796)
 #define COLIBRI_ETH_IRQ_GPIO    mfp_to_gpio(GPIO26_GPIO)
-
 /*
  * Asix AX88796 Ethernet
  */
@@ -80,35 +109,6 @@ static void __init colibri_pxa300_init_eth(void)
 static inline void __init colibri_pxa300_init_eth(void) {}
 #endif /* CONFIG_AX88796 */
 
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static mfp_cfg_t colibri_pxa300_usb_pin_config[] __initdata = {
-        GPIO0_2_USBH_PEN,
-        GPIO1_2_USBH_PWR,
-};
-
-static struct pxaohci_platform_data colibri_pxa300_ohci_info = {
-        .port_mode      = PMM_GLOBAL_MODE,
-        .flags          = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
-};
-
-void __init colibri_pxa300_init_ohci(void)
-{
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_usb_pin_config));
-        pxa_set_ohci_info(&colibri_pxa300_ohci_info);
-}
-#else
-static inline void colibri_pxa300_init_ohci(void) {}
-#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
-
-static mfp_cfg_t colibri_pxa300_mmc_pin_config[] __initdata = {
-        GPIO7_MMC1_CLK,
-        GPIO14_MMC1_CMD,
-        GPIO3_MMC1_DAT0,
-        GPIO4_MMC1_DAT1,
-        GPIO5_MMC1_DAT2,
-        GPIO6_MMC1_DAT3,
-};
-
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
 static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = {
         GPIO54_LCD_LDD_0,
@@ -171,24 +171,21 @@ static inline void colibri_pxa310_init_ac97(void) {}
 
 void __init colibri_pxa300_init(void)
 {
-        pxa_set_ffuart_info(NULL);
-        pxa_set_btuart_info(NULL);
-        pxa_set_stuart_info(NULL);
-
         colibri_pxa300_init_eth();
-        colibri_pxa300_init_ohci();
         colibri_pxa3xx_init_nand();
         colibri_pxa300_init_lcd();
         colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO));
         colibri_pxa310_init_ac97();
-        colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa300_mmc_pin_config),
-                                mfp_to_gpio(MFP_PIN_GPIO13));
+
+        /* Evalboard init */
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_evalboard_pin_config));
+        colibri_evalboard_init();
 }
 
 MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
         .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
         .init_machine   = colibri_pxa300_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index ca5f29e2e9cd..ff9ff5f4fc47 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -35,9 +35,72 @@
 #include "generic.h"
 #include "devices.h"
 
+#ifdef  CONFIG_MACH_COLIBRI_EVALBOARD
+static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = {
+        /* MMC */
+        GPIO22_MMC1_CLK,
+        GPIO23_MMC1_CMD,
+        GPIO18_MMC1_DAT0,
+        GPIO19_MMC1_DAT1,
+        GPIO20_MMC1_DAT2,
+        GPIO21_MMC1_DAT3,
+        GPIO28_GPIO,    /* SD detect */
+
+        /* UART 1 configuration (may be set by bootloader) */
+        GPIO99_UART1_CTS,
+        GPIO104_UART1_RTS,
+        GPIO97_UART1_RXD,
+        GPIO98_UART1_TXD,
+        GPIO101_UART1_DTR,
+        GPIO103_UART1_DSR,
+        GPIO100_UART1_DCD,
+        GPIO102_UART1_RI,
+
+        /* UART 2 configuration */
+        GPIO109_UART2_CTS,
+        GPIO112_UART2_RTS,
+        GPIO110_UART2_RXD,
+        GPIO111_UART2_TXD,
+
+        /* UART 3 configuration */
+        GPIO30_UART3_RXD,
+        GPIO31_UART3_TXD,
+
+        /* UHC */
+        GPIO2_2_USBH_PEN,
+        GPIO3_2_USBH_PWR,
+
+        /* I2C */
+        GPIO32_I2C_SCL,
+        GPIO33_I2C_SDA,
+
+        /* PCMCIA */
+        MFP_CFG(GPIO59, AF7),   /* PRST ; AF7 to tristate */
+        MFP_CFG(GPIO61, AF7),   /* PCE1 ; AF7 to tristate */
+        MFP_CFG(GPIO60, AF7),   /* PCE2 ; AF7 to tristate */
+        MFP_CFG(GPIO62, AF7),   /* PCD ; AF7 to tristate */
+        MFP_CFG(GPIO56, AF7),   /* PSKTSEL ; AF7 to tristate */
+        GPIO27_GPIO,            /* RDnWR ; input/tristate */
+        GPIO50_GPIO,            /* PREG ; input/tristate */
+        GPIO2_RDY,
+        GPIO5_NPIOR,
+        GPIO6_NPIOW,
+        GPIO7_NPIOS16,
+        GPIO8_NPWAIT,
+        GPIO29_GPIO,            /* PRDY (READY GPIO) */
+        GPIO57_GPIO,            /* PPEN (POWER GPIO) */
+        GPIO81_GPIO,            /* PCD (DETECT GPIO) */
+        GPIO77_GPIO,            /* PRST (RESET GPIO) */
+        GPIO53_GPIO,            /* PBVD1 */
+        GPIO79_GPIO,            /* PBVD2 */
+        GPIO54_GPIO,            /* POE */
+};
+#else
+static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = {};
+#endif
+
 #if defined(CONFIG_AX88796)
 #define COLIBRI_ETH_IRQ_GPIO    mfp_to_gpio(GPIO36_GPIO)
-
 /*
  * Asix AX88796 Ethernet
  */
@@ -84,26 +147,6 @@ static void __init colibri_pxa320_init_eth(void)
 static inline void __init colibri_pxa320_init_eth(void) {}
 #endif /* CONFIG_AX88796 */
 
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static mfp_cfg_t colibri_pxa320_usb_pin_config[] __initdata = {
-        GPIO2_2_USBH_PEN,
-        GPIO3_2_USBH_PWR,
-};
-
-static struct pxaohci_platform_data colibri_pxa320_ohci_info = {
-        .port_mode      = PMM_GLOBAL_MODE,
-        .flags          = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
-};
-
-void __init colibri_pxa320_init_ohci(void)
-{
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_usb_pin_config));
-        pxa_set_ohci_info(&colibri_pxa320_ohci_info);
-}
-#else
-static inline void colibri_pxa320_init_ohci(void) {}
-#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
-
 #if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE)
 static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = {
         .gpio_vbus              = mfp_to_gpio(MFP_PIN_GPIO96),
@@ -140,15 +183,6 @@ static void __init colibri_pxa320_init_udc(void)
 static inline void colibri_pxa320_init_udc(void) {}
 #endif
 
-static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = {
-        GPIO22_MMC1_CLK,
-        GPIO23_MMC1_CMD,
-        GPIO18_MMC1_DAT0,
-        GPIO19_MMC1_DAT1,
-        GPIO20_MMC1_DAT2,
-        GPIO21_MMC1_DAT3
-};
-
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
 static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = {
         GPIO6_2_LCD_LDD_0,
@@ -205,59 +239,24 @@ static inline void __init colibri_pxa320_init_ac97(void)
 static inline void colibri_pxa320_init_ac97(void) {}
 #endif
 
-/*
- * The following configuration is verified to work with the Toradex Orchid
- * carrier board
- */
-static mfp_cfg_t colibri_pxa320_uart_pin_config[] __initdata = {
-        /* UART 1 configuration (may be set by bootloader) */
-        GPIO99_UART1_CTS,
-        GPIO104_UART1_RTS,
-        GPIO97_UART1_RXD,
-        GPIO98_UART1_TXD,
-        GPIO101_UART1_DTR,
-        GPIO103_UART1_DSR,
-        GPIO100_UART1_DCD,
-        GPIO102_UART1_RI,
-
-        /* UART 2 configuration */
-        GPIO109_UART2_CTS,
-        GPIO112_UART2_RTS,
-        GPIO110_UART2_RXD,
-        GPIO111_UART2_TXD,
-
-        /* UART 3 configuration */
-        GPIO30_UART3_RXD,
-        GPIO31_UART3_TXD,
-};
-
-static void __init colibri_pxa320_init_uart(void)
-{
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_uart_pin_config));
-}
-
 void __init colibri_pxa320_init(void)
 {
-        pxa_set_ffuart_info(NULL);
-        pxa_set_btuart_info(NULL);
-        pxa_set_stuart_info(NULL);
-
         colibri_pxa320_init_eth();
-        colibri_pxa320_init_ohci();
         colibri_pxa3xx_init_nand();
         colibri_pxa320_init_lcd();
         colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO));
         colibri_pxa320_init_ac97();
-        colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config),
-                                mfp_to_gpio(MFP_PIN_GPIO28));
-        colibri_pxa320_init_uart();
         colibri_pxa320_init_udc();
+
+        /* Evalboard init */
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_evalboard_pin_config));
+        colibri_evalboard_init();
 }
 
 MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
         .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
         .init_machine   = colibri_pxa320_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index 199afa2ae303..96b2d9fbfef0 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -64,55 +64,6 @@ void __init colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data)
 }
 #endif
 
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static int mmc_detect_pin;
-
-static int colibri_pxa3xx_mci_init(struct device *dev,
-                                   irq_handler_t colibri_mmc_detect_int,
-                                   void *data)
-{
-        int ret;
-
-        ret = gpio_request(mmc_detect_pin, "mmc card detect");
-        if (ret)
-                return ret;
-
-        gpio_direction_input(mmc_detect_pin);
-        ret = request_irq(gpio_to_irq(mmc_detect_pin), colibri_mmc_detect_int,
-                          IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
-                          "MMC card detect", data);
-        if (ret) {
-                gpio_free(mmc_detect_pin);
-                return ret;
-        }
-
-        return 0;
-}
-
-static void colibri_pxa3xx_mci_exit(struct device *dev, void *data)
-{
-        free_irq(mmc_detect_pin, data);
-        gpio_free(gpio_to_irq(mmc_detect_pin));
-}
-
-static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = {
-        .detect_delay_ms        = 200,
-        .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
-        .init                   = colibri_pxa3xx_mci_init,
-        .exit                   = colibri_pxa3xx_mci_exit,
-        .gpio_card_detect       = -1,
-        .gpio_card_ro           = -1,
-        .gpio_power             = -1,
-};
-
-void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin)
-{
-        pxa3xx_mfp_config(pins, len);
-        mmc_detect_pin = detect_pin;
-        pxa_set_mci_info(&colibri_pxa3xx_mci_platform_data);
-}
-#endif /* CONFIG_MMC_PXA || CONFIG_MMC_PXA_MODULE */
-
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
 static int lcd_bl_pin;
 
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 821229acabe6..a5452a3a276d 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -28,6 +28,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/spi/corgi_lcd.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/mtd/sharpsl.h>
 #include <linux/input/matrix_keypad.h>
 #include <video/w100fb.h>
@@ -48,7 +49,6 @@
 #include <mach/irda.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
-#include <mach/pxa2xx_spi.h>
 #include <mach/corgi.h>
 #include <mach/sharpsl_pm.h>
 
@@ -721,7 +721,7 @@ static void __init fixup_corgi(struct machine_desc *desc,
 #ifdef CONFIG_MACH_CORGI
 MACHINE_START(CORGI, "SHARP Corgi")
         .fixup          = fixup_corgi,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = corgi_init,
         .timer          = &pxa_timer,
@@ -731,7 +731,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_SHEPHERD
 MACHINE_START(SHEPHERD, "SHARP Shepherd")
         .fixup          = fixup_corgi,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = corgi_init,
         .timer          = &pxa_timer,
@@ -741,7 +741,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_HUSKY
 MACHINE_START(HUSKY, "SHARP Husky")
         .fixup          = fixup_corgi,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = corgi_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 58093d9e07be..6a7aeab42f6c 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -38,8 +38,10 @@
 #include <linux/cpufreq.h>
 #include <linux/err.h>
 #include <linux/regulator/consumer.h>
+#include <linux/io.h>
 
 #include <mach/pxa2xx-regs.h>
+#include <mach/smemc.h>
 
 #ifdef DEBUG
 static unsigned int freq_debug;
@@ -242,7 +244,7 @@ static void pxa27x_guess_max_freq(void)
 
 static void init_sdram_rows(void)
 {
-        uint32_t mdcnfg = MDCNFG;
+        uint32_t mdcnfg = __raw_readl(MDCNFG);
         unsigned int drac2 = 0, drac0 = 0;
 
         if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
@@ -331,8 +333,8 @@ static int pxa_set_target(struct cpufreq_policy *policy,
          * we need to preset the smaller DRI before the change.  If we're
          * speeding up we need to set the larger DRI value after the change.
          */
-        preset_mdrefr = postset_mdrefr = MDREFR;
-        if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
+        preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
+        if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
                 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
                 preset_mdrefr |= mdrefr_dri(new_freq_mem);
         }
@@ -370,7 +372,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
 3:              nop                                                     \n\
           "
                      : "=&r" (unused)
-                     : "r" (&MDREFR), "r" (cclkcfg),
+                     : "r" (MDREFR), "r" (cclkcfg),
                        "r" (preset_mdrefr), "r" (postset_mdrefr)
                      : "r4", "r5");
         local_irq_restore(flags);
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 57cacaff194d..a305424a967d 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -27,6 +27,7 @@
 #include <mach/ohci.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/audio.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -255,9 +256,9 @@ static struct platform_device *devices[] __initdata = {
 static void __init csb726_init(void)
 {
         pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config));
-/*      MSC1 = 0x7ffc3ffc; *//* LAN9215/EXP_CS */
-/*      MSC2 = 0x06697ff4; *//* none/SM501 */
-        MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */
+/*      __raw_writel(0x7ffc3ffc, MSC1); *//* LAN9215/EXP_CS */
+/*      __raw_writel(0x06697ff4, MSC2); *//* none/SM501 */
+        __raw_writel((__raw_readl(MSC2) & ~0xffff) | 0x7ff4, MSC2); /* SM501 */
 
         pxa_set_ffuart_info(NULL);
         pxa_set_btuart_info(NULL);
@@ -273,7 +274,7 @@ static void __init csb726_init(void)
 
 MACHINE_START(CSB726, "Cogent CSB726")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .init_machine   = csb726_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index aaa1166df964..4c766e3b4af3 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -3,6 +3,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/spi/pxa2xx_spi.h>
 
 #include <asm/pmu.h>
 #include <mach/udc.h>
@@ -12,7 +13,6 @@
 #include <mach/irda.h>
 #include <mach/ohci.h>
 #include <plat/pxa27x_keypad.h>
-#include <mach/pxa2xx_spi.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
 #include <mach/hardware.h>
@@ -342,27 +342,6 @@ struct platform_device pxa27x_device_i2c_power = {
 };
 #endif
 
-#ifdef CONFIG_PXA3xx
-static struct resource pxa3xx_resources_i2c_power[] = {
-        {
-                .start  = 0x40f500c0,
-                .end    = 0x40f500d3,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_PWRI2C,
-                .end    = IRQ_PWRI2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device pxa3xx_device_i2c_power = {
-        .name           = "pxa3xx-pwri2c",
-        .id             = 1,
-        .resource       = pxa3xx_resources_i2c_power,
-        .num_resources  = ARRAY_SIZE(pxa3xx_resources_i2c_power),
-};
-#endif
-
 static struct resource pxai2s_resources[] = {
         {
                 .start  = 0x40400000,
@@ -633,30 +612,35 @@ struct platform_device pxa25x_device_assp = {
 #endif /* CONFIG_PXA25x */
 
 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-
-static struct resource pxa27x_resource_keypad[] = {
+static struct resource pxa27x_resource_camera[] = {
         [0] = {
-                .start  = 0x41500000,
-                .end    = 0x4150004c,
+                .start  = 0x50000000,
+                .end    = 0x50000fff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_KEYPAD,
-                .end    = IRQ_KEYPAD,
+                .start  = IRQ_CAMERA,
+                .end    = IRQ_CAMERA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-struct platform_device pxa27x_device_keypad = {
-        .name           = "pxa27x-keypad",
-        .id             = -1,
-        .resource       = pxa27x_resource_keypad,
-        .num_resources  = ARRAY_SIZE(pxa27x_resource_keypad),
+static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
+
+static struct platform_device pxa27x_device_camera = {
+        .name           = "pxa27x-camera",
+        .id             = 0, /* This is used to put cameras on this interface */
+        .dev            = {
+                .dma_mask               = &pxa27x_dma_mask_camera,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_camera),
+        .resource       = pxa27x_resource_camera,
 };
 
-void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
+void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
 {
-        pxa_register_device(&pxa27x_device_keypad, info);
+        pxa_register_device(&pxa27x_device_camera, info);
 }
 
 static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
@@ -689,6 +673,33 @@ void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
 {
         pxa_register_device(&pxa27x_device_ohci, info);
 }
+#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+static struct resource pxa27x_resource_keypad[] = {
+        [0] = {
+                .start  = 0x41500000,
+                .end    = 0x4150004c,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_KEYPAD,
+                .end    = IRQ_KEYPAD,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa27x_device_keypad = {
+        .name           = "pxa27x-keypad",
+        .id             = -1,
+        .resource       = pxa27x_resource_keypad,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_keypad),
+};
+
+void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
+{
+        pxa_register_device(&pxa27x_device_keypad, info);
+}
 
 static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
 
@@ -833,79 +844,9 @@ struct platform_device pxa27x_device_pwm1 = {
         .resource       = pxa27x_resource_pwm1,
         .num_resources  = ARRAY_SIZE(pxa27x_resource_pwm1),
 };
-
-static struct resource pxa27x_resource_camera[] = {
-        [0] = {
-                .start  = 0x50000000,
-                .end    = 0x50000fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_CAMERA,
-                .end    = IRQ_CAMERA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
-
-static struct platform_device pxa27x_device_camera = {
-        .name           = "pxa27x-camera",
-        .id             = 0, /* This is used to put cameras on this interface */
-        .dev            = {
-                .dma_mask               = &pxa27x_dma_mask_camera,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(pxa27x_resource_camera),
-        .resource       = pxa27x_resource_camera,
-};
-
-void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
-{
-        pxa_register_device(&pxa27x_device_camera, info);
-}
-#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
+#endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
 
 #ifdef CONFIG_PXA3xx
-static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource pxa3xx_resource_ssp4[] = {
-        [0] = {
-                .start  = 0x41a00000,
-                .end    = 0x41a0003f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_SSP4,
-                .end    = IRQ_SSP4,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                /* DRCMR for RX */
-                .start  = 2,
-                .end    = 2,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                /* DRCMR for TX */
-                .start  = 3,
-                .end    = 3,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-
-struct platform_device pxa3xx_device_ssp4 = {
-        /* PXA3xx SSP is basically equivalent to PXA27x */
-        .name           = "pxa27x-ssp",
-        .id             = 3,
-        .dev            = {
-                .dma_mask = &pxa3xx_ssp4_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-        .resource       = pxa3xx_resource_ssp4,
-        .num_resources  = ARRAY_SIZE(pxa3xx_resource_ssp4),
-};
-
 static struct resource pxa3xx_resources_mci2[] = {
         [0] = {
                 .start  = 0x42000000,
@@ -984,6 +925,54 @@ void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
         pxa_register_device(&pxa3xx_device_mci3, info);
 }
 
+static struct resource pxa3xx_resources_gcu[] = {
+        {
+                .start  = 0x54000000,
+                .end    = 0x54000fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_GCU,
+                .end    = IRQ_GCU,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device pxa3xx_device_gcu = {
+        .name           = "pxa3xx-gcu",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa3xx_resources_gcu),
+        .resource       = pxa3xx_resources_gcu,
+        .dev            = {
+                .dma_mask = &pxa3xx_gcu_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
+
+#endif /* CONFIG_PXA3xx */
+
+#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+static struct resource pxa3xx_resources_i2c_power[] = {
+        {
+                .start  = 0x40f500c0,
+                .end    = 0x40f500d3,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PWRI2C,
+                .end    = IRQ_PWRI2C,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa3xx_device_i2c_power = {
+        .name           = "pxa3xx-pwri2c",
+        .id             = 1,
+        .resource       = pxa3xx_resources_i2c_power,
+        .num_resources  = ARRAY_SIZE(pxa3xx_resources_i2c_power),
+};
+
 static struct resource pxa3xx_resources_nand[] = {
         [0] = {
                 .start  = 0x43100000,
@@ -1027,33 +1016,45 @@ void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
         pxa_register_device(&pxa3xx_device_nand, info);
 }
 
-static struct resource pxa3xx_resources_gcu[] = {
-        {
-                .start  = 0x54000000,
-                .end    = 0x54000fff,
+static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource pxa3xx_resource_ssp4[] = {
+        [0] = {
+                .start  = 0x41a00000,
+                .end    = 0x41a0003f,
                 .flags  = IORESOURCE_MEM,
         },
-        {
-                .start  = IRQ_GCU,
-                .end    = IRQ_GCU,
+        [1] = {
+                .start  = IRQ_SSP4,
+                .end    = IRQ_SSP4,
                 .flags  = IORESOURCE_IRQ,
         },
+        [2] = {
+                /* DRCMR for RX */
+                .start  = 2,
+                .end    = 2,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                /* DRCMR for TX */
+                .start  = 3,
+                .end    = 3,
+                .flags  = IORESOURCE_DMA,
+        },
 };
 
-static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device pxa3xx_device_gcu = {
-        .name           = "pxa3xx-gcu",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(pxa3xx_resources_gcu),
-        .resource       = pxa3xx_resources_gcu,
+struct platform_device pxa3xx_device_ssp4 = {
+        /* PXA3xx SSP is basically equivalent to PXA27x */
+        .name           = "pxa27x-ssp",
+        .id             = 3,
         .dev            = {
-                .dma_mask = &pxa3xx_gcu_dmamask,
-                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &pxa3xx_ssp4_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
         },
+        .resource       = pxa3xx_resource_ssp4,
+        .num_resources  = ARRAY_SIZE(pxa3xx_resource_ssp4),
 };
-
-#endif /* CONFIG_PXA3xx */
+#endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
 
 /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index ed0dbfdb22ed..a78bb3097739 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -26,6 +26,7 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/tdo24m.h>
 #include <linux/spi/libertas_spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/power_supply.h>
 #include <linux/apm-emulation.h>
 #include <linux/i2c.h>
@@ -46,7 +47,6 @@
 #include <plat/pxa27x_keypad.h>
 #include <plat/i2c.h>
 #include <mach/camera.h>
-#include <mach/pxa2xx_spi.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -1300,7 +1300,7 @@ static void __init em_x270_init(void)
 
 MACHINE_START(EM_X270, "Compulab EM-X270")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = em_x270_init,
@@ -1308,7 +1308,7 @@ MACHINE_END
 
 MACHINE_START(EXEDA, "Compulab eXeda")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = em_x270_init,
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index b25690ccadc4..edca0a043293 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -181,7 +181,7 @@ static void __init e330_init(void)
 MACHINE_START(E330, "Toshiba e330")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
@@ -230,7 +230,7 @@ static void __init e350_init(void)
 MACHINE_START(E350, "Toshiba e350")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
@@ -352,7 +352,7 @@ static void __init e400_init(void)
 MACHINE_START(E400, "Toshiba e400")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
@@ -540,7 +540,7 @@ static void __init e740_init(void)
 MACHINE_START(E740, "Toshiba e740")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
@@ -731,7 +731,7 @@ static void __init e750_init(void)
 MACHINE_START(E750, "Toshiba e750")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
@@ -926,7 +926,7 @@ static void __init e800_init(void)
 MACHINE_START(E800, "Toshiba e800")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 142c711f4cda..87cec0abe5b0 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -798,7 +798,7 @@ static void __init a780_init(void)
 
 MACHINE_START(EZX_A780, "Motorola EZX A780")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -863,7 +863,7 @@ static void __init e680_init(void)
 
 MACHINE_START(EZX_E680, "Motorola EZX E680")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -928,7 +928,7 @@ static void __init a1200_init(void)
 
 MACHINE_START(EZX_A1200, "Motorola EZX A1200")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -1118,7 +1118,7 @@ static void __init a910_init(void)
 
 MACHINE_START(EZX_A910, "Motorola EZX A910")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -1183,7 +1183,7 @@ static void __init e6_init(void)
 
 MACHINE_START(EZX_E6, "Motorola EZX E6")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -1222,7 +1222,7 @@ static void __init e2_init(void)
 
 MACHINE_START(EZX_E2, "Motorola EZX E2")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 6451e9c3a93f..d6e15f71fc09 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -28,6 +28,8 @@
 
 #include <mach/reset.h>
 #include <mach/gpio.h>
+#include <mach/smemc.h>
+#include <mach/pxa3xx-regs.h>
 
 #include "generic.h"
 
@@ -35,9 +37,10 @@ void clear_reset_status(unsigned int mask)
 {
         if (cpu_is_pxa2xx())
                 pxa2xx_clear_reset_status(mask);
-
-        if (cpu_is_pxa3xx())
-                pxa3xx_clear_reset_status(mask);
+        else {
+                /* RESET_STATUS_* has a 1:1 mapping with ARSR */
+                ARSR = mask;
+        }
 }
 
 unsigned long get_clock_tick_rate(void)
@@ -71,47 +74,17 @@ unsigned int get_clk_frequency_khz(int info)
 EXPORT_SYMBOL(get_clk_frequency_khz);
 
 /*
- * Return the current memory clock frequency in units of 10kHz
- */
-unsigned int get_memclk_frequency_10khz(void)
-{
-        if (cpu_is_pxa25x())
-                return pxa25x_get_memclk_frequency_10khz();
-        else if (cpu_is_pxa27x())
-                return pxa27x_get_memclk_frequency_10khz();
-        return 0;
-}
-EXPORT_SYMBOL(get_memclk_frequency_10khz);
-
-/*
  * Intel PXA2xx internal register mapping.
  *
- * Note 1: not all PXA2xx variants implement all those addresses.
- *
- * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
- *         and cache flush area.
+ * Note: virtual 0xfffe0000-0xffffffff is reserved for the vector table
+ *       and cache flush area.
  */
-static struct map_desc standard_io_desc[] __initdata = {
+static struct map_desc common_io_desc[] __initdata = {
         {       /* Devs */
                 .virtual        =  0xf2000000,
                 .pfn            = __phys_to_pfn(0x40000000),
                 .length         = 0x02000000,
                 .type           = MT_DEVICE
-        }, {    /* Mem Ctl */
-                .virtual        =  0xf6000000,
-                .pfn            = __phys_to_pfn(0x48000000),
-                .length         = 0x00200000,
-                .type           = MT_DEVICE
-        }, {    /* Camera */
-                .virtual        =  0xfa000000,
-                .pfn            = __phys_to_pfn(0x50000000),
-                .length         = 0x00100000,
-                .type           = MT_DEVICE
-        }, {    /* IMem ctl */
-                .virtual        =  0xfe000000,
-                .pfn            = __phys_to_pfn(0x58000000),
-                .length         = 0x00100000,
-                .type           = MT_DEVICE
         }, {    /* UNCACHED_PHYS_0 */
                 .virtual        = 0xff000000,
                 .pfn            = __phys_to_pfn(0x00000000),
@@ -122,6 +95,5 @@ static struct map_desc standard_io_desc[] __initdata = {
 
 void __init pxa_map_io(void)
 {
-        iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
-        get_clk_frequency_khz(1);
+        iotable_init(ARRAY_AND_SIZE(common_io_desc));
 }
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 4b1ad2769ed7..6205dc9a2b9d 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -20,7 +20,12 @@ extern void __init pxa26x_init_irq(void);
 #endif
 extern void __init pxa27x_init_irq(void);
 extern void __init pxa3xx_init_irq(void);
+extern void __init pxa95x_init_irq(void);
+
 extern void __init pxa_map_io(void);
+extern void __init pxa25x_map_io(void);
+extern void __init pxa27x_map_io(void);
+extern void __init pxa3xx_map_io(void);
 
 extern unsigned int get_clk_frequency_khz(int info);
 
@@ -32,18 +37,14 @@ extern unsigned int get_clk_frequency_khz(int info);
 
 #ifdef CONFIG_PXA25x
 extern unsigned pxa25x_get_clk_frequency_khz(int);
-extern unsigned pxa25x_get_memclk_frequency_10khz(void);
 #else
 #define pxa25x_get_clk_frequency_khz(x)         (0)
-#define pxa25x_get_memclk_frequency_10khz()     (0)
 #endif
 
 #ifdef CONFIG_PXA27x
 extern unsigned pxa27x_get_clk_frequency_khz(int);
-extern unsigned pxa27x_get_memclk_frequency_10khz(void);
 #else
 #define pxa27x_get_clk_frequency_khz(x)         (0)
-#define pxa27x_get_memclk_frequency_10khz()     (0)
 #endif
 
 #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
@@ -54,10 +55,8 @@ static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
 
 #ifdef CONFIG_PXA3xx
 extern unsigned pxa3xx_get_clk_frequency_khz(int);
-extern void pxa3xx_clear_reset_status(unsigned int);
 #else
 #define pxa3xx_get_clk_frequency_khz(x)         (0)
-static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
 #endif
 
 extern struct sysdev_class pxa_irq_sysclass;
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 1e2a9a13aec1..6fd319ea5284 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -225,7 +225,7 @@ static void __init gumstix_init(void)
 
 MACHINE_START(GUMSTIX, "Gumstix")
         .boot_params    = 0xa0000100, /* match u-boot bi_boot_params */
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = gumstix_init,
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index 7057a1f46db4..657db469de1f 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -32,6 +32,7 @@
 #include <mach/pxa25x.h>
 #include <mach/h5000.h>
 #include <mach/udc.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 
@@ -172,11 +173,11 @@ static unsigned long h5000_pin_config[] __initdata = {
 
 static void fix_msc(void)
 {
-        MSC0 = 0x129c24f2;
-        MSC1 = 0x7ff424fa;
-        MSC2 = 0x7ff47ff4;
+        __raw_writel(0x129c24f2, MSC0);
+        __raw_writel(0x7ff424fa, MSC1);
+        __raw_writel(0x7ff47ff4, MSC2);
 
-        MDREFR |= 0x02080000;
+        __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR);
 }
 
 /*
@@ -202,7 +203,7 @@ static void __init h5000_init(void)
 
 MACHINE_START(H5400, "HP iPAQ H5000")
         .boot_params = 0xa0000100,
-        .map_io = pxa_map_io,
+        .map_io = pxa25x_map_io,
         .init_irq = pxa25x_init_irq,
         .timer = &pxa_timer,
         .init_machine = h5000_init,
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index 01b7f07ebad2..e8603eba54bd 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -160,7 +160,7 @@ static void __init himalaya_init(void)
 
 MACHINE_START(HIMALAYA, "HTC Himalaya")
         .boot_params = 0xa0000100,
-        .map_io = pxa_map_io,
+        .map_io = pxa25x_map_io,
         .init_irq = pxa25x_init_irq,
         .init_machine = himalaya_init,
         .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 76d93a25bab6..a908e0a5f396 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -33,6 +33,7 @@
 #include <linux/regulator/max1586.h>
 #include <linux/spi/ads7846.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/usb/gpio_vbus.h>
 
 #include <mach/hardware.h>
@@ -43,7 +44,6 @@
 #include <mach/hx4700.h>
 #include <plat/i2c.h>
 #include <mach/irda.h>
-#include <mach/pxa2xx_spi.h>
 
 #include <video/platform_lcd.h>
 #include <video/w100fb.h>
@@ -871,7 +871,7 @@ static void __init hx4700_init(void)
 
 MACHINE_START(H4700, "HP iPAQ HX4700")
         .boot_params  = 0xa0000100,
-        .map_io       = pxa_map_io,
+        .map_io       = pxa27x_map_io,
         .nr_irqs      = HX4700_NR_IRQS,
         .init_irq     = pxa27x_init_irq,
         .init_machine = hx4700_init,
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index d51ee3d25e70..6cedc81da3bc 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -24,7 +24,7 @@
 #include <mach/mxm8x10.h>
 
 #include <linux/spi/spi.h>
-#include <mach/pxa2xx_spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/can/platform/mcp251x.h>
 
 #include "generic.h"
@@ -192,7 +192,7 @@ static void __init icontrol_init(void)
 
 MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = icontrol_init
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index e773dceeabc6..dd40e4a9291c 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -187,7 +187,7 @@ static struct map_desc idp_io_desc[] __initdata = {
 
 static void __init idp_map_io(void)
 {
-        pxa_map_io();
+        pxa25x_map_io();
         iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
 }
 
diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h
new file mode 100644
index 000000000000..f4c03659168c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/addr-map.h
@@ -0,0 +1,48 @@
+#ifndef __ASM_MACH_ADDR_MAP_H
+#define __ASM_MACH_ADDR_MAP_H
+
+/*
+ * Chip Selects
+ */
+#define PXA_CS0_PHYS            0x00000000
+#define PXA_CS1_PHYS            0x04000000
+#define PXA_CS2_PHYS            0x08000000
+#define PXA_CS3_PHYS            0x0C000000
+#define PXA_CS4_PHYS            0x10000000
+#define PXA_CS5_PHYS            0x14000000
+
+#define PXA300_CS0_PHYS         0x00000000      /* PXA300/PXA310 _only_ */
+#define PXA300_CS1_PHYS         0x30000000      /* PXA300/PXA310 _only_ */
+#define PXA3xx_CS2_PHYS         0x10000000
+#define PXA3xx_CS3_PHYS         0x14000000
+
+/*
+ * Peripheral Bus
+ */
+#define PERIPH_PHYS             0x40000000
+#define PERIPH_VIRT             0xf2000000
+#define PERIPH_SIZE             0x02000000
+
+/*
+ * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x)
+ */
+#define PXA2XX_SMEMC_PHYS       0x48000000
+#define PXA3XX_SMEMC_PHYS       0x4a000000
+#define SMEMC_VIRT              0xf6000000
+#define SMEMC_SIZE              0x00100000
+
+/*
+ * Dynamic Memory Controller (only on PXA3xx)
+ */
+#define DMEMC_PHYS              0x48100000
+#define DMEMC_VIRT              0xf6100000
+#define DMEMC_SIZE              0x00100000
+
+/*
+ * Internal Memory Controller (PXA27x and later)
+ */
+#define IMEMC_PHYS              0x58000000
+#define IMEMC_VIRT              0xfe000000
+#define IMEMC_SIZE              0x00100000
+
+#endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index 561562b4360b..7074e76146c9 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -26,6 +26,8 @@ enum balloon3_features {
 #define BALLOON3_FPGA_VIRT      (0xf1000000)    /* as per balloon2 */
 #define BALLOON3_FPGA_LENGTH    0x01000000
 
+#define BALLOON3_FPGA_SETnCLR           (0x1000)
+
 /* FPGA / CPLD registers for CF socket */
 #define BALLOON3_CF_STATUS_REG          (BALLOON3_FPGA_VIRT + 0x00e00008)
 #define BALLOON3_CF_CONTROL_REG         (BALLOON3_FPGA_VIRT + 0x00e00008)
@@ -35,7 +37,7 @@ enum balloon3_features {
 #define BALLOON3_NAND_BASE              (PXA_CS4_PHYS + 0x00e00000)
 #define BALLOON3_NAND_IO_REG            (BALLOON3_FPGA_VIRT + 0x00e00000)
 #define BALLOON3_NAND_CONTROL2_REG      (BALLOON3_FPGA_VIRT + 0x00e00010)
-#define BALLOON3_NAND_STAT_REG          (BALLOON3_FPGA_VIRT + 0x00e00010)
+#define BALLOON3_NAND_STAT_REG          (BALLOON3_FPGA_VIRT + 0x00e00014)
 #define BALLOON3_NAND_CONTROL_REG       (BALLOON3_FPGA_VIRT + 0x00e00014)
 
 /* fpga/cpld interrupt control register */
@@ -174,7 +176,7 @@ enum balloon3_features {
 #define BALLOON3_CODEC_IRQ      IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
 #define BALLOON3_S0_CD_IRQ      IRQ_GPIO(BALLOON3_GPIO_S0_CD)
 
-#define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 4)
+#define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 16)
 
 extern int balloon3_has(enum balloon3_features feature);
 
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index 58dada11054f..388a96f1ef93 100644
--- a/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
@@ -9,14 +9,14 @@
  */
 
 enum {
-        COLIBRI_PXA270_EVALBOARD = 0,
+        COLIBRI_EVALBOARD = 0,
         COLIBRI_PXA270_INCOME,
 };
 
-#if defined(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD)
-extern void colibri_pxa270_evalboard_init(void);
+#if defined(CONFIG_MACH_COLIBRI_EVALBOARD)
+extern void colibri_evalboard_init(void);
 #else
-static inline void colibri_pxa270_evalboard_init(void) {}
+static inline void colibri_evalboard_init(void) {}
 #endif
 
 #if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME)
@@ -59,5 +59,11 @@ static inline void colibri_pxa3xx_init_nand(void) {}
 #define GPIO0_COLIBRI_PXA270_SD_DETECT  0
 #define GPIO113_COLIBRI_PXA270_TS_IRQ   113
 
+/* GPIO definitions for Colibri PXA300/310 */
+#define GPIO39_COLIBRI_PXA300_SD_DETECT 39
+
+/* GPIO definitions for Colibri PXA320 */
+#define GPIO28_COLIBRI_PXA320_SD_DETECT 28
+
 #endif /* _COLIBRI_H_ */
 
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 814f1458a06a..6957ba56025b 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
+#include <mach/addr-map.h>
+
 /*
  * Workarounds for at least 2 errata so far require this.
  * The mapping is set in mach-pxa/generic.c.
@@ -193,14 +195,15 @@
 #define __cpu_is_pxa935(id)     (0)
 #endif
 
-#ifdef CONFIG_CPU_PXA950
-#define __cpu_is_pxa950(id)                             \
-        ({                                              \
+#ifdef CONFIG_CPU_PXA955
+#define __cpu_is_pxa955(id)                             \
+        ({                                              \
                 unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x697;                           \
-         })
+                _id == 0x581 || _id == 0xc08            \
+                        || _id == 0xb76;                \
+        })
 #else
-#define __cpu_is_pxa950(id)     (0)
+#define __cpu_is_pxa955(id)     (0)
 #endif
 
 #define cpu_is_pxa210()                                 \
@@ -253,16 +256,15 @@
                 __cpu_is_pxa935(read_cpuid_id());       \
          })
 
-#define cpu_is_pxa950()                                 \
+#define cpu_is_pxa955()                                 \
         ({                                              \
-                __cpu_is_pxa950(read_cpuid_id());       \
-         })
+                __cpu_is_pxa955(read_cpuid_id());       \
+        })
 
 
 /*
  * CPUID Core Generation Bit
  * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
- * == 0x3 for pxa300/pxa310/pxa320
  */
 #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
 #define __cpu_is_pxa2xx(id)                             \
@@ -277,8 +279,10 @@
 #ifdef CONFIG_PXA3xx
 #define __cpu_is_pxa3xx(id)                             \
         ({                                              \
-                unsigned int _id = (id) >> 13 & 0x7;    \
-                _id == 0x3;                             \
+                __cpu_is_pxa300(id)                     \
+                        || __cpu_is_pxa310(id)          \
+                        || __cpu_is_pxa320(id)          \
+                        || __cpu_is_pxa93x(id);         \
          })
 #else
 #define __cpu_is_pxa3xx(id)     (0)
@@ -287,13 +291,22 @@
 #if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
 #define __cpu_is_pxa93x(id)                             \
         ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x683 || _id == 0x693;           \
+                __cpu_is_pxa930(id)                     \
+                        || __cpu_is_pxa935(id);         \
          })
 #else
 #define __cpu_is_pxa93x(id)     (0)
 #endif
 
+#ifdef CONFIG_PXA95x
+#define __cpu_is_pxa95x(id)                             \
+        ({                                              \
+                __cpu_is_pxa955(id);                    \
+        })
+#else
+#define __cpu_is_pxa95x(id)     (0)
+#endif
+
 #define cpu_is_pxa2xx()                                 \
         ({                                              \
                 __cpu_is_pxa2xx(read_cpuid_id());       \
@@ -308,6 +321,12 @@
         ({                                              \
                 __cpu_is_pxa93x(read_cpuid_id());       \
          })
+
+#define cpu_is_pxa95x()                                 \
+        ({                                              \
+                __cpu_is_pxa95x(read_cpuid_id());       \
+        })
+
 /*
  * return current memory and LCD clock frequency in units of 10kHz
  */
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index d372caa75dc7..a4285fc00878 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -21,16 +21,14 @@
 
 #define PXA_IRQ(x)      (PXA_ISA_IRQ_NUM + (x))
 
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define IRQ_SSP3        PXA_IRQ(0)      /* SSP3 service request */
 #define IRQ_MSL         PXA_IRQ(1)      /* MSL Interface interrupt */
-#define IRQ_USBH2       PXA_IRQ(2)      /* USB Host interrupt 1 (OHCI) */
-#define IRQ_USBH1       PXA_IRQ(3)      /* USB Host interrupt 2 (non-OHCI) */
+#define IRQ_USBH2       PXA_IRQ(2)      /* USB Host interrupt 1 (OHCI,PXA27x) */
+#define IRQ_USBH1       PXA_IRQ(3)      /* USB Host interrupt 2 (non-OHCI,PXA27x) */
 #define IRQ_KEYPAD      PXA_IRQ(4)      /* Key pad controller */
-#define IRQ_MEMSTK      PXA_IRQ(5)      /* Memory Stick interrupt */
+#define IRQ_MEMSTK      PXA_IRQ(5)      /* Memory Stick interrupt (PXA27x) */
+#define IRQ_ACIPC0      PXA_IRQ(5)      /* AP-CP Communication (PXA930) */
 #define IRQ_PWRI2C      PXA_IRQ(6)      /* Power I2C interrupt */
-#endif
-
 #define IRQ_HWUART      PXA_IRQ(7)      /* HWUART Transmit/Receive/Error (PXA26x) */
 #define IRQ_OST_4_11    PXA_IRQ(7)      /* OS timer 4-11 matches (PXA27x) */
 #define IRQ_GPIO0       PXA_IRQ(8)      /* GPIO0 Edge Detect */
@@ -38,7 +36,8 @@
 #define IRQ_GPIO_2_x    PXA_IRQ(10)     /* GPIO[2-x] Edge Detect */
 #define IRQ_USB         PXA_IRQ(11)     /* USB Service */
 #define IRQ_PMU         PXA_IRQ(12)     /* Performance Monitoring Unit */
-#define IRQ_I2S         PXA_IRQ(13)     /* I2S Interrupt */
+#define IRQ_I2S         PXA_IRQ(13)     /* I2S Interrupt (PXA27x) */
+#define IRQ_SSP4        PXA_IRQ(13)     /* SSP4 service request (PXA3xx) */
 #define IRQ_AC97        PXA_IRQ(14)     /* AC97 Interrupt */
 #define IRQ_ASSP        PXA_IRQ(15)     /* Audio SSP Service Request (PXA25x) */
 #define IRQ_USIM        PXA_IRQ(15)     /* Smart Card interface interrupt (PXA27x) */
@@ -47,6 +46,7 @@
 #define IRQ_LCD         PXA_IRQ(17)     /* LCD Controller Service Request */
 #define IRQ_I2C         PXA_IRQ(18)     /* I2C Service Request */
 #define IRQ_ICP         PXA_IRQ(19)     /* ICP Transmit/Receive/Error */
+#define IRQ_ACIPC2      PXA_IRQ(19)     /* AP-CP Communication (PXA930) */
 #define IRQ_STUART      PXA_IRQ(20)     /* STUART Transmit/Receive/Error */
 #define IRQ_BTUART      PXA_IRQ(21)     /* BTUART Transmit/Receive/Error */
 #define IRQ_FFUART      PXA_IRQ(22)     /* FFUART Transmit/Receive/Error*/
@@ -60,19 +60,17 @@
 #define IRQ_RTC1Hz      PXA_IRQ(30)     /* RTC HZ Clock Tick */
 #define IRQ_RTCAlrm     PXA_IRQ(31)     /* RTC Alarm */
 
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define IRQ_TPM         PXA_IRQ(32)     /* TPM interrupt */
 #define IRQ_CAMERA      PXA_IRQ(33)     /* Camera Interface */
-#endif
-
-#ifdef CONFIG_PXA3xx
-#define IRQ_SSP4        PXA_IRQ(13)     /* SSP4 service request */
 #define IRQ_CIR         PXA_IRQ(34)     /* Consumer IR */
 #define IRQ_COMM_WDT    PXA_IRQ(35)     /* Comm WDT interrupt */
 #define IRQ_TSI         PXA_IRQ(36)     /* Touch Screen Interface (PXA320) */
+#define IRQ_ENHROT      PXA_IRQ(37)     /* Enhanced Rotary (PXA930) */
 #define IRQ_USIM2       PXA_IRQ(38)     /* USIM2 Controller */
-#define IRQ_GCU         PXA_IRQ(39)     /* Graphics Controller */
+#define IRQ_GCU         PXA_IRQ(39)     /* Graphics Controller (PXA3xx) */
+#define IRQ_ACIPC1      PXA_IRQ(40)     /* AP-CP Communication (PXA930) */
 #define IRQ_MMC2        PXA_IRQ(41)     /* MMC2 Controller */
+#define IRQ_TRKBALL     PXA_IRQ(43)     /* Track Ball (PXA930) */
 #define IRQ_1WIRE       PXA_IRQ(44)     /* 1-Wire Controller */
 #define IRQ_NAND        PXA_IRQ(45)     /* NAND Controller */
 #define IRQ_USB2        PXA_IRQ(46)     /* USB 2.0 Device Controller */
@@ -80,30 +78,14 @@
 #define IRQ_WAKEUP1     PXA_IRQ(50)     /* EXT_WAKEUP1 */
 #define IRQ_DMEMC       PXA_IRQ(51)     /* Dynamic Memory Controller */
 #define IRQ_MMC3        PXA_IRQ(55)     /* MMC3 Controller (PXA310) */
-#endif
 
-#ifdef CONFIG_CPU_PXA935
 #define IRQ_U2O         PXA_IRQ(64)     /* USB OTG 2.0 Controller (PXA935) */
 #define IRQ_U2H         PXA_IRQ(65)     /* USB Host 2.0 Controller (PXA935) */
-
-#define IRQ_MMC3_PXA935 PXA_IRQ(72)     /* MMC3 Controller (PXA935) */
-#define IRQ_MMC4_PXA935 PXA_IRQ(73)     /* MMC4 Controller (PXA935) */
-#define IRQ_MMC5_PXA935 PXA_IRQ(74)     /* MMC5 Controller (PXA935) */
-
+#define IRQ_PXA935_MMC0 PXA_IRQ(72)     /* MMC0 Controller (PXA935) */
+#define IRQ_PXA935_MMC1 PXA_IRQ(73)     /* MMC1 Controller (PXA935) */
+#define IRQ_PXA935_MMC2 PXA_IRQ(74)     /* MMC2 Controller (PXA935) */
+#define IRQ_PXA955_MMC3 PXA_IRQ(75)     /* MMC3 Controller (PXA955) */
 #define IRQ_U2P         PXA_IRQ(93)     /* USB PHY D+/D- Lines (PXA935) */
-#endif
-
-#ifdef CONFIG_CPU_PXA930
-#define IRQ_ENHROT      PXA_IRQ(37)     /* Enhanced Rotary (PXA930) */
-#define IRQ_ACIPC0      PXA_IRQ(5)
-#define IRQ_ACIPC1      PXA_IRQ(40)
-#define IRQ_ACIPC2      PXA_IRQ(19)
-#define IRQ_TRKBALL     PXA_IRQ(43)     /* Track Ball */
-#endif
-
-#ifdef CONFIG_CPU_PXA950
-#define IRQ_GC500       PXA_IRQ(70)     /* Graphics Controller (PXA950) */
-#endif
 
 #define PXA_GPIO_IRQ_BASE       PXA_IRQ(96)
 #define PXA_GPIO_IRQ_NUM        (192)
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 4fcddd9cab76..ee6ced1cea7f 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -17,72 +17,6 @@
 #include <mach/hardware.h>
 
 /*
- * PXA Chip selects
- */
-
-#define PXA_CS0_PHYS    0x00000000
-#define PXA_CS1_PHYS    0x04000000
-#define PXA_CS2_PHYS    0x08000000
-#define PXA_CS3_PHYS    0x0C000000
-#define PXA_CS4_PHYS    0x10000000
-#define PXA_CS5_PHYS    0x14000000
-
-/*
- * Memory controller
- */
-
-#define MDCNFG          __REG(0x48000000)  /* SDRAM Configuration Register 0 */
-#define MDREFR          __REG(0x48000004)  /* SDRAM Refresh Control Register */
-#define MSC0            __REG(0x48000008)  /* Static Memory Control Register 0 */
-#define MSC1            __REG(0x4800000C)  /* Static Memory Control Register 1 */
-#define MSC2            __REG(0x48000010)  /* Static Memory Control Register 2 */
-#define MECR            __REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR           __REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG          __REG(0x4800001C)  /* Synchronous Static Memory Control Register */
-#define SXMRS           __REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0          __REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1          __REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0          __REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1          __REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0           __REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1           __REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS           __REG(0x48000040)  /* MRS value to be written to SDRAM */
-#define BOOT_DEF        __REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
-
-/*
- * More handy macros for PCMCIA
- *
- * Arg is socket number
- */
-#define MCMEM(s)        __REG2(0x48000028, (s)<<2 )  /* Card interface Common Memory Space Socket s Timing */
-#define MCATT(s)        __REG2(0x48000030, (s)<<2 )  /* Card interface Attribute Space Socket s Timing Configuration */
-#define MCIO(s)         __REG2(0x48000038, (s)<<2 )  /* Card interface I/O Space Socket s Timing Configuration */
-
-/* MECR register defines */
-#define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
-#define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
-
-#define MDCNFG_DE0      (1 << 0)        /* SDRAM Bank 0 Enable */
-#define MDCNFG_DE1      (1 << 1)        /* SDRAM Bank 1 Enable */
-#define MDCNFG_DE2      (1 << 16)       /* SDRAM Bank 2 Enable */
-#define MDCNFG_DE3      (1 << 17)       /* SDRAM Bank 3 Enable */
-
-#define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
-#define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
-#define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
-#define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
-#define MDREFR_SLFRSH   (1 << 22)       /* SDRAM Self-Refresh Control/Status */
-#define MDREFR_APD      (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
-#define MDREFR_K2DB2    (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
-#define MDREFR_K2RUN    (1 << 18)       /* SDCLK2 Run Control/Status */
-#define MDREFR_K1DB2    (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
-#define MDREFR_K1RUN    (1 << 16)       /* SDCLK1 Run Control/Status */
-#define MDREFR_E1PIN    (1 << 15)       /* SDCKE1 Level Control/Status */
-#define MDREFR_K0DB2    (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
-#define MDREFR_K0RUN    (1 << 13)       /* SDCLK0 Run Control/Status */
-#define MDREFR_E0PIN    (1 << 12)       /* SDCKE0 Level Control/Status */
-
-/*
  * Power Manager
  */
 
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h b/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h
deleted file mode 100644
index b87cecd9bbdc..000000000000
--- a/arch/arm/mach-pxa/include/mach/pxa2xx_spi.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef PXA2XX_SPI_H_
-#define PXA2XX_SPI_H_
-
-#define PXA2XX_CS_ASSERT (0x01)
-#define PXA2XX_CS_DEASSERT (0x02)
-
-/* device.platform_data for SSP controller devices */
-struct pxa2xx_spi_master {
-        u32 clock_enable;
-        u16 num_chipselect;
-        u8 enable_dma;
-};
-
-/* spi_board_info.controller_data for SPI slave devices,
- * copied to spi_device.platform_data ... mostly for dma tuning
- */
-struct pxa2xx_spi_chip {
-        u8 tx_threshold;
-        u8 rx_threshold;
-        u8 dma_burst_size;
-        u32 timeout;
-        u8 enable_loopback;
-        int gpio_cs;
-        void (*cs_control)(u32 command);
-};
-
-extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
-
-#endif /*PXA2XX_SPI_H_*/
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index e91d63cfe811..e4fb4668c26e 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -16,15 +16,6 @@
 #include <mach/hardware.h>
 
 /*
- * Static Chip Selects
- */
-
-#define PXA300_CS0_PHYS         (0x00000000)    /* PXA300/PXA310 _only_ */
-#define PXA300_CS1_PHYS         (0x30000000)    /* PXA300/PXA310 _only_ */
-#define PXA3xx_CS2_PHYS         (0x10000000)
-#define PXA3xx_CS3_PHYS         (0x14000000)
-
-/*
  * Oscillator Configuration Register (OSCC)
  */
 #define OSCC           __REG(0x41350000)  /* Oscillator Configuration Register */
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
index 68464ce1c1ea..662288eb6f95 100644
--- a/arch/arm/mach-pxa/include/mach/regs-intc.h
+++ b/arch/arm/mach-pxa/include/mach/regs-intc.h
@@ -27,8 +27,4 @@
 #define ICFP3           __REG(0x40D0013C)  /* Interrupt Controller FIQ Pending Register 3 */
 #define ICPR3           __REG(0x40D00140)  /* Interrupt Controller Pending Register 3 */
 
-#define IPR(x)          __REG(0x40D0001C + (x < 32 ? (x << 2)           \
-                                : (x < 64 ? (0x94 + ((x - 32) << 2))    \
-                                : (0x128 + ((x - 64) << 2)))))
-
 #endif /* __ASM_MACH_REGS_INTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h
new file mode 100644
index 000000000000..654adc90c9a0
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/smemc.h
@@ -0,0 +1,74 @@
+/*
+ * Static memory controller register definitions for PXA CPUs
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SMEMC_REGS_H
+#define __SMEMC_REGS_H
+
+#define PXA2XX_SMEMC_BASE       0x48000000
+#define PXA3XX_SMEMC_BASE       0x4a000000
+#define SMEMC_VIRT              0xf6000000
+
+#define MDCNFG          (SMEMC_VIRT + 0x00)  /* SDRAM Configuration Register 0 */
+#define MDREFR          (SMEMC_VIRT + 0x04)  /* SDRAM Refresh Control Register */
+#define MSC0            (SMEMC_VIRT + 0x08)  /* Static Memory Control Register 0 */
+#define MSC1            (SMEMC_VIRT + 0x0C)  /* Static Memory Control Register 1 */
+#define MSC2            (SMEMC_VIRT + 0x10)  /* Static Memory Control Register 2 */
+#define MECR            (SMEMC_VIRT + 0x14)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR           (SMEMC_VIRT + 0x18)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG          (SMEMC_VIRT + 0x1C)  /* Synchronous Static Memory Control Register */
+#define SXMRS           (SMEMC_VIRT + 0x24)  /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0          (SMEMC_VIRT + 0x28)  /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1          (SMEMC_VIRT + 0x2C)  /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0          (SMEMC_VIRT + 0x30)  /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1          (SMEMC_VIRT + 0x34)  /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0           (SMEMC_VIRT + 0x38)  /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1           (SMEMC_VIRT + 0x3C)  /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS           (SMEMC_VIRT + 0x40)  /* MRS value to be written to SDRAM */
+#define BOOT_DEF        (SMEMC_VIRT + 0x44)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+#define MEMCLKCFG       (SMEMC_VIRT + 0x68)  /* Clock Configuration */
+#define CSADRCFG0       (SMEMC_VIRT + 0x80)  /* Address Configuration Register for CS0 */
+#define CSADRCFG1       (SMEMC_VIRT + 0x84)  /* Address Configuration Register for CS1 */
+#define CSADRCFG2       (SMEMC_VIRT + 0x88)  /* Address Configuration Register for CS2 */
+#define CSADRCFG3       (SMEMC_VIRT + 0x8C)  /* Address Configuration Register for CS3 */
+
+/*
+ * More handy macros for PCMCIA
+ *
+ * Arg is socket number
+ */
+#define MCMEM(s)        (SMEMC_VIRT + 0x28 + ((s)<<2))  /* Card interface Common Memory Space Socket s Timing */
+#define MCATT(s)        (SMEMC_VIRT + 0x30 + ((s)<<2))  /* Card interface Attribute Space Socket s Timing Configuration */
+#define MCIO(s)         (SMEMC_VIRT + 0x38 + ((s)<<2))  /* Card interface I/O Space Socket s Timing Configuration */
+
+/* MECR register defines */
+#define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
+#define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
+
+#define MDCNFG_DE0      (1 << 0)        /* SDRAM Bank 0 Enable */
+#define MDCNFG_DE1      (1 << 1)        /* SDRAM Bank 1 Enable */
+#define MDCNFG_DE2      (1 << 16)       /* SDRAM Bank 2 Enable */
+#define MDCNFG_DE3      (1 << 17)       /* SDRAM Bank 3 Enable */
+
+#define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
+#define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
+#define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
+#define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH   (1 << 22)       /* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD      (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2    (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN    (1 << 18)       /* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2    (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN    (1 << 16)       /* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN    (1 << 15)       /* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2    (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN    (1 << 13)       /* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN    (1 << 12)       /* SDCKE0 Level Control/Status */
+
+#endif
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 1beb40f692fc..54e91c9e71c8 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -16,20 +16,31 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
+#include <linux/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
+#include <mach/irqs.h>
 #include <mach/gpio.h>
-#include <mach/regs-intc.h>
 
 #include "generic.h"
 
-#define MAX_INTERNAL_IRQS       128
+#define IRQ_BASE                (void __iomem *)io_p2v(0x40d00000)
+
+#define ICIP                    (0x000)
+#define ICMR                    (0x004)
+#define ICLR                    (0x008)
+#define ICFR                    (0x00c)
+#define ICPR                    (0x010)
+#define ICCR                    (0x014)
+#define ICHP                    (0x018)
+#define IPR(i)                  (((i) < 32) ? (0x01c + ((i) << 2)) :            \
+                                ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) :      \
+                                      (0x144 + (((i) - 64) << 2)))
+#define IPR_VALID               (1 << 31)
+#define IRQ_BIT(n)              (((n) - PXA_IRQ(0)) & 0x1f)
 
-#define IRQ_BIT(n)      (((n) - PXA_IRQ(0)) & 0x1f)
-#define _ICMR(n)        (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
-#define _ICLR(n)        (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
+#define MAX_INTERNAL_IRQS       128
 
 /*
  * This is for peripheral IRQs internal to the PXA chip.
@@ -37,14 +48,27 @@
 
 static int pxa_internal_irq_nr;
 
+static inline int cpu_has_ipr(void)
+{
+        return !cpu_is_pxa25x();
+}
+
 static void pxa_mask_irq(unsigned int irq)
 {
-        _ICMR(irq) &= ~(1 << IRQ_BIT(irq));
+        void __iomem *base = get_irq_chip_data(irq);
+        uint32_t icmr = __raw_readl(base + ICMR);
+
+        icmr &= ~(1 << IRQ_BIT(irq));
+        __raw_writel(icmr, base + ICMR);
 }
 
 static void pxa_unmask_irq(unsigned int irq)
 {
-        _ICMR(irq) |= 1 << IRQ_BIT(irq);
+        void __iomem *base = get_irq_chip_data(irq);
+        uint32_t icmr = __raw_readl(base + ICMR);
+
+        icmr |= 1 << IRQ_BIT(irq);
+        __raw_writel(icmr, base + ICMR);
 }
 
 static struct irq_chip pxa_internal_irq_chip = {
@@ -86,12 +110,16 @@ static void pxa_ack_low_gpio(unsigned int irq)
 
 static void pxa_mask_low_gpio(unsigned int irq)
 {
-        ICMR &= ~(1 << (irq - PXA_IRQ(0)));
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        desc->chip->mask(irq);
 }
 
 static void pxa_unmask_low_gpio(unsigned int irq)
 {
-        ICMR |= 1 << (irq - PXA_IRQ(0));
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        desc->chip->unmask(irq);
 }
 
 static struct irq_chip pxa_low_gpio_chip = {
@@ -120,33 +148,45 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
         pxa_low_gpio_chip.set_wake = fn;
 }
 
+static inline void __iomem *irq_base(int i)
+{
+        static unsigned long phys_base[] = {
+                0x40d00000,
+                0x40d0009c,
+                0x40d00130,
+        };
+
+        return (void __iomem *)io_p2v(phys_base[i >> 5]);
+}
+
 void __init pxa_init_irq(int irq_nr, set_wake_t fn)
 {
-        int irq, i;
+        int irq, i, n;
 
         BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
 
         pxa_internal_irq_nr = irq_nr;
 
-        for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
-                _ICMR(irq) = 0; /* disable all IRQs */
-                _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
-        }
-
-        /* initialize interrupt priority */
-        if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
-                for (i = 0; i < irq_nr; i++)
-                        IPR(i) = i | (1 << 31);
+        for (n = 0; n < irq_nr; n += 32) {
+                void __iomem *base = irq_base(n);
+
+                __raw_writel(0, base + ICMR);   /* disable all IRQs */
+                __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
+                for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
+                        /* initialize interrupt priority */
+                        if (cpu_has_ipr())
+                                __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
+
+                        irq = PXA_IRQ(i);
+                        set_irq_chip(irq, &pxa_internal_irq_chip);
+                        set_irq_chip_data(irq, base);
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID);
+                }
         }
 
         /* only unmasked interrupts kick us out of idle */
-        ICCR = 1;
-
-        for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
-                set_irq_chip(irq, &pxa_internal_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
+        __raw_writel(1, irq_base(0) + ICCR);
 
         pxa_internal_irq_chip.set_wake = fn;
         pxa_init_low_gpio_irq(fn);
@@ -158,16 +198,18 @@ static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
 
 static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
 {
-        int i, irq = PXA_IRQ(0);
+        int i;
 
-        for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
-                saved_icmr[i] = _ICMR(irq);
-                _ICMR(irq) = 0;
+        for (i = 0; i < pxa_internal_irq_nr; i += 32) {
+                void __iomem *base = irq_base(i);
+
+                saved_icmr[i] = __raw_readl(base + ICMR);
+                __raw_writel(0, base + ICMR);
         }
 
-        if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
+        if (cpu_has_ipr()) {
                 for (i = 0; i < pxa_internal_irq_nr; i++)
-                        saved_ipr[i] = IPR(i);
+                        saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
         }
 
         return 0;
@@ -175,19 +217,20 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
 
 static int pxa_irq_resume(struct sys_device *dev)
 {
-        int i, irq = PXA_IRQ(0);
+        int i;
 
-        if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
-                for (i = 0; i < pxa_internal_irq_nr; i++)
-                        IPR(i) = saved_ipr[i];
-        }
+        for (i = 0; i < pxa_internal_irq_nr; i += 32) {
+                void __iomem *base = irq_base(i);
 
-        for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
-                _ICMR(irq) = saved_icmr[i];
-                _ICLR(irq) = 0;
+                __raw_writel(saved_icmr[i], base + ICMR);
+                __raw_writel(0, base + ICLR);
         }
 
-        ICCR = 1;
+        if (!cpu_is_pxa25x())
+                for (i = 0; i < pxa_internal_irq_nr; i++)
+                        __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
+
+        __raw_writel(1, IRQ_BASE + ICCR);
         return 0;
 }
 #else
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 41aa89e35772..ccb7bfad17ca 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -22,6 +22,7 @@
 #include <linux/clk.h>
 #include <linux/gpio.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/smc91x.h>
 #include <linux/i2c.h>
 #include <linux/leds.h>
@@ -42,7 +43,6 @@
 #include <mach/pxa300.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
-#include <mach/pxa2xx_spi.h>
 #include <plat/pxa27x_keypad.h>
 #include <mach/littleton.h>
 #include <plat/i2c.h>
@@ -438,7 +438,7 @@ static void __init littleton_init(void)
 
 MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .nr_irqs        = LITTLETON_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 623af0232a54..8ab62a677807 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -46,6 +46,7 @@
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -463,7 +464,7 @@ static void __init lpd270_init(void)
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
 
-        lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
+        lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
         lpd270_flash_data[1].width = 4;
 
         /*
@@ -495,7 +496,7 @@ static struct map_desc lpd270_io_desc[] __initdata = {
 
 static void __init lpd270_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
 
         /* for use I SRAM as framebuffer.  */
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 1499493cd070..3072dbea5c1f 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -25,7 +25,7 @@
 
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
-#include <mach/pxa2xx_spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 
 #include <asm/setup.h>
 #include <asm/memory.h>
@@ -50,6 +50,7 @@
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/pm.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -525,7 +526,7 @@ static void __init lubbock_init(void)
         pxa_set_ac97_info(NULL);
 
         lubbock_flash_data[0].width = lubbock_flash_data[1].width =
-                (BOOT_DEF & 1) ? 2 : 4;
+                (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
         /* Compensate for the nROMBT switch which swaps the flash banks */
         printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n",
                flashboot?"Flash":"ROM", flashboot);
@@ -549,7 +550,7 @@ static struct map_desc lubbock_io_desc[] __initdata = {
 
 static void __init lubbock_map_io(void)
 {
-        pxa_map_io();
+        pxa25x_map_io();
         iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
 
         PCFR |= PCFR_OPDE;
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 90663760307a..41198f0dc3ac 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -765,7 +765,7 @@ static void __init magician_init(void)
 
 MACHINE_START(MAGICIAN, "HTC Magician")
         .boot_params = 0xa0000100,
-        .map_io = pxa_map_io,
+        .map_io = pxa27x_map_io,
         .nr_irqs = MAGICIAN_NR_IRQS,
         .init_irq = pxa27x_init_irq,
         .init_machine = magician_init,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index a980a5c93e49..740c03590e3b 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -51,6 +51,7 @@
 #include <mach/irda.h>
 #include <mach/ohci.h>
 #include <plat/pxa27x_keypad.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -565,7 +566,7 @@ static void __init mainstone_init(void)
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
 
-        mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
+        mst_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
         mst_flash_data[1].width = 4;
 
         /* Compensate for SW7 which swaps the flash banks */
@@ -614,7 +615,7 @@ static struct map_desc mainstone_io_desc[] __initdata = {
 
 static void __init mainstone_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
 
         /*      for use I SRAM as framebuffer.  */
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f5fb915e1315..faafea3542fb 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -819,7 +819,7 @@ static void mioa701_machine_exit(void)
 
 MACHINE_START(MIOA701, "MIO A701")
         .boot_params    = 0xa0000100,
-        .map_io         = &pxa_map_io,
+        .map_io         = &pxa27x_map_io,
         .init_irq       = &pxa27x_init_irq,
         .init_machine   = mioa701_machine_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 116167aaba68..59cce78aebd1 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -94,7 +94,7 @@ static void __init mp900c_init(void)
 MACHINE_START(NEC_MP900, "MobilePro900/C")
         .boot_params    = 0xa0220100,
         .timer          = &pxa_timer,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = mp900c_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index ce092c521e6d..a6f898cbfac9 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -313,7 +313,7 @@ static struct map_desc palmld_io_desc[] __initdata = {
 
 static void __init palmld_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(palmld_io_desc, ARRAY_SIZE(palmld_io_desc));
 }
 
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 862da812cd10..df4d7d009fbb 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -203,7 +203,7 @@ static void __init palmt5_init(void)
 
 MACHINE_START(PALMT5, "Palm Tungsten|T5")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .reserve        = palmt5_reserve,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index 2131d5860919..a09a2374697b 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -25,6 +25,7 @@
 #include <linux/power_supply.h>
 #include <linux/gpio_keys.h>
 #include <linux/mtd/physmap.h>
+#include <linux/usb/gpio_vbus.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -116,6 +117,7 @@ static unsigned long palmtc_pin_config[] __initdata = {
 /******************************************************************************
  * SD/MMC card controller
  ******************************************************************************/
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
 static struct pxamci_platform_data palmtc_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .gpio_power             = GPIO_NR_PALMTC_SD_POWER,
@@ -124,9 +126,18 @@ static struct pxamci_platform_data palmtc_mci_platform_data = {
         .detect_delay_ms        = 200,
 };
 
+static void __init palmtc_mmc_init(void)
+{
+        pxa_set_mci_info(&palmtc_mci_platform_data);
+}
+#else
+static inline void palmtc_mmc_init(void) {}
+#endif
+
 /******************************************************************************
  * GPIO keys
  ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 static struct gpio_keys_button palmtc_pxa_buttons[] = {
         {KEY_F8, GPIO_NR_PALMTC_HOTSYNC_BUTTON, 1, "HotSync Button", EV_KEY, 1},
 };
@@ -144,9 +155,18 @@ static struct platform_device palmtc_pxa_keys = {
         },
 };
 
+static void __init palmtc_keys_init(void)
+{
+        platform_device_register(&palmtc_pxa_keys);
+}
+#else
+static inline void palmtc_keys_init(void) {}
+#endif
+
 /******************************************************************************
  * Backlight
  ******************************************************************************/
+#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
 static int palmtc_backlight_init(struct device *dev)
 {
         int ret;
@@ -196,17 +216,35 @@ static struct platform_device palmtc_backlight = {
         },
 };
 
+static void __init palmtc_pwm_init(void)
+{
+        platform_device_register(&palmtc_backlight);
+}
+#else
+static inline void palmtc_pwm_init(void) {}
+#endif
+
 /******************************************************************************
  * IrDA
  ******************************************************************************/
+#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE)
 static struct pxaficp_platform_data palmtc_ficp_platform_data = {
         .gpio_pwdown            = GPIO_NR_PALMTC_IR_DISABLE,
         .transceiver_cap        = IR_SIRMODE | IR_OFF,
 };
 
+static void __init palmtc_irda_init(void)
+{
+        pxa_set_ficp_info(&palmtc_ficp_platform_data);
+}
+#else
+static inline void palmtc_irda_init(void) {}
+#endif
+
 /******************************************************************************
  * Keyboard
  ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
 static const uint32_t palmtc_matrix_keys[] = {
         KEY(0, 0, KEY_F1),
         KEY(0, 1, KEY_X),
@@ -290,27 +328,103 @@ static struct platform_device palmtc_keyboard = {
                 .platform_data = &palmtc_keypad_platform_data,
         },
 };
+static void __init palmtc_mkp_init(void)
+{
+        platform_device_register(&palmtc_keyboard);
+}
+#else
+static inline void palmtc_mkp_init(void) {}
+#endif
 
 /******************************************************************************
  * UDC
  ******************************************************************************/
-static struct pxa2xx_udc_mach_info palmtc_udc_info __initdata = {
+#if defined(CONFIG_USB_GADGET_PXA25X)||defined(CONFIG_USB_GADGET_PXA25X_MODULE)
+static struct gpio_vbus_mach_info palmtc_udc_info = {
         .gpio_vbus              = GPIO_NR_PALMTC_USB_DETECT_N,
         .gpio_vbus_inverted     = 1,
         .gpio_pullup            = GPIO_NR_PALMTC_USB_POWER,
 };
 
+static struct platform_device palmtc_gpio_vbus = {
+        .name   = "gpio-vbus",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &palmtc_udc_info,
+        },
+};
+
+static void __init palmtc_udc_init(void)
+{
+        platform_device_register(&palmtc_gpio_vbus);
+};
+#else
+static inline void palmtc_udc_init(void) {}
+#endif
+
 /******************************************************************************
  * Touchscreen / Battery / GPIO-extender
  ******************************************************************************/
-static struct platform_device palmtc_ucb1400_core = {
+#if     defined(CONFIG_TOUCHSCREEN_UCB1400) || \
+        defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
+static struct platform_device palmtc_ucb1400_device = {
         .name   = "ucb1400_core",
         .id     = -1,
 };
 
+static void __init palmtc_ts_init(void)
+{
+        pxa_set_ac97_info(NULL);
+        platform_device_register(&palmtc_ucb1400_device);
+}
+#else
+static inline void palmtc_ts_init(void) {}
+#endif
+
+/******************************************************************************
+ * LEDs
+ ******************************************************************************/
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+struct gpio_led palmtc_gpio_leds[] = {
+{
+        .name                   = "palmtc:green:user",
+        .default_trigger        = "none",
+        .gpio                   = GPIO_NR_PALMTC_LED_POWER,
+        .active_low             = 1,
+}, {
+        .name                   = "palmtc:vibra:vibra",
+        .default_trigger        = "none",
+        .gpio                   = GPIO_NR_PALMTC_VIBRA_POWER,
+        .active_low             = 1,
+}
+
+};
+
+static struct gpio_led_platform_data palmtc_gpio_led_info = {
+        .leds           = palmtc_gpio_leds,
+        .num_leds       = ARRAY_SIZE(palmtc_gpio_leds),
+};
+
+static struct platform_device palmtc_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &palmtc_gpio_led_info,
+        }
+};
+
+static void __init palmtc_leds_init(void)
+{
+        platform_device_register(&palmtc_leds);
+}
+#else
+static inline void palmtc_leds_init(void) {}
+#endif
+
 /******************************************************************************
  * NOR Flash
  ******************************************************************************/
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
 static struct resource palmtc_flash_resource = {
         .start  = PXA_CS0_PHYS,
         .end    = PXA_CS0_PHYS + SZ_16M - 1,
@@ -356,24 +470,33 @@ static struct platform_device palmtc_flash = {
         },
 };
 
+static void __init palmtc_nor_init(void)
+{
+        platform_device_register(&palmtc_flash);
+}
+#else
+static inline void palmtc_nor_init(void) {}
+#endif
+
 /******************************************************************************
  * Framebuffer
  ******************************************************************************/
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
 static struct pxafb_mode_info palmtc_lcd_modes[] = {
-{
-        .pixclock       = 115384,
-        .xres           = 320,
-        .yres           = 320,
-        .bpp            = 16,
-
-        .left_margin    = 27,
-        .right_margin   = 7,
-        .upper_margin   = 7,
-        .lower_margin   = 8,
-
-        .hsync_len      = 6,
-        .vsync_len      = 1,
-},
+        {
+                .pixclock       = 115384,
+                .xres           = 320,
+                .yres           = 320,
+                .bpp            = 16,
+
+                .left_margin    = 27,
+                .right_margin   = 7,
+                .upper_margin   = 7,
+                .lower_margin   = 8,
+
+                .hsync_len      = 6,
+                .vsync_len      = 1,
+        },
 };
 
 static struct pxafb_mach_info palmtc_lcd_screen = {
@@ -382,17 +505,17 @@ static struct pxafb_mach_info palmtc_lcd_screen = {
         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
 };
 
+static void __init palmtc_lcd_init(void)
+{
+        set_pxa_fb_info(&palmtc_lcd_screen);
+}
+#else
+static inline void palmtc_lcd_init(void) {}
+#endif
+
 /******************************************************************************
  * Machine init
  ******************************************************************************/
-static struct platform_device *devices[] __initdata = {
-        &palmtc_backlight,
-        &palmtc_ucb1400_core,
-        &palmtc_keyboard,
-        &palmtc_pxa_keys,
-        &palmtc_flash,
-};
-
 static void __init palmtc_init(void)
 {
         pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtc_pin_config));
@@ -402,18 +525,21 @@ static void __init palmtc_init(void)
         pxa_set_stuart_info(NULL);
         pxa_set_hwuart_info(NULL);
 
-        set_pxa_fb_info(&palmtc_lcd_screen);
-        pxa_set_mci_info(&palmtc_mci_platform_data);
-        pxa_set_udc_info(&palmtc_udc_info);
-        pxa_set_ac97_info(NULL);
-        pxa_set_ficp_info(&palmtc_ficp_platform_data);
-
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        palmtc_mmc_init();
+        palmtc_keys_init();
+        palmtc_pwm_init();
+        palmtc_irda_init();
+        palmtc_mkp_init();
+        palmtc_udc_init();
+        palmtc_ts_init();
+        palmtc_nor_init();
+        palmtc_lcd_init();
+        palmtc_leds_init();
 };
 
 MACHINE_START(PALMTC, "Palm Tungsten|C")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmtc_init
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index a9dae7bc35d9..3f25014a136c 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -374,7 +374,7 @@ static void __init palmte2_init(void)
 
 MACHINE_START(PALMTE2, "Palm Tungsten|E2")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmte2_init
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 00e2d7ba84ed..8aadad55fbe4 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -442,7 +442,7 @@ static void __init centro_init(void)
 
 MACHINE_START(TREO680, "Palm Treo 680")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .reserve        = treo_reserve,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -451,7 +451,7 @@ MACHINE_END
 
 MACHINE_START(CENTRO, "Palm Centro 685")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .reserve        = treo_reserve,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index e5c9932b7588..595f002066cc 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -334,7 +334,7 @@ static struct map_desc palmtx_io_desc[] __initdata = {
 
 static void __init palmtx_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(palmtx_io_desc, ARRAY_SIZE(palmtx_io_desc));
 }
 
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index af6203fbca9c..7bf4017326e3 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -280,7 +280,7 @@ static void __init palmz72_init(void)
 
 MACHINE_START(PALMZ72, "Palm Zire72")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmz72_init
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index c77e8f30a439..1fc8a66407ae 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -25,12 +25,12 @@
 #include <linux/mtd/physmap.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/max7301.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/leds.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/pxa27x.h>
-#include <mach/pxa2xx_spi.h>
 #include <mach/pcm027.h>
 #include "generic.h"
 
@@ -244,7 +244,7 @@ static void __init pcm027_init(void)
 
 static void __init pcm027_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
 
         /* initialize sleep mode regs (wake-up sources, etc) */
         PGSR0 = 0x01308000;
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 93a191c889df..4f0ff1ab623d 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -25,6 +25,7 @@
 #include <linux/i2c.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/mtd/sharpsl.h>
 
 #include <mach/hardware.h>
@@ -43,7 +44,6 @@
 #include <mach/irda.h>
 #include <mach/poodle.h>
 #include <mach/pxafb.h>
-#include <mach/pxa2xx_spi.h>
 #include <plat/i2c.h>
 
 #include <asm/hardware/scoop.h>
@@ -466,7 +466,7 @@ static void __init fixup_poodle(struct machine_desc *desc,
 
 MACHINE_START(POODLE, "SHARP Poodle")
         .fixup          = fixup_poodle,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = POODLE_NR_IRQS,       /* 4 for LoCoMo */
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index de53f2e4aa39..3f5241c84894 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -23,6 +23,7 @@
 #include <linux/suspend.h>
 #include <linux/sysdev.h>
 
+#include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/gpio.h>
@@ -30,6 +31,7 @@
 #include <mach/reset.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -90,23 +92,21 @@ unsigned int pxa25x_get_clk_frequency_khz(int info)
         return (turbo & 1) ? (N/1000) : (M/1000);
 }
 
-/*
- * Return the current memory clock frequency in units of 10kHz
- */
-unsigned int pxa25x_get_memclk_frequency_10khz(void)
+static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
 {
-        return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
+        return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
 }
 
-static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
-{
-        return pxa25x_get_memclk_frequency_10khz() * 10000;
-}
+static const struct clkops clk_pxa25x_mem_ops = {
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable,
+        .getrate        = clk_pxa25x_mem_getrate,
+};
 
 static const struct clkops clk_pxa25x_lcd_ops = {
-        .enable         = clk_cken_enable,
-        .disable        = clk_cken_disable,
-        .getrate        = clk_pxa25x_lcd_getrate,
+        .enable         = clk_pxa2xx_cken_enable,
+        .disable        = clk_pxa2xx_cken_disable,
+        .getrate        = clk_pxa25x_mem_getrate,
 };
 
 static unsigned long gpio12_config_32k[] = {
@@ -160,31 +160,30 @@ static const struct clkops clk_pxa25x_gpio11_ops = {
  * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
  * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
  */
-static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
-
-static struct clk_lookup pxa25x_hwuart_clkreg =
-        INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
 
 /*
  * PXA 2xx clock declarations.
  */
+static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
+static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
+static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
+static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
+static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
+static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
+static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
+static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
+static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
+static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
+static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
+static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
+static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
+static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
+static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
+
 static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
-static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
-static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
-static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1);
-static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5);
 static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
 static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
-static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0);
-static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0);
-static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0);
-static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
-static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0);
-static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
-static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
-static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0);
-static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0);
-static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0);
+static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
 
 static struct clk_lookup pxa25x_clkregs[] = {
         INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
@@ -205,8 +204,12 @@ static struct clk_lookup pxa25x_clkregs[] = {
         INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
         INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
         INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
+        INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
 };
 
+static struct clk_lookup pxa25x_hwuart_clkreg =
+        INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
+
 #ifdef CONFIG_PM
 
 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
@@ -219,20 +222,17 @@ static struct clk_lookup pxa25x_clkregs[] = {
  */
 enum {
         SLEEP_SAVE_PSTR,
-        SLEEP_SAVE_CKEN,
         SLEEP_SAVE_COUNT
 };
 
 
 static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
 {
-        SAVE(CKEN);
         SAVE(PSTR);
 }
 
 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
 {
-        RESTORE(CKEN);
         RESTORE(PSTR);
 }
 
@@ -320,6 +320,22 @@ void __init pxa26x_init_irq(void)
 }
 #endif
 
+static struct map_desc pxa25x_io_desc[] __initdata = {
+        {       /* Mem Ctl */
+                .virtual        = SMEMC_VIRT,
+                .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
+                .length         = 0x00200000,
+                .type           = MT_DEVICE
+        },
+};
+
+void __init pxa25x_map_io(void)
+{
+        pxa_map_io();
+        iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
+        pxa25x_get_clk_frequency_khz(1);
+}
+
 static struct platform_device *pxa25x_devices[] __initdata = {
         &pxa25x_device_udc,
         &pxa_device_pmu,
@@ -339,7 +355,9 @@ static struct sys_device pxa25x_sysdev[] = {
                 .cls    = &pxa2xx_mfp_sysclass,
         }, {
                 .cls    = &pxa_gpio_sysclass,
-        },
+        }, {
+                .cls    = &pxa2xx_clock_sysclass,
+        }
 };
 
 static int __init pxa25x_init(void)
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index d1fbf29d561c..b2130b7a7b52 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -17,7 +17,9 @@
 #include <linux/suspend.h>
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
+#include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <mach/irqs.h>
@@ -27,6 +29,8 @@
 #include <mach/ohci.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
+#include <mach/smemc.h>
+
 #include <plat/i2c.h>
 
 #include "generic.h"
@@ -107,10 +111,9 @@ unsigned int pxa27x_get_clk_frequency_khz(int info)
 }
 
 /*
- * Return the current mem clock frequency in units of 10kHz as
- * reflected by CCCR[A], B, and L
+ * Return the current mem clock frequency as reflected by CCCR[A], B, and L
  */
-unsigned int pxa27x_get_memclk_frequency_10khz(void)
+static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
 {
         unsigned long ccsr, clkcfg;
         unsigned int l, L, m, M;
@@ -129,9 +132,15 @@ unsigned int pxa27x_get_memclk_frequency_10khz(void)
         L = l * BASE_CLK;
         M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
 
-        return (M / 10000);
+        return M;
 }
 
+static const struct clkops clk_pxa27x_mem_ops = {
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable,
+        .getrate        = clk_pxa27x_mem_getrate,
+};
+
 /*
  * Return the current LCD clock frequency in units of 10kHz as
  */
@@ -157,36 +166,38 @@ static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
 }
 
 static const struct clkops clk_pxa27x_lcd_ops = {
-        .enable         = clk_cken_enable,
-        .disable        = clk_cken_disable,
+        .enable         = clk_pxa2xx_cken_enable,
+        .disable        = clk_pxa2xx_cken_disable,
         .getrate        = clk_pxa27x_lcd_getrate,
 };
 
+static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
+static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
+static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
+static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
+static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
+static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
+
 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
-static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
-static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
-static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
-static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
-static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
-static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
-static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
-static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
-static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
-static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
-static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
-static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
-static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
-static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
-static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
-static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
-static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
-static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
-static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
-static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
-static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
-static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
-static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
+static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
 
 static struct clk_lookup pxa27x_clkregs[] = {
         INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
@@ -215,6 +226,7 @@ static struct clk_lookup pxa27x_clkregs[] = {
         INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
         INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
         INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
+        INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
 };
 
 #ifdef CONFIG_PM
@@ -246,7 +258,6 @@ int __init pxa27x_set_pwrmode(unsigned int mode)
  */
 enum {
         SLEEP_SAVE_PSTR,
-        SLEEP_SAVE_CKEN,
         SLEEP_SAVE_MDREFR,
         SLEEP_SAVE_PCFR,
         SLEEP_SAVE_COUNT
@@ -254,21 +265,19 @@ enum {
 
 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 {
-        SAVE(MDREFR);
+        sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
         SAVE(PCFR);
 
-        SAVE(CKEN);
         SAVE(PSTR);
 }
 
 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 {
-        RESTORE(MDREFR);
+        __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
         RESTORE(PCFR);
 
         PSSR = PSSR_RDH | PSSR_PH;
 
-        RESTORE(CKEN);
         RESTORE(PSTR);
 }
 
@@ -370,6 +379,27 @@ void __init pxa27x_init_irq(void)
         pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
 }
 
+static struct map_desc pxa27x_io_desc[] __initdata = {
+        {       /* Mem Ctl */
+                .virtual        = SMEMC_VIRT,
+                .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
+                .length         = 0x00200000,
+                .type           = MT_DEVICE
+        }, {    /* IMem ctl */
+                .virtual        =  0xfe000000,
+                .pfn            = __phys_to_pfn(0x58000000),
+                .length         = 0x00100000,
+                .type           = MT_DEVICE
+        },
+};
+
+void __init pxa27x_map_io(void)
+{
+        pxa_map_io();
+        iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
+        pxa27x_get_clk_frequency_khz(1);
+}
+
 /*
  * device registration specific to PXA27x.
  */
@@ -405,7 +435,9 @@ static struct sys_device pxa27x_sysdev[] = {
                 .cls    = &pxa2xx_mfp_sysclass,
         }, {
                 .cls    = &pxa_gpio_sysclass,
-        },
+        }, {
+                .cls    = &pxa2xx_clock_sysclass,
+        }
 };
 
 static int __init pxa27x_init(void)
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index d1c747cdacf8..e14818f5d950 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/sysdev.h>
 
+#include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 #include <mach/pxa3xx-regs.h>
@@ -30,193 +31,16 @@
 #include <mach/pm.h>
 #include <mach/dma.h>
 #include <mach/regs-intc.h>
+#include <mach/smemc.h>
 #include <plat/i2c.h>
 
 #include "generic.h"
 #include "devices.h"
 #include "clock.h"
 
-/* Crystal clock: 13MHz */
-#define BASE_CLK        13000000
-
-/* Ring Oscillator Clock: 60MHz */
-#define RO_CLK          60000000
-
-#define ACCR_D0CS       (1 << 26)
-#define ACCR_PCCE       (1 << 11)
-
 #define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
 #define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
 
-/* crystal frequency to static memory controller multiplier (SMCFS) */
-static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
-
-/* crystal frequency to HSIO bus frequency multiplier (HSS) */
-static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
-
-/*
- * Get the clock frequency as reflected by CCSR and the turbo flag.
- * We assume these values have been applied via a fcs.
- * If info is not 0 we also display the current settings.
- */
-unsigned int pxa3xx_get_clk_frequency_khz(int info)
-{
-        unsigned long acsr, xclkcfg;
-        unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
-
-        /* Read XCLKCFG register turbo bit */
-        __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
-        t = xclkcfg & 0x1;
-
-        acsr = ACSR;
-
-        xl  = acsr & 0x1f;
-        xn  = (acsr >> 8) & 0x7;
-        hss = (acsr >> 14) & 0x3;
-
-        XL = xl * BASE_CLK;
-        XN = xn * XL;
-
-        ro = acsr & ACCR_D0CS;
-
-        CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
-        HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
-
-        if (info) {
-                pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
-                        RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
-                        (ro) ? "" : "in");
-                pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
-                        XL / 1000000, (XL % 1000000) / 10000, xl);
-                pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
-                        XN / 1000000, (XN % 1000000) / 10000, xn,
-                        (t) ? "" : "in");
-                pr_info("HSIO bus clock: %d.%02dMHz\n",
-                        HSS / 1000000, (HSS % 1000000) / 10000);
-        }
-
-        return CLK / 1000;
-}
-
-void pxa3xx_clear_reset_status(unsigned int mask)
-{
-        /* RESET_STATUS_* has a 1:1 mapping with ARSR */
-        ARSR = mask;
-}
-
-/*
- * Return the current AC97 clock frequency.
- */
-static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
-{
-        unsigned long rate = 312000000;
-        unsigned long ac97_div;
-
-        ac97_div = AC97_DIV;
-
-        /* This may loose precision for some rates but won't for the
-         * standard 24.576MHz.
-         */
-        rate /= (ac97_div >> 12) & 0x7fff;
-        rate *= (ac97_div & 0xfff);
-
-        return rate;
-}
-
-/*
- * Return the current HSIO bus clock frequency
- */
-static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
-{
-        unsigned long acsr;
-        unsigned int hss, hsio_clk;
-
-        acsr = ACSR;
-
-        hss = (acsr >> 14) & 0x3;
-        hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
-
-        return hsio_clk;
-}
-
-void clk_pxa3xx_cken_enable(struct clk *clk)
-{
-        unsigned long mask = 1ul << (clk->cken & 0x1f);
-
-        if (clk->cken < 32)
-                CKENA |= mask;
-        else
-                CKENB |= mask;
-}
-
-void clk_pxa3xx_cken_disable(struct clk *clk)
-{
-        unsigned long mask = 1ul << (clk->cken & 0x1f);
-
-        if (clk->cken < 32)
-                CKENA &= ~mask;
-        else
-                CKENB &= ~mask;
-}
-
-const struct clkops clk_pxa3xx_cken_ops = {
-        .enable         = clk_pxa3xx_cken_enable,
-        .disable        = clk_pxa3xx_cken_disable,
-};
-
-static const struct clkops clk_pxa3xx_hsio_ops = {
-        .enable         = clk_pxa3xx_cken_enable,
-        .disable        = clk_pxa3xx_cken_disable,
-        .getrate        = clk_pxa3xx_hsio_getrate,
-};
-
-static const struct clkops clk_pxa3xx_ac97_ops = {
-        .enable         = clk_pxa3xx_cken_enable,
-        .disable        = clk_pxa3xx_cken_disable,
-        .getrate        = clk_pxa3xx_ac97_getrate,
-};
-
-static void clk_pout_enable(struct clk *clk)
-{
-        OSCC |= OSCC_PEN;
-}
-
-static void clk_pout_disable(struct clk *clk)
-{
-        OSCC &= ~OSCC_PEN;
-}
-
-static const struct clkops clk_pout_ops = {
-        .enable         = clk_pout_enable,
-        .disable        = clk_pout_disable,
-};
-
-static void clk_dummy_enable(struct clk *clk)
-{
-}
-
-static void clk_dummy_disable(struct clk *clk)
-{
-}
-
-static const struct clkops clk_dummy_ops = {
-        .enable         = clk_dummy_enable,
-        .disable        = clk_dummy_disable,
-};
-
-static struct clk clk_pxa3xx_pout = {
-        .ops            = &clk_pout_ops,
-        .rate           = 13000000,
-        .delay          = 70,
-};
-
-static struct clk clk_dummy = {
-        .ops            = &clk_dummy_ops,
-};
-
-static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
-static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
-static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
@@ -234,6 +58,12 @@ static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
 
+static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
+static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
+static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
+static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
+static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
+
 static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
         /* Power I2C clock is always on */
@@ -258,6 +88,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
+        INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
 };
 
 #ifdef CONFIG_PM
@@ -268,30 +99,6 @@ static struct clk_lookup pxa3xx_clkregs[] = {
 static void __iomem *sram;
 static unsigned long wakeup_src;
 
-#define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
-#define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
-
-enum {  SLEEP_SAVE_CKENA,
-        SLEEP_SAVE_CKENB,
-        SLEEP_SAVE_ACCR,
-
-        SLEEP_SAVE_COUNT,
-};
-
-static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
-{
-        SAVE(CKENA);
-        SAVE(CKENB);
-        SAVE(ACCR);
-}
-
-static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
-{
-        RESTORE(ACCR);
-        RESTORE(CKENA);
-        RESTORE(CKENB);
-}
-
 /*
  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
  * memory controller has to be reinitialised, so we place some code
@@ -390,9 +197,6 @@ static int pxa3xx_cpu_pm_valid(suspend_state_t state)
 }
 
 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
-        .save_count     = SLEEP_SAVE_COUNT,
-        .save           = pxa3xx_cpu_pm_save,
-        .restore        = pxa3xx_cpu_pm_restore,
         .valid          = pxa3xx_cpu_pm_valid,
         .enter          = pxa3xx_cpu_pm_enter,
 };
@@ -580,6 +384,22 @@ void __init pxa3xx_init_irq(void)
         pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
 }
 
+static struct map_desc pxa3xx_io_desc[] __initdata = {
+        {       /* Mem Ctl */
+                .virtual        = SMEMC_VIRT,
+                .pfn            = __phys_to_pfn(PXA3XX_SMEMC_BASE),
+                .length         = 0x00200000,
+                .type           = MT_DEVICE
+        }
+};
+
+void __init pxa3xx_map_io(void)
+{
+        pxa_map_io();
+        iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
+        pxa3xx_get_clk_frequency_khz(1);
+}
+
 /*
  * device registration specific to PXA3xx.
  */
@@ -615,7 +435,9 @@ static struct sys_device pxa3xx_sysdev[] = {
                 .cls    = &pxa3xx_mfp_sysclass,
         }, {
                 .cls    = &pxa_gpio_sysclass,
-        },
+        }, {
+                .cls    = &pxa3xx_clock_sysclass,
+        }
 };
 
 static int __init pxa3xx_init(void)
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 7d29dd3af79d..8aeacf908784 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -192,7 +192,7 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
 
 static int __init pxa930_init(void)
 {
-        if (cpu_is_pxa930() || cpu_is_pxa935() || cpu_is_pxa950()) {
+        if (cpu_is_pxa93x()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa930_mfp_addr_map);
         }
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
new file mode 100644
index 000000000000..437980f72710
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -0,0 +1,308 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa95x.c
+ *
+ * code specific to PXA95x aka MGx
+ *
+ * Copyright (C) 2009-2010 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/pxa930.h>
+#include <mach/reset.h>
+#include <mach/pm.h>
+#include <mach/dma.h>
+#include <mach/regs-intc.h>
+#include <plat/i2c.h>
+
+#include "generic.h"
+#include "devices.h"
+#include "clock.h"
+
+static struct mfp_addr_map pxa95x_mfp_addr_map[] __initdata = {
+
+        MFP_ADDR(GPIO0, 0x02e0),
+        MFP_ADDR(GPIO1, 0x02dc),
+        MFP_ADDR(GPIO2, 0x02e8),
+        MFP_ADDR(GPIO3, 0x02d8),
+        MFP_ADDR(GPIO4, 0x02e4),
+        MFP_ADDR(GPIO5, 0x02ec),
+        MFP_ADDR(GPIO6, 0x02f8),
+        MFP_ADDR(GPIO7, 0x02fc),
+        MFP_ADDR(GPIO8, 0x0300),
+        MFP_ADDR(GPIO9, 0x02d4),
+        MFP_ADDR(GPIO10, 0x02f4),
+        MFP_ADDR(GPIO11, 0x02f0),
+        MFP_ADDR(GPIO12, 0x0304),
+        MFP_ADDR(GPIO13, 0x0310),
+        MFP_ADDR(GPIO14, 0x0308),
+        MFP_ADDR(GPIO15, 0x030c),
+        MFP_ADDR(GPIO16, 0x04e8),
+        MFP_ADDR(GPIO17, 0x04f4),
+        MFP_ADDR(GPIO18, 0x04f8),
+        MFP_ADDR(GPIO19, 0x04fc),
+        MFP_ADDR(GPIO20, 0x0518),
+        MFP_ADDR(GPIO21, 0x051c),
+        MFP_ADDR(GPIO22, 0x04ec),
+        MFP_ADDR(GPIO23, 0x0500),
+        MFP_ADDR(GPIO24, 0x04f0),
+        MFP_ADDR(GPIO25, 0x0504),
+        MFP_ADDR(GPIO26, 0x0510),
+        MFP_ADDR(GPIO27, 0x0514),
+        MFP_ADDR(GPIO28, 0x0520),
+        MFP_ADDR(GPIO29, 0x0600),
+        MFP_ADDR(GPIO30, 0x0618),
+        MFP_ADDR(GPIO31, 0x0610),
+        MFP_ADDR(GPIO32, 0x060c),
+        MFP_ADDR(GPIO33, 0x061c),
+        MFP_ADDR(GPIO34, 0x0620),
+        MFP_ADDR(GPIO35, 0x0628),
+        MFP_ADDR(GPIO36, 0x062c),
+        MFP_ADDR(GPIO37, 0x0630),
+        MFP_ADDR(GPIO38, 0x0634),
+        MFP_ADDR(GPIO39, 0x0638),
+        MFP_ADDR(GPIO40, 0x063c),
+        MFP_ADDR(GPIO41, 0x0614),
+        MFP_ADDR(GPIO42, 0x0624),
+        MFP_ADDR(GPIO43, 0x0608),
+        MFP_ADDR(GPIO44, 0x0604),
+        MFP_ADDR(GPIO45, 0x050c),
+        MFP_ADDR(GPIO46, 0x0508),
+        MFP_ADDR(GPIO47, 0x02bc),
+        MFP_ADDR(GPIO48, 0x02b4),
+        MFP_ADDR(GPIO49, 0x02b8),
+        MFP_ADDR(GPIO50, 0x02c8),
+        MFP_ADDR(GPIO51, 0x02c0),
+        MFP_ADDR(GPIO52, 0x02c4),
+        MFP_ADDR(GPIO53, 0x02d0),
+        MFP_ADDR(GPIO54, 0x02cc),
+        MFP_ADDR(GPIO55, 0x029c),
+        MFP_ADDR(GPIO56, 0x02a0),
+        MFP_ADDR(GPIO57, 0x0294),
+        MFP_ADDR(GPIO58, 0x0298),
+        MFP_ADDR(GPIO59, 0x02a4),
+        MFP_ADDR(GPIO60, 0x02a8),
+        MFP_ADDR(GPIO61, 0x02b0),
+        MFP_ADDR(GPIO62, 0x02ac),
+        MFP_ADDR(GPIO63, 0x0640),
+        MFP_ADDR(GPIO64, 0x065c),
+        MFP_ADDR(GPIO65, 0x0648),
+        MFP_ADDR(GPIO66, 0x0644),
+        MFP_ADDR(GPIO67, 0x0674),
+        MFP_ADDR(GPIO68, 0x0658),
+        MFP_ADDR(GPIO69, 0x0654),
+        MFP_ADDR(GPIO70, 0x0660),
+        MFP_ADDR(GPIO71, 0x0668),
+        MFP_ADDR(GPIO72, 0x0664),
+        MFP_ADDR(GPIO73, 0x0650),
+        MFP_ADDR(GPIO74, 0x066c),
+        MFP_ADDR(GPIO75, 0x064c),
+        MFP_ADDR(GPIO76, 0x0670),
+        MFP_ADDR(GPIO77, 0x0678),
+        MFP_ADDR(GPIO78, 0x067c),
+        MFP_ADDR(GPIO79, 0x0694),
+        MFP_ADDR(GPIO80, 0x069c),
+        MFP_ADDR(GPIO81, 0x06a0),
+        MFP_ADDR(GPIO82, 0x06a4),
+        MFP_ADDR(GPIO83, 0x0698),
+        MFP_ADDR(GPIO84, 0x06bc),
+        MFP_ADDR(GPIO85, 0x06b4),
+        MFP_ADDR(GPIO86, 0x06b0),
+        MFP_ADDR(GPIO87, 0x06c0),
+        MFP_ADDR(GPIO88, 0x06c4),
+        MFP_ADDR(GPIO89, 0x06ac),
+        MFP_ADDR(GPIO90, 0x0680),
+        MFP_ADDR(GPIO91, 0x0684),
+        MFP_ADDR(GPIO92, 0x0688),
+        MFP_ADDR(GPIO93, 0x0690),
+        MFP_ADDR(GPIO94, 0x068c),
+        MFP_ADDR(GPIO95, 0x06a8),
+        MFP_ADDR(GPIO96, 0x06b8),
+        MFP_ADDR(GPIO97, 0x0410),
+        MFP_ADDR(GPIO98, 0x0418),
+        MFP_ADDR(GPIO99, 0x041c),
+        MFP_ADDR(GPIO100, 0x0414),
+        MFP_ADDR(GPIO101, 0x0408),
+        MFP_ADDR(GPIO102, 0x0324),
+        MFP_ADDR(GPIO103, 0x040c),
+        MFP_ADDR(GPIO104, 0x0400),
+        MFP_ADDR(GPIO105, 0x0328),
+        MFP_ADDR(GPIO106, 0x0404),
+
+        MFP_ADDR(GPIO159, 0x0524),
+        MFP_ADDR(GPIO163, 0x0534),
+        MFP_ADDR(GPIO167, 0x0544),
+        MFP_ADDR(GPIO168, 0x0548),
+        MFP_ADDR(GPIO169, 0x054c),
+        MFP_ADDR(GPIO170, 0x0550),
+        MFP_ADDR(GPIO171, 0x0554),
+        MFP_ADDR(GPIO172, 0x0558),
+        MFP_ADDR(GPIO173, 0x055c),
+
+        MFP_ADDR(nXCVREN, 0x0204),
+        MFP_ADDR(DF_CLE_nOE, 0x020c),
+        MFP_ADDR(DF_nADV1_ALE, 0x0218),
+        MFP_ADDR(DF_SCLK_E, 0x0214),
+        MFP_ADDR(DF_SCLK_S, 0x0210),
+        MFP_ADDR(nBE0, 0x021c),
+        MFP_ADDR(nBE1, 0x0220),
+        MFP_ADDR(DF_nADV2_ALE, 0x0224),
+        MFP_ADDR(DF_INT_RnB, 0x0228),
+        MFP_ADDR(DF_nCS0, 0x022c),
+        MFP_ADDR(DF_nCS1, 0x0230),
+        MFP_ADDR(nLUA, 0x0254),
+        MFP_ADDR(nLLA, 0x0258),
+        MFP_ADDR(DF_nWE, 0x0234),
+        MFP_ADDR(DF_nRE_nOE, 0x0238),
+        MFP_ADDR(DF_ADDR0, 0x024c),
+        MFP_ADDR(DF_ADDR1, 0x0250),
+        MFP_ADDR(DF_ADDR2, 0x025c),
+        MFP_ADDR(DF_ADDR3, 0x0260),
+        MFP_ADDR(DF_IO0, 0x023c),
+        MFP_ADDR(DF_IO1, 0x0240),
+        MFP_ADDR(DF_IO2, 0x0244),
+        MFP_ADDR(DF_IO3, 0x0248),
+        MFP_ADDR(DF_IO4, 0x0264),
+        MFP_ADDR(DF_IO5, 0x0268),
+        MFP_ADDR(DF_IO6, 0x026c),
+        MFP_ADDR(DF_IO7, 0x0270),
+        MFP_ADDR(DF_IO8, 0x0274),
+        MFP_ADDR(DF_IO9, 0x0278),
+        MFP_ADDR(DF_IO10, 0x027c),
+        MFP_ADDR(DF_IO11, 0x0280),
+        MFP_ADDR(DF_IO12, 0x0284),
+        MFP_ADDR(DF_IO13, 0x0288),
+        MFP_ADDR(DF_IO14, 0x028c),
+        MFP_ADDR(DF_IO15, 0x0290),
+
+        MFP_ADDR(GSIM_UIO, 0x0314),
+        MFP_ADDR(GSIM_UCLK, 0x0318),
+        MFP_ADDR(GSIM_UDET, 0x031c),
+        MFP_ADDR(GSIM_nURST, 0x0320),
+
+        MFP_ADDR(PMIC_INT, 0x06c8),
+
+        MFP_ADDR(RDY, 0x0200),
+
+        MFP_ADDR_END,
+};
+
+static DEFINE_CK(pxa95x_lcd, LCD, &clk_pxa3xx_hsio_ops);
+static DEFINE_CLK(pxa95x_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
+static DEFINE_PXA3_CKEN(pxa95x_ffuart, FFUART, 14857000, 1);
+static DEFINE_PXA3_CKEN(pxa95x_btuart, BTUART, 14857000, 1);
+static DEFINE_PXA3_CKEN(pxa95x_stuart, STUART, 14857000, 1);
+static DEFINE_PXA3_CKEN(pxa95x_i2c, I2C, 32842000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_keypad, KEYPAD, 32768, 0);
+static DEFINE_PXA3_CKEN(pxa95x_ssp1, SSP1, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_ssp2, SSP2, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0);
+
+static struct clk_lookup pxa95x_clkregs[] = {
+        INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
+        /* Power I2C clock is always on */
+        INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
+        INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
+        INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-uart.2", NULL),
+        INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-ir", "UARTCLK"),
+        INIT_CLKREG(&clk_pxa95x_i2c, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_pxa95x_keypad, "pxa27x-keypad", NULL),
+        INIT_CLKREG(&clk_pxa95x_ssp1, "pxa27x-ssp.0", NULL),
+        INIT_CLKREG(&clk_pxa95x_ssp2, "pxa27x-ssp.1", NULL),
+        INIT_CLKREG(&clk_pxa95x_ssp3, "pxa27x-ssp.2", NULL),
+        INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL),
+        INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
+        INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
+};
+
+void __init pxa95x_init_irq(void)
+{
+        pxa_init_irq(96, NULL);
+        pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
+}
+
+/*
+ * device registration specific to PXA93x.
+ */
+
+void __init pxa95x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
+{
+        pxa_register_device(&pxa3xx_device_i2c_power, info);
+}
+
+static struct platform_device *devices[] __initdata = {
+        &sa1100_device_rtc,
+        &pxa_device_rtc,
+        &pxa27x_device_ssp1,
+        &pxa27x_device_ssp2,
+        &pxa27x_device_ssp3,
+        &pxa3xx_device_ssp4,
+        &pxa27x_device_pwm0,
+        &pxa27x_device_pwm1,
+};
+
+static struct sys_device pxa95x_sysdev[] = {
+        {
+                .cls    = &pxa_irq_sysclass,
+        }, {
+                .cls    = &pxa_gpio_sysclass,
+        }, {
+                .cls    = &pxa3xx_clock_sysclass,
+        }
+};
+
+static int __init pxa95x_init(void)
+{
+        int ret = 0, i;
+
+        if (cpu_is_pxa95x()) {
+                mfp_init_base(io_p2v(MFPR_BASE));
+                mfp_init_addr(pxa95x_mfp_addr_map);
+
+                reset_status = ARSR;
+
+                /*
+                 * clear RDH bit every time after reset
+                 *
+                 * Note: the last 3 bits DxS are write-1-to-clear so carefully
+                 * preserve them here in case they will be referenced later
+                 */
+                ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
+
+                clkdev_add_table(pxa95x_clkregs, ARRAY_SIZE(pxa95x_clkregs));
+
+                if ((ret = pxa_init_dma(IRQ_DMA, 32)))
+                        return ret;
+
+                for (i = 0; i < ARRAY_SIZE(pxa95x_sysdev); i++) {
+                        ret = sysdev_register(&pxa95x_sysdev[i]);
+                        if (ret)
+                                pr_err("failed to register sysdev[%d]\n", i);
+                }
+
+                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+        }
+
+        return ret;
+}
+
+postcore_initcall(pxa95x_init);
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 4121d03ea2c3..8361151be054 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -588,6 +588,9 @@ static struct pxafb_mach_info raumfeld_sharp_lcd_info = {
         .num_modes      = 1,
         .video_mem_size = 0x400000,
         .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+#ifdef CONFIG_PXA3XX_GCU
+        .acceleration_enabled = 1,
+#endif
 };
 
 static void __init raumfeld_lcd_init(void)
@@ -616,6 +619,8 @@ static void __init raumfeld_lcd_init(void)
                 pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n");
         else
                 gpio_direction_output(GPIO_DISPLAY_ENABLE, 1);
+
+        platform_device_register(&pxa3xx_device_gcu);
 }
 
 /**
@@ -1085,7 +1090,7 @@ static void __init raumfeld_speaker_init(void)
 MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
         .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
         .init_machine   = raumfeld_controller_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
@@ -1095,7 +1100,7 @@ MACHINE_END
 MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
         .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
         .init_machine   = raumfeld_connector_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
@@ -1105,7 +1110,7 @@ MACHINE_END
 MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
         .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
         .init_machine   = raumfeld_speaker_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index ffa50e633ee6..c1ca8cb467fc 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -597,7 +597,7 @@ static void __init saar_init(void)
 MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
         /* Maintainer: Eric Miao <eric.miao@marvell.com> */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = saar_init,
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
new file mode 100644
index 000000000000..e497922f761a
--- /dev/null
+++ b/arch/arm/mach-pxa/saarb.c
@@ -0,0 +1,114 @@
+/*
+ *  linux/arch/arm/mach-pxa/saarb.c
+ *
+ *  Support for the Marvell Handheld Platform (aka SAARB)
+ *
+ *  Copyright (C) 2007-2010 Marvell International Ltd.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/mfd/88pm860x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/mfp.h>
+#include <mach/mfp-pxa930.h>
+#include <mach/gpio.h>
+
+#include <plat/i2c.h>
+
+#include "generic.h"
+
+#define SAARB_NR_IRQS   (IRQ_BOARD_START + 40)
+
+static struct pm860x_touch_pdata saarb_touch = {
+        .gpadc_prebias  = 1,
+        .slot_cycle     = 1,
+        .tsi_prebias    = 6,
+        .pen_prebias    = 16,
+        .pen_prechg     = 2,
+        .res_x          = 300,
+};
+
+static struct pm860x_backlight_pdata saarb_backlight[] = {
+        {
+                .id     = PM8606_ID_BACKLIGHT,
+                .iset   = PM8606_WLED_CURRENT(24),
+                .flags  = PM8606_BACKLIGHT1,
+        },
+        {},
+};
+
+static struct pm860x_led_pdata saarb_led[] = {
+        {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_RED,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_GREEN,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_BLUE,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_RED,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_GREEN,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_BLUE,
+        },
+};
+
+static struct pm860x_platform_data saarb_pm8607_info = {
+        .touch          = &saarb_touch,
+        .backlight      = &saarb_backlight[0],
+        .led            = &saarb_led[0],
+        .companion_addr = 0x10,
+        .irq_mode       = 0,
+        .irq_base       = IRQ_BOARD_START,
+
+        .i2c_port       = GI2C_PORT,
+};
+
+static struct i2c_board_info saarb_i2c_info[] = {
+        {
+                .type           = "88PM860x",
+                .addr           = 0x34,
+                .platform_data  = &saarb_pm8607_info,
+                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+        },
+};
+
+static void __init saarb_init(void)
+{
+        pxa_set_ffuart_info(NULL);
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(saarb_i2c_info));
+}
+
+MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)")
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .nr_irqs        = SAARB_NR_IRQS,
+        .init_irq       = pxa95x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = saarb_init,
+MACHINE_END
+
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 8fed027b12dc..e68d46d415f3 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -579,7 +579,8 @@ static int sharpsl_ac_check(void)
 static int sharpsl_pm_suspend(struct platform_device *pdev, pm_message_t state)
 {
         sharpsl_pm.flags |= SHARPSL_SUSPENDED;
-        flush_scheduled_work();
+        flush_delayed_work_sync(&toggle_charger);
+        flush_delayed_work_sync(&sharpsl_bat);
 
         if (sharpsl_pm.charge_mode == CHRG_ON)
                 sharpsl_pm.flags |= SHARPSL_DO_OFFLINE_CHRG;
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index ae008110db4e..c551da86baf6 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -14,7 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/hardware.h>
-
+#include <mach/smemc.h>
 #include <mach/pxa2xx-regs.h>
 
 #define MDREFR_KDIV     0x200a4000      // all banks
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c
index d6f6904132a6..232b7316ec08 100644
--- a/arch/arm/mach-pxa/smemc.c
+++ b/arch/arm/mach-pxa/smemc.c
@@ -9,50 +9,37 @@
 #include <linux/sysdev.h>
 
 #include <mach/hardware.h>
-
-#define SMEMC_PHYS_BASE (0x4A000000)
-#define SMEMC_PHYS_SIZE (0x90)
-
-#define MSC0            (0x08)  /* Static Memory Controller Register 0 */
-#define MSC1            (0x0C)  /* Static Memory Controller Register 1 */
-#define SXCNFG          (0x1C)  /* Synchronous Static Memory Control Register */
-#define MEMCLKCFG       (0x68)  /* Clock Configuration */
-#define CSADRCFG0       (0x80)  /* Address Configuration Register for CS0 */
-#define CSADRCFG1       (0x84)  /* Address Configuration Register for CS1 */
-#define CSADRCFG2       (0x88)  /* Address Configuration Register for CS2 */
-#define CSADRCFG3       (0x8C)  /* Address Configuration Register for CS3 */
+#include <mach/smemc.h>
 
 #ifdef CONFIG_PM
-static void __iomem *smemc_mmio_base;
-
 static unsigned long msc[2];
 static unsigned long sxcnfg, memclkcfg;
 static unsigned long csadrcfg[4];
 
 static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state)
 {
-        msc[0] = __raw_readl(smemc_mmio_base + MSC0);
-        msc[1] = __raw_readl(smemc_mmio_base + MSC1);
-        sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG);
-        memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG);
-        csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0);
-        csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1);
-        csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2);
-        csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3);
+        msc[0] = __raw_readl(MSC0);
+        msc[1] = __raw_readl(MSC1);
+        sxcnfg = __raw_readl(SXCNFG);
+        memclkcfg = __raw_readl(MEMCLKCFG);
+        csadrcfg[0] = __raw_readl(CSADRCFG0);
+        csadrcfg[1] = __raw_readl(CSADRCFG1);
+        csadrcfg[2] = __raw_readl(CSADRCFG2);
+        csadrcfg[3] = __raw_readl(CSADRCFG3);
 
         return 0;
 }
 
 static int pxa3xx_smemc_resume(struct sys_device *dev)
 {
-        __raw_writel(msc[0], smemc_mmio_base + MSC0);
-        __raw_writel(msc[1], smemc_mmio_base + MSC1);
-        __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG);
-        __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG);
-        __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0);
-        __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1);
-        __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2);
-        __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3);
+        __raw_writel(msc[0], MSC0);
+        __raw_writel(msc[1], MSC1);
+        __raw_writel(sxcnfg, SXCNFG);
+        __raw_writel(memclkcfg, MEMCLKCFG);
+        __raw_writel(csadrcfg[0], CSADRCFG0);
+        __raw_writel(csadrcfg[1], CSADRCFG1);
+        __raw_writel(csadrcfg[2], CSADRCFG2);
+        __raw_writel(csadrcfg[3], CSADRCFG3);
 
         return 0;
 }
@@ -73,10 +60,6 @@ static int __init smemc_init(void)
         int ret = 0;
 
         if (cpu_is_pxa3xx()) {
-                smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE);
-                if (smemc_mmio_base == NULL)
-                        return -ENODEV;
-
                 ret = sysdev_class_register(&smemc_sysclass);
                 if (ret)
                         return ret;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index f736119f1ebf..0bc938729c4c 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -23,10 +23,11 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/spi/corgi_lcd.h>
-#include <linux/mtd/physmap.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/mtd/sharpsl.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/regulator/machine.h>
+#include <linux/io.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -41,9 +42,9 @@
 #include <mach/mmc.h>
 #include <mach/ohci.h>
 #include <mach/pxafb.h>
-#include <mach/pxa2xx_spi.h>
 #include <mach/spitz.h>
 #include <mach/sharpsl_pm.h>
+#include <mach/smemc.h>
 
 #include <plat/i2c.h>
 
@@ -929,9 +930,10 @@ static void spitz_poweroff(void)
 
 static void spitz_restart(char mode, const char *cmd)
 {
+        uint32_t msc0 = __raw_readl(MSC0);
         /* Bootloader magic for a reboot */
-        if ((MSC0 & 0xffff0000) == 0x7ff00000)
-                MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
+        if ((msc0 & 0xffff0000) == 0x7ff00000)
+                __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0);
 
         spitz_poweroff();
 }
@@ -980,7 +982,7 @@ static void __init spitz_fixup(struct machine_desc *desc,
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
         .fixup          = spitz_fixup,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .init_machine   = spitz_init,
         .timer          = &pxa_timer,
@@ -990,7 +992,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
         .fixup          = spitz_fixup,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .init_machine   = spitz_init,
         .timer          = &pxa_timer,
@@ -1000,7 +1002,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
         .fixup          = spitz_fixup,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .init_machine   = spitz_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 738adc1773fd..9a14fdb83c82 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -46,10 +46,11 @@
 #include <plat/i2c.h>
 #include <mach/mmc.h>
 #include <mach/udc.h>
-#include <mach/pxa2xx_spi.h>
 #include <mach/pxa27x-udc.h>
+#include <mach/smemc.h>
 
 #include <linux/spi/spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/mfd/da903x.h>
 #include <linux/sht15.h>
 
@@ -976,7 +977,7 @@ static void __init stargate2_init(void)
 {
         /* This is probably a board specific hack as this must be set
            prior to connecting the MFP stuff up. */
-        MECR &= ~MECR_NOS;
+        __raw_writel(__raw_readl(MECR) & ~MECR_NOS, MECR);
 
         pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config));
 
@@ -998,7 +999,7 @@ static void __init stargate2_init(void)
 
 #ifdef CONFIG_MACH_INTELMOTE2
 MACHINE_START(INTELMOTE2, "IMOTE 2")
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = imote2_init,
@@ -1008,7 +1009,7 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_STARGATE2
 MACHINE_START(STARGATE2, "Stargate 2")
-        .map_io = pxa_map_io,
+        .map_io = pxa27x_map_io,
         .nr_irqs = STARGATE_NR_IRQS,
         .init_irq = pxa27x_init_irq,
         .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 2ea7545273ad..9cecf8366db8 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -490,7 +490,7 @@ static void __init tavorevb_init(void)
 MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
         /* Maintainer: Eric Miao <eric.miao@marvell.com> */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = tavorevb_init,
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
index dc3011697bbf..70191a9450eb 100644
--- a/arch/arm/mach-pxa/tavorevb3.c
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -127,7 +127,7 @@ static void __init evb3_init(void)
 
 MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .nr_irqs        = TAVOREVB3_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 293e40aeaf29..e7f64d9b4f2d 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -17,11 +17,11 @@
 #include <linux/interrupt.h>
 #include <linux/clockchips.h>
 #include <linux/sched.h>
-#include <linux/cnt32_to_63.h>
 
 #include <asm/div64.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 #include <mach/regs-ost.h>
 
 /*
@@ -32,29 +32,18 @@
  * long as there is always less than 582 seconds between successive
  * calls to sched_clock() which should always be the case in practice.
  */
+static DEFINE_CLOCK_DATA(cd);
 
-#define OSCR2NS_SCALE_FACTOR 10
-
-static unsigned long oscr2ns_scale;
-
-static void __init set_oscr2ns_scale(unsigned long oscr_rate)
+unsigned long long notrace sched_clock(void)
 {
-        unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
-        do_div(v, oscr_rate);
-        oscr2ns_scale = v;
-        /*
-         * We want an even value to automatically clear the top bit
-         * returned by cnt32_to_63() without an additional run time
-         * instruction. So if the LSB is 1 then round it up.
-         */
-        if (oscr2ns_scale & 1)
-                oscr2ns_scale++;
+        u32 cyc = OSCR;
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 }
 
-unsigned long long sched_clock(void)
+static void notrace pxa_update_sched_clock(void)
 {
-        unsigned long long v = cnt32_to_63(OSCR);
-        return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
+        u32 cyc = OSCR;
+        update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 
@@ -127,7 +116,6 @@ static struct clocksource cksrc_pxa_oscr0 = {
         .rating         = 200,
         .read           = pxa_read_oscr,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -145,7 +133,7 @@ static void __init pxa_timer_init(void)
         OIER = 0;
         OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 
-        set_oscr2ns_scale(clock_tick_rate);
+        init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);
 
         ckevt_pxa_osmr0.mult =
                 div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
@@ -155,12 +143,9 @@ static void __init pxa_timer_init(void)
                 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
         ckevt_pxa_osmr0.cpumask = cpumask_of(0);
 
-        cksrc_pxa_oscr0.mult =
-                clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
-
         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 
-        clocksource_register(&cksrc_pxa_oscr0);
+        clocksource_register_hz(&cksrc_pxa_oscr0, clock_tick_rate);
         clockevents_register_device(&ckevt_pxa_osmr0);
 }
 
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 0ee1df49606d..af152e70cfcf 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -32,6 +32,7 @@
 #include <linux/gpio.h>
 #include <linux/pda_power.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/input/matrix_keypad.h>
 
 #include <asm/setup.h>
@@ -44,8 +45,8 @@
 #include <mach/mmc.h>
 #include <mach/udc.h>
 #include <mach/tosa_bt.h>
-#include <mach/pxa2xx_spi.h>
 #include <mach/audio.h>
+#include <mach/smemc.h>
 
 #include <asm/mach/arch.h>
 #include <mach/tosa.h>
@@ -893,9 +894,11 @@ static void tosa_poweroff(void)
 
 static void tosa_restart(char mode, const char *cmd)
 {
+        uint32_t msc0 = __raw_readl(MSC0);
+
         /* Bootloader magic for a reboot */
-        if((MSC0 & 0xffff0000) == 0x7ff00000)
-                MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
+        if((msc0 & 0xffff0000) == 0x7ff00000)
+                __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0);
 
         tosa_poweroff();
 }
@@ -953,7 +956,7 @@ static void __init fixup_tosa(struct machine_desc *desc,
 
 MACHINE_START(TOSA, "SHARP Tosa")
         .fixup          = fixup_tosa,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = TOSA_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = tosa_init,
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 565d062f51d5..423261d63d07 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -40,13 +40,13 @@
 #include <asm/mach/flash.h>
 
 #include <mach/pxa27x.h>
-#include <mach/pxa2xx_spi.h>
 #include <mach/trizeps4.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
+#include <mach/smemc.h>
 #include <plat/i2c.h>
 
 #include "generic.h"
@@ -539,10 +539,10 @@ static void __init trizeps4_init(void)
 
 static void __init trizeps4_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));
 
-        if ((MSC0 & 0x8) && (BOOT_DEF & 0x1)) {
+        if ((__raw_readl(MSC0) & 0x8) && (__raw_readl(BOOT_DEF) & 0x1)) {
                 /* if flash is 16 bit wide its a Trizeps4 WL */
                 __machine_arch_type = MACH_TYPE_TRIZEPS4WL;
                 trizeps4_flash_data[0].width = 2;
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 438fc9a5ed59..de69b203afa7 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -983,7 +983,7 @@ static struct map_desc viper_io_desc[] __initdata = {
 
 static void __init viper_map_io(void)
 {
-        pxa_map_io();
+        pxa25x_map_io();
 
         iotable_init(viper_io_desc, ARRAY_SIZE(viper_io_desc));
 
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index f45ac0961778..b9b579715ff6 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -719,7 +719,7 @@ static void __init vpac270_init(void)
 
 MACHINE_START(VPAC270, "Voipac PXA270")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = vpac270_init
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index 3260ce73d327..51c0281c6e0a 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -31,6 +31,7 @@
 #include <mach/hardware.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa25x.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 
@@ -172,9 +173,9 @@ static void __init xcep_init(void)
 
         /* See Intel XScale Developer's Guide for details */
         /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */
-        MSC1 = (MSC1 & 0xffff) | 0xD5540000;
+        __raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1);
         /* Set RDF and RDN to appropriate values (chip select 5 (fpga)) */
-        MSC2 = (MSC2 & 0xffff) | 0x72A00000;
+        __raw_writel((__raw_readl(MSC2) & 0xffff) | 0x72A00000, MSC2);
 
         platform_add_devices(ARRAY_AND_SIZE(devices));
         pxa_set_i2c_info(&xcep_i2c_platform_data);
@@ -183,7 +184,7 @@ static void __init xcep_init(void)
 MACHINE_START(XCEP, "Iskratel XCEP")
         .boot_params    = 0xa0000100,
         .init_machine   = xcep_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index fefde9848d82..a323e076129e 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -20,6 +20,7 @@
 #include <linux/z2_battery.h>
 #include <linux/dma-mapping.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/spi/libertas_spi.h>
 #include <linux/spi/lms283gf05.h>
 #include <linux/power_supply.h>
@@ -38,7 +39,6 @@
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <plat/pxa27x_keypad.h>
-#include <mach/pxa2xx_spi.h>
 
 #include <plat/i2c.h>
 
@@ -704,7 +704,7 @@ static void __init z2_init(void)
 
 MACHINE_START(ZIPIT2, "Zipit Z2")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = z2_init,
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index dea46a2d089b..bf034c7670dd 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -20,6 +20,7 @@
 #include <linux/dm9000.h>
 #include <linux/mmc/host.h>
 #include <linux/spi/spi.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
@@ -41,12 +42,12 @@
 #include <mach/pxa27x-udc.h>
 #include <mach/udc.h>
 #include <mach/pxafb.h>
-#include <mach/pxa2xx_spi.h>
 #include <mach/mfp-pxa27x.h>
 #include <mach/pm.h>
 #include <mach/audio.h>
 #include <mach/arcom-pcmcia.h>
 #include <mach/zeus.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 
@@ -823,13 +824,16 @@ static mfp_cfg_t zeus_pin_config[] __initdata = {
 static void __init zeus_init(void)
 {
         u16 dm9000_msc = DM9K_MSC_VALUE;
+        u32 msc0, msc1;
 
         system_rev = __raw_readw(ZEUS_CPLD_VERSION);
         pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
 
         /* Fix timings for dm9000s (CS1/CS2)*/
-        MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16);
-        MSC1 = (MSC1 & 0xffff0000) | dm9000_msc;
+        msc0 = __raw_readl(MSC0) & 0x0000ffff | (dm9000_msc << 16);
+        msc1 = __raw_readl(MSC1) & 0xffff0000 | dm9000_msc;
+        __raw_writel(msc0, MSC0);
+        __raw_writel(msc1, MSC1);
 
         pm_power_off = zeus_power_off;
         zeus_setup_apm();
@@ -883,7 +887,7 @@ static struct map_desc zeus_io_desc[] __initdata = {
 
 static void __init zeus_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
 
         iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
 
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 702f7a68e87d..a4c784aab764 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -423,7 +423,7 @@ static void __init zylonite_init(void)
 
 MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .nr_irqs        = ZYLONITE_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 07c08151dfe6..1c6602cf50e4 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -30,8 +30,8 @@
 #include <linux/ata_platform.h>
 #include <linux/amba/mmci.h>
 #include <linux/gfp.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
 #include <asm/system.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -47,15 +47,13 @@
 
 #include <asm/hardware/gic.h>
 
-#include <mach/clkdev.h>
 #include <mach/platform.h>
 #include <mach/irqs.h>
-#include <plat/timer-sp.h>
+#include <asm/hardware/timer-sp.h>
 
-#include "core.h"
+#include <plat/sched_clock.h>
 
-/* used by entry-macro.S and platsmp.c */
-void __iomem *gic_cpu_base_addr;
+#include "core.h"
 
 #ifdef CONFIG_ZONE_DMA
 /*
@@ -658,6 +656,12 @@ void realview_leds_event(led_event_t ledevt)
 #endif  /* CONFIG_LEDS */
 
 /*
+ * The sched_clock counter
+ */
+#define REFCOUNTER              (__io_address(REALVIEW_SYS_BASE) + \
+                                 REALVIEW_SYS_24MHz_OFFSET)
+
+/*
  * Where is the timer (VA)?
  */
 void __iomem *timer0_va_base;
@@ -672,6 +676,8 @@ void __init realview_timer_init(unsigned int timer_irq)
 {
         u32 val;
 
+        versatile_sched_clock_init(REFCOUNTER, 24000000);
+
         /* 
          * set clock frequency: 
          *      REALVIEW_REFCLK is 32KHz
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 781bca68a9fa..693239ddc39e 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -53,7 +53,6 @@ extern struct platform_device realview_i2c_device;
 extern struct mmci_platform_data realview_mmc0_plat_data;
 extern struct mmci_platform_data realview_mmc1_plat_data;
 extern struct clcd_board clcd_plat_data;
-extern void __iomem *gic_cpu_base_addr;
 extern void __iomem *timer0_va_base;
 extern void __iomem *timer1_va_base;
 extern void __iomem *timer2_va_base;
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index f95521a5e5ce..a87523d095e6 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -11,14 +11,11 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
-#include <linux/completion.h>
 
 #include <asm/cacheflush.h>
 
 extern volatile int pen_release;
 
-static DECLARE_COMPLETION(cpu_killed);
-
 static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
@@ -34,10 +31,10 @@ static inline void cpu_enter_lowpower(void)
         "       bic     %0, %0, #0x20\n"
         "       mcr     p15, 0, %0, c1, c0, 1\n"
         "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, #0x04\n"
+        "       bic     %0, %0, %2\n"
         "       mcr     p15, 0, %0, c1, c0, 0\n"
           : "=&r" (v)
-          : "r" (0)
+          : "r" (0), "Ir" (CR_C)
           : "cc");
 }
 
@@ -46,17 +43,17 @@ static inline void cpu_leave_lowpower(void)
         unsigned int v;
 
         asm volatile(   "mrc    p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, #0x04\n"
+        "       orr     %0, %0, %1\n"
         "       mcr     p15, 0, %0, c1, c0, 0\n"
         "       mrc     p15, 0, %0, c1, c0, 1\n"
         "       orr     %0, %0, #0x20\n"
         "       mcr     p15, 0, %0, c1, c0, 1\n"
           : "=&r" (v)
-          :
+          : "Ir" (CR_C)
           : "cc");
 }
 
-static inline void platform_do_lowpower(unsigned int cpu)
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
         /*
          * there is no power-control hardware on this platform, so all
@@ -80,22 +77,19 @@ static inline void platform_do_lowpower(unsigned int cpu)
                 }
 
                 /*
-                 * getting here, means that we have come out of WFI without
+                 * Getting here, means that we have come out of WFI without
                  * having been woken up - this shouldn't happen
                  *
-                 * The trouble is, letting people know about this is not really
-                 * possible, since we are currently running incoherently, and
-                 * therefore cannot safely call printk() or anything else
+                 * Just note it happening - when we're woken, we can report
+                 * its occurrence.
                  */
-#ifdef DEBUG
-                printk("CPU%u: spurious wakeup call\n", cpu);
-#endif
+                (*spurious)++;
         }
 }
 
 int platform_cpu_kill(unsigned int cpu)
 {
-        return wait_for_completion_timeout(&cpu_killed, 5000);
+        return 1;
 }
 
 /*
@@ -105,30 +99,22 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-#ifdef DEBUG
-        unsigned int this_cpu = hard_smp_processor_id();
-
-        if (cpu != this_cpu) {
-                printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
-                           this_cpu, cpu);
-                BUG();
-        }
-#endif
-
-        printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
-        complete(&cpu_killed);
+        int spurious = 0;
 
         /*
          * we're ready for shutdown now, so do it
          */
         cpu_enter_lowpower();
-        platform_do_lowpower(cpu);
+        platform_do_lowpower(cpu, &spurious);
 
         /*
          * bring this CPU back into the world of cache
          * coherency, and then restore interrupts
          */
         cpu_leave_lowpower();
+
+        if (spurious)
+                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
 
 int platform_cpu_disable(unsigned int cpu)
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
index 340a5c276946..4071164aebaa 100644
--- a/arch/arm/mach-realview/include/mach/entry-macro.S
+++ b/arch/arm/mach-realview/include/mach/entry-macro.S
@@ -8,74 +8,11 @@
  * warranty of any kind, whether express or implied.
  */
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
                 .macro  disable_fiq
                 .endm
 
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =gic_cpu_base_addr
-                ldr     \base, [\base]
-                .endm
-
                 .macro  arch_ret_to_user, tmp1, tmp2
                 .endm
 
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an interrupt if it's
-                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
-                ldr     \tmp, =1021
-
-                bic     \irqnr, \irqstat, #0x1c00
-
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-
-                .endm
-
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt on the
-                 * controller, since this requires the original irqstat value which
-                 * we won't easily be able to recreate later.
-                 */
-
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* As above, this assumes that irqstat and base are preserved.. */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index d3cd265cb058..c8221b38ee7c 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -2,14 +2,13 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
-#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
  */
-static inline void smp_cross_call(const struct cpumask *mask)
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
 {
-        gic_raise_softirq(mask, 1);
+        gic_raise_softirq(mask, ipi);
 }
 
 #endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 009265818d55..a22bf67f2f78 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -19,7 +19,6 @@
 #include <asm/cacheflush.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/localtimer.h>
 #include <asm/unified.h>
 
 #include <mach/board-eb.h>
@@ -37,6 +36,19 @@ extern void realview_secondary_startup(void);
  */
 volatile int __cpuinitdata pen_release = -1;
 
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
+{
+        pen_release = val;
+        smp_wmb();
+        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
 static void __iomem *scu_base_addr(void)
 {
         if (machine_is_realview_eb_mp())
@@ -50,33 +62,22 @@ static void __iomem *scu_base_addr(void)
                 return (void __iomem *)0;
 }
 
-static inline unsigned int get_core_count(void)
-{
-        void __iomem *scu_base = scu_base_addr();
-        if (scu_base)
-                return scu_get_core_count(scu_base);
-        return 1;
-}
-
 static DEFINE_SPINLOCK(boot_lock);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        trace_hardirqs_off();
-
         /*
          * if any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_secondary_init(0);
 
         /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
-        pen_release = -1;
-        smp_wmb();
+        write_pen_release(-1);
 
         /*
          * Synchronise with the boot thread.
@@ -103,20 +104,14 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * Note that "pen_release" is the hardware CPU ID, whereas
          * "cpu" is Linux's internal ID.
          */
-        pen_release = cpu;
-        flush_cache_all();
+        write_pen_release(cpu);
 
         /*
-         * XXX
-         *
-         * This is a later addition to the booting protocol: the
-         * bootMonitor now puts secondary cores into WFI, so
-         * poke_milo() no longer gets the cores moving; we need
-         * to send a soft interrupt to wake the secondary core.
-         * Use smp_cross_call() for this, since there's little
-         * point duplicating the code here
+         * Send the secondary CPU a soft interrupt, thereby causing
+         * the boot monitor to read the system wide flags register,
+         * and branch to the address found there.
          */
-        smp_cross_call(cpumask_of(cpu));
+        smp_cross_call(cpumask_of(cpu), 1);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
@@ -136,48 +131,18 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         return pen_release != -1 ? -ENOSYS : 0;
 }
 
-static void __init poke_milo(void)
-{
-        /* nobody is to be released from the pen yet */
-        pen_release = -1;
-
-        /*
-         * Write the address of secondary startup into the system-wide flags
-         * register. The BootMonitor waits for this register to become
-         * non-zero.
-         */
-        __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
-                     __io_address(REALVIEW_SYS_FLAGSSET));
-
-        mb();
-}
-
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
  */
 void __init smp_init_cpus(void)
 {
-        unsigned int i, ncores = get_core_count();
+        void __iomem *scu_base = scu_base_addr();
+        unsigned int i, ncores;
 
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
-        unsigned int ncores = get_core_count();
-        unsigned int cpu = smp_processor_id();
-        int i;
+        ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
         /* sanity check */
-        if (ncores == 0) {
-                printk(KERN_ERR
-                       "Realview: strange CM count of 0? Default to 1\n");
-
-                ncores = 1;
-        }
-
         if (ncores > NR_CPUS) {
                 printk(KERN_WARNING
                        "Realview: no. of cores (%d) greater than configured "
@@ -186,13 +151,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                 ncores = NR_CPUS;
         }
 
-        smp_store_cpu_info(cpu);
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+}
 
-        /*
-         * are we trying to boot more cores than exist?
-         */
-        if (max_cpus > ncores)
-                max_cpus = ncores;
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
 
         /*
          * Initialise the present map, which describes the set of CPUs
@@ -201,21 +166,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
+        scu_enable(scu_base_addr());
+
         /*
-         * Initialise the SCU if there are more than one CPU and let
-         * them know where to start. Note that, on modern versions of
-         * MILO, the "poke" doesn't actually do anything until each
-         * individual core is sent a soft interrupt to get it out of
-         * WFI
+         * Write the address of secondary startup into the
+         * system-wide flags register. The BootMonitor waits
+         * until it receives a soft interrupt, and then the
+         * secondary CPU branches to this address.
          */
-        if (max_cpus > 1) {
-                /*
-                 * Enable the local timer or broadcast device for the
-                 * boot CPU, but only if we have more than one CPU.
-                 */
-                percpu_timer_setup();
-
-                scu_enable(scu_base_addr());
-                poke_milo();
-        }
+        __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
+                     __io_address(REALVIEW_SYS_FLAGSSET));
 }
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index f2697106f809..6ef5c5e528b2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -364,21 +364,19 @@ static void __init gic_init_irq(void)
                 writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
 
                 /* core tile GIC, primary */
-                gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
-                gic_dist_init(0, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE), 29);
-                gic_cpu_init(0, gic_cpu_base_addr);
+                gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE),
+                         __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
 
 #ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
                 /* board GIC, secondary */
-                gic_dist_init(1, __io_address(REALVIEW_EB_GIC_DIST_BASE), 64);
-                gic_cpu_init(1, __io_address(REALVIEW_EB_GIC_CPU_BASE));
+                gic_init(1, 64, __io_address(REALVIEW_EB_GIC_DIST_BASE),
+                         __io_address(REALVIEW_EB_GIC_CPU_BASE));
                 gic_cascade_irq(1, IRQ_EB11MP_EB_IRQ1);
 #endif
         } else {
                 /* board GIC, primary */
-                gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
-                gic_dist_init(0, __io_address(REALVIEW_EB_GIC_DIST_BASE), 29);
-                gic_cpu_init(0, gic_cpu_base_addr);
+                gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE),
+                         __io_address(REALVIEW_EB_GIC_CPU_BASE));
         }
 }
 
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index a4125619d71b..cbdc97a5685f 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -304,13 +304,14 @@ static struct platform_device char_lcd_device = {
 static void __init gic_init_irq(void)
 {
         /* ARM1176 DevChip GIC, primary */
-        gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
-        gic_dist_init(0, __io_address(REALVIEW_DC1176_GIC_DIST_BASE), IRQ_DC1176_GIC_START);
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_init(0, IRQ_DC1176_GIC_START,
+                 __io_address(REALVIEW_DC1176_GIC_DIST_BASE),
+                 __io_address(REALVIEW_DC1176_GIC_CPU_BASE));
 
         /* board GIC, secondary */
-        gic_dist_init(1, __io_address(REALVIEW_PB1176_GIC_DIST_BASE), IRQ_PB1176_GIC_START);
-        gic_cpu_init(1, __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
+        gic_init(1, IRQ_PB1176_GIC_START,
+                 __io_address(REALVIEW_PB1176_GIC_DIST_BASE),
+                 __io_address(REALVIEW_PB1176_GIC_CPU_BASE));
         gic_cascade_irq(1, IRQ_DC1176_PB_IRQ1);
 }
 
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 117b95b2ca15..8e8ab7d29a6a 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -309,13 +309,13 @@ static void __init gic_init_irq(void)
         writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
 
         /* ARM11MPCore test chip GIC, primary */
-        gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
-        gic_dist_init(0, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE), 29);
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
+                 __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
 
         /* board GIC, secondary */
-        gic_dist_init(1, __io_address(REALVIEW_PB11MP_GIC_DIST_BASE), IRQ_PB11MP_GIC_START);
-        gic_cpu_init(1, __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
+        gic_init(1, IRQ_PB11MP_GIC_START,
+                 __io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
+                 __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
         gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
 }
 
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 929b8dc12e81..841118e3e118 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -273,9 +273,9 @@ static struct platform_device pmu_device = {
 static void __init gic_init_irq(void)
 {
         /* ARM PB-A8 on-board GIC */
-        gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE);
-        gic_dist_init(0, __io_address(REALVIEW_PBA8_GIC_DIST_BASE), IRQ_PBA8_GIC_START);
-        gic_cpu_init(0, __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
+        gic_init(0, IRQ_PBA8_GIC_START,
+                 __io_address(REALVIEW_PBA8_GIC_DIST_BASE),
+                 __io_address(REALVIEW_PBA8_GIC_CPU_BASE));
 }
 
 static void __init realview_pba8_timer_init(void)
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index b9f9e20031a7..02b755b009db 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -313,15 +313,12 @@ static void __init gic_init_irq(void)
 {
         /* ARM PBX on-board GIC */
         if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
-                gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE);
-                gic_dist_init(0, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
-                              29);
-                gic_cpu_init(0, __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
+                gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
+                         __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
         } else {
-                gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE);
-                gic_dist_init(0, __io_address(REALVIEW_PBX_GIC_DIST_BASE),
-                              IRQ_PBX_GIC_START);
-                gic_cpu_init(0, __io_address(REALVIEW_PBX_GIC_CPU_BASE));
+                gic_init(0, IRQ_PBX_GIC_START,
+                         __io_address(REALVIEW_PBX_GIC_DIST_BASE),
+                         __io_address(REALVIEW_PBX_GIC_CPU_BASE));
         }
 }
 
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index 6983cb4d4cae..e82ab4aa7ab9 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -59,7 +59,7 @@ config MACH_JIVE
           Say Y here if you are using the Logitech Jive.
 
 config MACH_JIVE_SHOW_BOOTLOADER
-        bool "Allow access to bootloader partitions in MTD"
+        bool "Allow access to bootloader partitions in MTD (EXPERIMENTAL)"
         depends on MACH_JIVE && EXPERIMENTAL
 
 config MACH_SMDK2413
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 82ce4aa6d61a..72ab289e7816 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -24,8 +24,6 @@
 
 #include <mach/regs-irq.h>
 
-void __iomem *gic_cpu_base_addr;
-
 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
                          unsigned int irq_start);
 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
@@ -122,9 +120,7 @@ void __init s5pv310_init_irq(void)
 {
         int irq;
 
-        gic_cpu_base_addr = S5P_VA_GIC_CPU;
-        gic_dist_init(0, S5P_VA_GIC_DIST, IRQ_LOCALTIMER);
-        gic_cpu_init(0, S5P_VA_GIC_CPU);
+        gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 
         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-s5pv310/hotplug.c
index 03652c3605f6..afa5392d9fc0 100644
--- a/arch/arm/mach-s5pv310/hotplug.c
+++ b/arch/arm/mach-s5pv310/hotplug.c
@@ -13,14 +13,11 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
-#include <linux/completion.h>
 
 #include <asm/cacheflush.h>
 
 extern volatile int pen_release;
 
-static DECLARE_COMPLETION(cpu_killed);
-
 static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
@@ -33,13 +30,13 @@ static inline void cpu_enter_lowpower(void)
          * Turn off coherency
          */
         "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, #0x20\n"
+        "       bic     %0, %0, %2\n"
         "       mcr     p15, 0, %0, c1, c0, 1\n"
         "       mrc     p15, 0, %0, c1, c0, 0\n"
         "       bic     %0, %0, #0x04\n"
         "       mcr     p15, 0, %0, c1, c0, 0\n"
           : "=&r" (v)
-          : "r" (0)
+          : "r" (0), "Ir" (CR_C)
           : "cc");
 }
 
@@ -49,17 +46,17 @@ static inline void cpu_leave_lowpower(void)
 
         asm volatile(
         "mrc    p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, #0x04\n"
+        "       orr     %0, %0, %1\n"
         "       mcr     p15, 0, %0, c1, c0, 0\n"
         "       mrc     p15, 0, %0, c1, c0, 1\n"
         "       orr     %0, %0, #0x20\n"
         "       mcr     p15, 0, %0, c1, c0, 1\n"
           : "=&r" (v)
-          :
+          : "Ir" (CR_C)
           : "cc");
 }
 
-static inline void platform_do_lowpower(unsigned int cpu)
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
         /*
          * there is no power-control hardware on this platform, so all
@@ -83,22 +80,19 @@ static inline void platform_do_lowpower(unsigned int cpu)
                 }
 
                 /*
-                 * getting here, means that we have come out of WFI without
+                 * Getting here, means that we have come out of WFI without
                  * having been woken up - this shouldn't happen
                  *
-                 * The trouble is, letting people know about this is not really
-                 * possible, since we are currently running incoherently, and
-                 * therefore cannot safely call printk() or anything else
+                 * Just note it happening - when we're woken, we can report
+                 * its occurrence.
                  */
-#ifdef DEBUG
-                printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu);
-#endif
+                (*spurious)++;
         }
 }
 
 int platform_cpu_kill(unsigned int cpu)
 {
-        return wait_for_completion_timeout(&cpu_killed, 5000);
+        return 1;
 }
 
 /*
@@ -108,30 +102,22 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-#ifdef DEBUG
-        unsigned int this_cpu = hard_smp_processor_id();
-
-        if (cpu != this_cpu) {
-                printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
-                           this_cpu, cpu);
-                BUG();
-        }
-#endif
-
-        printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
-        complete(&cpu_killed);
+        int spurious = 0;
 
         /*
          * we're ready for shutdown now, so do it
          */
         cpu_enter_lowpower();
-        platform_do_lowpower(cpu);
+        platform_do_lowpower(cpu, &spurious);
 
         /*
          * bring this CPU back into the world of cache
          * coherency, and then restore interrupts
          */
         cpu_leave_lowpower();
+
+        if (spurious)
+                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
 
 int platform_cpu_disable(unsigned int cpu)
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index b7ec252384f4..393ccbd52c4a 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,16 +7,13 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
-#include <asm/smp_mpidr.h>
-
-extern void __iomem *gic_cpu_base_addr;
 
 /*
  * We use IRQ1 as the IPI
  */
-static inline void smp_cross_call(const struct cpumask *mask)
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
 {
-        gic_raise_softirq(mask, 1);
+        gic_raise_softirq(mask, ipi);
 }
 
 #endif
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-s5pv310/platsmp.c
index d357c198edee..34093b069f67 100644
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ b/arch/arm/mach-s5pv310/platsmp.c
@@ -22,7 +22,6 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/localtimer.h>
 #include <asm/smp_scu.h>
 #include <asm/unified.h>
 
@@ -38,6 +37,19 @@ extern void s5pv310_secondary_startup(void);
 
 volatile int __cpuinitdata pen_release = -1;
 
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
+{
+        pen_release = val;
+        smp_wmb();
+        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
 static void __iomem *scu_base_addr(void)
 {
         return (void __iomem *)(S5P_VA_SCU);
@@ -47,21 +59,18 @@ static DEFINE_SPINLOCK(boot_lock);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        trace_hardirqs_off();
-
         /*
          * if any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_secondary_init(0);
 
         /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
-        pen_release = -1;
-        smp_wmb();
+        write_pen_release(-1);
 
         /*
          * Synchronise with the boot thread.
@@ -88,16 +97,14 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * Note that "pen_release" is the hardware CPU ID, whereas
          * "cpu" is Linux's internal ID.
          */
-        pen_release = cpu;
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+        write_pen_release(cpu);
 
         /*
          * Send the secondary CPU a soft interrupt, thereby causing
          * the boot monitor to read the system wide flags register,
          * and branch to the address found there.
          */
-        smp_cross_call(cpumask_of(cpu));
+        smp_cross_call(cpumask_of(cpu), 1);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
@@ -130,13 +137,6 @@ void __init smp_init_cpus(void)
         ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
         /* sanity check */
-        if (ncores == 0) {
-                printk(KERN_ERR
-                       "S5PV310: strange CM count of 0? Default to 1\n");
-
-                ncores = 1;
-        }
-
         if (ncores > NR_CPUS) {
                 printk(KERN_WARNING
                        "S5PV310: no. of cores (%d) greater than configured "
@@ -149,18 +149,10 @@ void __init smp_init_cpus(void)
                 set_cpu_possible(i, true);
 }
 
-void __init smp_prepare_cpus(unsigned int max_cpus)
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
-        unsigned int ncores = num_possible_cpus();
-        unsigned int cpu = smp_processor_id();
         int i;
 
-        smp_store_cpu_info(cpu);
-
-        /* are we trying to boot more cores than exist? */
-        if (max_cpus > ncores)
-                max_cpus = ncores;
-
         /*
          * Initialise the present map, which describes the set of CPUs
          * actually populated at the present time.
@@ -168,25 +160,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
+        scu_enable(scu_base_addr());
+
         /*
-         * Initialise the SCU if there are more than one CPU and let
-         * them know where to start.
+         * Write the address of secondary startup into the
+         * system-wide flags register. The boot monitor waits
+         * until it receives a soft interrupt, and then the
+         * secondary CPU branches to this address.
          */
-        if (max_cpus > 1) {
-                /*
-                 * Enable the local timer or broadcast device for the
-                 * boot CPU, but only if we have more than one CPU.
-                 */
-                percpu_timer_setup();
-
-                scu_enable(scu_base_addr());
-
-                /*
-                 * Write the address of secondary startup into the
-                 * system-wide flags register. The boot monitor waits
-                 * until it receives a soft interrupt, and then the
-                 * secondary CPU branches to this address.
-                 */
         __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
-        }
 }
diff --git a/arch/arm/mach-s5pv310/time.c b/arch/arm/mach-s5pv310/time.c
index 01b012ad1bfd..b262d4615331 100644
--- a/arch/arm/mach-s5pv310/time.c
+++ b/arch/arm/mach-s5pv310/time.c
@@ -211,7 +211,6 @@ struct clocksource pwm_clocksource = {
         .rating         = 250,
         .read           = s5pv310_pwm4_read,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS ,
 };
 
@@ -230,10 +229,7 @@ static void __init s5pv310_clocksource_init(void)
         s5pv310_pwm_init(4, ~0);
         s5pv310_pwm_start(4, 1);
 
-        pwm_clocksource.mult =
-                clocksource_khz2mult(clock_rate/1000, pwm_clocksource.shift);
-
-        if (clocksource_register(&pwm_clocksource))
+        if (clocksource_register_hz(&pwm_clocksource, clock_rate))
                 panic("%s: can't register clocksource\n", pwm_clocksource.name);
 }
 
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 5da8c35aa0de..42625e4d949a 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -118,6 +118,16 @@ config SA1100_LART
           (also known as the LART).  See <http://www.lartmaker.nl/> for
           information on the LART.
 
+config SA1100_NANOENGINE
+        bool "nanoEngine"
+        select CPU_FREQ_SA1110
+        select PCI
+        select PCI_NANOENGINE
+        help
+          Say Y here if you are using the Bright Star Engineering nanoEngine.
+          See <http://www.brightstareng.com/arm/nanoeng.htm> for information
+          on the BSE nanoEngine.
+
 config SA1100_PLEB
         bool "PLEB"
         select CPU_FREQ_SA1100
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 89349c1dd7a6..e697691eed28 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -37,6 +37,9 @@ obj-$(CONFIG_SA1100_JORNADA720_SSP)	+= jornada720_ssp.o
 obj-$(CONFIG_SA1100_LART)               += lart.o
 led-$(CONFIG_SA1100_LART)               += leds-lart.o
 
+obj-$(CONFIG_SA1100_NANOENGINE)         += nanoengine.o
+obj-$(CONFIG_PCI_NANOENGINE)            += pci-nanoengine.o
+
 obj-$(CONFIG_SA1100_PLEB)               += pleb.o
 
 obj-$(CONFIG_SA1100_SHANNON)            += shannon.o
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index 96f7dc103b59..07d4e8ba3719 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -94,48 +94,47 @@
 
 #include "generic.h"
 
-typedef struct {
+struct sa1100_dram_regs {
         int speed;
         u32 mdcnfg;
         u32 mdcas0;
         u32 mdcas1;
         u32 mdcas2;
-} sa1100_dram_regs_t;
+};
 
 
 static struct cpufreq_driver sa1100_driver;
 
-static sa1100_dram_regs_t sa1100_dram_settings[] =
-{
-        /* speed,     mdcnfg,     mdcas0,     mdcas1,     mdcas2  clock frequency */
-        {  59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /*  59.0 MHz */
-        {  73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /*  73.7 MHz */
-        {  88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff }, /*  88.5 MHz */
-        { 103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff }, /* 103.2 MHz */
-        { 118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 118.0 MHz */
-        { 132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff }, /* 132.7 MHz */
-        { 147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff }, /* 147.5 MHz */
-        { 162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff }, /* 162.2 MHz */
-        { 176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff }, /* 176.9 MHz */
-        { 191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff }, /* 191.7 MHz */
-        { 206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 206.4 MHz */
-        { 221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff }, /* 221.2 MHz */
-        { 235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1 }, /* 235.9 MHz */
-        { 250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 250.7 MHz */
-        { 265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3 }, /* 265.4 MHz */
-        { 280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87 }, /* 280.2 MHz */
+static struct sa1100_dram_regs sa1100_dram_settings[] = {
+        /*speed,     mdcnfg,     mdcas0,     mdcas1,     mdcas2,   clock freq */
+        { 59000, 0x00dc88a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  59.0 MHz */
+        { 73700, 0x011490a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  73.7 MHz */
+        { 88500, 0x014e90a3, 0xcccccccf, 0xfffffffc, 0xffffffff},/*  88.5 MHz */
+        {103200, 0x01889923, 0xcccccccf, 0xfffffffc, 0xffffffff},/* 103.2 MHz */
+        {118000, 0x01c29923, 0x9999998f, 0xfffffff9, 0xffffffff},/* 118.0 MHz */
+        {132700, 0x01fb2123, 0x9999998f, 0xfffffff9, 0xffffffff},/* 132.7 MHz */
+        {147500, 0x02352123, 0x3333330f, 0xfffffff3, 0xffffffff},/* 147.5 MHz */
+        {162200, 0x026b29a3, 0x38e38e1f, 0xfff8e38e, 0xffffffff},/* 162.2 MHz */
+        {176900, 0x02a329a3, 0x71c71c1f, 0xfff1c71c, 0xffffffff},/* 176.9 MHz */
+        {191700, 0x02dd31a3, 0xe38e383f, 0xffe38e38, 0xffffffff},/* 191.7 MHz */
+        {206400, 0x03153223, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 206.4 MHz */
+        {221200, 0x034fba23, 0xc71c703f, 0xffc71c71, 0xffffffff},/* 221.2 MHz */
+        {235900, 0x03853a23, 0xe1e1e07f, 0xe1e1e1e1, 0xffffffe1},/* 235.9 MHz */
+        {250700, 0x03bf3aa3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 250.7 MHz */
+        {265400, 0x03f7c2a3, 0xc3c3c07f, 0xc3c3c3c3, 0xffffffc3},/* 265.4 MHz */
+        {280200, 0x0431c2a3, 0x878780ff, 0x87878787, 0xffffff87},/* 280.2 MHz */
         { 0, 0, 0, 0, 0 } /* last entry */
 };
 
 static void sa1100_update_dram_timings(int current_speed, int new_speed)
 {
-        sa1100_dram_regs_t *settings = sa1100_dram_settings;
+        struct sa1100_dram_regs *settings = sa1100_dram_settings;
 
         /* find speed */
         while (settings->speed != 0) {
-                if(new_speed == settings->speed)
+                if (new_speed == settings->speed)
                         break;
-                
+
                 settings++;
         }
 
@@ -149,7 +148,7 @@ static void sa1100_update_dram_timings(int current_speed, int new_speed)
                 /* We're going FASTER, so first relax the memory
                  * timings before changing the core frequency
                  */
-                
+
                 /* Half the memory access clock */
                 MDCNFG |= MDCNFG_CDB2;
 
@@ -187,7 +186,7 @@ static int sa1100_target(struct cpufreq_policy *policy,
         struct cpufreq_freqs freqs;
 
         new_ppcr = sa11x0_freq_to_ppcr(target_freq);
-        switch(relation){
+        switch (relation) {
         case CPUFREQ_RELATION_L:
                 if (sa11x0_ppcr_to_freq(new_ppcr) > policy->max)
                         new_ppcr--;
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 7252874d328b..675bf8ef97e8 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -16,28 +16,24 @@
  *
  * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
  */
-#include <linux/moduleparam.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
 #include <linux/cpufreq.h>
 #include <linux/delay.h>
 #include <linux/init.h>
-#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/moduleparam.h>
+#include <linux/types.h>
 
-#include <mach/hardware.h>
 #include <asm/cputype.h>
 #include <asm/mach-types.h>
-#include <asm/system.h>
+
+#include <mach/hardware.h>
 
 #include "generic.h"
 
 #undef DEBUG
 
-static struct cpufreq_driver sa1110_driver;
-
 struct sdram_params {
-        const char name[16];
+        const char name[20];
         u_char  rows;           /* bits                          */
         u_char  cas_latency;    /* cycles                        */
         u_char  tck;            /* clock cycle time (ns)         */
@@ -107,6 +103,15 @@ static struct sdram_params sdram_tbl[] __initdata = {
                 .twr            = 8,
                 .refresh        = 64000,
                 .cas_latency    = 3,
+        }, {    /* Micron MT48LC8M16A2TG-75 */
+                .name           = "MT48LC8M16A2TG-75",
+                .rows           = 12,
+                .tck            = 8,
+                .trcd           = 20,
+                .trp            = 20,
+                .twr            = 8,
+                .refresh        = 64000,
+                .cas_latency    = 3,
         },
 };
 
@@ -180,11 +185,13 @@ sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
                 sd->mdrefr |= MDREFR_K1DB2;
 
         /* initial number of '1's in MDCAS + 1 */
-        set_mdcas(sd->mdcas, sd_khz >= 62000, ns_to_cycles(sdram->trcd, mem_khz));
+        set_mdcas(sd->mdcas, sd_khz >= 62000,
+                ns_to_cycles(sdram->trcd, mem_khz));
 
 #ifdef DEBUG
-        printk("MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
-                sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1], sd->mdcas[2]);
+        printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
+                sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
+                sd->mdcas[2]);
 #endif
 }
 
@@ -213,7 +220,7 @@ sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
 
 #ifdef DEBUG
         mdelay(250);
-        printk("new dri value = %d\n", dri);
+        printk(KERN_DEBUG "new dri value = %d\n", dri);
 #endif
 
         sdram_set_refresh(dri);
@@ -232,7 +239,7 @@ static int sa1110_target(struct cpufreq_policy *policy,
         unsigned long flags;
         unsigned int ppcr, unused;
 
-        switch(relation){
+        switch (relation) {
         case CPUFREQ_RELATION_L:
                 ppcr = sa11x0_freq_to_ppcr(target_freq);
                 if (sa11x0_ppcr_to_freq(ppcr) > policy->max)
@@ -280,11 +287,10 @@ static int sa1110_target(struct cpufreq_policy *policy,
          * We wait 20ms to be safe.
          */
         sdram_set_refresh(2);
-        if (!irqs_disabled()) {
+        if (!irqs_disabled())
                 msleep(20);
-        } else {
+        else
                 mdelay(20);
-        }
 
         /*
          * Reprogram the DRAM timings with interrupts disabled, and
@@ -295,7 +301,7 @@ static int sa1110_target(struct cpufreq_policy *policy,
         local_irq_save(flags);
         asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
         udelay(10);
-        __asm__ __volatile__("                                  \n\
+        __asm__ __volatile__("\n\
                 b       2f                                      \n\
                 .align  5                                       \n\
 1:              str     %3, [%1, #0]            @ MDCNFG        \n\
@@ -336,7 +342,9 @@ static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
         return 0;
 }
 
-static struct cpufreq_driver sa1110_driver = {
+/* sa1110_driver needs __refdata because it must remain after init registers
+ * it with cpufreq_register_driver() */
+static struct cpufreq_driver sa1110_driver __refdata = {
         .flags          = CPUFREQ_STICKY,
         .verify         = sa11x0_verify_speed,
         .target         = sa1110_target,
@@ -349,7 +357,8 @@ static struct sdram_params *sa1110_find_sdram(const char *name)
 {
         struct sdram_params *sdram;
 
-        for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl); sdram++)
+        for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
+             sdram++)
                 if (strcmp(name, sdram->name) == 0)
                         return sdram;
 
@@ -369,14 +378,14 @@ static int __init sa1110_clk_init(void)
         if (!name[0]) {
                 if (machine_is_assabet())
                         name = "TC59SM716-CL3";
-
                 if (machine_is_pt_system3())
                         name = "K4S641632D";
-
                 if (machine_is_h3100())
                         name = "KM416S4030CT";
                 if (machine_is_jornada720())
-                        name = "K4S281632B-1H";
+                        name = "K4S281632B-1H";
+                if (machine_is_nanoengine())
+                        name = "MT48LC8M16A2TG-75";
         }
 
         sdram = sa1110_find_sdram(name);
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 3c1fcd696714..59d14f0fdcf8 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -16,9 +16,7 @@
 #include <linux/pm.h>
 #include <linux/cpufreq.h>
 #include <linux/ioport.h>
-#include <linux/sched.h>        /* just for sched_clock() - funny that */
 #include <linux/platform_device.h>
-#include <linux/cnt32_to_63.h>
 
 #include <asm/div64.h>
 #include <mach/hardware.h>
@@ -110,27 +108,6 @@ unsigned int sa11x0_getspeed(unsigned int cpu)
 }
 
 /*
- * This is the SA11x0 sched_clock implementation.  This has
- * a resolution of 271ns, and a maximum value of 32025597s (370 days).
- *
- * The return value is guaranteed to be monotonic in that range as
- * long as there is always less than 582 seconds between successive
- * calls to this function.
- *
- *  ( * 1E9 / 3686400 => * 78125 / 288)
- */
-unsigned long long sched_clock(void)
-{
-        unsigned long long v = cnt32_to_63(OSCR);
-
-        /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
-        v *= 78125<<1;
-        do_div(v, 288<<1);
-
-        return v;
-}
-
-/*
  * Default power-off for SA1100
  */
 static void sa1100_power_off(void)
@@ -163,10 +140,15 @@ static void sa11x0_register_device(struct platform_device *dev, void *data)
 
 static struct resource sa11x0udc_resources[] = {
         [0] = {
-                .start  = 0x80000000,
-                .end    = 0x8000ffff,
+                .start  = __PREG(Ser0UDCCR),
+                .end    = __PREG(Ser0UDCCR) + 0xffff,
                 .flags  = IORESOURCE_MEM,
         },
+        [1] = {
+                .start  = IRQ_Ser0UDC,
+                .end    = IRQ_Ser0UDC,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
@@ -184,10 +166,15 @@ static struct platform_device sa11x0udc_device = {
 
 static struct resource sa11x0uart1_resources[] = {
         [0] = {
-                .start  = 0x80010000,
-                .end    = 0x8001ffff,
+                .start  = __PREG(Ser1UTCR0),
+                .end    = __PREG(Ser1UTCR0) + 0xffff,
                 .flags  = IORESOURCE_MEM,
         },
+        [1] = {
+                .start  = IRQ_Ser1UART,
+                .end    = IRQ_Ser1UART,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device sa11x0uart1_device = {
@@ -199,10 +186,15 @@ static struct platform_device sa11x0uart1_device = {
 
 static struct resource sa11x0uart3_resources[] = {
         [0] = {
-                .start  = 0x80050000,
-                .end    = 0x8005ffff,
+                .start  = __PREG(Ser3UTCR0),
+                .end    = __PREG(Ser3UTCR0) + 0xffff,
                 .flags  = IORESOURCE_MEM,
         },
+        [1] = {
+                .start  = IRQ_Ser3UART,
+                .end    = IRQ_Ser3UART,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static struct platform_device sa11x0uart3_device = {
@@ -214,10 +206,15 @@ static struct platform_device sa11x0uart3_device = {
 
 static struct resource sa11x0mcp_resources[] = {
         [0] = {
-                .start  = 0x80060000,
-                .end    = 0x8006ffff,
+                .start  = __PREG(Ser4MCCR0),
+                .end    = __PREG(Ser4MCCR0) + 0xffff,
                 .flags  = IORESOURCE_MEM,
         },
+        [1] = {
+                .start  = IRQ_Ser4MCP,
+                .end    = IRQ_Ser4MCP,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
@@ -244,6 +241,11 @@ static struct resource sa11x0ssp_resources[] = {
                 .end    = 0x8007ffff,
                 .flags  = IORESOURCE_MEM,
         },
+        [1] = {
+                .start  = IRQ_Ser4SSP,
+                .end    = IRQ_Ser4SSP,
+                .flags  = IORESOURCE_IRQ,
+        },
 };
 
 static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 99f5856d8de4..967ae7684390 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -76,4 +76,12 @@ static inline unsigned long get_clock_tick_rate(void)
 #include "SA-1101.h"
 #endif
 
+#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI)
+#define PCIBIOS_MIN_IO          0
+#define PCIBIOS_MIN_MEM         0
+#define pcibios_assign_all_busses()     1
+#define HAVE_ARCH_PCI_SET_DMA_MASK      1
+#endif
+
+
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
new file mode 100644
index 000000000000..14f8382d0665
--- /dev/null
+++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-sa1100/include/mach/nanoengine.h
+ *
+ * This file contains the hardware specific definitions for nanoEngine.
+ * Only include this file from SA1100-specific files.
+ *
+ * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_ARCH_NANOENGINE_H
+#define __ASM_ARCH_NANOENGINE_H
+
+#include <mach/irqs.h>
+
+#define GPIO_PC_READY0  GPIO_GPIO(11) /* ready for socket 0 (active high)*/
+#define GPIO_PC_READY1  GPIO_GPIO(12) /* ready for socket 1 (active high) */
+#define GPIO_PC_CD0     GPIO_GPIO(13) /* detect for socket 0 (active low) */
+#define GPIO_PC_CD1     GPIO_GPIO(14) /* detect for socket 1 (active low) */
+#define GPIO_PC_RESET0  GPIO_GPIO(15) /* reset socket 0 */
+#define GPIO_PC_RESET1  GPIO_GPIO(16) /* reset socket 1 */
+
+#define NANOENGINE_IRQ_GPIO_PCI         IRQ_GPIO0
+#define NANOENGINE_IRQ_GPIO_PC_READY0   IRQ_GPIO11
+#define NANOENGINE_IRQ_GPIO_PC_READY1   IRQ_GPIO12
+#define NANOENGINE_IRQ_GPIO_PC_CD0      IRQ_GPIO13
+#define NANOENGINE_IRQ_GPIO_PC_CD1      IRQ_GPIO14
+
+/*
+ * nanoEngine Memory Map:
+ *
+ * 0000.0000 - 003F.0000 -   4 MB Flash
+ * C000.0000 - C1FF.FFFF -  32 MB SDRAM
+ * 1860.0000 - 186F.FFFF -   1 MB Internal PCI Memory Read/Write
+ * 18A1.0000 - 18A1.FFFF -  64 KB Internal PCI Config Space
+ * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
+ * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
+ *
+ */
+
+#define NANO_PCI_MEM_RW_PHYS            0x18600000
+#define NANO_PCI_MEM_RW_VIRT            0xf1000000
+#define NANO_PCI_MEM_RW_SIZE            SZ_1M
+#define NANO_PCI_CONFIG_SPACE_PHYS      0x18A10000
+#define NANO_PCI_CONFIG_SPACE_VIRT      0xf2000000
+#define NANO_PCI_CONFIG_SPACE_SIZE      SZ_64K
+
+#endif
+
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
new file mode 100644
index 000000000000..72087f0658b7
--- /dev/null
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -0,0 +1,119 @@
+/*
+ * linux/arch/arm/mach-sa1100/nanoengine.c
+ *
+ * Bright Star Engineering's nanoEngine board init code.
+ *
+ * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/root_dev.h>
+
+#include <asm/mach-types.h>
+#include <asm/setup.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/map.h>
+#include <asm/mach/serial_sa1100.h>
+
+#include <mach/hardware.h>
+#include <mach/nanoengine.h>
+
+#include "generic.h"
+
+/* Flash bank 0 */
+static struct mtd_partition nanoengine_partitions[] = {
+        {
+                .name   = "nanoEngine boot firmware and parameter table",
+                .size           = 0x00010000,  /* 32K */
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "kernel/initrd reserved",
+                .size           = 0x002f0000,
+                .offset         = 0x00010000,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "experimental filesystem allocation",
+                .size           = 0x00100000,
+                .offset         = 0x00300000,
+                .mask_flags     = MTD_WRITEABLE,
+        }
+};
+
+static struct flash_platform_data nanoengine_flash_data = {
+        .map_name       = "jedec_probe",
+        .parts          = nanoengine_partitions,
+        .nr_parts       = ARRAY_SIZE(nanoengine_partitions),
+};
+
+static struct resource nanoengine_flash_resources[] = {
+        {
+                .start  = SA1100_CS0_PHYS,
+                .end    = SA1100_CS0_PHYS + SZ_32M - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = SA1100_CS1_PHYS,
+                .end    = SA1100_CS1_PHYS + SZ_32M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct map_desc nanoengine_io_desc[] __initdata = {
+        {
+                /* System Registers */
+                .virtual        = 0xf0000000,
+                .pfn            = __phys_to_pfn(0x10000000),
+                .length         = 0x00100000,
+                .type           = MT_DEVICE
+        }, {
+                /* Internal PCI Memory Read/Write */
+                .virtual        = NANO_PCI_MEM_RW_VIRT,
+                .pfn            = __phys_to_pfn(NANO_PCI_MEM_RW_PHYS),
+                .length         = NANO_PCI_MEM_RW_SIZE,
+                .type           = MT_DEVICE
+        }, {
+                /* Internal PCI Config Space */
+                .virtual        = NANO_PCI_CONFIG_SPACE_VIRT,
+                .pfn            = __phys_to_pfn(NANO_PCI_CONFIG_SPACE_PHYS),
+                .length         = NANO_PCI_CONFIG_SPACE_SIZE,
+                .type           = MT_DEVICE
+        }
+};
+
+static void __init nanoengine_map_io(void)
+{
+        sa1100_map_io();
+        iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));
+
+        sa1100_register_uart(0, 1);
+        sa1100_register_uart(1, 2);
+        sa1100_register_uart(2, 3);
+        Ser1SDCR0 |= SDCR0_UART;
+        /* disable IRDA -- UART2 is used as a normal serial port */
+        Ser2UTCR4 = 0;
+        Ser2HSCR0 = 0;
+}
+
+static void __init nanoengine_init(void)
+{
+        sa11x0_register_mtd(&nanoengine_flash_data, nanoengine_flash_resources,
+                ARRAY_SIZE(nanoengine_flash_resources));
+}
+
+MACHINE_START(NANOENGINE, "BSE nanoEngine")
+        .boot_params    = 0xc0000000,
+        .map_io         = nanoengine_map_io,
+        .init_irq       = sa1100_init_irq,
+        .timer          = &sa1100_timer,
+        .init_machine   = nanoengine_init,
+MACHINE_END
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
new file mode 100644
index 000000000000..fba7a913f12b
--- /dev/null
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -0,0 +1,284 @@
+/*
+ * linux/arch/arm/mach-sa1100/pci-nanoengine.c
+ *
+ * PCI functions for BSE nanoEngine PCI
+ *
+ * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/pci.h>
+#include <linux/spinlock.h>
+
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+
+#include <mach/nanoengine.h>
+
+static DEFINE_SPINLOCK(nano_lock);
+
+static int nanoengine_get_pci_address(struct pci_bus *bus,
+        unsigned int devfn, int where, unsigned long *address)
+{
+        int ret = PCIBIOS_DEVICE_NOT_FOUND;
+        unsigned int busnr = bus->number;
+
+        *address = NANO_PCI_CONFIG_SPACE_VIRT +
+                ((bus->number << 16) | (devfn << 8) | (where & ~3));
+
+        ret = (busnr > 255 || devfn > 255 || where > 255) ?
+                PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+
+        return ret;
+}
+
+static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+        int size, u32 *val)
+{
+        int ret;
+        unsigned long address;
+        unsigned long flags;
+        u32 v;
+
+        /* nanoEngine PCI bridge does not return -1 for a non-existing
+         * device. We must fake the answer. We know that the only valid
+         * device is device zero at bus 0, which is the network chip. */
+        if (bus->number != 0 || (devfn >> 3) != 0) {
+                v = -1;
+                nanoengine_get_pci_address(bus, devfn, where, &address);
+                goto exit_function;
+        }
+
+        spin_lock_irqsave(&nano_lock, flags);
+
+        ret = nanoengine_get_pci_address(bus, devfn, where, &address);
+        if (ret != PCIBIOS_SUCCESSFUL)
+                return ret;
+        v = __raw_readl(address);
+
+        spin_unlock_irqrestore(&nano_lock, flags);
+
+        v >>= ((where & 3) * 8);
+        v &= (unsigned long)(-1) >> ((4 - size) * 8);
+
+exit_function:
+        *val = v;
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+        int size, u32 val)
+{
+        int ret;
+        unsigned long address;
+        unsigned long flags;
+        unsigned shift;
+        u32 v;
+
+        shift = (where & 3) * 8;
+
+        spin_lock_irqsave(&nano_lock, flags);
+
+        ret = nanoengine_get_pci_address(bus, devfn, where, &address);
+        if (ret != PCIBIOS_SUCCESSFUL)
+                return ret;
+        v = __raw_readl(address);
+        switch (size) {
+        case 1:
+                v &= ~(0xFF << shift);
+                v |= val << shift;
+                break;
+        case 2:
+                v &= ~(0xFFFF << shift);
+                v |= val << shift;
+                break;
+        case 4:
+                v = val;
+                break;
+        }
+        __raw_writel(v, address);
+
+        spin_unlock_irqrestore(&nano_lock, flags);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops pci_nano_ops = {
+        .read   = nanoengine_read_config,
+        .write  = nanoengine_write_config,
+};
+
+static int __init pci_nanoengine_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return NANOENGINE_IRQ_GPIO_PCI;
+}
+
+struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        return pci_scan_bus(sys->busnr, &pci_nano_ops, sys);
+}
+
+static struct resource pci_io_ports = {
+        .name   = "PCI IO",
+        .start  = 0x400,
+        .end    = 0x7FF,
+        .flags  = IORESOURCE_IO,
+};
+
+static struct resource pci_non_prefetchable_memory = {
+        .name   = "PCI non-prefetchable",
+        .start  = NANO_PCI_MEM_RW_PHYS,
+        /* nanoEngine documentation says there is a 1 Megabyte window here,
+         * but PCI reports just 128 + 8 kbytes. */
+        .end    = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
+/*      .end    = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
+        .flags  = IORESOURCE_MEM,
+};
+
+/*
+ * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
+ * overlaps with previously defined memory.
+ *
+ * Here is what happens:
+ *
+# dmesg
+...
+pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
+pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
+pci 0000:00:00.0: reg 14: [io  0x0000-0x003f]
+pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
+pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
+pci 0000:00:00.0: supports D1 D2
+pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
+pci 0000:00:00.0: PME# disabled
+PCI: bus0: Fast back to back transfers enabled
+pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000)
+pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
+pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
+pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
+pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
+pci 0000:00:00.0: BAR 1: assigned [io  0x0400-0x043f]
+pci 0000:00:00.0: BAR 1: set to [io  0x0400-0x043f] (PCI address [0x0-0x3f])
+ *
+ * On the other hand, if we do not request the prefetchable memory resource,
+ * linux will alloc it first and the two non-prefetchable memory areas that
+ * are our real interest will not be mapped. So we choose to map it to an
+ * unused area. It gets recognized as expansion ROM, but becomes disabled.
+ *
+ * Here is what happens then:
+ *
+# dmesg
+...
+pci 0000:00:00.0: [8086:1209] type 0 class 0x000200
+pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
+pci 0000:00:00.0: reg 14: [io  0x0000-0x003f]
+pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
+pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
+pci 0000:00:00.0: supports D1 D2
+pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
+pci 0000:00:00.0: PME# disabled
+PCI: bus0: Fast back to back transfers enabled
+pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
+pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
+pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
+pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
+pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
+pci 0000:00:00.0: BAR 1: assigned [io  0x0400-0x043f]
+pci 0000:00:00.0: BAR 1: set to [io  0x0400-0x043f] (PCI address [0x0-0x3f])
+
+# lspci -vv -s 0000:00:00.0
+00:00.0 Class 0200: Device 8086:1209 (rev 09)
+        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+        Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx-
+        Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes
+        Interrupt: pin A routed to IRQ 0
+        Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
+        Region 1: I/O ports at 0400 [size=64]
+        Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K]
+        [virtual] Expansion ROM at 78000000 [disabled] [size=1M]
+        Capabilities: [dc] Power Management version 2
+                Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
+                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
+        Kernel driver in use: e100
+        Kernel modules: e100
+ *
+ */
+static struct resource pci_prefetchable_memory = {
+        .name   = "PCI prefetchable",
+        .start  = 0x78000000,
+        .end    = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
+        .flags  = IORESOURCE_MEM  | IORESOURCE_PREFETCH,
+};
+
+static int __init pci_nanoengine_setup_resources(struct resource **resource)
+{
+        if (request_resource(&ioport_resource, &pci_io_ports)) {
+                printk(KERN_ERR "PCI: unable to allocate io port region\n");
+                return -EBUSY;
+        }
+        if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) {
+                release_resource(&pci_io_ports);
+                printk(KERN_ERR "PCI: unable to allocate non prefetchable\n");
+                return -EBUSY;
+        }
+        if (request_resource(&iomem_resource, &pci_prefetchable_memory)) {
+                release_resource(&pci_io_ports);
+                release_resource(&pci_non_prefetchable_memory);
+                printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
+                return -EBUSY;
+        }
+        resource[0] = &pci_io_ports;
+        resource[1] = &pci_non_prefetchable_memory;
+        resource[2] = &pci_prefetchable_memory;
+
+        return 1;
+}
+
+int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
+{
+        int ret = 0;
+
+        if (nr == 0) {
+                sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
+                sys->io_offset = 0x400;
+                ret = pci_nanoengine_setup_resources(sys->resource);
+                /* Enable alternate memory bus master mode, see
+                 * "Intel StrongARM SA1110 Developer's Manual",
+                 * section 10.8, "Alternate Memory Bus Master Mode". */
+                GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
+                GAFR |= GPIO_MBGNT | GPIO_MBREQ;
+                TUCR |= TUCR_MBGPIO;
+        }
+
+        return ret;
+}
+
+static struct hw_pci nanoengine_pci __initdata = {
+        .map_irq                = pci_nanoengine_map_irq,
+        .nr_controllers         = 1,
+        .scan                   = pci_nanoengine_scan_bus,
+        .setup                  = pci_nanoengine_setup,
+};
+
+static int __init nanoengine_pci_init(void)
+{
+        if (machine_is_nanoengine())
+                pci_common_init(&nanoengine_pci);
+        return 0;
+}
+
+subsys_initcall(nanoengine_pci_init);
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 27692d0ffbe8..cfb76077bd25 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -166,9 +166,6 @@ static void __init simpad_map_io(void)
         PCFR = 0;
         PSDR = 0;
 
-        sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
-                              ARRAY_SIZE(simpad_flash_resources));
-        sa11x0_register_mcp(&simpad_mcp_data);
 }
 
 static void simpad_power_off(void)
@@ -216,6 +213,10 @@ static int __init simpad_init(void)
 
         pm_power_off = simpad_power_off;
 
+        sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
+                              ARRAY_SIZE(simpad_flash_resources));
+        sa11x0_register_mcp(&simpad_mcp_data);
+
         ret = platform_add_devices(devices, ARRAY_SIZE(devices));
         if(ret)
                 printk(KERN_WARNING "simpad: Unable to register mq200 framebuffer device");
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 74b6e0e570b6..ae4f3d80416f 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -12,12 +12,39 @@
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/sched.h>        /* just for sched_clock() - funny that */
 #include <linux/timex.h>
 #include <linux/clockchips.h>
 
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 #include <mach/hardware.h>
 
+/*
+ * This is the SA11x0 sched_clock implementation.
+ */
+static DEFINE_CLOCK_DATA(cd);
+
+/*
+ * Constants generated by clocks_calc_mult_shift(m, s, 3.6864MHz,
+ * NSEC_PER_SEC, 60).
+ * This gives a resolution of about 271ns and a wrap period of about 19min.
+ */
+#define SC_MULT         2275555556u
+#define SC_SHIFT        23
+
+unsigned long long notrace sched_clock(void)
+{
+        u32 cyc = OSCR;
+        return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
+}
+
+static void notrace sa1100_update_sched_clock(void)
+{
+        u32 cyc = OSCR;
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+
 #define MIN_OSCR_DELTA 2
 
 static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
@@ -81,7 +108,6 @@ static struct clocksource cksrc_sa1100_oscr = {
         .rating         = 200,
         .read           = sa1100_read_oscr,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -97,6 +123,9 @@ static void __init sa1100_timer_init(void)
         OIER = 0;               /* disable any timer interrupts */
         OSSR = 0xf;             /* clear status on all timers */
 
+        init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32,
+                               3686400, SC_MULT, SC_SHIFT);
+
         ckevt_sa1100_osmr0.mult =
                 div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift);
         ckevt_sa1100_osmr0.max_delta_ns =
@@ -105,12 +134,9 @@ static void __init sa1100_timer_init(void)
                 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
         ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
 
-        cksrc_sa1100_oscr.mult =
-                clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_sa1100_oscr.shift);
-
         setup_irq(IRQ_OST0, &sa1100_timer_irq);
 
-        clocksource_register(&cksrc_sa1100_oscr);
+        clocksource_register_hz(&cksrc_sa1100_oscr, CLOCK_TICK_RATE);
         clockevents_register_device(&ckevt_sa1100_osmr0);
 }
 
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 51dcd59eda6a..4d1b4c5c9389 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -5,26 +5,27 @@ comment "SH-Mobile System Type"
 config ARCH_SH7367
         bool "SH-Mobile G3 (SH7367)"
         select CPU_V6
-        select HAVE_CLK
-        select COMMON_CLKDEV
         select SH_CLK_CPG
-        select GENERIC_CLOCKEVENTS
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config ARCH_SH7377
         bool "SH-Mobile G4 (SH7377)"
         select CPU_V7
-        select HAVE_CLK
-        select COMMON_CLKDEV
         select SH_CLK_CPG
-        select GENERIC_CLOCKEVENTS
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config ARCH_SH7372
         bool "SH-Mobile AP4 (SH7372)"
         select CPU_V7
-        select HAVE_CLK
-        select COMMON_CLKDEV
         select SH_CLK_CPG
-        select GENERIC_CLOCKEVENTS
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+
+config ARCH_SH73A0
+        bool "SH-Mobile AG5 (R8A73A00)"
+        select CPU_V7
+        select SH_CLK_CPG
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_GIC
 
 comment "SH-Mobile Board Type"
 
@@ -57,6 +58,15 @@ config AP4EVB_WVGA
 
 endchoice
 
+config MACH_AG5EVM
+        bool "AG5EVM board"
+        depends on ARCH_SH73A0
+
+config MACH_MACKEREL
+        bool "mackerel board"
+        depends on ARCH_SH7372
+        select ARCH_REQUIRE_GPIOLIB
+
 comment "SH-Mobile System Configuration"
 
 menu "Memory configuration"
@@ -64,8 +74,8 @@ menu "Memory configuration"
 config MEMORY_START
         hex "Physical memory start address"
         default "0x50000000" if MACH_G3EVM
-        default "0x40000000" if MACH_G4EVM
-        default "0x40000000" if MACH_AP4EVB
+        default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
+                                MACH_MACKEREL
         default "0x00000000"
         ---help---
           Tweak this only when porting to a new machine which does not
@@ -76,7 +86,8 @@ config MEMORY_SIZE
         hex "Physical memory size"
         default "0x08000000" if MACH_G3EVM
         default "0x08000000" if MACH_G4EVM
-        default "0x10000000" if MACH_AP4EVB
+        default "0x20000000" if MACH_AG5EVM
+        default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
         default "0x04000000"
         help
           This sets the default memory size assumed by your kernel. It can
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index ae416fe7daf2..e2507f66f9d5 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -9,14 +9,34 @@ obj-y				:= timer.o console.o clock.o pm_runtime.o
 obj-$(CONFIG_ARCH_SH7367)       += setup-sh7367.o clock-sh7367.o intc-sh7367.o
 obj-$(CONFIG_ARCH_SH7377)       += setup-sh7377.o clock-sh7377.o intc-sh7377.o
 obj-$(CONFIG_ARCH_SH7372)       += setup-sh7372.o clock-sh7372.o intc-sh7372.o
+obj-$(CONFIG_ARCH_SH73A0)       += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
+
+# SMP objects
+smp-y                           := platsmp.o headsmp.o
+smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+smp-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
+smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o
 
 # Pinmux setup
-pfc-$(CONFIG_ARCH_SH7367)       := pfc-sh7367.o
-pfc-$(CONFIG_ARCH_SH7377)       := pfc-sh7377.o
-pfc-$(CONFIG_ARCH_SH7372)       := pfc-sh7372.o
-obj-$(CONFIG_GENERIC_GPIO)      += $(pfc-y)
+pfc-y                           :=
+pfc-$(CONFIG_ARCH_SH7367)       += pfc-sh7367.o
+pfc-$(CONFIG_ARCH_SH7377)       += pfc-sh7377.o
+pfc-$(CONFIG_ARCH_SH7372)       += pfc-sh7372.o
+pfc-$(CONFIG_ARCH_SH73A0)       += pfc-sh73a0.o
+
+# IRQ objects
+obj-$(CONFIG_ARCH_SH7367)       += entry-intc.o
+obj-$(CONFIG_ARCH_SH7377)       += entry-intc.o
+obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
+obj-$(CONFIG_ARCH_SH73A0)       += entry-gic.o
 
 # Board objects
 obj-$(CONFIG_MACH_G3EVM)        += board-g3evm.o
 obj-$(CONFIG_MACH_G4EVM)        += board-g4evm.o
 obj-$(CONFIG_MACH_AP4EVB)       += board-ap4evb.o
+obj-$(CONFIG_MACH_AG5EVM)       += board-ag5evm.o
+obj-$(CONFIG_MACH_MACKEREL)     += board-mackerel.o
+
+# Framework support
+obj-$(CONFIG_SMP)               += $(smp-y)
+obj-$(CONFIG_GENERIC_GPIO)      += $(pfc-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
new file mode 100644
index 000000000000..c18a740a4159
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -0,0 +1,315 @@
+/*
+ * arch/arm/mach-shmobile/board-ag5evm.c
+ *
+ * Copyright (C) 2010  Takashi Yoshii <yoshii.takashi.zj@renesas.com>
+ * Copyright (C) 2009  Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial_sci.h>
+#include <linux/smsc911x.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/input/sh_keysc.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+
+#include <sound/sh_fsi.h>
+
+#include <mach/hardware.h>
+#include <mach/sh73a0.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/traps.h>
+
+static struct resource smsc9220_resources[] = {
+        [0] = {
+                .start          = 0x14000000,
+                .end            = 0x14000000 + SZ_64K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = gic_spi(33), /* PINT1 */
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct smsc911x_platform_config smsc9220_platdata = {
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct platform_device eth_device = {
+        .name           = "smsc911x",
+        .id             = 0,
+        .dev  = {
+                .platform_data = &smsc9220_platdata,
+        },
+        .resource       = smsc9220_resources,
+        .num_resources  = ARRAY_SIZE(smsc9220_resources),
+};
+
+static struct sh_keysc_info keysc_platdata = {
+        .mode           = SH_KEYSC_MODE_6,
+        .scan_timing    = 3,
+        .delay          = 100,
+        .keycodes       = {
+                KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G,
+                KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N,
+                KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U,
+                KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP,
+                KEY_SPACE, KEY_9, KEY_6, KEY_3, KEY_WAKEUP, KEY_RIGHT, \
+                KEY_COFFEE,
+                KEY_0, KEY_8, KEY_5, KEY_2, KEY_DOWN, KEY_ENTER, KEY_UP,
+                KEY_KPASTERISK, KEY_7, KEY_4, KEY_1, KEY_STOP, KEY_LEFT, \
+                KEY_COMPUTER,
+        },
+};
+
+static struct resource keysc_resources[] = {
+        [0] = {
+                .name   = "KEYSC",
+                .start  = 0xe61b0000,
+                .end    = 0xe61b0098 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(71),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device keysc_device = {
+        .name           = "sh_keysc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(keysc_resources),
+        .resource       = keysc_resources,
+        .dev            = {
+                .platform_data  = &keysc_platdata,
+        },
+};
+
+/* FSI A */
+static struct sh_fsi_platform_info fsi_info = {
+        .porta_flags = SH_FSI_OUT_SLAVE_MODE    |
+                       SH_FSI_IN_SLAVE_MODE     |
+                       SH_FSI_OFMT(I2S)         |
+                       SH_FSI_IFMT(I2S),
+};
+
+static struct resource fsi_resources[] = {
+        [0] = {
+                .name   = "FSI",
+                .start  = 0xEC230000,
+                .end    = 0xEC230400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(146),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device fsi_device = {
+        .name           = "sh_fsi2",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(fsi_resources),
+        .resource       = fsi_resources,
+        .dev    = {
+                .platform_data  = &fsi_info,
+        },
+};
+
+static struct resource sh_mmcif_resources[] = {
+        [0] = {
+                .name   = "MMCIF",
+                .start  = 0xe6bd0000,
+                .end    = 0xe6bd00ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(141),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = gic_spi(140),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_mmcif_plat_data sh_mmcif_platdata = {
+        .sup_pclk       = 0,
+        .ocr            = MMC_VDD_165_195,
+        .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+};
+
+static struct platform_device mmc_device = {
+        .name           = "sh_mmcif",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &sh_mmcif_platdata,
+        },
+        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+        .resource       = sh_mmcif_resources,
+};
+
+static struct platform_device *ag5evm_devices[] __initdata = {
+        &eth_device,
+        &keysc_device,
+        &fsi_device,
+        &mmc_device,
+};
+
+static struct map_desc ag5evm_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+static void __init ag5evm_map_io(void)
+{
+        iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
+
+        /* setup early devices and console here as well */
+        sh73a0_add_early_devices();
+        shmobile_setup_console();
+}
+
+#define PINTC_ADDR      0xe6900000
+#define PINTER0A        (PINTC_ADDR + 0xa0)
+#define PINTCR0A        (PINTC_ADDR + 0xb0)
+
+void __init ag5evm_init_irq(void)
+{
+        sh73a0_init_irq();
+
+        /* setup PINT: enable PINTA2 as active low */
+        __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A);
+        __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
+}
+
+static void __init ag5evm_init(void)
+{
+        sh73a0_pinmux_init();
+
+        /* enable SCIFA2 */
+        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
+        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
+        gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
+        gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
+
+        /* enable KEYSC */
+        gpio_request(GPIO_FN_KEYIN0_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN1_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN2_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN3_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN4_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN5_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN6_PU, NULL);
+        gpio_request(GPIO_FN_KEYIN7_PU, NULL);
+        gpio_request(GPIO_FN_KEYOUT0, NULL);
+        gpio_request(GPIO_FN_KEYOUT1, NULL);
+        gpio_request(GPIO_FN_KEYOUT2, NULL);
+        gpio_request(GPIO_FN_KEYOUT3, NULL);
+        gpio_request(GPIO_FN_KEYOUT4, NULL);
+        gpio_request(GPIO_FN_KEYOUT5, NULL);
+        gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
+        gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
+        gpio_request(GPIO_FN_KEYOUT8, NULL);
+        gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
+
+        /* enable I2C channel 2 and 3 */
+        gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
+        gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
+        gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
+        gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
+
+        /* enable MMCIF */
+        gpio_request(GPIO_FN_MMCCLK0, NULL);
+        gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
+        gpio_request(GPIO_FN_MMCD0_0, NULL);
+        gpio_request(GPIO_FN_MMCD0_1, NULL);
+        gpio_request(GPIO_FN_MMCD0_2, NULL);
+        gpio_request(GPIO_FN_MMCD0_3, NULL);
+        gpio_request(GPIO_FN_MMCD0_4, NULL);
+        gpio_request(GPIO_FN_MMCD0_5, NULL);
+        gpio_request(GPIO_FN_MMCD0_6, NULL);
+        gpio_request(GPIO_FN_MMCD0_7, NULL);
+        gpio_request(GPIO_PORT208, NULL); /* Reset */
+        gpio_direction_output(GPIO_PORT208, 1);
+
+        /* enable SMSC911X */
+        gpio_request(GPIO_PORT144, NULL); /* PINTA2 */
+        gpio_direction_input(GPIO_PORT144);
+        gpio_request(GPIO_PORT145, NULL); /* RESET */
+        gpio_direction_output(GPIO_PORT145, 1);
+
+        /* FSI A */
+        gpio_request(GPIO_FN_FSIACK, NULL);
+        gpio_request(GPIO_FN_FSIAILR, NULL);
+        gpio_request(GPIO_FN_FSIAIBT, NULL);
+        gpio_request(GPIO_FN_FSIAISLD, NULL);
+        gpio_request(GPIO_FN_FSIAOSLD, NULL);
+
+#ifdef CONFIG_CACHE_L2X0
+        /* Shared attribute override enable, 64K*8way */
+        l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
+#endif
+        sh73a0_add_standard_devices();
+        platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
+}
+
+static void __init ag5evm_timer_init(void)
+{
+        sh73a0_clock_init();
+        shmobile_timer.init();
+        return;
+}
+
+struct sys_timer ag5evm_timer = {
+        .init   = ag5evm_timer_init,
+};
+
+MACHINE_START(AG5EVM, "ag5evm")
+        .map_io         = ag5evm_map_io,
+        .init_irq       = ag5evm_init_irq,
+        .handle_irq     = shmobile_handle_irq_gic,
+        .init_machine   = ag5evm_init,
+        .timer          = &ag5evm_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index d440e5f456ad..cd79d7c1ba0d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -61,6 +61,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/setup.h>
 
 /*
  * Address      Interface               BusWidth        note
@@ -272,6 +273,15 @@ static struct resource sh_mmcif_resources[] = {
         },
 };
 
+static struct sh_mmcif_dma sh_mmcif_dma = {
+        .chan_priv_rx   = {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+        },
+        .chan_priv_tx   = {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+        },
+};
+
 static struct sh_mmcif_plat_data sh_mmcif_plat = {
         .sup_pclk       = 0,
         .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -279,6 +289,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
                           MMC_CAP_8_BIT_DATA |
                           MMC_CAP_NEEDS_POLL,
         .get_cd         = slot_cn7_get_cd,
+        .dma            = &sh_mmcif_dma,
 };
 
 static struct platform_device sh_mmcif_device = {
@@ -501,7 +512,12 @@ static struct platform_device keysc_device = {
 static struct resource mipidsi0_resources[] = {
         [0] = {
                 .start  = 0xffc60000,
-                .end    = 0xffc68fff,
+                .end    = 0xffc63073,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xffc68000,
+                .end    = 0xffc680ef,
                 .flags  = IORESOURCE_MEM,
         },
 };
@@ -509,6 +525,7 @@ static struct resource mipidsi0_resources[] = {
 static struct sh_mipi_dsi_info mipidsi0_info = {
         .data_format    = MIPI_RGB888,
         .lcd_chan       = &lcdc_info.ch[0],
+        .vsynw_offset   = 17,
 };
 
 static struct platform_device mipidsi0_device = {
@@ -521,44 +538,6 @@ static struct platform_device mipidsi0_device = {
         },
 };
 
-/* This function will disappear when we switch to (runtime) PM */
-static int __init ap4evb_init_display_clk(void)
-{
-        struct clk *lcdc_clk;
-        struct clk *dsitx_clk;
-        int ret;
-
-        lcdc_clk = clk_get(&lcdc_device.dev, "sh_mobile_lcdc_fb.0");
-        if (IS_ERR(lcdc_clk))
-                return PTR_ERR(lcdc_clk);
-
-        dsitx_clk = clk_get(&mipidsi0_device.dev, "sh-mipi-dsi.0");
-        if (IS_ERR(dsitx_clk)) {
-                ret = PTR_ERR(dsitx_clk);
-                goto eclkdsitxget;
-        }
-
-        ret = clk_enable(lcdc_clk);
-        if (ret < 0)
-                goto eclklcdcon;
-
-        ret = clk_enable(dsitx_clk);
-        if (ret < 0)
-                goto eclkdsitxon;
-
-        return 0;
-
-eclkdsitxon:
-        clk_disable(lcdc_clk);
-eclklcdcon:
-        clk_put(dsitx_clk);
-eclkdsitxget:
-        clk_put(lcdc_clk);
-
-        return ret;
-}
-device_initcall(ap4evb_init_display_clk);
-
 static struct platform_device *qhd_devices[] __initdata = {
         &mipidsi0_device,
         &keysc_device,
@@ -664,9 +643,8 @@ static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
                 return -EIO;
 
         ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
-        clk_put(fsib_clk);
         if (ret < 0)
-                return ret;
+                goto fsi_set_rate_end;
 
         /* FSI DIV setting */
         ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
@@ -674,10 +652,14 @@ static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
                 /* disable FSI B */
                 if (enable)
                         __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
-                return ret;
+                goto fsi_set_rate_end;
         }
 
-        return ackmd_bpfmd;
+        ret = ackmd_bpfmd;
+
+fsi_set_rate_end:
+        clk_put(fsib_clk);
+        return ret;
 }
 
 static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
@@ -764,10 +746,15 @@ static struct platform_device lcdc1_device = {
         },
 };
 
+static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
+                                unsigned long *parent_freq);
+
+
 static struct sh_mobile_hdmi_info hdmi_info = {
         .lcd_chan = &sh_mobile_lcdc1_info.ch[0],
         .lcd_dev = &lcdc1_device.dev,
         .flags = HDMI_SND_SRC_SPDIF,
+        .clk_optimize_parent = ap4evb_clk_optimize,
 };
 
 static struct resource hdmi_resources[] = {
@@ -794,6 +781,25 @@ static struct platform_device hdmi_device = {
         },
 };
 
+static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
+                                unsigned long *parent_freq)
+{
+        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
+        long error;
+
+        if (IS_ERR(hdmi_ick)) {
+                int ret = PTR_ERR(hdmi_ick);
+                pr_err("Cannot get HDMI ICK: %d\n", ret);
+                return ret;
+        }
+
+        error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
+
+        clk_put(hdmi_ick);
+
+        return error;
+}
+
 static struct gpio_led ap4evb_leds[] = {
         {
                 .name                   = "led4",
@@ -1181,7 +1187,7 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_OVCN2_1,    NULL);
 
         /* setup USB phy */
-        __raw_writew(0x8a0a, 0xE6058130);       /* USBCR2 */
+        __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
 
         /* enable FSI2 port A (ak4643) */
         gpio_request(GPIO_FN_FSIAIBT,   NULL);
@@ -1355,6 +1361,7 @@ static struct sys_timer ap4evb_timer = {
 MACHINE_START(AP4EVB, "ap4evb")
         .map_io         = ap4evb_map_io,
         .init_irq       = sh7372_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = ap4evb_init,
         .timer          = &ap4evb_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index 3b83d6320bec..686b304a7708 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -367,6 +367,7 @@ static struct sys_timer g3evm_timer = {
 MACHINE_START(G3EVM, "g3evm")
         .map_io         = g3evm_map_io,
         .init_irq       = sh7367_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = g3evm_init,
         .timer          = &g3evm_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index 5b3b582ef3f2..c13f01280b7e 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -394,6 +394,7 @@ static struct sys_timer g4evm_timer = {
 MACHINE_START(G4EVM, "g4evm")
         .map_io         = g4evm_map_io,
         .init_irq       = sh7377_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
         .init_machine   = g4evm_init,
         .timer          = &g4evm_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
new file mode 100644
index 000000000000..5bcf5c1e1399
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -0,0 +1,1200 @@
+/*
+ * mackerel board support
+ *
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * based on ap4evb
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/leds.h>
+#include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/smsc911x.h>
+#include <linux/sh_intc.h>
+#include <linux/tca6416_keypad.h>
+#include <linux/usb/r8a66597.h>
+
+#include <video/sh_mobile_hdmi.h>
+#include <video/sh_mobile_lcdc.h>
+#include <media/sh_mobile_ceu.h>
+#include <media/soc_camera.h>
+#include <media/soc_camera_platform.h>
+#include <sound/sh_fsi.h>
+
+#include <mach/common.h>
+#include <mach/sh7372.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+/*
+ * Address      Interface               BusWidth        note
+ * ------------------------------------------------------------------
+ * 0x0000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = ON
+ * 0x0800_0000  user area               -
+ * 0x1000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = OFF
+ * 0x1400_0000  Ether (LAN9220)         16bit
+ * 0x1600_0000  user area               -               cannot use with NAND
+ * 0x1800_0000  user area               -
+ * 0x1A00_0000  -
+ * 0x4000_0000  LPDDR2-SDRAM (POP)      32bit
+ */
+
+/*
+ * CPU mode
+ *
+ * SW4                                     | Boot Area| Master   | Remarks
+ *  1  | 2   | 3   | 4   | 5   | 6   | 8   |          | Processor|
+ * ----+-----+-----+-----+-----+-----+-----+----------+----------+--------------
+ * ON  | ON  | OFF | ON  | ON  | OFF | OFF | External | System   | External ROM
+ * ON  | ON  | ON  | ON  | ON  | OFF | OFF | External | System   | ROM Debug
+ * ON  | ON  | X   | ON  | OFF | OFF | OFF | Built-in | System   | ROM Debug
+ * X   | OFF | X   | X   | X   | X   | OFF | Built-in | System   | MaskROM
+ * OFF | X   | X   | X   | X   | X   | OFF | Built-in | System   | MaskROM
+ * X   | X   | X   | OFF | X   | X   | OFF | Built-in | System   | MaskROM
+ * OFF | ON  | OFF | X   | X   | OFF | ON  | External | System   | Standalone
+ * ON  | OFF | OFF | X   | X   | OFF | ON  | External | Realtime | Standalone
+*/
+
+/*
+ * NOR Flash ROM
+ *
+ *  SW1  |     SW2    | SW7  | NOR Flash ROM
+ *  bit1 | bit1  bit2 | bit1 | Memory allocation
+ * ------+------------+------+------------------
+ *  OFF  | ON     OFF | ON   |    Area 0
+ *  OFF  | ON     OFF | OFF  |    Area 4
+ */
+
+/*
+ * SMSC 9220
+ *
+ *  SW1         SMSC 9220
+ * -----------------------
+ *  ON          access disable
+ *  OFF         access enable
+ */
+
+/*
+ * NAND Flash ROM
+ *
+ *  SW1  |     SW2    | SW7  | NAND Flash ROM
+ *  bit1 | bit1  bit2 | bit2 | Memory allocation
+ * ------+------------+------+------------------
+ *  OFF  | ON     OFF | ON   |    FCE 0
+ *  OFF  | ON     OFF | OFF  |    FCE 1
+ */
+
+/*
+ * External interrupt pin settings
+ *
+ * IRQX  | pin setting        | device             | level
+ * ------+--------------------+--------------------+-------
+ * IRQ0  | ICR1A.IRQ0SA=0010  | SDHI2 card detect  | Low
+ * IRQ6  | ICR1A.IRQ6SA=0011  | Ether(LAN9220)     | High
+ * IRQ7  | ICR1A.IRQ7SA=0010  | LCD Tuch Panel     | Low
+ * IRQ8  | ICR2A.IRQ8SA=0010  | MMC/SD card detect | Low
+ * IRQ9  | ICR2A.IRQ9SA=0010  | KEY(TCA6408)       | Low
+ * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345)    | High
+ * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975)     | High
+ */
+
+/*
+ * USB
+ *
+ * USB0 : CN22 : Function
+ * USB1 : CN31 : Function/Host *1
+ *
+ * J30 (for CN31) *1
+ * ----------+---------------+-------------
+ * 1-2 short | VBUS 5V       | Host
+ * open      | external VBUS | Function
+ *
+ * *1
+ * CN31 is used as Host in Linux.
+ */
+
+/*
+ * SDHI0 (CN12)
+ *
+ * SW56 : OFF
+ *
+ */
+
+/* MMC /SDHI1 (CN7)
+ *
+ * I/O voltage : 1.8v
+ *
+ * Power voltage : 1.8v or 3.3v
+ *  J22 : select power voltage *1
+ *      1-2 pin : 1.8v
+ *      2-3 pin : 3.3v
+ *
+ * *1
+ * Please change J22 depends the card to be used.
+ * MMC's OCR field set to support either voltage for the card inserted.
+ *
+ *      SW1     |       SW33
+ *              | bit1 | bit2 | bit3 | bit4
+ * -------------+------+------+------+-------
+ * MMC0   OFF   |  OFF |  ON  |  ON  |  X
+ * MMC1   ON    |  OFF |  ON  |  X   | ON
+ * SDHI1  OFF   |  ON  |   X  |  OFF | ON
+ *
+ */
+
+/*
+ * SDHI2 (CN23)
+ *
+ * microSD card sloct
+ *
+ */
+
+/*
+ * FIXME !!
+ *
+ * gpio_no_direction
+ * are quick_hack.
+ *
+ * current gpio frame work doesn't have
+ * the method to control only pull up/down/free.
+ * this function should be replaced by correct gpio function
+ */
+static void __init gpio_no_direction(u32 addr)
+{
+        __raw_writeb(0x00, addr);
+}
+
+/* MTD */
+static struct mtd_partition nor_flash_partitions[] = {
+        {
+                .name           = "loader",
+                .offset         = 0x00000000,
+                .size           = 512 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "bootenv",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 512 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "kernel_ro",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 8 * 1024 * 1024,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 8 * 1024 * 1024,
+        },
+        {
+                .name           = "data",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 2,
+        .parts          = nor_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
+};
+
+static struct resource nor_flash_resources[] = {
+        [0]     = {
+                .start  = 0x00000000,
+                .end    = 0x08000000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device nor_flash_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &nor_flash_data,
+        },
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+        .resource       = nor_flash_resources,
+};
+
+/* SMSC */
+static struct resource smc911x_resources[] = {
+        {
+                .start  = 0x14000000,
+                .end    = 0x16000000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = evt2irq(0x02c0) /* IRQ6A */,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+        },
+};
+
+static struct smsc911x_platform_config smsc911x_info = {
+        .flags          = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct platform_device smc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc911x_resources),
+        .resource       = smc911x_resources,
+        .dev            = {
+                .platform_data = &smsc911x_info,
+        },
+};
+
+/* LCDC */
+static struct fb_videomode mackerel_lcdc_modes[] = {
+        {
+                .name           = "WVGA Panel",
+                .xres           = 800,
+                .yres           = 480,
+                .left_margin    = 220,
+                .right_margin   = 110,
+                .hsync_len      = 70,
+                .upper_margin   = 20,
+                .lower_margin   = 5,
+                .vsync_len      = 5,
+                .sync           = 0,
+        },
+};
+
+static struct sh_mobile_lcdc_info lcdc_info = {
+        .clock_source = LCDC_CLK_BUS,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .bpp = 16,
+                .lcd_cfg = mackerel_lcdc_modes,
+                .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
+                .interface_type         = RGB24,
+                .clock_divider          = 2,
+                .flags                  = 0,
+                .lcd_size_cfg.width     = 152,
+                .lcd_size_cfg.height    = 91,
+        }
+};
+
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC",
+                .start  = 0xfe940000,
+                .end    = 0xfe943fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x580),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+        .resource       = lcdc_resources,
+        .dev    = {
+                .platform_data  = &lcdc_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+
+/* HDMI */
+static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
+        .clock_source = LCDC_CLK_EXTERNAL,
+        .ch[0] = {
+                .chan = LCDC_CHAN_MAINLCD,
+                .bpp = 16,
+                .interface_type = RGB24,
+                .clock_divider = 1,
+                .flags = LCDC_FLAGS_DWPOL,
+        }
+};
+
+static struct resource hdmi_lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC1",
+                .start  = 0xfe944000,
+                .end    = 0xfe947fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x1780),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device hdmi_lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(hdmi_lcdc_resources),
+        .resource       = hdmi_lcdc_resources,
+        .id             = 1,
+        .dev    = {
+                .platform_data  = &hdmi_lcdc_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+
+static struct sh_mobile_hdmi_info hdmi_info = {
+        .lcd_chan       = &hdmi_lcdc_info.ch[0],
+        .lcd_dev        = &hdmi_lcdc_device.dev,
+        .flags          = HDMI_SND_SRC_SPDIF,
+};
+
+static struct resource hdmi_resources[] = {
+        [0] = {
+                .name   = "HDMI",
+                .start  = 0xe6be0000,
+                .end    = 0xe6be00ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
+                .start  = evt2irq(0x17e0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device hdmi_device = {
+        .name           = "sh-mobile-hdmi",
+        .num_resources  = ARRAY_SIZE(hdmi_resources),
+        .resource       = hdmi_resources,
+        .id             = -1,
+        .dev    = {
+                .platform_data  = &hdmi_info,
+        },
+};
+
+static int __init hdmi_init_pm_clock(void)
+{
+        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
+        int ret;
+        long rate;
+
+        if (IS_ERR(hdmi_ick)) {
+                ret = PTR_ERR(hdmi_ick);
+                pr_err("Cannot get HDMI ICK: %d\n", ret);
+                goto out;
+        }
+
+        ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
+        if (ret < 0) {
+                pr_err("Cannot set PLLC2 parent: %d, %d users\n",
+                       ret, sh7372_pllc2_clk.usecount);
+                goto out;
+        }
+
+        pr_debug("PLLC2 initial frequency %lu\n",
+                 clk_get_rate(&sh7372_pllc2_clk));
+
+        rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
+        if (rate < 0) {
+                pr_err("Cannot get suitable rate: %ld\n", rate);
+                ret = rate;
+                goto out;
+        }
+
+        ret = clk_set_rate(&sh7372_pllc2_clk, rate);
+        if (ret < 0) {
+                pr_err("Cannot set rate %ld: %d\n", rate, ret);
+                goto out;
+        }
+
+        ret = clk_enable(&sh7372_pllc2_clk);
+        if (ret < 0) {
+                pr_err("Cannot enable pllc2 clock\n");
+                goto out;
+        }
+
+        pr_debug("PLLC2 set frequency %lu\n", rate);
+
+        ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
+        if (ret < 0) {
+                pr_err("Cannot set HDMI parent: %d\n", ret);
+                goto out;
+        }
+
+out:
+        if (!IS_ERR(hdmi_ick))
+                clk_put(hdmi_ick);
+        return ret;
+}
+device_initcall(hdmi_init_pm_clock);
+
+/* USB1 (Host) */
+static void usb1_host_port_power(int port, int power)
+{
+        if (!power) /* only power-on is supported for now */
+                return;
+
+        /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
+        __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
+}
+
+static struct r8a66597_platdata usb1_host_data = {
+        .on_chip        = 1,
+        .port_power     = usb1_host_port_power,
+};
+
+static struct resource usb1_host_resources[] = {
+        [0] = {
+                .name   = "USBHS",
+                .start  = 0xE68B0000,
+                .end    = 0xE68B00E6 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x1ce0) /* USB1_USB1I0 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb1_host_device = {
+        .name   = "r8a66597_hcd",
+        .id     = 1,
+        .dev = {
+                .dma_mask               = NULL,         /*  not use dma */
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &usb1_host_data,
+        },
+        .num_resources  = ARRAY_SIZE(usb1_host_resources),
+        .resource       = usb1_host_resources,
+};
+
+/* LED */
+static struct gpio_led mackerel_leds[] = {
+        {
+                .name           = "led0",
+                .gpio           = GPIO_PORT0,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name           = "led1",
+                .gpio           = GPIO_PORT1,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name           = "led2",
+                .gpio           = GPIO_PORT2,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name           = "led3",
+                .gpio           = GPIO_PORT159,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }
+};
+
+static struct gpio_led_platform_data mackerel_leds_pdata = {
+        .leds = mackerel_leds,
+        .num_leds = ARRAY_SIZE(mackerel_leds),
+};
+
+static struct platform_device leds_device = {
+        .name = "leds-gpio",
+        .id = 0,
+        .dev = {
+                .platform_data  = &mackerel_leds_pdata,
+        },
+};
+
+/* FSI */
+#define IRQ_FSI evt2irq(0x1840)
+static int __fsi_set_round_rate(struct clk *clk, long rate, int enable)
+{
+        int ret;
+
+        if (rate <= 0)
+                return 0;
+
+        if (!enable) {
+                clk_disable(clk);
+                return 0;
+        }
+
+        ret = clk_set_rate(clk, clk_round_rate(clk, rate));
+        if (ret < 0)
+                return ret;
+
+        return clk_enable(clk);
+}
+
+static int fsi_set_rate(struct device *dev, int is_porta, int rate, int enable)
+{
+        struct clk *fsib_clk;
+        struct clk *fdiv_clk = &sh7372_fsidivb_clk;
+        long fsib_rate = 0;
+        long fdiv_rate = 0;
+        int ackmd_bpfmd;
+        int ret;
+
+        /* FSIA is slave mode. nothing to do here */
+        if (is_porta)
+                return 0;
+
+        /* clock start */
+        switch (rate) {
+        case 44100:
+                fsib_rate       = rate * 256;
+                ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+                break;
+        case 48000:
+                fsib_rate       = 85428000; /* around 48kHz x 256 x 7 */
+                fdiv_rate       = rate * 256;
+                ackmd_bpfmd     = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+                break;
+        default:
+                pr_err("unsupported rate in FSI2 port B\n");
+                return -EINVAL;
+        }
+
+        /* FSI B setting */
+        fsib_clk = clk_get(dev, "ickb");
+        if (IS_ERR(fsib_clk))
+                return -EIO;
+
+        /* fsib */
+        ret = __fsi_set_round_rate(fsib_clk, fsib_rate, enable);
+        if (ret < 0)
+                goto fsi_set_rate_end;
+
+        /* FSI DIV */
+        ret = __fsi_set_round_rate(fdiv_clk, fdiv_rate, enable);
+        if (ret < 0) {
+                /* disable FSI B */
+                if (enable)
+                        __fsi_set_round_rate(fsib_clk, fsib_rate, 0);
+                goto fsi_set_rate_end;
+        }
+
+        ret = ackmd_bpfmd;
+
+fsi_set_rate_end:
+        clk_put(fsib_clk);
+        return ret;
+}
+
+static struct sh_fsi_platform_info fsi_info = {
+        .porta_flags =  SH_FSI_BRS_INV          |
+                        SH_FSI_OUT_SLAVE_MODE   |
+                        SH_FSI_IN_SLAVE_MODE    |
+                        SH_FSI_OFMT(PCM)        |
+                        SH_FSI_IFMT(PCM),
+
+        .portb_flags =  SH_FSI_BRS_INV  |
+                        SH_FSI_BRM_INV  |
+                        SH_FSI_LRS_INV  |
+                        SH_FSI_OFMT(SPDIF),
+
+        .set_rate = fsi_set_rate,
+};
+
+static struct resource fsi_resources[] = {
+        [0] = {
+                .name   = "FSI",
+                .start  = 0xFE3C0000,
+                .end    = 0xFE3C0400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_FSI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device fsi_device = {
+        .name           = "sh_fsi2",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(fsi_resources),
+        .resource       = fsi_resources,
+        .dev    = {
+                .platform_data  = &fsi_info,
+        },
+};
+
+static struct platform_device fsi_ak4643_device = {
+        .name           = "sh_fsi2_a_ak4643",
+};
+
+/*
+ * The card detect pin of the top SD/MMC slot (CN7) is active low and is
+ * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ */
+static int slot_cn7_get_cd(struct platform_device *pdev)
+{
+        if (gpio_is_valid(GPIO_PORT41))
+                return !gpio_get_value(GPIO_PORT41);
+        else
+                return -ENXIO;
+}
+
+/* SDHI0 */
+static struct sh_mobile_sdhi_info sdhi0_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+};
+
+static struct resource sdhi0_resources[] = {
+        [0] = {
+                .name   = "SDHI0",
+                .start  = 0xe6850000,
+                .end    = 0xe68501ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0e00) /* SDHI0 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi0_device = {
+        .name           = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi0_resources),
+        .resource       = sdhi0_resources,
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &sdhi0_info,
+        },
+};
+
+#if !defined(CONFIG_MMC_SH_MMCIF)
+/* SDHI1 */
+static struct sh_mobile_sdhi_info sdhi1_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
+        .tmio_ocr_mask  = MMC_VDD_165_195,
+        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED |
+                          MMC_CAP_NEEDS_POLL,
+        .get_cd         = slot_cn7_get_cd,
+};
+
+static struct resource sdhi1_resources[] = {
+        [0] = {
+                .name   = "SDHI1",
+                .start  = 0xe6860000,
+                .end    = 0xe68601ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0e80),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi1_device = {
+        .name           = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi1_resources),
+        .resource       = sdhi1_resources,
+        .id             = 1,
+        .dev    = {
+                .platform_data  = &sdhi1_info,
+        },
+};
+#endif
+
+/* SDHI2 */
+static struct sh_mobile_sdhi_info sdhi2_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI2_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI2_RX,
+        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED |
+                          MMC_CAP_NEEDS_POLL,
+};
+
+static struct resource sdhi2_resources[] = {
+        [0] = {
+                .name   = "SDHI2",
+                .start  = 0xe6870000,
+                .end    = 0xe68701ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x1200),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi2_device = {
+        .name   = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi2_resources),
+        .resource       = sdhi2_resources,
+        .id             = 2,
+        .dev    = {
+                .platform_data  = &sdhi2_info,
+        },
+};
+
+/* SH_MMCIF */
+static struct resource sh_mmcif_resources[] = {
+        [0] = {
+                .name   = "MMCIF",
+                .start  = 0xE6BD0000,
+                .end    = 0xE6BD00FF,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* MMC ERR */
+                .start  = evt2irq(0x1ac0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* MMC NOR */
+                .start  = evt2irq(0x1ae0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct sh_mmcif_plat_data sh_mmcif_plat = {
+        .sup_pclk       = 0,
+        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .caps           = MMC_CAP_4_BIT_DATA |
+                          MMC_CAP_8_BIT_DATA |
+                          MMC_CAP_NEEDS_POLL,
+        .get_cd         = slot_cn7_get_cd,
+};
+
+static struct platform_device sh_mmcif_device = {
+        .name           = "sh_mmcif",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &sh_mmcif_plat,
+        },
+        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+        .resource       = sh_mmcif_resources,
+};
+
+
+static int mackerel_camera_add(struct soc_camera_link *icl, struct device *dev);
+static void mackerel_camera_del(struct soc_camera_link *icl);
+
+static int camera_set_capture(struct soc_camera_platform_info *info,
+                              int enable)
+{
+        return 0; /* camera sensor always enabled */
+}
+
+static struct soc_camera_platform_info camera_info = {
+        .format_name = "UYVY",
+        .format_depth = 16,
+        .format = {
+                .code = V4L2_MBUS_FMT_UYVY8_2X8,
+                .colorspace = V4L2_COLORSPACE_SMPTE170M,
+                .field = V4L2_FIELD_NONE,
+                .width = 640,
+                .height = 480,
+        },
+        .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
+        SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 |
+        SOCAM_DATA_ACTIVE_HIGH,
+        .set_capture = camera_set_capture,
+};
+
+static struct soc_camera_link camera_link = {
+        .bus_id         = 0,
+        .add_device     = mackerel_camera_add,
+        .del_device     = mackerel_camera_del,
+        .module_name    = "soc_camera_platform",
+        .priv           = &camera_info,
+};
+
+static void dummy_release(struct device *dev)
+{
+}
+
+static struct platform_device camera_device = {
+        .name           = "soc_camera_platform",
+        .dev            = {
+                .platform_data  = &camera_info,
+                .release        = dummy_release,
+        },
+};
+
+static int mackerel_camera_add(struct soc_camera_link *icl,
+                               struct device *dev)
+{
+        if (icl != &camera_link)
+                return -ENODEV;
+
+        camera_info.dev = dev;
+
+        return platform_device_register(&camera_device);
+}
+
+static void mackerel_camera_del(struct soc_camera_link *icl)
+{
+        if (icl != &camera_link)
+                return;
+
+        platform_device_unregister(&camera_device);
+        memset(&camera_device.dev.kobj, 0,
+               sizeof(camera_device.dev.kobj));
+}
+
+static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
+        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+};
+
+static struct resource ceu_resources[] = {
+        [0] = {
+                .name   = "CEU",
+                .start  = 0xfe910000,
+                .end    = 0xfe91009f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x880),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device ceu_device = {
+        .name           = "sh_mobile_ceu",
+        .id             = 0, /* "ceu0" clock */
+        .num_resources  = ARRAY_SIZE(ceu_resources),
+        .resource       = ceu_resources,
+        .dev            = {
+                .platform_data  = &sh_mobile_ceu_info,
+        },
+};
+
+static struct platform_device mackerel_camera = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &camera_link,
+        },
+};
+
+static struct platform_device *mackerel_devices[] __initdata = {
+        &nor_flash_device,
+        &smc911x_device,
+        &lcdc_device,
+        &usb1_host_device,
+        &leds_device,
+        &fsi_device,
+        &fsi_ak4643_device,
+        &sdhi0_device,
+#if !defined(CONFIG_MMC_SH_MMCIF)
+        &sdhi1_device,
+#endif
+        &sdhi2_device,
+        &sh_mmcif_device,
+        &ceu_device,
+        &mackerel_camera,
+        &hdmi_lcdc_device,
+        &hdmi_device,
+};
+
+/* Keypad Initialization */
+#define KEYPAD_BUTTON(ev_type, ev_code, act_low) \
+{                                                               \
+        .type           = ev_type,                              \
+        .code           = ev_code,                              \
+        .active_low     = act_low,                              \
+}
+
+#define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1)
+
+static struct tca6416_button mackerel_gpio_keys[] = {
+        KEYPAD_BUTTON_LOW(KEY_HOME),
+        KEYPAD_BUTTON_LOW(KEY_MENU),
+        KEYPAD_BUTTON_LOW(KEY_BACK),
+        KEYPAD_BUTTON_LOW(KEY_POWER),
+};
+
+static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = {
+        .buttons        = mackerel_gpio_keys,
+        .nbuttons       = ARRAY_SIZE(mackerel_gpio_keys),
+        .rep            = 1,
+        .use_polling    = 0,
+        .pinmask        = 0x000F,
+};
+
+/* I2C */
+#define IRQ9 evt2irq(0x0320)
+
+static struct i2c_board_info i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("ak4643", 0x13),
+        },
+        /* Keypad */
+        {
+                I2C_BOARD_INFO("tca6408-keys", 0x20),
+                .platform_data = &mackerel_tca6416_keys_info,
+                .irq = IRQ9,
+        },
+};
+
+#define IRQ21 evt2irq(0x32a0)
+
+static struct i2c_board_info i2c1_devices[] = {
+        /* Accelerometer */
+        {
+                I2C_BOARD_INFO("adxl34x", 0x53),
+                .irq = IRQ21,
+        },
+};
+
+static struct map_desc mackerel_io_desc[] __initdata = {
+        /* create a 1:1 entity map for 0xe6xxxxxx
+         * used by CPGA, INTC and PFC.
+         */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 256 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+static void __init mackerel_map_io(void)
+{
+        iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
+
+        /* setup early devices and console here as well */
+        sh7372_add_early_devices();
+        shmobile_setup_console();
+}
+
+#define GPIO_PORT9CR    0xE6051009
+#define GPIO_PORT10CR   0xE605100A
+#define SRCR4           0xe61580bc
+#define USCCR1          0xE6058144
+static void __init mackerel_init(void)
+{
+        u32 srcr4;
+        struct clk *clk;
+
+        sh7372_pinmux_init();
+
+        /* enable SCIFA0 */
+        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
+        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
+
+        /* enable SMSC911X */
+        gpio_request(GPIO_FN_CS5A,      NULL);
+        gpio_request(GPIO_FN_IRQ6_39,   NULL);
+
+        /* LCDC */
+        gpio_request(GPIO_FN_LCDD23,   NULL);
+        gpio_request(GPIO_FN_LCDD22,   NULL);
+        gpio_request(GPIO_FN_LCDD21,   NULL);
+        gpio_request(GPIO_FN_LCDD20,   NULL);
+        gpio_request(GPIO_FN_LCDD19,   NULL);
+        gpio_request(GPIO_FN_LCDD18,   NULL);
+        gpio_request(GPIO_FN_LCDD17,   NULL);
+        gpio_request(GPIO_FN_LCDD16,   NULL);
+        gpio_request(GPIO_FN_LCDD15,   NULL);
+        gpio_request(GPIO_FN_LCDD14,   NULL);
+        gpio_request(GPIO_FN_LCDD13,   NULL);
+        gpio_request(GPIO_FN_LCDD12,   NULL);
+        gpio_request(GPIO_FN_LCDD11,   NULL);
+        gpio_request(GPIO_FN_LCDD10,   NULL);
+        gpio_request(GPIO_FN_LCDD9,    NULL);
+        gpio_request(GPIO_FN_LCDD8,    NULL);
+        gpio_request(GPIO_FN_LCDD7,    NULL);
+        gpio_request(GPIO_FN_LCDD6,    NULL);
+        gpio_request(GPIO_FN_LCDD5,    NULL);
+        gpio_request(GPIO_FN_LCDD4,    NULL);
+        gpio_request(GPIO_FN_LCDD3,    NULL);
+        gpio_request(GPIO_FN_LCDD2,    NULL);
+        gpio_request(GPIO_FN_LCDD1,    NULL);
+        gpio_request(GPIO_FN_LCDD0,    NULL);
+        gpio_request(GPIO_FN_LCDDISP,  NULL);
+        gpio_request(GPIO_FN_LCDDCK,   NULL);
+
+        gpio_request(GPIO_PORT31, NULL); /* backlight */
+        gpio_direction_output(GPIO_PORT31, 1);
+
+        gpio_request(GPIO_PORT151, NULL); /* LCDDON */
+        gpio_direction_output(GPIO_PORT151, 1);
+
+        /* USB enable */
+        gpio_request(GPIO_FN_VBUS0_1,    NULL);
+        gpio_request(GPIO_FN_IDIN_1_18,  NULL);
+        gpio_request(GPIO_FN_PWEN_1_115, NULL);
+        gpio_request(GPIO_FN_OVCN_1_114, NULL);
+        gpio_request(GPIO_FN_EXTLP_1,    NULL);
+        gpio_request(GPIO_FN_OVCN2_1,    NULL);
+
+        /* setup USB phy */
+        __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
+
+        /* enable FSI2 port A (ak4643) */
+        gpio_request(GPIO_FN_FSIAIBT,   NULL);
+        gpio_request(GPIO_FN_FSIAILR,   NULL);
+        gpio_request(GPIO_FN_FSIAISLD,  NULL);
+        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+        gpio_request(GPIO_PORT161,      NULL);
+        gpio_direction_output(GPIO_PORT161, 0); /* slave */
+
+        gpio_request(GPIO_PORT9,  NULL);
+        gpio_request(GPIO_PORT10, NULL);
+        gpio_no_direction(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
+        gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
+
+        intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
+
+        /* setup FSI2 port B (HDMI) */
+        gpio_request(GPIO_FN_FSIBCK, NULL);
+        __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
+
+        /* set SPU2 clock to 119.6 MHz */
+        clk = clk_get(NULL, "spu_clk");
+        if (!IS_ERR(clk)) {
+                clk_set_rate(clk, clk_round_rate(clk, 119600000));
+                clk_put(clk);
+        }
+
+        /* enable Keypad */
+        gpio_request(GPIO_FN_IRQ9_42,   NULL);
+        set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
+
+        /* enable Accelerometer */
+        gpio_request(GPIO_FN_IRQ21,     NULL);
+        set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
+
+        /* enable SDHI0 */
+        gpio_request(GPIO_FN_SDHICD0, NULL);
+        gpio_request(GPIO_FN_SDHIWP0, NULL);
+        gpio_request(GPIO_FN_SDHICMD0, NULL);
+        gpio_request(GPIO_FN_SDHICLK0, NULL);
+        gpio_request(GPIO_FN_SDHID0_3, NULL);
+        gpio_request(GPIO_FN_SDHID0_2, NULL);
+        gpio_request(GPIO_FN_SDHID0_1, NULL);
+        gpio_request(GPIO_FN_SDHID0_0, NULL);
+
+#if !defined(CONFIG_MMC_SH_MMCIF)
+        /* enable SDHI1 */
+        gpio_request(GPIO_FN_SDHICMD1, NULL);
+        gpio_request(GPIO_FN_SDHICLK1, NULL);
+        gpio_request(GPIO_FN_SDHID1_3, NULL);
+        gpio_request(GPIO_FN_SDHID1_2, NULL);
+        gpio_request(GPIO_FN_SDHID1_1, NULL);
+        gpio_request(GPIO_FN_SDHID1_0, NULL);
+#endif
+        /* card detect pin for MMC slot (CN7) */
+        gpio_request(GPIO_PORT41, NULL);
+        gpio_direction_input(GPIO_PORT41);
+
+        /* enable SDHI2 */
+        gpio_request(GPIO_FN_SDHICMD2, NULL);
+        gpio_request(GPIO_FN_SDHICLK2, NULL);
+        gpio_request(GPIO_FN_SDHID2_3, NULL);
+        gpio_request(GPIO_FN_SDHID2_2, NULL);
+        gpio_request(GPIO_FN_SDHID2_1, NULL);
+        gpio_request(GPIO_FN_SDHID2_0, NULL);
+
+        /* MMCIF */
+        gpio_request(GPIO_FN_MMCD0_0, NULL);
+        gpio_request(GPIO_FN_MMCD0_1, NULL);
+        gpio_request(GPIO_FN_MMCD0_2, NULL);
+        gpio_request(GPIO_FN_MMCD0_3, NULL);
+        gpio_request(GPIO_FN_MMCD0_4, NULL);
+        gpio_request(GPIO_FN_MMCD0_5, NULL);
+        gpio_request(GPIO_FN_MMCD0_6, NULL);
+        gpio_request(GPIO_FN_MMCD0_7, NULL);
+        gpio_request(GPIO_FN_MMCCMD0, NULL);
+        gpio_request(GPIO_FN_MMCCLK0, NULL);
+
+        /* enable GPS module (GT-720F) */
+        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
+        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
+
+        /* CEU */
+        gpio_request(GPIO_FN_VIO_CLK, NULL);
+        gpio_request(GPIO_FN_VIO_VD, NULL);
+        gpio_request(GPIO_FN_VIO_HD, NULL);
+        gpio_request(GPIO_FN_VIO_FIELD, NULL);
+        gpio_request(GPIO_FN_VIO_CKO, NULL);
+        gpio_request(GPIO_FN_VIO_D7, NULL);
+        gpio_request(GPIO_FN_VIO_D6, NULL);
+        gpio_request(GPIO_FN_VIO_D5, NULL);
+        gpio_request(GPIO_FN_VIO_D4, NULL);
+        gpio_request(GPIO_FN_VIO_D3, NULL);
+        gpio_request(GPIO_FN_VIO_D2, NULL);
+        gpio_request(GPIO_FN_VIO_D1, NULL);
+        gpio_request(GPIO_FN_VIO_D0, NULL);
+
+        /* HDMI */
+        gpio_request(GPIO_FN_HDMI_HPD, NULL);
+        gpio_request(GPIO_FN_HDMI_CEC, NULL);
+
+        /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
+        srcr4 = __raw_readl(SRCR4);
+        __raw_writel(srcr4 | (1 << 13), SRCR4);
+        udelay(50);
+        __raw_writel(srcr4 & ~(1 << 13), SRCR4);
+
+        i2c_register_board_info(0, i2c0_devices,
+                                ARRAY_SIZE(i2c0_devices));
+        i2c_register_board_info(1, i2c1_devices,
+                                ARRAY_SIZE(i2c1_devices));
+
+        sh7372_add_standard_devices();
+
+        platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
+}
+
+static void __init mackerel_timer_init(void)
+{
+        sh7372_clock_init();
+        shmobile_timer.init();
+
+        /* External clock source */
+        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+}
+
+static struct sys_timer mackerel_timer = {
+        .init           = mackerel_timer_init,
+};
+
+MACHINE_START(MACKEREL, "mackerel")
+        .map_io         = mackerel_map_io,
+        .init_irq       = sh7372_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = mackerel_init,
+        .timer          = &mackerel_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index 9f78729098f2..6b186aefcbd6 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -20,8 +20,8 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/sh_clk.h>
+#include <linux/clkdev.h>
 #include <mach/common.h>
-#include <asm/clkdev.h>
 
 /* SH7367 registers */
 #define RTFRQCR    0xe6150000
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 3aa026069435..9aa8d68d1a9c 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -20,8 +20,8 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/sh_clk.h>
+#include <linux/clkdev.h>
 #include <mach/common.h>
-#include <asm/clkdev.h>
 
 /* SH7372 registers */
 #define FRQCRA          0xe6150000
@@ -507,7 +507,7 @@ enum { MSTP001,
        MSTP223,
        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
        MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
-       MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
+       MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
        MSTP_NR };
 
 #define MSTP(_parent, _reg, _bit, _flags) \
@@ -543,6 +543,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
         [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
+        [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
         [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
         [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
         [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
@@ -596,9 +597,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
         CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
         CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
-        CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
-        CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
-        CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
+        CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+        CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
 
         /* MSTP32 clocks */
         CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
@@ -610,7 +612,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
-        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
+        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
         CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
         CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
@@ -633,6 +635,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
+        CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
         CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
         CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index f91395aeb9ab..95942466e63f 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -20,8 +20,8 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/sh_clk.h>
+#include <linux/clkdev.h>
 #include <mach/common.h>
-#include <asm/clkdev.h>
 
 /* SH7377 registers */
 #define RTFRQCR    0xe6150000
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
new file mode 100644
index 000000000000..720a71433be6
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -0,0 +1,356 @@
+/*
+ * sh73a0 clock framework support
+ *
+ * Copyright (C) 2010 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+
+#define FRQCRA          0xe6150000
+#define FRQCRB          0xe6150004
+#define FRQCRD          0xe61500e4
+#define VCLKCR1         0xe6150008
+#define VCLKCR2         0xe615000C
+#define VCLKCR3         0xe615001C
+#define ZBCKCR          0xe6150010
+#define FLCKCR          0xe6150014
+#define SD0CKCR         0xe6150074
+#define SD1CKCR         0xe6150078
+#define SD2CKCR         0xe615007C
+#define FSIACKCR        0xe6150018
+#define FSIBCKCR        0xe6150090
+#define SUBCKCR         0xe6150080
+#define SPUACKCR        0xe6150084
+#define SPUVCKCR        0xe6150094
+#define MSUCKCR         0xe6150088
+#define HSICKCR         0xe615008C
+#define MFCK1CR         0xe6150098
+#define MFCK2CR         0xe615009C
+#define DSITCKCR        0xe6150060
+#define DSI0PCKCR       0xe6150064
+#define DSI1PCKCR       0xe6150068
+#define DSI0PHYCR       0xe615006C
+#define DSI1PHYCR       0xe6150070
+#define PLLECR          0xe61500d0
+#define PLL0CR          0xe61500d8
+#define PLL1CR          0xe6150028
+#define PLL2CR          0xe615002c
+#define PLL3CR          0xe61500dc
+#define SMSTPCR0        0xe6150130
+#define SMSTPCR1        0xe6150134
+#define SMSTPCR2        0xe6150138
+#define SMSTPCR3        0xe615013c
+#define SMSTPCR4        0xe6150140
+#define SMSTPCR5        0xe6150144
+#define CKSCR           0xe61500c0
+
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk r_clk = {
+        .rate           = 32768,
+};
+
+/*
+ * 26MHz default rate for the EXTAL1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh73a0_extal1_clk = {
+        .rate           = 26000000,
+};
+
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+struct clk sh73a0_extal2_clk = {
+        .rate           = 48000000,
+};
+
+/* A fixed divide-by-2 block */
+static unsigned long div2_recalc(struct clk *clk)
+{
+        return clk->parent->rate / 2;
+}
+
+static struct clk_ops div2_clk_ops = {
+        .recalc         = div2_recalc,
+};
+
+/* Divide extal1 by two */
+static struct clk extal1_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh73a0_extal1_clk,
+};
+
+/* Divide extal2 by two */
+static struct clk extal2_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &sh73a0_extal2_clk,
+};
+
+static struct clk_ops main_clk_ops = {
+        .recalc         = followparent_recalc,
+};
+
+/* Main clock */
+static struct clk main_clk = {
+        .ops            = &main_clk_ops,
+};
+
+/* PLL0, PLL1, PLL2, PLL3 */
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (__raw_readl(PLLECR) & (1 << clk->enable_bit))
+                mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1);
+
+        return clk->parent->rate * mult;
+}
+
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+};
+
+static struct clk pll0_clk = {
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &main_clk,
+        .enable_reg     = (void __iomem *)PLL0CR,
+        .enable_bit     = 0,
+};
+
+static struct clk pll1_clk = {
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &main_clk,
+        .enable_reg     = (void __iomem *)PLL1CR,
+        .enable_bit     = 1,
+};
+
+static struct clk pll2_clk = {
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &main_clk,
+        .enable_reg     = (void __iomem *)PLL2CR,
+        .enable_bit     = 2,
+};
+
+static struct clk pll3_clk = {
+        .ops            = &pll_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &main_clk,
+        .enable_reg     = (void __iomem *)PLL3CR,
+        .enable_bit     = 3,
+};
+
+/* Divide PLL1 by two */
+static struct clk pll1_div2_clk = {
+        .ops            = &div2_clk_ops,
+        .parent         = &pll1_clk,
+};
+
+static struct clk *main_clks[] = {
+        &r_clk,
+        &sh73a0_extal1_clk,
+        &sh73a0_extal2_clk,
+        &extal1_div2_clk,
+        &extal2_div2_clk,
+        &main_clk,
+        &pll0_clk,
+        &pll1_clk,
+        &pll2_clk,
+        &pll3_clk,
+        &pll1_div2_clk,
+};
+
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in FRQCRB to update hardware setting */
+        value = __raw_readl(FRQCRB);
+        value |= (1 << 31);
+        __raw_writel(value, FRQCRB);
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+                          24, 0, 36, 48, 7 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick = div4_kick,
+};
+
+enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
+        DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+        SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
+        [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
+        [DIV4_M3] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
+        [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
+        [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
+        [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
+        [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
+        [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
+        [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
+        [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
+};
+
+enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
+        DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
+        DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
+        DIV6_SPUA, DIV6_SPUV, DIV6_MSU,
+        DIV6_HSI,  DIV6_MFG1, DIV6_MFG2,
+        DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
+        DIV6_NR };
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
+        [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
+        [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
+        [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, 0),
+        [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
+        [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
+        [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
+        [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+        [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
+        [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
+        [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
+        [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
+        [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
+        [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
+        [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
+        [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
+        [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
+        [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
+        [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
+        [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
+};
+
+enum { MSTP001,
+        MSTP125, MSTP116,
+        MSTP219,
+        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+        MSTP331, MSTP329, MSTP323, MSTP312,
+        MSTP411, MSTP410, MSTP403,
+        MSTP_NR };
+
+#define MSTP(_parent, _reg, _bit, _flags) \
+        SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
+
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
+        [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
+        [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
+        [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
+        [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
+        [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
+        [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
+        [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
+        [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
+        [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
+        [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
+        [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
+        [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
+};
+
+#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
+#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("r_clk", &r_clk),
+
+        /* MSTP32 clocks */
+        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
+        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
+        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
+        CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
+        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
+        CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
+        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
+        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
+        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
+        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
+        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
+        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
+        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
+        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
+        CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
+        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
+};
+
+void __init sh73a0_clock_init(void)
+{
+        int k, ret = 0;
+
+        /* detect main clock parent */
+        switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
+        case 0:
+                main_clk.parent = &sh73a0_extal1_clk;
+                break;
+        case 1:
+                main_clk.parent = &extal1_div2_clk;
+                break;
+        case 2:
+                main_clk.parent = &sh73a0_extal2_clk;
+                break;
+        case 3:
+                main_clk.parent = &extal2_div2_clk;
+                break;
+        }
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        if (!ret)
+                clk_init();
+        else
+                panic("failed to setup sh73a0 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/entry-gic.S b/arch/arm/mach-shmobile/entry-gic.S
new file mode 100644
index 000000000000..e20239b08c83
--- /dev/null
+++ b/arch/arm/mach-shmobile/entry-gic.S
@@ -0,0 +1,18 @@
+/*
+ * ARM Interrupt demux handler using GIC
+ *
+ * Copyright (C) 2010 Magnus Damm
+ * Copyright (C) 2011 Paul Mundt
+ * Copyright (C) 2010 - 2011 Renesas Solutions Corp.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/assembler.h>
+#include <asm/entry-macro-multi.S>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
+
+        arch_irq_handler shmobile_handle_irq_gic
diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S
new file mode 100644
index 000000000000..cac0a7ae2084
--- /dev/null
+++ b/arch/arm/mach-shmobile/entry-intc.S
@@ -0,0 +1,57 @@
+/*
+ * ARM Interrupt demux handler using INTC
+ *
+ * Copyright (C) 2010 Magnus Damm
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/entry-macro-multi.S>
+
+#define INTCA_BASE      0xe6980000
+#define INTFLGA_OFFS    0x00000018 /* accept pending interrupt */
+#define INTEVTA_OFFS    0x00000020 /* vector number of accepted interrupt */
+#define INTLVLA_OFFS    0x00000030 /* priority level of accepted interrupt */
+#define INTLVLB_OFFS    0x00000034 /* previous priority level */
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =INTCA_BASE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        /* The single INTFLGA read access below results in the following:
+         *
+         * 1. INTLVLB is updated with old priority value from INTLVLA
+         * 2. Highest priority interrupt is accepted
+         * 3. INTLVLA is updated to contain priority of accepted interrupt
+         * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
+         */
+        ldr     \irqnr, [\base, #INTFLGA_OFFS]
+
+        /* Restore INTLVLA with the value saved in INTLVLB.
+         * This is required to support interrupt priorities properly.
+         */
+        ldrb    \tmp, [\base, #INTLVLB_OFFS]
+        strb    \tmp, [\base, #INTLVLA_OFFS]
+
+        /* Handle invalid vector number case */
+        cmp     \irqnr, #0
+        beq     1000f
+
+        /* Convert vector to irq number, same as the evt2irq() macro */
+        lsr     \irqnr, \irqnr, #0x5
+        subs    \irqnr, \irqnr, #16
+
+1000:
+        .endm
+
+        .macro  test_for_ipi, irqnr, irqstat, base, tmp
+        .endm
+
+        .macro  test_for_ltirq, irqnr, irqstat, base, tmp
+        .endm
+
+        arch_irq_handler shmobile_handle_irq_intc
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
new file mode 100644
index 000000000000..d4cec6b4c7d9
--- /dev/null
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -0,0 +1,27 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2010  Takashi Yoshii
+ *
+ * Based on vexpress, Copyright (c) 2003 ARM Limited, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/memory.h>
+
+        __INIT
+
+/*
+ * Reset vector for secondary CPUs.
+ * This will be mapped at address 0 by SBAR register.
+ * We need _long_ jump to the physical address.
+ */
+        .align  12
+ENTRY(shmobile_secondary_vector)
+        ldr     pc, 1f
+1:      .long   secondary_startup - PAGE_OFFSET + PHYS_OFFSET
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
new file mode 100644
index 000000000000..238a0d97d2d5
--- /dev/null
+++ b/arch/arm/mach-shmobile/hotplug.c
@@ -0,0 +1,41 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+int platform_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+
+void platform_cpu_die(unsigned int cpu)
+{
+        while (1) {
+                /*
+                 * here's the WFI
+                 */
+                asm(".word      0xe320f003\n"
+                    :
+                    :
+                    : "memory", "cc");
+        }
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+        /*
+         * we don't allow CPU 0 to be shutdown (it is still too special
+         * e.g. clock tick interrupts)
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index efeef778a875..013ac0ee8256 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -3,8 +3,11 @@
 
 extern struct sys_timer shmobile_timer;
 extern void shmobile_setup_console(void);
+extern void shmobile_secondary_vector(void);
 struct clk;
 extern int clk_init(void);
+extern void shmobile_handle_irq_intc(struct pt_regs *);
+extern void shmobile_handle_irq_gic(struct pt_regs *);
 
 extern void sh7367_init_irq(void);
 extern void sh7367_add_early_devices(void);
@@ -30,4 +33,17 @@ extern void sh7372_pinmux_init(void);
 extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
+extern void sh73a0_init_irq(void);
+extern void sh73a0_add_early_devices(void);
+extern void sh73a0_add_standard_devices(void);
+extern void sh73a0_clock_init(void);
+extern void sh73a0_pinmux_init(void);
+extern struct clk sh73a0_extal1_clk;
+extern struct clk sh73a0_extal2_clk;
+
+extern unsigned int sh73a0_get_core_count(void);
+extern void sh73a0_secondary_init(unsigned int cpu);
+extern int sh73a0_boot_secondary(unsigned int cpu);
+extern void sh73a0_smp_prepare_cpus(void);
+
 #endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index f428c4db2b60..d791f10eeac7 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2010  Paul Mundt
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -15,47 +14,21 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
-#include <mach/irqs.h>
-
-#define INTCA_BASE      0xe6980000
-#define INTFLGA_OFFS    0x00000018 /* accept pending interrupt */
-#define INTEVTA_OFFS    0x00000020 /* vector number of accepted interrupt */
-#define INTLVLA_OFFS    0x00000030 /* priority level of accepted interrupt */
-#define INTLVLB_OFFS    0x00000034 /* previous priority level */
 
         .macro  disable_fiq
         .endm
 
         .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =INTCA_BASE
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
         .endm
 
         .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        /* The single INTFLGA read access below results in the following:
-         *
-         * 1. INTLVLB is updated with old priority value from INTLVLA
-         * 2. Highest priority interrupt is accepted
-         * 3. INTLVLA is updated to contain priority of accepted interrupt
-         * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
-         */
-        ldr     \irqnr, [\base, #INTFLGA_OFFS]
-
-        /* Restore INTLVLA with the value saved in INTLVLB.
-         * This is required to support interrupt priorities properly.
-         */
-        ldrb    \tmp, [\base, #INTLVLB_OFFS]
-        strb    \tmp, [\base, #INTLVLA_OFFS]
+        .endm
 
-        /* Handle invalid vector number case */
-        cmp     \irqnr, #0
-        beq     1000f
+        .macro  test_for_ipi, irqnr, irqstat, base, tmp
+        .endm
 
-        /* Convert vector to irq number, same as the evt2irq() macro */
-        lsr     \irqnr, \irqnr, #0x5
-        subs    \irqnr, \irqnr, #16
+        .macro  test_for_ltirq, irqnr, irqstat, base, tmp
+        .endm
 
-1000:
+        .macro  arch_ret_to_user, tmp1, tmp2
         .endm
diff --git a/arch/arm/mach-shmobile/include/mach/hardware.h b/arch/arm/mach-shmobile/include/mach/hardware.h
index 3f0ef194603e..99264a5ce5e4 100644
--- a/arch/arm/mach-shmobile/include/mach/hardware.h
+++ b/arch/arm/mach-shmobile/include/mach/hardware.h
@@ -1,7 +1,4 @@
 #ifndef __ASM_MACH_HARDWARE_H
 #define __ASM_MACH_HARDWARE_H
 
-/* INTFLGA register - used by low level interrupt code in entry-macro.S */
-#define INTFLGA                 0xe6980018
-
 #endif /* __ASM_MACH_HARDWARE_H */
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
new file mode 100644
index 000000000000..e3ebfa73956e
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
@@ -0,0 +1,87 @@
+LIST "partner-jet-setup.txt"
+LIST "(C) Copyright 2010 Renesas Solutions Corp"
+LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
+
+LIST "RWT Setting"
+EW 0xE6020004, 0xA500
+EW 0xE6030004, 0xA500
+
+DD 0x01001000, 0x01001000
+
+LIST "GPIO Setting"
+EB 0xE6051013, 0xA2
+
+LIST "CPG"
+ED 0xE6150080, 0x00000180
+ED 0xE61500C0, 0x00000002
+
+WAIT 1, 0xFE40009C
+
+LIST "FRQCR"
+ED 0xE6150000, 0x2D1305C3
+ED 0xE61500E0, 0x9E40358E
+ED 0xE6150004, 0x80331050
+
+WAIT 1, 0xFE40009C
+
+ED 0xE61500E4, 0x00002000
+
+WAIT 1, 0xFE40009C
+
+LIST "PLL"
+ED 0xE6150028, 0x00004000
+
+WAIT 1, 0xFE40009C
+
+ED 0xE615002C, 0x93000040
+
+WAIT 1, 0xFE40009C
+
+LIST "BSC"
+ED 0xFEC10000, 0x00E0001B
+
+LIST "SBSC1"
+ED 0xFE400354, 0x01AD8000
+ED 0xFE400354, 0x01AD8001
+
+WAIT 5, 0xFE40009C
+
+ED 0xFE400008, 0xBCC90151
+ED 0xFE400040, 0x41774113
+ED 0xFE400044, 0x2712E229
+ED 0xFE400048, 0x20C18505
+ED 0xFE40004C, 0x00110209
+ED 0xFE400010, 0x00000087
+
+WAIT 10, 0xFE40009C
+
+ED 0xFE400084, 0x0000003F
+EB 0xFE500000, 0x00
+
+WAIT 5, 0xFE40009C
+
+ED 0xFE400084, 0x0000FF0A
+EB 0xFE500000, 0x00
+
+WAIT 1, 0xFE40009C
+
+ED 0xFE400084, 0x00002201
+EB 0xFE500000, 0x00
+ED 0xFE400084, 0x00000302
+EB 0xFE500000, 0x00
+EB 0xFE5C0000, 0x00
+ED 0xFE400008, 0xBCC90159
+ED 0xFE40008C, 0x88800004
+ED 0xFE400094, 0x00000004
+ED 0xFE400028, 0xA55A0032
+ED 0xFE40002C, 0xA55A000C
+ED 0xFE400020, 0xA55A2048
+ED 0xFE400008, 0xBCC90959
+
+LIST "Change CPGA setting"
+ED 0xE61500E0, 0x9E40352E
+ED 0xE6150004, 0x80331050
+
+WAIT 1, 0xFE40009C
+
+ED 0xE6150354, 0x00000002
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
new file mode 100644
index 000000000000..e3ebfa73956e
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
@@ -0,0 +1,87 @@
+LIST "partner-jet-setup.txt"
+LIST "(C) Copyright 2010 Renesas Solutions Corp"
+LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
+
+LIST "RWT Setting"
+EW 0xE6020004, 0xA500
+EW 0xE6030004, 0xA500
+
+DD 0x01001000, 0x01001000
+
+LIST "GPIO Setting"
+EB 0xE6051013, 0xA2
+
+LIST "CPG"
+ED 0xE6150080, 0x00000180
+ED 0xE61500C0, 0x00000002
+
+WAIT 1, 0xFE40009C
+
+LIST "FRQCR"
+ED 0xE6150000, 0x2D1305C3
+ED 0xE61500E0, 0x9E40358E
+ED 0xE6150004, 0x80331050
+
+WAIT 1, 0xFE40009C
+
+ED 0xE61500E4, 0x00002000
+
+WAIT 1, 0xFE40009C
+
+LIST "PLL"
+ED 0xE6150028, 0x00004000
+
+WAIT 1, 0xFE40009C
+
+ED 0xE615002C, 0x93000040
+
+WAIT 1, 0xFE40009C
+
+LIST "BSC"
+ED 0xFEC10000, 0x00E0001B
+
+LIST "SBSC1"
+ED 0xFE400354, 0x01AD8000
+ED 0xFE400354, 0x01AD8001
+
+WAIT 5, 0xFE40009C
+
+ED 0xFE400008, 0xBCC90151
+ED 0xFE400040, 0x41774113
+ED 0xFE400044, 0x2712E229
+ED 0xFE400048, 0x20C18505
+ED 0xFE40004C, 0x00110209
+ED 0xFE400010, 0x00000087
+
+WAIT 10, 0xFE40009C
+
+ED 0xFE400084, 0x0000003F
+EB 0xFE500000, 0x00
+
+WAIT 5, 0xFE40009C
+
+ED 0xFE400084, 0x0000FF0A
+EB 0xFE500000, 0x00
+
+WAIT 1, 0xFE40009C
+
+ED 0xFE400084, 0x00002201
+EB 0xFE500000, 0x00
+ED 0xFE400084, 0x00000302
+EB 0xFE500000, 0x00
+EB 0xFE5C0000, 0x00
+ED 0xFE400008, 0xBCC90159
+ED 0xFE40008C, 0x88800004
+ED 0xFE400094, 0x00000004
+ED 0xFE400028, 0xA55A0032
+ED 0xFE40002C, 0xA55A000C
+ED 0xFE400020, 0xA55A2048
+ED 0xFE400008, 0xBCC90959
+
+LIST "Change CPGA setting"
+ED 0xE61500E0, 0x9E40352E
+ED 0xE6150004, 0x80331050
+
+WAIT 1, 0xFE40009C
+
+ED 0xE6150354, 0x00000002
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index fa15b5f8a001..dcb714f4d75a 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -1,7 +1,10 @@
 #ifndef __ASM_MACH_IRQS_H
 #define __ASM_MACH_IRQS_H
 
-#define NR_IRQS         512
+#define NR_IRQS         1024
+
+/* GIC */
+#define gic_spi(nr)             ((nr) + 32)
 
 /* INTCA */
 #define evt2irq(evt)            (((evt) >> 5) - 16)
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index e4f9004e7103..5736efcca60c 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -455,6 +455,8 @@ enum {
         SHDMA_SLAVE_SDHI1_TX,
         SHDMA_SLAVE_SDHI2_RX,
         SHDMA_SLAVE_SDHI2_TX,
+        SHDMA_SLAVE_MMCIF_RX,
+        SHDMA_SLAVE_MMCIF_TX,
 };
 
 extern struct clk sh7372_extal1_clk;
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
new file mode 100644
index 000000000000..ceb2cdc92bf9
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -0,0 +1,467 @@
+#ifndef __ASM_SH73A0_H__
+#define __ASM_SH73A0_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function and MSEL switch
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+        /* Hardware manual Table 25-1 (GPIO) */
+        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
+
+        GPIO_PORT128, GPIO_PORT129,
+
+        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+
+        GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+        GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
+        GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
+
+        GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
+        GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
+
+        GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
+        GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
+
+        GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
+        GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
+
+        GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
+        GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
+
+        GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
+        GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
+
+        GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
+        GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
+
+        GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
+
+        GPIO_PORT288, GPIO_PORT289,
+
+        GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
+        GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
+
+        GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
+        GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
+
+        /* Table 25-1 (Function 0-7) */
+        GPIO_FN_VBUS_0,
+        GPIO_FN_GPI0,
+        GPIO_FN_GPI1,
+        GPIO_FN_GPI2,
+        GPIO_FN_GPI3,
+        GPIO_FN_GPI4,
+        GPIO_FN_GPI5,
+        GPIO_FN_GPI6,
+        GPIO_FN_GPI7,
+        GPIO_FN_SCIFA7_RXD,
+        GPIO_FN_SCIFA7_CTS_,
+        GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
+        GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
+        GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+        GPIO_FN_PORT16_VIO_CKOR,
+        GPIO_FN_SCIFA0_TXD,
+        GPIO_FN_SCIFA7_TXD,
+        GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+        GPIO_FN_GPO0,
+        GPIO_FN_GPO1,
+        GPIO_FN_GPO2, GPIO_FN_STATUS0,
+        GPIO_FN_GPO3, GPIO_FN_STATUS1,
+        GPIO_FN_GPO4, GPIO_FN_STATUS2,
+        GPIO_FN_VINT,
+        GPIO_FN_TCKON,
+        GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+        GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
+        GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+        GPIO_FN_PORT28_TPU1TO1,
+        GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
+        GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
+        GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
+        GPIO_FN_SCIFA4_TXD,
+        GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
+        GPIO_FN_SCIFA4_RTS_,
+        GPIO_FN_SCIFA4_CTS_,
+        GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
+        GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
+        GPIO_FN_FSIBOSLD,
+        GPIO_FN_FSIBISLD,
+        GPIO_FN_VACK,
+        GPIO_FN_XTAL1L,
+        GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
+        GPIO_FN_SCIFA0_RXD,
+        GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
+        GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
+        GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
+        GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
+        GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
+        GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
+        GPIO_FN_FSIAOMC,
+        GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
+
+        GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
+        GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
+        GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
+        GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
+        GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
+        GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
+        GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+        GPIO_FN_A0, GPIO_FN_BS_,
+        GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
+        GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
+        GPIO_FN_A14, GPIO_FN_KEYOUT5,
+        GPIO_FN_A15, GPIO_FN_KEYOUT4,
+        GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
+        GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
+        GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
+        GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
+        GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
+        GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
+        GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
+        GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
+        GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
+        GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
+        GPIO_FN_A26, GPIO_FN_KEYIN6,
+        GPIO_FN_KEYIN7,
+        GPIO_FN_D0_NAF0,
+        GPIO_FN_D1_NAF1,
+        GPIO_FN_D2_NAF2,
+        GPIO_FN_D3_NAF3,
+        GPIO_FN_D4_NAF4,
+        GPIO_FN_D5_NAF5,
+        GPIO_FN_D6_NAF6,
+        GPIO_FN_D7_NAF7,
+        GPIO_FN_D8_NAF8,
+        GPIO_FN_D9_NAF9,
+        GPIO_FN_D10_NAF10,
+        GPIO_FN_D11_NAF11,
+        GPIO_FN_D12_NAF12,
+        GPIO_FN_D13_NAF13,
+        GPIO_FN_D14_NAF14,
+        GPIO_FN_D15_NAF15,
+        GPIO_FN_CS4_,
+        GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
+        GPIO_FN_CS5B_, GPIO_FN_FCE1_,
+        GPIO_FN_CS6B_, GPIO_FN_DACK0,
+        GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+        GPIO_FN_WAIT_, GPIO_FN_DREQ0,
+        GPIO_FN_RD__FSC,
+        GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
+        GPIO_FN_WE1_,
+        GPIO_FN_FRB,
+        GPIO_FN_CKO,
+        GPIO_FN_NBRSTOUT_,
+        GPIO_FN_NBRST_,
+        GPIO_FN_BBIF2_TXD,
+        GPIO_FN_BBIF2_RXD,
+        GPIO_FN_BBIF2_SYNC,
+        GPIO_FN_BBIF2_SCK,
+        GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
+        GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
+        GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
+        GPIO_FN_SCIFA3_TXD,
+        GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
+        GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
+        GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
+        GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
+        GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
+        GPIO_FN_PORT115_I2C_SCL3,
+        GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
+        GPIO_FN_PORT116_I2C_SDA3,
+        GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
+        GPIO_FN_HSI_TX_FLAG,
+        GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
+        GPIO_FN_LCD2D0,
+
+        GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
+        GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
+        GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
+        GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
+        GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
+        GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
+        GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
+        GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
+        GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
+        GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
+        GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
+        GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
+        GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
+        GPIO_FN_LCD2D6,
+        GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
+        GPIO_FN_LCD2D7,
+        GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
+        GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
+        GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
+        GPIO_FN_LCD2D2,
+        GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
+        GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
+        GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
+        GPIO_FN_LCD2D4,
+        GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
+        GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
+        GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
+        GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
+        GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+        GPIO_FN_VIO_CKO,
+        GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
+        GPIO_FN_PORT149_KEYOUT9,
+        GPIO_FN_MFG0_IN2,
+        GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
+        GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
+        GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
+        GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
+        GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
+        GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
+        GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
+        GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
+        GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
+        GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
+        GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
+        GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
+        GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+        GPIO_FN_TPU3TO0,
+        GPIO_FN_LCDD0,
+        GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
+        GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
+        GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
+        GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
+        GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+        GPIO_FN_TPU2TO1,
+        GPIO_FN_LCDD6,
+        GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+        GPIO_FN_LCDD8, GPIO_FN_D16,
+        GPIO_FN_LCDD9, GPIO_FN_D17,
+        GPIO_FN_LCDD10, GPIO_FN_D18,
+        GPIO_FN_LCDD11, GPIO_FN_D19,
+        GPIO_FN_LCDD12, GPIO_FN_D20,
+        GPIO_FN_LCDD13, GPIO_FN_D21,
+        GPIO_FN_LCDD14, GPIO_FN_D22,
+        GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+        GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+        GPIO_FN_LCDD17, GPIO_FN_D25,
+        GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+        GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+        GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+        GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+        GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+        GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+        GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
+        GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
+        GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
+        GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+        GPIO_FN_PORT218_VIO_CKOR,
+        GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
+        GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
+        GPIO_FN_LCD2DCK_2,
+        GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
+        GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+        GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
+        GPIO_FN_PORT221_LCD2HSYN,
+        GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
+        GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
+
+        GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
+        GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
+        GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
+        GPIO_FN_SCIFA1_RXD,
+        GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
+        GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
+        GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
+        GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
+        GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
+        GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
+        GPIO_FN_LCD2D20,
+        GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
+        GPIO_FN_LCD2D21,
+        GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
+        GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
+        GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
+        GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
+        GPIO_FN_SCIFA6_TXD,
+        GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+        GPIO_FN_TPU4TO0,
+        GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
+        GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
+        GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
+        GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
+        GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
+        GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
+        GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
+        GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
+        GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
+        GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
+        GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
+        GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
+        GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+        GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
+        GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+        GPIO_FN_SDHICLK0,
+        GPIO_FN_SDHICD0,
+        GPIO_FN_SDHID0_0,
+        GPIO_FN_SDHID0_1,
+        GPIO_FN_SDHID0_2,
+        GPIO_FN_SDHID0_3,
+        GPIO_FN_SDHICMD0,
+        GPIO_FN_SDHIWP0,
+        GPIO_FN_SDHICLK1,
+        GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
+        GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
+        GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
+        GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
+        GPIO_FN_SDHICMD1,
+        GPIO_FN_SDHICLK2,
+        GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
+        GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
+        GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
+        GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
+        GPIO_FN_SDHICMD2,
+        GPIO_FN_MMCCLK0,
+        GPIO_FN_MMCD0_0,
+        GPIO_FN_MMCD0_1,
+        GPIO_FN_MMCD0_2,
+        GPIO_FN_MMCD0_3,
+        GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
+        GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
+        GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
+        GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
+        GPIO_FN_MMCCMD0,
+        GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
+        GPIO_FN_MCP_WAIT__MCP_FRB,
+        GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
+        GPIO_FN_MCP_D15_MCP_NAF15,
+        GPIO_FN_MCP_D14_MCP_NAF14,
+        GPIO_FN_MCP_D13_MCP_NAF13,
+        GPIO_FN_MCP_D12_MCP_NAF12,
+        GPIO_FN_MCP_D11_MCP_NAF11,
+        GPIO_FN_MCP_D10_MCP_NAF10,
+        GPIO_FN_MCP_D9_MCP_NAF9,
+        GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
+        GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
+
+        GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
+        GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
+        GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
+        GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
+        GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
+        GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
+        GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
+        GPIO_FN_MCP_NBRSTOUT_,
+        GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
+
+        /* MSEL2 special case */
+        GPIO_FN_TSIF2_TS_XX1,
+        GPIO_FN_TSIF2_TS_XX2,
+        GPIO_FN_TSIF2_TS_XX3,
+        GPIO_FN_TSIF2_TS_XX4,
+        GPIO_FN_TSIF2_TS_XX5,
+        GPIO_FN_TSIF1_TS_XX1,
+        GPIO_FN_TSIF1_TS_XX2,
+        GPIO_FN_TSIF1_TS_XX3,
+        GPIO_FN_TSIF1_TS_XX4,
+        GPIO_FN_TSIF1_TS_XX5,
+        GPIO_FN_TSIF0_TS_XX1,
+        GPIO_FN_TSIF0_TS_XX2,
+        GPIO_FN_TSIF0_TS_XX3,
+        GPIO_FN_TSIF0_TS_XX4,
+        GPIO_FN_TSIF0_TS_XX5,
+        GPIO_FN_MST1_TS_XX1,
+        GPIO_FN_MST1_TS_XX2,
+        GPIO_FN_MST1_TS_XX3,
+        GPIO_FN_MST1_TS_XX4,
+        GPIO_FN_MST1_TS_XX5,
+        GPIO_FN_MST0_TS_XX1,
+        GPIO_FN_MST0_TS_XX2,
+        GPIO_FN_MST0_TS_XX3,
+        GPIO_FN_MST0_TS_XX4,
+        GPIO_FN_MST0_TS_XX5,
+
+        /* MSEL3 special cases */
+        GPIO_FN_SDHI0_VCCQ_MC0_ON,
+        GPIO_FN_SDHI0_VCCQ_MC0_OFF,
+        GPIO_FN_DEBUG_MON_VIO,
+        GPIO_FN_DEBUG_MON_LCDD,
+        GPIO_FN_LCDC_LCDC0,
+        GPIO_FN_LCDC_LCDC1,
+
+        /* MSEL4 special cases */
+        GPIO_FN_IRQ9_MEM_INT,
+        GPIO_FN_IRQ9_MCP_INT,
+        GPIO_FN_A11,
+        GPIO_FN_KEYOUT8,
+        GPIO_FN_TPU4TO3,
+        GPIO_FN_RESETA_N_PU_ON,
+        GPIO_FN_RESETA_N_PU_OFF,
+        GPIO_FN_EDBGREQ_PD,
+        GPIO_FN_EDBGREQ_PU,
+
+        /* Functions with pull-ups */
+        GPIO_FN_KEYIN0_PU,
+        GPIO_FN_KEYIN1_PU,
+        GPIO_FN_KEYIN2_PU,
+        GPIO_FN_KEYIN3_PU,
+        GPIO_FN_KEYIN4_PU,
+        GPIO_FN_KEYIN5_PU,
+        GPIO_FN_KEYIN6_PU,
+        GPIO_FN_KEYIN7_PU,
+        GPIO_FN_SDHID1_0_PU,
+        GPIO_FN_SDHID1_1_PU,
+        GPIO_FN_SDHID1_2_PU,
+        GPIO_FN_SDHID1_3_PU,
+        GPIO_FN_SDHICMD1_PU,
+        GPIO_FN_MMCCMD0_PU,
+        GPIO_FN_MMCCMD1_PU,
+        GPIO_FN_FSIACK_PU,
+        GPIO_FN_FSIAILR_PU,
+        GPIO_FN_FSIAIBT_PU,
+        GPIO_FN_FSIAISLD_PU,
+};
+
+#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/smp.h b/arch/arm/mach-shmobile/include/mach/smp.h
new file mode 100644
index 000000000000..50db94e927ad
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/smp.h
@@ -0,0 +1,16 @@
+#ifndef __MACH_SMP_H
+#define __MACH_SMP_H
+
+#include <asm/hardware/gic.h>
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
+{
+#if defined(CONFIG_ARM_GIC)
+        gic_raise_softirq(mask, ipi);
+#endif
+}
+
+#endif
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
new file mode 100644
index 000000000000..6d6a205bcf90
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -0,0 +1,23 @@
+#ifndef ZBOOT_H
+#define ZBOOT_H
+
+#include <asm/mach-types.h>
+#include <mach/zboot_macros.h>
+
+/**************************************************
+ *
+ *              board specific settings
+ *
+ **************************************************/
+
+#ifdef CONFIG_MACH_AP4EVB
+#define MACH_TYPE       MACH_TYPE_AP4EVB
+#include "mach/head-ap4evb.txt"
+#elif CONFIG_MACH_MACKEREL
+#define MACH_TYPE       MACH_TYPE_MACKEREL
+#include "mach/head-mackerel.txt"
+#else
+#error "unsupported board."
+#endif
+
+#endif /* ZBOOT_H */
diff --git a/arch/arm/mach-shmobile/include/mach/zboot_macros.h b/arch/arm/mach-shmobile/include/mach/zboot_macros.h
new file mode 100644
index 000000000000..aa6111fbc989
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/zboot_macros.h
@@ -0,0 +1,65 @@
+#ifndef __ZBOOT_MACRO_H
+#define __ZBOOT_MACRO_H
+
+/* The LIST command is used to include comments in the script */
+.macro  LIST comment
+.endm
+
+/* The ED command is used to write a 32-bit word */
+.macro ED, addr, data
+        LDR     r0, 1f
+        LDR     r1, 2f
+        STR     r1, [r0]
+        B       3f
+1 :     .long   \addr
+2 :     .long   \data
+3 :
+.endm
+
+/* The EW command is used to write a 16-bit word */
+.macro EW, addr, data
+        LDR     r0, 1f
+        LDR     r1, 2f
+        STRH    r1, [r0]
+        B       3f
+1 :     .long   \addr
+2 :     .long   \data
+3 :
+.endm
+
+/* The EB command is used to write an 8-bit word */
+.macro EB, addr, data
+        LDR     r0, 1f
+        LDR     r1, 2f
+        STRB    r1, [r0]
+        B       3f
+1 :     .long   \addr
+2 :     .long   \data
+3 :
+.endm
+
+/* The WAIT command is used to delay the execution */
+.macro  WAIT, time, reg
+        LDR     r1, 1f
+        LDR     r0, 2f
+        STR     r0, [r1]
+10 :
+        LDR     r0, [r1]
+        CMP     r0, #0x00000000
+        BNE     10b
+        NOP
+        B       3f
+1 :     .long   \reg
+2 :     .long   \time * 100
+3 :
+.endm
+
+/* The DD command is used to read a 32-bit word */
+.macro  DD, start, end
+        LDR     r1, 1f
+        B       2f
+1 :     .long   \start
+2 :
+.endm
+
+#endif /* __ZBOOT_MACRO_H */
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
new file mode 100644
index 000000000000..322d8d57cbcf
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -0,0 +1,267 @@
+/*
+ * sh73a0 processor support - INTC hardware block
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sh_intc.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources INTCS */
+        PINTCS_PINT1, PINTCS_PINT2,
+        RTDMAC_0_DEI0, RTDMAC_0_DEI1, RTDMAC_0_DEI2, RTDMAC_0_DEI3,
+        CEU, MFI, BBIF2, VPU, TSIF1, _3DG_SGX543, _2DDMAC_2DDM0,
+        RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR,
+        KEYSC_KEY, VINT, MSIOF,
+        TMU0_TUNI00, TMU0_TUNI01, TMU0_TUNI02,
+        CMT0, TSIF0, CMT2, LMB, MSUG, MSU_MSU, MSU_MSU2,
+        CTI, RWDT0, ICB, PEP, ASA, JPU_JPEG, LCDC, LCRC,
+        RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
+        RTDMAC_3_DEI10, RTDMAC_3_DEI11,
+        FRC, GCU, LCDC1, CSIRX,
+        DSITX0_DSITX00, DSITX0_DSITX01,
+        SPU2_SPU0, SPU2_SPU1, FSI,
+        TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12,
+        TSIF2, CMT4, MFIS2, CPORTS2R, TSG, DMASCH1, SCUW,
+        VIO60, VIO61, CEU21, CSI21, DSITX1_DSITX10, DSITX1_DSITX11,
+        DISP, DSRV, EMUX2_EMUX20I, EMUX2_EMUX21I,
+        MSTIF0_MST00I, MSTIF0_MST01I, MSTIF1_MST10I, MSTIF1_MST11I,
+        SPUV,
+
+        /* interrupt groups INTCS */
+        RTDMAC_0, RTDMAC_1, RTDMAC_2, RTDMAC_3,
+        DSITX0, SPU2, TMU1, MSU,
+};
+
+static struct intc_vect intcs_vectors[] = {
+        INTCS_VECT(PINTCS_PINT1, 0x0600), INTCS_VECT(PINTCS_PINT2, 0x0620),
+        INTCS_VECT(RTDMAC_0_DEI0, 0x0800), INTCS_VECT(RTDMAC_0_DEI1, 0x0820),
+        INTCS_VECT(RTDMAC_0_DEI2, 0x0840), INTCS_VECT(RTDMAC_0_DEI3, 0x0860),
+        INTCS_VECT(CEU, 0x0880), INTCS_VECT(MFI, 0x0900),
+        INTCS_VECT(BBIF2, 0x0960), INTCS_VECT(VPU, 0x0980),
+        INTCS_VECT(TSIF1, 0x09a0), INTCS_VECT(_3DG_SGX543, 0x09e0),
+        INTCS_VECT(_2DDMAC_2DDM0, 0x0a00),
+        INTCS_VECT(RTDMAC_1_DEI4, 0x0b80), INTCS_VECT(RTDMAC_1_DEI5, 0x0ba0),
+        INTCS_VECT(RTDMAC_1_DADERR, 0x0bc0),
+        INTCS_VECT(KEYSC_KEY, 0x0be0), INTCS_VECT(VINT, 0x0c80),
+        INTCS_VECT(MSIOF, 0x0d20),
+        INTCS_VECT(TMU0_TUNI00, 0x0e80), INTCS_VECT(TMU0_TUNI01, 0x0ea0),
+        INTCS_VECT(TMU0_TUNI02, 0x0ec0),
+        INTCS_VECT(CMT0, 0x0f00), INTCS_VECT(TSIF0, 0x0f20),
+        INTCS_VECT(CMT2, 0x0f40), INTCS_VECT(LMB, 0x0f60),
+        INTCS_VECT(MSUG, 0x0f80),
+        INTCS_VECT(MSU_MSU, 0x0fa0), INTCS_VECT(MSU_MSU2, 0x0fc0),
+        INTCS_VECT(CTI, 0x0400), INTCS_VECT(RWDT0, 0x0440),
+        INTCS_VECT(ICB, 0x0480), INTCS_VECT(PEP, 0x04a0),
+        INTCS_VECT(ASA, 0x04c0), INTCS_VECT(JPU_JPEG, 0x0560),
+        INTCS_VECT(LCDC, 0x0580), INTCS_VECT(LCRC, 0x05a0),
+        INTCS_VECT(RTDMAC_2_DEI6, 0x1300), INTCS_VECT(RTDMAC_2_DEI7, 0x1320),
+        INTCS_VECT(RTDMAC_2_DEI8, 0x1340), INTCS_VECT(RTDMAC_2_DEI9, 0x1360),
+        INTCS_VECT(RTDMAC_3_DEI10, 0x1380), INTCS_VECT(RTDMAC_3_DEI11, 0x13a0),
+        INTCS_VECT(FRC, 0x1700), INTCS_VECT(GCU, 0x1760),
+        INTCS_VECT(LCDC1, 0x1780), INTCS_VECT(CSIRX, 0x17a0),
+        INTCS_VECT(DSITX0_DSITX00, 0x17c0), INTCS_VECT(DSITX0_DSITX01, 0x17e0),
+        INTCS_VECT(SPU2_SPU0, 0x1800), INTCS_VECT(SPU2_SPU1, 0x1820),
+        INTCS_VECT(FSI, 0x1840),
+        INTCS_VECT(TMU1_TUNI10, 0x1900), INTCS_VECT(TMU1_TUNI11, 0x1920),
+        INTCS_VECT(TMU1_TUNI12, 0x1940),
+        INTCS_VECT(TSIF2, 0x1960), INTCS_VECT(CMT4, 0x1980),
+        INTCS_VECT(MFIS2, 0x1a00), INTCS_VECT(CPORTS2R, 0x1a20),
+        INTCS_VECT(TSG, 0x1ae0), INTCS_VECT(DMASCH1, 0x1b00),
+        INTCS_VECT(SCUW, 0x1b40),
+        INTCS_VECT(VIO60, 0x1b60), INTCS_VECT(VIO61, 0x1b80),
+        INTCS_VECT(CEU21, 0x1ba0), INTCS_VECT(CSI21, 0x1be0),
+        INTCS_VECT(DSITX1_DSITX10, 0x1c00), INTCS_VECT(DSITX1_DSITX11, 0x1c20),
+        INTCS_VECT(DISP, 0x1c40), INTCS_VECT(DSRV, 0x1c60),
+        INTCS_VECT(EMUX2_EMUX20I, 0x1c80), INTCS_VECT(EMUX2_EMUX21I, 0x1ca0),
+        INTCS_VECT(MSTIF0_MST00I, 0x1cc0), INTCS_VECT(MSTIF0_MST01I, 0x1ce0),
+        INTCS_VECT(MSTIF1_MST10I, 0x1d00), INTCS_VECT(MSTIF1_MST11I, 0x1d20),
+        INTCS_VECT(SPUV, 0x2300),
+};
+
+static struct intc_group intcs_groups[] __initdata = {
+        INTC_GROUP(RTDMAC_0, RTDMAC_0_DEI0, RTDMAC_0_DEI1,
+                   RTDMAC_0_DEI2, RTDMAC_0_DEI3),
+        INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI4, RTDMAC_1_DEI5, RTDMAC_1_DADERR),
+        INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI6, RTDMAC_2_DEI7,
+                   RTDMAC_2_DEI8, RTDMAC_2_DEI9),
+        INTC_GROUP(RTDMAC_3, RTDMAC_3_DEI10, RTDMAC_3_DEI11),
+        INTC_GROUP(TMU1, TMU1_TUNI12, TMU1_TUNI11, TMU1_TUNI10),
+        INTC_GROUP(DSITX0, DSITX0_DSITX00, DSITX0_DSITX01),
+        INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
+        INTC_GROUP(MSU, MSU_MSU, MSU_MSU2),
+};
+
+static struct intc_mask_reg intcs_mask_registers[] = {
+        { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
+          { 0, 0, 0, CEU,
+            0, 0, 0, 0 } },
+        { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
+          { 0, 0, 0, VPU,
+            BBIF2, 0, 0, MFI } },
+        { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
+          { 0, 0, 0, _2DDMAC_2DDM0,
+            0, ASA, PEP, ICB } },
+        { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
+          { 0, 0, 0, CTI,
+            JPU_JPEG, 0, LCRC, LCDC } },
+        { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
+          { KEYSC_KEY, RTDMAC_1_DADERR, RTDMAC_1_DEI5, RTDMAC_1_DEI4,
+            RTDMAC_0_DEI3, RTDMAC_0_DEI2, RTDMAC_0_DEI1, RTDMAC_0_DEI0 } },
+        { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
+          { 0, 0, MSIOF, 0,
+            _3DG_SGX543, 0, 0, 0 } },
+        { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
+          { 0, TMU0_TUNI02, TMU0_TUNI01, TMU0_TUNI00,
+            0, 0, 0, 0 } },
+        { 0xffd201a0, 0xffd201e0, 8, /* IMR8SA / IMCR8SA */
+          { 0, 0, 0, 0,
+            0, MSU_MSU, MSU_MSU2, MSUG } },
+        { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
+          { 0, RWDT0, CMT2, CMT0,
+            0, 0, 0, 0 } },
+        { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
+          { 0, 0, 0, 0,
+            0, TSIF1, LMB, TSIF0 } },
+        { 0xffd201b0, 0xffd201f0, 8, /* IMR12SA / IMCR12SA */
+          { 0, 0, 0, 0,
+            0, 0, PINTCS_PINT2, PINTCS_PINT1 } },
+        { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
+          { RTDMAC_2_DEI6, RTDMAC_2_DEI7, RTDMAC_2_DEI8, RTDMAC_2_DEI9,
+            RTDMAC_3_DEI10, RTDMAC_3_DEI11, 0, 0 } },
+        { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
+          { FRC, 0, 0, GCU,
+            LCDC1, CSIRX, DSITX0_DSITX00, DSITX0_DSITX01 } },
+        { 0xffd50194, 0xffd501d4, 8, /* IMR5SA3 / IMCR5SA3 */
+          { SPU2_SPU0, SPU2_SPU1, FSI, 0,
+            0, 0, 0, 0 } },
+        { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
+          { TMU1_TUNI10, TMU1_TUNI11, TMU1_TUNI12, 0,
+            TSIF2, CMT4, 0, 0 } },
+        { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
+          { MFIS2, CPORTS2R, 0, 0,
+            0, 0, 0, TSG } },
+        { 0xffd501a0, 0xffd501e0, 8, /* IMR8SA3 / IMCR8SA3 */
+          { DMASCH1, 0, SCUW, VIO60,
+            VIO61, CEU21, 0, CSI21 } },
+        { 0xffd501a4, 0xffd501e4, 8, /* IMR9SA3 / IMCR9SA3 */
+          { DSITX1_DSITX10, DSITX1_DSITX11, DISP, DSRV,
+            EMUX2_EMUX20I, EMUX2_EMUX21I, MSTIF0_MST00I, MSTIF0_MST01I } },
+        { 0xffd501a8, 0xffd501e8, 8, /* IMR10SA3 / IMCR10SA3 */
+          { MSTIF0_MST00I, MSTIF0_MST01I, 0, 0,
+            0, 0, 0, 0  } },
+        { 0xffd60180, 0xffd601c0, 8, /* IMR0SA4 / IMCR0SA4 */
+          { SPUV, 0, 0, 0,
+            0, 0, 0, 0  } },
+};
+
+/* Priority is needed for INTCA to receive the INTCS interrupt */
+static struct intc_prio_reg intcs_prio_registers[] = {
+        { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC_2DDM0, ICB } },
+        { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
+        { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
+        { 0xffd2000c, 0, 16, 4, /* IPRDS */ { PINTCS_PINT1, PINTCS_PINT2,
+                                              0, 0 } },
+        { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_0, CEU, MFI, VPU } },
+        { 0xffd20014, 0, 16, 4, /* IPRFS */ { KEYSC_KEY, RTDMAC_1,
+                                              CMT2, CMT0 } },
+        { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_TUNI00, TMU0_TUNI01,
+                                              TMU0_TUNI02, TSIF1 } },
+        { 0xffd2001c, 0, 16, 4, /* IPRHS */ { VINT, 0, 0, 0 } },
+        { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, 0 } },
+        { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, _3DG_SGX543, MSUG, MSU } },
+        { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, ASA, LMB, PEP } },
+        { 0xffd20030, 0, 16, 4, /* IPRMS */ { 0, 0, 0, RWDT0 } },
+        { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC_2, 0, 0, 0 } },
+        { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC_3, 0, 0, 0 } },
+        { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { FRC, 0, 0, 0 } },
+        { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX0, 0 } },
+        { 0xffd50028, 0, 16, 4, /* IPRKS3 */ { SPU2, 0, FSI, 0 } },
+        { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, TSIF2 } },
+        { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, 0, 0, 0 } },
+        { 0xffd50038, 0, 16, 4, /* IPROS3 */ { MFIS2, CPORTS2R, 0, 0 } },
+        { 0xffd50040, 0, 16, 4, /* IPRQS3 */ { DMASCH1, 0, SCUW, VIO60 } },
+        { 0xffd50044, 0, 16, 4, /* IPRRS3 */ { VIO61, CEU21, 0, CSI21 } },
+        { 0xffd50048, 0, 16, 4, /* IPRSS3 */ { DSITX1_DSITX10, DSITX1_DSITX11,
+                                               DISP, DSRV } },
+        { 0xffd5004c, 0, 16, 4, /* IPRTS3 */ { EMUX2_EMUX20I, EMUX2_EMUX21I,
+                                               MSTIF0_MST00I, MSTIF0_MST01I } },
+        { 0xffd50050, 0, 16, 4, /* IPRUS3 */ { MSTIF1_MST10I, MSTIF1_MST11I,
+                                               0, 0 } },
+        { 0xffd60000, 0, 16, 4, /* IPRAS4 */ { SPUV, 0, 0, 0 } },
+};
+
+static struct resource intcs_resources[] __initdata = {
+        [0] = {
+                .start  = 0xffd20000,
+                .end    = 0xffd201ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xffd50000,
+                .end    = 0xffd501ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = 0xffd60000,
+                .end    = 0xffd601ff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct intc_desc intcs_desc __initdata = {
+        .name = "sh73a0-intcs",
+        .resource = intcs_resources,
+        .num_resources = ARRAY_SIZE(intcs_resources),
+        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
+                           intcs_prio_registers, NULL, NULL),
+};
+
+static struct irqaction sh73a0_intcs_cascade;
+
+static irqreturn_t sh73a0_intcs_demux(int irq, void *dev_id)
+{
+        unsigned int evtcodeas = ioread32((void __iomem *)dev_id);
+
+        generic_handle_irq(intcs_evt2irq(evtcodeas));
+
+        return IRQ_HANDLED;
+}
+
+void __init sh73a0_init_irq(void)
+{
+        void __iomem *gic_base = __io(0xf0001000);
+        void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+
+        gic_init(0, 29, gic_base, gic_base);
+
+        register_intc_controller(&intcs_desc);
+
+        /* demux using INTEVTSA */
+        sh73a0_intcs_cascade.name = "INTCS cascade";
+        sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
+        sh73a0_intcs_cascade.dev_id = intevtsa;
+        setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
+}
diff --git a/arch/arm/mach-shmobile/localtimer.c b/arch/arm/mach-shmobile/localtimer.c
new file mode 100644
index 000000000000..2111c28b724e
--- /dev/null
+++ b/arch/arm/mach-shmobile/localtimer.c
@@ -0,0 +1,25 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile - local timer portion
+ *
+ * Copyright (C) 2010  Magnus Damm
+ *
+ * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+        evt->irq = 29;
+        twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
new file mode 100644
index 000000000000..3eed44eb98b4
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -0,0 +1,2746 @@
+/*
+ * sh73a0 processor support - PFC hardware block
+ *
+ * Copyright (C) 2010 Renesas Solutions Corp.
+ * Copyright (C) 2010 NISHIMOTO Hiroki
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <mach/sh73a0.h>
+
+#define _1(fn, pfx, sfx) fn(pfx, sfx)
+
+#define _10(fn, pfx, sfx)                               \
+        _1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx),       \
+        _1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx),       \
+        _1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx),       \
+        _1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx),       \
+        _1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
+
+#define _310(fn, pfx, sfx)                              \
+        _10(fn, pfx,    sfx), _10(fn, pfx##1, sfx),     \
+        _10(fn, pfx##2, sfx), _10(fn, pfx##3, sfx),     \
+        _10(fn, pfx##4, sfx), _10(fn, pfx##5, sfx),     \
+        _10(fn, pfx##6, sfx), _10(fn, pfx##7, sfx),     \
+        _10(fn, pfx##8, sfx), _10(fn, pfx##9, sfx),     \
+        _10(fn, pfx##10, sfx),                          \
+        _1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx),   \
+        _1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx),   \
+        _1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx),   \
+        _1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx),   \
+        _1(fn, pfx##118, sfx),                          \
+        _1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx),   \
+        _10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx),   \
+        _10(fn, pfx##15, sfx),                          \
+        _1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx),   \
+        _1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx),   \
+        _1(fn, pfx##164, sfx),                          \
+        _1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx),   \
+        _1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx),   \
+        _1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx),   \
+        _1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx),   \
+        _10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx),   \
+        _10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx),   \
+        _10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx),   \
+        _10(fn, pfx##26, sfx), _10(fn, pfx##27, sfx),   \
+        _1(fn, pfx##280, sfx), _1(fn, pfx##281, sfx),   \
+        _1(fn, pfx##282, sfx),                          \
+        _1(fn, pfx##288, sfx), _1(fn, pfx##289, sfx),   \
+        _10(fn, pfx##29, sfx), _10(fn, pfx##30, sfx)
+
+#define _PORT(pfx, sfx) pfx##_##sfx
+#define PORT_310(str) _310(_PORT, PORT, str)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        PORT_310(DATA),                 /* PORT0_DATA -> PORT309_DATA */
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        PORT_310(IN),                   /* PORT0_IN -> PORT309_IN */
+        PINMUX_INPUT_END,
+
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PORT_310(IN_PU),                /* PORT0_IN_PU -> PORT309_IN_PU */
+        PINMUX_INPUT_PULLUP_END,
+
+        PINMUX_INPUT_PULLDOWN_BEGIN,
+        PORT_310(IN_PD),                /* PORT0_IN_PD -> PORT309_IN_PD */
+        PINMUX_INPUT_PULLDOWN_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        PORT_310(OUT),                  /* PORT0_OUT -> PORT309_OUT */
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        PORT_310(FN_IN),                /* PORT0_FN_IN -> PORT309_FN_IN */
+        PORT_310(FN_OUT),               /* PORT0_FN_OUT -> PORT309_FN_OUT */
+        PORT_310(FN0),                  /* PORT0_FN0 -> PORT309_FN0 */
+        PORT_310(FN1),                  /* PORT0_FN1 -> PORT309_FN1 */
+        PORT_310(FN2),                  /* PORT0_FN2 -> PORT309_FN2 */
+        PORT_310(FN3),                  /* PORT0_FN3 -> PORT309_FN3 */
+        PORT_310(FN4),                  /* PORT0_FN4 -> PORT309_FN4 */
+        PORT_310(FN5),                  /* PORT0_FN5 -> PORT309_FN5 */
+        PORT_310(FN6),                  /* PORT0_FN6 -> PORT309_FN6 */
+        PORT_310(FN7),                  /* PORT0_FN7 -> PORT309_FN7 */
+
+        MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+        MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+        MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+        MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+        MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+        MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+        MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+        MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+        MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+        MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+        MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+        MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+        MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+        MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+        MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+        MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+        MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+        MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+        MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+        MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+        MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+        MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+        MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+        MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+        MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+        MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+        MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+        MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+        MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+        MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+        MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+        MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+        MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+        MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+        MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+        MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+        MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+        MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+        MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+        MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+        MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+        MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        /* Hardware manual Table 25-1 (Function 0-7) */
+        VBUS_0_MARK,
+        GPI0_MARK,
+        GPI1_MARK,
+        GPI2_MARK,
+        GPI3_MARK,
+        GPI4_MARK,
+        GPI5_MARK,
+        GPI6_MARK,
+        GPI7_MARK,
+        SCIFA7_RXD_MARK,
+        SCIFA7_CTS__MARK,
+        GPO7_MARK, MFG0_OUT2_MARK,
+        GPO6_MARK, MFG1_OUT2_MARK,
+        GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
+        SCIFA0_TXD_MARK,
+        SCIFA7_TXD_MARK,
+        SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
+        GPO0_MARK,
+        GPO1_MARK,
+        GPO2_MARK, STATUS0_MARK,
+        GPO3_MARK, STATUS1_MARK,
+        GPO4_MARK, STATUS2_MARK,
+        VINT_MARK,
+        TCKON_MARK,
+        XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
+        MFG0_OUT1_MARK, PORT27_IROUT_MARK,
+        XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
+        PORT28_TPU1TO1_MARK,
+        SIM_RST_MARK, PORT29_TPU1TO1_MARK,
+        SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
+        SIM_D_MARK, PORT31_IROUT_MARK,
+        SCIFA4_TXD_MARK,
+        SCIFA4_RXD_MARK, XWUP_MARK,
+        SCIFA4_RTS__MARK,
+        SCIFA4_CTS__MARK,
+        FSIBOBT_MARK, FSIBIBT_MARK,
+        FSIBOLR_MARK, FSIBILR_MARK,
+        FSIBOSLD_MARK,
+        FSIBISLD_MARK,
+        VACK_MARK,
+        XTAL1L_MARK,
+        SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
+        SCIFA0_RXD_MARK,
+        SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
+        FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
+        FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
+        FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
+        FSICISLD_MARK, FSIDISLD_MARK,
+        FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
+        FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
+
+        FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
+        FSIAOSLD_MARK, BBIF2_TXD2_MARK,
+        FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
+        PORT53_FSICSPDIF_MARK,
+        FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
+        FSICCK_MARK, FSICOMC_MARK,
+        FSIAISLD_MARK, TPU0TO0_MARK,
+        A0_MARK, BS__MARK,
+        A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
+        A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
+        A14_MARK, KEYOUT5_MARK,
+        A15_MARK, KEYOUT4_MARK,
+        A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
+        A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
+        A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
+        A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
+        A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
+        A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
+        A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
+        A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
+        A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
+        A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
+        A26_MARK, KEYIN6_MARK,
+        KEYIN7_MARK,
+        D0_NAF0_MARK,
+        D1_NAF1_MARK,
+        D2_NAF2_MARK,
+        D3_NAF3_MARK,
+        D4_NAF4_MARK,
+        D5_NAF5_MARK,
+        D6_NAF6_MARK,
+        D7_NAF7_MARK,
+        D8_NAF8_MARK,
+        D9_NAF9_MARK,
+        D10_NAF10_MARK,
+        D11_NAF11_MARK,
+        D12_NAF12_MARK,
+        D13_NAF13_MARK,
+        D14_NAF14_MARK,
+        D15_NAF15_MARK,
+        CS4__MARK,
+        CS5A__MARK, PORT91_RDWR_MARK,
+        CS5B__MARK, FCE1__MARK,
+        CS6B__MARK, DACK0_MARK,
+        FCE0__MARK, CS6A__MARK,
+        WAIT__MARK, DREQ0_MARK,
+        RD__FSC_MARK,
+        WE0__FWE_MARK, RDWR_FWE_MARK,
+        WE1__MARK,
+        FRB_MARK,
+        CKO_MARK,
+        NBRSTOUT__MARK,
+        NBRST__MARK,
+        BBIF2_TXD_MARK,
+        BBIF2_RXD_MARK,
+        BBIF2_SYNC_MARK,
+        BBIF2_SCK_MARK,
+        SCIFA3_CTS__MARK, MFG3_IN2_MARK,
+        SCIFA3_RXD_MARK, MFG3_IN1_MARK,
+        BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
+        SCIFA3_TXD_MARK,
+        HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
+        HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
+        HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
+        HSI_TX_READY_MARK, BBIF1_TXD_MARK,
+        HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
+        PORT115_I2C_SCL3_MARK,
+        HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
+        PORT116_I2C_SDA3_MARK,
+        HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
+        HSI_TX_FLAG_MARK,
+        VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
+
+        VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
+        VIO2_HD_MARK, LCD2D1_MARK,
+        VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
+        VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
+        PORT131_KEYOUT11_MARK, LCD2D11_MARK,
+        VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
+        PORT132_KEYOUT10_MARK, LCD2D12_MARK,
+        VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
+        VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
+        VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
+        VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
+        VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
+        VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
+        VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
+        VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
+        VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
+        VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
+        VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
+        VIO2_D5_MARK, LCD2D3_MARK,
+        VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
+        VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
+        PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
+        VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
+        LCD2D18_MARK,
+        VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
+        VIO_CKO_MARK,
+        A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
+        MFG0_IN2_MARK,
+        TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
+        TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
+        TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
+        SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
+        SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
+        SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
+        SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
+        DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
+        PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
+        PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
+        PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
+        PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
+        PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
+        LCDD0_MARK,
+        LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
+        LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
+        LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
+        LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
+        LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
+        LCDD6_MARK,
+        LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
+        LCDD8_MARK, D16_MARK,
+        LCDD9_MARK, D17_MARK,
+        LCDD10_MARK, D18_MARK,
+        LCDD11_MARK, D19_MARK,
+        LCDD12_MARK, D20_MARK,
+        LCDD13_MARK, D21_MARK,
+        LCDD14_MARK, D22_MARK,
+        LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
+        LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
+        LCDD17_MARK, D25_MARK,
+        LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
+        LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
+        LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
+        LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
+        LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
+        LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
+        LCDDCK_MARK, LCDWR__MARK,
+        LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
+        VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
+        LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
+        PORT218_VIO_CKOR_MARK,
+        LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
+        MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
+        LCDVSYN_MARK, LCDVSYN2_MARK,
+        LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
+        MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
+        LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
+        VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
+
+        SCIFA1_TXD_MARK, OVCN2_MARK,
+        EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
+        SCIFA1_RTS__MARK, IDIN_MARK,
+        SCIFA1_RXD_MARK,
+        SCIFA1_CTS__MARK, MFG1_IN1_MARK,
+        MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
+        MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
+        MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
+        MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
+        MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
+        MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
+        MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
+        MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
+        MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
+        MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
+        SCIFA6_TXD_MARK,
+        PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
+        PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
+        PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
+        PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
+        MSIOF2R_RXD_MARK,
+        PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
+        MSIOF2R_TXD_MARK,
+        PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
+        TPU1TO0_MARK,
+        PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
+        TPU3TO1_MARK,
+        PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
+        TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
+        PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
+        MSIOF2R_TSYNC_MARK,
+        SDHICLK0_MARK,
+        SDHICD0_MARK,
+        SDHID0_0_MARK,
+        SDHID0_1_MARK,
+        SDHID0_2_MARK,
+        SDHID0_3_MARK,
+        SDHICMD0_MARK,
+        SDHIWP0_MARK,
+        SDHICLK1_MARK,
+        SDHID1_0_MARK, TS_SPSYNC2_MARK,
+        SDHID1_1_MARK, TS_SDAT2_MARK,
+        SDHID1_2_MARK, TS_SDEN2_MARK,
+        SDHID1_3_MARK, TS_SCK2_MARK,
+        SDHICMD1_MARK,
+        SDHICLK2_MARK,
+        SDHID2_0_MARK, TS_SPSYNC4_MARK,
+        SDHID2_1_MARK, TS_SDAT4_MARK,
+        SDHID2_2_MARK, TS_SDEN4_MARK,
+        SDHID2_3_MARK, TS_SCK4_MARK,
+        SDHICMD2_MARK,
+        MMCCLK0_MARK,
+        MMCD0_0_MARK,
+        MMCD0_1_MARK,
+        MMCD0_2_MARK,
+        MMCD0_3_MARK,
+        MMCD0_4_MARK, TS_SPSYNC5_MARK,
+        MMCD0_5_MARK, TS_SDAT5_MARK,
+        MMCD0_6_MARK, TS_SDEN5_MARK,
+        MMCD0_7_MARK, TS_SCK5_MARK,
+        MMCCMD0_MARK,
+        RESETOUTS__MARK, EXTAL2OUT_MARK,
+        MCP_WAIT__MCP_FRB_MARK,
+        MCP_CKO_MARK, MMCCLK1_MARK,
+        MCP_D15_MCP_NAF15_MARK,
+        MCP_D14_MCP_NAF14_MARK,
+        MCP_D13_MCP_NAF13_MARK,
+        MCP_D12_MCP_NAF12_MARK,
+        MCP_D11_MCP_NAF11_MARK,
+        MCP_D10_MCP_NAF10_MARK,
+        MCP_D9_MCP_NAF9_MARK,
+        MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
+        MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
+
+        MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
+        MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
+        MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
+        MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
+        MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
+        MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
+        MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
+        MCP_NBRSTOUT__MARK,
+        MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
+
+        /* MSEL2 special cases */
+        TSIF2_TS_XX1_MARK,
+        TSIF2_TS_XX2_MARK,
+        TSIF2_TS_XX3_MARK,
+        TSIF2_TS_XX4_MARK,
+        TSIF2_TS_XX5_MARK,
+        TSIF1_TS_XX1_MARK,
+        TSIF1_TS_XX2_MARK,
+        TSIF1_TS_XX3_MARK,
+        TSIF1_TS_XX4_MARK,
+        TSIF1_TS_XX5_MARK,
+        TSIF0_TS_XX1_MARK,
+        TSIF0_TS_XX2_MARK,
+        TSIF0_TS_XX3_MARK,
+        TSIF0_TS_XX4_MARK,
+        TSIF0_TS_XX5_MARK,
+        MST1_TS_XX1_MARK,
+        MST1_TS_XX2_MARK,
+        MST1_TS_XX3_MARK,
+        MST1_TS_XX4_MARK,
+        MST1_TS_XX5_MARK,
+        MST0_TS_XX1_MARK,
+        MST0_TS_XX2_MARK,
+        MST0_TS_XX3_MARK,
+        MST0_TS_XX4_MARK,
+        MST0_TS_XX5_MARK,
+
+        /* MSEL3 special cases */
+        SDHI0_VCCQ_MC0_ON_MARK,
+        SDHI0_VCCQ_MC0_OFF_MARK,
+        DEBUG_MON_VIO_MARK,
+        DEBUG_MON_LCDD_MARK,
+        LCDC_LCDC0_MARK,
+        LCDC_LCDC1_MARK,
+
+        /* MSEL4 special cases */
+        IRQ9_MEM_INT_MARK,
+        IRQ9_MCP_INT_MARK,
+        A11_MARK,
+        KEYOUT8_MARK,
+        TPU4TO3_MARK,
+        RESETA_N_PU_ON_MARK,
+        RESETA_N_PU_OFF_MARK,
+        EDBGREQ_PD_MARK,
+        EDBGREQ_PU_MARK,
+
+        /* Functions with pull-ups */
+        KEYIN0_PU_MARK,
+        KEYIN1_PU_MARK,
+        KEYIN2_PU_MARK,
+        KEYIN3_PU_MARK,
+        KEYIN4_PU_MARK,
+        KEYIN5_PU_MARK,
+        KEYIN6_PU_MARK,
+        KEYIN7_PU_MARK,
+        SDHID1_0_PU_MARK,
+        SDHID1_1_PU_MARK,
+        SDHID1_2_PU_MARK,
+        SDHID1_3_PU_MARK,
+        SDHICMD1_PU_MARK,
+        MMCCMD0_PU_MARK,
+        MMCCMD1_PU_MARK,
+        FSIACK_PU_MARK,
+        FSIAILR_PU_MARK,
+        FSIAIBT_PU_MARK,
+        FSIAISLD_PU_MARK,
+
+        PINMUX_MARK_END,
+};
+
+#define PORT_DATA_I(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
+
+#define PORT_DATA_I_PD(nr)      \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_IN, PORT##nr##_IN_PD)
+
+#define PORT_DATA_I_PU(nr)      \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_IN, PORT##nr##_IN_PU)
+
+#define PORT_DATA_I_PU_PD(nr)   \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_IN, PORT##nr##_IN_PD,        \
+                                PORT##nr##_IN_PU)
+
+#define PORT_DATA_O(nr) \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT)
+
+#define PORT_DATA_IO(nr)        \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN)
+
+#define PORT_DATA_IO_PD(nr)     \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN,          \
+                                PORT##nr##_IN_PD)
+
+#define PORT_DATA_IO_PU(nr)     \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN,          \
+                                PORT##nr##_IN_PU)
+
+#define PORT_DATA_IO_PU_PD(nr)  \
+        PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,    \
+                                PORT##nr##_OUT, PORT##nr##_IN,          \
+                                PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+static pinmux_enum_t pinmux_data[] = {
+        /* specify valid pin states for each pin in GPIO mode */
+
+        /* Table 25-1 (I/O and Pull U/D) */
+        PORT_DATA_I_PD(0),
+        PORT_DATA_I_PU(1),
+        PORT_DATA_I_PU(2),
+        PORT_DATA_I_PU(3),
+        PORT_DATA_I_PU(4),
+        PORT_DATA_I_PU(5),
+        PORT_DATA_I_PU(6),
+        PORT_DATA_I_PU(7),
+        PORT_DATA_I_PU(8),
+        PORT_DATA_I_PD(9),
+        PORT_DATA_I_PD(10),
+        PORT_DATA_I_PU_PD(11),
+        PORT_DATA_IO_PU_PD(12),
+        PORT_DATA_IO_PU_PD(13),
+        PORT_DATA_IO_PU_PD(14),
+        PORT_DATA_IO_PU_PD(15),
+        PORT_DATA_IO_PD(16),
+        PORT_DATA_IO_PD(17),
+        PORT_DATA_IO_PU(18),
+        PORT_DATA_IO_PU(19),
+        PORT_DATA_O(20),
+        PORT_DATA_O(21),
+        PORT_DATA_O(22),
+        PORT_DATA_O(23),
+        PORT_DATA_O(24),
+        PORT_DATA_I_PD(25),
+        PORT_DATA_I_PD(26),
+        PORT_DATA_IO_PU(27),
+        PORT_DATA_IO_PU(28),
+        PORT_DATA_IO_PD(29),
+        PORT_DATA_IO_PD(30),
+        PORT_DATA_IO_PU(31),
+        PORT_DATA_IO_PD(32),
+        PORT_DATA_I_PU_PD(33),
+        PORT_DATA_IO_PD(34),
+        PORT_DATA_I_PU_PD(35),
+        PORT_DATA_IO_PD(36),
+        PORT_DATA_IO(37),
+        PORT_DATA_O(38),
+        PORT_DATA_I_PU(39),
+        PORT_DATA_I_PU_PD(40),
+        PORT_DATA_O(41),
+        PORT_DATA_IO_PD(42),
+        PORT_DATA_IO_PU_PD(43),
+        PORT_DATA_IO_PU_PD(44),
+        PORT_DATA_IO_PD(45),
+        PORT_DATA_IO_PD(46),
+        PORT_DATA_IO_PD(47),
+        PORT_DATA_I_PD(48),
+        PORT_DATA_IO_PU_PD(49),
+        PORT_DATA_IO_PD(50),
+
+        PORT_DATA_IO_PD(51),
+        PORT_DATA_O(52),
+        PORT_DATA_IO_PU_PD(53),
+        PORT_DATA_IO_PU_PD(54),
+        PORT_DATA_IO_PD(55),
+        PORT_DATA_I_PU_PD(56),
+        PORT_DATA_IO(57),
+        PORT_DATA_IO(58),
+        PORT_DATA_IO(59),
+        PORT_DATA_IO(60),
+        PORT_DATA_IO(61),
+        PORT_DATA_IO_PD(62),
+        PORT_DATA_IO_PD(63),
+        PORT_DATA_IO_PU_PD(64),
+        PORT_DATA_IO_PD(65),
+        PORT_DATA_IO_PU_PD(66),
+        PORT_DATA_IO_PU_PD(67),
+        PORT_DATA_IO_PU_PD(68),
+        PORT_DATA_IO_PU_PD(69),
+        PORT_DATA_IO_PU_PD(70),
+        PORT_DATA_IO_PU_PD(71),
+        PORT_DATA_IO_PU_PD(72),
+        PORT_DATA_I_PU_PD(73),
+        PORT_DATA_IO_PU(74),
+        PORT_DATA_IO_PU(75),
+        PORT_DATA_IO_PU(76),
+        PORT_DATA_IO_PU(77),
+        PORT_DATA_IO_PU(78),
+        PORT_DATA_IO_PU(79),
+        PORT_DATA_IO_PU(80),
+        PORT_DATA_IO_PU(81),
+        PORT_DATA_IO_PU(82),
+        PORT_DATA_IO_PU(83),
+        PORT_DATA_IO_PU(84),
+        PORT_DATA_IO_PU(85),
+        PORT_DATA_IO_PU(86),
+        PORT_DATA_IO_PU(87),
+        PORT_DATA_IO_PU(88),
+        PORT_DATA_IO_PU(89),
+        PORT_DATA_O(90),
+        PORT_DATA_IO_PU(91),
+        PORT_DATA_O(92),
+        PORT_DATA_IO_PU(93),
+        PORT_DATA_O(94),
+        PORT_DATA_I_PU_PD(95),
+        PORT_DATA_IO(96),
+        PORT_DATA_IO(97),
+        PORT_DATA_IO(98),
+        PORT_DATA_I_PU(99),
+        PORT_DATA_O(100),
+        PORT_DATA_O(101),
+        PORT_DATA_I_PU(102),
+        PORT_DATA_IO_PD(103),
+        PORT_DATA_I_PU_PD(104),
+        PORT_DATA_I_PD(105),
+        PORT_DATA_I_PD(106),
+        PORT_DATA_I_PU_PD(107),
+        PORT_DATA_I_PU_PD(108),
+        PORT_DATA_IO_PD(109),
+        PORT_DATA_IO_PD(110),
+        PORT_DATA_IO_PU_PD(111),
+        PORT_DATA_IO_PU_PD(112),
+        PORT_DATA_IO_PU_PD(113),
+        PORT_DATA_IO_PD(114),
+        PORT_DATA_IO_PU(115),
+        PORT_DATA_IO_PU(116),
+        PORT_DATA_IO_PU_PD(117),
+        PORT_DATA_IO_PU_PD(118),
+        PORT_DATA_IO_PD(128),
+
+        PORT_DATA_IO_PD(129),
+        PORT_DATA_IO_PU_PD(130),
+        PORT_DATA_IO_PD(131),
+        PORT_DATA_IO_PD(132),
+        PORT_DATA_IO_PD(133),
+        PORT_DATA_IO_PU_PD(134),
+        PORT_DATA_IO_PU_PD(135),
+        PORT_DATA_IO_PU_PD(136),
+        PORT_DATA_IO_PU_PD(137),
+        PORT_DATA_IO_PD(138),
+        PORT_DATA_IO_PD(139),
+        PORT_DATA_IO_PD(140),
+        PORT_DATA_IO_PD(141),
+        PORT_DATA_IO_PD(142),
+        PORT_DATA_IO_PD(143),
+        PORT_DATA_IO_PU_PD(144),
+        PORT_DATA_IO_PD(145),
+        PORT_DATA_IO_PU_PD(146),
+        PORT_DATA_IO_PU_PD(147),
+        PORT_DATA_IO_PU_PD(148),
+        PORT_DATA_IO_PU_PD(149),
+        PORT_DATA_I_PU_PD(150),
+        PORT_DATA_IO_PU_PD(151),
+        PORT_DATA_IO_PU_PD(152),
+        PORT_DATA_IO_PD(153),
+        PORT_DATA_IO_PD(154),
+        PORT_DATA_I_PU_PD(155),
+        PORT_DATA_IO_PU_PD(156),
+        PORT_DATA_I_PD(157),
+        PORT_DATA_IO_PD(158),
+        PORT_DATA_IO_PU_PD(159),
+        PORT_DATA_IO_PU_PD(160),
+        PORT_DATA_I_PU_PD(161),
+        PORT_DATA_I_PU_PD(162),
+        PORT_DATA_IO_PU_PD(163),
+        PORT_DATA_I_PU_PD(164),
+        PORT_DATA_IO_PD(192),
+        PORT_DATA_IO_PU_PD(193),
+        PORT_DATA_IO_PD(194),
+        PORT_DATA_IO_PU_PD(195),
+        PORT_DATA_IO_PD(196),
+        PORT_DATA_IO_PD(197),
+        PORT_DATA_IO_PD(198),
+        PORT_DATA_IO_PD(199),
+        PORT_DATA_IO_PU_PD(200),
+        PORT_DATA_IO_PU_PD(201),
+        PORT_DATA_IO_PU_PD(202),
+        PORT_DATA_IO_PU_PD(203),
+        PORT_DATA_IO_PU_PD(204),
+        PORT_DATA_IO_PU_PD(205),
+        PORT_DATA_IO_PU_PD(206),
+        PORT_DATA_IO_PD(207),
+        PORT_DATA_IO_PD(208),
+        PORT_DATA_IO_PD(209),
+        PORT_DATA_IO_PD(210),
+        PORT_DATA_IO_PD(211),
+        PORT_DATA_IO_PD(212),
+        PORT_DATA_IO_PD(213),
+        PORT_DATA_IO_PU_PD(214),
+        PORT_DATA_IO_PU_PD(215),
+        PORT_DATA_IO_PD(216),
+        PORT_DATA_IO_PD(217),
+        PORT_DATA_O(218),
+        PORT_DATA_IO_PD(219),
+        PORT_DATA_IO_PD(220),
+        PORT_DATA_IO_PU_PD(221),
+        PORT_DATA_IO_PU_PD(222),
+        PORT_DATA_I_PU_PD(223),
+        PORT_DATA_I_PU_PD(224),
+
+        PORT_DATA_IO_PU_PD(225),
+        PORT_DATA_O(226),
+        PORT_DATA_IO_PU_PD(227),
+        PORT_DATA_I_PU_PD(228),
+        PORT_DATA_I_PD(229),
+        PORT_DATA_IO(230),
+        PORT_DATA_IO_PU_PD(231),
+        PORT_DATA_IO_PU_PD(232),
+        PORT_DATA_I_PU_PD(233),
+        PORT_DATA_IO_PU_PD(234),
+        PORT_DATA_IO_PU_PD(235),
+        PORT_DATA_IO_PU_PD(236),
+        PORT_DATA_IO_PD(237),
+        PORT_DATA_IO_PU_PD(238),
+        PORT_DATA_IO_PU_PD(239),
+        PORT_DATA_IO_PU_PD(240),
+        PORT_DATA_O(241),
+        PORT_DATA_I_PD(242),
+        PORT_DATA_IO_PU_PD(243),
+        PORT_DATA_IO_PU_PD(244),
+        PORT_DATA_IO_PU_PD(245),
+        PORT_DATA_IO_PU_PD(246),
+        PORT_DATA_IO_PU_PD(247),
+        PORT_DATA_IO_PU_PD(248),
+        PORT_DATA_IO_PU_PD(249),
+        PORT_DATA_IO_PU_PD(250),
+        PORT_DATA_IO_PU_PD(251),
+        PORT_DATA_IO_PU_PD(252),
+        PORT_DATA_IO_PU_PD(253),
+        PORT_DATA_IO_PU_PD(254),
+        PORT_DATA_IO_PU_PD(255),
+        PORT_DATA_IO_PU_PD(256),
+        PORT_DATA_IO_PU_PD(257),
+        PORT_DATA_IO_PU_PD(258),
+        PORT_DATA_IO_PU_PD(259),
+        PORT_DATA_IO_PU_PD(260),
+        PORT_DATA_IO_PU_PD(261),
+        PORT_DATA_IO_PU_PD(262),
+        PORT_DATA_IO_PU_PD(263),
+        PORT_DATA_IO_PU_PD(264),
+        PORT_DATA_IO_PU_PD(265),
+        PORT_DATA_IO_PU_PD(266),
+        PORT_DATA_IO_PU_PD(267),
+        PORT_DATA_IO_PU_PD(268),
+        PORT_DATA_IO_PU_PD(269),
+        PORT_DATA_IO_PU_PD(270),
+        PORT_DATA_IO_PU_PD(271),
+        PORT_DATA_IO_PU_PD(272),
+        PORT_DATA_IO_PU_PD(273),
+        PORT_DATA_IO_PU_PD(274),
+        PORT_DATA_IO_PU_PD(275),
+        PORT_DATA_IO_PU_PD(276),
+        PORT_DATA_IO_PU_PD(277),
+        PORT_DATA_IO_PU_PD(278),
+        PORT_DATA_IO_PU_PD(279),
+        PORT_DATA_IO_PU_PD(280),
+        PORT_DATA_O(281),
+        PORT_DATA_O(282),
+        PORT_DATA_I_PU(288),
+        PORT_DATA_IO_PU_PD(289),
+        PORT_DATA_IO_PU_PD(290),
+        PORT_DATA_IO_PU_PD(291),
+        PORT_DATA_IO_PU_PD(292),
+        PORT_DATA_IO_PU_PD(293),
+        PORT_DATA_IO_PU_PD(294),
+        PORT_DATA_IO_PU_PD(295),
+        PORT_DATA_IO_PU_PD(296),
+        PORT_DATA_IO_PU_PD(297),
+        PORT_DATA_IO_PU_PD(298),
+
+        PORT_DATA_IO_PU_PD(299),
+        PORT_DATA_IO_PU_PD(300),
+        PORT_DATA_IO_PU_PD(301),
+        PORT_DATA_IO_PU_PD(302),
+        PORT_DATA_IO_PU_PD(303),
+        PORT_DATA_IO_PU_PD(304),
+        PORT_DATA_IO_PU_PD(305),
+        PORT_DATA_O(306),
+        PORT_DATA_O(307),
+        PORT_DATA_I_PU(308),
+        PORT_DATA_O(309),
+
+        /* Table 25-1 (Function 0-7) */
+        PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
+        PINMUX_DATA(GPI0_MARK, PORT1_FN1),
+        PINMUX_DATA(GPI1_MARK, PORT2_FN1),
+        PINMUX_DATA(GPI2_MARK, PORT3_FN1),
+        PINMUX_DATA(GPI3_MARK, PORT4_FN1),
+        PINMUX_DATA(GPI4_MARK, PORT5_FN1),
+        PINMUX_DATA(GPI5_MARK, PORT6_FN1),
+        PINMUX_DATA(GPI6_MARK, PORT7_FN1),
+        PINMUX_DATA(GPI7_MARK, PORT8_FN1),
+        PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
+        PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
+        PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
+        PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
+        PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
+        PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
+        PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
+        PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
+        PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
+        PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
+        PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
+        PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
+        PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
+        PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
+        PINMUX_DATA(GPO0_MARK, PORT20_FN1),
+        PINMUX_DATA(GPO1_MARK, PORT21_FN1),
+        PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
+        PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
+        PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
+        PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
+        PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
+        PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
+        PINMUX_DATA(VINT_MARK, PORT25_FN1),
+        PINMUX_DATA(TCKON_MARK, PORT26_FN1),
+        PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
+        PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
+                MSEL2CR_MSEL16_1), \
+        PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
+                MSEL2CR_MSEL18_0), \
+        PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
+        PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
+        PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
+        PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
+                MSEL2CR_MSEL16_1), \
+        PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
+                MSEL2CR_MSEL18_0), \
+        PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
+        PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
+        PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
+        PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
+        PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
+        PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
+        PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
+        PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
+        PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
+        PINMUX_DATA(XWUP_MARK, PORT33_FN3),
+        PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
+        PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
+        PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
+        PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
+        PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
+        PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
+        PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
+        PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
+        PINMUX_DATA(VACK_MARK, PORT40_FN1),
+        PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
+        PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
+        PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
+        PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
+        PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
+        PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
+        PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
+        PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
+        PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
+        PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
+        PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
+        PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
+        PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
+        PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
+        PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
+        PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
+        PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
+        PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
+        PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
+        PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
+        PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
+        PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
+        PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
+        PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
+        PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
+        PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
+
+        PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
+        PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
+        PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
+        PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
+        PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
+        PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
+        PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
+        PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
+        PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
+        PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
+        PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
+        PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
+        PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
+        PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
+        PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
+        PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
+        PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
+        PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
+        PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
+        PINMUX_DATA(A0_MARK, PORT57_FN1), \
+        PINMUX_DATA(BS__MARK, PORT57_FN2),
+        PINMUX_DATA(A12_MARK, PORT58_FN1), \
+        PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
+        PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
+        PINMUX_DATA(A13_MARK, PORT59_FN1), \
+        PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
+        PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
+        PINMUX_DATA(A14_MARK, PORT60_FN1), \
+        PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
+        PINMUX_DATA(A15_MARK, PORT61_FN1), \
+        PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
+        PINMUX_DATA(A16_MARK, PORT62_FN1), \
+        PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
+        PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A17_MARK, PORT63_FN1), \
+        PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
+        PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A18_MARK, PORT64_FN1), \
+        PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
+        PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A19_MARK, PORT65_FN1), \
+        PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
+        PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A20_MARK, PORT66_FN1), \
+        PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
+        PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A21_MARK, PORT67_FN1), \
+        PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
+        PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A22_MARK, PORT68_FN1), \
+        PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
+        PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A23_MARK, PORT69_FN1), \
+        PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
+        PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A24_MARK, PORT70_FN1), \
+        PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
+        PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A25_MARK, PORT71_FN1), \
+        PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
+        PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
+        PINMUX_DATA(A26_MARK, PORT72_FN1), \
+        PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
+        PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
+        PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
+        PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
+        PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
+        PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
+        PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
+        PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
+        PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
+        PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
+        PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
+        PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
+        PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
+        PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
+        PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
+        PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
+        PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
+        PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
+        PINMUX_DATA(CS4__MARK, PORT90_FN1),
+        PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
+        PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
+        PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
+        PINMUX_DATA(FCE1__MARK, PORT92_FN2),
+        PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
+        PINMUX_DATA(DACK0_MARK, PORT93_FN4),
+        PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
+        PINMUX_DATA(CS6A__MARK, PORT94_FN2),
+        PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
+        PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
+        PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
+        PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
+        PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
+        PINMUX_DATA(WE1__MARK, PORT98_FN1),
+        PINMUX_DATA(FRB_MARK, PORT99_FN1),
+        PINMUX_DATA(CKO_MARK, PORT100_FN1),
+        PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
+        PINMUX_DATA(NBRST__MARK, PORT102_FN1),
+        PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
+        PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
+        PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
+        PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
+        PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
+        PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
+        PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
+        PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
+        PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
+        PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
+        PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
+        PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
+        PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
+        PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
+        PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
+        PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
+        PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
+        PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
+        PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
+        PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
+        PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
+        PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
+        PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
+        PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
+        PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
+        PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
+        PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
+        PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
+        PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
+        PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
+        PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
+        PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
+        PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
+        PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
+        PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
+        PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
+
+        PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
+        PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
+        PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
+        PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
+        PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
+        PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
+        PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
+                MSEL4CR_MSEL10_1), \
+        PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
+        PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
+        PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
+        PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
+        PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
+        PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
+        PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
+        PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
+        PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
+        PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
+        PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
+        PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
+        PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
+        PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
+        PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
+        PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
+        PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
+        PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
+        PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
+        PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
+        PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
+        PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
+        PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
+        PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
+        PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
+        PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
+        PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
+        PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
+        PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
+        PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
+        PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
+        PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
+        PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
+        PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
+        PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
+        PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
+        PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
+        PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
+        PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
+        PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
+        PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
+        PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
+        PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
+        PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
+        PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
+        PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
+        PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
+        PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
+        PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
+        PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
+        PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
+        PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
+        PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
+        PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
+        PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
+        PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
+        PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
+        PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
+        PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
+        PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
+        PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
+        PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
+        PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
+        PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
+        PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
+        PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
+        PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
+        PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
+        PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
+        PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
+        PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
+        PINMUX_DATA(A27_MARK, PORT149_FN1), \
+        PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
+        PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
+        PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
+        PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
+        PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
+        PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
+        PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
+        PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
+        PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
+        PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
+        PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
+        PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
+        PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
+        PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
+        PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
+        PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
+        PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
+        PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
+        PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
+                MSEL4CR_MSEL10_0),
+        PINMUX_DATA(DINT__MARK, PORT158_FN1), \
+        PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
+        PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
+        PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
+        PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
+        PINMUX_DATA(NMI_MARK, PORT159_FN3),
+        PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
+        PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
+        PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
+        PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
+        PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
+        PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
+        PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
+        PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
+        PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
+        PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
+        PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
+        PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_1), \
+        PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
+        PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
+        PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_1), \
+        PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
+        PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
+        PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_1), \
+        PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
+        PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
+        PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_1),
+        PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
+        PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_1), \
+        PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
+        PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
+        PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
+        PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
+        PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
+        PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
+        PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
+        PINMUX_DATA(D16_MARK, PORT200_FN6),
+        PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
+        PINMUX_DATA(D17_MARK, PORT201_FN6),
+        PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
+        PINMUX_DATA(D18_MARK, PORT202_FN6),
+        PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
+        PINMUX_DATA(D19_MARK, PORT203_FN6),
+        PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
+        PINMUX_DATA(D20_MARK, PORT204_FN6),
+        PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
+        PINMUX_DATA(D21_MARK, PORT205_FN6),
+        PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
+        PINMUX_DATA(D22_MARK, PORT206_FN6),
+        PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
+        PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D23_MARK, PORT207_FN6),
+        PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
+        PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D24_MARK, PORT208_FN6),
+        PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
+        PINMUX_DATA(D25_MARK, PORT209_FN6),
+        PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
+        PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
+        PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D26_MARK, PORT210_FN6),
+        PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
+        PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D27_MARK, PORT211_FN6),
+        PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
+        PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
+        PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D28_MARK, PORT212_FN6),
+        PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
+        PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
+        PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D29_MARK, PORT213_FN6),
+        PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
+        PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
+        PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D30_MARK, PORT214_FN6),
+        PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
+        PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
+        PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(D31_MARK, PORT215_FN6),
+        PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
+        PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
+        PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
+        PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
+        PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
+        PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_1), \
+        PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
+        PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
+        PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
+        PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
+        PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
+        PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
+        PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
+        PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
+        PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
+        PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
+        PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_1), \
+        PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
+        PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
+        PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
+        PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
+        PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
+        PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
+        PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
+        PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_1), \
+        PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
+        PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
+        PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
+        PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
+        PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
+        PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
+        PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_1), \
+        PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
+
+        PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
+        PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
+        PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
+        PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
+        PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
+        PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
+        PINMUX_DATA(IDIN_MARK, PORT227_FN4),
+        PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
+        PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
+        PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
+        PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
+        PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
+        PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
+        PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
+        PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
+        PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
+        PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
+        PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
+        PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
+        PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
+        PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_0), \
+        PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
+        PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
+        PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
+        PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_0), \
+        PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
+        PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
+        PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
+                MSEL2CR_MSEL16_0),
+        PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
+        PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
+                MSEL2CR_MSEL16_0),
+        PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
+        PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_0), \
+        PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
+        PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
+        PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
+                MSEL4CR_MSEL26_0), \
+        PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
+        PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
+        PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
+        PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
+        PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
+        PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
+        PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
+        PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
+        PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
+        PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
+        PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_0), \
+        PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
+        PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
+        PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
+        PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_0), \
+        PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
+        PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
+        PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
+        PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_0), \
+        PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
+        PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
+        PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
+        PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_0), \
+        PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
+        PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
+        PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
+        PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
+                MSEL4CR_MSEL20_0), \
+        PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
+        PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
+        PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
+        PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
+                MSEL2CR_MSEL18_0), \
+        PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
+        PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
+        PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
+        PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
+                MSEL2CR_MSEL18_0), \
+        PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
+        PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
+        PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
+        PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
+        PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
+        PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
+        PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
+        PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
+        PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
+        PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
+        PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
+        PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
+        PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
+        PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
+        PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
+        PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
+        PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
+        PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
+        PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
+        PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
+        PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
+        PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
+        PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
+        PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
+        PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
+        PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
+        PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
+        PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
+        PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
+        PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
+        PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
+        PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
+        PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), \
+        PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
+        PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
+        PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
+        PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
+        PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
+        PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
+        PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
+        PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
+        PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
+        PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
+        PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
+        PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
+        PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
+        PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
+        PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
+        PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
+
+        PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
+        PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
+        PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
+        PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
+        PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
+        PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
+        PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
+        PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
+        PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
+        PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
+        PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
+
+        /* MSEL2 special cases */
+        PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+                MSEL2CR_MSEL12_0),
+        PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
+                MSEL2CR_MSEL12_1),
+        PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+                MSEL2CR_MSEL12_0),
+        PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
+                MSEL2CR_MSEL12_1),
+        PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
+                MSEL2CR_MSEL12_0),
+        PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+                MSEL2CR_MSEL9_0),
+        PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
+                MSEL2CR_MSEL9_1),
+        PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+                MSEL2CR_MSEL9_0),
+        PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
+                MSEL2CR_MSEL9_1),
+        PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
+                MSEL2CR_MSEL9_0),
+        PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+                MSEL2CR_MSEL6_0),
+        PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
+                MSEL2CR_MSEL6_1),
+        PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+                MSEL2CR_MSEL6_0),
+        PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
+                MSEL2CR_MSEL6_1),
+        PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
+                MSEL2CR_MSEL6_0),
+        PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+                MSEL2CR_MSEL3_0),
+        PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
+                MSEL2CR_MSEL3_1),
+        PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+                MSEL2CR_MSEL3_0),
+        PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
+                MSEL2CR_MSEL3_1),
+        PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
+                MSEL2CR_MSEL3_0),
+        PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+                MSEL2CR_MSEL0_0),
+        PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
+                MSEL2CR_MSEL0_1),
+        PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+                MSEL2CR_MSEL0_0),
+        PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
+                MSEL2CR_MSEL0_1),
+        PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
+                MSEL2CR_MSEL0_0),
+
+        /* MSEL3 special cases */
+        PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
+        PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
+        PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
+        PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
+        PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
+        PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
+
+        /* MSEL4 special cases */
+        PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
+        PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
+        PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
+        PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
+        PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
+        PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
+        PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
+        PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
+        PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
+
+        /* Functions with pull-ups */
+        PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU),
+        PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU),
+        PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU),
+        PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU),
+        PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU),
+        PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU),
+        PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
+        PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
+
+        PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_IN_PU, PORT259_FN1),
+        PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_IN_PU, PORT260_FN1),
+        PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_IN_PU, PORT261_FN1),
+        PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_IN_PU, PORT262_FN1),
+        PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_IN_PU, PORT263_FN1),
+
+        PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
+                MSEL4CR_MSEL15_0),
+        PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT279_IN_PU,
+                MSEL4CR_MSEL15_1),
+        PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
+        PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
+        PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
+        PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
+};
+
+#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
+#define GPIO_PORT_310() _310(_GPIO_PORT, , unused)
+#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+
+static struct pinmux_gpio pinmux_gpios[] = {
+        GPIO_PORT_310(),
+
+        /* Table 25-1 (Functions 0-7) */
+        GPIO_FN(VBUS_0),
+        GPIO_FN(GPI0),
+        GPIO_FN(GPI1),
+        GPIO_FN(GPI2),
+        GPIO_FN(GPI3),
+        GPIO_FN(GPI4),
+        GPIO_FN(GPI5),
+        GPIO_FN(GPI6),
+        GPIO_FN(GPI7),
+        GPIO_FN(SCIFA7_RXD),
+        GPIO_FN(SCIFA7_CTS_),
+        GPIO_FN(GPO7), \
+        GPIO_FN(MFG0_OUT2),
+        GPIO_FN(GPO6), \
+        GPIO_FN(MFG1_OUT2),
+        GPIO_FN(GPO5), \
+        GPIO_FN(SCIFA0_SCK), \
+        GPIO_FN(FSICOSLDT3), \
+        GPIO_FN(PORT16_VIO_CKOR),
+        GPIO_FN(SCIFA0_TXD),
+        GPIO_FN(SCIFA7_TXD),
+        GPIO_FN(SCIFA7_RTS_), \
+        GPIO_FN(PORT19_VIO_CKO2),
+        GPIO_FN(GPO0),
+        GPIO_FN(GPO1),
+        GPIO_FN(GPO2), \
+        GPIO_FN(STATUS0),
+        GPIO_FN(GPO3), \
+        GPIO_FN(STATUS1),
+        GPIO_FN(GPO4), \
+        GPIO_FN(STATUS2),
+        GPIO_FN(VINT),
+        GPIO_FN(TCKON),
+        GPIO_FN(XDVFS1), \
+        GPIO_FN(PORT27_I2C_SCL2), \
+        GPIO_FN(PORT27_I2C_SCL3), \
+        GPIO_FN(MFG0_OUT1), \
+        GPIO_FN(PORT27_IROUT),
+        GPIO_FN(XDVFS2), \
+        GPIO_FN(PORT28_I2C_SDA2), \
+        GPIO_FN(PORT28_I2C_SDA3), \
+        GPIO_FN(PORT28_TPU1TO1),
+        GPIO_FN(SIM_RST), \
+        GPIO_FN(PORT29_TPU1TO1),
+        GPIO_FN(SIM_CLK), \
+        GPIO_FN(PORT30_VIO_CKOR),
+        GPIO_FN(SIM_D), \
+        GPIO_FN(PORT31_IROUT),
+        GPIO_FN(SCIFA4_TXD),
+        GPIO_FN(SCIFA4_RXD), \
+        GPIO_FN(XWUP),
+        GPIO_FN(SCIFA4_RTS_),
+        GPIO_FN(SCIFA4_CTS_),
+        GPIO_FN(FSIBOBT), \
+        GPIO_FN(FSIBIBT),
+        GPIO_FN(FSIBOLR), \
+        GPIO_FN(FSIBILR),
+        GPIO_FN(FSIBOSLD),
+        GPIO_FN(FSIBISLD),
+        GPIO_FN(VACK),
+        GPIO_FN(XTAL1L),
+        GPIO_FN(SCIFA0_RTS_), \
+        GPIO_FN(FSICOSLDT2),
+        GPIO_FN(SCIFA0_RXD),
+        GPIO_FN(SCIFA0_CTS_), \
+        GPIO_FN(FSICOSLDT1),
+        GPIO_FN(FSICOBT), \
+        GPIO_FN(FSICIBT), \
+        GPIO_FN(FSIDOBT), \
+        GPIO_FN(FSIDIBT),
+        GPIO_FN(FSICOLR), \
+        GPIO_FN(FSICILR), \
+        GPIO_FN(FSIDOLR), \
+        GPIO_FN(FSIDILR),
+        GPIO_FN(FSICOSLD), \
+        GPIO_FN(PORT47_FSICSPDIF),
+        GPIO_FN(FSICISLD), \
+        GPIO_FN(FSIDISLD),
+        GPIO_FN(FSIACK), \
+        GPIO_FN(PORT49_IRDA_OUT), \
+        GPIO_FN(PORT49_IROUT), \
+        GPIO_FN(FSIAOMC),
+        GPIO_FN(FSIAOLR), \
+        GPIO_FN(BBIF2_TSYNC2), \
+        GPIO_FN(TPU2TO2), \
+        GPIO_FN(FSIAILR),
+
+        GPIO_FN(FSIAOBT), \
+        GPIO_FN(BBIF2_TSCK2), \
+        GPIO_FN(TPU2TO3), \
+        GPIO_FN(FSIAIBT),
+        GPIO_FN(FSIAOSLD), \
+        GPIO_FN(BBIF2_TXD2),
+        GPIO_FN(FSIASPDIF), \
+        GPIO_FN(PORT53_IRDA_IN), \
+        GPIO_FN(TPU3TO3), \
+        GPIO_FN(FSIBSPDIF), \
+        GPIO_FN(PORT53_FSICSPDIF),
+        GPIO_FN(FSIBCK), \
+        GPIO_FN(PORT54_IRDA_FIRSEL), \
+        GPIO_FN(TPU3TO2), \
+        GPIO_FN(FSIBOMC), \
+        GPIO_FN(FSICCK), \
+        GPIO_FN(FSICOMC),
+        GPIO_FN(FSIAISLD), \
+        GPIO_FN(TPU0TO0),
+        GPIO_FN(A0), \
+        GPIO_FN(BS_),
+        GPIO_FN(A12), \
+        GPIO_FN(PORT58_KEYOUT7), \
+        GPIO_FN(TPU4TO2),
+        GPIO_FN(A13), \
+        GPIO_FN(PORT59_KEYOUT6), \
+        GPIO_FN(TPU0TO1),
+        GPIO_FN(A14), \
+        GPIO_FN(KEYOUT5),
+        GPIO_FN(A15), \
+        GPIO_FN(KEYOUT4),
+        GPIO_FN(A16), \
+        GPIO_FN(KEYOUT3), \
+        GPIO_FN(MSIOF0_SS1),
+        GPIO_FN(A17), \
+        GPIO_FN(KEYOUT2), \
+        GPIO_FN(MSIOF0_TSYNC),
+        GPIO_FN(A18), \
+        GPIO_FN(KEYOUT1), \
+        GPIO_FN(MSIOF0_TSCK),
+        GPIO_FN(A19), \
+        GPIO_FN(KEYOUT0), \
+        GPIO_FN(MSIOF0_TXD),
+        GPIO_FN(A20), \
+        GPIO_FN(KEYIN0), \
+        GPIO_FN(MSIOF0_RSCK),
+        GPIO_FN(A21), \
+        GPIO_FN(KEYIN1), \
+        GPIO_FN(MSIOF0_RSYNC),
+        GPIO_FN(A22), \
+        GPIO_FN(KEYIN2), \
+        GPIO_FN(MSIOF0_MCK0),
+        GPIO_FN(A23), \
+        GPIO_FN(KEYIN3), \
+        GPIO_FN(MSIOF0_MCK1),
+        GPIO_FN(A24), \
+        GPIO_FN(KEYIN4), \
+        GPIO_FN(MSIOF0_RXD),
+        GPIO_FN(A25), \
+        GPIO_FN(KEYIN5), \
+        GPIO_FN(MSIOF0_SS2),
+        GPIO_FN(A26), \
+        GPIO_FN(KEYIN6),
+        GPIO_FN(KEYIN7),
+        GPIO_FN(D0_NAF0),
+        GPIO_FN(D1_NAF1),
+        GPIO_FN(D2_NAF2),
+        GPIO_FN(D3_NAF3),
+        GPIO_FN(D4_NAF4),
+        GPIO_FN(D5_NAF5),
+        GPIO_FN(D6_NAF6),
+        GPIO_FN(D7_NAF7),
+        GPIO_FN(D8_NAF8),
+        GPIO_FN(D9_NAF9),
+        GPIO_FN(D10_NAF10),
+        GPIO_FN(D11_NAF11),
+        GPIO_FN(D12_NAF12),
+        GPIO_FN(D13_NAF13),
+        GPIO_FN(D14_NAF14),
+        GPIO_FN(D15_NAF15),
+        GPIO_FN(CS4_),
+        GPIO_FN(CS5A_), \
+        GPIO_FN(PORT91_RDWR),
+        GPIO_FN(CS5B_), \
+        GPIO_FN(FCE1_),
+        GPIO_FN(CS6B_), \
+        GPIO_FN(DACK0),
+        GPIO_FN(FCE0_), \
+        GPIO_FN(CS6A_),
+        GPIO_FN(WAIT_), \
+        GPIO_FN(DREQ0),
+        GPIO_FN(RD__FSC),
+        GPIO_FN(WE0__FWE), \
+        GPIO_FN(RDWR_FWE),
+        GPIO_FN(WE1_),
+        GPIO_FN(FRB),
+        GPIO_FN(CKO),
+        GPIO_FN(NBRSTOUT_),
+        GPIO_FN(NBRST_),
+        GPIO_FN(BBIF2_TXD),
+        GPIO_FN(BBIF2_RXD),
+        GPIO_FN(BBIF2_SYNC),
+        GPIO_FN(BBIF2_SCK),
+        GPIO_FN(SCIFA3_CTS_), \
+        GPIO_FN(MFG3_IN2),
+        GPIO_FN(SCIFA3_RXD), \
+        GPIO_FN(MFG3_IN1),
+        GPIO_FN(BBIF1_SS2), \
+        GPIO_FN(SCIFA3_RTS_), \
+        GPIO_FN(MFG3_OUT1),
+        GPIO_FN(SCIFA3_TXD),
+        GPIO_FN(HSI_RX_DATA), \
+        GPIO_FN(BBIF1_RXD),
+        GPIO_FN(HSI_TX_WAKE), \
+        GPIO_FN(BBIF1_TSCK),
+        GPIO_FN(HSI_TX_DATA), \
+        GPIO_FN(BBIF1_TSYNC),
+        GPIO_FN(HSI_TX_READY), \
+        GPIO_FN(BBIF1_TXD),
+        GPIO_FN(HSI_RX_READY), \
+        GPIO_FN(BBIF1_RSCK), \
+        GPIO_FN(PORT115_I2C_SCL2), \
+        GPIO_FN(PORT115_I2C_SCL3),
+        GPIO_FN(HSI_RX_WAKE), \
+        GPIO_FN(BBIF1_RSYNC), \
+        GPIO_FN(PORT116_I2C_SDA2), \
+        GPIO_FN(PORT116_I2C_SDA3),
+        GPIO_FN(HSI_RX_FLAG), \
+        GPIO_FN(BBIF1_SS1), \
+        GPIO_FN(BBIF1_FLOW),
+        GPIO_FN(HSI_TX_FLAG),
+        GPIO_FN(VIO_VD), \
+        GPIO_FN(PORT128_LCD2VSYN), \
+        GPIO_FN(VIO2_VD), \
+        GPIO_FN(LCD2D0),
+
+        GPIO_FN(VIO_HD), \
+        GPIO_FN(PORT129_LCD2HSYN), \
+        GPIO_FN(PORT129_LCD2CS_), \
+        GPIO_FN(VIO2_HD), \
+        GPIO_FN(LCD2D1),
+        GPIO_FN(VIO_D0), \
+        GPIO_FN(PORT130_MSIOF2_RXD), \
+        GPIO_FN(LCD2D10),
+        GPIO_FN(VIO_D1), \
+        GPIO_FN(PORT131_KEYOUT6), \
+        GPIO_FN(PORT131_MSIOF2_SS1), \
+        GPIO_FN(PORT131_KEYOUT11), \
+        GPIO_FN(LCD2D11),
+        GPIO_FN(VIO_D2), \
+        GPIO_FN(PORT132_KEYOUT7), \
+        GPIO_FN(PORT132_MSIOF2_SS2), \
+        GPIO_FN(PORT132_KEYOUT10), \
+        GPIO_FN(LCD2D12),
+        GPIO_FN(VIO_D3), \
+        GPIO_FN(MSIOF2_TSYNC), \
+        GPIO_FN(LCD2D13),
+        GPIO_FN(VIO_D4), \
+        GPIO_FN(MSIOF2_TXD), \
+        GPIO_FN(LCD2D14),
+        GPIO_FN(VIO_D5), \
+        GPIO_FN(MSIOF2_TSCK), \
+        GPIO_FN(LCD2D15),
+        GPIO_FN(VIO_D6), \
+        GPIO_FN(PORT136_KEYOUT8), \
+        GPIO_FN(LCD2D16),
+        GPIO_FN(VIO_D7), \
+        GPIO_FN(PORT137_KEYOUT9), \
+        GPIO_FN(LCD2D17),
+        GPIO_FN(VIO_D8), \
+        GPIO_FN(PORT138_KEYOUT8), \
+        GPIO_FN(VIO2_D0), \
+        GPIO_FN(LCD2D6),
+        GPIO_FN(VIO_D9), \
+        GPIO_FN(PORT139_KEYOUT9), \
+        GPIO_FN(VIO2_D1), \
+        GPIO_FN(LCD2D7),
+        GPIO_FN(VIO_D10), \
+        GPIO_FN(TPU0TO2), \
+        GPIO_FN(VIO2_D2), \
+        GPIO_FN(LCD2D8),
+        GPIO_FN(VIO_D11), \
+        GPIO_FN(TPU0TO3), \
+        GPIO_FN(VIO2_D3), \
+        GPIO_FN(LCD2D9),
+        GPIO_FN(VIO_D12), \
+        GPIO_FN(PORT142_KEYOUT10), \
+        GPIO_FN(VIO2_D4), \
+        GPIO_FN(LCD2D2),
+        GPIO_FN(VIO_D13), \
+        GPIO_FN(PORT143_KEYOUT11), \
+        GPIO_FN(PORT143_KEYOUT6), \
+        GPIO_FN(VIO2_D5), \
+        GPIO_FN(LCD2D3),
+        GPIO_FN(VIO_D14), \
+        GPIO_FN(PORT144_KEYOUT7), \
+        GPIO_FN(VIO2_D6), \
+        GPIO_FN(LCD2D4),
+        GPIO_FN(VIO_D15), \
+        GPIO_FN(TPU1TO3), \
+        GPIO_FN(PORT145_LCD2DISP), \
+        GPIO_FN(PORT145_LCD2RS), \
+        GPIO_FN(VIO2_D7), \
+        GPIO_FN(LCD2D5),
+        GPIO_FN(VIO_CLK), \
+        GPIO_FN(LCD2DCK), \
+        GPIO_FN(PORT146_LCD2WR_), \
+        GPIO_FN(VIO2_CLK), \
+        GPIO_FN(LCD2D18),
+        GPIO_FN(VIO_FIELD), \
+        GPIO_FN(LCD2RD_), \
+        GPIO_FN(VIO2_FIELD), \
+        GPIO_FN(LCD2D19),
+        GPIO_FN(VIO_CKO),
+        GPIO_FN(A27), \
+        GPIO_FN(PORT149_RDWR), \
+        GPIO_FN(MFG0_IN1), \
+        GPIO_FN(PORT149_KEYOUT9),
+        GPIO_FN(MFG0_IN2),
+        GPIO_FN(TS_SPSYNC3), \
+        GPIO_FN(MSIOF2_RSCK),
+        GPIO_FN(TS_SDAT3), \
+        GPIO_FN(MSIOF2_RSYNC),
+        GPIO_FN(TPU1TO2), \
+        GPIO_FN(TS_SDEN3), \
+        GPIO_FN(PORT153_MSIOF2_SS1),
+        GPIO_FN(SCIFA2_TXD1), \
+        GPIO_FN(MSIOF2_MCK0),
+        GPIO_FN(SCIFA2_RXD1), \
+        GPIO_FN(MSIOF2_MCK1),
+        GPIO_FN(SCIFA2_RTS1_), \
+        GPIO_FN(PORT156_MSIOF2_SS2),
+        GPIO_FN(SCIFA2_CTS1_), \
+        GPIO_FN(PORT157_MSIOF2_RXD),
+        GPIO_FN(DINT_), \
+        GPIO_FN(SCIFA2_SCK1), \
+        GPIO_FN(TS_SCK3),
+        GPIO_FN(PORT159_SCIFB_SCK), \
+        GPIO_FN(PORT159_SCIFA5_SCK), \
+        GPIO_FN(NMI),
+        GPIO_FN(PORT160_SCIFB_TXD), \
+        GPIO_FN(PORT160_SCIFA5_TXD),
+        GPIO_FN(PORT161_SCIFB_CTS_), \
+        GPIO_FN(PORT161_SCIFA5_CTS_),
+        GPIO_FN(PORT162_SCIFB_RXD), \
+        GPIO_FN(PORT162_SCIFA5_RXD),
+        GPIO_FN(PORT163_SCIFB_RTS_), \
+        GPIO_FN(PORT163_SCIFA5_RTS_), \
+        GPIO_FN(TPU3TO0),
+        GPIO_FN(LCDD0),
+        GPIO_FN(LCDD1), \
+        GPIO_FN(PORT193_SCIFA5_CTS_), \
+        GPIO_FN(BBIF2_TSYNC1),
+        GPIO_FN(LCDD2), \
+        GPIO_FN(PORT194_SCIFA5_RTS_), \
+        GPIO_FN(BBIF2_TSCK1),
+        GPIO_FN(LCDD3), \
+        GPIO_FN(PORT195_SCIFA5_RXD), \
+        GPIO_FN(BBIF2_TXD1),
+        GPIO_FN(LCDD4), \
+        GPIO_FN(PORT196_SCIFA5_TXD),
+        GPIO_FN(LCDD5), \
+        GPIO_FN(PORT197_SCIFA5_SCK), \
+        GPIO_FN(MFG2_OUT2), \
+        GPIO_FN(TPU2TO1),
+        GPIO_FN(LCDD6),
+        GPIO_FN(LCDD7), \
+        GPIO_FN(TPU4TO1), \
+        GPIO_FN(MFG4_OUT2),
+        GPIO_FN(LCDD8), \
+        GPIO_FN(D16),
+        GPIO_FN(LCDD9), \
+        GPIO_FN(D17),
+        GPIO_FN(LCDD10), \
+        GPIO_FN(D18),
+        GPIO_FN(LCDD11), \
+        GPIO_FN(D19),
+        GPIO_FN(LCDD12), \
+        GPIO_FN(D20),
+        GPIO_FN(LCDD13), \
+        GPIO_FN(D21),
+        GPIO_FN(LCDD14), \
+        GPIO_FN(D22),
+        GPIO_FN(LCDD15), \
+        GPIO_FN(PORT207_MSIOF0L_SS1), \
+        GPIO_FN(D23),
+        GPIO_FN(LCDD16), \
+        GPIO_FN(PORT208_MSIOF0L_SS2), \
+        GPIO_FN(D24),
+        GPIO_FN(LCDD17), \
+        GPIO_FN(D25),
+        GPIO_FN(LCDD18), \
+        GPIO_FN(DREQ2), \
+        GPIO_FN(PORT210_MSIOF0L_SS1), \
+        GPIO_FN(D26),
+        GPIO_FN(LCDD19), \
+        GPIO_FN(PORT211_MSIOF0L_SS2), \
+        GPIO_FN(D27),
+        GPIO_FN(LCDD20), \
+        GPIO_FN(TS_SPSYNC1), \
+        GPIO_FN(MSIOF0L_MCK0), \
+        GPIO_FN(D28),
+        GPIO_FN(LCDD21), \
+        GPIO_FN(TS_SDAT1), \
+        GPIO_FN(MSIOF0L_MCK1), \
+        GPIO_FN(D29),
+        GPIO_FN(LCDD22), \
+        GPIO_FN(TS_SDEN1), \
+        GPIO_FN(MSIOF0L_RSCK), \
+        GPIO_FN(D30),
+        GPIO_FN(LCDD23), \
+        GPIO_FN(TS_SCK1), \
+        GPIO_FN(MSIOF0L_RSYNC), \
+        GPIO_FN(D31),
+        GPIO_FN(LCDDCK), \
+        GPIO_FN(LCDWR_),
+        GPIO_FN(LCDRD_), \
+        GPIO_FN(DACK2), \
+        GPIO_FN(PORT217_LCD2RS), \
+        GPIO_FN(MSIOF0L_TSYNC), \
+        GPIO_FN(VIO2_FIELD3), \
+        GPIO_FN(PORT217_LCD2DISP),
+        GPIO_FN(LCDHSYN), \
+        GPIO_FN(LCDCS_), \
+        GPIO_FN(LCDCS2_), \
+        GPIO_FN(DACK3), \
+        GPIO_FN(PORT218_VIO_CKOR),
+        GPIO_FN(LCDDISP), \
+        GPIO_FN(LCDRS), \
+        GPIO_FN(PORT219_LCD2WR_), \
+        GPIO_FN(DREQ3), \
+        GPIO_FN(MSIOF0L_TSCK), \
+        GPIO_FN(VIO2_CLK3), \
+        GPIO_FN(LCD2DCK_2),
+        GPIO_FN(LCDVSYN), \
+        GPIO_FN(LCDVSYN2),
+        GPIO_FN(LCDLCLK), \
+        GPIO_FN(DREQ1), \
+        GPIO_FN(PORT221_LCD2CS_), \
+        GPIO_FN(PWEN), \
+        GPIO_FN(MSIOF0L_RXD), \
+        GPIO_FN(VIO2_HD3), \
+        GPIO_FN(PORT221_LCD2HSYN),
+        GPIO_FN(LCDDON), \
+        GPIO_FN(LCDDON2), \
+        GPIO_FN(DACK1), \
+        GPIO_FN(OVCN), \
+        GPIO_FN(MSIOF0L_TXD), \
+        GPIO_FN(VIO2_VD3), \
+        GPIO_FN(PORT222_LCD2VSYN),
+
+        GPIO_FN(SCIFA1_TXD), \
+        GPIO_FN(OVCN2),
+        GPIO_FN(EXTLP), \
+        GPIO_FN(SCIFA1_SCK), \
+        GPIO_FN(PORT226_VIO_CKO2),
+        GPIO_FN(SCIFA1_RTS_), \
+        GPIO_FN(IDIN),
+        GPIO_FN(SCIFA1_RXD),
+        GPIO_FN(SCIFA1_CTS_), \
+        GPIO_FN(MFG1_IN1),
+        GPIO_FN(MSIOF1_TXD), \
+        GPIO_FN(SCIFA2_TXD2),
+        GPIO_FN(MSIOF1_TSYNC), \
+        GPIO_FN(SCIFA2_CTS2_),
+        GPIO_FN(MSIOF1_TSCK), \
+        GPIO_FN(SCIFA2_SCK2),
+        GPIO_FN(MSIOF1_RXD), \
+        GPIO_FN(SCIFA2_RXD2),
+        GPIO_FN(MSIOF1_RSCK), \
+        GPIO_FN(SCIFA2_RTS2_), \
+        GPIO_FN(VIO2_CLK2), \
+        GPIO_FN(LCD2D20),
+        GPIO_FN(MSIOF1_RSYNC), \
+        GPIO_FN(MFG1_IN2), \
+        GPIO_FN(VIO2_VD2), \
+        GPIO_FN(LCD2D21),
+        GPIO_FN(MSIOF1_MCK0), \
+        GPIO_FN(PORT236_I2C_SDA2),
+        GPIO_FN(MSIOF1_MCK1), \
+        GPIO_FN(PORT237_I2C_SCL2),
+        GPIO_FN(MSIOF1_SS1), \
+        GPIO_FN(VIO2_FIELD2), \
+        GPIO_FN(LCD2D22),
+        GPIO_FN(MSIOF1_SS2), \
+        GPIO_FN(VIO2_HD2), \
+        GPIO_FN(LCD2D23),
+        GPIO_FN(SCIFA6_TXD),
+        GPIO_FN(PORT241_IRDA_OUT), \
+        GPIO_FN(PORT241_IROUT), \
+        GPIO_FN(MFG4_OUT1), \
+        GPIO_FN(TPU4TO0),
+        GPIO_FN(PORT242_IRDA_IN), \
+        GPIO_FN(MFG4_IN2),
+        GPIO_FN(PORT243_IRDA_FIRSEL), \
+        GPIO_FN(PORT243_VIO_CKO2),
+        GPIO_FN(PORT244_SCIFA5_CTS_), \
+        GPIO_FN(MFG2_IN1), \
+        GPIO_FN(PORT244_SCIFB_CTS_), \
+        GPIO_FN(MSIOF2R_RXD),
+        GPIO_FN(PORT245_SCIFA5_RTS_), \
+        GPIO_FN(MFG2_IN2), \
+        GPIO_FN(PORT245_SCIFB_RTS_), \
+        GPIO_FN(MSIOF2R_TXD),
+        GPIO_FN(PORT246_SCIFA5_RXD), \
+        GPIO_FN(MFG1_OUT1), \
+        GPIO_FN(PORT246_SCIFB_RXD), \
+        GPIO_FN(TPU1TO0),
+        GPIO_FN(PORT247_SCIFA5_TXD), \
+        GPIO_FN(MFG3_OUT2), \
+        GPIO_FN(PORT247_SCIFB_TXD), \
+        GPIO_FN(TPU3TO1),
+        GPIO_FN(PORT248_SCIFA5_SCK), \
+        GPIO_FN(MFG2_OUT1), \
+        GPIO_FN(PORT248_SCIFB_SCK), \
+        GPIO_FN(TPU2TO0), \
+        GPIO_FN(PORT248_I2C_SCL3), \
+        GPIO_FN(MSIOF2R_TSCK),
+        GPIO_FN(PORT249_IROUT), \
+        GPIO_FN(MFG4_IN1), \
+        GPIO_FN(PORT249_I2C_SDA3), \
+        GPIO_FN(MSIOF2R_TSYNC),
+        GPIO_FN(SDHICLK0),
+        GPIO_FN(SDHICD0),
+        GPIO_FN(SDHID0_0),
+        GPIO_FN(SDHID0_1),
+        GPIO_FN(SDHID0_2),
+        GPIO_FN(SDHID0_3),
+        GPIO_FN(SDHICMD0),
+        GPIO_FN(SDHIWP0),
+        GPIO_FN(SDHICLK1),
+        GPIO_FN(SDHID1_0), \
+        GPIO_FN(TS_SPSYNC2),
+        GPIO_FN(SDHID1_1), \
+        GPIO_FN(TS_SDAT2),
+        GPIO_FN(SDHID1_2), \
+        GPIO_FN(TS_SDEN2),
+        GPIO_FN(SDHID1_3), \
+        GPIO_FN(TS_SCK2),
+        GPIO_FN(SDHICMD1),
+        GPIO_FN(SDHICLK2),
+        GPIO_FN(SDHID2_0), \
+        GPIO_FN(TS_SPSYNC4),
+        GPIO_FN(SDHID2_1), \
+        GPIO_FN(TS_SDAT4),
+        GPIO_FN(SDHID2_2), \
+        GPIO_FN(TS_SDEN4),
+        GPIO_FN(SDHID2_3), \
+        GPIO_FN(TS_SCK4),
+        GPIO_FN(SDHICMD2),
+        GPIO_FN(MMCCLK0),
+        GPIO_FN(MMCD0_0),
+        GPIO_FN(MMCD0_1),
+        GPIO_FN(MMCD0_2),
+        GPIO_FN(MMCD0_3),
+        GPIO_FN(MMCD0_4), \
+        GPIO_FN(TS_SPSYNC5),
+        GPIO_FN(MMCD0_5), \
+        GPIO_FN(TS_SDAT5),
+        GPIO_FN(MMCD0_6), \
+        GPIO_FN(TS_SDEN5),
+        GPIO_FN(MMCD0_7), \
+        GPIO_FN(TS_SCK5),
+        GPIO_FN(MMCCMD0),
+        GPIO_FN(RESETOUTS_), \
+        GPIO_FN(EXTAL2OUT),
+        GPIO_FN(MCP_WAIT__MCP_FRB),
+        GPIO_FN(MCP_CKO), \
+        GPIO_FN(MMCCLK1),
+        GPIO_FN(MCP_D15_MCP_NAF15),
+        GPIO_FN(MCP_D14_MCP_NAF14),
+        GPIO_FN(MCP_D13_MCP_NAF13),
+        GPIO_FN(MCP_D12_MCP_NAF12),
+        GPIO_FN(MCP_D11_MCP_NAF11),
+        GPIO_FN(MCP_D10_MCP_NAF10),
+        GPIO_FN(MCP_D9_MCP_NAF9),
+        GPIO_FN(MCP_D8_MCP_NAF8), \
+        GPIO_FN(MMCCMD1),
+        GPIO_FN(MCP_D7_MCP_NAF7), \
+        GPIO_FN(MMCD1_7),
+
+        GPIO_FN(MCP_D6_MCP_NAF6), \
+        GPIO_FN(MMCD1_6),
+        GPIO_FN(MCP_D5_MCP_NAF5), \
+        GPIO_FN(MMCD1_5),
+        GPIO_FN(MCP_D4_MCP_NAF4), \
+        GPIO_FN(MMCD1_4),
+        GPIO_FN(MCP_D3_MCP_NAF3), \
+        GPIO_FN(MMCD1_3),
+        GPIO_FN(MCP_D2_MCP_NAF2), \
+        GPIO_FN(MMCD1_2),
+        GPIO_FN(MCP_D1_MCP_NAF1), \
+        GPIO_FN(MMCD1_1),
+        GPIO_FN(MCP_D0_MCP_NAF0), \
+        GPIO_FN(MMCD1_0),
+        GPIO_FN(MCP_NBRSTOUT_),
+        GPIO_FN(MCP_WE0__MCP_FWE), \
+        GPIO_FN(MCP_RDWR_MCP_FWE),
+
+        /* MSEL2 special cases */
+        GPIO_FN(TSIF2_TS_XX1),
+        GPIO_FN(TSIF2_TS_XX2),
+        GPIO_FN(TSIF2_TS_XX3),
+        GPIO_FN(TSIF2_TS_XX4),
+        GPIO_FN(TSIF2_TS_XX5),
+        GPIO_FN(TSIF1_TS_XX1),
+        GPIO_FN(TSIF1_TS_XX2),
+        GPIO_FN(TSIF1_TS_XX3),
+        GPIO_FN(TSIF1_TS_XX4),
+        GPIO_FN(TSIF1_TS_XX5),
+        GPIO_FN(TSIF0_TS_XX1),
+        GPIO_FN(TSIF0_TS_XX2),
+        GPIO_FN(TSIF0_TS_XX3),
+        GPIO_FN(TSIF0_TS_XX4),
+        GPIO_FN(TSIF0_TS_XX5),
+        GPIO_FN(MST1_TS_XX1),
+        GPIO_FN(MST1_TS_XX2),
+        GPIO_FN(MST1_TS_XX3),
+        GPIO_FN(MST1_TS_XX4),
+        GPIO_FN(MST1_TS_XX5),
+        GPIO_FN(MST0_TS_XX1),
+        GPIO_FN(MST0_TS_XX2),
+        GPIO_FN(MST0_TS_XX3),
+        GPIO_FN(MST0_TS_XX4),
+        GPIO_FN(MST0_TS_XX5),
+
+        /* MSEL3 special cases */
+        GPIO_FN(SDHI0_VCCQ_MC0_ON),
+        GPIO_FN(SDHI0_VCCQ_MC0_OFF),
+        GPIO_FN(DEBUG_MON_VIO),
+        GPIO_FN(DEBUG_MON_LCDD),
+        GPIO_FN(LCDC_LCDC0),
+        GPIO_FN(LCDC_LCDC1),
+
+        /* MSEL4 special cases */
+        GPIO_FN(IRQ9_MEM_INT),
+        GPIO_FN(IRQ9_MCP_INT),
+        GPIO_FN(A11),
+        GPIO_FN(KEYOUT8),
+        GPIO_FN(TPU4TO3),
+        GPIO_FN(RESETA_N_PU_ON),
+        GPIO_FN(RESETA_N_PU_OFF),
+        GPIO_FN(EDBGREQ_PD),
+        GPIO_FN(EDBGREQ_PU),
+
+        /* Functions with pull-ups */
+        GPIO_FN(KEYIN0_PU),
+        GPIO_FN(KEYIN1_PU),
+        GPIO_FN(KEYIN2_PU),
+        GPIO_FN(KEYIN3_PU),
+        GPIO_FN(KEYIN4_PU),
+        GPIO_FN(KEYIN5_PU),
+        GPIO_FN(KEYIN6_PU),
+        GPIO_FN(KEYIN7_PU),
+        GPIO_FN(SDHID1_0_PU),
+        GPIO_FN(SDHID1_1_PU),
+        GPIO_FN(SDHID1_2_PU),
+        GPIO_FN(SDHID1_3_PU),
+        GPIO_FN(SDHICMD1_PU),
+        GPIO_FN(MMCCMD0_PU),
+        GPIO_FN(MMCCMD1_PU),
+        GPIO_FN(FSIACK_PU),
+        GPIO_FN(FSIAILR_PU),
+        GPIO_FN(FSIAIBT_PU),
+        GPIO_FN(FSIAISLD_PU),
+};
+
+#define PORTCR(nr, reg) \
+        { PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
+                0, \
+                /*0001*/ PORT##nr##_OUT , \
+                /*0010*/ PORT##nr##_IN , 0, 0, 0, 0, 0, 0, 0, \
+                /*1010*/ PORT##nr##_IN_PD, 0, 0, 0, \
+                /*1110*/ PORT##nr##_IN_PU, 0, \
+                PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
+                PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
+                PORT##nr##_FN6, PORT##nr##_FN7, 0, 0, 0, 0, 0, 0, 0, 0 } \
+        }
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        PORTCR(0, 0xe6050000), /* PORT0CR */
+        PORTCR(1, 0xe6050001), /* PORT1CR */
+        PORTCR(2, 0xe6050002), /* PORT2CR */
+        PORTCR(3, 0xe6050003), /* PORT3CR */
+        PORTCR(4, 0xe6050004), /* PORT4CR */
+        PORTCR(5, 0xe6050005), /* PORT5CR */
+        PORTCR(6, 0xe6050006), /* PORT6CR */
+        PORTCR(7, 0xe6050007), /* PORT7CR */
+        PORTCR(8, 0xe6050008), /* PORT8CR */
+        PORTCR(9, 0xe6050009), /* PORT9CR */
+
+        PORTCR(10, 0xe605000a), /* PORT10CR */
+        PORTCR(11, 0xe605000b), /* PORT11CR */
+        PORTCR(12, 0xe605000c), /* PORT12CR */
+        PORTCR(13, 0xe605000d), /* PORT13CR */
+        PORTCR(14, 0xe605000e), /* PORT14CR */
+        PORTCR(15, 0xe605000f), /* PORT15CR */
+        PORTCR(16, 0xe6050010), /* PORT16CR */
+        PORTCR(17, 0xe6050011), /* PORT17CR */
+        PORTCR(18, 0xe6050012), /* PORT18CR */
+        PORTCR(19, 0xe6050013), /* PORT19CR */
+
+        PORTCR(20, 0xe6050014), /* PORT20CR */
+        PORTCR(21, 0xe6050015), /* PORT21CR */
+        PORTCR(22, 0xe6050016), /* PORT22CR */
+        PORTCR(23, 0xe6050017), /* PORT23CR */
+        PORTCR(24, 0xe6050018), /* PORT24CR */
+        PORTCR(25, 0xe6050019), /* PORT25CR */
+        PORTCR(26, 0xe605001a), /* PORT26CR */
+        PORTCR(27, 0xe605001b), /* PORT27CR */
+        PORTCR(28, 0xe605001c), /* PORT28CR */
+        PORTCR(29, 0xe605001d), /* PORT29CR */
+
+        PORTCR(30, 0xe605001e), /* PORT30CR */
+        PORTCR(31, 0xe605001f), /* PORT31CR */
+        PORTCR(32, 0xe6051020), /* PORT32CR */
+        PORTCR(33, 0xe6051021), /* PORT33CR */
+        PORTCR(34, 0xe6051022), /* PORT34CR */
+        PORTCR(35, 0xe6051023), /* PORT35CR */
+        PORTCR(36, 0xe6051024), /* PORT36CR */
+        PORTCR(37, 0xe6051025), /* PORT37CR */
+        PORTCR(38, 0xe6051026), /* PORT38CR */
+        PORTCR(39, 0xe6051027), /* PORT39CR */
+
+        PORTCR(40, 0xe6051028), /* PORT40CR */
+        PORTCR(41, 0xe6051029), /* PORT41CR */
+        PORTCR(42, 0xe605102a), /* PORT42CR */
+        PORTCR(43, 0xe605102b), /* PORT43CR */
+        PORTCR(44, 0xe605102c), /* PORT44CR */
+        PORTCR(45, 0xe605102d), /* PORT45CR */
+        PORTCR(46, 0xe605102e), /* PORT46CR */
+        PORTCR(47, 0xe605102f), /* PORT47CR */
+        PORTCR(48, 0xe6051030), /* PORT48CR */
+        PORTCR(49, 0xe6051031), /* PORT49CR */
+
+        PORTCR(50, 0xe6051032), /* PORT50CR */
+        PORTCR(51, 0xe6051033), /* PORT51CR */
+        PORTCR(52, 0xe6051034), /* PORT52CR */
+        PORTCR(53, 0xe6051035), /* PORT53CR */
+        PORTCR(54, 0xe6051036), /* PORT54CR */
+        PORTCR(55, 0xe6051037), /* PORT55CR */
+        PORTCR(56, 0xe6051038), /* PORT56CR */
+        PORTCR(57, 0xe6051039), /* PORT57CR */
+        PORTCR(58, 0xe605103a), /* PORT58CR */
+        PORTCR(59, 0xe605103b), /* PORT59CR */
+
+        PORTCR(60, 0xe605103c), /* PORT60CR */
+        PORTCR(61, 0xe605103d), /* PORT61CR */
+        PORTCR(62, 0xe605103e), /* PORT62CR */
+        PORTCR(63, 0xe605103f), /* PORT63CR */
+        PORTCR(64, 0xe6051040), /* PORT64CR */
+        PORTCR(65, 0xe6051041), /* PORT65CR */
+        PORTCR(66, 0xe6051042), /* PORT66CR */
+        PORTCR(67, 0xe6051043), /* PORT67CR */
+        PORTCR(68, 0xe6051044), /* PORT68CR */
+        PORTCR(69, 0xe6051045), /* PORT69CR */
+
+        PORTCR(70, 0xe6051046), /* PORT70CR */
+        PORTCR(71, 0xe6051047), /* PORT71CR */
+        PORTCR(72, 0xe6051048), /* PORT72CR */
+        PORTCR(73, 0xe6051049), /* PORT73CR */
+        PORTCR(74, 0xe605104a), /* PORT74CR */
+        PORTCR(75, 0xe605104b), /* PORT75CR */
+        PORTCR(76, 0xe605104c), /* PORT76CR */
+        PORTCR(77, 0xe605104d), /* PORT77CR */
+        PORTCR(78, 0xe605104e), /* PORT78CR */
+        PORTCR(79, 0xe605104f), /* PORT79CR */
+
+        PORTCR(80, 0xe6051050), /* PORT80CR */
+        PORTCR(81, 0xe6051051), /* PORT81CR */
+        PORTCR(82, 0xe6051052), /* PORT82CR */
+        PORTCR(83, 0xe6051053), /* PORT83CR */
+        PORTCR(84, 0xe6051054), /* PORT84CR */
+        PORTCR(85, 0xe6051055), /* PORT85CR */
+        PORTCR(86, 0xe6051056), /* PORT86CR */
+        PORTCR(87, 0xe6051057), /* PORT87CR */
+        PORTCR(88, 0xe6051058), /* PORT88CR */
+        PORTCR(89, 0xe6051059), /* PORT89CR */
+
+        PORTCR(90, 0xe605105a), /* PORT90CR */
+        PORTCR(91, 0xe605105b), /* PORT91CR */
+        PORTCR(92, 0xe605105c), /* PORT92CR */
+        PORTCR(93, 0xe605105d), /* PORT93CR */
+        PORTCR(94, 0xe605105e), /* PORT94CR */
+        PORTCR(95, 0xe605105f), /* PORT95CR */
+        PORTCR(96, 0xe6052060), /* PORT96CR */
+        PORTCR(97, 0xe6052061), /* PORT97CR */
+        PORTCR(98, 0xe6052062), /* PORT98CR */
+        PORTCR(99, 0xe6052063), /* PORT99CR */
+
+        PORTCR(100, 0xe6052064), /* PORT100CR */
+        PORTCR(101, 0xe6052065), /* PORT101CR */
+        PORTCR(102, 0xe6052066), /* PORT102CR */
+        PORTCR(103, 0xe6052067), /* PORT103CR */
+        PORTCR(104, 0xe6052068), /* PORT104CR */
+        PORTCR(105, 0xe6052069), /* PORT105CR */
+        PORTCR(106, 0xe605206a), /* PORT106CR */
+        PORTCR(107, 0xe605206b), /* PORT107CR */
+        PORTCR(108, 0xe605206c), /* PORT108CR */
+        PORTCR(109, 0xe605206d), /* PORT109CR */
+
+        PORTCR(110, 0xe605206e), /* PORT110CR */
+        PORTCR(111, 0xe605206f), /* PORT111CR */
+        PORTCR(112, 0xe6052070), /* PORT112CR */
+        PORTCR(113, 0xe6052071), /* PORT113CR */
+        PORTCR(114, 0xe6052072), /* PORT114CR */
+        PORTCR(115, 0xe6052073), /* PORT115CR */
+        PORTCR(116, 0xe6052074), /* PORT116CR */
+        PORTCR(117, 0xe6052075), /* PORT117CR */
+        PORTCR(118, 0xe6052076), /* PORT118CR */
+
+        PORTCR(128, 0xe6052080), /* PORT128CR */
+        PORTCR(129, 0xe6052081), /* PORT129CR */
+
+        PORTCR(130, 0xe6052082), /* PORT130CR */
+        PORTCR(131, 0xe6052083), /* PORT131CR */
+        PORTCR(132, 0xe6052084), /* PORT132CR */
+        PORTCR(133, 0xe6052085), /* PORT133CR */
+        PORTCR(134, 0xe6052086), /* PORT134CR */
+        PORTCR(135, 0xe6052087), /* PORT135CR */
+        PORTCR(136, 0xe6052088), /* PORT136CR */
+        PORTCR(137, 0xe6052089), /* PORT137CR */
+        PORTCR(138, 0xe605208a), /* PORT138CR */
+        PORTCR(139, 0xe605208b), /* PORT139CR */
+
+        PORTCR(140, 0xe605208c), /* PORT140CR */
+        PORTCR(141, 0xe605208d), /* PORT141CR */
+        PORTCR(142, 0xe605208e), /* PORT142CR */
+        PORTCR(143, 0xe605208f), /* PORT143CR */
+        PORTCR(144, 0xe6052090), /* PORT144CR */
+        PORTCR(145, 0xe6052091), /* PORT145CR */
+        PORTCR(146, 0xe6052092), /* PORT146CR */
+        PORTCR(147, 0xe6052093), /* PORT147CR */
+        PORTCR(148, 0xe6052094), /* PORT148CR */
+        PORTCR(149, 0xe6052095), /* PORT149CR */
+
+        PORTCR(150, 0xe6052096), /* PORT150CR */
+        PORTCR(151, 0xe6052097), /* PORT151CR */
+        PORTCR(152, 0xe6052098), /* PORT152CR */
+        PORTCR(153, 0xe6052099), /* PORT153CR */
+        PORTCR(154, 0xe605209a), /* PORT154CR */
+        PORTCR(155, 0xe605209b), /* PORT155CR */
+        PORTCR(156, 0xe605209c), /* PORT156CR */
+        PORTCR(157, 0xe605209d), /* PORT157CR */
+        PORTCR(158, 0xe605209e), /* PORT158CR */
+        PORTCR(159, 0xe605209f), /* PORT159CR */
+
+        PORTCR(160, 0xe60520a0), /* PORT160CR */
+        PORTCR(161, 0xe60520a1), /* PORT161CR */
+        PORTCR(162, 0xe60520a2), /* PORT162CR */
+        PORTCR(163, 0xe60520a3), /* PORT163CR */
+        PORTCR(164, 0xe60520a4), /* PORT164CR */
+
+        PORTCR(192, 0xe60520c0), /* PORT192CR */
+        PORTCR(193, 0xe60520c1), /* PORT193CR */
+        PORTCR(194, 0xe60520c2), /* PORT194CR */
+        PORTCR(195, 0xe60520c3), /* PORT195CR */
+        PORTCR(196, 0xe60520c4), /* PORT196CR */
+        PORTCR(197, 0xe60520c5), /* PORT197CR */
+        PORTCR(198, 0xe60520c6), /* PORT198CR */
+        PORTCR(199, 0xe60520c7), /* PORT199CR */
+
+        PORTCR(200, 0xe60520c8), /* PORT200CR */
+        PORTCR(201, 0xe60520c9), /* PORT201CR */
+        PORTCR(202, 0xe60520ca), /* PORT202CR */
+        PORTCR(203, 0xe60520cb), /* PORT203CR */
+        PORTCR(204, 0xe60520cc), /* PORT204CR */
+        PORTCR(205, 0xe60520cd), /* PORT205CR */
+        PORTCR(206, 0xe60520ce), /* PORT206CR */
+        PORTCR(207, 0xe60520cf), /* PORT207CR */
+        PORTCR(208, 0xe60520d0), /* PORT208CR */
+        PORTCR(209, 0xe60520d1), /* PORT209CR */
+
+        PORTCR(210, 0xe60520d2), /* PORT210CR */
+        PORTCR(211, 0xe60520d3), /* PORT211CR */
+        PORTCR(212, 0xe60520d4), /* PORT212CR */
+        PORTCR(213, 0xe60520d5), /* PORT213CR */
+        PORTCR(214, 0xe60520d6), /* PORT214CR */
+        PORTCR(215, 0xe60520d7), /* PORT215CR */
+        PORTCR(216, 0xe60520d8), /* PORT216CR */
+        PORTCR(217, 0xe60520d9), /* PORT217CR */
+        PORTCR(218, 0xe60520da), /* PORT218CR */
+        PORTCR(219, 0xe60520db), /* PORT219CR */
+
+        PORTCR(220, 0xe60520dc), /* PORT220CR */
+        PORTCR(221, 0xe60520dd), /* PORT221CR */
+        PORTCR(222, 0xe60520de), /* PORT222CR */
+        PORTCR(223, 0xe60520df), /* PORT223CR */
+        PORTCR(224, 0xe60530e0), /* PORT224CR */
+        PORTCR(225, 0xe60530e1), /* PORT225CR */
+        PORTCR(226, 0xe60530e2), /* PORT226CR */
+        PORTCR(227, 0xe60530e3), /* PORT227CR */
+        PORTCR(228, 0xe60530e4), /* PORT228CR */
+        PORTCR(229, 0xe60530e5), /* PORT229CR */
+
+        PORTCR(230, 0xe60530e6), /* PORT230CR */
+        PORTCR(231, 0xe60530e7), /* PORT231CR */
+        PORTCR(232, 0xe60530e8), /* PORT232CR */
+        PORTCR(233, 0xe60530e9), /* PORT233CR */
+        PORTCR(234, 0xe60530ea), /* PORT234CR */
+        PORTCR(235, 0xe60530eb), /* PORT235CR */
+        PORTCR(236, 0xe60530ec), /* PORT236CR */
+        PORTCR(237, 0xe60530ed), /* PORT237CR */
+        PORTCR(238, 0xe60530ee), /* PORT238CR */
+        PORTCR(239, 0xe60530ef), /* PORT239CR */
+
+        PORTCR(240, 0xe60530f0), /* PORT240CR */
+        PORTCR(241, 0xe60530f1), /* PORT241CR */
+        PORTCR(242, 0xe60530f2), /* PORT242CR */
+        PORTCR(243, 0xe60530f3), /* PORT243CR */
+        PORTCR(244, 0xe60530f4), /* PORT244CR */
+        PORTCR(245, 0xe60530f5), /* PORT245CR */
+        PORTCR(246, 0xe60530f6), /* PORT246CR */
+        PORTCR(247, 0xe60530f7), /* PORT247CR */
+        PORTCR(248, 0xe60530f8), /* PORT248CR */
+        PORTCR(249, 0xe60530f9), /* PORT249CR */
+
+        PORTCR(250, 0xe60530fa), /* PORT250CR */
+        PORTCR(251, 0xe60530fb), /* PORT251CR */
+        PORTCR(252, 0xe60530fc), /* PORT252CR */
+        PORTCR(253, 0xe60530fd), /* PORT253CR */
+        PORTCR(254, 0xe60530fe), /* PORT254CR */
+        PORTCR(255, 0xe60530ff), /* PORT255CR */
+        PORTCR(256, 0xe6053100), /* PORT256CR */
+        PORTCR(257, 0xe6053101), /* PORT257CR */
+        PORTCR(258, 0xe6053102), /* PORT258CR */
+        PORTCR(259, 0xe6053103), /* PORT259CR */
+
+        PORTCR(260, 0xe6053104), /* PORT260CR */
+        PORTCR(261, 0xe6053105), /* PORT261CR */
+        PORTCR(262, 0xe6053106), /* PORT262CR */
+        PORTCR(263, 0xe6053107), /* PORT263CR */
+        PORTCR(264, 0xe6053108), /* PORT264CR */
+        PORTCR(265, 0xe6053109), /* PORT265CR */
+        PORTCR(266, 0xe605310a), /* PORT266CR */
+        PORTCR(267, 0xe605310b), /* PORT267CR */
+        PORTCR(268, 0xe605310c), /* PORT268CR */
+        PORTCR(269, 0xe605310d), /* PORT269CR */
+
+        PORTCR(270, 0xe605310e), /* PORT270CR */
+        PORTCR(271, 0xe605310f), /* PORT271CR */
+        PORTCR(272, 0xe6053110), /* PORT272CR */
+        PORTCR(273, 0xe6053111), /* PORT273CR */
+        PORTCR(274, 0xe6053112), /* PORT274CR */
+        PORTCR(275, 0xe6053113), /* PORT275CR */
+        PORTCR(276, 0xe6053114), /* PORT276CR */
+        PORTCR(277, 0xe6053115), /* PORT277CR */
+        PORTCR(278, 0xe6053116), /* PORT278CR */
+        PORTCR(279, 0xe6053117), /* PORT279CR */
+
+        PORTCR(280, 0xe6053118), /* PORT280CR */
+        PORTCR(281, 0xe6053119), /* PORT281CR */
+        PORTCR(282, 0xe605311a), /* PORT282CR */
+
+        PORTCR(288, 0xe6052120), /* PORT288CR */
+        PORTCR(289, 0xe6052121), /* PORT289CR */
+
+        PORTCR(290, 0xe6052122), /* PORT290CR */
+        PORTCR(291, 0xe6052123), /* PORT291CR */
+        PORTCR(292, 0xe6052124), /* PORT292CR */
+        PORTCR(293, 0xe6052125), /* PORT293CR */
+        PORTCR(294, 0xe6052126), /* PORT294CR */
+        PORTCR(295, 0xe6052127), /* PORT295CR */
+        PORTCR(296, 0xe6052128), /* PORT296CR */
+        PORTCR(297, 0xe6052129), /* PORT297CR */
+        PORTCR(298, 0xe605212a), /* PORT298CR */
+        PORTCR(299, 0xe605212b), /* PORT299CR */
+
+        PORTCR(300, 0xe605212c), /* PORT300CR */
+        PORTCR(301, 0xe605212d), /* PORT301CR */
+        PORTCR(302, 0xe605212e), /* PORT302CR */
+        PORTCR(303, 0xe605212f), /* PORT303CR */
+        PORTCR(304, 0xe6052130), /* PORT304CR */
+        PORTCR(305, 0xe6052131), /* PORT305CR */
+        PORTCR(306, 0xe6052132), /* PORT306CR */
+        PORTCR(307, 0xe6052133), /* PORT307CR */
+        PORTCR(308, 0xe6052134), /* PORT308CR */
+        PORTCR(309, 0xe6052135), /* PORT309CR */
+
+        { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
+                        MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
+                        MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
+                        MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
+                        0, 0,
+                        MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
+                        MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
+                        MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
+                        MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
+                        MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
+                        MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
+                        MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
+                        MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
+                        MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
+                        MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
+                        MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
+                        MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
+                        MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
+                        MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
+                        MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
+                }
+        },
+        { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
+                        0, 0,
+                        MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
+                        0, 0,
+                        0, 0,
+                        MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
+                        0, 0,
+                        0, 0,
+                }
+        },
+        { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
+                        0, 0,
+                        0, 0,
+                        MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
+                        0, 0,
+                        MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
+                        MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
+                        MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
+                        MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
+                        MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
+                        0, 0,
+                        0, 0,
+                        0, 0,
+                        MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
+                        0, 0,
+                        MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
+                        MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
+                        MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
+                        MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
+                        MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
+                        MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
+                        MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
+                        0, 0,
+                        0, 0,
+                        MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
+                        0, 0,
+                        0, 0,
+                        MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
+                        0, 0,
+                }
+        },
+        { },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
+                        PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+                        PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+                        PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+                        PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+                        PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+                        PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+                        PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+                        PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+        },
+        { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
+                        PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+                        PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+                        PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+                        PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+                        PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+                        PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+                        PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+                        PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+        },
+        { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
+                        PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+                        PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+                        PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+                        PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+                        PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+                        PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+                        PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+                        PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+                        PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+                        PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+                        PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+                        PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+                        PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
+                        PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+                        PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+                        PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+                        PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+                        PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+                        PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+                        PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+                        PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, 0, PORT164_DATA,
+                        PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
+                        PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
+                        PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
+                        PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
+                        PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
+                        PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+                        PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+                        PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+                        PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+        },
+        { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
+                        PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
+                        PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
+                        PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
+                        PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
+                        PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
+                        PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
+                        PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
+                        PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
+        },
+        { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
+                        0, 0, 0, 0,
+                        0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
+                        PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
+                        PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
+                        PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
+                        PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
+                        PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
+                        PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
+                        0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        0, 0, PORT309_DATA, PORT308_DATA,
+                        PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
+                        PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
+                        PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
+                        PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
+                        PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
+        },
+        { },
+};
+
+static struct pinmux_info sh73a0_pinmux_info = {
+        .name = "sh73a0_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
+        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PORT0,
+        .last_gpio = GPIO_FN_FSIAISLD_PU,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void sh73a0_pinmux_init(void)
+{
+        register_pinmux(&sh73a0_pinmux_info);
+}
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
new file mode 100644
index 000000000000..65e879bab4dc
--- /dev/null
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -0,0 +1,70 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2011  Paul Mundt
+ *
+ * Based on vexpress, Copyright (C) 2002 ARM Ltd, All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/localtimer.h>
+#include <asm/mach-types.h>
+#include <mach/common.h>
+
+static unsigned int __init shmobile_smp_get_core_count(void)
+{
+        if (machine_is_ag5evm())
+                return sh73a0_get_core_count();
+
+        return 1;
+}
+
+static void __init shmobile_smp_prepare_cpus(void)
+{
+        if (machine_is_ag5evm())
+                sh73a0_smp_prepare_cpus();
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+        trace_hardirqs_off();
+
+        if (machine_is_ag5evm())
+                sh73a0_secondary_init(cpu);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        if (machine_is_ag5evm())
+                return sh73a0_boot_secondary(cpu);
+
+        return -ENOSYS;
+}
+
+void __init smp_init_cpus(void)
+{
+        unsigned int ncores = shmobile_smp_get_core_count();
+        unsigned int i;
+
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
+
+        for (i = 0; i < max_cpus; i++)
+                set_cpu_present(i, true);
+
+        shmobile_smp_prepare_cpus();
+}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 564a6d0be473..2e3e11ee7c43 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -416,6 +416,16 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
                 .addr           = 0xe6870030,
                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
                 .mid_rid        = 0xce,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+                .addr           = 0xe6bd0034,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+                .addr           = 0xe6bd0034,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd2,
         },
 };
 
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
new file mode 100644
index 000000000000..f1eff8b37bd6
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -0,0 +1,412 @@
+/*
+ * sh73a0 processor support
+ *
+ * Copyright (C) 2010  Takashi Yoshii
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2008  Yoshihiro Shimoda
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/serial_sci.h>
+#include <linux/sh_intc.h>
+#include <linux/sh_timer.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xe6c40000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(72), gic_spi(72),
+                            gic_spi(72), gic_spi(72) },
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xe6c50000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(73), gic_spi(73),
+                            gic_spi(73), gic_spi(73) },
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xe6c60000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(74), gic_spi(74),
+                            gic_spi(74), gic_spi(74) },
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xe6c70000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(75), gic_spi(75),
+                            gic_spi(75), gic_spi(75) },
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xe6c80000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(78), gic_spi(78),
+                            gic_spi(78), gic_spi(78) },
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xe6cb0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(79), gic_spi(79),
+                            gic_spi(79), gic_spi(79) },
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
+static struct plat_sci_port scif6_platform_data = {
+        .mapbase        = 0xe6cc0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(156), gic_spi(156),
+                            gic_spi(156), gic_spi(156) },
+};
+
+static struct platform_device scif6_device = {
+        .name           = "sh-sci",
+        .id             = 6,
+        .dev            = {
+                .platform_data  = &scif6_platform_data,
+        },
+};
+
+static struct plat_sci_port scif7_platform_data = {
+        .mapbase        = 0xe6cd0000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFA,
+        .irqs           = { gic_spi(143), gic_spi(143),
+                            gic_spi(143), gic_spi(143) },
+};
+
+static struct platform_device scif7_device = {
+        .name           = "sh-sci",
+        .id             = 7,
+        .dev            = {
+                .platform_data  = &scif7_platform_data,
+        },
+};
+
+static struct plat_sci_port scif8_platform_data = {
+        .mapbase        = 0xe6c30000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .type           = PORT_SCIFB,
+        .irqs           = { gic_spi(80), gic_spi(80),
+                            gic_spi(80), gic_spi(80) },
+};
+
+static struct platform_device scif8_device = {
+        .name           = "sh-sci",
+        .id             = 8,
+        .dev            = {
+                .platform_data  = &scif8_platform_data,
+        },
+};
+
+static struct sh_timer_config cmt10_platform_data = {
+        .name = "CMT10",
+        .channel_offset = 0x10,
+        .timer_bit = 0,
+        .clockevent_rating = 125,
+        .clocksource_rating = 125,
+};
+
+static struct resource cmt10_resources[] = {
+        [0] = {
+                .name   = "CMT10",
+                .start  = 0xe6138010,
+                .end    = 0xe613801b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(65),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt10_device = {
+        .name           = "sh_cmt",
+        .id             = 10,
+        .dev = {
+                .platform_data  = &cmt10_platform_data,
+        },
+        .resource       = cmt10_resources,
+        .num_resources  = ARRAY_SIZE(cmt10_resources),
+};
+
+/* TMU */
+static struct sh_timer_config tmu00_platform_data = {
+        .name = "TMU00",
+        .channel_offset = 0x4,
+        .timer_bit = 0,
+        .clockevent_rating = 200,
+};
+
+static struct resource tmu00_resources[] = {
+        [0] = {
+                .name   = "TMU00",
+                .start  = 0xfff60008,
+                .end    = 0xfff60013,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu00_device = {
+        .name           = "sh_tmu",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &tmu00_platform_data,
+        },
+        .resource       = tmu00_resources,
+        .num_resources  = ARRAY_SIZE(tmu00_resources),
+};
+
+static struct sh_timer_config tmu01_platform_data = {
+        .name = "TMU01",
+        .channel_offset = 0x10,
+        .timer_bit = 1,
+        .clocksource_rating = 200,
+};
+
+static struct resource tmu01_resources[] = {
+        [0] = {
+                .name   = "TMU01",
+                .start  = 0xfff60014,
+                .end    = 0xfff6001f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device tmu01_device = {
+        .name           = "sh_tmu",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &tmu01_platform_data,
+        },
+        .resource       = tmu01_resources,
+        .num_resources  = ARRAY_SIZE(tmu01_resources),
+};
+
+static struct resource i2c0_resources[] = {
+        [0] = {
+                .name   = "IIC0",
+                .start  = 0xe6820000,
+                .end    = 0xe6820425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(167),
+                .end    = gic_spi(170),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource i2c1_resources[] = {
+        [0] = {
+                .name   = "IIC1",
+                .start  = 0xe6822000,
+                .end    = 0xe6822425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(51),
+                .end    = gic_spi(54),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource i2c2_resources[] = {
+        [0] = {
+                .name   = "IIC2",
+                .start  = 0xe6824000,
+                .end    = 0xe6824425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(171),
+                .end    = gic_spi(174),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource i2c3_resources[] = {
+        [0] = {
+                .name   = "IIC3",
+                .start  = 0xe6826000,
+                .end    = 0xe6826425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(183),
+                .end    = gic_spi(186),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource i2c4_resources[] = {
+        [0] = {
+                .name   = "IIC4",
+                .start  = 0xe6828000,
+                .end    = 0xe6828425 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(187),
+                .end    = gic_spi(190),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c0_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 0,
+        .resource       = i2c0_resources,
+        .num_resources  = ARRAY_SIZE(i2c0_resources),
+};
+
+static struct platform_device i2c1_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 1,
+        .resource       = i2c1_resources,
+        .num_resources  = ARRAY_SIZE(i2c1_resources),
+};
+
+static struct platform_device i2c2_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 2,
+        .resource       = i2c2_resources,
+        .num_resources  = ARRAY_SIZE(i2c2_resources),
+};
+
+static struct platform_device i2c3_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 3,
+        .resource       = i2c3_resources,
+        .num_resources  = ARRAY_SIZE(i2c3_resources),
+};
+
+static struct platform_device i2c4_device = {
+        .name           = "i2c-sh_mobile",
+        .id             = 4,
+        .resource       = i2c4_resources,
+        .num_resources  = ARRAY_SIZE(i2c4_resources),
+};
+
+static struct platform_device *sh73a0_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
+        &scif8_device,
+        &cmt10_device,
+        &tmu00_device,
+        &tmu01_device,
+};
+
+static struct platform_device *sh73a0_late_devices[] __initdata = {
+        &i2c0_device,
+        &i2c1_device,
+        &i2c2_device,
+        &i2c3_device,
+        &i2c4_device,
+};
+
+void __init sh73a0_add_standard_devices(void)
+{
+        platform_add_devices(sh73a0_early_devices,
+                            ARRAY_SIZE(sh73a0_early_devices));
+        platform_add_devices(sh73a0_late_devices,
+                            ARRAY_SIZE(sh73a0_late_devices));
+}
+
+void __init sh73a0_add_early_devices(void)
+{
+        early_platform_add_devices(sh73a0_early_devices,
+                                   ARRAY_SIZE(sh73a0_early_devices));
+}
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
new file mode 100644
index 000000000000..a156d2108df1
--- /dev/null
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -0,0 +1,97 @@
+/*
+ * SMP support for R-Mobile / SH-Mobile - sh73a0 portion
+ *
+ * Copyright (C) 2010  Magnus Damm
+ * Copyright (C) 2010  Takashi Yoshii
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <mach/common.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_twd.h>
+#include <asm/hardware/gic.h>
+
+#define WUPCR           0xe6151010
+#define SRESCR          0xe6151018
+#define PSTR            0xe6151040
+#define SBAR            0xe6180020
+#define APARMBAREA      0xe6f10020
+
+static void __iomem *scu_base_addr(void)
+{
+        return (void __iomem *)0xf0000000;
+}
+
+static DEFINE_SPINLOCK(scu_lock);
+static unsigned long tmp;
+
+static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
+{
+        void __iomem *scu_base = scu_base_addr();
+
+        spin_lock(&scu_lock);
+        tmp = __raw_readl(scu_base + 8);
+        tmp &= ~clr;
+        tmp |= set;
+        spin_unlock(&scu_lock);
+
+        /* disable cache coherency after releasing the lock */
+        __raw_writel(tmp, scu_base + 8);
+}
+
+unsigned int __init sh73a0_get_core_count(void)
+{
+        void __iomem *scu_base = scu_base_addr();
+
+        return scu_get_core_count(scu_base);
+}
+
+void __cpuinit sh73a0_secondary_init(unsigned int cpu)
+{
+        gic_secondary_init(0);
+}
+
+int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
+{
+        /* enable cache coherency */
+        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+
+        if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
+                __raw_writel(1 << cpu, __io(WUPCR));    /* wake up */
+        else
+                __raw_writel(1 << cpu, __io(SRESCR));   /* reset */
+
+        return 0;
+}
+
+void __init sh73a0_smp_prepare_cpus(void)
+{
+#ifdef CONFIG_HAVE_ARM_TWD
+        twd_base = (void __iomem *)0xf0000600;
+#endif
+
+        scu_enable(scu_base_addr());
+
+        /* Map the reset vector (in headsmp.S) */
+        __raw_writel(0, __io(APARMBAREA));      /* 4k */
+        __raw_writel(__pa(shmobile_secondary_vector), __io(SBAR));
+
+        /* enable cache coherency on CPU0 */
+        modify_scu_cpu_psr(0, 3 << (0 * 8));
+}
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
index ba32a15127ab..3970a9cdce26 100644
--- a/arch/arm/mach-tcc8k/clock.c
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -12,8 +12,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/spinlock.h>
-
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 #include <mach/clock.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c
index 78d06008841d..e0a8d609afe1 100644
--- a/arch/arm/mach-tcc8k/time.c
+++ b/arch/arm/mach-tcc8k/time.c
@@ -35,7 +35,6 @@ static struct clocksource clocksource_tcc = {
         .rating         = 200,
         .read           = tcc_get_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 28,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -103,9 +102,7 @@ static int __init tcc_clockevent_init(struct clk *clock)
 {
         unsigned int c = clk_get_rate(clock);
 
-        clocksource_tcc.mult = clocksource_hz2mult(c,
-                                        clocksource_tcc.shift);
-        clocksource_register(&clocksource_tcc);
+        clocksource_register_hz(&clocksource_tcc, c);
 
         clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
                                         clockevent_tcc.shift);
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index ae19f95585be..77948e0f4909 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -25,7 +25,7 @@
 #include <linux/slab.h>
 #include <linux/seq_file.h>
 #include <linux/regulator/consumer.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 #include "clock.h"
 #include "board.h"
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index 94fd859770f1..083a4cfc6cf0 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -21,7 +21,7 @@
 #define __MACH_TEGRA_CLOCK_H
 
 #include <linux/list.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 #define DIV_BUS                 (1 << 0)
 #define DIV_U71                 (1 << 1)
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 8e7f115aa21e..a5cb1ce76ff2 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -11,12 +11,9 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
-#include <linux/completion.h>
 
 #include <asm/cacheflush.h>
 
-static DECLARE_COMPLETION(cpu_killed);
-
 static inline void cpu_enter_lowpower(void)
 {
         unsigned int v;
@@ -29,13 +26,13 @@ static inline void cpu_enter_lowpower(void)
          * Turn off coherency
          */
         "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, #0x20\n"
+        "       bic     %0, %0, %2\n"
         "       mcr     p15, 0, %0, c1, c0, 1\n"
         "       mrc     p15, 0, %0, c1, c0, 0\n"
         "       bic     %0, %0, #0x04\n"
         "       mcr     p15, 0, %0, c1, c0, 0\n"
           : "=&r" (v)
-          : "r" (0)
+          : "r" (0), "Ir" (CR_C)
           : "cc");
 }
 
@@ -45,17 +42,17 @@ static inline void cpu_leave_lowpower(void)
 
         asm volatile(
         "mrc    p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, #0x04\n"
+        "       orr     %0, %0, %1\n"
         "       mcr     p15, 0, %0, c1, c0, 0\n"
         "       mrc     p15, 0, %0, c1, c0, 1\n"
         "       orr     %0, %0, #0x20\n"
         "       mcr     p15, 0, %0, c1, c0, 1\n"
           : "=&r" (v)
-          :
+          : "Ir" (CR_C)
           : "cc");
 }
 
-static inline void platform_do_lowpower(unsigned int cpu)
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 {
         /*
          * there is no power-control hardware on this platform, so all
@@ -79,22 +76,19 @@ static inline void platform_do_lowpower(unsigned int cpu)
                 /*}*/
 
                 /*
-                 * getting here, means that we have come out of WFI without
+                 * Getting here, means that we have come out of WFI without
                  * having been woken up - this shouldn't happen
                  *
-                 * The trouble is, letting people know about this is not really
-                 * possible, since we are currently running incoherently, and
-                 * therefore cannot safely call printk() or anything else
+                 * Just note it happening - when we're woken, we can report
+                 * its occurrence.
                  */
-#ifdef DEBUG
-                printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu);
-#endif
+                (*spurious)++;
         }
 }
 
 int platform_cpu_kill(unsigned int cpu)
 {
-        return wait_for_completion_timeout(&cpu_killed, 5000);
+        return 1;
 }
 
 /*
@@ -104,30 +98,22 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-#ifdef DEBUG
-        unsigned int this_cpu = hard_smp_processor_id();
-
-        if (cpu != this_cpu) {
-                printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
-                           this_cpu, cpu);
-                BUG();
-        }
-#endif
-
-        printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
-        complete(&cpu_killed);
+        int spurious = 0;
 
         /*
          * we're ready for shutdown now, so do it
          */
         cpu_enter_lowpower();
-        platform_do_lowpower(cpu);
+        platform_do_lowpower(cpu, &spurious);
 
         /*
          * bring this CPU back into the world of cache
          * coherency, and then restore interrupts
          */
         cpu_leave_lowpower();
+
+        if (spurious)
+                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 }
 
 int platform_cpu_disable(unsigned int cpu)
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
index 2ba9e5c9d2f6..dd165c53889d 100644
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -16,8 +16,8 @@
 #include <mach/io.h>
 
 #if defined(CONFIG_ARM_GIC)
-
-#include <asm/hardware/gic.h>
+#define HAVE_GET_IRQNR_PREAMBLE
+#include <asm/hardware/entry-macro-gic.S>
 
         /* Uses the GIC interrupt controller built into the cpu */
 #define ICTRL_BASE (IO_CPU_VIRT + 0x100)
@@ -32,68 +32,6 @@
 
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
-
-        /*
-         * The interrupt numbering scheme is defined in the
-         * interrupt controller spec.  To wit:
-         *
-         * Interrupts 0-15 are IPI
-         * 16-28 are reserved
-         * 29-31 are local.  We allow 30 to be used for the watchdog.
-         * 32-1020 are global
-         * 1021-1022 are reserved
-         * 1023 is "spurious" (no interrupt)
-         *
-         * For now, we ignore all local interrupts so only return an interrupt
-         * if it's between 30 and 1020.  The test_for_ipi routine below will
-         * pick up on IPIs.
-         *
-         * A simple read from the controller will tell us the number of the
-         * highest priority enabled interrupt.  We then just need to check
-         * whether it is in the valid range for an IRQ (30-1020 inclusive).
-         */
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-        /* bits 12-10 = src CPU, 9-0 = int # */
-        ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-
-        ldr             \tmp, =1021
-
-        bic     \irqnr, \irqstat, #0x1c00
-
-        cmp     \irqnr, #29
-        cmpcc   \irqnr, \irqnr
-        cmpne   \irqnr, \tmp
-        cmpcs   \irqnr, \irqnr
-
-        .endm
-
-        /* We assume that irqstat (the raw value of the IRQ acknowledge
-         * register) is preserved from the macro above.
-         * If there is an IPI, we immediately signal end of interrupt on the
-         * controller, since this requires the original irqstat value which
-         * we won't easily be able to recreate later.
-         */
-
-        .macro test_for_ipi, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #16
-        strcc   \irqstat, [\base, #GIC_CPU_EOI]
-        cmpcs   \irqnr, \irqnr
-        .endm
-
-        /* As above, this assumes that irqstat and base are preserved.. */
-
-        .macro test_for_ltirq, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        mov     \tmp, #0
-        cmp     \irqnr, #29
-        moveq   \tmp, #1
-        streq   \irqstat, [\base, #GIC_CPU_EOI]
-        cmp     \tmp, #0
-        .endm
-
 #else
         /* legacy interrupt controller for AP16 */
         .macro  disable_fiq
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
index f0981b1ac59e..4cea2230c8dc 100644
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -65,8 +65,8 @@
 
 #ifndef __ASSEMBLER__
 
-#define __arch_ioremap(p, s, t) tegra_ioremap(p, s, t)
-#define __arch_iounmap(v)       tegra_iounmap(v)
+#define __arch_ioremap          tegra_ioremap
+#define __arch_iounmap          tegra_iounmap
 
 void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
 void tegra_iounmap(volatile void __iomem *addr);
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h
new file mode 100644
index 000000000000..3ad086e859c3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/sdhci.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-arm/arch-tegra/include/mach/sdhci.h
+ *
+ * Copyright (C) 2009 Palm, Inc.
+ * Author: Yvonne Yip <y@palm.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ASM_ARM_ARCH_TEGRA_SDHCI_H
+#define __ASM_ARM_ARCH_TEGRA_SDHCI_H
+
+#include <linux/mmc/host.h>
+
+struct tegra_sdhci_platform_data {
+        int cd_gpio;
+        int wp_gpio;
+        int power_gpio;
+        int is_8bit;
+};
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index e4a34a35a544..c8221b38ee7c 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -2,21 +2,13 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
-#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
  */
-static inline void smp_cross_call(const struct cpumask *mask)
-{
-        gic_raise_softirq(mask, 1);
-}
-
-/*
- * Do nothing on MPcore.
- */
-static inline void smp_cross_call_done(cpumask_t callmap)
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
 {
+        gic_raise_softirq(mask, ipi);
 }
 
 #endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 50a8dfb9a0cf..5407de01abf0 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -94,8 +94,8 @@ void __init tegra_init_irq(void)
                 writel(0, ictlr_to_virt(i) + ICTLR_CPU_IEP_CLASS);
         }
 
-        gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 29);
-        gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+        gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
+                 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 
         gic = get_irq_chip(29);
         gic_unmask_irq = gic->unmask;
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1c0fd92cab39..ec1f68924edf 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -22,7 +22,6 @@
 #include <asm/cacheflush.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/localtimer.h>
 #include <asm/smp_scu.h>
 
 #include <mach/iomap.h>
@@ -41,14 +40,12 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        trace_hardirqs_off();
-
         /*
          * if any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100);
+        gic_secondary_init(0);
 
         /*
          * Synchronise with the boot thread.
@@ -117,24 +114,20 @@ void __init smp_init_cpus(void)
 {
         unsigned int i, ncores = scu_get_core_count(scu_base);
 
+        if (ncores > NR_CPUS) {
+                printk(KERN_ERR "Tegra: no. of cores (%u) greater than configured (%u), clipping\n",
+                        ncores, NR_CPUS);
+                ncores = NR_CPUS;
+        }
+
         for (i = 0; i < ncores; i++)
                 cpu_set(i, cpu_possible_map);
 }
 
-void __init smp_prepare_cpus(unsigned int max_cpus)
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
-        unsigned int ncores = scu_get_core_count(scu_base);
-        unsigned int cpu = smp_processor_id();
         int i;
 
-        smp_store_cpu_info(cpu);
-
-        /*
-         * are we trying to boot more cores than exist?
-         */
-        if (max_cpus > ncores)
-                max_cpus = ncores;
-
         /*
          * Initialise the present map, which describes the set of CPUs
          * actually populated at the present time.
@@ -142,15 +135,5 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
-        /*
-         * Initialise the SCU if there are more than one CPU and let
-         * them know where to start. Note that, on modern versions of
-         * MILO, the "poke" doesn't actually do anything until each
-         * individual core is sent a soft interrupt to get it out of
-         * WFI
-         */
-        if (max_cpus > 1) {
-                percpu_timer_setup();
-                scu_enable(scu_base);
-        }
+        scu_enable(scu_base);
 }
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index ae3b308e22a4..f0dae6d8ba52 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -24,8 +24,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/hrtimer.h>
-
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 #include <mach/iomap.h>
 
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 9057d6fd1d31..7b8ad1f98f44 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -18,6 +18,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/sched.h>
 #include <linux/time.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -25,10 +26,10 @@
 #include <linux/clocksource.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <linux/cnt32_to_63.h>
 
 #include <asm/mach/time.h>
 #include <asm/localtimer.h>
+#include <asm/sched_clock.h>
 
 #include <mach/iomap.h>
 #include <mach/irqs.h>
@@ -91,7 +92,7 @@ static void tegra_timer_set_mode(enum clock_event_mode mode,
 
 static cycle_t tegra_clocksource_read(struct clocksource *cs)
 {
-        return cnt32_to_63(timer_readl(TIMERUS_CNTR_1US));
+        return timer_readl(TIMERUS_CNTR_1US);
 }
 
 static struct clock_event_device tegra_clockevent = {
@@ -106,14 +107,29 @@ static struct clocksource tegra_clocksource = {
         .name   = "timer_us",
         .rating = 300,
         .read   = tegra_clocksource_read,
-        .mask   = 0x7FFFFFFFFFFFFFFFULL,
+        .mask   = CLOCKSOURCE_MASK(32),
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-unsigned long long sched_clock(void)
+static DEFINE_CLOCK_DATA(cd);
+
+/*
+ * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60).
+ * This gives a resolution of about 1us and a wrap period of about 1h11min.
+ */
+#define SC_MULT         4194304000u
+#define SC_SHIFT        22
+
+unsigned long long notrace sched_clock(void)
 {
-        return clocksource_cyc2ns(tegra_clocksource.read(&tegra_clocksource),
-                tegra_clocksource.mult, tegra_clocksource.shift);
+        u32 cyc = timer_readl(TIMERUS_CNTR_1US);
+        return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
+}
+
+static void notrace tegra_update_sched_clock(void)
+{
+        u32 cyc = timer_readl(TIMERUS_CNTR_1US);
+        update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
@@ -158,6 +174,9 @@ static void __init tegra_init_timer(void)
                 WARN(1, "Unknown clock rate");
         }
 
+        init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
+                               1000000, SC_MULT, SC_SHIFT);
+
         if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
                 printk(KERN_ERR "Failed to register clocksource\n");
                 BUG();
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 7458fc6df5c6..fabcc49abe80 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -25,8 +25,8 @@
 #include <linux/timer.h>
 #include <linux/io.h>
 #include <linux/seq_file.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
 #include <mach/hardware.h>
 #include <mach/syscon.h>
 
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 3fc4472719be..3ec58bd2d6e4 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -9,6 +9,7 @@
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  */
 #include <linux/interrupt.h>
+#include <linux/sched.h>
 #include <linux/time.h>
 #include <linux/timex.h>
 #include <linux/clockchips.h>
@@ -21,6 +22,7 @@
 #include <mach/hardware.h>
 
 /* Generic stuff */
+#include <asm/sched_clock.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
@@ -352,12 +354,18 @@ static struct clocksource clocksource_u300_1mhz = {
  * this wraps around for now, since it is just a relative time
  * stamp. (Inspired by OMAP implementation.)
  */
+static DEFINE_CLOCK_DATA(cd);
+
 unsigned long long notrace sched_clock(void)
 {
-        return clocksource_cyc2ns(clocksource_u300_1mhz.read(
-                                  &clocksource_u300_1mhz),
-                                  clocksource_u300_1mhz.mult,
-                                  clocksource_u300_1mhz.shift);
+        u32 cyc = readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
+
+static void notrace u300_update_sched_clock(void)
+{
+        u32 cyc = readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+        update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 
@@ -375,6 +383,8 @@ static void __init u300_timer_init(void)
         clk_enable(clk);
         rate = clk_get_rate(clk);
 
+        init_sched_clock(&cd, u300_update_sched_clock, 32, rate);
+
         /*
          * Disable the "OS" and "DD" timers - these are designed for Symbian!
          * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
@@ -412,9 +422,7 @@ static void __init u300_timer_init(void)
         writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
                 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
 
-        clocksource_calc_mult_shift(&clocksource_u300_1mhz,
-                                    rate, APPTIMER_MIN_RANGE);
-        if (clocksource_register(&clocksource_u300_1mhz))
+        if (clocksource_register_hz(&clocksource_u300_1mhz, rate))
                 printk(KERN_ERR "timer: failed to initialize clock "
                        "source %s\n", clocksource_u300_1mhz.name);
 
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 2dd44a0b4615..247caa3400d0 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -7,28 +7,30 @@ config UX500_SOC_COMMON
         select HAS_MTU
         select NOMADIK_GPIO
 
-config UX500_SOC_DB8500
-        bool
+menu "Ux500 SoC"
 
 config UX500_SOC_DB5500
-        bool
+        bool "DB5500"
+
+config UX500_SOC_DB8500
+        bool "DB8500"
+
+endmenu
 
-choice
-        prompt "Ux500 target platform"
-        default MACH_U8500_MOP
+menu "Ux500 target platform"
 
-config MACH_U8500_MOP
+config MACH_U8500
         bool "U8500 Development platform"
-        select UX500_SOC_DB8500
+        depends on UX500_SOC_DB8500
         help
           Include support for the mop500 development platform.
 
 config MACH_U5500
         bool "U5500 Development platform"
-        select UX500_SOC_DB5500
+        depends on UX500_SOC_DB5500
         help
           Include support for the U5500 development platform.
-endchoice
+endmenu
 
 config UX500_DEBUG_UART
         int "Ux500 UART to use for low-level debug"
@@ -39,14 +41,14 @@ config UX500_DEBUG_UART
 
 config U5500_MODEM_IRQ
         bool "Modem IRQ support"
-        depends on MACH_U5500
+        depends on UX500_SOC_DB5500
         default y
         help
           Add support for handling IRQ:s from modem side
 
 config U5500_MBOX
         bool "Mailbox support"
-        depends on MACH_U5500 && U5500_MODEM_IRQ
+        depends on U5500_MODEM_IRQ
         default y
         help
           Add support for U5500 mailbox communication with modem side
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 9e27a84433cb..53ebb429e971 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,14 +2,17 @@
 # Makefile for the linux kernel, U8500 machine.
 #
 
-obj-y                           := clock.o cpu.o devices.o
-obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o devices-db5500.o
+obj-y                           := clock.o cpu.o devices.o devices-common.o \
+                                   id.o
+obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o prcmu.o
-obj-$(CONFIG_MACH_U8500_MOP)    += board-mop500.o board-mop500-sdi.o
-obj-$(CONFIG_MACH_U5500)        += board-u5500.o
+obj-$(CONFIG_MACH_U8500)        += board-mop500.o board-mop500-sdi.o \
+                                board-mop500-keypads.o
+obj-$(CONFIG_MACH_U5500)        += board-u5500.o board-u5500-sdi.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
 obj-$(CONFIG_REGULATOR_AB8500)  += board-mop500-regulators.o
-obj-$(CONFIG_U5500_MODEM_IRQ)   += modem_irq.o
-obj-$(CONFIG_U5500_MBOX)        += mbox.o
+obj-$(CONFIG_U5500_MODEM_IRQ)   += modem-irq-db5500.o
+obj-$(CONFIG_U5500_MBOX)        += mbox-db5500.o
+obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
diff --git a/arch/arm/mach-ux500/board-mop500-keypads.c b/arch/arm/mach-ux500/board-mop500-keypads.c
new file mode 100644
index 000000000000..70318c354d32
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-keypads.c
@@ -0,0 +1,229 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Keypad layouts for various boards
+ */
+
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/stmpe.h>
+#include <linux/mfd/tc3589x.h>
+#include <linux/input/matrix_keypad.h>
+
+#include <plat/pincfg.h>
+#include <plat/ske.h>
+
+#include <mach/devices.h>
+#include <mach/hardware.h>
+
+#include "devices-db8500.h"
+#include "board-mop500.h"
+
+/* STMPE/SKE keypad use this key layout */
+static const unsigned int mop500_keymap[] = {
+        KEY(2, 5, KEY_END),
+        KEY(4, 1, KEY_POWER),
+        KEY(3, 5, KEY_VOLUMEDOWN),
+        KEY(1, 3, KEY_3),
+        KEY(5, 2, KEY_RIGHT),
+        KEY(5, 0, KEY_9),
+
+        KEY(0, 5, KEY_MENU),
+        KEY(7, 6, KEY_ENTER),
+        KEY(4, 5, KEY_0),
+        KEY(6, 7, KEY_2),
+        KEY(3, 4, KEY_UP),
+        KEY(3, 3, KEY_DOWN),
+
+        KEY(6, 4, KEY_SEND),
+        KEY(6, 2, KEY_BACK),
+        KEY(4, 2, KEY_VOLUMEUP),
+        KEY(5, 5, KEY_1),
+        KEY(4, 3, KEY_LEFT),
+        KEY(3, 2, KEY_7),
+};
+
+static const struct matrix_keymap_data mop500_keymap_data = {
+        .keymap         = mop500_keymap,
+        .keymap_size    = ARRAY_SIZE(mop500_keymap),
+};
+
+/*
+ * Nomadik SKE keypad
+ */
+#define ROW_PIN_I0      164
+#define ROW_PIN_I1      163
+#define ROW_PIN_I2      162
+#define ROW_PIN_I3      161
+#define ROW_PIN_I4      156
+#define ROW_PIN_I5      155
+#define ROW_PIN_I6      154
+#define ROW_PIN_I7      153
+#define COL_PIN_O0      168
+#define COL_PIN_O1      167
+#define COL_PIN_O2      166
+#define COL_PIN_O3      165
+#define COL_PIN_O4      160
+#define COL_PIN_O5      159
+#define COL_PIN_O6      158
+#define COL_PIN_O7      157
+
+#define SKE_KPD_MAX_ROWS        8
+#define SKE_KPD_MAX_COLS        8
+
+static int ske_kp_rows[] = {
+        ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3,
+        ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7,
+};
+
+/*
+ * ske_set_gpio_row: request and set gpio rows
+ */
+static int ske_set_gpio_row(int gpio)
+{
+        int ret;
+
+        ret = gpio_request(gpio, "ske-kp");
+        if (ret < 0) {
+                pr_err("ske_set_gpio_row: gpio request failed\n");
+                return ret;
+        }
+
+        ret = gpio_direction_output(gpio, 1);
+        if (ret < 0) {
+                pr_err("ske_set_gpio_row: gpio direction failed\n");
+                gpio_free(gpio);
+        }
+
+        return ret;
+}
+
+/*
+ * ske_kp_init - enable the gpio configuration
+ */
+static int ske_kp_init(void)
+{
+        int ret, i;
+
+        for (i = 0; i < SKE_KPD_MAX_ROWS; i++) {
+                ret = ske_set_gpio_row(ske_kp_rows[i]);
+                if (ret < 0) {
+                        pr_err("ske_kp_init: failed init\n");
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
+static struct ske_keypad_platform_data ske_keypad_board = {
+        .init           = ske_kp_init,
+        .keymap_data    = &mop500_keymap_data,
+        .no_autorepeat  = true,
+        .krow           = SKE_KPD_MAX_ROWS,     /* 8x8 matrix */
+        .kcol           = SKE_KPD_MAX_COLS,
+        .debounce_ms    = 40,                   /* in millisecs */
+};
+
+/*
+ * STMPE1601
+ */
+static struct stmpe_keypad_platform_data stmpe1601_keypad_data = {
+        .debounce_ms    = 64,
+        .scan_count     = 8,
+        .no_autorepeat  = true,
+        .keymap_data    = &mop500_keymap_data,
+};
+
+static struct stmpe_platform_data stmpe1601_data = {
+        .id             = 1,
+        .blocks         = STMPE_BLOCK_KEYPAD,
+        .irq_trigger    = IRQF_TRIGGER_FALLING,
+        .irq_base       = MOP500_STMPE1601_IRQ(0),
+        .keypad         = &stmpe1601_keypad_data,
+        .autosleep      = true,
+        .autosleep_timeout = 1024,
+};
+
+static struct i2c_board_info mop500_i2c0_devices_stuib[] = {
+        {
+                I2C_BOARD_INFO("stmpe1601", 0x40),
+                .irq = NOMADIK_GPIO_TO_IRQ(218),
+                .platform_data = &stmpe1601_data,
+                .flags = I2C_CLIENT_WAKE,
+        },
+};
+
+/*
+ * TC35893
+ */
+
+static const unsigned int uib_keymap[] = {
+        KEY(3, 1, KEY_END),
+        KEY(4, 1, KEY_POWER),
+        KEY(6, 4, KEY_VOLUMEDOWN),
+        KEY(4, 2, KEY_EMAIL),
+        KEY(3, 3, KEY_RIGHT),
+        KEY(2, 5, KEY_BACKSPACE),
+
+        KEY(6, 7, KEY_MENU),
+        KEY(5, 0, KEY_ENTER),
+        KEY(4, 3, KEY_0),
+        KEY(3, 4, KEY_DOT),
+        KEY(5, 2, KEY_UP),
+        KEY(3, 5, KEY_DOWN),
+
+        KEY(4, 5, KEY_SEND),
+        KEY(0, 5, KEY_BACK),
+        KEY(6, 2, KEY_VOLUMEUP),
+        KEY(1, 3, KEY_SPACE),
+        KEY(7, 6, KEY_LEFT),
+        KEY(5, 5, KEY_SEARCH),
+};
+
+static struct matrix_keymap_data uib_keymap_data = {
+        .keymap         = uib_keymap,
+        .keymap_size    = ARRAY_SIZE(uib_keymap),
+};
+
+static struct tc3589x_keypad_platform_data tc35893_data = {
+        .krow = TC_KPD_ROWS,
+        .kcol = TC_KPD_COLUMNS,
+        .debounce_period = TC_KPD_DEBOUNCE_PERIOD,
+        .settle_time = TC_KPD_SETTLE_TIME,
+        .irqtype = IRQF_TRIGGER_FALLING,
+        .enable_wakeup = true,
+        .keymap_data    = &uib_keymap_data,
+        .no_autorepeat  = true,
+};
+
+static struct tc3589x_platform_data tc3589x_keypad_data = {
+        .block = TC3589x_BLOCK_KEYPAD,
+        .keypad = &tc35893_data,
+        .irq_base = MOP500_EGPIO_IRQ_BASE,
+};
+
+static struct i2c_board_info mop500_i2c0_devices_uib[] = {
+        {
+                I2C_BOARD_INFO("tc3589x", 0x44),
+                .platform_data = &tc3589x_keypad_data,
+                .irq = NOMADIK_GPIO_TO_IRQ(218),
+                .flags = I2C_CLIENT_WAKE,
+        },
+};
+
+void mop500_keypad_init(void)
+{
+        db8500_add_ske_keypad(&ske_keypad_board);
+
+        i2c_register_board_info(0, mop500_i2c0_devices_stuib,
+                        ARRAY_SIZE(mop500_i2c0_devices_stuib));
+
+        i2c_register_board_info(0, mop500_i2c0_devices_uib,
+                        ARRAY_SIZE(mop500_i2c0_devices_uib));
+
+}
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index bac995665b58..4b996676594e 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -16,10 +16,24 @@
 #include <mach/devices.h>
 #include <mach/hardware.h>
 
+#include "devices-db8500.h"
 #include "pins-db8500.h"
 #include "board-mop500.h"
 
 static pin_cfg_t mop500_sdi_pins[] = {
+        /* SDI0 (MicroSD slot) */
+        GPIO18_MC0_CMDDIR,
+        GPIO19_MC0_DAT0DIR,
+        GPIO20_MC0_DAT2DIR,
+        GPIO21_MC0_DAT31DIR,
+        GPIO22_MC0_FBCLK,
+        GPIO23_MC0_CLK,
+        GPIO24_MC0_CMD,
+        GPIO25_MC0_DAT0,
+        GPIO26_MC0_DAT1,
+        GPIO27_MC0_DAT2,
+        GPIO28_MC0_DAT3,
+
         /* SDI4 (on-board eMMC) */
         GPIO197_MC4_DAT3,
         GPIO198_MC4_DAT2,
@@ -50,6 +64,55 @@ static pin_cfg_t mop500_sdi2_pins[] = {
 };
 
 /*
+ * SDI 0 (MicroSD slot)
+ */
+
+/* MMCIPOWER bits */
+#define MCI_DATA2DIREN          (1 << 2)
+#define MCI_CMDDIREN            (1 << 3)
+#define MCI_DATA0DIREN          (1 << 4)
+#define MCI_DATA31DIREN         (1 << 5)
+#define MCI_FBCLKEN             (1 << 7)
+
+static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
+                                   unsigned char power_mode)
+{
+        if (power_mode == MMC_POWER_UP)
+                gpio_set_value_cansleep(GPIO_SDMMC_EN, 1);
+        else if (power_mode == MMC_POWER_OFF)
+                gpio_set_value_cansleep(GPIO_SDMMC_EN, 0);
+
+        return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
+               MCI_DATA2DIREN | MCI_DATA31DIREN;
+}
+
+static struct mmci_platform_data mop500_sdi0_data = {
+        .vdd_handler    = mop500_sdi0_vdd_handler,
+        .ocr_mask       = MMC_VDD_29_30,
+        .f_max          = 100000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA,
+        .gpio_cd        = GPIO_SDMMC_CD,
+        .gpio_wp        = -1,
+};
+
+void mop500_sdi_tc35892_init(void)
+{
+        int ret;
+
+        ret = gpio_request(GPIO_SDMMC_EN, "SDMMC_EN");
+        if (!ret)
+                ret = gpio_request(GPIO_SDMMC_1V8_3V_SEL,
+                                   "GPIO_SDMMC_1V8_3V_SEL");
+        if (ret)
+                return;
+
+        gpio_direction_output(GPIO_SDMMC_1V8_3V_SEL, 1);
+        gpio_direction_output(GPIO_SDMMC_EN, 0);
+
+        db8500_add_sdi0(&mop500_sdi0_data);
+}
+
+/*
  * SDI 2 (POP eMMC, not on DB8500ed)
  */
 
@@ -74,18 +137,24 @@ static struct mmci_platform_data mop500_sdi4_data = {
         .gpio_wp        = -1,
 };
 
-void mop500_sdi_init(void)
+void __init mop500_sdi_init(void)
 {
         nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins));
 
-        u8500_sdi2_device.dev.platform_data = &mop500_sdi2_data;
-        u8500_sdi4_device.dev.platform_data = &mop500_sdi4_data;
+        /*
+         * sdi0 will finally be added when the TC35892 initializes and calls
+         * mop500_sdi_tc35892_init() above.
+         */
 
+        /* PoP:ed eMMC */
         if (!cpu_is_u8500ed()) {
                 nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
-                amba_device_register(&u8500_sdi2_device, &iomem_resource);
+                /* POP eMMC on v1.0 has problems with high speed */
+                if (!cpu_is_u8500v10())
+                        mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
+                db8500_add_sdi2(&mop500_sdi2_data);
         }
 
         /* On-board eMMC */
-        amba_device_register(&u8500_sdi4_device, &iomem_resource);
+        db8500_add_sdi4(&mop500_sdi4_data);
 }
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index cac83a694880..a1c9ea1a66df 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -13,25 +13,26 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/ab8500.h>
-#include <linux/input/matrix_keypad.h>
+#include <linux/mfd/tc3589x.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <plat/pincfg.h>
 #include <plat/i2c.h>
-#include <plat/ske.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
 #include <mach/irqs.h>
 
+#include "devices-db8500.h"
 #include "pins-db8500.h"
 #include "board-mop500.h"
 
@@ -69,22 +70,12 @@ static pin_cfg_t mop500_pins[] = {
         GPIO166_KP_O2,
         GPIO167_KP_O1,
         GPIO168_KP_O0,
-};
 
-static void ab4500_spi_cs_control(u32 command)
-{
-        /* set the FRM signal, which is CS  - TODO */
-}
+        /* GPIO_EXP_INT */
+        GPIO217_GPIO,
 
-struct pl022_config_chip ab4500_chip_info = {
-        .com_mode = INTERRUPT_TRANSFER,
-        .iface = SSP_INTERFACE_MOTOROLA_SPI,
-        /* we can act as master only */
-        .hierarchy = SSP_MASTER,
-        .slave_tx_disable = 0,
-        .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
-        .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
-        .cs_control = ab4500_spi_cs_control,
+        /* STMPE1601 IRQ */
+        GPIO218_GPIO    | PIN_INPUT_PULLUP,
 };
 
 static struct ab8500_platform_data ab8500_platdata = {
@@ -93,9 +84,9 @@ static struct ab8500_platform_data ab8500_platdata = {
 
 static struct resource ab8500_resources[] = {
         [0] = {
-                .start = IRQ_AB8500,
-                .end = IRQ_AB8500,
-                .flags = IORESOURCE_IRQ
+                .start  = IRQ_DB8500_AB8500,
+                .end    = IRQ_DB8500_AB8500,
+                .flags  = IORESOURCE_IRQ
         }
 };
 
@@ -109,19 +100,6 @@ struct platform_device ab8500_device = {
         .resource = ab8500_resources,
 };
 
-static struct spi_board_info ab8500_spi_devices[] = {
-        {
-                .modalias = "ab8500-spi",
-                .controller_data = &ab4500_chip_info,
-                .platform_data = &ab8500_platdata,
-                .max_speed_hz = 12000000,
-                .bus_num = 0,
-                .chip_select = 0,
-                .mode = SPI_MODE_3,
-                .irq = IRQ_DB8500_AB8500,
-        },
-};
-
 static struct pl022_ssp_controller ssp0_platform_data = {
         .bus_id = 0,
         /* pl022 not yet supports dma */
@@ -132,6 +110,34 @@ static struct pl022_ssp_controller ssp0_platform_data = {
         .num_chipselect = 5,
 };
 
+/*
+ * TC35892
+ */
+
+static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base)
+{
+        mop500_sdi_tc35892_init();
+}
+
+static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = {
+        .gpio_base      = MOP500_EGPIO(0),
+        .setup          = mop500_tc35892_init,
+};
+
+static struct tc3589x_platform_data mop500_tc35892_data = {
+        .block          = TC3589x_BLOCK_GPIO,
+        .gpio           = &mop500_tc35892_gpio_data,
+        .irq_base       = MOP500_EGPIO_IRQ_BASE,
+};
+
+static struct i2c_board_info mop500_i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("tc3589x", 0x42),
+                .irq            = NOMADIK_GPIO_TO_IRQ(217),
+                .platform_data  = &mop500_tc35892_data,
+        },
+};
+
 #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
 static struct nmk_i2c_controller u8500_i2c##id##_data = { \
         /*                              \
@@ -161,159 +167,49 @@ U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
 U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
 U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
 
-static struct amba_device *amba_devs[] __initdata = {
-        &ux500_uart0_device,
-        &ux500_uart1_device,
-        &ux500_uart2_device,
-        &u8500_ssp0_device,
-};
-
-static const unsigned int ux500_keymap[] = {
-        KEY(2, 5, KEY_END),
-        KEY(4, 1, KEY_POWER),
-        KEY(3, 5, KEY_VOLUMEDOWN),
-        KEY(1, 3, KEY_3),
-        KEY(5, 2, KEY_RIGHT),
-        KEY(5, 0, KEY_9),
-
-        KEY(0, 5, KEY_MENU),
-        KEY(7, 6, KEY_ENTER),
-        KEY(4, 5, KEY_0),
-        KEY(6, 7, KEY_2),
-        KEY(3, 4, KEY_UP),
-        KEY(3, 3, KEY_DOWN),
-
-        KEY(6, 4, KEY_SEND),
-        KEY(6, 2, KEY_BACK),
-        KEY(4, 2, KEY_VOLUMEUP),
-        KEY(5, 5, KEY_1),
-        KEY(4, 3, KEY_LEFT),
-        KEY(3, 2, KEY_7),
-};
-
-static const struct matrix_keymap_data ux500_keymap_data = {
-        .keymap         = ux500_keymap,
-        .keymap_size    = ARRAY_SIZE(ux500_keymap),
-};
+static void __init mop500_i2c_init(void)
+{
+        db8500_add_i2c0(&u8500_i2c0_data);
+        db8500_add_i2c1(&u8500_i2c1_data);
+        db8500_add_i2c2(&u8500_i2c2_data);
+        db8500_add_i2c3(&u8500_i2c3_data);
+}
 
-/*
- * Nomadik SKE keypad
- */
-#define ROW_PIN_I0      164
-#define ROW_PIN_I1      163
-#define ROW_PIN_I2      162
-#define ROW_PIN_I3      161
-#define ROW_PIN_I4      156
-#define ROW_PIN_I5      155
-#define ROW_PIN_I6      154
-#define ROW_PIN_I7      153
-#define COL_PIN_O0      168
-#define COL_PIN_O1      167
-#define COL_PIN_O2      166
-#define COL_PIN_O3      165
-#define COL_PIN_O4      160
-#define COL_PIN_O5      159
-#define COL_PIN_O6      158
-#define COL_PIN_O7      157
-
-#define SKE_KPD_MAX_ROWS        8
-#define SKE_KPD_MAX_COLS        8
-
-static int ske_kp_rows[] = {
-        ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3,
-        ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7,
+/* add any platform devices here - TODO */
+static struct platform_device *platform_devs[] __initdata = {
 };
 
-/*
- * ske_set_gpio_row: request and set gpio rows
- */
-static int ske_set_gpio_row(int gpio)
+static void __init mop500_spi_init(void)
 {
-        int ret;
-
-        ret = gpio_request(gpio, "ske-kp");
-        if (ret < 0) {
-                pr_err("ske_set_gpio_row: gpio request failed\n");
-                return ret;
-        }
-
-        ret = gpio_direction_output(gpio, 1);
-        if (ret < 0) {
-                pr_err("ske_set_gpio_row: gpio direction failed\n");
-                gpio_free(gpio);
-        }
-
-        return ret;
+        db8500_add_ssp0(&ssp0_platform_data);
 }
 
-/*
- * ske_kp_init - enable the gpio configuration
- */
-static int ske_kp_init(void)
+static void __init mop500_uart_init(void)
 {
-        int ret, i;
-
-        for (i = 0; i < SKE_KPD_MAX_ROWS; i++) {
-                ret = ske_set_gpio_row(ske_kp_rows[i]);
-                if (ret < 0) {
-                        pr_err("ske_kp_init: failed init\n");
-                        return ret;
-                }
-        }
-
-        return 0;
+        db8500_add_uart0();
+        db8500_add_uart1();
+        db8500_add_uart2();
 }
 
-static struct ske_keypad_platform_data ske_keypad_board = {
-        .init           = ske_kp_init,
-        .keymap_data    = &ux500_keymap_data,
-        .no_autorepeat  = true,
-        .krow           = SKE_KPD_MAX_ROWS,     /* 8x8 matrix */
-        .kcol           = SKE_KPD_MAX_COLS,
-        .debounce_ms    = 40,                   /* in millsecs */
-};
-
-
-
-/* add any platform devices here - TODO */
-static struct platform_device *platform_devs[] __initdata = {
-        &u8500_i2c0_device,
-        &ux500_i2c1_device,
-        &ux500_i2c2_device,
-        &ux500_i2c3_device,
-        &ux500_ske_keypad_device,
-};
-
 static void __init u8500_init_machine(void)
 {
-        int i;
-
         u8500_init_devices();
 
         nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins));
 
-        u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data;
-        ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data;
-        ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data;
-        ux500_i2c3_device.dev.platform_data = &u8500_i2c3_data;
-        ux500_ske_keypad_device.dev.platform_data = &ske_keypad_board;
-
-        u8500_ssp0_device.dev.platform_data = &ssp0_platform_data;
-
-        /* Register the active AMBA devices on this board */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-
         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
+        mop500_i2c_init();
         mop500_sdi_init();
+        mop500_spi_init();
+        mop500_uart_init();
+
+        mop500_keypad_init();
+
+        platform_device_register(&ab8500_device);
 
-        /* If HW is early drop (ED) or V1.0 then use SPI to access AB8500 */
-        if (cpu_is_u8500ed() || cpu_is_u8500v10())
-                spi_register_board_info(ab8500_spi_devices,
-                        ARRAY_SIZE(ab8500_spi_devices));
-        else /* If HW is v.1.1 or later use I2C to access AB8500 */
-                platform_device_register(&ab8500_device);
+        i2c_register_board_info(0, mop500_i2c0_devices,
+                                ARRAY_SIZE(mop500_i2c0_devices));
 }
 
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 2d240322fa6f..3104ae2a02c2 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,6 +7,15 @@
 #ifndef __BOARD_MOP500_H
 #define __BOARD_MOP500_H
 
+#define MOP500_EGPIO(x)                 (NOMADIK_NR_GPIO + (x))
+
+/* GPIOs on the TC35892 expander */
+#define GPIO_SDMMC_CD                   MOP500_EGPIO(3)
+#define GPIO_SDMMC_EN                   MOP500_EGPIO(17)
+#define GPIO_SDMMC_1V8_3V_SEL           MOP500_EGPIO(18)
+
 extern void mop500_sdi_init(void);
+extern void mop500_sdi_tc35892_init(void);
+extern void mop500_keypad_init(void);
 
 #endif
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
new file mode 100644
index 000000000000..54712acc0394
--- /dev/null
+++ b/arch/arm/mach-ux500/board-u5500-sdi.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Hanumath Prasad <ulf.hansson@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/amba/mmci.h>
+#include <linux/mmc/host.h>
+#include <linux/gpio.h>
+
+#include <plat/pincfg.h>
+#include <mach/db5500-regs.h>
+#include <plat/ste_dma40.h>
+
+#include "pins-db5500.h"
+#include "devices-db5500.h"
+#include "ste-dma40-db5500.h"
+
+static pin_cfg_t u5500_sdi_pins[] = {
+        /* SDI0 (POP eMMC) */
+        GPIO5_MC0_DAT0          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO6_MC0_DAT1          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO7_MC0_DAT2          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO8_MC0_DAT3          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO9_MC0_DAT4          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO10_MC0_DAT5         | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO11_MC0_DAT6         | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO12_MC0_DAT7         | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO13_MC0_CMD          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO14_MC0_CLK          | PIN_DIR_OUTPUT | PIN_VAL_LOW,
+};
+
+static struct mmci_platform_data u5500_sdi0_data = {
+        .ocr_mask       = MMC_VDD_165_195,
+        .f_max          = 50000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_8_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED,
+        .gpio_cd        = -1,
+        .gpio_wp        = -1,
+};
+
+void __init u5500_sdi_init(void)
+{
+        nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins));
+
+        db5500_add_sdi0(&u5500_sdi0_data);
+}
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 1ca094a45e71..39d370c1f3b4 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -9,6 +9,7 @@
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <linux/gpio.h>
+#include <linux/irq.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -17,20 +18,24 @@
 #include <mach/devices.h>
 #include <mach/setup.h>
 
-static struct amba_device *amba_board_devs[] __initdata = {
-        &ux500_uart0_device,
-        &ux500_uart1_device,
-        &ux500_uart2_device,
-};
+#include "devices-db5500.h"
+
+static void __init u5500_uart_init(void)
+{
+        db5500_add_uart0();
+        db5500_add_uart1();
+        db5500_add_uart2();
+}
 
 static void __init u5500_init_machine(void)
 {
         u5500_init_devices();
 
-        amba_add_devices(amba_board_devs, ARRAY_SIZE(amba_board_devs));
+        u5500_sdi_init();
+        u5500_uart_init();
 }
 
-MACHINE_START(U8500, "ST-Ericsson U5500 Platform")
+MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
         .boot_params    = 0x00000100,
         .map_io         = u5500_map_io,
         .init_irq       = ux500_init_irq,
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 1675047daf20..b2b0a3b9be8f 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -13,13 +13,18 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 #include <plat/mtu.h>
 #include <mach/hardware.h>
 #include "clock.h"
 
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>      /* for copy_from_user */
+static LIST_HEAD(clk_list);
+#endif
+
 #define PRCC_PCKEN              0x00
 #define PRCC_PCKDIS             0x04
 #define PRCC_KCKEN              0x08
@@ -131,9 +136,8 @@ EXPORT_SYMBOL(clk_disable);
  */
 static unsigned long clk_mtu_get_rate(struct clk *clk)
 {
-        void __iomem *addr = __io_address(UX500_PRCMU_BASE)
-                + PRCM_TCR;
-        u32 tcr = readl(addr);
+        void __iomem *addr;
+        u32 tcr;
         int mtu = (int) clk->data;
         /*
          * One of these is selected eventually
@@ -144,6 +148,21 @@ static unsigned long clk_mtu_get_rate(struct clk *clk)
         unsigned long mturate;
         unsigned long retclk;
 
+        if (cpu_is_u5500())
+                addr = __io_address(U5500_PRCMU_BASE);
+        else if (cpu_is_u8500())
+                addr = __io_address(U8500_PRCMU_BASE);
+        else
+                ux500_unknown_soc();
+
+        /*
+         * On a startup, always conifgure the TCR to the doze mode;
+         * bootloaders do it for us. Do this in the kernel too.
+         */
+        writel(PRCM_TCR_DOZE_MODE, addr + PRCM_TCR);
+
+        tcr = readl(addr + PRCM_TCR);
+
         /* Get the rate from the parent as a default */
         if (clk->parent_periph)
                 mturate = clk_get_rate(clk->parent_periph);
@@ -153,45 +172,6 @@ static unsigned long clk_mtu_get_rate(struct clk *clk)
                 /* We need to be connected SOMEWHERE */
                 BUG();
 
-        /*
-         * Are we in doze mode?
-         * In this mode the parent peripheral or the fixed 32768 Hz
-         * clock is fed into the block.
-         */
-        if (!(tcr & PRCM_TCR_DOZE_MODE)) {
-                /*
-                 * Here we're using the clock input from the APE ULP
-                 * clock domain. But first: are the timers stopped?
-                 */
-                if (tcr & PRCM_TCR_STOPPED) {
-                        clk32k = 0;
-                        mturate = 0;
-                } else {
-                        /* Else default mode: 0 and 2.4 MHz */
-                        clk32k = 0;
-                        if (cpu_is_u5500())
-                                /* DB5500 divides by 8 */
-                                mturate /= 8;
-                        else if (cpu_is_u8500ed()) {
-                                /*
-                                 * This clocking setting must not be used
-                                 * in the ED chip, it is simply not
-                                 * connected anywhere!
-                                 */
-                                mturate = 0;
-                                BUG();
-                        } else
-                                /*
-                                 * In this mode the ulp38m4 clock is divided
-                                 * by a factor 16, on the DB8500 typically
-                                 * 38400000 / 16 ~ 2.4 MHz.
-                                 * TODO: Replace the constant with a reference
-                                 * to the ULP source once this is modeled.
-                                 */
-                                mturate = 38400000 / 16;
-                }
-        }
-
         /* Return the clock selected for this MTU */
         if (tcr & (1 << mtu))
                 retclk = clk32k;
@@ -317,6 +297,7 @@ static struct clkops clk_prcc_ops = {
 };
 
 static struct clk clk_32khz = {
+        .name =  "clk_32khz",
         .rate = 32000,
 };
 
@@ -366,94 +347,96 @@ static DEFINE_PRCMU_CLK(uiccclk,	0x4, 1, UICCCLK); /* v1 */
  */
 
 /* Peripheral Cluster #1 */
-static DEFINE_PRCC_CLK(1, i2c4,         10, 9, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, i2c4,         10, 9, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, gpio0,        9, -1, NULL);
-static DEFINE_PRCC_CLK(1, slimbus0,     8,  8, &clk_slimclk);
-static DEFINE_PRCC_CLK(1, spi3_ed,      7,  7, NULL);
-static DEFINE_PRCC_CLK(1, spi3_v1,      7, -1, NULL);
-static DEFINE_PRCC_CLK(1, i2c2,         6,  6, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, slimbus0,     8,  8, &clk_slimclk);
+static DEFINE_PRCC_CLK(1, spi3_ed,      7,  7, NULL);
+static DEFINE_PRCC_CLK(1, spi3_v1,      7, -1, NULL);
+static DEFINE_PRCC_CLK(1, i2c2,         6,  6, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, sdi0,         5,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(1, msp1_ed,      4,  4, &clk_msp02clk);
-static DEFINE_PRCC_CLK(1, msp1_v1,      4,  4, &clk_msp1clk);
-static DEFINE_PRCC_CLK(1, msp0,         3,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(1, i2c1,         2,  2, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, uart1,        1,  1, &clk_uartclk);
-static DEFINE_PRCC_CLK(1, uart0,        0,  0, &clk_uartclk);
+static DEFINE_PRCC_CLK(1, msp1_ed,      4,  4, &clk_msp02clk);
+static DEFINE_PRCC_CLK(1, msp1_v1,      4,  4, &clk_msp1clk);
+static DEFINE_PRCC_CLK(1, msp0,         3,  3, &clk_msp02clk);
+static DEFINE_PRCC_CLK(1, i2c1,         2,  2, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, uart1,        1,  1, &clk_uartclk);
+static DEFINE_PRCC_CLK(1, uart0,        0,  0, &clk_uartclk);
 
 /* Peripheral Cluster #2 */
 
 static DEFINE_PRCC_CLK(2, gpio1_ed,     12, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssitx_ed,     11, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssirx_ed,     10, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi0_ed,       9, -1, NULL);
-static DEFINE_PRCC_CLK(2, sdi3_ed,       8,  6, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, sdi1_ed,       7,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, msp2_ed,       6,  4, &clk_msp02clk);
-static DEFINE_PRCC_CLK(2, sdi4_ed,       4,  2, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, ssitx_ed,     11, -1, NULL);
+static DEFINE_PRCC_CLK(2, ssirx_ed,     10, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi0_ed,       9, -1, NULL);
+static DEFINE_PRCC_CLK(2, sdi3_ed,       8,  6, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, sdi1_ed,       7,  5, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, msp2_ed,       6,  4, &clk_msp02clk);
+static DEFINE_PRCC_CLK(2, sdi4_ed,       4,  2, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(2, pwl_ed,        3,  1, NULL);
-static DEFINE_PRCC_CLK(2, spi1_ed,       2, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi2_ed,       1, -1, NULL);
-static DEFINE_PRCC_CLK(2, i2c3_ed,       0,  0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(2, spi1_ed,       2, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi2_ed,       1, -1, NULL);
+static DEFINE_PRCC_CLK(2, i2c3_ed,       0,  0, &clk_i2cclk);
 
 static DEFINE_PRCC_CLK(2, gpio1_v1,     11, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssitx_v1,     10,  7, NULL);
-static DEFINE_PRCC_CLK(2, ssirx_v1,      9,  6, NULL);
-static DEFINE_PRCC_CLK(2, spi0_v1,       8, -1, NULL);
-static DEFINE_PRCC_CLK(2, sdi3_v1,       7,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, sdi1_v1,       6,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, msp2_v1,       5,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(2, sdi4_v1,       4,  2, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, ssitx_v1,     10,  7, NULL);
+static DEFINE_PRCC_CLK(2, ssirx_v1,      9,  6, NULL);
+static DEFINE_PRCC_CLK(2, spi0_v1,       8, -1, NULL);
+static DEFINE_PRCC_CLK(2, sdi3_v1,       7,  5, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, sdi1_v1,       6,  4, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, msp2_v1,       5,  3, &clk_msp02clk);
+static DEFINE_PRCC_CLK(2, sdi4_v1,       4,  2, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(2, pwl_v1,        3,  1, NULL);
-static DEFINE_PRCC_CLK(2, spi1_v1,       2, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi2_v1,       1, -1, NULL);
-static DEFINE_PRCC_CLK(2, i2c3_v1,       0,  0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(2, spi1_v1,       2, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi2_v1,       1, -1, NULL);
+static DEFINE_PRCC_CLK(2, i2c3_v1,       0,  0, &clk_i2cclk);
 
 /* Peripheral Cluster #3 */
-static DEFINE_PRCC_CLK(3, gpio2,        8, -1, NULL);
-static DEFINE_PRCC_CLK(3, sdi5,         7,  7, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, uart2,        6,  6, &clk_uartclk);
-static DEFINE_PRCC_CLK(3, ske,          5,  5, &clk_32khz);
-static DEFINE_PRCC_CLK(3, sdi2,         4,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, i2c0,         3,  3, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp1_ed,      2,  2, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp0_ed,      1,  1, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp1_v1,      2,  2, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, ssp0_v1,      1,  1, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, fsmc,         0, -1, NULL);
+static DEFINE_PRCC_CLK(3, gpio2,        8, -1, NULL);
+static DEFINE_PRCC_CLK(3, sdi5,         7,  7, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(3, uart2,        6,  6, &clk_uartclk);
+static DEFINE_PRCC_CLK(3, ske,          5,  5, &clk_32khz);
+static DEFINE_PRCC_CLK(3, sdi2,         4,  4, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(3, i2c0,         3,  3, &clk_i2cclk);
+static DEFINE_PRCC_CLK(3, ssp1_ed,      2,  2, &clk_i2cclk);
+static DEFINE_PRCC_CLK(3, ssp0_ed,      1,  1, &clk_i2cclk);
+static DEFINE_PRCC_CLK(3, ssp1_v1,      2,  2, &clk_sspclk);
+static DEFINE_PRCC_CLK(3, ssp0_v1,      1,  1, &clk_sspclk);
+static DEFINE_PRCC_CLK(3, fsmc,         0, -1, NULL);
 
 /* Peripheral Cluster #4 is in the always on domain */
 
 /* Peripheral Cluster #5 */
-static DEFINE_PRCC_CLK(5, gpio3,        1, -1, NULL);
-static DEFINE_PRCC_CLK(5, usb_ed,       0,  0, &clk_i2cclk);
-static DEFINE_PRCC_CLK(5, usb_v1,       0,  0, NULL);
+static DEFINE_PRCC_CLK(5, gpio3,        1, -1, NULL);
+static DEFINE_PRCC_CLK(5, usb_ed,       0,  0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(5, usb_v1,       0,  0, NULL);
 
 /* Peripheral Cluster #6 */
 
 /* MTU ID in data */
 static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
 static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(6, cfgreg_v1,    6,  6, NULL);
-static DEFINE_PRCC_CLK(6, dmc_ed,       6,  6, NULL);
-static DEFINE_PRCC_CLK(6, hash1,        5, -1, NULL);
-static DEFINE_PRCC_CLK(6, unipro_v1,    4,  1, &clk_uniproclk);
-static DEFINE_PRCC_CLK(6, cryp1_ed,     4, -1, NULL);
-static DEFINE_PRCC_CLK(6, pka,          3, -1, NULL);
-static DEFINE_PRCC_CLK(6, hash0,        2, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp0,        1, -1, NULL);
-static DEFINE_PRCC_CLK(6, rng_ed,       0,  0, &clk_i2cclk);
-static DEFINE_PRCC_CLK(6, rng_v1,       0,  0, &clk_rngclk);
+static DEFINE_PRCC_CLK(6, cfgreg_v1,    6,  6, NULL);
+static DEFINE_PRCC_CLK(6, dmc_ed,       6,  6, NULL);
+static DEFINE_PRCC_CLK(6, hash1,        5, -1, NULL);
+static DEFINE_PRCC_CLK(6, unipro_v1,    4,  1, &clk_uniproclk);
+static DEFINE_PRCC_CLK(6, cryp1_ed,     4, -1, NULL);
+static DEFINE_PRCC_CLK(6, pka,          3, -1, NULL);
+static DEFINE_PRCC_CLK(6, hash0,        2, -1, NULL);
+static DEFINE_PRCC_CLK(6, cryp0,        1, -1, NULL);
+static DEFINE_PRCC_CLK(6, rng_ed,       0,  0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(6, rng_v1,       0,  0, &clk_rngclk);
 
 /* Peripheral Cluster #7 */
 
-static DEFINE_PRCC_CLK(7, tzpc0_ed,     4, -1, NULL);
+static DEFINE_PRCC_CLK(7, tzpc0_ed,     4, -1, NULL);
 /* MTU ID in data */
 static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
 static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(7, wdg_ed,       1, -1, NULL);
-static DEFINE_PRCC_CLK(7, cfgreg_ed,    0, -1, NULL);
+static DEFINE_PRCC_CLK(7, wdg_ed,       1, -1, NULL);
+static DEFINE_PRCC_CLK(7, cfgreg_ed,    0, -1, NULL);
 
-static struct clk clk_dummy_apb_pclk;
+static struct clk clk_dummy_apb_pclk = {
+        .name = "apb_pclk",
+};
 
 static struct clk_lookup u8500_common_clks[] = {
         CLK(dummy_apb_pclk, NULL,       "apb_pclk"),
@@ -554,7 +537,7 @@ static struct clk_lookup u8500_ed_clks[] = {
 
 static struct clk_lookup u8500_v1_clks[] = {
         /* Peripheral Cluster #1 */
-        CLK(i2c4,       "nmk-i2c.4",    NULL),
+        CLK(i2c4,       "nmk-i2c.4",    NULL),
         CLK(spi3_v1,    "spi3",         NULL),
         CLK(msp1_v1,    "msp1",         NULL),
 
@@ -599,6 +582,183 @@ static struct clk_lookup u8500_v1_clks[] = {
         CLK(uiccclk,    "uicc",         NULL),
 };
 
+#ifdef CONFIG_DEBUG_FS
+/*
+ *      debugfs support to trace clock tree hierarchy and attributes with
+ *      powerdebug
+ */
+static struct dentry *clk_debugfs_root;
+
+void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
+{
+        while (num--) {
+                /* Check that the clock has not been already registered */
+                if (!(cl->clk->list.prev != cl->clk->list.next))
+                        list_add_tail(&cl->clk->list, &clk_list);
+
+                cl++;
+        }
+}
+
+static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
+                                                  size_t size, loff_t *off)
+{
+        struct clk *clk = file->f_dentry->d_inode->i_private;
+        char cusecount[128];
+        unsigned int len;
+
+        len = sprintf(cusecount, "%u\n", clk->enabled);
+        return simple_read_from_buffer(buf, size, off, cusecount, len);
+}
+
+static ssize_t rate_dbg_read(struct file *file, char __user *buf,
+                                          size_t size, loff_t *off)
+{
+        struct clk *clk = file->f_dentry->d_inode->i_private;
+        char crate[128];
+        unsigned int rate;
+        unsigned int len;
+
+        rate = clk_get_rate(clk);
+        len = sprintf(crate, "%u\n", rate);
+        return simple_read_from_buffer(buf, size, off, crate, len);
+}
+
+static const struct file_operations usecount_fops = {
+        .read = usecount_dbg_read,
+};
+
+static const struct file_operations set_rate_fops = {
+        .read = rate_dbg_read,
+};
+
+static struct dentry *clk_debugfs_register_dir(struct clk *c,
+                                                struct dentry *p_dentry)
+{
+        struct dentry *d, *clk_d, *child, *child_tmp;
+        char s[255];
+        char *p = s;
+
+        if (c->name == NULL)
+                p += sprintf(p, "BUG");
+        else
+                p += sprintf(p, "%s", c->name);
+
+        clk_d = debugfs_create_dir(s, p_dentry);
+        if (!clk_d)
+                return NULL;
+
+        d = debugfs_create_file("usecount", S_IRUGO,
+                                clk_d, c, &usecount_fops);
+        if (!d)
+                goto err_out;
+        d = debugfs_create_file("rate", S_IRUGO,
+                                clk_d, c, &set_rate_fops);
+        if (!d)
+                goto err_out;
+        /*
+         * TODO : not currently available in ux500
+         * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
+         * if (!d)
+         *      goto err_out;
+         */
+
+        return clk_d;
+
+err_out:
+        d = clk_d;
+        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
+                debugfs_remove(child);
+        debugfs_remove(clk_d);
+        return NULL;
+}
+
+static void clk_debugfs_remove_dir(struct dentry *cdentry)
+{
+        struct dentry *d, *child, *child_tmp;
+
+        d = cdentry;
+        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
+                debugfs_remove(child);
+        debugfs_remove(cdentry);
+        return ;
+}
+
+static int clk_debugfs_register_one(struct clk *c)
+{
+        struct clk *pa = c->parent_periph;
+        struct clk *bpa = c->parent_cluster;
+
+        if (!(bpa && !pa)) {
+                c->dent = clk_debugfs_register_dir(c,
+                                pa ? pa->dent : clk_debugfs_root);
+                if (!c->dent)
+                        return -ENOMEM;
+        }
+
+        if (bpa) {
+                c->dent_bus = clk_debugfs_register_dir(c,
+                                bpa->dent_bus ? bpa->dent_bus : bpa->dent);
+                if ((!c->dent_bus) &&  (c->dent)) {
+                        clk_debugfs_remove_dir(c->dent);
+                        c->dent = NULL;
+                        return -ENOMEM;
+                }
+        }
+        return 0;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+        int err;
+        struct clk *pa = c->parent_periph;
+        struct clk *bpa = c->parent_cluster;
+
+        if (pa && (!pa->dent && !pa->dent_bus)) {
+                err = clk_debugfs_register(pa);
+                if (err)
+                        return err;
+        }
+
+        if (bpa && (!bpa->dent && !bpa->dent_bus)) {
+                err = clk_debugfs_register(bpa);
+                if (err)
+                        return err;
+        }
+
+        if ((!c->dent) && (!c->dent_bus)) {
+                err = clk_debugfs_register_one(c);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+        struct clk *c;
+        struct dentry *d;
+        int err;
+
+        d = debugfs_create_dir("clock", NULL);
+        if (!d)
+                return -ENOMEM;
+        clk_debugfs_root = d;
+
+        list_for_each_entry(c, &clk_list, list) {
+                err = clk_debugfs_register(c);
+                if (err)
+                        goto err_out;
+        }
+        return 0;
+err_out:
+        debugfs_remove_recursive(clk_debugfs_root);
+        return err;
+}
+
+late_initcall(clk_debugfs_init);
+#endif /* defined(CONFIG_DEBUG_FS) */
+
 int __init clk_init(void)
 {
         if (cpu_is_u8500ed()) {
@@ -609,7 +769,8 @@ int __init clk_init(void)
                 /* Clock tree for U5500 not implemented yet */
                 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
                 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
-                clk_per6clk.rate = 26000000;
+                clk_uartclk.rate = 36360000;
+                clk_sdmmcclk.rate = 99900000;
         }
 
         clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
@@ -618,5 +779,12 @@ int __init clk_init(void)
         else
                 clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
 
+#ifdef CONFIG_DEBUG_FS
+        clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
+        if (cpu_is_u8500ed())
+                clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
+        else
+                clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
+#endif
         return 0;
 }
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
index a05802501527..074490705229 100644
--- a/arch/arm/mach-ux500/clock.h
+++ b/arch/arm/mach-ux500/clock.h
@@ -90,6 +90,10 @@ struct clk {
 
         struct clk              *parent_cluster;
         struct clk              *parent_periph;
+#if defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;          /* For visible tree hierarchy */
+        struct dentry           *dent_bus;      /* For visible tree hierarchy */
+#endif
 };
 
 #define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg)         \
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index 2f87075e9d6f..af04e0891a78 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -8,15 +8,33 @@
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 
 #include <asm/mach/map.h>
 
+#include <plat/gpio.h>
+
 #include <mach/hardware.h>
 #include <mach/devices.h>
 #include <mach/setup.h>
 #include <mach/irqs.h>
 
+#include "devices-db5500.h"
+
+static struct map_desc u5500_uart_io_desc[] __initdata = {
+        __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K),
+        __IO_DEV_DESC(U5500_UART2_BASE, SZ_4K),
+};
+
 static struct map_desc u5500_io_desc[] __initdata = {
+        __IO_DEV_DESC(U5500_GIC_CPU_BASE, SZ_4K),
+        __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K),
+        __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K),
+        __IO_DEV_DESC(U5500_TWD_BASE, SZ_4K),
+        __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K),
+        __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K),
+        __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K),
+
         __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
         __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K),
         __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K),
@@ -110,21 +128,39 @@ static struct platform_device mbox2_device = {
 };
 
 static struct platform_device *u5500_platform_devs[] __initdata = {
-        &u5500_gpio_devs[0],
-        &u5500_gpio_devs[1],
-        &u5500_gpio_devs[2],
-        &u5500_gpio_devs[3],
-        &u5500_gpio_devs[4],
-        &u5500_gpio_devs[5],
-        &u5500_gpio_devs[6],
-        &u5500_gpio_devs[7],
         &mbox0_device,
         &mbox1_device,
         &mbox2_device,
 };
 
+static resource_size_t __initdata db5500_gpio_base[] = {
+        U5500_GPIOBANK0_BASE,
+        U5500_GPIOBANK1_BASE,
+        U5500_GPIOBANK2_BASE,
+        U5500_GPIOBANK3_BASE,
+        U5500_GPIOBANK4_BASE,
+        U5500_GPIOBANK5_BASE,
+        U5500_GPIOBANK6_BASE,
+        U5500_GPIOBANK7_BASE,
+};
+
+static void __init db5500_add_gpios(void)
+{
+        struct nmk_gpio_platform_data pdata = {
+                /* No custom data yet */
+        };
+
+        dbx500_add_gpios(ARRAY_AND_SIZE(db5500_gpio_base),
+                         IRQ_DB5500_GPIO0, &pdata);
+}
+
 void __init u5500_map_io(void)
 {
+        /*
+         * Map the UARTs early so that the DEBUG_LL stuff continues to work.
+         */
+        iotable_init(u5500_uart_io_desc, ARRAY_SIZE(u5500_uart_io_desc));
+
         ux500_map_io();
 
         iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
@@ -132,7 +168,9 @@ void __init u5500_map_io(void)
 
 void __init u5500_init_devices(void)
 {
-        ux500_init_devices();
+        db5500_add_gpios();
+        db5500_dma_init();
+        db5500_add_rtc();
 
         platform_add_devices(u5500_platform_devs,
                              ARRAY_SIZE(u5500_platform_devs));
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 4acab7544b3c..1748fbc58530 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -22,115 +22,93 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
 
+#include "devices-db8500.h"
+
 static struct platform_device *platform_devs[] __initdata = {
-        &u8500_gpio_devs[0],
-        &u8500_gpio_devs[1],
-        &u8500_gpio_devs[2],
-        &u8500_gpio_devs[3],
-        &u8500_gpio_devs[4],
-        &u8500_gpio_devs[5],
-        &u8500_gpio_devs[6],
-        &u8500_gpio_devs[7],
-        &u8500_gpio_devs[8],
         &u8500_dma40_device,
 };
 
 /* minimum static i/o mapping required to boot U8500 platforms */
+static struct map_desc u8500_uart_io_desc[] __initdata = {
+        __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
+};
+
 static struct map_desc u8500_io_desc[] __initdata = {
+        __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_TWD_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
+
+        __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
+
         __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
-        __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
-        __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M),
 };
 
-static struct map_desc u8500ed_io_desc[] __initdata = {
+static struct map_desc u8500_ed_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
         __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K),
 };
 
-static struct map_desc u8500v1_io_desc[] __initdata = {
+static struct map_desc u8500_v1_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K),
 };
 
-/*
- * Functions to differentiate between later ASICs
- * We look into the end of the ROM to locate the hardcoded ASIC ID.
- * This is only needed to differentiate between minor revisions and
- * process variants of an ASIC, the major revisions are encoded in
- * the cpuid.
- */
-#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOT_ROM_BASE + 0x1FFF4)
-#define U8500_ASIC_ID_LOC_V2    (U8500_BOOT_ROM_BASE + 0x1DBF4)
-#define U8500_ASIC_REV_ED       0x01
-#define U8500_ASIC_REV_V10      0xA0
-#define U8500_ASIC_REV_V11      0xA1
-#define U8500_ASIC_REV_V20      0xB0
-
-/**
- * struct db8500_asic_id - fields of the ASIC ID
- * @process: the manufacturing process, 0x40 is 40 nm
- *  0x00 is "standard"
- * @partnumber: hithereto 0x8500 for DB8500
- * @revision: version code in the series
- * This field definion is not formally defined but makes
- * sense.
- */
-struct db8500_asic_id {
-        u8 process;
-        u16 partnumber;
-        u8 revision;
+static struct map_desc u8500_v2_io_desc[] __initdata = {
+        __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
 };
 
-/* This isn't going to change at runtime */
-static struct db8500_asic_id db8500_id;
-
-static void __init get_db8500_asic_id(void)
+void __init u8500_map_io(void)
 {
-        u32 asicid;
+        /*
+         * Map the UARTs early so that the DEBUG_LL stuff continues to work.
+         */
+        iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
 
-        if (cpu_is_u8500v1() || cpu_is_u8500ed())
-                asicid = readl(__io_address(U8500_ASIC_ID_LOC_ED_V1));
-        else if (cpu_is_u8500v2())
-                asicid = readl(__io_address(U8500_ASIC_ID_LOC_V2));
-        else
-                BUG();
-
-        db8500_id.process = (asicid >> 24);
-        db8500_id.partnumber = (asicid >> 16) & 0xFFFFU;
-        db8500_id.revision = asicid & 0xFFU;
-}
+        ux500_map_io();
 
-bool cpu_is_u8500v10(void)
-{
-        return (db8500_id.revision == U8500_ASIC_REV_V10);
-}
+        iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
 
-bool cpu_is_u8500v11(void)
-{
-        return (db8500_id.revision == U8500_ASIC_REV_V11);
+        if (cpu_is_u8500ed())
+                iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
+        else if (cpu_is_u8500v1())
+                iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
+        else if (cpu_is_u8500v2())
+                iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
 }
 
-bool cpu_is_u8500v20(void)
-{
-        return (db8500_id.revision == U8500_ASIC_REV_V20);
-}
+static resource_size_t __initdata db8500_gpio_base[] = {
+        U8500_GPIOBANK0_BASE,
+        U8500_GPIOBANK1_BASE,
+        U8500_GPIOBANK2_BASE,
+        U8500_GPIOBANK3_BASE,
+        U8500_GPIOBANK4_BASE,
+        U8500_GPIOBANK5_BASE,
+        U8500_GPIOBANK6_BASE,
+        U8500_GPIOBANK7_BASE,
+        U8500_GPIOBANK8_BASE,
+};
 
-void __init u8500_map_io(void)
+static void __init db8500_add_gpios(void)
 {
-        ux500_map_io();
-
-        iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
-
-        if (cpu_is_u8500ed())
-                iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc));
-        else
-                iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc));
+        struct nmk_gpio_platform_data pdata = {
+                /* No custom data yet */
+        };
 
-        /* Read out the ASIC ID as early as we can */
-        get_db8500_asic_id();
+        dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
+                         IRQ_DB8500_GPIO0, &pdata);
 }
 
 /*
@@ -138,26 +116,13 @@ void __init u8500_map_io(void)
  */
 void __init u8500_init_devices(void)
 {
-        /* Display some ASIC boilerplate */
-        pr_info("DB8500: process: %02x, revision ID: 0x%02x\n",
-                db8500_id.process, db8500_id.revision);
-        if (cpu_is_u8500ed())
-                pr_info("DB8500: Early Drop (ED)\n");
-        else if (cpu_is_u8500v10())
-                pr_info("DB8500: version 1.0\n");
-        else if (cpu_is_u8500v11())
-                pr_info("DB8500: version 1.1\n");
-        else if (cpu_is_u8500v20())
-                pr_info("DB8500: version 2.0\n");
-        else
-                pr_warning("ASIC: UNKNOWN SILICON VERSION!\n");
-
-        ux500_init_devices();
-
         if (cpu_is_u8500ed())
                 dma40_u8500ed_fixup();
 
-        /* Register the platform devices */
+        db8500_add_rtc();
+        db8500_add_gpios();
+
+        platform_device_register_simple("cpufreq-u8500", -1, NULL, 0);
         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
         return ;
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 608a1372b172..5a43107c6232 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -6,7 +6,6 @@
  */
 
 #include <linux/platform_device.h>
-#include <linux/amba/bus.h>
 #include <linux/io.h>
 #include <linux/clk.h>
 
@@ -20,54 +19,36 @@
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
+#include <mach/prcmu.h>
 
 #include "clock.h"
 
-static struct map_desc ux500_io_desc[] __initdata = {
-        __IO_DEV_DESC(UX500_UART0_BASE, SZ_4K),
-        __IO_DEV_DESC(UX500_UART2_BASE, SZ_4K),
-
-        __IO_DEV_DESC(UX500_GIC_CPU_BASE, SZ_4K),
-        __IO_DEV_DESC(UX500_GIC_DIST_BASE, SZ_4K),
-        __IO_DEV_DESC(UX500_L2CC_BASE, SZ_4K),
-        __IO_DEV_DESC(UX500_TWD_BASE, SZ_4K),
-        __IO_DEV_DESC(UX500_SCU_BASE, SZ_4K),
-
-        __IO_DEV_DESC(UX500_CLKRST1_BASE, SZ_4K),
-        __IO_DEV_DESC(UX500_CLKRST2_BASE, SZ_4K),
-        __IO_DEV_DESC(UX500_CLKRST3_BASE, SZ_4K),
-        __IO_DEV_DESC(UX500_CLKRST5_BASE, SZ_4K),
-        __IO_DEV_DESC(UX500_CLKRST6_BASE, SZ_4K),
-
-        __IO_DEV_DESC(UX500_MTU0_BASE, SZ_4K),
-        __IO_DEV_DESC(UX500_MTU1_BASE, SZ_4K),
-
-        __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K),
-};
-
-static struct amba_device *ux500_amba_devs[] __initdata = {
-        &ux500_pl031_device,
-};
+#ifdef CONFIG_CACHE_L2X0
+static void __iomem *l2x0_base;
+#endif
 
-void __init ux500_map_io(void)
+void __init ux500_init_irq(void)
 {
-        iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc));
-}
+        void __iomem *dist_base;
+        void __iomem *cpu_base;
 
-void __init ux500_init_devices(void)
-{
-        amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs));
-}
+        if (cpu_is_u5500()) {
+                dist_base = __io_address(U5500_GIC_DIST_BASE);
+                cpu_base = __io_address(U5500_GIC_CPU_BASE);
+        } else if (cpu_is_u8500()) {
+                dist_base = __io_address(U8500_GIC_DIST_BASE);
+                cpu_base = __io_address(U8500_GIC_CPU_BASE);
+        } else
+                ux500_unknown_soc();
 
-void __init ux500_init_irq(void)
-{
-        gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
-        gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
+        gic_init(0, 29, dist_base, cpu_base);
 
         /*
          * Init clocks here so that they are available for system timer
          * initialization.
          */
+        if (cpu_is_u8500())
+                prcmu_early_init();
         clk_init();
 }
 
@@ -81,7 +62,8 @@ static inline void ux500_cache_wait(void __iomem *reg, unsigned long mask)
 
 static inline void ux500_cache_sync(void)
 {
-        void __iomem *base = __io_address(UX500_L2CC_BASE);
+        void __iomem *base = l2x0_base;
+
         writel_relaxed(0, base + L2X0_CACHE_SYNC);
         ux500_cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
@@ -103,20 +85,23 @@ static void ux500_l2x0_disable(void)
  */
 static void ux500_l2x0_inv_all(void)
 {
-        void __iomem *l2x0_base = __io_address(UX500_L2CC_BASE);
+        void __iomem *base = l2x0_base;
         uint32_t l2x0_way_mask = (1<<16) - 1;   /* Bitmask of active ways */
 
         /* invalidate all ways */
-        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
-        ux500_cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
+        writel_relaxed(l2x0_way_mask, base + L2X0_INV_WAY);
+        ux500_cache_wait(base + L2X0_INV_WAY, l2x0_way_mask);
         ux500_cache_sync();
 }
 
 static int ux500_l2x0_init(void)
 {
-        void __iomem *l2x0_base;
-
-        l2x0_base = __io_address(UX500_L2CC_BASE);
+        if (cpu_is_u5500())
+                l2x0_base = __io_address(U5500_L2CC_BASE);
+        else if (cpu_is_u8500())
+                l2x0_base = __io_address(U8500_L2CC_BASE);
+        else
+                ux500_unknown_soc();
 
         /* 64KB way size, 8 way associativity, force WA */
         l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
@@ -134,13 +119,21 @@ static void __init ux500_timer_init(void)
 {
 #ifdef CONFIG_LOCAL_TIMERS
         /* Setup the local timer base */
-        twd_base = __io_address(UX500_TWD_BASE);
+        if (cpu_is_u5500())
+                twd_base = __io_address(U5500_TWD_BASE);
+        else if (cpu_is_u8500())
+                twd_base = __io_address(U8500_TWD_BASE);
+        else
+                ux500_unknown_soc();
 #endif
-        /* Setup the MTU base */
-        if (cpu_is_u8500ed())
+        if (cpu_is_u5500())
+                mtu_base = __io_address(U5500_MTU0_BASE);
+        else if (cpu_is_u8500ed())
                 mtu_base = __io_address(U8500_MTU0_BASE_ED);
+        else if (cpu_is_u8500())
+                mtu_base = __io_address(U8500_MTU0_BASE);
         else
-                mtu_base = __io_address(UX500_MTU0_BASE);
+                ux500_unknown_soc();
 
         nmdk_timer_init();
 }
diff --git a/arch/arm/mach-ux500/cpufreq.c b/arch/arm/mach-ux500/cpufreq.c
new file mode 100644
index 000000000000..5c5b747f134d
--- /dev/null
+++ b/arch/arm/mach-ux500/cpufreq.c
@@ -0,0 +1,211 @@
+/*
+ * CPU frequency scaling for u8500
+ * Inspired by linux/arch/arm/mach-davinci/cpufreq.c
+ *
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ * Author: Martin Persson <martin.persson@stericsson.com>
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+
+#include <mach/hardware.h>
+#include <mach/prcmu.h>
+#include <mach/prcmu-defs.h>
+
+#define DRIVER_NAME "cpufreq-u8500"
+#define CPUFREQ_NAME "u8500"
+
+static struct device *dev;
+
+static struct cpufreq_frequency_table freq_table[] = {
+        [0] = {
+                .index = 0,
+                .frequency = 200000,
+        },
+        [1] = {
+                .index = 1,
+                .frequency = 300000,
+        },
+        [2] = {
+                .index = 2,
+                .frequency = 600000,
+        },
+        [3] = {
+                /* Used for CPU_OPP_MAX, if available */
+                .index = 3,
+                .frequency = CPUFREQ_TABLE_END,
+        },
+        [4] = {
+                .index = 4,
+                .frequency = CPUFREQ_TABLE_END,
+        },
+};
+
+static enum prcmu_cpu_opp index2opp[] = {
+        CPU_OPP_EXT_CLK,
+        CPU_OPP_50,
+        CPU_OPP_100,
+        CPU_OPP_MAX
+};
+
+static int u8500_cpufreq_verify_speed(struct cpufreq_policy *policy)
+{
+        return cpufreq_frequency_table_verify(policy, freq_table);
+}
+
+static int u8500_cpufreq_target(struct cpufreq_policy *policy,
+                                unsigned int target_freq,
+                                unsigned int relation)
+{
+        struct cpufreq_freqs freqs;
+        unsigned int index;
+        int ret = 0;
+
+        /*
+         * Ensure desired rate is within allowed range.  Some govenors
+         * (ondemand) will just pass target_freq=0 to get the minimum.
+         */
+        if (target_freq < policy->cpuinfo.min_freq)
+                target_freq = policy->cpuinfo.min_freq;
+        if (target_freq > policy->cpuinfo.max_freq)
+                target_freq = policy->cpuinfo.max_freq;
+
+        ret = cpufreq_frequency_table_target(policy, freq_table,
+                                             target_freq, relation, &index);
+        if (ret < 0) {
+                dev_err(dev, "Could not look up next frequency\n");
+                return ret;
+        }
+
+        freqs.old = policy->cur;
+        freqs.new = freq_table[index].frequency;
+        freqs.cpu = policy->cpu;
+
+        if (freqs.old == freqs.new) {
+                dev_dbg(dev, "Current and target frequencies are equal\n");
+                return 0;
+        }
+
+        dev_dbg(dev, "transition: %u --> %u\n", freqs.old, freqs.new);
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+        ret = prcmu_set_cpu_opp(index2opp[index]);
+        if (ret < 0) {
+                dev_err(dev, "Failed to set OPP level\n");
+                return ret;
+        }
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        return ret;
+}
+
+static unsigned int u8500_cpufreq_getspeed(unsigned int cpu)
+{
+        int i;
+
+        for (i = 0; prcmu_get_cpu_opp() != index2opp[i]; i++)
+                ;
+        return freq_table[i].frequency;
+}
+
+static int __cpuinit u8500_cpu_init(struct cpufreq_policy *policy)
+{
+        int res;
+
+        BUILD_BUG_ON(ARRAY_SIZE(index2opp) + 1 != ARRAY_SIZE(freq_table));
+
+        if (cpu_is_u8500v2()) {
+                freq_table[1].frequency = 400000;
+                freq_table[2].frequency = 800000;
+                if (prcmu_has_arm_maxopp())
+                        freq_table[3].frequency = 1000000;
+        }
+
+        /* get policy fields based on the table */
+        res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+        if (!res)
+                cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+        else {
+                dev_err(dev, "u8500-cpufreq : Failed to read policy table\n");
+                return res;
+        }
+
+        policy->min = policy->cpuinfo.min_freq;
+        policy->max = policy->cpuinfo.max_freq;
+        policy->cur = u8500_cpufreq_getspeed(policy->cpu);
+        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+
+        /*
+         * FIXME : Need to take time measurement across the target()
+         *         function with no/some/all drivers in the notification
+         *         list.
+         */
+        policy->cpuinfo.transition_latency = 200 * 1000; /* in ns */
+
+        /* policy sharing between dual CPUs */
+        cpumask_copy(policy->cpus, &cpu_present_map);
+
+        policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
+
+        return res;
+}
+
+static struct freq_attr *u8500_cpufreq_attr[] = {
+        &cpufreq_freq_attr_scaling_available_freqs,
+        NULL,
+};
+static int u8500_cpu_exit(struct cpufreq_policy *policy)
+{
+        cpufreq_frequency_table_put_attr(policy->cpu);
+        return 0;
+}
+
+static struct cpufreq_driver u8500_driver = {
+        .owner = THIS_MODULE,
+        .flags = CPUFREQ_STICKY,
+        .verify = u8500_cpufreq_verify_speed,
+        .target = u8500_cpufreq_target,
+        .get = u8500_cpufreq_getspeed,
+        .init = u8500_cpu_init,
+        .exit = u8500_cpu_exit,
+        .name = CPUFREQ_NAME,
+        .attr = u8500_cpufreq_attr,
+};
+
+static int __init u8500_cpufreq_probe(struct platform_device *pdev)
+{
+        dev = &pdev->dev;
+        return cpufreq_register_driver(&u8500_driver);
+}
+
+static int __exit u8500_cpufreq_remove(struct platform_device *pdev)
+{
+        return cpufreq_unregister_driver(&u8500_driver);
+}
+
+static struct platform_driver u8500_cpufreq_driver = {
+        .driver = {
+                .name    = DRIVER_NAME,
+                .owner   = THIS_MODULE,
+        },
+        .remove = __exit_p(u8500_cpufreq_remove),
+};
+
+static int __init u8500_cpufreq_init(void)
+{
+        return platform_driver_probe(&u8500_cpufreq_driver,
+                                     &u8500_cpufreq_probe);
+}
+
+device_initcall(u8500_cpufreq_init);
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
new file mode 100644
index 000000000000..fe69f5fac1bb
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+
+#include <plat/gpio.h>
+
+#include <mach/hardware.h>
+
+#include "devices-common.h"
+
+struct amba_device *
+dbx500_add_amba_device(const char *name, resource_size_t base,
+                       int irq, void *pdata, unsigned int periphid)
+{
+        struct amba_device *dev;
+        int ret;
+
+        dev = kzalloc(sizeof *dev, GFP_KERNEL);
+        if (!dev)
+                return ERR_PTR(-ENOMEM);
+
+        dev->dev.init_name = name;
+
+        dev->res.start = base;
+        dev->res.end = base + SZ_4K - 1;
+        dev->res.flags = IORESOURCE_MEM;
+
+        dev->dma_mask = DMA_BIT_MASK(32);
+        dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+
+        dev->irq[0] = irq;
+        dev->irq[1] = NO_IRQ;
+
+        dev->periphid = periphid;
+
+        dev->dev.platform_data = pdata;
+
+        ret = amba_device_register(dev, &iomem_resource);
+        if (ret) {
+                kfree(dev);
+                return ERR_PTR(ret);
+        }
+
+        return dev;
+}
+
+static struct platform_device *
+dbx500_add_platform_device(const char *name, int id, void *pdata,
+                           struct resource *res, int resnum)
+{
+        struct platform_device *dev;
+        int ret;
+
+        dev = platform_device_alloc(name, id);
+        if (!dev)
+                return ERR_PTR(-ENOMEM);
+
+        dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+        dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
+
+        ret = platform_device_add_resources(dev, res, resnum);
+        if (ret)
+                goto out_free;
+
+        dev->dev.platform_data = pdata;
+
+        ret = platform_device_add(dev);
+        if (ret)
+                goto out_free;
+
+        return dev;
+
+out_free:
+        platform_device_put(dev);
+        return ERR_PTR(ret);
+}
+
+struct platform_device *
+dbx500_add_platform_device_4k1irq(const char *name, int id,
+                                  resource_size_t base,
+                                  int irq, void *pdata)
+{
+        struct resource resources[] = {
+                [0] = {
+                        .start  = base,
+                        .end    = base + SZ_4K - 1,
+                        .flags  = IORESOURCE_MEM,
+                },
+                [1] = {
+                        .start  = irq,
+                        .end    = irq,
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        return dbx500_add_platform_device(name, id, pdata, resources,
+                                          ARRAY_SIZE(resources));
+}
+
+static struct platform_device *
+dbx500_add_gpio(int id, resource_size_t addr, int irq,
+                struct nmk_gpio_platform_data *pdata)
+{
+        struct resource resources[] = {
+                {
+                        .start  = addr,
+                        .end    = addr + 127,
+                        .flags  = IORESOURCE_MEM,
+                },
+                {
+                        .start  = irq,
+                        .end    = irq,
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        return platform_device_register_resndata(NULL, "gpio", id,
+                                resources, ARRAY_SIZE(resources),
+                                pdata, sizeof(*pdata));
+}
+
+void dbx500_add_gpios(resource_size_t *base, int num, int irq,
+                      struct nmk_gpio_platform_data *pdata)
+{
+        int first = 0;
+        int i;
+
+        for (i = 0; i < num; i++, first += 32, irq++) {
+                pdata->first_gpio = first;
+                pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
+
+                dbx500_add_gpio(i, base[i], irq, pdata);
+        }
+}
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
new file mode 100644
index 000000000000..cbadc117d2db
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#ifndef __DEVICES_COMMON_H
+#define __DEVICES_COMMON_H
+
+extern struct amba_device *
+dbx500_add_amba_device(const char *name, resource_size_t base,
+                       int irq, void *pdata, unsigned int periphid);
+
+extern struct platform_device *
+dbx500_add_platform_device_4k1irq(const char *name, int id,
+                                  resource_size_t base,
+                                  int irq, void *pdata);
+
+struct spi_master_cntlr;
+
+static inline struct amba_device *
+dbx500_add_msp_spi(const char *name, resource_size_t base, int irq,
+                   struct spi_master_cntlr *pdata)
+{
+        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+}
+
+static inline struct amba_device *
+dbx500_add_spi(const char *name, resource_size_t base, int irq,
+                                   struct spi_master_cntlr *pdata)
+{
+        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+}
+
+struct mmci_platform_data;
+
+static inline struct amba_device *
+dbx500_add_sdi(const char *name, resource_size_t base, int irq,
+               struct mmci_platform_data *pdata)
+{
+        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+}
+
+static inline struct amba_device *
+dbx500_add_uart(const char *name, resource_size_t base, int irq)
+{
+        return dbx500_add_amba_device(name, base, irq, NULL, 0);
+}
+
+struct nmk_i2c_controller;
+
+static inline struct platform_device *
+dbx500_add_i2c(int id, resource_size_t base, int irq,
+               struct nmk_i2c_controller *pdata)
+{
+        return dbx500_add_platform_device_4k1irq("nmk-i2c", id, base, irq,
+                                                 pdata);
+}
+
+struct msp_i2s_platform_data;
+
+static inline struct platform_device *
+dbx500_add_msp_i2s(int id, resource_size_t base, int irq,
+                   struct msp_i2s_platform_data *pdata)
+{
+        return dbx500_add_platform_device_4k1irq("MSP_I2S", id, base, irq,
+                                                 pdata);
+}
+
+static inline struct amba_device *
+dbx500_add_rtc(resource_size_t base, int irq)
+{
+        return dbx500_add_amba_device("rtc-pl031", base, irq, NULL, 0);
+}
+
+struct nmk_gpio_platform_data;
+
+void dbx500_add_gpios(resource_size_t *base, int num, int irq,
+                      struct nmk_gpio_platform_data *pdata);
+
+#endif
diff --git a/arch/arm/mach-ux500/devices-db5500.c b/arch/arm/mach-ux500/devices-db5500.c
deleted file mode 100644
index 33e5b56bebb6..000000000000
--- a/arch/arm/mach-ux500/devices-db5500.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-
-#include <mach/hardware.h>
-#include <mach/devices.h>
-
-static struct nmk_gpio_platform_data u5500_gpio_data[] = {
-        GPIO_DATA("GPIO-0-31", 0),
-        GPIO_DATA("GPIO-32-63", 32), /* 36..63 not routed to pin */
-        GPIO_DATA("GPIO-64-95", 64), /* 83..95 not routed to pin */
-        GPIO_DATA("GPIO-96-127", 96), /* 102..127 not routed to pin */
-        GPIO_DATA("GPIO-128-159", 128), /* 149..159 not routed to pin */
-        GPIO_DATA("GPIO-160-191", 160),
-        GPIO_DATA("GPIO-192-223", 192),
-        GPIO_DATA("GPIO-224-255", 224), /* 228..255 not routed to pin */
-};
-
-static struct resource u5500_gpio_resources[] = {
-        GPIO_RESOURCE(0),
-        GPIO_RESOURCE(1),
-        GPIO_RESOURCE(2),
-        GPIO_RESOURCE(3),
-        GPIO_RESOURCE(4),
-        GPIO_RESOURCE(5),
-        GPIO_RESOURCE(6),
-        GPIO_RESOURCE(7),
-};
-
-struct platform_device u5500_gpio_devs[] = {
-        GPIO_DEVICE(0),
-        GPIO_DEVICE(1),
-        GPIO_DEVICE(2),
-        GPIO_DEVICE(3),
-        GPIO_DEVICE(4),
-        GPIO_DEVICE(5),
-        GPIO_DEVICE(6),
-        GPIO_DEVICE(7),
-};
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
new file mode 100644
index 000000000000..c8d7901c1f2d
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#ifndef __DEVICES_DB5500_H
+#define __DEVICES_DB5500_H
+
+#include "devices-common.h"
+
+#define db5500_add_i2c1(pdata) \
+        dbx500_add_i2c(1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata)
+#define db5500_add_i2c2(pdata) \
+        dbx500_add_i2c(2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata)
+#define db5500_add_i2c3(pdata) \
+        dbx500_add_i2c(3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata)
+
+#define db5500_add_msp0_i2s(pdata) \
+        dbx500_add_msp_i2s(0, U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata)
+#define db5500_add_msp1_i2s(pdata) \
+        dbx500_add_msp_i2s(1, U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata)
+#define db5500_add_msp2_i2s(pdata) \
+        dbx500_add_msp_i2s(2, U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata)
+
+#define db5500_add_msp0_spi(pdata) \
+        dbx500_add_msp_spi("msp0", U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata)
+#define db5500_add_msp1_spi(pdata) \
+        dbx500_add_msp_spi("msp1", U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata)
+#define db5500_add_msp2_spi(pdata) \
+        dbx500_add_msp_spi("msp2", U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata)
+
+#define db5500_add_rtc() \
+        dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC);
+
+#define db5500_add_sdi0(pdata) \
+        dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata)
+#define db5500_add_sdi1(pdata) \
+        dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata)
+#define db5500_add_sdi2(pdata) \
+        dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata)
+#define db5500_add_sdi3(pdata) \
+        dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata)
+#define db5500_add_sdi4(pdata) \
+        dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata)
+
+#define db5500_add_spi0(pdata) \
+        dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata)
+#define db5500_add_spi1(pdata) \
+        dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata)
+#define db5500_add_spi2(pdata) \
+        dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata)
+#define db5500_add_spi3(pdata) \
+        dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata)
+
+#define db5500_add_uart0() \
+        dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0)
+#define db5500_add_uart1() \
+        dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1)
+#define db5500_add_uart2() \
+        dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2)
+#define db5500_add_uart3() \
+        dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3)
+
+#endif
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 4a94be3304b9..23c695d54977 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -19,173 +19,6 @@
 
 #include "ste-dma40-db8500.h"
 
-static struct nmk_gpio_platform_data u8500_gpio_data[] = {
-        GPIO_DATA("GPIO-0-31", 0),
-        GPIO_DATA("GPIO-32-63", 32), /* 37..63 not routed to pin */
-        GPIO_DATA("GPIO-64-95", 64),
-        GPIO_DATA("GPIO-96-127", 96), /* 98..127 not routed to pin */
-        GPIO_DATA("GPIO-128-159", 128),
-        GPIO_DATA("GPIO-160-191", 160), /* 172..191 not routed to pin */
-        GPIO_DATA("GPIO-192-223", 192),
-        GPIO_DATA("GPIO-224-255", 224), /* 231..255 not routed to pin */
-        GPIO_DATA("GPIO-256-288", 256), /* 268..288 not routed to pin */
-};
-
-static struct resource u8500_gpio_resources[] = {
-        GPIO_RESOURCE(0),
-        GPIO_RESOURCE(1),
-        GPIO_RESOURCE(2),
-        GPIO_RESOURCE(3),
-        GPIO_RESOURCE(4),
-        GPIO_RESOURCE(5),
-        GPIO_RESOURCE(6),
-        GPIO_RESOURCE(7),
-        GPIO_RESOURCE(8),
-};
-
-struct platform_device u8500_gpio_devs[] = {
-        GPIO_DEVICE(0),
-        GPIO_DEVICE(1),
-        GPIO_DEVICE(2),
-        GPIO_DEVICE(3),
-        GPIO_DEVICE(4),
-        GPIO_DEVICE(5),
-        GPIO_DEVICE(6),
-        GPIO_DEVICE(7),
-        GPIO_DEVICE(8),
-};
-
-struct amba_device u8500_ssp0_device = {
-        .dev = {
-                .coherent_dma_mask = ~0,
-                .init_name = "ssp0",
-        },
-        .res = {
-                .start = U8500_SSP0_BASE,
-                .end   = U8500_SSP0_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_DB8500_SSP0, NO_IRQ },
-        /* ST-Ericsson modified id */
-        .periphid = SSP_PER_ID,
-};
-
-static struct resource u8500_i2c0_resources[] = {
-        [0] = {
-                .start  = U8500_I2C0_BASE,
-                .end    = U8500_I2C0_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_DB8500_I2C0,
-                .end    = IRQ_DB8500_I2C0,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device u8500_i2c0_device = {
-        .name           = "nmk-i2c",
-        .id             = 0,
-        .resource       = u8500_i2c0_resources,
-        .num_resources  = ARRAY_SIZE(u8500_i2c0_resources),
-};
-
-static struct resource u8500_i2c4_resources[] = {
-        [0] = {
-                .start  = U8500_I2C4_BASE,
-                .end    = U8500_I2C4_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_DB8500_I2C4,
-                .end    = IRQ_DB8500_I2C4,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device u8500_i2c4_device = {
-        .name           = "nmk-i2c",
-        .id             = 4,
-        .resource       = u8500_i2c4_resources,
-        .num_resources  = ARRAY_SIZE(u8500_i2c4_resources),
-};
-
-/*
- * SD/MMC
- */
-
-struct amba_device u8500_sdi0_device = {
-        .dev            = {
-                .init_name = "sdi0",
-        },
-        .res            = {
-                .start  = U8500_SDI0_BASE,
-                .end    = U8500_SDI0_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC0, NO_IRQ},
-};
-
-struct amba_device u8500_sdi1_device = {
-        .dev            = {
-                .init_name = "sdi1",
-        },
-        .res            = {
-                .start  = U8500_SDI1_BASE,
-                .end    = U8500_SDI1_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC1, NO_IRQ},
-};
-
-struct amba_device u8500_sdi2_device = {
-        .dev            = {
-                .init_name = "sdi2",
-        },
-        .res            = {
-                .start  = U8500_SDI2_BASE,
-                .end    = U8500_SDI2_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC2, NO_IRQ},
-};
-
-struct amba_device u8500_sdi3_device = {
-        .dev            = {
-                .init_name = "sdi3",
-        },
-        .res            = {
-                .start  = U8500_SDI3_BASE,
-                .end    = U8500_SDI3_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC3, NO_IRQ},
-};
-
-struct amba_device u8500_sdi4_device = {
-        .dev            = {
-                .init_name = "sdi4",
-        },
-        .res            = {
-                .start  = U8500_SDI4_BASE,
-                .end    = U8500_SDI4_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC4, NO_IRQ},
-};
-
-struct amba_device u8500_sdi5_device = {
-        .dev            = {
-                .init_name = "sdi5",
-        },
-        .res            = {
-                .start  = U8500_SDI5_BASE,
-                .end    = U8500_SDI5_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC5, NO_IRQ},
-};
-
 static struct resource dma40_resources[] = {
         [0] = {
                 .start = U8500_DMA_BASE,
@@ -295,7 +128,7 @@ struct resource keypad_resources[] = {
         },
 };
 
-struct platform_device ux500_ske_keypad_device = {
+struct platform_device u8500_ske_keypad_device = {
         .name = "nmk-ske-keypad",
         .id = -1,
         .num_resources = ARRAY_SIZE(keypad_resources),
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
new file mode 100644
index 000000000000..3a770c756979
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#ifndef __DEVICES_DB8500_H
+#define __DEVICES_DB8500_H
+
+#include "devices-common.h"
+
+struct ske_keypad_platform_data;
+struct pl022_ssp_controller;
+
+static inline struct platform_device *
+db8500_add_ske_keypad(struct ske_keypad_platform_data *pdata)
+{
+        return dbx500_add_platform_device_4k1irq("nmk-ske-keypad", -1,
+                                                 U8500_SKE_BASE,
+                                                 IRQ_DB8500_KB, pdata);
+}
+
+static inline struct amba_device *
+db8500_add_ssp(const char *name, resource_size_t base, int irq,
+               struct pl022_ssp_controller *pdata)
+{
+        return dbx500_add_amba_device(name, base, irq, pdata, SSP_PER_ID);
+}
+
+
+#define db8500_add_i2c0(pdata) \
+        dbx500_add_i2c(0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
+#define db8500_add_i2c1(pdata) \
+        dbx500_add_i2c(1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata)
+#define db8500_add_i2c2(pdata) \
+        dbx500_add_i2c(2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata)
+#define db8500_add_i2c3(pdata) \
+        dbx500_add_i2c(3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata)
+#define db8500_add_i2c4(pdata) \
+        dbx500_add_i2c(4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
+
+#define db8500_add_msp0_i2s(pdata) \
+        dbx500_add_msp_i2s(0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
+#define db8500_add_msp1_i2s(pdata) \
+        dbx500_add_msp_i2s(1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
+#define db8500_add_msp2_i2s(pdata) \
+        dbx500_add_msp_i2s(2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
+#define db8500_add_msp3_i2s(pdata) \
+        dbx500_add_msp_i2s(3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
+
+#define db8500_add_msp0_spi(pdata) \
+        dbx500_add_msp_spi("msp0", U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
+#define db8500_add_msp1_spi(pdata) \
+        dbx500_add_msp_spi("msp1", U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
+#define db8500_add_msp2_spi(pdata) \
+        dbx500_add_msp_spi("msp2", U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
+#define db8500_add_msp3_spi(pdata) \
+        dbx500_add_msp_spi("msp3", U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
+
+#define db8500_add_rtc() \
+        dbx500_add_rtc(U8500_RTC_BASE, IRQ_DB8500_RTC);
+
+#define db8500_add_sdi0(pdata) \
+        dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata)
+#define db8500_add_sdi1(pdata) \
+        dbx500_add_sdi("sdi1", U8500_SDI1_BASE, IRQ_DB8500_SDMMC1, pdata)
+#define db8500_add_sdi2(pdata) \
+        dbx500_add_sdi("sdi2", U8500_SDI2_BASE, IRQ_DB8500_SDMMC2, pdata)
+#define db8500_add_sdi3(pdata) \
+        dbx500_add_sdi("sdi3", U8500_SDI3_BASE, IRQ_DB8500_SDMMC3, pdata)
+#define db8500_add_sdi4(pdata) \
+        dbx500_add_sdi("sdi4", U8500_SDI4_BASE, IRQ_DB8500_SDMMC4, pdata)
+#define db8500_add_sdi5(pdata) \
+        dbx500_add_sdi("sdi5", U8500_SDI5_BASE, IRQ_DB8500_SDMMC5, pdata)
+
+#define db8500_add_ssp0(pdata) \
+        db8500_add_ssp("ssp0", U8500_SSP0_BASE, IRQ_DB8500_SSP0, pdata)
+#define db8500_add_ssp1(pdata) \
+        db8500_add_ssp("ssp1", U8500_SSP1_BASE, IRQ_DB8500_SSP1, pdata)
+
+#define db8500_add_spi0(pdata) \
+        dbx500_add_spi("spi0", U8500_SPI0_BASE, IRQ_DB8500_SPI0, pdata)
+#define db8500_add_spi1(pdata) \
+        dbx500_add_spi("spi1", U8500_SPI1_BASE, IRQ_DB8500_SPI1, pdata)
+#define db8500_add_spi2(pdata) \
+        dbx500_add_spi("spi2", U8500_SPI2_BASE, IRQ_DB8500_SPI2, pdata)
+#define db8500_add_spi3(pdata) \
+        dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata)
+
+#define db8500_add_uart0() \
+        dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0)
+#define db8500_add_uart1() \
+        dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1)
+#define db8500_add_uart2() \
+        dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2)
+
+#endif
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c
index 8a268893cb7f..ea0a2f92ca70 100644
--- a/arch/arm/mach-ux500/devices.c
+++ b/arch/arm/mach-ux500/devices.c
@@ -14,69 +14,6 @@
 #include <mach/hardware.h>
 #include <mach/setup.h>
 
-#define __MEM_4K_RESOURCE(x) \
-        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
-
-struct amba_device ux500_pl031_device = {
-        .dev = {
-                .init_name = "pl031",
-        },
-        .res = {
-                .start  = UX500_RTC_BASE,
-                .end    = UX500_RTC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_RTC_RTT, NO_IRQ},
-};
-
-struct amba_device ux500_uart0_device = {
-        .dev = { .init_name = "uart0" },
-        __MEM_4K_RESOURCE(UX500_UART0_BASE),
-        .irq = {IRQ_UART0, NO_IRQ},
-};
-
-struct amba_device ux500_uart1_device = {
-        .dev = { .init_name = "uart1" },
-        __MEM_4K_RESOURCE(UX500_UART1_BASE),
-        .irq = {IRQ_UART1, NO_IRQ},
-};
-
-struct amba_device ux500_uart2_device = {
-        .dev = { .init_name = "uart2" },
-        __MEM_4K_RESOURCE(UX500_UART2_BASE),
-        .irq = {IRQ_UART2, NO_IRQ},
-};
-
-#define UX500_I2C_RESOURCES(id, size)                           \
-static struct resource ux500_i2c##id##_resources[] = {          \
-        [0] = {                                                 \
-                .start  = UX500_I2C##id##_BASE,                 \
-                .end    = UX500_I2C##id##_BASE + size - 1,      \
-                .flags  = IORESOURCE_MEM,                       \
-        },                                                      \
-        [1] = {                                                 \
-                .start  = IRQ_I2C##id,                          \
-                .end    = IRQ_I2C##id,                          \
-                .flags  = IORESOURCE_IRQ                        \
-        }                                                       \
-}
-
-UX500_I2C_RESOURCES(1, SZ_4K);
-UX500_I2C_RESOURCES(2, SZ_4K);
-UX500_I2C_RESOURCES(3, SZ_4K);
-
-#define UX500_I2C_PDEVICE(cid)                                  \
-struct platform_device ux500_i2c##cid##_device = {              \
-        .name           = "nmk-i2c",                            \
-        .id             = cid,                                  \
-        .num_resources  = 2,                                    \
-        .resource       = ux500_i2c##cid##_resources,           \
-}
-
-UX500_I2C_PDEVICE(1);
-UX500_I2C_PDEVICE(2);
-UX500_I2C_PDEVICE(3);
-
 void __init amba_add_devices(struct amba_device *devs[], int num)
 {
         int i;
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
new file mode 100644
index 000000000000..32a061f8a95b
--- /dev/null
+++ b/arch/arm/mach-ux500/dma-db5500.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
+ * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <plat/ste_dma40.h>
+#include <mach/setup.h>
+#include <mach/hardware.h>
+
+#include "ste-dma40-db5500.h"
+
+static struct resource dma40_resources[] = {
+        [0] = {
+                .start = U5500_DMA_BASE,
+                .end   = U5500_DMA_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+                .name  = "base",
+        },
+        [1] = {
+                .start = U5500_DMA_LCPA_BASE,
+                .end   = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
+                .flags = IORESOURCE_MEM,
+                .name  = "lcpa",
+        },
+        [2] = {
+                .start = IRQ_DB5500_DMA,
+                .end   = IRQ_DB5500_DMA,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+/* Default configuration for physical memcpy */
+static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
+        .mode = STEDMA40_MODE_PHYSICAL,
+        .dir = STEDMA40_MEM_TO_MEM,
+
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .src_info.psize = STEDMA40_PSIZE_PHY_1,
+        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.psize = STEDMA40_PSIZE_PHY_1,
+        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+};
+
+/* Default configuration for logical memcpy */
+static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
+        .dir = STEDMA40_MEM_TO_MEM,
+
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .src_info.psize = STEDMA40_PSIZE_LOG_1,
+        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
+        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+};
+
+/*
+ * Mapping between soruce event lines and physical device address This was
+ * created assuming that the event line is tied to a device and therefore the
+ * address is constant, however this is not true for at least USB, and the
+ * values are just placeholders for USB.  This table is preserved and used for
+ * now.
+ */
+static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = {
+        [DB5500_DMA_DEV24_SDMMC0_RX] = -1,
+};
+
+/* Mapping between destination event lines and physical device address */
+static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = {
+        [DB5500_DMA_DEV24_SDMMC0_TX] = -1,
+};
+
+static int dma40_memcpy_event[] = {
+        DB5500_DMA_MEMCPY_TX_1,
+        DB5500_DMA_MEMCPY_TX_2,
+        DB5500_DMA_MEMCPY_TX_3,
+        DB5500_DMA_MEMCPY_TX_4,
+        DB5500_DMA_MEMCPY_TX_5,
+};
+
+static struct stedma40_platform_data dma40_plat_data = {
+        .dev_len                = ARRAY_SIZE(dma40_rx_map),
+        .dev_rx                 = dma40_rx_map,
+        .dev_tx                 = dma40_tx_map,
+        .memcpy                 = dma40_memcpy_event,
+        .memcpy_len             = ARRAY_SIZE(dma40_memcpy_event),
+        .memcpy_conf_phy        = &dma40_memcpy_conf_phy,
+        .memcpy_conf_log        = &dma40_memcpy_conf_log,
+        .disabled_channels      = {-1},
+};
+
+static struct platform_device dma40_device = {
+        .dev = {
+                .platform_data = &dma40_plat_data,
+        },
+        .name           = "dma40",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dma40_resources),
+        .resource       = dma40_resources
+};
+
+void __init db5500_dma_init(void)
+{
+        int ret;
+
+        ret = platform_device_register(&dma40_device);
+        if (ret)
+                dev_err(&dma40_device.dev, "unable to register device: %d\n", ret);
+
+}
diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S
index a6be2cdf2b2f..64fa451edcfd 100644
--- a/arch/arm/mach-ux500/headsmp.S
+++ b/arch/arm/mach-ux500/headsmp.S
@@ -23,7 +23,6 @@ ENTRY(u8500_secondary_startup)
         ldmia   r4, {r5, r6}
         sub     r4, r4, r5
         add     r6, r6, r4
-        dsb
 pen:    ldr     r7, [r6]
         cmp     r7, r0
         bne     pen
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
index b782a03024be..dd8037ebccf8 100644
--- a/arch/arm/mach-ux500/hotplug.c
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -11,14 +11,11 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
-#include <linux/completion.h>
 
 #include <asm/cacheflush.h>
 
 extern volatile int pen_release;
 
-static DECLARE_COMPLETION(cpu_killed);
-
 static inline void platform_do_lowpower(unsigned int cpu)
 {
         flush_cache_all();
@@ -38,7 +35,7 @@ static inline void platform_do_lowpower(unsigned int cpu)
 
 int platform_cpu_kill(unsigned int cpu)
 {
-        return wait_for_completion_timeout(&cpu_killed, 5000);
+        return 1;
 }
 
 /*
@@ -48,19 +45,6 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void platform_cpu_die(unsigned int cpu)
 {
-#ifdef DEBUG
-        unsigned int this_cpu = hard_smp_processor_id();
-
-        if (cpu != this_cpu) {
-                printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
-                           this_cpu, cpu);
-                BUG();
-        }
-#endif
-
-        printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
-        complete(&cpu_killed);
-
         /* directly enter low power state, skipping secure registers */
         platform_do_lowpower(cpu);
 }
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
new file mode 100644
index 000000000000..d35122ebc67b
--- /dev/null
+++ b/arch/arm/mach-ux500/id.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/cputype.h>
+#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/setup.h>
+
+struct dbx500_asic_id dbx500_id;
+
+static unsigned int ux500_read_asicid(phys_addr_t addr)
+{
+        phys_addr_t base = addr & ~0xfff;
+        struct map_desc desc = {
+                .virtual        = IO_ADDRESS(base),
+                .pfn            = __phys_to_pfn(base),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        };
+
+        iotable_init(&desc, 1);
+
+        /* As in devicemaps_init() */
+        local_flush_tlb_all();
+        flush_cache_all();
+
+        return readl(__io_address(addr));
+}
+
+static void ux500_print_soc_info(unsigned int asicid)
+{
+        unsigned int rev = dbx500_revision();
+
+        pr_info("DB%4x ", dbx500_partnumber());
+
+        if (rev == 0x01)
+                pr_cont("Early Drop");
+        else if (rev >= 0xA0)
+                pr_cont("v%d.%d" , (rev >> 4) - 0xA + 1, rev & 0xf);
+        else
+                pr_cont("Unknown");
+
+        pr_cont(" [%#010x]\n", asicid);
+}
+
+static unsigned int partnumber(unsigned int asicid)
+{
+        return (asicid >> 8) & 0xffff;
+}
+
+/*
+ * SOC          MIDR            ASICID ADDRESS          ASICID VALUE
+ * DB8500ed     0x410fc090      0x9001FFF4              0x00850001
+ * DB8500v1     0x411fc091      0x9001FFF4              0x008500A0
+ * DB8500v1.1   0x411fc091      0x9001FFF4              0x008500A1
+ * DB8500v2     0x412fc091      0x9001DBF4              0x008500B0
+ * DB5500v1     0x412fc091      0x9001FFF4              0x005500A0
+ */
+
+void __init ux500_map_io(void)
+{
+        unsigned int cpuid = read_cpuid_id();
+        unsigned int asicid = 0;
+        phys_addr_t addr = 0;
+
+        switch (cpuid) {
+        case 0x410fc090: /* DB8500ed */
+        case 0x411fc091: /* DB8500v1 */
+                addr = 0x9001FFF4;
+                break;
+
+        case 0x412fc091: /* DB8500v2 / DB5500v1 */
+                asicid = ux500_read_asicid(0x9001DBF4);
+                if (partnumber(asicid) == 0x8500)
+                        /* DB8500v2 */
+                        break;
+
+                /* DB5500v1 */
+                addr = 0x9001FFF4;
+                break;
+        }
+
+        if (addr)
+                asicid = ux500_read_asicid(addr);
+
+        if (!asicid) {
+                pr_err("Unable to identify SoC\n");
+                ux500_unknown_soc();
+        }
+
+        dbx500_id.process = asicid >> 24;
+        dbx500_id.partnumber = partnumber(asicid);
+        dbx500_id.revision = asicid & 0xff;
+
+        ux500_print_soc_info(asicid);
+}
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 3eafc0e24ba5..bd88c1e74060 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -114,4 +114,8 @@
 #define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
 #define U5500_MBOX2_LOCAL_END   (U5500_MBOX_BASE + 0x3F)
 
+#define U5500_ESRAM_BASE                0x40000000
+#define U5500_ESRAM_DMA_LCPA_OFFSET     0x10000
+#define U5500_DMA_LCPA_BASE    (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
+
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index f07d0986409d..0fefb34c11e4 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -92,7 +92,8 @@
 #define U8500_SCR_BASE          (U8500_PER4_BASE + 0x05000)
 #define U8500_DMC_BASE          (U8500_PER4_BASE + 0x06000)
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
-#define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x0f000)
+#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
+#define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
 
 /* per3 base addresses */
 #define U8500_FSMC_BASE         (U8500_PER3_BASE + 0x0000)
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index be7c0f14e310..700fb05ee815 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -14,7 +14,24 @@
 #error Invalid Ux500 debug UART
 #endif
 
-#define __UX500_UART(n) UX500_UART##n##_BASE
+/*
+ * DEBUG_LL only works if only one SOC is built in.  We don't use #else below
+ * in order to get "__UX500_UART redefined" warnings if more than one SOC is
+ * built, so that there's some hint during the build that something is wrong.
+ */
+
+#ifdef CONFIG_UX500_SOC_DB5500
+#define __UX500_UART(n) U5500_UART##n##_BASE
+#endif
+
+#ifdef CONFIG_UX500_SOC_DB8500
+#define __UX500_UART(n) U8500_UART##n##_BASE
+#endif
+
+#ifndef __UX500_UART
+#error Unknown SOC
+#endif
+
 #define UX500_UART(n)   __UX500_UART(n)
 #define UART_BASE       UX500_UART(CONFIG_UX500_DEBUG_UART)
 
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index b91a4d1211a2..020b6369a30a 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -14,27 +14,10 @@ extern struct platform_device u5500_gpio_devs[];
 extern struct platform_device u8500_gpio_devs[];
 
 extern struct amba_device ux500_pl031_device;
-extern struct amba_device u8500_ssp0_device;
-extern struct amba_device ux500_uart0_device;
-extern struct amba_device ux500_uart1_device;
-extern struct amba_device ux500_uart2_device;
 
-extern struct platform_device ux500_i2c1_device;
-extern struct platform_device ux500_i2c2_device;
-extern struct platform_device ux500_i2c3_device;
-
-extern struct platform_device u8500_i2c0_device;
-extern struct platform_device u8500_i2c4_device;
 extern struct platform_device u8500_dma40_device;
 extern struct platform_device ux500_ske_keypad_device;
 
-extern struct amba_device u8500_sdi0_device;
-extern struct amba_device u8500_sdi1_device;
-extern struct amba_device u8500_sdi2_device;
-extern struct amba_device u8500_sdi3_device;
-extern struct amba_device u8500_sdi4_device;
-extern struct amba_device u8500_sdi5_device;
-
 void dma40_u8500ed_fixup(void);
 
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
index 60ea88db8283..071bba94f727 100644
--- a/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -11,79 +11,10 @@
  * warranty of any kind, whether express or implied.
  */
 #include <mach/hardware.h>
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
                 .macro  disable_fiq
                 .endm
 
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =IO_ADDRESS(UX500_GIC_CPU_BASE)
-                .endm
-
                 .macro  arch_ret_to_user, tmp1, tmp2
                 .endm
-
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an
-                 * interrupt if it's between 30 and 1020. The test_for_ipi
-                 * routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number
-                 * of the highest priority enabled interrupt. We then just
-                 * need to check whether it is in the valid range for an
-                 * IRQ (30-1020 inclusive).
-                 */
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-                /* bits 12-10 = src CPU, 9-0 = int # */
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-
-                ldr     \tmp, =1021
-
-                bic     \irqnr, \irqstat, #0x1c00
-
-                cmp     \irqnr, #29
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-
-                .endm
-
-                /* We assume that irqstat (the raw value of the IRQ
-                 * acknowledge register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of
-                 * interrupt on the controller, since this requires the
-                 * original irqstat value which we won't easily be able
-                 * to recreate later.
-                 */
-
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
-
-                /* As above, this assumes that irqstat and base
-                 * are preserved..
-                 */
-
-                .macro test_for_ltirq, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                mov     \tmp, #0
-                cmp     \irqnr, #29
-                moveq   \tmp, #1
-                streq   \irqstat, [\base, #GIC_CPU_EOI]
-                cmp     \tmp, #0
-                .endm
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
index d548a622e7d2..3c4cd31ad9f7 100644
--- a/arch/arm/mach-ux500/include/mach/gpio.h
+++ b/arch/arm/mach-ux500/include/mach/gpio.h
@@ -9,42 +9,4 @@
 
 #include <plat/gpio.h>
 
-#define __GPIO_RESOURCE(soc, block)                                     \
-        {                                                               \
-                .start  = soc##_GPIOBANK##block##_BASE,                 \
-                .end    = soc##_GPIOBANK##block##_BASE + 127,           \
-                .flags  = IORESOURCE_MEM,                               \
-        },                                                              \
-        {                                                               \
-                .start  = IRQ_GPIO##block,                              \
-                .end    = IRQ_GPIO##block,                              \
-                .flags  = IORESOURCE_IRQ,                               \
-        }
-
-#define __GPIO_DEVICE(soc, block)                                       \
-        {                                                               \
-                .name           = "gpio",                               \
-                .id             = block,                                \
-                .num_resources  = 2,                                    \
-                .resource       = &soc##_gpio_resources[block * 2],     \
-                .dev = {                                                \
-                        .platform_data = &soc##_gpio_data[block],       \
-                },                                                      \
-        }
-
-#define GPIO_DATA(_name, first)                                         \
-        {                                                               \
-                .name           = _name,                                \
-                .first_gpio     = first,                                \
-                .first_irq      = NOMADIK_GPIO_TO_IRQ(first),           \
-        }
-
-#ifdef CONFIG_UX500_SOC_DB8500
-#define GPIO_RESOURCE(block)    __GPIO_RESOURCE(U8500, block)
-#define GPIO_DEVICE(block)      __GPIO_DEVICE(u8500, block)
-#elif defined(CONFIG_UX500_SOC_DB5500)
-#define GPIO_RESOURCE(block)    __GPIO_RESOURCE(U5500, block)
-#define GPIO_DEVICE(block)      __GPIO_DEVICE(u5500, block)
-#endif
-
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 32e883a8f2a2..bf63f2631ba0 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -29,118 +29,14 @@
 #include <mach/db8500-regs.h>
 #include <mach/db5500-regs.h>
 
-#ifdef CONFIG_UX500_SOC_DB8500
-#define UX500(periph)           U8500_##periph##_BASE
-#elif defined(CONFIG_UX500_SOC_DB5500)
-#define UX500(periph)           U5500_##periph##_BASE
-#endif
-
-#define UX500_BACKUPRAM0_BASE   UX500(BACKUPRAM0)
-#define UX500_BACKUPRAM1_BASE   UX500(BACKUPRAM1)
-#define UX500_B2R2_BASE         UX500(B2R2)
-
-#define UX500_CLKRST1_BASE      UX500(CLKRST1)
-#define UX500_CLKRST2_BASE      UX500(CLKRST2)
-#define UX500_CLKRST3_BASE      UX500(CLKRST3)
-#define UX500_CLKRST5_BASE      UX500(CLKRST5)
-#define UX500_CLKRST6_BASE      UX500(CLKRST6)
-
-#define UX500_DMA_BASE          UX500(DMA)
-#define UX500_FSMC_BASE         UX500(FSMC)
-
-#define UX500_GIC_CPU_BASE      UX500(GIC_CPU)
-#define UX500_GIC_DIST_BASE     UX500(GIC_DIST)
-
-#define UX500_I2C1_BASE         UX500(I2C1)
-#define UX500_I2C2_BASE         UX500(I2C2)
-#define UX500_I2C3_BASE         UX500(I2C3)
-
-#define UX500_L2CC_BASE         UX500(L2CC)
-#define UX500_MCDE_BASE         UX500(MCDE)
-#define UX500_MTU0_BASE         UX500(MTU0)
-#define UX500_MTU1_BASE         UX500(MTU1)
-#define UX500_PRCMU_BASE        UX500(PRCMU)
-
-#define UX500_RNG_BASE          UX500(RNG)
-#define UX500_RTC_BASE          UX500(RTC)
-
-#define UX500_SCU_BASE          UX500(SCU)
-
-#define UX500_SDI0_BASE         UX500(SDI0)
-#define UX500_SDI1_BASE         UX500(SDI1)
-#define UX500_SDI2_BASE         UX500(SDI2)
-#define UX500_SDI3_BASE         UX500(SDI3)
-#define UX500_SDI4_BASE         UX500(SDI4)
-
-#define UX500_SPI0_BASE         UX500(SPI0)
-#define UX500_SPI1_BASE         UX500(SPI1)
-#define UX500_SPI2_BASE         UX500(SPI2)
-#define UX500_SPI3_BASE         UX500(SPI3)
-
-#define UX500_SIA_BASE          UX500(SIA)
-#define UX500_SVA_BASE          UX500(SVA)
-
-#define UX500_TWD_BASE          UX500(TWD)
-
-#define UX500_UART0_BASE        UX500(UART0)
-#define UX500_UART1_BASE        UX500(UART1)
-#define UX500_UART2_BASE        UX500(UART2)
-
-#define UX500_USBOTG_BASE       UX500(USBOTG)
-
 /* ST-Ericsson modified pl022 id */
 #define SSP_PER_ID              0x01080022
 
 #ifndef __ASSEMBLY__
 
-#include <asm/cputype.h>
-
-static inline bool cpu_is_u8500(void)
-{
-#ifdef CONFIG_UX500_SOC_DB8500
-        return 1;
-#else
-        return 0;
-#endif
-}
-
-#define CPUID_DB8500ED  0x410fc090
-#define CPUID_DB8500V1  0x411fc091
-#define CPUID_DB8500V2  0x412fc091
+#include <mach/id.h>
 
-static inline bool cpu_is_u8500ed(void)
-{
-        return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500ED);
-}
-
-static inline bool cpu_is_u8500v1(void)
-{
-        return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V1);
-}
-
-static inline bool cpu_is_u8500v2(void)
-{
-        return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V2);
-}
-
-#ifdef CONFIG_UX500_SOC_DB8500
-bool cpu_is_u8500v10(void);
-bool cpu_is_u8500v11(void);
-bool cpu_is_u8500v20(void);
-#else
-static inline bool cpu_is_u8500v10(void) { return false; }
-static inline bool cpu_is_u8500v11(void) { return false; }
-static inline bool cpu_is_u8500v20(void) { return false; }
-#endif
-
-static inline bool cpu_is_u5500(void)
-{
-#ifdef CONFIG_UX500_SOC_DB5500
-        return 1;
-#else
-        return 0;
-#endif
-}
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 
 #endif
 
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
new file mode 100644
index 000000000000..f1288d10b6ab
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_UX500_ID
+#define __MACH_UX500_ID
+
+/**
+ * struct dbx500_asic_id - fields of the ASIC ID
+ * @process: the manufacturing process, 0x40 is 40 nm 0x00 is "standard"
+ * @partnumber: hithereto 0x8500 for DB8500
+ * @revision: version code in the series
+ */
+struct dbx500_asic_id {
+        u16     partnumber;
+        u8      revision;
+        u8      process;
+};
+
+extern struct dbx500_asic_id dbx500_id;
+
+static inline unsigned int __attribute_const__ dbx500_partnumber(void)
+{
+        return dbx500_id.partnumber;
+}
+
+static inline unsigned int __attribute_const__ dbx500_revision(void)
+{
+        return dbx500_id.revision;
+}
+
+/*
+ * SOCs
+ */
+
+static inline bool __attribute_const__ cpu_is_u8500(void)
+{
+        return dbx500_partnumber() == 0x8500;
+}
+
+static inline bool __attribute_const__ cpu_is_u5500(void)
+{
+        return dbx500_partnumber() == 0x5500;
+}
+
+/*
+ * 8500 revisions
+ */
+
+static inline bool __attribute_const__ cpu_is_u8500ed(void)
+{
+        return cpu_is_u8500() && dbx500_revision() == 0x00;
+}
+
+static inline bool __attribute_const__ cpu_is_u8500v1(void)
+{
+        return cpu_is_u8500() && (dbx500_revision() & 0xf0) == 0xA0;
+}
+
+static inline bool __attribute_const__ cpu_is_u8500v10(void)
+{
+        return cpu_is_u8500() && dbx500_revision() == 0xA0;
+}
+
+static inline bool __attribute_const__ cpu_is_u8500v11(void)
+{
+        return cpu_is_u8500() && dbx500_revision() == 0xA1;
+}
+
+static inline bool __attribute_const__ cpu_is_u8500v2(void)
+{
+        return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0);
+}
+
+#define ux500_unknown_soc()     BUG()
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index cca4f705601e..7cdeb2af0ebb 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -8,12 +8,36 @@
 #ifndef __MACH_IRQS_BOARD_MOP500_H
 #define __MACH_IRQS_BOARD_MOP500_H
 
-#define AB8500_NR_IRQS                  104
+/* Number of AB8500 irqs is taken from header file */
+#include <linux/mfd/ab8500.h>
 
 #define MOP500_AB8500_IRQ_BASE          IRQ_BOARD_START
 #define MOP500_AB8500_IRQ_END           (MOP500_AB8500_IRQ_BASE \
                                          + AB8500_NR_IRQS)
-#define MOP500_IRQ_END                  MOP500_AB8500_IRQ_END
+
+/* TC35892 */
+#define TC35892_NR_INTERNAL_IRQS        8
+#define TC35892_INT_GPIO(x)             (TC35892_NR_INTERNAL_IRQS + (x))
+#define TC35892_NR_GPIOS                24
+#define TC35892_NR_IRQS                 TC35892_INT_GPIO(TC35892_NR_GPIOS)
+
+#define MOP500_EGPIO_NR_IRQS            TC35892_NR_IRQS
+
+#define MOP500_EGPIO_IRQ_BASE           MOP500_AB8500_IRQ_END
+#define MOP500_EGPIO_IRQ_END            (MOP500_EGPIO_IRQ_BASE \
+                                         + MOP500_EGPIO_NR_IRQS)
+/* STMPE1601 irqs */
+#define STMPE_NR_INTERNAL_IRQS          9
+#define STMPE_INT_GPIO(x)               (STMPE_NR_INTERNAL_IRQS + (x))
+#define STMPE_NR_GPIOS                  24
+#define STMPE_NR_IRQS                   STMPE_INT_GPIO(STMPE_NR_GPIOS)
+
+#define MOP500_STMPE1601_IRQBASE        MOP500_EGPIO_IRQ_END
+#define MOP500_STMPE1601_IRQ(x)         (MOP500_STMPE1601_IRQBASE + (x))
+
+#define MOP500_NR_IRQS          MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
+
+#define MOP500_IRQ_END          MOP500_NR_IRQS
 
 #if MOP500_IRQ_END > IRQ_BOARD_END
 #undef IRQ_BOARD_END
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 693aa57de88d..ba1294c13c4d 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -21,50 +21,6 @@
 
 /* Interrupt numbers generic for shared peripheral */
 #define IRQ_MTU0                (IRQ_SHPI_START + 4)
-#define IRQ_SPI2                (IRQ_SHPI_START + 6)
-#define IRQ_SPI0                (IRQ_SHPI_START + 8)
-#define IRQ_UART0               (IRQ_SHPI_START + 11)
-#define IRQ_I2C3                (IRQ_SHPI_START + 12)
-#define IRQ_SSP0                (IRQ_SHPI_START + 14)
-#define IRQ_MTU1                (IRQ_SHPI_START + 17)
-#define IRQ_RTC_RTT             (IRQ_SHPI_START + 18)
-#define IRQ_UART1               (IRQ_SHPI_START + 19)
-#define IRQ_I2C0                (IRQ_SHPI_START + 21)
-#define IRQ_I2C1                (IRQ_SHPI_START + 22)
-#define IRQ_USBOTG              (IRQ_SHPI_START + 23)
-#define IRQ_DMA                 (IRQ_SHPI_START + 25)
-#define IRQ_UART2               (IRQ_SHPI_START + 26)
-#define IRQ_HSIR_EXCEP          (IRQ_SHPI_START + 29)
-#define IRQ_MSP0                (IRQ_SHPI_START + 31)
-#define IRQ_HSIR_CH0_OVRRUN     (IRQ_SHPI_START + 32)
-#define IRQ_HSIR_CH1_OVRRUN     (IRQ_SHPI_START + 33)
-#define IRQ_HSIR_CH2_OVRRUN     (IRQ_SHPI_START + 34)
-#define IRQ_HSIR_CH3_OVRRUN     (IRQ_SHPI_START + 35)
-#define IRQ_AB8500              (IRQ_SHPI_START + 40)
-#define IRQ_PRCMU               (IRQ_SHPI_START + 47)
-#define IRQ_DISP                (IRQ_SHPI_START + 48)
-#define IRQ_SiPI3               (IRQ_SHPI_START + 49)
-#define IRQ_I2C4                (IRQ_SHPI_START + 51)
-#define IRQ_SSP1                (IRQ_SHPI_START + 52)
-#define IRQ_I2C2                (IRQ_SHPI_START + 55)
-#define IRQ_SDMMC0              (IRQ_SHPI_START + 60)
-#define IRQ_MSP1                (IRQ_SHPI_START + 62)
-#define IRQ_SPI1                (IRQ_SHPI_START + 96)
-#define IRQ_MSP2                (IRQ_SHPI_START + 98)
-#define IRQ_SDMMC4              (IRQ_SHPI_START + 99)
-#define IRQ_HSIRD0              (IRQ_SHPI_START + 104)
-#define IRQ_HSIRD1              (IRQ_SHPI_START + 105)
-#define IRQ_HSITD0              (IRQ_SHPI_START + 106)
-#define IRQ_HSITD1              (IRQ_SHPI_START + 107)
-#define IRQ_GPIO0               (IRQ_SHPI_START + 119)
-#define IRQ_GPIO1               (IRQ_SHPI_START + 120)
-#define IRQ_GPIO2               (IRQ_SHPI_START + 121)
-#define IRQ_GPIO3               (IRQ_SHPI_START + 122)
-#define IRQ_GPIO4               (IRQ_SHPI_START + 123)
-#define IRQ_GPIO5               (IRQ_SHPI_START + 124)
-#define IRQ_GPIO6               (IRQ_SHPI_START + 125)
-#define IRQ_GPIO7               (IRQ_SHPI_START + 126)
-#define IRQ_GPIO8               (IRQ_SHPI_START + 127)
 
 /* There are 128 shared peripheral interrupts assigned to
  * INTID[160:32]. The first 32 interrupts are reserved.
@@ -80,7 +36,7 @@
 /* This will be overridden by board-specific irq headers */
 #define IRQ_BOARD_END                   IRQ_BOARD_START
 
-#ifdef CONFIG_MACH_U8500_MOP
+#ifdef CONFIG_MACH_U8500
 #include <mach/irqs-board-mop500.h>
 #endif
 
diff --git a/arch/arm/mach-ux500/include/mach/mbox.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
index 7f9da4d2fbda..7f9da4d2fbda 100644
--- a/arch/arm/mach-ux500/include/mach/mbox.h
+++ b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-defs.h b/arch/arm/mach-ux500/include/mach/prcmu-defs.h
new file mode 100644
index 000000000000..848ba64b561f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-defs.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ * Author: Martin Persson <martin.persson@stericsson.com>
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCM Unit definitions
+ */
+
+#ifndef __MACH_PRCMU_DEFS_H
+#define __MACH_PRCMU_DEFS_H
+
+enum prcmu_cpu_opp {
+        CPU_OPP_INIT      = 0x00,
+        CPU_OPP_NO_CHANGE = 0x01,
+        CPU_OPP_100       = 0x02,
+        CPU_OPP_50        = 0x03,
+        CPU_OPP_MAX       = 0x04,
+        CPU_OPP_EXT_CLK   = 0x07
+};
+enum prcmu_ape_opp {
+        APE_OPP_NO_CHANGE = 0x00,
+        APE_OPP_100       = 0x02,
+        APE_OPP_50        = 0x03,
+};
+
+#endif /* __MACH_PRCMU_DEFS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
index 8885f39a6421..455467e88791 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
@@ -1,10 +1,15 @@
 /*
- * Copyright (c) 2009 ST-Ericsson SA
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCM Unit registers
  */
+
 #ifndef __MACH_PRCMU_REGS_H
 #define __MACH_PRCMU_REGS_H
 
@@ -88,4 +93,4 @@
 /* Miscellaneous unit registers */
 #define PRCM_DSI_SW_RESET          (_PRCMU_BASE + 0x324)
 
-#endif /* __MACH_PRCMU__REGS_H */
+#endif /* __MACH_PRCMU_REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
index 549843ff6dbe..c49e456162ef 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -2,14 +2,27 @@
  * Copyright (C) STMicroelectronics 2009
  * Copyright (C) ST-Ericsson SA 2010
  *
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
+ *
  * License Terms: GNU General Public License v2
  *
- * PRCMU f/w APIs
+ * PRCM Unit f/w API
  */
 #ifndef __MACH_PRCMU_H
 #define __MACH_PRCMU_H
+#include <mach/prcmu-defs.h>
 
+void __init prcmu_early_init(void);
 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+int prcmu_set_ape_opp(enum prcmu_ape_opp opp);
+int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp);
+int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
+                           enum prcmu_cpu_opp cpu_opp);
+int prcmu_get_ape_opp(void);
+int prcmu_get_cpu_opp(void);
+bool prcmu_has_arm_maxopp(void);
 
 #endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 54bbe648bf58..a7d363fdb4cd 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -14,18 +14,23 @@
 #include <asm/mach/time.h>
 #include <linux/init.h>
 
-extern void __init ux500_map_io(void);
+void __init ux500_map_io(void);
 extern void __init u5500_map_io(void);
 extern void __init u8500_map_io(void);
 
-extern void __init ux500_init_devices(void);
 extern void __init u5500_init_devices(void);
 extern void __init u8500_init_devices(void);
 
 extern void __init ux500_init_irq(void);
+
+extern void __init u5500_sdi_init(void);
+
+extern void __init db5500_dma_init(void);
+
 /* We re-use nomadik_timer for this platform */
 extern void nmdk_timer_init(void);
 
+struct amba_device;
 extern void __init amba_add_devices(struct amba_device *devs[], int num);
 
 struct sys_timer;
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index 197e8417375e..ca2b15b1b3b1 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,7 +10,6 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
-#include <asm/smp_mpidr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
@@ -18,8 +17,8 @@ extern void u8500_secondary_startup(void);
 /*
  * We use IRQ1 as the IPI
  */
-static inline void smp_cross_call(const struct cpumask *mask)
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
 {
-        gic_raise_softirq(mask, 1);
+        gic_raise_softirq(mask, ipi);
 }
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 0271ca0a83df..9a6614c6808e 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -19,38 +19,43 @@
 #define __ASM_ARCH_UNCOMPRESS_H
 
 #include <asm/setup.h>
+#include <asm/mach-types.h>
 #include <linux/io.h>
+#include <linux/amba/serial.h>
 #include <mach/hardware.h>
 
-#define U8500_UART_DR           0x80007000
-#define U8500_UART_LCRH         0x8000702c
-#define U8500_UART_CR           0x80007030
-#define U8500_UART_FR           0x80007018
+static u32 ux500_uart_base;
 
 static void putc(const char c)
 {
         /* Do nothing if the UART is not enabled. */
-        if (!(__raw_readb(U8500_UART_CR) & 0x1))
+        if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1))
                 return;
 
         if (c == '\n')
                 putc('\r');
 
-        while (__raw_readb(U8500_UART_FR) & (1 << 5))
+        while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 5))
                 barrier();
-        __raw_writeb(c, U8500_UART_DR);
+        __raw_writeb(c, ux500_uart_base + UART01x_DR);
 }
 
 static void flush(void)
 {
-        if (!(__raw_readb(U8500_UART_CR) & 0x1))
+        if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1))
                 return;
-        while (__raw_readb(U8500_UART_FR) & (1 << 3))
+        while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 3))
                 barrier();
 }
 
 static inline void arch_decomp_setup(void)
 {
+        if (machine_is_u8500())
+                ux500_uart_base = U8500_UART2_BASE;
+        else if (machine_is_u5500())
+                ux500_uart_base = U5500_UART0_BASE;
+        else /* not much can be done to help here */
+                ux500_uart_base = U8500_UART2_BASE;
 }
 
 #define arch_decomp_wdog() /* nothing to do here */
diff --git a/arch/arm/mach-ux500/mbox.c b/arch/arm/mach-ux500/mbox-db5500.c
index 63435389c544..cbf15718fc3c 100644
--- a/arch/arm/mach-ux500/mbox.c
+++ b/arch/arm/mach-ux500/mbox-db5500.c
@@ -38,7 +38,7 @@
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/completion.h>
-#include <mach/mbox.h>
+#include <mach/mbox-db5500.h>
 
 #define MBOX_NAME "mbox"
 
diff --git a/arch/arm/mach-ux500/modem_irq.c b/arch/arm/mach-ux500/modem-irq-db5500.c
index 3187f8871169..e1296a7447c8 100644
--- a/arch/arm/mach-ux500/modem_irq.c
+++ b/arch/arm/mach-ux500/modem-irq-db5500.c
@@ -12,6 +12,8 @@
 #include <linux/io.h>
 #include <linux/slab.h>
 
+#include <mach/id.h>
+
 #define MODEM_INTCON_BASE_ADDR 0xBFFD3000
 #define MODEM_INTCON_SIZE 0xFFF
 
@@ -101,6 +103,9 @@ static int modem_irq_init(void)
         static struct irq_chip  modem_irq_chip;
         struct modem_irq *mi;
 
+        if (!cpu_is_u5500())
+                return -ENODEV;
+
         pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n",
                    IRQ_DB5500_MODEM);
 
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 9e4c678de785..4fff4d408417 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -18,39 +18,57 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/localtimer.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
+#include <mach/setup.h>
 
 /*
  * control for which core is the next to come out of the secondary
  * boot "holding pen"
  */
-volatile int __cpuinitdata pen_release = -1;
+volatile int pen_release = -1;
 
-static unsigned int __init get_core_count(void)
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
 {
-        return scu_get_core_count(__io_address(UX500_SCU_BASE));
+        pen_release = val;
+        smp_wmb();
+        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static void __iomem *scu_base_addr(void)
+{
+        if (cpu_is_u5500())
+                return __io_address(U5500_SCU_BASE);
+        else if (cpu_is_u8500())
+                return __io_address(U8500_SCU_BASE);
+        else
+                ux500_unknown_soc();
+
+        return NULL;
 }
 
 static DEFINE_SPINLOCK(boot_lock);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        trace_hardirqs_off();
-
         /*
          * if any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_cpu_init(0, __io_address(UX500_GIC_CPU_BASE));
+        gic_secondary_init(0);
 
         /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
-        pen_release = -1;
+        write_pen_release(-1);
 
         /*
          * Synchronise with the boot thread.
@@ -74,11 +92,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * the holding pen - release it, then wait for it to flag
          * that it has been released by resetting pen_release.
          */
-        pen_release = cpu;
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1);
+        write_pen_release(cpu);
 
-        smp_cross_call(cpumask_of(cpu));
+        smp_cross_call(cpumask_of(cpu), 1);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
@@ -97,8 +113,14 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init wakeup_secondary(void)
 {
-        /* nobody is to be released from the pen yet */
-        pen_release = -1;
+        void __iomem *backupram;
+
+        if (cpu_is_u5500())
+                backupram = __io_address(U5500_BACKUPRAM0_BASE);
+        else if (cpu_is_u8500())
+                backupram = __io_address(U8500_BACKUPRAM0_BASE);
+        else
+                ux500_unknown_soc();
 
         /*
          * write the address of secondary startup into the backup ram register
@@ -106,15 +128,13 @@ static void __init wakeup_secondary(void)
          * backup ram register at offset 0x1FF0, which is what boot rom code
          * is waiting for. This would wake up the secondary core from WFE
          */
-#define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4
+#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
         __raw_writel(virt_to_phys(u8500_secondary_startup),
-                __io_address(UX500_BACKUPRAM0_BASE) +
-                U8500_CPU1_JUMPADDR_OFFSET);
+                     backupram + UX500_CPU1_JUMPADDR_OFFSET);
 
-#define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
+#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
         __raw_writel(0xA1FEED01,
-                __io_address(UX500_BACKUPRAM0_BASE) +
-                U8500_CPU1_WAKEMAGIC_OFFSET);
+                     backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
 
         /* make sure write buffer is drained */
         mb();
@@ -126,40 +146,27 @@ static void __init wakeup_secondary(void)
  */
 void __init smp_init_cpus(void)
 {
-        unsigned int i, ncores = get_core_count();
+        void __iomem *scu_base = scu_base_addr();
+        unsigned int i, ncores;
 
-        for (i = 0; i < ncores; i++)
-                set_cpu_possible(i, true);
-}
-
-void __init smp_prepare_cpus(unsigned int max_cpus)
-{
-        unsigned int ncores = get_core_count();
-        unsigned int cpu = smp_processor_id();
-        int i;
+        ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
         /* sanity check */
-        if (ncores == 0) {
-                printk(KERN_ERR
-                       "U8500: strange CM count of 0? Default to 1\n");
-                ncores = 1;
-        }
-
-        if (ncores > num_possible_cpus())       {
+        if (ncores > NR_CPUS) {
                 printk(KERN_WARNING
                        "U8500: no. of cores (%d) greater than configured "
                        "maximum of %d - clipping\n",
-                       ncores, num_possible_cpus());
-                ncores = num_possible_cpus();
+                       ncores, NR_CPUS);
+                ncores = NR_CPUS;
         }
 
-        smp_store_cpu_info(cpu);
+        for (i = 0; i < ncores; i++)
+                set_cpu_possible(i, true);
+}
 
-        /*
-         * are we trying to boot more cores than exist?
-         */
-        if (max_cpus > ncores)
-                max_cpus = ncores;
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int i;
 
         /*
          * Initialise the present map, which describes the set of CPUs
@@ -168,13 +175,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
-        if (max_cpus > 1) {
-                /*
-                 * Enable the local timer or broadcast device for the
-                 * boot CPU, but only if we have more than one CPU.
-                 */
-                percpu_timer_setup();
-                scu_enable(__io_address(UX500_SCU_BASE));
-                wakeup_secondary();
-        }
+        scu_enable(scu_base_addr());
+        wakeup_secondary();
 }
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c
index 293274d1342a..c522d26ef348 100644
--- a/arch/arm/mach-ux500/prcmu.c
+++ b/arch/arm/mach-ux500/prcmu.c
@@ -1,10 +1,14 @@
 /*
- * Copyright (C) ST Ericsson SA 2010
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
  *
  * License Terms: GNU General Public License v2
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
  *
- * U8500 PRCMU driver.
+ * U8500 PRCM Unit interface driver
+ *
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -19,11 +23,26 @@
 
 #include <mach/hardware.h>
 #include <mach/prcmu-regs.h>
+#include <mach/prcmu-defs.h>
+
+/* Global var to runtime determine TCDM base for v2 or v1 */
+static __iomem void *tcdm_base;
+
+#define _MBOX_HEADER            (tcdm_base + 0xFE8)
+#define MBOX_HEADER_REQ_MB0     (_MBOX_HEADER + 0x0)
+
+#define REQ_MB1 (tcdm_base + 0xFD0)
+#define REQ_MB5 (tcdm_base + 0xE44)
 
-#define PRCMU_TCDM_BASE __io_address(U8500_PRCMU_TCDM_BASE)
+#define REQ_MB1_ARMOPP          (REQ_MB1 + 0x0)
+#define REQ_MB1_APEOPP          (REQ_MB1 + 0x1)
+#define REQ_MB1_BOOSTOPP        (REQ_MB1 + 0x2)
 
-#define REQ_MB5 (PRCMU_TCDM_BASE + 0xE44)
-#define ACK_MB5 (PRCMU_TCDM_BASE + 0xDF4)
+#define ACK_MB1 (tcdm_base + 0xE04)
+#define ACK_MB5 (tcdm_base + 0xDF4)
+
+#define ACK_MB1_CURR_ARMOPP             (ACK_MB1 + 0x0)
+#define ACK_MB1_CURR_APEOPP             (ACK_MB1 + 0x1)
 
 #define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
 #define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
@@ -33,10 +52,33 @@
 #define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
 #define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
 
-#define I2C_WRITE(slave) ((slave) << 1)
-#define I2C_READ(slave) (((slave) << 1) | BIT(0))
+#define PRCM_AVS_VARM_MAX_OPP           (tcdm_base + 0x2E4)
+#define PRCM_AVS_ISMODEENABLE           7
+#define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
+
+#define I2C_WRITE(slave) \
+        (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
+#define I2C_READ(slave) \
+        (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0) | BIT(0))
 #define I2C_STOP_EN BIT(3)
 
+enum mb1_h {
+        MB1H_ARM_OPP = 1,
+        MB1H_APE_OPP,
+        MB1H_ARM_APE_OPP,
+};
+
+static struct {
+        struct mutex lock;
+        struct completion work;
+        struct {
+                u8 arm_opp;
+                u8 ape_opp;
+                u8 arm_status;
+                u8 ape_status;
+        } ack;
+} mb1_transfer;
+
 enum ack_mb5_status {
         I2C_WR_OK = 0x01,
         I2C_RD_OK = 0x02,
@@ -145,6 +187,104 @@ unlock_and_return:
 }
 EXPORT_SYMBOL(prcmu_abb_write);
 
+static int set_ape_cpu_opps(u8 header, enum prcmu_ape_opp ape_opp,
+                            enum prcmu_cpu_opp cpu_opp)
+{
+        bool do_ape;
+        bool do_arm;
+        int err = 0;
+
+        do_ape = ((header == MB1H_APE_OPP) || (header == MB1H_ARM_APE_OPP));
+        do_arm = ((header == MB1H_ARM_OPP) || (header == MB1H_ARM_APE_OPP));
+
+        mutex_lock(&mb1_transfer.lock);
+
+        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
+                cpu_relax();
+
+        writeb(0, MBOX_HEADER_REQ_MB0);
+        writeb(cpu_opp, REQ_MB1_ARMOPP);
+        writeb(ape_opp, REQ_MB1_APEOPP);
+        writeb(0, REQ_MB1_BOOSTOPP);
+        writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
+        wait_for_completion(&mb1_transfer.work);
+        if ((do_ape) && (mb1_transfer.ack.ape_status != 0))
+                err = -EIO;
+        if ((do_arm) && (mb1_transfer.ack.arm_status != 0))
+                err = -EIO;
+
+        mutex_unlock(&mb1_transfer.lock);
+
+        return err;
+}
+
+/**
+ * prcmu_set_ape_opp() - Set the OPP of the APE.
+ * @opp:        The OPP to set.
+ *
+ * This function sets the OPP of the APE.
+ */
+int prcmu_set_ape_opp(enum prcmu_ape_opp opp)
+{
+        return set_ape_cpu_opps(MB1H_APE_OPP, opp, APE_OPP_NO_CHANGE);
+}
+EXPORT_SYMBOL(prcmu_set_ape_opp);
+
+/**
+ * prcmu_set_cpu_opp() - Set the OPP of the CPU.
+ * @opp:        The OPP to set.
+ *
+ * This function sets the OPP of the CPU.
+ */
+int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp)
+{
+        return set_ape_cpu_opps(MB1H_ARM_OPP, CPU_OPP_NO_CHANGE, opp);
+}
+EXPORT_SYMBOL(prcmu_set_cpu_opp);
+
+/**
+ * prcmu_set_ape_cpu_opps() - Set the OPPs of the APE and the CPU.
+ * @ape_opp:    The APE OPP to set.
+ * @cpu_opp:    The CPU OPP to set.
+ *
+ * This function sets the OPPs of the APE and the CPU.
+ */
+int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
+                           enum prcmu_cpu_opp cpu_opp)
+{
+        return set_ape_cpu_opps(MB1H_ARM_APE_OPP, ape_opp, cpu_opp);
+}
+EXPORT_SYMBOL(prcmu_set_ape_cpu_opps);
+
+/**
+ * prcmu_get_ape_opp() - Get the OPP of the APE.
+ *
+ * This function gets the OPP of the APE.
+ */
+enum prcmu_ape_opp prcmu_get_ape_opp(void)
+{
+        return readb(ACK_MB1_CURR_APEOPP);
+}
+EXPORT_SYMBOL(prcmu_get_ape_opp);
+
+/**
+ * prcmu_get_cpu_opp() - Get the OPP of the CPU.
+ *
+ * This function gets the OPP of the CPU. The OPP is specified in %%.
+ * PRCMU_OPP_EXT is a special OPP value, not specified in %%.
+ */
+int prcmu_get_cpu_opp(void)
+{
+        return readb(ACK_MB1_CURR_ARMOPP);
+}
+EXPORT_SYMBOL(prcmu_get_cpu_opp);
+
+bool prcmu_has_arm_maxopp(void)
+{
+        return (readb(PRCM_AVS_VARM_MAX_OPP) & PRCM_AVS_ISMODEENABLE_MASK)
+                == PRCM_AVS_ISMODEENABLE_MASK;
+}
+
 static void read_mailbox_0(void)
 {
         writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
@@ -152,6 +292,9 @@ static void read_mailbox_0(void)
 
 static void read_mailbox_1(void)
 {
+        mb1_transfer.ack.arm_opp = readb(ACK_MB1_CURR_ARMOPP);
+        mb1_transfer.ack.ape_opp = readb(ACK_MB1_CURR_APEOPP);
+        complete(&mb1_transfer.work);
         writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
 }
 
@@ -217,15 +360,35 @@ static irqreturn_t prcmu_irq_handler(int irq, void *data)
         return IRQ_HANDLED;
 }
 
+void __init prcmu_early_init(void)
+{
+        if (cpu_is_u8500v11() || cpu_is_u8500ed()) {
+                tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1);
+        } else if (cpu_is_u8500v2()) {
+                tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
+        } else {
+                pr_err("prcmu: Unsupported chip version\n");
+                BUG();
+        }
+}
+
 static int __init prcmu_init(void)
 {
+        if (cpu_is_u8500ed()) {
+                pr_err("prcmu: Unsupported chip version\n");
+                return 0;
+        }
+
+        mutex_init(&mb1_transfer.lock);
+        init_completion(&mb1_transfer.work);
         mutex_init(&mb5_transfer.lock);
         init_completion(&mb5_transfer.work);
 
         /* Clean up the mailbox interrupts after pre-kernel code. */
         writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
 
-        return request_irq(IRQ_PRCMU, prcmu_irq_handler, 0, "prcmu", NULL);
+        return request_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 0,
+                           "prcmu", NULL);
 }
 
 arch_initcall(prcmu_init);
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index c781f30c8368..3f7b5e9d83c5 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -4,6 +4,7 @@ menu "Versatile platform type"
 config ARCH_VERSATILE_PB
         bool "Support Versatile/PB platform"
         select CPU_ARM926T
+        select MIGHT_HAVE_PCI
         default y
         help
           Include support for the ARM(R) Versatile/PB platform.
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index e38acb0f89c8..13a83e45a33b 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -31,8 +31,8 @@
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
 #include <linux/gfp.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <asm/leds.h>
@@ -46,10 +46,11 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/clkdev.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
-#include <plat/timer-sp.h>
+#include <asm/hardware/timer-sp.h>
+
+#include <plat/sched_clock.h>
 
 #include "core.h"
 
@@ -886,6 +887,12 @@ void __init versatile_init(void)
 }
 
 /*
+ * The sched_clock counter
+ */
+#define REFCOUNTER              (__io_address(VERSATILE_SYS_BASE) + \
+                                 VERSATILE_SYS_24MHz_OFFSET)
+
+/*
  * Where is the timer (VA)?
  */
 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
@@ -900,6 +907,8 @@ static void __init versatile_timer_init(void)
 {
         u32 val;
 
+        versatile_sched_clock_init(REFCOUNTER, 24000000);
+
         /* 
          * set clock frequency: 
          *      VERSATILE_REFCLK is 32KHz
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 1b71b77ade22..2c0ac7de2814 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -5,4 +5,5 @@
 obj-y                                   := v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS)              += localtimer.o
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index 57dd95ce41f9..362780d868de 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -22,5 +22,3 @@ struct map_desc;
 
 void v2m_map_io(struct map_desc *tile, size_t num);
 extern struct sys_timer v2m_timer;
-
-extern void __iomem *gic_cpu_base_addr;
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index fd25ccd7272f..e628402b754c 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -8,8 +8,8 @@
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
 #include <asm/pgtable.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -18,10 +18,9 @@
 #include <asm/pmu.h>
 #include <asm/smp_twd.h>
 
-#include <mach/clkdev.h>
 #include <mach/ct-ca9x4.h>
 
-#include <plat/timer-sp.h>
+#include <asm/hardware/timer-sp.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -60,13 +59,10 @@ static void __init ct_ca9x4_map_io(void)
         v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
 
-void __iomem *gic_cpu_base_addr;
-
 static void __init ct_ca9x4_init_irq(void)
 {
-        gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
-        gic_dist_init(0, MMIO_P2V(A9_MPCORE_GIC_DIST), 29);
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
+                 MMIO_P2V(A9_MPCORE_GIC_CPU));
 }
 
 #if 0
diff --git a/arch/arm/mach-vexpress/hotplug.c b/arch/arm/mach-vexpress/hotplug.c
new file mode 100644
index 000000000000..ea4cbfb90a66
--- /dev/null
+++ b/arch/arm/mach-vexpress/hotplug.c
@@ -0,0 +1,128 @@
+/*
+ *  linux/arch/arm/mach-realview/hotplug.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+
+extern volatile int pen_release;
+
+static inline void cpu_enter_lowpower(void)
+{
+        unsigned int v;
+
+        flush_cache_all();
+        asm volatile(
+                "mcr    p15, 0, %1, c7, c5, 0\n"
+        "       mcr     p15, 0, %1, c7, c10, 4\n"
+        /*
+         * Turn off coherency
+         */
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       bic     %0, %0, %3\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+        "       mrc     p15, 0, %0, c1, c0, 0\n"
+        "       bic     %0, %0, %2\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+          : "=&r" (v)
+          : "r" (0), "Ir" (CR_C), "Ir" (0x40)
+          : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+        unsigned int v;
+
+        asm volatile(
+                "mrc    p15, 0, %0, c1, c0, 0\n"
+        "       orr     %0, %0, %1\n"
+        "       mcr     p15, 0, %0, c1, c0, 0\n"
+        "       mrc     p15, 0, %0, c1, c0, 1\n"
+        "       orr     %0, %0, %2\n"
+        "       mcr     p15, 0, %0, c1, c0, 1\n"
+          : "=&r" (v)
+          : "Ir" (CR_C), "Ir" (0x40)
+          : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
+{
+        /*
+         * there is no power-control hardware on this platform, so all
+         * we can do is put the core into WFI; this is safe as the calling
+         * code will have already disabled interrupts
+         */
+        for (;;) {
+                /*
+                 * here's the WFI
+                 */
+                asm(".word      0xe320f003\n"
+                    :
+                    :
+                    : "memory", "cc");
+
+                if (pen_release == cpu) {
+                        /*
+                         * OK, proper wakeup, we're done
+                         */
+                        break;
+                }
+
+                /*
+                 * Getting here, means that we have come out of WFI without
+                 * having been woken up - this shouldn't happen
+                 *
+                 * Just note it happening - when we're woken, we can report
+                 * its occurrence.
+                 */
+                (*spurious)++;
+        }
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+        return 1;
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+        int spurious = 0;
+
+        /*
+         * we're ready for shutdown now, so do it
+         */
+        cpu_enter_lowpower();
+        platform_do_lowpower(cpu, &spurious);
+
+        /*
+         * bring this CPU back into the world of cache
+         * coherency, and then restore interrupts
+         */
+        cpu_leave_lowpower();
+
+        if (spurious)
+                pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+        /*
+         * we don't allow CPU 0 to be shutdown (it is still too special
+         * e.g. clock tick interrupts)
+         */
+        return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S
index 20e9fb514f0a..73c11297509e 100644
--- a/arch/arm/mach-vexpress/include/mach/entry-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/entry-macro.S
@@ -1,67 +1,7 @@
-#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>
 
         .macro  disable_fiq
         .endm
 
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =gic_cpu_base_addr
-        ldr     \base, [\base]
-        .endm
-
         .macro  arch_ret_to_user, tmp1, tmp2
         .endm
-
-        /*
-         * The interrupt numbering scheme is defined in the
-         * interrupt controller spec.  To wit:
-         *
-         * Interrupts 0-15 are IPI
-         * 16-28 are reserved
-         * 29-31 are local.  We allow 30 to be used for the watchdog.
-         * 32-1020 are global
-         * 1021-1022 are reserved
-         * 1023 is "spurious" (no interrupt)
-         *
-         * For now, we ignore all local interrupts so only return an interrupt if it's
-         * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-         *
-         * A simple read from the controller will tell us the number of the highest
-         * priority enabled interrupt.  We then just need to check whether it is in the
-         * valid range for an IRQ (30-1020 inclusive).
-         */
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-        ldr     \tmp, =1021
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #29
-        cmpcc   \irqnr, \irqnr
-        cmpne   \irqnr, \tmp
-        cmpcs   \irqnr, \irqnr
-        .endm
-
-        /* We assume that irqstat (the raw value of the IRQ acknowledge
-         * register) is preserved from the macro above.
-         * If there is an IPI, we immediately signal end of interrupt on the
-         * controller, since this requires the original irqstat value which
-         * we won't easily be able to recreate later.
-         */
-
-        .macro test_for_ipi, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #16
-        strcc   \irqstat, [\base, #GIC_CPU_EOI]
-        cmpcs   \irqnr, \irqnr
-        .endm
-
-        /* As above, this assumes that irqstat and base are preserved.. */
-
-        .macro test_for_ltirq, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        mov     \tmp, #0
-        cmp     \irqnr, #29
-        moveq   \tmp, #1
-        streq   \irqstat, [\base, #GIC_CPU_EOI]
-        cmp     \tmp, #0
-        .endm
-
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 5a6da4fd247e..4c05e4a9713a 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,13 +2,12 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-#include <asm/smp_mpidr.h>
 
 /*
  * We use IRQ1 as the IPI
  */
-static inline void smp_cross_call(const struct cpumask *mask)
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
 {
-        gic_raise_softirq(mask, 1);
+        gic_raise_softirq(mask, ipi);
 }
 #endif
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 670970699ba9..b1687b6abe63 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -17,7 +17,6 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
-#include <asm/localtimer.h>
 #include <asm/smp_scu.h>
 #include <asm/unified.h>
 
@@ -35,6 +34,19 @@ extern void vexpress_secondary_startup(void);
  */
 volatile int __cpuinitdata pen_release = -1;
 
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
+{
+        pen_release = val;
+        smp_wmb();
+        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
 static void __iomem *scu_base_addr(void)
 {
         return MMIO_P2V(A9_MPCORE_SCU);
@@ -44,21 +56,18 @@ static DEFINE_SPINLOCK(boot_lock);
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        trace_hardirqs_off();
-
         /*
          * if any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
          */
-        gic_cpu_init(0, gic_cpu_base_addr);
+        gic_secondary_init(0);
 
         /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
-        pen_release = -1;
-        smp_wmb();
+        write_pen_release(-1);
 
         /*
          * Synchronise with the boot thread.
@@ -83,16 +92,14 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * since we haven't sent them a soft interrupt, they shouldn't
          * be there.
          */
-        pen_release = cpu;
-        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+        write_pen_release(cpu);
 
         /*
          * Send the secondary CPU a soft interrupt, thereby causing
          * the boot monitor to read the system wide flags register,
          * and branch to the address found there.
          */
-        smp_cross_call(cpumask_of(cpu));
+        smp_cross_call(cpumask_of(cpu), 1);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
@@ -124,13 +131,6 @@ void __init smp_init_cpus(void)
         ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 
         /* sanity check */
-        if (ncores == 0) {
-                printk(KERN_ERR
-                       "vexpress: strange CM count of 0? Default to 1\n");
-
-                ncores = 1;
-        }
-
         if (ncores > NR_CPUS) {
                 printk(KERN_WARNING
                        "vexpress: no. of cores (%d) greater than configured "
@@ -143,20 +143,10 @@ void __init smp_init_cpus(void)
                 set_cpu_possible(i, true);
 }
 
-void __init smp_prepare_cpus(unsigned int max_cpus)
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
-        unsigned int ncores = num_possible_cpus();
-        unsigned int cpu = smp_processor_id();
         int i;
 
-        smp_store_cpu_info(cpu);
-
-        /*
-         * are we trying to boot more cores than exist?
-         */
-        if (max_cpus > ncores)
-                max_cpus = ncores;
-
         /*
          * Initialise the present map, which describes the set of CPUs
          * actually populated at the present time.
@@ -164,27 +154,15 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (i = 0; i < max_cpus; i++)
                 set_cpu_present(i, true);
 
+        scu_enable(scu_base_addr());
+
         /*
-         * Initialise the SCU if there are more than one CPU and let
-         * them know where to start.
+         * Write the address of secondary startup into the
+         * system-wide flags register. The boot monitor waits
+         * until it receives a soft interrupt, and then the
+         * secondary CPU branches to this address.
          */
-        if (max_cpus > 1) {
-                /*
-                 * Enable the local timer or broadcast device for the
-                 * boot CPU, but only if we have more than one CPU.
-                 */
-                percpu_timer_setup();
-
-                scu_enable(scu_base_addr());
-
-                /*
-                 * Write the address of secondary startup into the
-                 * system-wide flags register. The boot monitor waits
-                 * until it receives a soft interrupt, and then the
-                 * secondary CPU branches to this address.
-                 */
-                writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
-                writel(BSYM(virt_to_phys(vexpress_secondary_startup)),
-                        MMIO_P2V(V2M_SYS_FLAGSSET));
-        }
+        writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
+        writel(BSYM(virt_to_phys(vexpress_secondary_startup)),
+                MMIO_P2V(V2M_SYS_FLAGSSET));
 }
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 7eaa232180a5..a9ed3428a2fa 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -11,18 +11,18 @@
 #include <linux/spinlock.h>
 #include <linux/sysdev.h>
 #include <linux/usb/isp1760.h>
+#include <linux/clkdev.h>
 
-#include <asm/clkdev.h>
 #include <asm/sizes.h>
 #include <asm/mach/flash.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/arm_timer.h>
+#include <asm/hardware/timer-sp.h>
 
-#include <mach/clkdev.h>
 #include <mach/motherboard.h>
 
-#include <plat/timer-sp.h>
+#include <plat/sched_clock.h>
 
 #include "core.h"
 
@@ -50,6 +50,8 @@ void __init v2m_map_io(struct map_desc *tile, size_t num)
 
 static void __init v2m_timer_init(void)
 {
+        versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
+
         writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
         writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
 
diff --git a/arch/arm/mach-w90x900/clock.h b/arch/arm/mach-w90x900/clock.h
index c56ddab3d912..b88a1b16b2e9 100644
--- a/arch/arm/mach-w90x900/clock.h
+++ b/arch/arm/mach-w90x900/clock.h
@@ -10,7 +10,7 @@
  * the Free Software Foundation; either version 2 of the License.
  */
 
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 void nuc900_clk_enable(struct clk *clk, int enable);
 void nuc900_subclk_enable(struct clk *clk, int enable);
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index b80f769bc135..4b089cb930dc 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -153,7 +153,6 @@ static struct clocksource clocksource_nuc900 = {
         .rating = 200,
         .read   = nuc900_get_cycles,
         .mask   = CLOCKSOURCE_MASK(TDR_SHIFT),
-        .shift  = 10,
         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -176,9 +175,7 @@ static void __init nuc900_clocksource_init(void)
         val |= (COUNTEN | PERIOD | PRESCALE);
         __raw_writel(val, REG_TCSR1);
 
-        clocksource_nuc900.mult =
-                clocksource_khz2mult((rate / 1000), clocksource_nuc900.shift);
-        clocksource_register(&clocksource_nuc900);
+        clocksource_register_hz(&clocksource_nuc900, rate);
 }
 
 static void __init nuc900_timer_init(void)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 4414a01e1e8a..fcc1e628e050 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -382,6 +382,12 @@ config CPU_FEROCEON_OLD_ID
           for which the CPU ID is equal to the ARM926 ID.
           Relevant for Feroceon-1850 and early Feroceon-2850.
 
+# Marvell PJ4
+config CPU_PJ4
+        bool
+        select CPU_V7
+        select ARM_THUMBEE
+
 # ARMv6
 config CPU_V6
         bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE
@@ -599,6 +605,14 @@ config CPU_CP15_MPU
         help
           Processor has the CP15 register, which has MPU related registers.
 
+config CPU_USE_DOMAINS
+        bool
+        depends on MMU
+        default y if !CPU_32v6K
+        help
+          This option enables or disables the use of domain switching
+          via the set_fs() function.
+
 #
 # CPU supports 36-bit I/O
 #
@@ -628,6 +642,33 @@ config ARM_THUMBEE
           Say Y here if you have a CPU with the ThumbEE extension and code to
           make use of it. Say N for code that can run on CPUs without ThumbEE.
 
+config SWP_EMULATE
+        bool "Emulate SWP/SWPB instructions"
+        depends on CPU_V7
+        select HAVE_PROC_CPU if PROC_FS
+        default y if SMP
+        help
+          ARMv6 architecture deprecates use of the SWP/SWPB instructions.
+          ARMv7 multiprocessing extensions introduce the ability to disable
+          these instructions, triggering an undefined instruction exception
+          when executed. Say Y here to enable software emulation of these
+          instructions for userspace (not kernel) using LDREX/STREX.
+          Also creates /proc/cpu/swp_emulation for statistics.
+
+          In some older versions of glibc [<=2.8] SWP is used during futex
+          trylock() operations with the assumption that the code will not
+          be preempted. This invalid assumption may be more likely to fail
+          with SWP emulation enabled, leading to deadlock of the user
+          application.
+
+          NOTE: when accessing uncached shared regions, LDREX/STREX rely
+          on an external transaction monitoring block called a global
+          monitor to maintain update atomicity. If your system does not
+          implement a global monitor, this option can cause programs that
+          perform SWP operations to uncached memory to deadlock.
+
+          If unsure, say Y.
+
 config CPU_BIG_ENDIAN
         bool "Build big-endian kernel"
         depends on ARCH_SUPPORTS_BIG_ENDIAN
@@ -772,7 +813,7 @@ config CACHE_L2X0
         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
                    REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
                    ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
-                   ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+                   ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
         default y
         select OUTER_CACHE
         select OUTER_CACHE_SYNC
@@ -789,7 +830,7 @@ config CACHE_PL310
 
 config CACHE_TAUROS2
         bool "Enable the Tauros2 L2 cache controller"
-        depends on (ARCH_DOVE || ARCH_MMP)
+        depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
         default y
         select OUTER_CACHE
         help
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index d63b6c413758..00d74a04af3a 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -5,8 +5,8 @@
 obj-y                           := dma-mapping.o extable.o fault.o init.o \
                                    iomap.o
 
-obj-$(CONFIG_MMU)               += fault-armv.o flush.o ioremap.o mmap.o \
-                                   pgd.o mmu.o vmregion.o
+obj-$(CONFIG_MMU)               += fault-armv.o flush.o idmap.o ioremap.o \
+                                   mmap.o pgd.o mmu.o vmregion.o
 
 ifneq ($(CONFIG_MMU),y)
 obj-y                           += nommu.o
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 809f1bf9fa29..6b48e0a3d7aa 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -312,7 +312,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
                 addr = page_address(page);
 
         if (addr)
-                *handle = page_to_dma(dev, page);
+                *handle = pfn_to_dma(dev, page_to_pfn(page));
 
         return addr;
 }
@@ -407,7 +407,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr
         if (!arch_is_coherent())
                 __dma_free_remap(cpu_addr, size);
 
-        __dma_free_buffer(dma_to_page(dev, handle), size);
+        __dma_free_buffer(pfn_to_page(dma_to_pfn(dev, handle)), size);
 }
 EXPORT_SYMBOL(dma_free_coherent);
 
@@ -555,17 +555,20 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
         struct scatterlist *s;
         int i, j;
 
+        BUG_ON(!valid_dma_direction(dir));
+
         for_each_sg(sg, s, nents, i) {
-                s->dma_address = dma_map_page(dev, sg_page(s), s->offset,
+                s->dma_address = __dma_map_page(dev, sg_page(s), s->offset,
                                                 s->length, dir);
                 if (dma_mapping_error(dev, s->dma_address))
                         goto bad_mapping;
         }
+        debug_dma_map_sg(dev, sg, nents, nents, dir);
         return nents;
 
  bad_mapping:
         for_each_sg(sg, s, i, j)
-                dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
+                __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
         return 0;
 }
 EXPORT_SYMBOL(dma_map_sg);
@@ -586,8 +589,10 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
         struct scatterlist *s;
         int i;
 
+        debug_dma_unmap_sg(dev, sg, nents, dir);
+
         for_each_sg(sg, s, nents, i)
-                dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
+                __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir);
 }
 EXPORT_SYMBOL(dma_unmap_sg);
 
@@ -612,6 +617,8 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
                 __dma_page_dev_to_cpu(sg_page(s), s->offset,
                                       s->length, dir);
         }
+
+        debug_dma_sync_sg_for_cpu(dev, sg, nents, dir);
 }
 EXPORT_SYMBOL(dma_sync_sg_for_cpu);
 
@@ -636,5 +643,16 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
                 __dma_page_cpu_to_dev(sg_page(s), s->offset,
                                       s->length, dir);
         }
+
+        debug_dma_sync_sg_for_device(dev, sg, nents, dir);
 }
 EXPORT_SYMBOL(dma_sync_sg_for_device);
+
+#define PREALLOC_DMA_DEBUG_ENTRIES      4096
+
+static int __init dma_debug_do_init(void)
+{
+        dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+        return 0;
+}
+fs_initcall(dma_debug_do_init);
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 83e59f870426..01210dba0221 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -26,7 +26,7 @@
 
 #include "mm.h"
 
-static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
+static pteval_t shared_pte_mask = L_PTE_MT_BUFFERABLE;
 
 #if __LINUX_ARM_ARCH__ < 6
 /*
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 1e21e125fe3a..f10f9bac2206 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -108,7 +108,7 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
 
                 pte = pte_offset_map(pmd, addr);
                 printk(", *pte=%08lx", pte_val(*pte));
-                printk(", *ppte=%08lx", pte_val(pte[-PTRS_PER_PTE]));
+                printk(", *ppte=%08lx", pte_val(pte[PTE_HWTABLE_PTRS]));
                 pte_unmap(pte);
         } while(0);
 
diff --git a/arch/arm/mm/idmap.c b/arch/arm/mm/idmap.c
new file mode 100644
index 000000000000..57299446f787
--- /dev/null
+++ b/arch/arm/mm/idmap.c
@@ -0,0 +1,67 @@
+#include <linux/kernel.h>
+
+#include <asm/cputype.h>
+#include <asm/pgalloc.h>
+#include <asm/pgtable.h>
+
+static void idmap_add_pmd(pgd_t *pgd, unsigned long addr, unsigned long end,
+        unsigned long prot)
+{
+        pmd_t *pmd = pmd_offset(pgd, addr);
+
+        addr = (addr & PMD_MASK) | prot;
+        pmd[0] = __pmd(addr);
+        addr += SECTION_SIZE;
+        pmd[1] = __pmd(addr);
+        flush_pmd_entry(pmd);
+}
+
+void identity_mapping_add(pgd_t *pgd, unsigned long addr, unsigned long end)
+{
+        unsigned long prot, next;
+
+        prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE;
+        if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
+                prot |= PMD_BIT4;
+
+        pgd += pgd_index(addr);
+        do {
+                next = pgd_addr_end(addr, end);
+                idmap_add_pmd(pgd, addr, next, prot);
+        } while (pgd++, addr = next, addr != end);
+}
+
+#ifdef CONFIG_SMP
+static void idmap_del_pmd(pgd_t *pgd, unsigned long addr, unsigned long end)
+{
+        pmd_t *pmd = pmd_offset(pgd, addr);
+        pmd_clear(pmd);
+}
+
+void identity_mapping_del(pgd_t *pgd, unsigned long addr, unsigned long end)
+{
+        unsigned long next;
+
+        pgd += pgd_index(addr);
+        do {
+                next = pgd_addr_end(addr, end);
+                idmap_del_pmd(pgd, addr, next);
+        } while (pgd++, addr = next, addr != end);
+}
+#endif
+
+/*
+ * In order to soft-boot, we need to insert a 1:1 mapping in place of
+ * the user-mode pages.  This will then ensure that we have predictable
+ * results when turning the mmu off
+ */
+void setup_mm_for_reboot(char mode)
+{
+        /*
+         * We need to access to user-mode page tables here. For kernel threads
+         * we don't have any user-mode mappings so we use the context that we
+         * "borrowed".
+         */
+        identity_mapping_add(current->active_mm->pgd, 0, TASK_SIZE);
+        local_flush_tlb_all();
+}
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 55c17a6fb22f..ab506272b2d3 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -204,12 +204,8 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
         /*
          * Don't allow RAM to be mapped - this causes problems with ARMv6+
          */
-        if (pfn_valid(pfn)) {
-                printk(KERN_WARNING "BUG: Your driver calls ioremap() on system memory.  This leads\n"
-                       "to architecturally unpredictable behaviour on ARMv6+, and ioremap()\n"
-                       "will fail in the next kernel release.  Please fix your driver.\n");
-                WARN_ON(1);
-        }
+        if (WARN_ON(pfn_valid(pfn)))
+                return NULL;
 
         type = get_mem_type(mtype);
         if (!type)
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 6630620380a4..36960df5fb76 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -16,7 +16,7 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
 }
 
 struct mem_type {
-        unsigned int prot_pte;
+        pteval_t prot_pte;
         unsigned int prot_l1;
         unsigned int prot_sect;
         unsigned int domain;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 72ad3e1f56cf..3c67e92f7d59 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -24,6 +24,7 @@
 #include <asm/smp_plat.h>
 #include <asm/tlb.h>
 #include <asm/highmem.h>
+#include <asm/traps.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -62,7 +63,7 @@ struct cachepolicy {
         const char      policy[16];
         unsigned int    cr_mask;
         unsigned int    pmd;
-        unsigned int    pte;
+        pteval_t        pte;
 };
 
 static struct cachepolicy cache_policies[] __initdata = {
@@ -190,7 +191,7 @@ void adjust_cr(unsigned long mask, unsigned long set)
 }
 #endif
 
-#define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
+#define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 
 static struct mem_type mem_types[] = {
@@ -235,19 +236,18 @@ static struct mem_type mem_types[] = {
         },
         [MT_LOW_VECTORS] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-                                L_PTE_EXEC,
+                                L_PTE_RDONLY,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .domain    = DOMAIN_USER,
         },
         [MT_HIGH_VECTORS] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-                                L_PTE_USER | L_PTE_EXEC,
+                                L_PTE_USER | L_PTE_RDONLY,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .domain    = DOMAIN_USER,
         },
         [MT_MEMORY] = {
-                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-                                L_PTE_WRITE | L_PTE_EXEC,
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
@@ -258,21 +258,20 @@ static struct mem_type mem_types[] = {
         },
         [MT_MEMORY_NONCACHED] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-                                L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE,
+                                L_PTE_MT_BUFFERABLE,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
                 .domain    = DOMAIN_KERNEL,
         },
         [MT_MEMORY_DTCM] = {
                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-                                L_PTE_WRITE,
+                                L_PTE_XN,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
                 .domain    = DOMAIN_KERNEL,
         },
         [MT_MEMORY_ITCM] = {
-                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
-                                L_PTE_WRITE | L_PTE_EXEC,
+                .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
                 .prot_l1   = PMD_TYPE_TABLE,
                 .domain    = DOMAIN_KERNEL,
         },
@@ -479,7 +478,7 @@ static void __init build_mem_type_table(void)
 
         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
-                                 L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot);
+                                 L_PTE_DIRTY | kern_pgprot);
 
         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
@@ -535,7 +534,7 @@ static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned l
 {
         if (pmd_none(*pmd)) {
                 pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t));
-                __pmd_populate(pmd, __pa(pte) | prot);
+                __pmd_populate(pmd, __pa(pte), prot);
         }
         BUG_ON(pmd_bad(*pmd));
         return pte_offset_kernel(pmd, addr);
@@ -553,7 +552,7 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 }
 
 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
-                                      unsigned long end, unsigned long phys,
+                                      unsigned long end, phys_addr_t phys,
                                       const struct mem_type *type)
 {
         pmd_t *pmd = pmd_offset(pgd, addr);
@@ -588,7 +587,8 @@ static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
 static void __init create_36bit_mapping(struct map_desc *md,
                                         const struct mem_type *type)
 {
-        unsigned long phys, addr, length, end;
+        unsigned long addr, length, end;
+        phys_addr_t phys;
         pgd_t *pgd;
 
         addr = md->virtual;
@@ -914,12 +914,11 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 {
         struct map_desc map;
         unsigned long addr;
-        void *vectors;
 
         /*
          * Allocate the vector page early.
          */
-        vectors = early_alloc(PAGE_SIZE);
+        vectors_page = early_alloc(PAGE_SIZE);
 
         for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
                 pmd_clear(pmd_off_k(addr));
@@ -959,7 +958,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
          * location (0xffff0000).  If we aren't using high-vectors, also
          * create a mapping at the low-vectors virtual address.
          */
-        map.pfn = __phys_to_pfn(virt_to_phys(vectors));
+        map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
         map.virtual = 0xffff0000;
         map.length = PAGE_SIZE;
         map.type = MT_HIGH_VECTORS;
@@ -1044,38 +1043,3 @@ void __init paging_init(struct machine_desc *mdesc)
         empty_zero_page = virt_to_page(zero_page);
         __flush_dcache_page(NULL, empty_zero_page);
 }
-
-/*
- * In order to soft-boot, we need to insert a 1:1 mapping in place of
- * the user-mode pages.  This will then ensure that we have predictable
- * results when turning the mmu off
- */
-void setup_mm_for_reboot(char mode)
-{
-        unsigned long base_pmdval;
-        pgd_t *pgd;
-        int i;
-
-        /*
-         * We need to access to user-mode page tables here. For kernel threads
-         * we don't have any user-mode mappings so we use the context that we
-         * "borrowed".
-         */
-        pgd = current->active_mm->pgd;
-
-        base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
-        if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
-                base_pmdval |= PMD_BIT4;
-
-        for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
-                unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
-                pmd_t *pmd;
-
-                pmd = pmd_off(pgd, i << PGDIR_SHIFT);
-                pmd[0] = __pmd(pmdval);
-                pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
-                flush_pmd_entry(pmd);
-        }
-
-        local_flush_tlb_all();
-}
diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c
index 69bbfc6645a6..93292a18cf77 100644
--- a/arch/arm/mm/pgd.c
+++ b/arch/arm/mm/pgd.c
@@ -17,12 +17,10 @@
 
 #include "mm.h"
 
-#define FIRST_KERNEL_PGD_NR     (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
-
 /*
  * need to get a 16k page for level 1
  */
-pgd_t *get_pgd_slow(struct mm_struct *mm)
+pgd_t *pgd_alloc(struct mm_struct *mm)
 {
         pgd_t *new_pgd, *init_pgd;
         pmd_t *new_pmd, *init_pmd;
@@ -32,14 +30,14 @@ pgd_t *get_pgd_slow(struct mm_struct *mm)
         if (!new_pgd)
                 goto no_pgd;
 
-        memset(new_pgd, 0, FIRST_KERNEL_PGD_NR * sizeof(pgd_t));
+        memset(new_pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 
         /*
          * Copy over the kernel and IO PGD entries
          */
         init_pgd = pgd_offset_k(0);
-        memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
-                       (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
+        memcpy(new_pgd + USER_PTRS_PER_PGD, init_pgd + USER_PTRS_PER_PGD,
+                       (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 
         clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t));
 
@@ -73,28 +71,29 @@ no_pgd:
         return NULL;
 }
 
-void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd)
+void pgd_free(struct mm_struct *mm, pgd_t *pgd_base)
 {
+        pgd_t *pgd;
         pmd_t *pmd;
         pgtable_t pte;
 
-        if (!pgd)
+        if (!pgd_base)
                 return;
 
-        /* pgd is always present and good */
-        pmd = pmd_off(pgd, 0);
-        if (pmd_none(*pmd))
-                goto free;
-        if (pmd_bad(*pmd)) {
-                pmd_ERROR(*pmd);
-                pmd_clear(pmd);
-                goto free;
-        }
+        pgd = pgd_base + pgd_index(0);
+        if (pgd_none_or_clear_bad(pgd))
+                goto no_pgd;
+
+        pmd = pmd_offset(pgd, 0);
+        if (pmd_none_or_clear_bad(pmd))
+                goto no_pmd;
 
         pte = pmd_pgtable(*pmd);
         pmd_clear(pmd);
         pte_free(mm, pte);
+no_pmd:
+        pgd_clear(pgd);
         pmd_free(mm, pmd);
-free:
-        free_pages((unsigned long) pgd, 2);
+no_pgd:
+        free_pages((unsigned long) pgd_base, 2);
 }
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index b795afd0a2c6..e32fa499194c 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -91,7 +91,7 @@
 #if L_PTE_SHARED != PTE_EXT_SHARED
 #error PTE shared bit mismatch
 #endif
-#if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\
+#if (L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
      L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
 #error Invalid Linux PTE bit settings
 #endif
@@ -109,6 +109,10 @@
  *  110x   0   1   0    r/w     r/o
  *  11x0   0   1   0    r/w     r/o
  *  1111   0   1   1    r/w     r/w
+ *
+ * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
+ *  110x   1   1   1    r/o     r/o
+ *  11x0   1   1   1    r/o     r/o
  */
         .macro  armv6_mt_table pfx
 \pfx\()_mt_table:
@@ -131,7 +135,7 @@
         .endm
 
         .macro  armv6_set_pte_ext pfx
-        str     r1, [r0], #-2048                @ linux version
+        str     r1, [r0], #2048                 @ linux version
 
         bic     r3, r1, #0x000003fc
         bic     r3, r3, #PTE_TYPE_MASK
@@ -142,17 +146,20 @@
         and     r2, r1, #L_PTE_MT_MASK
         ldr     r2, [ip, r2]
 
-        tst     r1, #L_PTE_WRITE
-        tstne   r1, #L_PTE_DIRTY
-        orreq   r3, r3, #PTE_EXT_APX
+        eor     r1, r1, #L_PTE_DIRTY
+        tst     r1, #L_PTE_DIRTY|L_PTE_RDONLY
+        orrne   r3, r3, #PTE_EXT_APX
 
         tst     r1, #L_PTE_USER
         orrne   r3, r3, #PTE_EXT_AP1
+#ifdef CONFIG_CPU_USE_DOMAINS
+        @ allow kernel read/write access to read-only user pages
         tstne   r3, #PTE_EXT_APX
         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+#endif
 
-        tst     r1, #L_PTE_EXEC
-        orreq   r3, r3, #PTE_EXT_XN
+        tst     r1, #L_PTE_XN
+        orrne   r3, r3, #PTE_EXT_XN
 
         orr     r3, r3, r2
 
@@ -180,9 +187,9 @@
  *  1111  0xff  r/w     r/w
  */
         .macro  armv3_set_pte_ext wc_disable=1
-        str     r1, [r0], #-2048                @ linux version
+        str     r1, [r0], #2048                 @ linux version
 
-        eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
+        eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
 
         bic     r2, r1, #PTE_SMALL_AP_MASK      @ keep C, B bits
         bic     r2, r2, #PTE_TYPE_MASK
@@ -191,7 +198,7 @@
         tst     r3, #L_PTE_USER                 @ user?
         orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
 
-        tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ write and dirty?
+        tst     r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
         orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
 
         tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
@@ -203,7 +210,7 @@
         bicne   r2, r2, #PTE_BUFFERABLE
 #endif
         .endif
-        str     r2, [r0]                        @ hardware version
+        str     r2, [r0]                @ hardware version
         .endm
 
 
@@ -223,9 +230,9 @@
  *  1111  11    r/w     r/w
  */
         .macro  xscale_set_pte_ext_prologue
-        str     r1, [r0], #-2048                @ linux version
+        str     r1, [r0]                        @ linux version
 
-        eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
+        eor     r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
 
         bic     r2, r1, #PTE_SMALL_AP_MASK      @ keep C, B bits
         orr     r2, r2, #PTE_TYPE_EXT           @ extended page
@@ -233,7 +240,7 @@
         tst     r3, #L_PTE_USER                 @ user?
         orrne   r2, r2, #PTE_EXT_AP_URO_SRW     @ yes -> user r/o, system r/w
 
-        tst     r3, #L_PTE_WRITE | L_PTE_DIRTY  @ write and dirty?
+        tst     r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
         orreq   r2, r2, #PTE_EXT_AP_UNO_SRW     @ yes -> user n/a, system r/w
                                                 @ combined with user -> user r/w
         .endm
@@ -242,7 +249,7 @@
         tst     r3, #L_PTE_PRESENT | L_PTE_YOUNG        @ present and young?
         movne   r2, #0                          @ no -> fault
 
-        str     r2, [r0]                        @ hardware version
+        str     r2, [r0, #2048]!                @ hardware version
         mov     ip, #0
         mcr     p15, 0, r0, c7, c10, 1          @ clean L1 D line
         mcr     p15, 0, ip, c7, c10, 4          @ data write barrier
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 9b9ff5d949fd..b49fab21517c 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -124,15 +124,13 @@ ENDPROC(cpu_v7_switch_mm)
  *      Set a level 2 translation table entry.
  *
  *      - ptep  - pointer to level 2 translation table entry
- *                (hardware version is stored at -1024 bytes)
+ *                (hardware version is stored at +2048 bytes)
  *      - pte   - PTE value to store
  *      - ext   - value for extended PTE bits
  */
 ENTRY(cpu_v7_set_pte_ext)
 #ifdef CONFIG_MMU
- ARM(   str     r1, [r0], #-2048        )       @ linux version
- THUMB( str     r1, [r0]                )       @ linux version
- THUMB( sub     r0, r0, #2048           )
+        str     r1, [r0]                        @ linux version
 
         bic     r3, r1, #0x000003f0
         bic     r3, r3, #PTE_TYPE_MASK
@@ -142,23 +140,26 @@ ENTRY(cpu_v7_set_pte_ext)
         tst     r1, #1 << 4
         orrne   r3, r3, #PTE_EXT_TEX(1)
 
-        tst     r1, #L_PTE_WRITE
-        tstne   r1, #L_PTE_DIRTY
-        orreq   r3, r3, #PTE_EXT_APX
+        eor     r1, r1, #L_PTE_DIRTY
+        tst     r1, #L_PTE_RDONLY | L_PTE_DIRTY
+        orrne   r3, r3, #PTE_EXT_APX
 
         tst     r1, #L_PTE_USER
         orrne   r3, r3, #PTE_EXT_AP1
+#ifdef CONFIG_CPU_USE_DOMAINS
+        @ allow kernel read/write access to read-only user pages
         tstne   r3, #PTE_EXT_APX
         bicne   r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+#endif
 
-        tst     r1, #L_PTE_EXEC
-        orreq   r3, r3, #PTE_EXT_XN
+        tst     r1, #L_PTE_XN
+        orrne   r3, r3, #PTE_EXT_XN
 
         tst     r1, #L_PTE_YOUNG
         tstne   r1, #L_PTE_PRESENT
         moveq   r3, #0
 
-        str     r3, [r0]
+        str     r3, [r0, #2048]!
         mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
 #endif
         mov     pc, lr
@@ -273,8 +274,6 @@ __v7_setup:
         ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
         ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
-        mov     r10, #0x1f                      @ domains 0, 1 = manager
-        mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
         /*
          * Memory region attributes with SCTLR.TRE=1
          *
@@ -313,6 +312,10 @@ __v7_setup:
 #ifdef CONFIG_CPU_ENDIAN_BE8
         orr     r6, r6, #1 << 25                @ big-endian page tables
 #endif
+#ifdef CONFIG_SWP_EMULATE
+        orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
+        bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
+#endif
         mrc     p15, 0, r0, c1, c0, 0           @ read control register
         bic     r0, r0, r5                      @ clear bits them
         orr     r0, r0, r6                      @ set them
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 523408c0bb38..5a37c5e45c41 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -500,8 +500,8 @@ ENTRY(cpu_xscale_set_pte_ext)
         @
         @ Erratum 40: must set memory to write-through for user read-only pages
         @
-        and     ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_WRITE) & ~(4 << 2)
-        teq     ip, #L_PTE_MT_WRITEBACK | L_PTE_USER
+        and     ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_RDONLY) & ~(4 << 2)
+        teq     ip, #L_PTE_MT_WRITEBACK | L_PTE_USER | L_PTE_RDONLY
 
         moveq   r1, #L_PTE_MT_WRITETHROUGH
         and     r1, r1, #L_PTE_MT_MASK
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 558cdfaf76b6..07f23bb42bed 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -17,6 +17,7 @@
 #include <linux/interrupt.h>
 #include <linux/time.h>
 #include <linux/init.h>
+#include <linux/sched.h>
 #include <linux/timex.h>
 #include <linux/sched.h>
 #include <linux/io.h>
@@ -24,6 +25,7 @@
 #include <linux/clockchips.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
+#include <asm/sched_clock.h>
 #include <asm/uaccess.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
@@ -50,15 +52,21 @@ static struct clocksource iop_clocksource = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static DEFINE_CLOCK_DATA(cd);
+
 /*
  * IOP sched_clock() implementation via its clocksource.
  */
-unsigned long long sched_clock(void)
+unsigned long long notrace sched_clock(void)
 {
-        cycle_t cyc = iop_clocksource_read(NULL);
-        struct clocksource *cs = &iop_clocksource;
+        u32 cyc = 0xffffffffu - read_tcr1();
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
 
-        return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+static void notrace iop_update_sched_clock(void)
+{
+        u32 cyc = 0xffffffffu - read_tcr1();
+        update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 /*
@@ -88,6 +96,7 @@ static void iop_set_mode(enum clock_event_mode mode,
         case CLOCK_EVT_MODE_PERIODIC:
                 write_tmr0(tmr & ~IOP_TMR_EN);
                 write_tcr0(ticks_per_jiffy - 1);
+                write_trr0(ticks_per_jiffy - 1);
                 tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
@@ -143,6 +152,8 @@ void __init iop_init_time(unsigned long tick_rate)
 {
         u32 timer_ctl;
 
+        init_sched_clock(&cd, iop_update_sched_clock, 32, tick_rate);
+
         ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
         iop_tick_rate = tick_rate;
 
@@ -153,6 +164,7 @@ void __init iop_init_time(unsigned long tick_rate)
          * Set up interrupting clockevent timer 0.
          */
         write_tmr0(timer_ctl & ~IOP_TMR_EN);
+        write_tisr(1);
         setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
         clockevents_calc_mult_shift(&iop_clockevent,
                                     tick_rate, IOP_MIN_RANGE);
@@ -162,9 +174,6 @@ void __init iop_init_time(unsigned long tick_rate)
                 clockevent_delta2ns(0xf, &iop_clockevent);
         iop_clockevent.cpumask = cpumask_of(0);
         clockevents_register_device(&iop_clockevent);
-        write_trr0(ticks_per_jiffy - 1);
-        write_tcr0(ticks_per_jiffy - 1);
-        write_tmr0(timer_ctl);
 
         /*
          * Set up free-running clocksource timer 1.
@@ -172,7 +181,5 @@ void __init iop_init_time(unsigned long tick_rate)
         write_trr1(0xffffffff);
         write_tcr1(0xffffffff);
         write_tmr1(timer_ctl);
-        clocksource_calc_mult_shift(&iop_clocksource, tick_rate,
-                                    IOP_MIN_RANGE);
-        clocksource_register(&iop_clocksource);
+        clocksource_register_hz(&iop_clocksource, tick_rate);
 }
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 64e3a64520e0..389f21795015 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -21,10 +21,6 @@ config ARCH_MX2
 
 config ARCH_MX25
         bool "MX25-based"
-        select CPU_ARM926T
-        select ARCH_MXC_IOMUX_V3
-        select HAVE_FB_IMX
-        select ARCH_MXC_AUDMUX_V2
         help
           This enables support for systems based on the Freescale i.MX25 family
 
@@ -51,7 +47,6 @@ endchoice
 
 source "arch/arm/mach-imx/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
-source "arch/arm/mach-mx25/Kconfig"
 source "arch/arm/mach-mxc91231/Kconfig"
 source "arch/arm/mach-mx5/Kconfig"
 
@@ -68,12 +63,10 @@ config MXC_IRQ_PRIOR
           Say N here, unless you have a specialized requirement.
 
 config MXC_TZIC
-        bool "Enable TrustZone Interrupt Controller"
-        depends on ARCH_MX51
-        help
-          This will be automatically selected for all processors
-          containing this interrupt controller.
-          Say N here only if you are really sure.
+        bool
+
+config MXC_AVIC
+        bool
 
 config MXC_PWM
         tristate "Enable PWM driver"
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 372670952789..5fd20e96876c 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,10 +3,11 @@
 #
 
 # Common support
-obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
+obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o
 
-# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
+# MX51 uses the TZIC interrupt controller, older platforms use AVIC
 obj-$(CONFIG_MXC_TZIC) += tzic.o
+obj-$(CONFIG_MXC_AVIC) += avic.o
 
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 0be1ac7f421b..175e3647bb27 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -209,7 +209,7 @@ static int mxc_audmux_v2_init(void)
                 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
         }
 #endif
-#if defined(CONFIG_ARCH_MX25)
+#if defined(CONFIG_SOC_IMX25)
         if (cpu_is_mx25()) {
                 audmux_clk = clk_get(NULL, "audmux");
                 if (IS_ERR(audmux_clk)) {
@@ -220,7 +220,7 @@ static int mxc_audmux_v2_init(void)
                 }
                 audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
         }
-#endif
+#endif /* if defined(CONFIG_SOC_IMX25) */
         audmux_debugfs_init();
 
         return 0;
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/avic.c
index 7331f2ace5fe..9a4e8a22dd0a 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -24,6 +24,8 @@
 #include <asm/mach/irq.h>
 #include <mach/hardware.h>
 
+#include "irq-common.h"
+
 #define AVIC_INTCNTL            0x00    /* int control reg */
 #define AVIC_NIMASK             0x04    /* int mask reg */
 #define AVIC_INTENNUM           0x08    /* int enable number reg */
@@ -46,9 +48,9 @@
 
 void __iomem *avic_base;
 
-int imx_irq_set_priority(unsigned char irq, unsigned char prio)
-{
 #ifdef CONFIG_MXC_IRQ_PRIOR
+static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
+{
         unsigned int temp;
         unsigned int mask = 0x0F << irq % 8 * 4;
 
@@ -62,14 +64,11 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio)
         __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
 
         return 0;
-#else
-        return -ENOSYS;
-#endif
 }
-EXPORT_SYMBOL(imx_irq_set_priority);
+#endif
 
 #ifdef CONFIG_FIQ
-int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
+static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
 {
         unsigned int irqt;
 
@@ -87,7 +86,6 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
 
         return 0;
 }
-EXPORT_SYMBOL(mxc_set_irq_fiq);
 #endif /* CONFIG_FIQ */
 
 /* Disable interrupt number "irq" in the AVIC */
@@ -102,10 +100,18 @@ static void mxc_unmask_irq(unsigned int irq)
         __raw_writel(irq, avic_base + AVIC_INTENNUM);
 }
 
-static struct irq_chip mxc_avic_chip = {
-        .ack = mxc_mask_irq,
-        .mask = mxc_mask_irq,
-        .unmask = mxc_unmask_irq,
+static struct mxc_irq_chip mxc_avic_chip = {
+        .base = {
+                .ack = mxc_mask_irq,
+                .mask = mxc_mask_irq,
+                .unmask = mxc_unmask_irq,
+        },
+#ifdef CONFIG_MXC_IRQ_PRIOR
+        .set_priority = avic_irq_set_priority,
+#endif
+#ifdef CONFIG_FIQ
+        .set_irq_fiq = avic_set_irq_fiq,
+#endif
 };
 
 /*
@@ -133,7 +139,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
         __raw_writel(0, avic_base + AVIC_INTTYPEH);
         __raw_writel(0, avic_base + AVIC_INTTYPEL);
         for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
-                set_irq_chip(i, &mxc_avic_chip);
+                set_irq_chip(i, &mxc_avic_chip.base);
                 set_irq_handler(i, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 039538e68793..ce81481becf1 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -144,7 +144,6 @@ static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)
         imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
 
         policy->cur = clk_get_rate(cpu_clk) / 1000;
-        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
         policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
         policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
 
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index 735776d84956..e9bcefe79a43 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
@@ -36,9 +37,10 @@ int __init mxc_register_device(struct platform_device *pdev, void *data)
         return ret;
 }
 
-struct platform_device *__init imx_add_platform_device(const char *name, int id,
+struct platform_device *__init imx_add_platform_device_dmamask(
+                const char *name, int id,
                 const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data)
+                const void *data, size_t size_data, u64 dmamask)
 {
         int ret = -ENOMEM;
         struct platform_device *pdev;
@@ -47,6 +49,23 @@ struct platform_device *__init imx_add_platform_device(const char *name, int id,
         if (!pdev)
                 goto err;
 
+        if (dmamask) {
+                /*
+                 * This memory isn't freed when the device is put,
+                 * I don't have a nice idea for that though.  Conceptually
+                 * dma_mask in struct device should not be a pointer.
+                 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
+                 */
+                pdev->dev.dma_mask =
+                        kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
+                if (!pdev->dev.dma_mask)
+                        /* ret is still -ENOMEM; */
+                        goto err;
+
+                *pdev->dev.dma_mask = dmamask;
+                pdev->dev.coherent_dma_mask = dmamask;
+        }
+
         if (res) {
                 ret = platform_device_add_resources(pdev, res, num_resources);
                 if (ret)
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 9aa6f3ea9012..2537166468ac 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,29 +1,73 @@
-config IMX_HAVE_PLATFORM_ESDHC
-        bool
-
 config IMX_HAVE_PLATFORM_FEC
         bool
-        default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51
+        default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51
 
 config IMX_HAVE_PLATFORM_FLEXCAN
         select HAVE_CAN_FLEXCAN if CAN
         bool
 
+config IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        bool
+
 config IMX_HAVE_PLATFORM_GPIO_KEYS
         bool
-        default y if ARCH_MX51
+        default y if SOC_IMX51
+
+config IMX_HAVE_PLATFORM_IMX21_HCD
+        bool
         
+config IMX_HAVE_PLATFORM_IMX2_WDT
+        bool
+
+config IMX_HAVE_PLATFORM_IMXDI_RTC
+        bool
+
+config IMX_HAVE_PLATFORM_IMX_FB
+        bool
+        select HAVE_FB_IMX
+
 config IMX_HAVE_PLATFORM_IMX_I2C
         bool
 
+config IMX_HAVE_PLATFORM_IMX_KEYPAD
+        bool
+
 config IMX_HAVE_PLATFORM_IMX_SSI
         bool
 
 config IMX_HAVE_PLATFORM_IMX_UART
         bool
 
+config IMX_HAVE_PLATFORM_IMX_UDC
+        bool
+
+config IMX_HAVE_PLATFORM_MX1_CAMERA
+        bool
+
+config IMX_HAVE_PLATFORM_MX2_CAMERA
+        bool
+
+config IMX_HAVE_PLATFORM_MXC_EHCI
+        bool
+
+config IMX_HAVE_PLATFORM_MXC_MMC
+        bool
+
 config IMX_HAVE_PLATFORM_MXC_NAND
         bool
 
+config IMX_HAVE_PLATFORM_MXC_PWM
+        bool
+
+config IMX_HAVE_PLATFORM_MXC_RNGA
+        bool
+        select ARCH_HAS_RNGA
+
+config IMX_HAVE_PLATFORM_MXC_W1
+        bool
+
+config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+        bool
+
 config IMX_HAVE_PLATFORM_SPI_IMX
         bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 45aefeb283ba..75cd2ece9053 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -1,10 +1,24 @@
-obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
 obj-y += platform-imx-dma.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c
deleted file mode 100644
index 2605bfa0dfb0..000000000000
--- a/arch/arm/plat-mxc/devices/platform-esdhc.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-
-#include <mach/hardware.h>
-#include <mach/devices-common.h>
-#include <mach/esdhc.h>
-
-#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR,  \
-                .irq = soc ## _INT_ESDHC ## hwid,                       \
-        }
-
-#define imx_esdhc_imx_data_entry(soc, id, hwid) \
-        [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid)
-
-#ifdef CONFIG_ARCH_MX25
-const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = {
-#define imx25_esdhc_data_entry(_id, _hwid)                              \
-        imx_esdhc_imx_data_entry(MX25, _id, _hwid)
-        imx25_esdhc_data_entry(0, 1),
-        imx25_esdhc_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_ARCH_MX25 */
-
-#ifdef CONFIG_ARCH_MX35
-const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = {
-#define imx35_esdhc_data_entry(_id, _hwid)                           \
-        imx_esdhc_imx_data_entry(MX35, _id, _hwid)
-        imx35_esdhc_data_entry(0, 1),
-        imx35_esdhc_data_entry(1, 2),
-        imx35_esdhc_data_entry(2, 3),
-};
-#endif /* ifdef CONFIG_ARCH_MX35 */
-
-#ifdef CONFIG_ARCH_MX51
-const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = {
-#define imx51_esdhc_data_entry(_id, _hwid)                              \
-        imx_esdhc_imx_data_entry(MX51, _id, _hwid)
-        imx51_esdhc_data_entry(0, 1),
-        imx51_esdhc_data_entry(1, 2),
-        imx51_esdhc_data_entry(2, 3),
-        imx51_esdhc_data_entry(3, 4),
-};
-#endif /* ifdef CONFIG_ARCH_MX51 */
-
-struct platform_device *__init imx_add_esdhc(
-                const struct imx_esdhc_imx_data *data,
-                const struct esdhc_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
-                        ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index 11d087f4e219..269ec78aba77 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -16,22 +16,22 @@
                 .irq = soc ## _INT_FEC,                                 \
         }
 
-#ifdef CONFIG_ARCH_MX25
+#ifdef CONFIG_SOC_IMX25
 const struct imx_fec_data imx25_fec_data __initconst =
         imx_fec_data_entry_single(MX25);
-#endif /* ifdef CONFIG_ARCH_MX25 */
+#endif /* ifdef CONFIG_SOC_IMX25 */
 
 #ifdef CONFIG_SOC_IMX27
 const struct imx_fec_data imx27_fec_data __initconst =
         imx_fec_data_entry_single(MX27);
 #endif /* ifdef CONFIG_SOC_IMX27 */
 
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 const struct imx_fec_data imx35_fec_data __initconst =
         imx_fec_data_entry_single(MX35);
 #endif
 
-#ifdef CONFIG_ARCH_MX51
+#ifdef CONFIG_SOC_IMX51
 const struct imx_fec_data imx51_fec_data __initconst =
         imx_fec_data_entry_single(MX51);
 #endif
diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c
index 5e97a01f14f3..4e8497af2eb1 100644
--- a/arch/arm/plat-mxc/devices/platform-flexcan.c
+++ b/arch/arm/plat-mxc/devices/platform-flexcan.c
@@ -5,26 +5,54 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-struct platform_device *__init imx_add_flexcan(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irq,
+#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size)           \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR,           \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_CAN ## _hwid,                        \
+        }
+
+#define imx_flexcan_data_entry(soc, _id, _hwid, _size)                  \
+        [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size)
+
+#ifdef CONFIG_SOC_IMX25
+const struct imx_flexcan_data imx25_flexcan_data[] __initconst = {
+#define imx25_flexcan_data_entry(_id, _hwid)                            \
+        imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K)
+        imx25_flexcan_data_entry(0, 1),
+        imx25_flexcan_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX25 */
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_flexcan_data imx35_flexcan_data[] __initconst = {
+#define imx35_flexcan_data_entry(_id, _hwid)                            \
+        imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K)
+        imx35_flexcan_data_entry(0, 1),
+        imx35_flexcan_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX35 */
+
+struct platform_device *__init imx_add_flexcan(
+                const struct imx_flexcan_data *data,
                 const struct flexcan_platform_data *pdata)
 {
         struct resource res[] = {
                 {
-                        .start = iobase,
-                        .end = iobase + iosize - 1,
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
                         .flags = IORESOURCE_MEM,
                 }, {
-                        .start = irq,
-                        .end = irq,
+                        .start = data->irq,
+                        .end = data->irq,
                         .flags = IORESOURCE_IRQ,
                 },
         };
 
-        return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata));
+        return imx_add_platform_device("flexcan", data->id,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
new file mode 100644
index 000000000000..59c33f6e401c
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_fsl_usb2_udc_data_entry_single(soc)                         \
+        {                                                               \
+                .iobase = soc ## _USB_OTG_BASE_ADDR,                    \
+                .irq = soc ## _INT_USB_OTG,                             \
+        }
+
+#ifdef CONFIG_SOC_IMX25
+const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
+        imx_fsl_usb2_udc_data_entry_single(MX25);
+#endif /* ifdef CONFIG_SOC_IMX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
+        imx_fsl_usb2_udc_data_entry_single(MX27);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_SOC_IMX31
+const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst =
+        imx_fsl_usb2_udc_data_entry_single(MX31);
+#endif /* ifdef CONFIG_SOC_IMX31 */
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
+        imx_fsl_usb2_udc_data_entry_single(MX35);
+#endif /* ifdef CONFIG_SOC_IMX35 */
+
+struct platform_device *__init imx_add_fsl_usb2_udc(
+                const struct imx_fsl_usb2_udc_data *data,
+                const struct fsl_usb2_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_512 - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("fsl-usb2-udc", -1,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index 3a705c7877dd..33530d2d5ed1 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -31,25 +31,25 @@ struct imx_imx_sdma_data {
                 },                                                      \
         }
 
-#ifdef CONFIG_ARCH_MX25
-const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
+#ifdef CONFIG_SOC_IMX25
+struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
         imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0);
-#endif /* ifdef CONFIG_ARCH_MX25 */
+#endif /* ifdef CONFIG_SOC_IMX25 */
 
-#ifdef CONFIG_ARCH_MX31
+#ifdef CONFIG_SOC_IMX31
 struct imx_imx_sdma_data imx31_imx_sdma_data __initdata =
         imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0);
-#endif /* ifdef CONFIG_ARCH_MX31 */
+#endif /* ifdef CONFIG_SOC_IMX31 */
 
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 struct imx_imx_sdma_data imx35_imx_sdma_data __initdata =
         imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0);
-#endif /* ifdef CONFIG_ARCH_MX35 */
+#endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_ARCH_MX51
-const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
+#ifdef CONFIG_SOC_IMX51
+struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
         imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0);
-#endif /* ifdef CONFIG_ARCH_MX51 */
+#endif /* ifdef CONFIG_SOC_IMX51 */
 
 static struct platform_device __init __maybe_unused *imx_add_imx_sdma(
                 const struct imx_imx_sdma_data *data)
@@ -76,6 +76,83 @@ static struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
         return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0);
 }
 
+#ifdef CONFIG_ARCH_MX25
+static struct sdma_script_start_addrs addr_imx25_to1 = {
+        .ap_2_ap_addr = 729,
+        .uart_2_mcu_addr = 904,
+        .per_2_app_addr = 1255,
+        .mcu_2_app_addr = 834,
+        .uartsh_2_mcu_addr = 1120,
+        .per_2_shp_addr = 1329,
+        .mcu_2_shp_addr = 1048,
+        .ata_2_mcu_addr = 1560,
+        .mcu_2_ata_addr = 1479,
+        .app_2_per_addr = 1189,
+        .app_2_mcu_addr = 770,
+        .shp_2_per_addr = 1407,
+        .shp_2_mcu_addr = 979,
+};
+#endif
+
+#ifdef CONFIG_ARCH_MX31
+static struct sdma_script_start_addrs addr_imx31_to1 = {
+        .per_2_per_addr = 1677,
+};
+
+static struct sdma_script_start_addrs addr_imx31_to2 = {
+        .ap_2_ap_addr = 423,
+        .ap_2_bp_addr = 829,
+        .bp_2_ap_addr = 1029,
+};
+#endif
+
+#ifdef CONFIG_ARCH_MX35
+static struct sdma_script_start_addrs addr_imx35_to1 = {
+        .ap_2_ap_addr = 642,
+        .uart_2_mcu_addr = 817,
+        .mcu_2_app_addr = 747,
+        .uartsh_2_mcu_addr = 1183,
+        .per_2_shp_addr = 1033,
+        .mcu_2_shp_addr = 961,
+        .ata_2_mcu_addr = 1333,
+        .mcu_2_ata_addr = 1252,
+        .app_2_mcu_addr = 683,
+        .shp_2_per_addr = 1111,
+        .shp_2_mcu_addr = 892,
+};
+
+static struct sdma_script_start_addrs addr_imx35_to2 = {
+        .ap_2_ap_addr = 729,
+        .uart_2_mcu_addr = 904,
+        .per_2_app_addr = 1597,
+        .mcu_2_app_addr = 834,
+        .uartsh_2_mcu_addr = 1270,
+        .per_2_shp_addr = 1120,
+        .mcu_2_shp_addr = 1048,
+        .ata_2_mcu_addr = 1429,
+        .mcu_2_ata_addr = 1339,
+        .app_2_per_addr = 1531,
+        .app_2_mcu_addr = 770,
+        .shp_2_per_addr = 1198,
+        .shp_2_mcu_addr = 979,
+};
+#endif
+
+#ifdef CONFIG_SOC_IMX51
+static struct sdma_script_start_addrs addr_imx51_to1 = {
+        .ap_2_ap_addr = 642,
+        .uart_2_mcu_addr = 817,
+        .mcu_2_app_addr = 747,
+        .mcu_2_shp_addr = 961,
+        .ata_2_mcu_addr = 1473,
+        .mcu_2_ata_addr = 1392,
+        .app_2_per_addr = 1033,
+        .app_2_mcu_addr = 683,
+        .shp_2_per_addr = 1251,
+        .shp_2_mcu_addr = 892,
+};
+#endif
+
 static int __init imxXX_add_imx_dma(void)
 {
         struct platform_device *ret;
@@ -86,30 +163,42 @@ static int __init imxXX_add_imx_dma(void)
         else
 #endif
 
-#if defined(CONFIG_ARCH_MX25)
-        if (cpu_is_mx25())
+#if defined(CONFIG_SOC_IMX25)
+        if (cpu_is_mx25()) {
+                imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25_to1;
                 ret = imx_add_imx_sdma(&imx25_imx_sdma_data);
-        else
+        } else
 #endif
 
-#if defined(CONFIG_ARCH_MX31)
+#if defined(CONFIG_SOC_IMX31)
         if (cpu_is_mx31()) {
-                imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4;
+                int to_version = mx31_revision() >> 4;
+                imx31_imx_sdma_data.pdata.to_version = to_version;
+                if (to_version == 1)
+                        imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1;
+                else
+                        imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2;
                 ret = imx_add_imx_sdma(&imx31_imx_sdma_data);
         } else
 #endif
 
-#if defined(CONFIG_ARCH_MX35)
+#if defined(CONFIG_SOC_IMX35)
         if (cpu_is_mx35()) {
-                imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4;
+                int to_version = mx35_revision() >> 4;
+                imx35_imx_sdma_data.pdata.to_version = to_version;
+                if (to_version == 1)
+                        imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1;
+                else
+                        imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2;
                 ret = imx_add_imx_sdma(&imx35_imx_sdma_data);
         } else
 #endif
 
 #if defined(CONFIG_ARCH_MX51)
-        if (cpu_is_mx51())
+        if (cpu_is_mx51()) {
+                imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1;
                 ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
-        else
+        } else
 #endif
                 ret = ERR_PTR(-ENODEV);
 
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c
new file mode 100644
index 000000000000..6100a7d824dd
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_imx_fb_data_entry_single(soc, _size)                        \
+        {                                                               \
+                .iobase = soc ## _LCDC_BASE_ADDR,                       \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_LCDC,                                \
+        }
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
+        imx_imx_fb_data_entry_single(MX21, SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_SOC_IMX25
+const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
+        imx_imx_fb_data_entry_single(MX25, SZ_16K);
+#endif /* ifdef CONFIG_SOC_IMX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
+        imx_imx_fb_data_entry_single(MX27, SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+struct platform_device *__init imx_add_imx_fb(
+                const struct imx_imx_fb_data *data,
+                const struct imx_fb_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("imx-fb", 0,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 679588453aad..72ba880c75af 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -30,7 +30,7 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
         imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
-#ifdef CONFIG_ARCH_MX25
+#ifdef CONFIG_SOC_IMX25
 const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
 #define imx25_imx_i2c_data_entry(_id, _hwid)                            \
         imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K)
@@ -38,7 +38,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
         imx25_imx_i2c_data_entry(1, 2),
         imx25_imx_i2c_data_entry(2, 3),
 };
-#endif /* ifdef CONFIG_ARCH_MX25 */
+#endif /* ifdef CONFIG_SOC_IMX25 */
 
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
@@ -49,7 +49,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX27 */
 
-#ifdef CONFIG_ARCH_MX31
+#ifdef CONFIG_SOC_IMX31
 const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
 #define imx31_imx_i2c_data_entry(_id, _hwid)                            \
         imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K)
@@ -57,9 +57,9 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
         imx31_imx_i2c_data_entry(1, 2),
         imx31_imx_i2c_data_entry(2, 3),
 };
-#endif /* ifdef CONFIG_ARCH_MX31 */
+#endif /* ifdef CONFIG_SOC_IMX31 */
 
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
 #define imx35_imx_i2c_data_entry(_id, _hwid)                            \
         imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
@@ -67,16 +67,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
         imx35_imx_i2c_data_entry(1, 2),
         imx35_imx_i2c_data_entry(2, 3),
 };
-#endif /* ifdef CONFIG_ARCH_MX35 */
+#endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_ARCH_MX51
+#ifdef CONFIG_SOC_IMX51
 const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
 #define imx51_imx_i2c_data_entry(_id, _hwid)                            \
         imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
         imx51_imx_i2c_data_entry(0, 1),
         imx51_imx_i2c_data_entry(1, 2),
 };
-#endif /* ifdef CONFIG_ARCH_MX51 */
+#endif /* ifdef CONFIG_SOC_IMX51 */
 
 struct platform_device *__init imx_add_imx_i2c(
                 const struct imx_imx_i2c_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
new file mode 100644
index 000000000000..40238f0b8643
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_imx_keypad_data_entry_single(soc, _size)                    \
+        {                                                               \
+                .iobase = soc ## _KPP_BASE_ADDR,                        \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_KPP,                                 \
+        }
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
+        imx_imx_keypad_data_entry_single(MX21, SZ_16);
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_SOC_IMX25
+const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst =
+        imx_imx_keypad_data_entry_single(MX25, SZ_16K);
+#endif /* ifdef CONFIG_SOC_IMX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
+        imx_imx_keypad_data_entry_single(MX27, SZ_16);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_SOC_IMX31
+const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst =
+        imx_imx_keypad_data_entry_single(MX31, SZ_16);
+#endif /* ifdef CONFIG_SOC_IMX31 */
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst =
+        imx_imx_keypad_data_entry_single(MX35, SZ_16);
+#endif /* ifdef CONFIG_SOC_IMX35 */
+
+struct platform_device *__init imx_add_imx_keypad(
+                const struct imx_imx_keypad_data *data,
+                const struct matrix_keymap_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imx-keypad", -1,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
index 38a7a0b8f2f1..2569c8d8a2ef 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
@@ -30,14 +30,14 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
-#ifdef CONFIG_ARCH_MX25
+#ifdef CONFIG_SOC_IMX25
 const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
 #define imx25_imx_ssi_data_entry(_id, _hwid)                            \
         imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
         imx25_imx_ssi_data_entry(0, 1),
         imx25_imx_ssi_data_entry(1, 2),
 };
-#endif /* ifdef CONFIG_ARCH_MX25 */
+#endif /* ifdef CONFIG_SOC_IMX25 */
 
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
@@ -48,32 +48,33 @@ const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX27 */
 
-#ifdef CONFIG_ARCH_MX31
+#ifdef CONFIG_SOC_IMX31
 const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = {
 #define imx31_imx_ssi_data_entry(_id, _hwid)                            \
         imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K)
         imx31_imx_ssi_data_entry(0, 1),
         imx31_imx_ssi_data_entry(1, 2),
 };
-#endif /* ifdef CONFIG_ARCH_MX31 */
+#endif /* ifdef CONFIG_SOC_IMX31 */
 
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
 #define imx35_imx_ssi_data_entry(_id, _hwid)                            \
         imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K)
         imx35_imx_ssi_data_entry(0, 1),
         imx35_imx_ssi_data_entry(1, 2),
 };
-#endif /* ifdef CONFIG_ARCH_MX35 */
+#endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_ARCH_MX51
+#ifdef CONFIG_SOC_IMX51
 const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
 #define imx51_imx_ssi_data_entry(_id, _hwid)                            \
         imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K)
         imx51_imx_ssi_data_entry(0, 1),
         imx51_imx_ssi_data_entry(1, 2),
+        imx51_imx_ssi_data_entry(2, 3),
 };
-#endif /* ifdef CONFIG_ARCH_MX51 */
+#endif /* ifdef CONFIG_SOC_IMX51 */
 
 struct platform_device *__init imx_add_imx_ssi(
                 const struct imx_imx_ssi_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index 2039640adf27..3c854c2cc6dd 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -47,7 +47,7 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
 };
 #endif
 
-#ifdef CONFIG_ARCH_MX25
+#ifdef CONFIG_SOC_IMX25
 const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
 #define imx25_imx_uart_data_entry(_id, _hwid)                           \
         imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
@@ -57,7 +57,7 @@ const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
         imx25_imx_uart_data_entry(3, 4),
         imx25_imx_uart_data_entry(4, 5),
 };
-#endif /* ifdef CONFIG_ARCH_MX25 */
+#endif /* ifdef CONFIG_SOC_IMX25 */
 
 #ifdef CONFIG_SOC_IMX27
 const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
@@ -72,7 +72,7 @@ const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX27 */
 
-#ifdef CONFIG_ARCH_MX31
+#ifdef CONFIG_SOC_IMX31
 const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
 #define imx31_imx_uart_data_entry(_id, _hwid)                           \
         imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K)
@@ -82,9 +82,9 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
         imx31_imx_uart_data_entry(3, 4),
         imx31_imx_uart_data_entry(4, 5),
 };
-#endif /* ifdef CONFIG_ARCH_MX31 */
+#endif /* ifdef CONFIG_SOC_IMX31 */
 
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
 #define imx35_imx_uart_data_entry(_id, _hwid)                           \
         imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
@@ -92,9 +92,21 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
         imx35_imx_uart_data_entry(1, 2),
         imx35_imx_uart_data_entry(2, 3),
 };
-#endif /* ifdef CONFIG_ARCH_MX35 */
+#endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_ARCH_MX51
+#ifdef CONFIG_SOC_IMX50
+const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = {
+#define imx50_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K)
+        imx50_imx_uart_data_entry(0, 1),
+        imx50_imx_uart_data_entry(1, 2),
+        imx50_imx_uart_data_entry(2, 3),
+        imx50_imx_uart_data_entry(3, 4),
+        imx50_imx_uart_data_entry(4, 5),
+};
+#endif /* ifdef CONFIG_SOC_IMX50 */
+
+#ifdef CONFIG_SOC_IMX51
 const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
 #define imx51_imx_uart_data_entry(_id, _hwid)                           \
         imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
@@ -102,7 +114,17 @@ const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
         imx51_imx_uart_data_entry(1, 2),
         imx51_imx_uart_data_entry(2, 3),
 };
-#endif /* ifdef CONFIG_ARCH_MX51 */
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+#ifdef CONFIG_SOC_IMX53
+const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = {
+#define imx53_imx_uart_data_entry(_id, _hwid)                           \
+        imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K)
+        imx53_imx_uart_data_entry(0, 1),
+        imx53_imx_uart_data_entry(1, 2),
+        imx53_imx_uart_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
 
 struct platform_device *__init imx_add_imx_uart_3irq(
                 const struct imx_imx_uart_3irq_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
new file mode 100644
index 000000000000..e0aec61177f4
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size)          \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR,          \
+                .iosize = _size,                                        \
+        }
+#define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size)                 \
+        [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size)
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
+        imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_SOC_IMX25
+const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst =
+        imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K);
+#endif /* ifdef CONFIG_SOC_IMX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
+        imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_SOC_IMX31
+const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst =
+        imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K);
+#endif /* ifdef CONFIG_SOC_IMX31 */
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst =
+        imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K);
+#endif /* ifdef CONFIG_SOC_IMX35 */
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
+#define imx51_imx2_wdt_data_entry(_id, _hwid)                           \
+        imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K)
+        imx51_imx2_wdt_data_entry(0, 1),
+        imx51_imx2_wdt_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+struct platform_device *__init imx_add_imx2_wdt(
+                const struct imx_imx2_wdt_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+        };
+        return imx_add_platform_device("imx2-wdt", data->id,
+                        res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c
new file mode 100644
index 000000000000..5770a42f33bf
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_imx21_hcd_data_entry_single(soc)                            \
+        {                                                               \
+                .iobase = soc ## _USBOTG_BASE_ADDR,                     \
+                .irq = soc ## _INT_USBHOST,                             \
+        }
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst =
+        imx_imx21_hcd_data_entry_single(MX21);
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+struct platform_device *__init imx_add_imx21_hcd(
+                const struct imx_imx21_hcd_data *data,
+                const struct mx21_usbh_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_8K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("imx21-hcd", 0,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/plat-mxc/devices/platform-imx_udc.c
new file mode 100644
index 000000000000..6fd675dfce14
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_udc.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_imx_udc_data_entry_single(soc, _size)                       \
+        {                                                               \
+                .iobase = soc ## _USBD_BASE_ADDR,                       \
+                .iosize = _size,                                        \
+                .irq0 = soc ## _INT_USBD0,                              \
+                .irq1 = soc ## _INT_USBD1,                              \
+                .irq2 = soc ## _INT_USBD2,                              \
+                .irq3 = soc ## _INT_USBD3,                              \
+                .irq4 = soc ## _INT_USBD4,                              \
+                .irq5 = soc ## _INT_USBD5,                              \
+                .irq6 = soc ## _INT_USBD6,                              \
+        }
+
+#define imx_imx_udc_data_entry(soc, _size)                              \
+        [_id] = imx_imx_udc_data_entry_single(soc, _size)
+
+#ifdef CONFIG_SOC_IMX1
+const struct imx_imx_udc_data imx1_imx_udc_data __initconst =
+        imx_imx_udc_data_entry_single(MX1, SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX1 */
+
+struct platform_device *__init imx_add_imx_udc(
+                const struct imx_imx_udc_data *data,
+                const struct imxusb_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq0,
+                        .end = data->irq0,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->irq1,
+                        .end = data->irq1,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->irq2,
+                        .end = data->irq2,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->irq3,
+                        .end = data->irq3,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->irq4,
+                        .end = data->irq4,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->irq5,
+                        .end = data->irq5,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->irq6,
+                        .end = data->irq6,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imx_udc", 0,
+                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
new file mode 100644
index 000000000000..10653cc8d1fa
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_imxdi_rtc_data_entry_single(soc)                            \
+        {                                                               \
+                .iobase = soc ## _DRYICE_BASE_ADDR,                     \
+                .irq = soc ## _INT_DRYICE,                              \
+        }
+
+#ifdef CONFIG_SOC_IMX25
+const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst =
+        imx_imxdi_rtc_data_entry_single(MX25);
+#endif /* ifdef CONFIG_SOC_IMX25 */
+
+struct platform_device *__init imx_add_imxdi_rtc(
+                const struct imx_imxdi_rtc_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_16K,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imxdi_rtc", 0,
+                        res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/plat-mxc/devices/platform-mx1-camera.c
new file mode 100644
index 000000000000..edcc581a30a9
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mx1-camera.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mx1_camera_data_entry_single(soc, _size)                    \
+        {                                                               \
+                .iobase = soc ## _CSI ## _BASE_ADDR,                    \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_CSI,                                 \
+        }
+
+#ifdef CONFIG_SOC_IMX1
+const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst =
+        imx_mx1_camera_data_entry_single(MX1, 10);
+#endif /* ifdef CONFIG_SOC_IMX1 */
+
+struct platform_device *__init imx_add_mx1_camera(
+                const struct imx_mx1_camera_data *data,
+                const struct mx1_camera_pdata *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("mx1-camera", 0,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c
new file mode 100644
index 000000000000..b3f4828dc447
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mx2_camera_data_entry_single(soc)                           \
+        {                                                               \
+                .iobasecsi = soc ## _CSI_BASE_ADDR,                     \
+                .iosizecsi = SZ_4K,                                     \
+                .irqcsi = soc ## _INT_CSI,                              \
+        }
+#define imx_mx2_camera_data_entry_single_emma(soc)                      \
+        {                                                               \
+                .iobasecsi = soc ## _CSI_BASE_ADDR,                     \
+                .iosizecsi = SZ_32,                                     \
+                .irqcsi = soc ## _INT_CSI,                              \
+                .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR,             \
+                .iosizeemmaprp = SZ_32,                                 \
+                .irqemmaprp = soc ## _INT_EMMAPRP,                      \
+        }
+
+#ifdef CONFIG_SOC_IMX25
+const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
+        imx_mx2_camera_data_entry_single(MX25);
+#endif /* ifdef CONFIG_SOC_IMX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
+        imx_mx2_camera_data_entry_single_emma(MX27);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+struct platform_device *__init imx_add_mx2_camera(
+                const struct imx_mx2_camera_data *data,
+                const struct mx2_camera_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobasecsi,
+                        .end = data->iobasecsi + data->iosizecsi - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irqcsi,
+                        .end = data->irqcsi,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->iobaseemmaprp,
+                        .end = data->iobaseemmaprp + data->iosizeemmaprp - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irqemmaprp,
+                        .end = data->irqemmaprp,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("mx2-camera", 0,
+                        res, data->iobaseemmaprp ? 4 : 2,
+                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
new file mode 100644
index 000000000000..cc488f4b6204
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mxc_ehci_data_entry_single(soc, _id, hs)                    \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _USB_ ## hs ## _BASE_ADDR,             \
+                .irq = soc ## _INT_USB_ ## hs,                          \
+        }
+
+#ifdef CONFIG_SOC_IMX25
+const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst =
+        imx_mxc_ehci_data_entry_single(MX25, 0, OTG);
+const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst =
+        imx_mxc_ehci_data_entry_single(MX25, 1, HS);
+#endif /* ifdef CONFIG_SOC_IMX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
+        imx_mxc_ehci_data_entry_single(MX27, 0, OTG);
+const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = {
+        imx_mxc_ehci_data_entry_single(MX27, 1, HS1),
+        imx_mxc_ehci_data_entry_single(MX27, 2, HS2),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_SOC_IMX31
+const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst =
+        imx_mxc_ehci_data_entry_single(MX31, 0, OTG);
+const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = {
+        imx_mxc_ehci_data_entry_single(MX31, 1, HS1),
+        imx_mxc_ehci_data_entry_single(MX31, 2, HS2),
+};
+#endif /* ifdef CONFIG_SOC_IMX31 */
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst =
+        imx_mxc_ehci_data_entry_single(MX35, 0, OTG);
+const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
+        imx_mxc_ehci_data_entry_single(MX35, 1, HS);
+#endif /* ifdef CONFIG_SOC_IMX35 */
+
+struct platform_device *__init imx_add_mxc_ehci(
+                const struct imx_mxc_ehci_data *data,
+                const struct mxc_usbh_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_512 - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+        return imx_add_platform_device_dmamask("mxc-ehci", data->id,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c
new file mode 100644
index 000000000000..90d762f6f93b
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size)           \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR,          \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_SDHC ## _hwid,                       \
+                .dmareq = soc ## _DMA_REQ_SDHC ## _hwid,                \
+        }
+#define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size)                  \
+        [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size)
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = {
+#define imx21_mxc_mmc_data_entry(_id, _hwid)                            \
+        imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K)
+        imx21_mxc_mmc_data_entry(0, 1),
+        imx21_mxc_mmc_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = {
+#define imx27_mxc_mmc_data_entry(_id, _hwid)                            \
+        imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K)
+        imx27_mxc_mmc_data_entry(0, 1),
+        imx27_mxc_mmc_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_SOC_IMX31
+const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = {
+#define imx31_mxc_mmc_data_entry(_id, _hwid)                            \
+        imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K)
+        imx31_mxc_mmc_data_entry(0, 1),
+        imx31_mxc_mmc_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX31 */
+
+struct platform_device *__init imx_add_mxc_mmc(
+                const struct imx_mxc_mmc_data *data,
+                const struct imxmmc_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_4K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = data->dmareq,
+                        .end = data->dmareq,
+                        .flags = IORESOURCE_DMA,
+                },
+        };
+        return imx_add_platform_device_dmamask("mxc-mmc", data->id,
+                        res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
index 3fdcc32e3d67..1568f39fba8b 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -31,27 +31,27 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
         imx_mxc_nand_data_entry_single(MX21, SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
-#ifdef CONFIG_ARCH_MX25
+#ifdef CONFIG_SOC_IMX25
 const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
         imx_mxc_nand_data_entry_single(MX25, SZ_8K);
-#endif /* ifdef CONFIG_ARCH_MX25 */
+#endif /* ifdef CONFIG_SOC_IMX25 */
 
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
         imx_mxc_nand_data_entry_single(MX27, SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX27 */
 
-#ifdef CONFIG_ARCH_MX31
+#ifdef CONFIG_SOC_IMX31
 const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
         imx_mxc_nand_data_entry_single(MX31, SZ_4K);
 #endif
 
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
         imx_mxc_nand_data_entry_single(MX35, SZ_8K);
 #endif
 
-#ifdef CONFIG_ARCH_MX51
+#ifdef CONFIG_SOC_IMX51
 const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
         imx_mxc_nandv3_data_entry_single(MX51, SZ_16K);
 #endif
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
new file mode 100644
index 000000000000..3d8ebdba38ee
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)           \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR,           \
+                .iosize = _size,                                        \
+                .irq = soc ## _INT_PWM ## _hwid,                        \
+        }
+#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size)                  \
+        [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst =
+        imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_SOC_IMX25
+const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = {
+#define imx25_mxc_pwm_data_entry(_id, _hwid)                            \
+        imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K)
+        imx25_mxc_pwm_data_entry(0, 1),
+        imx25_mxc_pwm_data_entry(1, 2),
+        imx25_mxc_pwm_data_entry(2, 3),
+        imx25_mxc_pwm_data_entry(3, 4),
+};
+#endif /* ifdef CONFIG_SOC_IMX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
+        imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+struct platform_device *__init imx_add_mxc_pwm(
+                const struct imx_mxc_pwm_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + data->iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("mxc_pwm", data->id,
+                        res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c
new file mode 100644
index 000000000000..b4b7612b6e17
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+struct imx_mxc_rnga_data {
+        resource_size_t iobase;
+};
+
+#define imx_mxc_rnga_data_entry_single(soc)                             \
+        {                                                               \
+                .iobase = soc ## _RNGA_BASE_ADDR,                       \
+        }
+
+#ifdef CONFIG_SOC_IMX31
+static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst =
+        imx_mxc_rnga_data_entry_single(MX31);
+#endif /* ifdef CONFIG_SOC_IMX31 */
+
+static struct platform_device *__init imx_add_mxc_rnga(
+                const struct imx_mxc_rnga_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_16K - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+        };
+        return imx_add_platform_device("mxc_rnga", -1,
+                        res, ARRAY_SIZE(res), NULL, 0);
+}
+
+static int __init imxXX_add_mxc_rnga(void)
+{
+        struct platform_device *ret;
+
+#if defined(CONFIG_SOC_IMX31)
+        if (cpu_is_mx31())
+                ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data);
+        else
+#endif /* if defined(CONFIG_SOC_IMX31) */
+                ret = ERR_PTR(-ENODEV);
+
+        if (IS_ERR(ret))
+                return PTR_ERR(ret);
+
+        return 0;
+}
+arch_initcall(imxXX_add_mxc_rnga);
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c
new file mode 100644
index 000000000000..96fa5ea91fe8
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mxc_w1_data_entry_single(soc)                               \
+        {                                                               \
+                .iobase = soc ## _OWIRE_BASE_ADDR,                      \
+        }
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst =
+        imx_mxc_w1_data_entry_single(MX21);
+#endif /* ifdef CONFIG_SOC_IMX21 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst =
+        imx_mxc_w1_data_entry_single(MX27);
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_SOC_IMX31
+const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst =
+        imx_mxc_w1_data_entry_single(MX31);
+#endif /* ifdef CONFIG_SOC_IMX31 */
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst =
+        imx_mxc_w1_data_entry_single(MX35);
+#endif /* ifdef CONFIG_SOC_IMX35 */
+
+struct platform_device *__init imx_add_mxc_w1(
+                const struct imx_mxc_w1_data *data)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_4K - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+        };
+
+        return imx_add_platform_device("mxc_w1", 0,
+                        res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
new file mode 100644
index 000000000000..b3525648a01d
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+#include <mach/esdhc.h>
+
+#define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \
+        {                                                               \
+                .id = _id,                                              \
+                .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR,  \
+                .irq = soc ## _INT_ESDHC ## hwid,                       \
+        }
+
+#define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid)   \
+        [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid)
+
+#ifdef CONFIG_SOC_IMX25
+const struct imx_sdhci_esdhc_imx_data
+imx25_sdhci_esdhc_imx_data[] __initconst = {
+#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
+        imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid)
+        imx25_sdhci_esdhc_imx_data_entry(0, 1),
+        imx25_sdhci_esdhc_imx_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_SOC_IMX25 */
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_sdhci_esdhc_imx_data
+imx35_sdhci_esdhc_imx_data[] __initconst = {
+#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
+        imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid)
+        imx35_sdhci_esdhc_imx_data_entry(0, 1),
+        imx35_sdhci_esdhc_imx_data_entry(1, 2),
+        imx35_sdhci_esdhc_imx_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX35 */
+
+#ifdef CONFIG_SOC_IMX51
+const struct imx_sdhci_esdhc_imx_data
+imx51_sdhci_esdhc_imx_data[] __initconst = {
+#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid)                    \
+        imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid)
+        imx51_sdhci_esdhc_imx_data_entry(0, 1),
+        imx51_sdhci_esdhc_imx_data_entry(1, 2),
+        imx51_sdhci_esdhc_imx_data_entry(2, 3),
+        imx51_sdhci_esdhc_imx_data_entry(3, 4),
+};
+#endif /* ifdef CONFIG_SOC_IMX51 */
+
+struct platform_device *__init imx_add_sdhci_esdhc_imx(
+                const struct imx_sdhci_esdhc_imx_data *data,
+                const struct esdhc_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = data->iobase,
+                        .end = data->iobase + SZ_16K - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = data->irq,
+                        .end = data->irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
+                        ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 17f724c9452d..8ea49adcdfc1 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -30,7 +30,7 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
 };
 #endif
 
-#ifdef CONFIG_ARCH_MX25
+#ifdef CONFIG_SOC_IMX25
 const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
 #define imx25_cspi_data_entry(_id, _hwid)                               \
         imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
@@ -38,7 +38,7 @@ const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
         imx25_cspi_data_entry(1, 2),
         imx25_cspi_data_entry(2, 3),
 };
-#endif /* ifdef CONFIG_ARCH_MX25 */
+#endif /* ifdef CONFIG_SOC_IMX25 */
 
 #ifdef CONFIG_SOC_IMX27
 const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
@@ -50,7 +50,7 @@ const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX27 */
 
-#ifdef CONFIG_ARCH_MX31
+#ifdef CONFIG_SOC_IMX31
 const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
 #define imx31_cspi_data_entry(_id, _hwid)                               \
         imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
@@ -58,18 +58,18 @@ const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
         imx31_cspi_data_entry(1, 2),
         imx31_cspi_data_entry(2, 3),
 };
-#endif /* ifdef CONFIG_ARCH_MX31 */
+#endif /* ifdef CONFIG_SOC_IMX31 */
 
-#ifdef CONFIG_ARCH_MX35
+#ifdef CONFIG_SOC_IMX35
 const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
 #define imx35_cspi_data_entry(_id, _hwid)                           \
         imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
         imx35_cspi_data_entry(0, 1),
         imx35_cspi_data_entry(1, 2),
 };
-#endif /* ifdef CONFIG_ARCH_MX35 */
+#endif /* ifdef CONFIG_SOC_IMX35 */
 
-#ifdef CONFIG_ARCH_MX51
+#ifdef CONFIG_SOC_IMX51
 const struct imx_spi_imx_data imx51_cspi_data __initconst =
         imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K);
 
@@ -79,7 +79,7 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
         imx51_ecspi_data_entry(0, 1),
         imx51_ecspi_data_entry(1, 2),
 };
-#endif /* ifdef CONFIG_ARCH_MX51 */
+#endif /* ifdef CONFIG_SOC_IMX51 */
 
 struct platform_device *__init imx_add_spi_imx(
                 const struct imx_spi_imx_data *data,
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 9915607683de..8772ce346a58 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -49,6 +49,7 @@
 
 #define MXC_OTG_OFFSET          0
 #define MXC_H1_OFFSET           0x200
+#define MXC_H2_OFFSET           0x400
 
 /* USB_CTRL */
 #define MXC_OTG_UCTRL_OWIE_BIT          (1 << 27)       /* OTG wakeup intr enable */
@@ -61,6 +62,11 @@
 #define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
 #define MXC_H1_OC_DIS_BIT                       (1 << 5)        /* UH1 Disable Overcurrent Event */
 
+/* USBH2CTRL */
+#define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
+#define MXC_H2_UCTRL_H2WIE_BIT          (1 << 7)
+#define MXC_H2_UCTRL_H2PM_BIT           (1 << 4)
+
 #define MXC_USBCMD_OFFSET                       0x140
 
 /* USBCMD */
@@ -69,9 +75,9 @@
 int mxc_initialize_usb_hw(int port, unsigned int flags)
 {
         unsigned int v;
-#if defined(CONFIG_ARCH_MX25)
+#if defined(CONFIG_SOC_IMX25)
         if (cpu_is_mx25()) {
-                v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+                v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
                                      USBCTRL_OTGBASE_OFFSET));
 
                 switch (port) {
@@ -108,14 +114,14 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                         return -EINVAL;
                 }
 
-                writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+                writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
                                      USBCTRL_OTGBASE_OFFSET));
                 return 0;
         }
-#endif /* CONFIG_ARCH_MX25 */
+#endif /* if defined(CONFIG_SOC_IMX25) */
 #if defined(CONFIG_ARCH_MX3)
         if (cpu_is_mx31()) {
-                v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
+                v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
                                      USBCTRL_OTGBASE_OFFSET));
 
                 switch (port) {
@@ -153,13 +159,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                         return -EINVAL;
                 }
 
-                writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
+                writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
                                      USBCTRL_OTGBASE_OFFSET));
                 return 0;
         }
 
         if (cpu_is_mx35()) {
-                v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
+                v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
                                      USBCTRL_OTGBASE_OFFSET));
 
                 switch (port) {
@@ -196,7 +202,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                         return -EINVAL;
                 }
 
-                writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR +
+                writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
                                      USBCTRL_OTGBASE_OFFSET));
                 return 0;
         }
@@ -206,7 +212,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                 /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
                  * are identical
                  */
-                v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
+                v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
                                      USBCTRL_OTGBASE_OFFSET));
                 switch (port) {
                 case 0: /* OTG port */
@@ -241,12 +247,12 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                 default:
                         return -EINVAL;
                 }
-                writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR +
+                writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
                                      USBCTRL_OTGBASE_OFFSET));
                 return 0;
         }
 #endif /* CONFIG_MACH_MX27 */
-#ifdef CONFIG_ARCH_MX51
+#ifdef CONFIG_SOC_IMX51
         if (cpu_is_mx51()) {
                 void __iomem *usb_base;
                 void __iomem *usbotg_base;
@@ -254,6 +260,10 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                 int ret = 0;
 
                 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+                if (!usb_base) {
+                        printk(KERN_ERR "%s(): ioremap failed\n", __func__);
+                        return -ENOMEM;
+                }
 
                 switch (port) {
                 case 0: /* OTG port */
@@ -262,6 +272,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                 case 1: /* Host 1 port */
                         usbotg_base = usb_base + MXC_H1_OFFSET;
                         break;
+                case 2: /* Host 2 port */
+                        usbotg_base = usb_base + MXC_H2_OFFSET;
+                        break;
                 default:
                         printk(KERN_ERR"%s no such port %d\n", __func__, port);
                         ret = -ENOENT;
@@ -274,10 +287,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                         if (flags & MXC_EHCI_INTERNAL_PHY) {
                                 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 
-                                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                        v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */
-                                else
-                                        v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */
+                                if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
+                                        /* OC/USBPWR is not used */
+                                        v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                                } else {
+                                        /* OC/USBPWR is used */
+                                        v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                                }
                                 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 
                                 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
@@ -285,16 +301,23 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                                         v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
                                 else
                                         v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
+                                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                        v |= MXC_OTG_UCTRL_OPM_BIT;
+                                else
+                                        v &= ~MXC_OTG_UCTRL_OPM_BIT;
                                 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
                         }
                         break;
                 case 1: /* Host 1 */
                         /*Host ULPI */
                         v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
-                        if (flags & MXC_EHCI_WAKEUP_ENABLED)
-                                v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
-                        else
-                                v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */
+                        if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                                /* HOST1 wakeup/ULPI intr enable */
+                                v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+                        } else {
+                                /* HOST1 wakeup/ULPI intr disable */
+                                v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
+                        }
 
                         if (flags & MXC_EHCI_POWER_PINS_ENABLED)
                                 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
@@ -315,6 +338,22 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
                                 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
                         __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
                         break;
+                case 2: /* Host 2 ULPI */
+                        v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
+                        if (flags & MXC_EHCI_WAKEUP_ENABLED) {
+                                /* HOST1 wakeup/ULPI intr enable */
+                                v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+                        } else {
+                                /* HOST1 wakeup/ULPI intr disable */
+                                v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
+                        }
+
+                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
+                                v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                        else
+                                v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                        __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
+                        break;
                 }
 
 error:
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
index ee9582f4972e..d69d343ff61f 100644
--- a/arch/arm/plat-mxc/epit.c
+++ b/arch/arm/plat-mxc/epit.c
@@ -93,7 +93,6 @@ static struct clocksource clocksource_epit = {
         .rating         = 200,
         .read           = epit_read,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -101,9 +100,7 @@ static int __init epit_clocksource_init(struct clk *timer_clk)
 {
         unsigned int c = clk_get_rate(timer_clk);
 
-        clocksource_epit.mult = clocksource_hz2mult(c,
-                                        clocksource_epit.shift);
-        clocksource_register(&clocksource_epit);
+        clocksource_register_hz(&clocksource_epit, c);
 
         return 0;
 }
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 9c3e36232b5b..bc2c7bc6f10a 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
         u32 irq_stat;
-        struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
+        struct mxc_gpio_port *port = get_irq_data(irq);
 
         irq_stat = __raw_readl(port->base + GPIO_ISR) &
                         __raw_readl(port->base + GPIO_IMR);
@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
         int i;
         u32 irq_msk, irq_stat;
-        struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
+        struct mxc_gpio_port *port = get_irq_data(irq);
 
         /* walk through all interrupt status registers */
         for (i = 0; i < gpio_table_size; i++) {
@@ -349,3 +349,113 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
 
         return 0;
 }
+
+#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
+        {                                                               \
+                .chip.label = "gpio-" #_id,                             \
+                .irq = _irq,                                            \
+                .irq_high = _irq_high,                                  \
+                .base = soc ## _IO_ADDRESS(                             \
+                                soc ## _GPIO ## _hwid ## _BASE_ADDR),   \
+                .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32,   \
+        }
+
+#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq)                 \
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
+#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid)                           \
+        DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
+
+#define DEFINE_REGISTER_FUNCTION(prefix)                                \
+int __init prefix ## _register_gpios(void)                              \
+{                                                                       \
+        return mxc_gpio_init(prefix ## _gpio_ports,                     \
+                        ARRAY_SIZE(prefix ## _gpio_ports));             \
+}
+
+#if defined(CONFIG_SOC_IMX1)
+static struct mxc_gpio_port imx1_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
+};
+
+DEFINE_REGISTER_FUNCTION(imx1)
+
+#endif /* if defined(CONFIG_SOC_IMX1) */
+
+#if defined(CONFIG_SOC_IMX21)
+static struct mxc_gpio_port imx21_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
+        DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
+        DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
+        DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
+        DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
+        DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
+};
+
+DEFINE_REGISTER_FUNCTION(imx21)
+
+#endif /* if defined(CONFIG_SOC_IMX21) */
+
+#if defined(CONFIG_SOC_IMX25)
+static struct mxc_gpio_port imx25_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
+};
+
+DEFINE_REGISTER_FUNCTION(imx25)
+
+#endif /* if defined(CONFIG_SOC_IMX25) */
+
+#if defined(CONFIG_SOC_IMX27)
+static struct mxc_gpio_port imx27_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
+        DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
+        DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
+        DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
+        DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
+        DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
+};
+
+DEFINE_REGISTER_FUNCTION(imx27)
+
+#endif /* if defined(CONFIG_SOC_IMX27) */
+
+#if defined(CONFIG_SOC_IMX31)
+static struct mxc_gpio_port imx31_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
+};
+
+DEFINE_REGISTER_FUNCTION(imx31)
+
+#endif /* if defined(CONFIG_SOC_IMX31) */
+
+#if defined(CONFIG_SOC_IMX35)
+static struct mxc_gpio_port imx35_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
+        DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
+};
+
+DEFINE_REGISTER_FUNCTION(imx35)
+
+#endif /* if defined(CONFIG_SOC_IMX35) */
+
+#if defined(CONFIG_SOC_IMX50)
+static struct mxc_gpio_port imx50_gpio_ports[] = {
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+        DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
+};
+
+DEFINE_REGISTER_FUNCTION(imx50)
+
+#endif /* if defined(CONFIG_SOC_IMX50) */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7a1e1f89ff09..aea2cd3b6d15 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -20,7 +20,9 @@ extern void mx25_map_io(void);
 extern void mx27_map_io(void);
 extern void mx31_map_io(void);
 extern void mx35_map_io(void);
+extern void mx50_map_io(void);
 extern void mx51_map_io(void);
+extern void mx53_map_io(void);
 extern void mxc91231_map_io(void);
 extern void mxc_init_irq(void __iomem *);
 extern void tzic_init_irq(void __iomem *);
@@ -30,7 +32,9 @@ extern void mx25_init_irq(void);
 extern void mx27_init_irq(void);
 extern void mx31_init_irq(void);
 extern void mx35_init_irq(void);
+extern void mx50_init_irq(void);
 extern void mx51_init_irq(void);
+extern void mx53_init_irq(void);
 extern void mxc91231_init_irq(void);
 extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
 extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
@@ -42,6 +46,8 @@ extern int mx31_clocks_init(unsigned long fref);
 extern int mx35_clocks_init(void);
 extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
+extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
+                        unsigned long ckih1, unsigned long ckih2);
 extern int mxc91231_clocks_init(unsigned long fref);
 extern int mxc_register_gpios(void);
 extern int mxc_register_device(struct platform_device *pdev, void *data);
@@ -50,5 +56,6 @@ extern void mxc_arch_reset_init(void __iomem *);
 extern void mxc91231_power_off(void);
 extern void mxc91231_arch_reset(int, const char *);
 extern void mxc91231_prepare_idle(void);
-
+extern void mx51_efikamx_reset(void);
+extern int mx53_revision(void);
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index d56213fb901b..3b3a37c25c56 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -10,58 +10,49 @@
  * published by the Free Software Foundation.
  *
  */
-#define IMX_NEEDS_DEPRECATED_SYMBOLS
+#include <mach/hardware.h>
 
 #ifdef CONFIG_ARCH_MX1
-#include <mach/mx1.h>
-#define UART_PADDR      UART1_BASE_ADDR
-#define UART_VADDR      IO_ADDRESS(UART1_BASE_ADDR)
+#define UART_PADDR      MX1_UART1_BASE_ADDR
 #endif
 
 #ifdef CONFIG_ARCH_MX25
 #ifdef UART_PADDR
 #error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#include <mach/mx25.h>
 #define UART_PADDR      MX25_UART1_BASE_ADDR
-#define UART_VADDR      MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR)
 #endif
 
 #ifdef CONFIG_ARCH_MX2
 #ifdef UART_PADDR
 #error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#include <mach/mx2x.h>
-#define UART_PADDR      UART1_BASE_ADDR
-#define UART_VADDR      AIPI_IO_ADDRESS(UART1_BASE_ADDR)
+#define UART_PADDR      MX2x_UART1_BASE_ADDR
 #endif
 
 #ifdef CONFIG_ARCH_MX3
 #ifdef UART_PADDR
 #error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#include <mach/mx3x.h>
-#define UART_PADDR      UART1_BASE_ADDR
-#define UART_VADDR      AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#define UART_PADDR      MX3x_UART1_BASE_ADDR
 #endif
 
 #ifdef CONFIG_ARCH_MX5
 #ifdef UART_PADDR
 #error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#include <mach/mx51.h>
 #define UART_PADDR      MX51_UART1_BASE_ADDR
-#define UART_VADDR      MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
 #endif
 
 #ifdef CONFIG_ARCH_MXC91231
 #ifdef UART_PADDR
 #error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#include <mach/mxc91231.h>
 #define UART_PADDR      MXC91231_UART2_BASE_ADDR
-#define UART_VADDR      MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
 #endif
+
+#define UART_VADDR      IMX_IO_ADDRESS(UART_PADDR)
+
                 .macro  addruart, rp, rv
                 ldr     \rp, =UART_PADDR        @ physical
                 ldr     \rv, =UART_VADDR        @ virtual
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 8c6896fd1e5f..8658c9caa650 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -10,9 +10,19 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 
-struct platform_device *imx_add_platform_device(const char *name, int id,
+struct platform_device *imx_add_platform_device_dmamask(
+                const char *name, int id,
                 const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data);
+                const void *data, size_t size_data, u64 dmamask);
+
+static inline struct platform_device *imx_add_platform_device(
+                const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data)
+{
+        return imx_add_platform_device_dmamask(
+                        name, id, res, num_resources, data, size_data, 0);
+}
 
 #include <linux/fec.h>
 struct imx_fec_data {
@@ -24,15 +34,63 @@ struct platform_device *__init imx_add_fec(
                 const struct fec_platform_data *pdata);
 
 #include <linux/can/platform/flexcan.h>
-struct platform_device *__init imx_add_flexcan(int id,
-                resource_size_t iobase, resource_size_t iosize,
-                resource_size_t irq,
+struct imx_flexcan_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_flexcan(
+                const struct imx_flexcan_data *data,
                 const struct flexcan_platform_data *pdata);
 
+#include <linux/fsl_devices.h>
+struct imx_fsl_usb2_udc_data {
+        resource_size_t iobase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_fsl_usb2_udc(
+                const struct imx_fsl_usb2_udc_data *data,
+                const struct fsl_usb2_platform_data *pdata);
+
 #include <linux/gpio_keys.h>
 struct platform_device *__init imx_add_gpio_keys(
                 const struct gpio_keys_platform_data *pdata);
 
+#include <mach/mx21-usbhost.h>
+struct imx_imx21_hcd_data {
+        resource_size_t iobase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx21_hcd(
+                const struct imx_imx21_hcd_data *data,
+                const struct mx21_usbh_platform_data *pdata);
+
+struct imx_imx2_wdt_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+};
+struct platform_device *__init imx_add_imx2_wdt(
+                const struct imx_imx2_wdt_data *data);
+
+struct imx_imxdi_rtc_data {
+        resource_size_t iobase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imxdi_rtc(
+                const struct imx_imxdi_rtc_data *data);
+
+#include <mach/imxfb.h>
+struct imx_imx_fb_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx_fb(
+                const struct imx_imx_fb_data *data,
+                const struct imx_fb_platform_data *pdata);
+
 #include <mach/i2c.h>
 struct imx_imx_i2c_data {
         int id;
@@ -44,6 +102,16 @@ struct platform_device *__init imx_add_imx_i2c(
                 const struct imx_imx_i2c_data *data,
                 const struct imxi2c_platform_data *pdata);
 
+#include <linux/input/matrix_keypad.h>
+struct imx_imx_keypad_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx_keypad(
+                const struct imx_imx_keypad_data *data,
+                const struct matrix_keymap_data *pdata);
+
 #include <mach/ssi.h>
 struct imx_imx_ssi_data {
         int id;
@@ -82,6 +150,67 @@ struct platform_device *__init imx_add_imx_uart_1irq(
                 const struct imx_imx_uart_1irq_data *data,
                 const struct imxuart_platform_data *pdata);
 
+#include <mach/usb.h>
+struct imx_imx_udc_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq0;
+        resource_size_t irq1;
+        resource_size_t irq2;
+        resource_size_t irq3;
+        resource_size_t irq4;
+        resource_size_t irq5;
+        resource_size_t irq6;
+};
+struct platform_device *__init imx_add_imx_udc(
+                const struct imx_imx_udc_data *data,
+                const struct imxusb_platform_data *pdata);
+
+#include <mach/mx1_camera.h>
+struct imx_mx1_camera_data {
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_mx1_camera(
+                const struct imx_mx1_camera_data *data,
+                const struct mx1_camera_pdata *pdata);
+
+#include <mach/mx2_cam.h>
+struct imx_mx2_camera_data {
+        resource_size_t iobasecsi;
+        resource_size_t iosizecsi;
+        resource_size_t irqcsi;
+        resource_size_t iobaseemmaprp;
+        resource_size_t iosizeemmaprp;
+        resource_size_t irqemmaprp;
+};
+struct platform_device *__init imx_add_mx2_camera(
+                const struct imx_mx2_camera_data *data,
+                const struct mx2_camera_platform_data *pdata);
+
+#include <mach/mxc_ehci.h>
+struct imx_mxc_ehci_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t irq;
+};
+struct platform_device *__init imx_add_mxc_ehci(
+                const struct imx_mxc_ehci_data *data,
+                const struct mxc_usbh_platform_data *pdata);
+
+#include <mach/mmc.h>
+struct imx_mxc_mmc_data {
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        resource_size_t irq;
+        resource_size_t dmareq;
+};
+struct platform_device *__init imx_add_mxc_mmc(
+                const struct imx_mxc_mmc_data *data,
+                const struct imxmmc_platform_data *pdata);
+
 #include <mach/mxc_nand.h>
 struct imx_mxc_nand_data {
         /*
@@ -99,24 +228,39 @@ struct platform_device *__init imx_add_mxc_nand(
                 const struct imx_mxc_nand_data *data,
                 const struct mxc_nand_platform_data *pdata);
 
-#include <mach/spi.h>
-struct imx_spi_imx_data {
-        const char *devid;
+struct imx_mxc_pwm_data {
         int id;
         resource_size_t iobase;
         resource_size_t iosize;
-        int irq;
+        resource_size_t irq;
 };
-struct platform_device *__init imx_add_spi_imx(
-                const struct imx_spi_imx_data *data,
-                const struct spi_imx_master *pdata);
+struct platform_device *__init imx_add_mxc_pwm(
+                const struct imx_mxc_pwm_data *data);
+
+struct imx_mxc_w1_data {
+        resource_size_t iobase;
+};
+struct platform_device *__init imx_add_mxc_w1(
+                const struct imx_mxc_w1_data *data);
 
 #include <mach/esdhc.h>
-struct imx_esdhc_imx_data {
+struct imx_sdhci_esdhc_imx_data {
         int id;
         resource_size_t iobase;
         resource_size_t irq;
 };
-struct platform_device *__init imx_add_esdhc(
-                const struct imx_esdhc_imx_data *data,
+struct platform_device *__init imx_add_sdhci_esdhc_imx(
+                const struct imx_sdhci_esdhc_imx_data *data,
                 const struct esdhc_platform_data *pdata);
+
+#include <mach/spi.h>
+struct imx_spi_imx_data {
+        const char *devid;
+        int id;
+        resource_size_t iobase;
+        resource_size_t iosize;
+        int irq;
+};
+struct platform_device *__init imx_add_spi_imx(
+                const struct imx_spi_imx_data *data,
+                const struct spi_imx_master *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index aeb08697726b..bd9bb9799141 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -54,15 +54,15 @@
 #elif defined CONFIG_MXC_TZIC
         @ Load offset & priority of the highest priority
         @ interrupt pending.
+        @ 0x080 is INTSEC0 register
         @ 0xD80 is HIPND0 register
         mov     \irqnr, #0
-        mov     \irqstat, #0x0D80
-1000:
-        ldr     \tmp,   [\irqstat, \base]
-        cmp     \tmp, #0
-        bne     1001f
-        addeq   \irqnr, \irqnr, #32
-        addeq   \irqstat, \irqstat, #4
+1000:   add     \irqstat, \base, \irqnr, lsr #3
+        ldr     \tmp, [\irqstat, #0xd80]
+        ldr     \irqstat, [\irqstat, #0x080]
+        ands    \tmp, \tmp, \irqstat
+        bne     1001f
+        add     \irqnr, \irqnr, #32
         cmp     \irqnr, #128
         blo     1000b
         b       2001f
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index af33b74f569e..0044e2f1bea8 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -23,6 +23,11 @@
 #include <mach/hardware.h>
 #include <asm-generic/gpio.h>
 
+
+/* There's a off-by-one betweem the gpio bank number and the gpiochip */
+/* range e.g. GPIO_1_5 is gpio 5 under linux */
+#define IMX_GPIO_NR(bank, nr)           (((bank) - 1) * 32 + (nr))
+
 /* use gpiolib dispatchers */
 #define gpio_get_value          __gpio_get_value
 #define gpio_set_value          __gpio_set_value
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index ebadf4ac43fc..26bb1bab4aeb 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -22,13 +22,92 @@
 
 #include <asm/sizes.h>
 
-#define IMX_IO_ADDRESS(addr, module)                                    \
-        ((void __force __iomem *)                                       \
-         (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\
-         (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0))
+#ifdef __ASSEMBLER__
+#define IOMEM(addr)     (addr)
+#else
+#define IOMEM(addr)     ((void __force __iomem *)(addr))
+#endif
+
+#define IMX_IO_P2V_MODULE(addr, module)                                 \
+        (((addr) - module ## _BASE_ADDR) < module ## _SIZE ?            \
+         (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
+
+/*
+ * This is rather complicated for humans and ugly to verify, but for a machine
+ * it's OK.  Still more as it is usually only applied to constants.  The upsides
+ * on using this approach are:
+ *
+ *  - same mapping on all i.MX machines
+ *  - works for assembler, too
+ *  - no need to nurture #defines for virtual addresses
+ *
+ * The downside it, it's hard to verify (but I have a script for that).
+ *
+ * Obviously this needs to be injective for each SoC.  In general it maps the
+ * whole address space to [0xf4000000, 0xf5ffffff].  So [0xf6000000,0xfeffffff]
+ * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
+ *
+ * It applies the following mappings for the different SoCs:
+ *
+ * mx1:
+ *      IO      0x00200000+0x100000     ->      0xf4000000+0x100000
+ * mx21:
+ *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
+ *      SAHB1   0x80000000+0x100000     ->      0xf4000000+0x100000
+ *      X_MEMC  0xdf000000+0x004000     ->      0xf5f00000+0x004000
+ * mx25:
+ *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
+ *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
+ * mx27:
+ *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
+ *      SAHB1   0x80000000+0x100000     ->      0xf4000000+0x100000
+ *      X_MEMC  0xd8000000+0x100000     ->      0xf5c00000+0x100000
+ * mx31:
+ *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
+ *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
+ * mx35:
+ *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
+ *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
+ * mx50:
+ *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
+ *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
+ * mx51:
+ *      IRAM    0x1ffe0000+0x020000     ->      0xf4fe0000+0x020000
+ *      DEBUG   0x60000000+0x100000     ->      0xf5000000+0x100000
+ *      SPBA0   0x70000000+0x100000     ->      0xf5400000+0x100000
+ *      AIPS1   0x73f00000+0x100000     ->      0xf5700000+0x100000
+ *      AIPS2   0x83f00000+0x100000     ->      0xf4300000+0x100000
+ * mxc91231:
+ *      L2CC    0x30000000+0x010000     ->      0xf4400000+0x010000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      ROMP    0x60000000+0x010000     ->      0xf5000000+0x010000
+ *      AVIC    0x68000000+0x010000     ->      0xf5800000+0x010000
+ *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
+ *      SPBA1   0x52000000+0x100000     ->      0xf5600000+0x100000
+ *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ */
+#define IMX_IO_P2V(x)   (                                               \
+                        0xf4000000 +                                    \
+                        (((x) & 0x50000000) >> 6) +                     \
+                        (((x) & 0x0b000000) >> 4) +                     \
+                        (((x) & 0x000fffff)))
+
+#define IMX_IO_ADDRESS(x)       IOMEM(IMX_IO_P2V(x))
 
 #ifdef CONFIG_ARCH_MX5
+#include <mach/mx50.h>
 #include <mach/mx51.h>
+#include <mach/mx53.h>
 #endif
 
 #ifdef CONFIG_ARCH_MX3
@@ -61,4 +140,11 @@
 
 #include <mach/mxc.h>
 
+#define imx_map_entry(soc, name, _type) {                               \
+        .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
+        .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),           \
+        .length = soc ## _ ## name ## _SIZE,                            \
+        .type = _type,                                                  \
+}
+
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 5263506b7ddf..9de8f062ad5d 100644
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -1,6 +1,8 @@
 /*
  * This structure describes the machine which we are running on.
  */
+#ifndef __MACH_IMXFB_H__
+#define __MACH_IMXFB_H__
 
 #include <linux/fb.h>
 
@@ -79,3 +81,4 @@ struct imx_fb_platform_data {
 };
 
 void set_imx_fb_info(struct imx_fb_platform_data *);
+#endif /* ifndef __MACH_IMXFB_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
new file mode 100644
index 000000000000..058a922ca147
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
@@ -0,0 +1,977 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_IOMUX_MX50_H__
+#define __MACH_IOMUX_MX50_H__
+
+#include <mach/iomux-v3.h>
+
+#define MX50_ELCDIF_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
+
+#define MX50_SD_PAD_CTRL        (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+                                        PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
+
+#define MX50_UART_PAD_CTRL      (PAD_CTL_DSE_HIGH | PAD_CTL_PKE)
+
+#define MX50_I2C_PAD_CTRL       (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \
+                                        PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
+
+#define MX50_USB_PAD_CTRL       (PAD_CTL_PKE | PAD_CTL_PUE | \
+                                        PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
+
+#define MX50_FEC_PAD_CTRL       (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+                                        PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \
+                                        PAD_CTL_DSE_HIGH)
+
+#define MX50_OWIRE_PAD_CTRL     (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+                                        PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \
+                                        PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+
+#define MX50_KEYPAD_CTRL        (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+                                        PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH)
+
+#define MX50_CSPI_SS_PAD        (PAD_CTL_PKE | PAD_CTL_PUE | \
+                                        PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_KEY_COL0__KEY_COL0     IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_COL0__GPIO_4_0     IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_COL0__NANDF_CLE    IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_KEY_ROW0__KEY_ROW0     IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL)
+#define MX50_PAD_KEY_ROW0__GPIO_4_1     IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_ROW0__NANDF_ALE    IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_KEY_COL1__KEY_COL1     IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_COL1__GPIO_4_2     IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_COL1__NANDF_CE0    IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_KEY_ROW1__KEY_ROW1     IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
+#define MX50_PAD_KEY_ROW1__GPIO_4_3     IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_ROW1__NANDF_CE1    IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_KEY_COL2__KEY_COL2     IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL)
+#define MX50_PAD_KEY_COL2__GPIO_4_4     IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_COL2__NANDF_CE2    IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_KEY_ROW2__KEY_ROW2     IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL)
+#define MX50_PAD_KEY_ROW2__GPIO_4_5     IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_ROW2__NANDF_CE3    IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_KEY_COL3__KEY_COL3     IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_COL3__GPIO_4_6     IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_COL3__NANDF_READY  IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \
+                                                        PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define MX50_PAD_KEY_COL3__SDMA_EXT0    IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_KEY_ROW3__KEY_ROW3     IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
+#define MX50_PAD_KEY_ROW3__GPIO_4_7     IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_KEY_ROW3__NANDF_DQS    IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_KEY_ROW3__SDMA_EXT1    IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_I2C1_SCL__I2C1_SCL     IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C1_SCL__GPIO_6_18    IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C1_SCL__UART2_TXD    IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL)
+
+#define MX50_PAD_I2C1_SDA__I2C1_SDA     IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C1_SDA__GPIO_6_19    IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C1_SDA__UART2_RXD    IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL)
+
+#define MX50_PAD_I2C2_SCL__I2C2_SCL     IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C2_SCL__GPIO_6_20    IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C2_SCL__UART2_CTS    IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_I2C2_SCL__DCDC_OK      IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_I2C2_SDA__I2C2_SDA     IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C2_SDA__GPIO_6_21    IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C2_SDA__UART2_RTS    IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_I2C2_SDA__PWRSTABLE    IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_I2C3_SCL__I2C3_SCL     IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                        MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C3_SCL__GPIO_6_22    IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C3_SCL__FEC_MDC      IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_I2C3_SCL__PMIC_RDY     IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C3_SCL__GPT_CAPIN1   IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C3_SCL__USBOTG_OC    IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL)
+
+#define MX50_PAD_I2C3_SDA__I2C3_SDA     IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \
+                                                                MX50_I2C_PAD_CTRL)
+#define MX50_PAD_I2C3_SDA__GPIO_6_23    IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C3_SDA__FEC_MDIO     IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL)
+#define MX50_PAD_I2C3_SDA__PWRFAIL_INT  IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C3_SDA__ALARM_DEB    IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C3_SDA__GPT_CAPIN1   IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_I2C3_SDA__USBOTG_PWR   IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \
+                                                        PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_PWM1__PWM1_PWMO        IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PWM1__GPIO_6_24        IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PWM1__USBOTG_OC        IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL)
+#define MX50_PAD_PWM1__GPT_CMPOUT1      IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PWM2__PWM2_PWMO        IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PWM2__GPIO_6_25        IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PWM2__USBOTG_PWR       IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \
+                                                        PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
+#define MX50_PAD_PWM2__DCDC_PWM         IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PWM2__GPT_CMPOUT2      IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_PWM2__ANY_PU_RST       IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_OWIRE__OWIRE           IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL)
+#define MX50_PAD_OWIRE__GPIO_6_26       IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_OWIRE__USBH1_OC        IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL)
+#define MX50_PAD_OWIRE__SSI_EXT1_CLK    IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_OWIRE__EPDC_PWRIRQ     IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_OWIRE__GPT_CMPOUT3     IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPITO__EPITO           IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPITO__GPIO_6_27       IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPITO__USBH1_PWR       IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \
+                                                        PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
+#define MX50_PAD_EPITO__SSI_EXT2_CLK    IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPITO__TOG_EN          IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPITO__GPT_CLKIN       IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_WDOG__WDOG             IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_WDOG__GPIO_6_28        IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_WDOG__WDOG_RST         IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_WDOG__XTAL32K          IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SSI_TXFS__SSI_TXFS     IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_TXFS__GPIO_6_0     IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SSI_TXC__SSI_TXC       IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_TXC__GPIO_6_1      IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SSI_TXD__SSI_TXD       IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_TXD__GPIO_6_2      IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_TXD__CSPI_RDY      IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SSI_RXD__SSI_RXD       IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXD__GPIO_6_3      IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXD__CSPI_SS3      IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD)
+
+#define MX50_PAD_SSI_RXFS__AUD3_RXFS    IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXFS__GPIO_6_4     IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXFS__UART5_TXD    IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_SSI_RXFS__WEIM_D6      IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXFS__CSPI_SS2     IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_SSI_RXFS__FEC_COL      IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SSI_RXFS__FEC_MDC      IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_SSI_RXC__AUD3_RXC      IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXC__GPIO_6_5      IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXC__UART5_RXD     IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_SSI_RXC__WEIM_D7       IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXC__CSPI_SS1      IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_SSI_RXC__FEC_RX_CLK    IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
+#define MX50_PAD_SSI_RXC__FEC_MDIO      IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
+
+#define MX50_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_TXD__GPIO_6_6    IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_RXD__GPIO_6_7    IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_CTS__GPIO_6_8    IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART1_CTS__UART5_TXD   IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_CTS__SD4_D4      IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART1_CTS__SD4_CMD     IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
+
+#define MX50_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_RTS__GPIO_6_9    IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART1_RTS__UART5_RXD   IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART1_RTS__SD4_D5      IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART1_RTS__SD4_CLK     IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL)
+
+#define MX50_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_TXD__GPIO_6_10   IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART2_TXD__SD4_D6      IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART2_TXD__SD4_D4      IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
+
+#define MX50_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_RXD__GPIO_6_11   IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART2_RXD__SD4_D7      IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART2_RXD__SD4_D5      IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
+
+#define MX50_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_CTS__GPIO_6_12   IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART2_CTS__SD4_CMD     IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART2_CTS__SD4_D6      IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
+
+#define MX50_PAD_UART2_RTS__UART2_RTS   IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART2_RTS__GPIO_6_13   IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART2_RTS__SD4_CLK     IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART2_RTS__SD4_D7      IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
+
+#define MX50_PAD_UART3_TXD__UART3_TXD   IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART3_TXD__GPIO_6_14   IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART3_TXD__SD1_D4      IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART3_TXD__SD4_D0      IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART3_TXD__SD2_WP      IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART3_TXD__WEIM_D12    IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_UART3_RXD__UART3_RXD   IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART3_RXD__GPIO_6_15   IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART3_RXD__SD1_D5      IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART3_RXD__SD4_D1      IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART3_RXD__SD2_CD      IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART3_RXD__WEIM_D13    IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_UART4_TXD__UART4_TXD   IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__GPIO_6_16   IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__UART3_CTS   IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__SD1_D6      IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__SD4_D2      IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__SD2_LCTL    IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART4_TXD__WEIM_D14    IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_UART4_RXD__UART4_RXD   IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART4_RXD__GPIO_6_17   IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_UART4_RXD__UART3_RTS   IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_UART4_RXD__SD1_D7      IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART4_RXD__SD4_D3      IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART4_RXD__SD1_LCTL    IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_UART4_RXD__WEIM_D15    IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_CSPI_SCLK__CSPI_SCLK   IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_CSPI_SCLK__GPIO_4_8    IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_CSPI_MOSI__CSPI_MOSI   IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_CSPI_MOSI__GPIO_4_9    IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_CSPI_MISO__CSPI_MISO   IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_CSPI_MISO__GPIO_4_10   IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_CSPI_SS0__CSPI_SS0     IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_CSPI_SS0__GPIO_4_11    IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK       IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12         IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY          IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY        IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SCLK__UART3_RTS         IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6        IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SCLK__WEIM_D8           IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI       IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13         IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1          IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1        IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI1_MOSI__UART3_CTS         IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7        IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MOSI__WEIM_D9           IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO       IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MISO__GPIO_4_14         IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MISO__CSPI_SS2          IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2        IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI1_MISO__UART4_RTS         IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8        IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_MISO__WEIM_D10          IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0         IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI1_SS0__GPIO_4_15          IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
+#define MX50_PAD_ECSPI1_SS0__CSPI_SS3           IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3         IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI1_SS0__UART4_CTS          IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9         IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI1_SS0__WEIM_D11           IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK       IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16         IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR         IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY        IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SCLK__UART5_RTS         IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK     IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4        IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SCLK__WEIM_D8           IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI       IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17         IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD         IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1        IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI2_MOSI__UART5_CTS         IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN         IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5        IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MOSI__WEIM_D9           IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO       IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__GPIO_4_18         IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
+#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS         IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2        IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI2_MISO__UART5_TXD         IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC      IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6        IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_MISO__WEIM_D10          IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0         IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI2_SS0__GPIO_4_19          IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS          IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3         IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
+#define MX50_PAD_ECSPI2_SS0__UART5_RXD          IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC       IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7         IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_ECSPI2_SS0__WEIM_D11           IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_CLK__GPIO_5_0      IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_CLK__CLKO          IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_CMD__GPIO_5_1      IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_CMD__CLKO2         IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD1_D0__SD1_D0         IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_D0__GPIO_5_2       IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_D0__PLL1_BYP       IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD1_D1__SD1_D1         IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_D1__GPIO_5_3       IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_D1__PLL2_BYP       IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD1_D2__SD1_D2         IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_D2__GPIO_5_4       IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD1_D2__PLL3_BYP       IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD1_D3__SD1_D3         IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD1_D3__GPIO_5_5       IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD2_CLK__SD2_CLK       IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_CLK__GPIO_5_6      IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_CLK__MSHC_SCLK     IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL)
+
+#define MX50_PAD_SD2_CMD__SD2_CMD       IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_CMD__GPIO_5_7      IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_CMD__MSHC_BS       IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL)
+
+#define MX50_PAD_SD2_D0__SD2_D0         IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D0__GPIO_5_8       IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D0__MSHC_D0        IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D0__KEY_COL4       IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD2_D1__SD2_D1         IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D1__GPIO_5_9       IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D1__MSHC_D1        IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D1__KEY_ROW4       IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD2_D2__SD2_D2         IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D2__GPIO_5_10      IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D2__MSHC_D2        IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D2__KEY_COL5       IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD2_D3__SD2_D3         IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D3__GPIO_5_11      IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D3__MSHC_D3        IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D3__KEY_ROW5       IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD2_D4__SD2_D4         IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D4__GPIO_5_12      IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D4__AUD4_RXFS      IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D4__KEY_COL6       IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D4__WEIM_D0        IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D4__CCM_OUT0       IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD2_D5__SD2_D5         IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D5__GPIO_5_13      IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D5__AUD4_RXC       IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D5__KEY_ROW6       IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D5__WEIM_D1        IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D5__CCM_OUT1       IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD2_D6__SD2_D6         IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D6__GPIO_5_14      IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D6__AUD4_RXD       IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D6__KEY_COL7       IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D6__WEIM_D2        IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D6__CCM_OUT2       IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD2_D7__SD2_D7         IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_D7__GPIO_5_15      IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D7__AUD4_TXFS      IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D7__KEY_ROW7       IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D7__WEIM_D3        IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_D7__CCM_STOP       IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD2_WP__SD2_WP         IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_WP__GPIO_5_16      IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_WP__AUD4_TXD       IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_WP__WEIM_D4        IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_WP__CCM_WAIT       IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD2_CD__SD2_CD         IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD2_CD__GPIO_5_17      IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_CD__AUD4_TXC       IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_CD__WEIM_D5        IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD2_CD__CCM_REF_EN     IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ       IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ   IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B       IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1       IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B       IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0       IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS   IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD   IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB       IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI   IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK   IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO   IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D0__DISP_D0       IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D0__GPIO_2_0      IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D0__FEC_TXCLK     IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE)
+
+#define MX50_PAD_DISP_D1__DISP_D1       IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D1__GPIO_2_1      IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D1__FEC_RX_ER     IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX50_PAD_DISP_D1__WEIM_A17      IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D2__DISP_D2       IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D2__GPIO_2_2      IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D2__FEC_RX_DV     IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX50_PAD_DISP_D2__WEIM_A18      IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D3__DISP_D3       IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D3__GPIO_2_3      IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D3__FEC_RXD1      IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX50_PAD_DISP_D3__WEIM_A19      IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D3__FEC_COL       IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D4__DISP_D4       IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D4__GPIO_2_4      IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D4__FEC_RXD0      IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE)
+#define MX50_PAD_DISP_D4__WEIM_A20      IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D5__DISP_D5       IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D5__GPIO_2_5      IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D5__FEC_TX_EN     IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_DISP_D5__WEIM_A21      IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D6__DISP_D6       IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D6__GPIO_2_6      IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D6__FEC_TXD1      IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_DISP_D6__WEIM_A22      IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D6__FEC_RX_CLK    IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D7__DISP_D7       IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D7__GPIO_2_7      IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D7__FEC_TXD0      IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_DISP_D7__WEIM_A23      IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
+
+
+#define MX50_PAD_DISP_WR__ELCDIF_WR     IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_WR__GPIO_2_16     IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_WR__WEIM_A24      IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_RD__ELCDIF_RD     IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_RD__GPIO_2_19     IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_RD__ELCDIF_EN     IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_RD__WEIM_A25      IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_RS__ELCDIF_RS     IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_RS__GPIO_2_17     IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_RS__ELCDIF_VSYNC  IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_RS__WEIM_A26      IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_CS__ELCDIF_CS     IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_CS__GPIO_2_21     IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_CS__ELCDIF_HSYNC  IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_CS__WEIM_A27      IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_CS__WEIM_CS3      IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC        IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_BUSY__GPIO_2_18           IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_BUSY__WEIM_CS3            IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_RESET__GPIO_2_20  IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_RESET__WEIM_CS3   IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_CMD__SD3_CMD       IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_CMD__GPIO_5_18     IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_CMD__NANDF_WRN     IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_CMD__SSP_CMD       IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_CLK__SD3_CLK       IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_CLK__GPIO_5_19     IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_CLK__NANDF_RDN     IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_CLK__SSP_CLK       IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_D0__SD3_D0         IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_D0__GPIO_5_20      IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_D0__NANDF_D4       IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_D0__SSP_D0         IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_D0__PLL1_BYP       IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_D1__SD3_D1         IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_D1__GPIO_5_21      IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_D1__NANDF_D5       IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_D1__PLL2_BYP       IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_D2__SD3_D2         IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_D2__GPIO_5_22      IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_D2__NANDF_D6       IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_D2__SSP_D2         IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_D2__PLL3_BYP       IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_D3__SD3_D3         IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_D3__GPIO_5_23      IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_D3__NANDF_D7       IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_D3__SSP_D3         IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_D4__SD3_D4         IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_D4__GPIO_5_24      IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_D4__NANDF_D0       IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_D4__SSP_D4         IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_D5__SD3_D5         IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_D5__GPIO_5_25      IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_D5__NANDF_D1       IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_D5__SSP_D5         IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_D6__SD3_D6         IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_D6__GPIO_5_26      IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_D6__NANDF_D2       IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_D6__SSP_D6         IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_D7__SD3_D7         IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_D7__GPIO_5_27      IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_D7__NANDF_D3       IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_D7__SSP_D7         IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_SD3_WP__SD3_WP         IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_WP__GPIO_5_28      IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_SD3_WP__NANDF_RESETN   IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_SD3_WP__SSP_CD         IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_SD3_WP__SD4_LCTL       IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_SD3_WP__WEIM_CS3       IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D8__DISP_D8       IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D8__GPIO_2_8      IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D8__NANDF_CLE     IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D8__SD1_LCTL      IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D8__SD4_CMD       IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D8__KEY_COL4      IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D8__FEC_TX_CLK    IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D9__DISP_D9       IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D9__GPIO_2_9      IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D9__NANDF_ALE     IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D9__SD2_LCTL      IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D9__SD4_CLK       IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D9__KEY_ROW4      IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D9__FEC_RX_ER     IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D10__DISP_D10     IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D10__GPIO_2_10    IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D10__NANDF_CEN0   IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D10__SD3_LCTL     IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D10__SD4_D0       IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D10__KEY_COL5     IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D10__FEC_RX_DV    IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D11__DISP_D11     IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D11__GPIO_2_11    IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D11__NANDF_CEN1   IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D11__SD4_D1       IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D11__KEY_ROW5     IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D11__FEC_RDAT1    IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D12__DISP_D12     IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D12__GPIO_2_12    IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D12__NANDF_CEN2   IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D12__SD1_CD       IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D12__SD4_D2       IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D12__KEY_COL6     IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D12__FEC_RDAT0    IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D13__DISP_D13     IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D13__GPIO_2_13    IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D13__NANDF_CEN3   IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D13__SD3_CD       IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D13__SD4_D3       IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D13__KEY_ROW6     IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D13__FEC_TX_EN    IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D14__DISP_D14     IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D14__GPIO_2_14    IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D14__NANDF_RDY0   IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D14__SD1_WP       IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D14__SD4_WP       IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D14__KEY_COL7     IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D14__FEC_TDAT1    IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_DISP_D15__DISP_D15     IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_DISP_D15__GPIO_2_15    IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D15__NANDF_DQS    IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D15__SD3_RST      IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D15__SD4_CD       IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL)
+#define MX50_PAD_DISP_D15__KEY_ROW7     IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL)
+#define MX50_PAD_DISP_D15__FEC_TDAT0    IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D0__EPDC_D0       IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D0__GPIO_3_0      IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D0__WEIM_D0       IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D0__ELCDIF_RS     IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D1__EPDC_D1       IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D1__GPIO_3_1      IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D1__WEIM_D1       IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D1__ELCDIF_CS     IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_D1__ELCDIF_EN     IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D2__EPDC_D2       IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D2__GPIO_3_2      IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D2__WEIM_D2       IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D2__ELCDIF_WR     IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC  IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D3__EPDC_D3       IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D3__GPIO_3_3      IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D3__WEIM_D3       IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D3__ELCDIF_RD     IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC  IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D4__EPDC_D4       IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D4__GPIO_3_4      IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D4__WEIM_D4       IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D5__EPDC_D5       IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D5__GPIO_3_5      IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D5__WEIM_D5       IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D6__EPDC_D6       IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D6__GPIO_3_6      IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D6__WEIM_D6       IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D7__EPDC_D7       IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D7__GPIO_3_7      IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D7__WEIM_D7       IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D8__EPDC_D8       IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D8__GPIO_3_8      IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D8__WEIM_D8       IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D8__ELCDIF_D24    IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D9__EPDC_D9       IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D9__GPIO_3_9      IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D9__WEIM_D9       IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D9__ELCDIF_D25    IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D10__EPDC_D10     IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D10__GPIO_3_10    IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D10__WEIM_D10     IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D10__ELCDIF_D26   IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D11__EPDC_D11     IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D11__GPIO_3_11    IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D11__WEIM_D11     IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D11__ELCDIF_D27   IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D12__EPDC_D12     IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D12__GPIO_3_12    IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D12__WEIM_D12     IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D12__ELCDIF_D28   IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D13__EPDC_D13     IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D13__GPIO_3_13    IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D13__WEIM_D13     IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D13__ELCDIF_D29   IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D14__EPDC_D14     IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D14__GPIO_3_14    IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D14__WEIM_D14     IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D14__ELCDIF_D30   IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_D14__AUD6_TXD     IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_D15__EPDC_D15     IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D15__GPIO_3_15    IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D15__WEIM_D15     IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_D15__ELCDIF_D31   IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_D15__AUD6_TXC     IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDCLK__GPIO_3_16  IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDCLK__WEIM_D16   IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS  IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_GDSP__EPDC_GDSP   IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDSP__GPIO_3_17   IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDSP__WEIM_D17    IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDSP__ELCDIF_D17  IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_GDSP__AUD6_RXD    IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_GDOE__EPDC_GDOE   IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDOE__GPIO_3_18   IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDOE__WEIM_D18    IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDOE__ELCDIF_D18  IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_GDOE__AUD6_RXC    IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_GDRL__EPDC_GDRL   IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDRL__GPIO_3_19   IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDRL__WEIM_D19    IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_GDRL__ELCDIF_D19  IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_GDRL__AUD6_RXFS   IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLK__GPIO_3_20  IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLK__WEIM_D20   IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLK__AUD5_TXD   IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21  IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOEZ__WEIM_D21   IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC   IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOED__GPIO_3_22  IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOED__WEIM_D22   IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOED__AUD5_TXFS  IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDOE__EPDC_SDOE   IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOE__GPIO_3_23   IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOE__WEIM_D23    IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOE__ELCDIF_D23  IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_SDOE__AUD5_RXD    IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDLE__EPDC_SDLE   IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDLE__GPIO_3_24   IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDLE__WEIM_D24    IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDLE__ELCDIF_D8   IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_SDLE__AUD5_RXC    IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN       IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25         IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLKN__WEIM_D25          IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9         IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS         IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDSHR__GPIO_3_26  IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDSHR__WEIM_D26   IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_SDSHR__AUD4_TXD   IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM       IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27         IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCOM__WEIM_D27          IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11        IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC          IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT     IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28        IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28         IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12       IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS        IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0   IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29       IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29        IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13      IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD        IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1   IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30       IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30        IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14      IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC        IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2   IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31       IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31        IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15      IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS       IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0       IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3        IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20       IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2        IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1       IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_VCOM0__GPIO_4_21  IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_VCOM0__WEIM_EB3   IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_VCOM1__GPIO_4_22  IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_VCOM1__WEIM_CS3   IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EPDC_BDR0__EPDC_BDR0   IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_BDR0__GPIO_4_23   IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_BDR0__ELCDIF_D7   IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_BDR1__EPDC_BDR1   IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_BDR1__GPIO_4_24   IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_BDR1__ELCDIF_D6   IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE0__GPIO_4_25  IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5  IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE1__GPIO_4_26  IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4  IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2         IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE2__GPIO_4_27          IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3        IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE3__GPIO_4_28  IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2  IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE4__GPIO_4_29  IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1  IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE5__GPIO_4_30  IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0  IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL)
+
+#define MX50_PAD_EIM_DA0__WEIM_A0       IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA0__GPIO_1_0      IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA0__KEY_COL4      IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_DA1__WEIM_A1       IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA1__GPIO_1_1      IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA1__KEY_ROW4      IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL)
+
+#define MX50_PAD_EIM_DA2__WEIM_A2       IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA2__GPIO_1_2      IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA2__KEY_COL5      IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_DA3__WEIM_A3       IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA3__GPIO_1_3      IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA3__KEY_ROW5      IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL)
+
+#define MX50_PAD_EIM_DA4__WEIM_A4       IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA4__GPIO_1_4      IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA4__KEY_COL6      IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_DA5__WEIM_A5       IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA5__GPIO_1_5      IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA5__KEY_ROW6      IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL)
+
+#define MX50_PAD_EIM_DA6__WEIM_A6       IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA6__GPIO_1_6      IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA6__KEY_COL7      IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_DA7__WEIM_A7       IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA7__GPIO_1_7      IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA7__KEY_ROW7      IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL)
+
+#define MX50_PAD_EIM_DA8__WEIM_A8       IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA8__GPIO_1_8      IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_EIM_DA8__NANDF_CLE     IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_EIM_DA9__WEIM_A9       IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA9__GPIO_1_9      IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_EIM_DA9__NANDF_ALE     IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_EIM_DA10__WEIM_A10     IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA10__GPIO_1_10    IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_EIM_DA10__NANDF_CE0    IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_EIM_DA11__WEIM_A11     IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA11__GPIO_1_11    IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_EIM_DA11__NANDF_CE1    IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+
+#define MX50_PAD_EIM_DA12__WEIM_A12     IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA12__GPIO_1_12    IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_EIM_DA12__NANDF_CE2    IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_EIM_DA12__EPDC_SDCE6   IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_DA13__WEIM_A13     IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA13__GPIO_1_13    IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_EIM_DA13__NANDF_CE3    IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
+#define MX50_PIN_EIM_DA13__EPDC_SDCE7   IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_DA14__WEIM_A14     IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA14__GPIO_1_14    IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA14__NANDF_READY  IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \
+                                                        PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define MX50_PAD_EIM_DA14__EPDC_SDCE8   IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_DA15__WEIM_A15     IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_DA15__GPIO_1_15    IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PIN_EIM_DA15__NANDF_DQS    IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH)
+#define MX50_PAD_EIM_DA15__EPDC_SDCE9   IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_CS2__WEIM_CS2      IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_CS2__GPIO_1_16     IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_CS2__WEIM_A27      IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_CS1__WEIM_CS1      IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_CS1__GPIO_1_17     IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_CS0__WEIM_CS0      IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_CS0__GPIO_1_18     IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_EB0__WEIM_EB0      IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_EB0__GPIO_1_19     IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_EB1__WEIM_EB1      IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_EB1__GPIO_1_20     IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_WAIT__WEIM_WAIT    IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_WAIT__GPIO_1_21    IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_BCLK__WEIM_BCLK    IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_BCLK__GPIO_1_22    IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_RDY__WEIM_RDY      IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_RDY__GPIO_1_23     IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_OE__WEIM_OE        IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_OE__GPIO_1_24      IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_RW__WEIM_RW        IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_RW__GPIO_1_25      IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_LBA__WEIM_LBA      IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_LBA__GPIO_1_26     IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX50_PAD_EIM_CRE__WEIM_CRE      IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX50_PAD_EIM_CRE__GPIO_1_27     IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL)
+
+#endif /* __MACH_IOMUX_MX50_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index d7a41e9a2605..b6767f90ef14 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -15,373 +15,1553 @@
 
 #include <mach/iomux-v3.h>
 
-/*
- * various IOMUX alternate output functions (1-7)
- */
-typedef enum iomux_config {
-        IOMUX_CONFIG_ALT0,
-        IOMUX_CONFIG_ALT1,
-        IOMUX_CONFIG_ALT2,
-        IOMUX_CONFIG_ALT3,
-        IOMUX_CONFIG_ALT4,
-        IOMUX_CONFIG_ALT5,
-        IOMUX_CONFIG_ALT6,
-        IOMUX_CONFIG_ALT7,
-        IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
-        IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
-} iomux_pin_cfg_t;
-
 /* Pad control groupings */
-#define MX51_UART1_PAD_CTRL     (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                PAD_CTL_DSE_HIGH)
-#define MX51_UART2_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_SRE_FAST)
-#define MX51_UART3_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_SRE_FAST)
+#define MX51_UART_PAD_CTRL      (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
+                                PAD_CTL_HYS | PAD_CTL_SRE_FAST)
 #define MX51_I2C_PAD_CTRL       (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
-                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
-#define MX51_USBH1_PAD_CTRL     (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
-                                PAD_CTL_PKE | PAD_CTL_HYS)
-#define MX51_GPIO_PAD_CTRL              (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
-                                PAD_CTL_SRE_FAST)
-#define MX51_GPIO_PAD_CTRL_2    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
-                                        PAD_CTL_PUS_100K_UP)
-#define MX51_ECSPI_PAD_CTRL     (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_SRE_FAST)
-#define MX51_SDHCI_PAD_CTRL     (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
-                                PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \
-                                PAD_CTL_DVS)
+                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+                                PAD_CTL_HYS)
+#define MX51_ESDHC_PAD_CTRL     (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+                                PAD_CTL_HYS)
+#define MX51_USBH1_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
+                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
+                                PAD_CTL_HYS | PAD_CTL_PUE)
+#define MX51_ECSPI_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_HYS | \
+                                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
+#define MX51_SDHCI_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
+                                PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
+                                PAD_CTL_SRE_FAST | PAD_CTL_DVS)
+#define MX51_GPIO_PAD_CTRL      (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
 
-#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
-                                        PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
-#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE)
-#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
+#define MX51_PAD_CTRL_2         (PAD_CTL_PKE | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_3         (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
+#define MX51_PAD_CTRL_4         (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
+#define MX51_PAD_CTRL_5         (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
 
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
  * See also iomux-v3.h
  */
 
-/*                                                        PAD    MUX   ALT INPSE PATH PADCTRL */
-#define MX51_PAD_EIM_DA0__EIM_DA0               IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1               IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2               IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3               IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4               IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5               IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6               IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7               IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA8__EIM_DA8               IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9               IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10             IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11             IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12             IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13             IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14             IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15             IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__GPIO_2_0              IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D16__I2C1_SDA              IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \
-                                                        0x09b4, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D17__GPIO_2_1              IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D18__GPIO_2_2              IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__GPIO_2_3              IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__I2C1_SCL              IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \
-                                                        0x09b0, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_EIM_D20__GPIO_2_4              IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO_2_5              IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_EIM_D22__GPIO_2_6              IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D23__GPIO_2_7              IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART2_CTS             IOMUX_PAD(0x414, 0x080, 4, 0x0,   0, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART2_RTS             IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A16__GPIO_2_10             IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A17__GPIO_2_11             IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A18__GPIO_2_12             IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A19__GPIO_2_13             IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A20__GPIO_2_14             IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A21__GPIO_2_15             IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A23__GPIO_2_17             IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A24__GPIO_2_18             IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A25__GPIO_2_19             IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A26__GPIO_2_20             IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_A27__GPIO_2_21             IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB2__FEC_MDIO              IOMUX_PAD(0x468, 0x0d4, 3, 0x0,   0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
-#define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB3__FEC_RDAT1             IOMUX_PAD(0x46c, 0x0d8, 3, 0x0,   0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS2__FEC_RDAT2             IOMUX_PAD(0x47c, 0x0e8, 3, 0x0,   0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS3__FEC_RDAT3             IOMUX_PAD(0x480, 0x0ec, 3, 0x0,   0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS4__FEC_RX_ER             IOMUX_PAD(0x484, 0x0f0, 3, 0x0,   0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CS5__FEC_CRS               IOMUX_PAD(0x488, 0x0f4, 3, 0x0,   0, MX51_PAD_CTRL_2)
-#define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WE_B__GPIO_3_3           IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RE_B__GPIO_3_4           IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_ALE__GPIO_3_5            IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CLE__GPIO_3_6            IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_WP_B__GPIO_3_7           IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x0,   0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__FEC_RXCLK           IOMUX_PAD(0x504, 0x128, 1, 0x0,   0, MX51_PAD_CTRL_2)
-#define MX51_PAD_NANDF_RB6__FEC_RDAT0           IOMUX_PAD(0x5DC, 0x134, 1, 0x0,   0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_RB7__FEC_TDAT0           IOMUX_PAD(0x5E0, 0x138, 1, 0x0,   0, MX51_PAD_CTRL_5)
-#define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS2__FEC_TX_ER           IOMUX_PAD(0x520, 0x138, 2, 0x0,   0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__FEC_MDC             IOMUX_PAD(0x524, 0x13C, 2, 0x0,   0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS4__FEC_TDAT1           IOMUX_PAD(0x528, 0x140, 2, 0x0,   0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS5__FEC_TDAT2           IOMUX_PAD(0x52C, 0x144, 2, 0x0,   0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS6__FEC_TDAT3           IOMUX_PAD(0x530, 0x148, 2, 0x0,   0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_CS7__FEC_TX_EN           IOMUX_PAD(0x534, 0x14C, 1, 0x0,   0, MX51_PAD_CTRL_5)
-#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      IOMUX_PAD(0x538, 0x150, 1, 0x0,   0, MX51_PAD_CTRL_4)
-#define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53C, 0x154, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D11__GPIO_3_29           IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D10__GPIO_3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D9__GPIO_3_31            IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D8__GPIO_4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D7__GPIO_4_1             IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D6__GPIO_4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D5__GPIO_4_3             IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D4__GPIO_4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D3__GPIO_4_5             IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D2__GPIO_4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D1__GPIO_4_7             IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_D0__GPIO_4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D8__GPIO_3_12             IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D9__GPIO_3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0           IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D12__GPIO_4_9             IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D13__GPIO_4_10            IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D14__GPIO_4_11            IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D15__GPIO_4_12            IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D16__GPIO_4_11            IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D17__GPIO_4_12            IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D18__GPIO_4_11            IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_D19__GPIO_4_12            IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_VSYNC__GPIO_4_13          IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_HSYNC__GPIO_4_14          IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15         IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__GPIO_4_16            IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__HSI2C_CLK            IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__HSI2C_DAT            IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD       IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD       IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK         IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS         IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        IOMUX_PAD(0x600, 0x210, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        IOMUX_PAD(0x604, 0x214, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          IOMUX_PAD(0x608, 0x218, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          IOMUX_PAD(0x60C, 0x21C, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          IOMUX_PAD(0x610, 0x220, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        IOMUX_PAD(0x614, 0x224, 0, 0x0,   0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__UART3_RXD           IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__GPIO_1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__UART3_TXD           IOMUX_PAD(0x634, 0x244, 1, 0x0,   0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__GPIO_1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_OWIRE_LINE__GPIO_1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__UART3_RTS            IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__I2C2_SCL             IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \
-                                                        0x09b8, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__UART3_CTS            IOMUX_PAD(0x660, 0x270, 2, 0,     0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__I2C2_SDA             IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \
-                                                        0x09bc, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, 2, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL)
-#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1                 IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2                 IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3                 IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4                 IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT6__GPIO_1_19          IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT7__GPIO_1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT8__GPIO_1_30          IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT9__GPIO_1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__AUD5_RXFS             IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD1_CLK__AUD5_RXC              IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__AUD5_TXD            IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__AUD5_RXD            IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__AUD5_TXC            IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__AUD5_TXFS           IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \
-                                                        MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \
-                                                        MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO_1_0             IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO_1_1             IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO_1_2             IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__I2C2_SCL             IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \
-                                                        0x9b8,   3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO_1_3             IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__I2C2_SDA             IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \
-                                                        0x9bc,   3, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO_1_4             IOMUX_PAD(0x804, 0x3D8, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO_1_5             IOMUX_PAD(0x808, 0x3DC, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO_1_6             IOMUX_PAD(0x80C, 0x3E0, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO_1_7             IOMUX_PAD(0x810, 0x3E4, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO_1_8             IOMUX_PAD(0x814, 0x3E8, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_9__GPIO_1_9             IOMUX_PAD(0x818, 0x3EC, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+/* Raw pin modes without pad control */
+/*                                                        PAD    MUX ALT INPSE PATH PADCTRL */
+#define _MX51_PAD_EIM_D16__AUD4_RXFS            IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D16__AUD5_TXD             IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0)
+#define _MX51_PAD_EIM_D16__EIM_D16              IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D16__GPIO2_0              IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D16__I2C1_SDA             IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0)
+#define _MX51_PAD_EIM_D16__UART2_CTS            IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D16__USBH2_DATA0          IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D17__AUD5_RXD             IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0)
+#define _MX51_PAD_EIM_D17__EIM_D17              IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D17__GPIO2_1              IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D17__UART2_RXD            IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0)
+#define _MX51_PAD_EIM_D17__UART3_CTS            IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D17__USBH2_DATA1          IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D18__AUD5_TXC             IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0)
+#define _MX51_PAD_EIM_D18__EIM_D18              IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D18__GPIO2_2              IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D18__UART2_TXD            IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D18__UART3_RTS            IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0)
+#define _MX51_PAD_EIM_D18__USBH2_DATA2          IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D19__AUD4_RXC             IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D19__AUD5_TXFS            IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0)
+#define _MX51_PAD_EIM_D19__EIM_D19              IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D19__GPIO2_3              IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D19__I2C1_SCL             IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0)
+#define _MX51_PAD_EIM_D19__UART2_RTS            IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0)
+#define _MX51_PAD_EIM_D19__USBH2_DATA3          IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D20__AUD4_TXD             IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0)
+#define _MX51_PAD_EIM_D20__EIM_D20              IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D20__GPIO2_4              IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB       IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D20__USBH2_DATA4          IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D21__AUD4_RXD             IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0)
+#define _MX51_PAD_EIM_D21__EIM_D21              IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D21__GPIO2_5              IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB       IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D21__USBH2_DATA5          IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D22__AUD4_TXC             IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0)
+#define _MX51_PAD_EIM_D22__EIM_D22              IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D22__GPIO2_6              IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D22__USBH2_DATA6          IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D23__AUD4_TXFS            IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0)
+#define _MX51_PAD_EIM_D23__EIM_D23              IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D23__GPIO2_7              IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D23__SPDIF_OUT1           IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D23__USBH2_DATA7          IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D24__AUD6_RXFS            IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0)
+#define _MX51_PAD_EIM_D24__EIM_D24              IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D24__GPIO2_8              IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D24__I2C2_SDA             IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0)
+#define _MX51_PAD_EIM_D24__UART3_CTS            IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D24__USBOTG_DATA0         IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D25__EIM_D25              IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D25__KEY_COL6             IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0)
+#define _MX51_PAD_EIM_D25__UART2_CTS            IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D25__UART3_RXD            IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0)
+#define _MX51_PAD_EIM_D25__USBOTG_DATA1         IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D26__EIM_D26              IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D26__KEY_COL7             IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0)
+#define _MX51_PAD_EIM_D26__UART2_RTS            IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0)
+#define _MX51_PAD_EIM_D26__UART3_TXD            IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D26__USBOTG_DATA2         IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D27__AUD6_RXC             IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0)
+#define _MX51_PAD_EIM_D27__EIM_D27              IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D27__GPIO2_9              IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D27__I2C2_SCL             IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0)
+#define _MX51_PAD_EIM_D27__UART3_RTS            IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0)
+#define _MX51_PAD_EIM_D27__USBOTG_DATA3         IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D28__AUD6_TXD             IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0)
+#define _MX51_PAD_EIM_D28__EIM_D28              IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D28__KEY_ROW4             IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0)
+#define _MX51_PAD_EIM_D28__USBOTG_DATA4         IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D29__AUD6_RXD             IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0)
+#define _MX51_PAD_EIM_D29__EIM_D29              IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D29__KEY_ROW5             IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0)
+#define _MX51_PAD_EIM_D29__USBOTG_DATA5         IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D30__AUD6_TXC             IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0)
+#define _MX51_PAD_EIM_D30__EIM_D30              IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D30__KEY_ROW6             IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0)
+#define _MX51_PAD_EIM_D30__USBOTG_DATA6         IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D31__AUD6_TXFS            IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0)
+#define _MX51_PAD_EIM_D31__EIM_D31              IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_D31__KEY_ROW7             IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0)
+#define _MX51_PAD_EIM_D31__USBOTG_DATA7         IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A16__EIM_A16              IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A16__GPIO2_10             IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0        IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A17__EIM_A17              IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A17__GPIO2_11             IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1        IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A18__BOOT_LPB0            IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A18__EIM_A18              IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A18__GPIO2_12             IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A19__BOOT_LPB1            IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A19__EIM_A19              IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A19__GPIO2_13             IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A20__BOOT_UART_SRC0       IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A20__EIM_A20              IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A20__GPIO2_14             IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A21__BOOT_UART_SRC1       IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A21__EIM_A21              IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A21__GPIO2_15             IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A22__EIM_A22              IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A22__GPIO2_16             IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A23__BOOT_HPN_EN          IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A23__EIM_A23              IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A23__GPIO2_17             IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A24__EIM_A24              IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A24__GPIO2_18             IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A24__USBH2_CLK            IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A25__DISP1_PIN4           IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A25__EIM_A25              IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A25__GPIO2_19             IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A25__USBH2_DIR            IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A26__CSI1_DATA_EN         IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0)
+#define _MX51_PAD_EIM_A26__DISP2_EXT_CLK        IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0)
+#define _MX51_PAD_EIM_A26__EIM_A26              IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A26__GPIO2_20             IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A26__USBH2_STP            IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A27__CSI2_DATA_EN         IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0)
+#define _MX51_PAD_EIM_A27__DISP1_PIN1           IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0)
+#define _MX51_PAD_EIM_A27__EIM_A27              IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A27__GPIO2_21             IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_A27__USBH2_NXT            IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_EB0__EIM_EB0              IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_EB1__EIM_EB1              IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_EB2__AUD5_RXFS            IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0)
+#define _MX51_PAD_EIM_EB2__CSI1_D2              IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_EB2__EIM_EB2              IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_EB2__FEC_MDIO             IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0)
+#define _MX51_PAD_EIM_EB2__GPIO2_22             IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_EB2__GPT_CMPOUT1          IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_EB3__AUD5_RXC             IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0)
+#define _MX51_PAD_EIM_EB3__CSI1_D3              IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_EB3__EIM_EB3              IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_EB3__FEC_RDATA1           IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0)
+#define _MX51_PAD_EIM_EB3__GPIO2_23             IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_EB3__GPT_CMPOUT2          IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_OE__EIM_OE                IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_OE__GPIO2_24              IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS0__EIM_CS0              IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS0__GPIO2_25             IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS1__EIM_CS1              IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS1__GPIO2_26             IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS2__AUD5_TXD             IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0)
+#define _MX51_PAD_EIM_CS2__CSI1_D4              IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS2__EIM_CS2              IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS2__FEC_RDATA2           IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0)
+#define _MX51_PAD_EIM_CS2__GPIO2_27             IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS2__USBOTG_STP           IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS3__AUD5_RXD             IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0)
+#define _MX51_PAD_EIM_CS3__CSI1_D5              IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS3__EIM_CS3              IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS3__FEC_RDATA3           IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0)
+#define _MX51_PAD_EIM_CS3__GPIO2_28             IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS3__USBOTG_NXT           IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS4__AUD5_TXC             IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0)
+#define _MX51_PAD_EIM_CS4__CSI1_D6              IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS4__EIM_CS4              IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS4__FEC_RX_ER            IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0)
+#define _MX51_PAD_EIM_CS4__GPIO2_29             IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS4__USBOTG_CLK           IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS5__AUD5_TXFS            IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0)
+#define _MX51_PAD_EIM_CS5__CSI1_D7              IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK        IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0)
+#define _MX51_PAD_EIM_CS5__EIM_CS5              IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS5__FEC_CRS              IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0)
+#define _MX51_PAD_EIM_CS5__GPIO2_30             IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CS5__USBOTG_DIR           IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DTACK__EIM_DTACK          IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DTACK__GPIO2_31           IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_LBA__EIM_LBA              IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_LBA__GPIO3_1              IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0)
+#define _MX51_PAD_EIM_CRE__EIM_CRE              IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_CRE__GPIO3_2              IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0)
+#define _MX51_PAD_DRAM_CS1__DRAM_CS1            IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_WE_B__GPIO3_3           IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0)
+#define _MX51_PAD_NANDF_WE_B__NANDF_WE_B        IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_WE_B__PATA_DIOW         IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_WE_B__SD3_DATA0         IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0)
+#define _MX51_PAD_NANDF_RE_B__GPIO3_4           IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0)
+#define _MX51_PAD_NANDF_RE_B__NANDF_RE_B        IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RE_B__PATA_DIOR         IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RE_B__SD3_DATA1         IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0)
+#define _MX51_PAD_NANDF_ALE__GPIO3_5            IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0)
+#define _MX51_PAD_NANDF_ALE__NANDF_ALE          IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN     IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CLE__GPIO3_6            IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0)
+#define _MX51_PAD_NANDF_CLE__NANDF_CLE          IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CLE__PATA_RESET_B       IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_WP_B__GPIO3_7           IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0)
+#define _MX51_PAD_NANDF_WP_B__NANDF_WP_B        IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_WP_B__PATA_DMACK        IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_WP_B__SD3_DATA2         IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0)
+#define _MX51_PAD_NANDF_RB0__ECSPI2_SS1         IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0)
+#define _MX51_PAD_NANDF_RB0__GPIO3_8            IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0)
+#define _MX51_PAD_NANDF_RB0__NANDF_RB0          IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB0__PATA_DMARQ         IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB0__SD3_DATA3          IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0)
+#define _MX51_PAD_NANDF_RB1__CSPI_MOSI          IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0)
+#define _MX51_PAD_NANDF_RB1__ECSPI2_RDY         IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB1__GPIO3_9            IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB1__NANDF_RB1          IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB1__PATA_IORDY         IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB1__SD4_CMD            IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB2__DISP2_WAIT         IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0)
+#define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK        IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB2__FEC_COL            IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0)
+#define _MX51_PAD_NANDF_RB2__GPIO3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB2__NANDF_RB2          IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB2__USBH3_H3_DP        IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB2__USBH3_NXT          IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0)
+#define _MX51_PAD_NANDF_RB3__DISP1_WAIT         IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB3__ECSPI2_MISO        IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB3__FEC_RX_CLK         IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0)
+#define _MX51_PAD_NANDF_RB3__GPIO3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB3__NANDF_RB3          IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RB3__USBH3_CLK          IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0)
+#define _MX51_PAD_NANDF_RB3__USBH3_H3_DM        IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO_NAND__GPIO_NAND          IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0)
+#define _MX51_PAD_GPIO_NAND__PATA_INTRQ         IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS0__GPIO3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS0__NANDF_CS0          IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS1__GPIO3_17           IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS1__NANDF_CS1          IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS2__CSPI_SCLK          IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0)
+#define _MX51_PAD_NANDF_CS2__FEC_TX_ER          IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS2__GPIO3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS2__NANDF_CS2          IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS2__PATA_CS_0          IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS2__SD4_CLK            IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS2__USBH3_H1_DP        IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS3__FEC_MDC            IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS3__GPIO3_19           IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS3__NANDF_CS3          IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS3__PATA_CS_1          IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS3__SD4_DAT0           IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS3__USBH3_H1_DM        IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS4__FEC_TDATA1         IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS4__GPIO3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS4__NANDF_CS4          IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS4__PATA_DA_0          IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS4__SD4_DAT1           IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS4__USBH3_STP          IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0)
+#define _MX51_PAD_NANDF_CS5__FEC_TDATA2         IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS5__GPIO3_21           IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS5__NANDF_CS5          IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS5__PATA_DA_1          IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS5__SD4_DAT2           IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS5__USBH3_DIR          IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0)
+#define _MX51_PAD_NANDF_CS6__CSPI_SS3           IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0)
+#define _MX51_PAD_NANDF_CS6__FEC_TDATA3         IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS6__GPIO3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS6__NANDF_CS6          IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS6__PATA_DA_2          IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS6__SD4_DAT3           IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS7__FEC_TX_EN          IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS7__GPIO3_23           IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS7__NANDF_CS7          IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_CS7__SD3_CLK            IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0     IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK     IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0)
+#define _MX51_PAD_NANDF_RDY_INT__GPIO3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT  IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0)
+#define _MX51_PAD_NANDF_RDY_INT__SD3_CMD        IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D15__ECSPI2_MOSI        IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D15__GPIO3_25           IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D15__NANDF_D15          IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D15__PATA_DATA15        IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D15__SD3_DAT7           IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D14__ECSPI2_SS3         IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0)
+#define _MX51_PAD_NANDF_D14__GPIO3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D14__NANDF_D14          IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D14__PATA_DATA14        IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D14__SD3_DAT6           IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D13__ECSPI2_SS2         IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D13__GPIO3_27           IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D13__NANDF_D13          IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D13__PATA_DATA13        IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D13__SD3_DAT5           IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D12__ECSPI2_SS1         IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0)
+#define _MX51_PAD_NANDF_D12__GPIO3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D12__NANDF_D12          IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D12__PATA_DATA12        IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D12__SD3_DAT4           IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D11__FEC_RX_DV          IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0)
+#define _MX51_PAD_NANDF_D11__GPIO3_29           IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D11__NANDF_D11          IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D11__PATA_DATA11        IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D11__SD3_DATA3          IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0)
+#define _MX51_PAD_NANDF_D10__GPIO3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D10__NANDF_D10          IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D10__PATA_DATA10        IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D10__SD3_DATA2          IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0)
+#define _MX51_PAD_NANDF_D9__FEC_RDATA0          IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0)
+#define _MX51_PAD_NANDF_D9__GPIO3_31            IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D9__NANDF_D9            IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D9__PATA_DATA9          IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D9__SD3_DATA1           IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0)
+#define _MX51_PAD_NANDF_D8__FEC_TDATA0          IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D8__GPIO4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D8__NANDF_D8            IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D8__PATA_DATA8          IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D8__SD3_DATA0           IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0)
+#define _MX51_PAD_NANDF_D7__GPIO4_1             IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D7__NANDF_D7            IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D7__PATA_DATA7          IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D7__USBH3_DATA0         IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0)
+#define _MX51_PAD_NANDF_D6__GPIO4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D6__NANDF_D6            IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D6__PATA_DATA6          IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D6__SD4_LCTL            IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D6__USBH3_DATA1         IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0)
+#define _MX51_PAD_NANDF_D5__GPIO4_3             IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D5__NANDF_D5            IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D5__PATA_DATA5          IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D5__SD4_WP              IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D5__USBH3_DATA2         IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0)
+#define _MX51_PAD_NANDF_D4__GPIO4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D4__NANDF_D4            IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D4__PATA_DATA4          IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D4__SD4_CD              IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D4__USBH3_DATA3         IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0)
+#define _MX51_PAD_NANDF_D3__GPIO4_5             IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D3__NANDF_D3            IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D3__PATA_DATA3          IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D3__SD4_DAT4            IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D3__USBH3_DATA4         IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0)
+#define _MX51_PAD_NANDF_D2__GPIO4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D2__NANDF_D2            IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D2__PATA_DATA2          IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D2__SD4_DAT5            IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D2__USBH3_DATA5         IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0)
+#define _MX51_PAD_NANDF_D1__GPIO4_7             IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D1__NANDF_D1            IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D1__PATA_DATA1          IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D1__SD4_DAT6            IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D1__USBH3_DATA6         IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0)
+#define _MX51_PAD_NANDF_D0__GPIO4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D0__NANDF_D0            IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D0__PATA_DATA0          IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D0__SD4_DAT7            IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0)
+#define _MX51_PAD_NANDF_D0__USBH3_DATA7         IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0)
+#define _MX51_PAD_CSI1_D8__CSI1_D8              IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D8__GPIO3_12             IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0)
+#define _MX51_PAD_CSI1_D9__CSI1_D9              IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D9__GPIO3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D10__CSI1_D10            IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D11__CSI1_D11            IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D12__CSI1_D12            IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D13__CSI1_D13            IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D14__CSI1_D14            IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D15__CSI1_D15            IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D16__CSI1_D16            IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D17__CSI1_D17            IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D18__CSI1_D18            IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_D19__CSI1_D19            IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC        IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_VSYNC__GPIO3_14          IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC        IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_HSYNC__GPIO3_15          IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK      IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI1_MCLK__CSI1_MCLK          IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D12__CSI2_D12            IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D12__GPIO4_9             IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D13__CSI2_D13            IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D13__GPIO4_10            IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D14__CSI2_D14            IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D15__CSI2_D15            IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D16__CSI2_D16            IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D17__CSI2_D17            IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D18__CSI2_D18            IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D18__GPIO4_11            IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D19__CSI2_D19            IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_D19__GPIO4_12            IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC        IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_VSYNC__GPIO4_13          IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC        IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_HSYNC__GPIO4_14          IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK      IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSI2_PIXCLK__GPIO4_15         IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0)
+#define _MX51_PAD_I2C1_CLK__GPIO4_16            IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0)
+#define _MX51_PAD_I2C1_CLK__I2C1_CLK            IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_I2C1_DAT__GPIO4_17            IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0)
+#define _MX51_PAD_I2C1_DAT__I2C1_DAT            IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD         IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0)
+#define _MX51_PAD_AUD3_BB_TXD__GPIO4_18         IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0)
+#define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD         IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0)
+#define _MX51_PAD_AUD3_BB_RXD__GPIO4_19         IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0)
+#define _MX51_PAD_AUD3_BB_RXD__UART3_RXD        IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0)
+#define _MX51_PAD_AUD3_BB_CK__AUD3_TXC          IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0)
+#define _MX51_PAD_AUD3_BB_CK__GPIO4_20          IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0)
+#define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS         IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_AUD3_BB_FS__GPIO4_21          IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_AUD3_BB_FS__UART3_TXD         IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI       IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_MOSI__GPIO4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_MOSI__I2C1_SDA          IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0)
+#define _MX51_PAD_CSPI1_MISO__AUD4_RXD          IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0)
+#define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO       IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_MISO__GPIO4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_SS0__AUD4_TXC           IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0)
+#define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0         IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_SS0__GPIO4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_SS1__AUD4_TXD           IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0)
+#define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1         IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_SS1__GPIO4_25           IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_RDY__AUD4_TXFS          IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0)
+#define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY         IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_RDY__GPIO4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK       IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_SCLK__GPIO4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0)
+#define _MX51_PAD_CSPI1_SCLK__I2C1_SCL          IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0)
+#define _MX51_PAD_UART1_RXD__GPIO4_28           IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0)
+#define _MX51_PAD_UART1_RXD__UART1_RXD          IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0)
+#define _MX51_PAD_UART1_TXD__GPIO4_29           IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_UART1_TXD__PWM2_PWMO          IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_UART1_TXD__UART1_TXD          IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_UART1_RTS__GPIO4_30           IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0)
+#define _MX51_PAD_UART1_RTS__UART1_RTS          IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0)
+#define _MX51_PAD_UART1_CTS__GPIO4_31           IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0)
+#define _MX51_PAD_UART1_CTS__UART1_CTS          IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0)
+#define _MX51_PAD_UART2_RXD__FIRI_TXD           IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0)
+#define _MX51_PAD_UART2_RXD__GPIO1_20           IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0)
+#define _MX51_PAD_UART2_RXD__UART2_RXD          IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0)
+#define _MX51_PAD_UART2_TXD__FIRI_RXD           IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_UART2_TXD__GPIO1_21           IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0)
+#define _MX51_PAD_UART2_TXD__UART2_TXD          IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0)
+#define _MX51_PAD_UART3_RXD__CSI1_D0            IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0)
+#define _MX51_PAD_UART3_RXD__GPIO1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0)
+#define _MX51_PAD_UART3_RXD__UART1_DTR          IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0)
+#define _MX51_PAD_UART3_RXD__UART3_RXD          IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0)
+#define _MX51_PAD_UART3_TXD__CSI1_D1            IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0)
+#define _MX51_PAD_UART3_TXD__GPIO1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0)
+#define _MX51_PAD_UART3_TXD__UART1_DSR          IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0)
+#define _MX51_PAD_UART3_TXD__UART3_TXD          IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0)
+#define _MX51_PAD_OWIRE_LINE__GPIO1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0)
+#define _MX51_PAD_OWIRE_LINE__OWIRE_LINE        IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0)
+#define _MX51_PAD_OWIRE_LINE__SPDIF_OUT         IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_ROW0__KEY_ROW0            IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_ROW1__KEY_ROW1            IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_ROW2__KEY_ROW2            IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_ROW3__KEY_ROW3            IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL0__KEY_COL0            IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL0__PLL1_BYP            IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0)
+#define _MX51_PAD_KEY_COL1__KEY_COL1            IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL1__PLL2_BYP            IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0)
+#define _MX51_PAD_KEY_COL2__KEY_COL2            IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL2__PLL3_BYP            IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL3__KEY_COL3            IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL4__I2C2_SCL            IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0)
+#define _MX51_PAD_KEY_COL4__KEY_COL4            IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL4__SPDIF_OUT1          IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL4__UART1_RI            IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL4__UART3_RTS           IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0)
+#define _MX51_PAD_KEY_COL5__I2C2_SDA            IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0)
+#define _MX51_PAD_KEY_COL5__KEY_COL5            IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL5__UART1_DCD           IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0)
+#define _MX51_PAD_KEY_COL5__UART3_CTS           IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_CLK__CSPI_SCLK          IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0)
+#define _MX51_PAD_USBH1_CLK__GPIO1_25           IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_CLK__I2C2_SCL           IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0)
+#define _MX51_PAD_USBH1_CLK__USBH1_CLK          IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DIR__CSPI_MOSI          IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0)
+#define _MX51_PAD_USBH1_DIR__GPIO1_26           IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DIR__I2C2_SDA           IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0)
+#define _MX51_PAD_USBH1_DIR__USBH1_DIR          IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_STP__CSPI_RDY           IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_STP__GPIO1_27           IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_STP__UART3_RXD          IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0)
+#define _MX51_PAD_USBH1_STP__USBH1_STP          IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_NXT__CSPI_MISO          IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0)
+#define _MX51_PAD_USBH1_NXT__GPIO1_28           IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_NXT__UART3_TXD          IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_NXT__USBH1_NXT          IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA0__GPIO1_11         IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA0__UART2_CTS        IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA0__USBH1_DATA0      IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA1__GPIO1_12         IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA1__UART2_RXD        IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0)
+#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1      IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA2__GPIO1_13         IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA2__UART2_TXD        IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0)
+#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2      IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA3__GPIO1_14         IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA3__UART2_RTS        IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0)
+#define _MX51_PAD_USBH1_DATA3__USBH1_DATA3      IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA4__CSPI_SS0         IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA4__GPIO1_15         IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA4__USBH1_DATA4      IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA5__CSPI_SS1         IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0)
+#define _MX51_PAD_USBH1_DATA5__GPIO1_16         IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA5__USBH1_DATA5      IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA6__CSPI_SS3         IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0)
+#define _MX51_PAD_USBH1_DATA6__GPIO1_17         IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA6__USBH1_DATA6      IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3       IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3       IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0)
+#define _MX51_PAD_USBH1_DATA7__GPIO1_18         IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0)
+#define _MX51_PAD_USBH1_DATA7__USBH1_DATA7      IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_PIN11__DI1_PIN11          IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_PIN11__ECSPI1_SS2         IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_PIN11__GPIO3_0            IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_PIN12__DI1_PIN12          IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_PIN12__GPIO3_1            IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0)
+#define _MX51_PAD_DI1_PIN13__DI1_PIN13          IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_PIN13__GPIO3_2            IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0)
+#define _MX51_PAD_DI1_D0_CS__DI1_D0_CS          IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_D0_CS__GPIO3_3            IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0)
+#define _MX51_PAD_DI1_D1_CS__DI1_D1_CS          IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_D1_CS__DISP1_PIN14        IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_D1_CS__DISP1_PIN5         IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_D1_CS__GPIO3_4            IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0)
+#define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1    IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0)
+#define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN        IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0)
+#define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5       IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0)
+#define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6    IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0)
+#define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO        IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0)
+#define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6       IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0)
+#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17   IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7    IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0)
+#define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK        IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7       IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0)
+#define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK  IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16    IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8     IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0)
+#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS  IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS  IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISPB2_SER_RS__GPIO3_8        IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0)
+#define _MX51_PAD_DISP1_DAT0__DISP1_DAT0        IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT1__DISP1_DAT1        IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT2__DISP1_DAT2        IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT3__DISP1_DAT3        IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT4__DISP1_DAT4        IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT5__DISP1_DAT5        IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC      IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT6__DISP1_DAT6        IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG   IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT7__DISP1_DAT7        IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT8__BOOT_SRC0         IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT8__DISP1_DAT8        IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT9__BOOT_SRC1         IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT9__DISP1_DAT9        IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE  IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT10__DISP1_DAT10      IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2   IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT11__DISP1_DAT11      IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL     IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT12__DISP1_DAT12      IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0    IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT13__DISP1_DAT13      IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1    IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT14__DISP1_DAT14      IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH   IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT15__DISP1_DAT15      IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0  IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT16__DISP1_DAT16      IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1  IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT17__DISP1_DAT17      IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT18__DISP1_DAT18      IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT18__DISP2_PIN11      IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT18__DISP2_PIN5       IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT19__DISP1_DAT19      IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT19__DISP2_PIN12      IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT19__DISP2_PIN6       IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0   IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT20__DISP1_DAT20      IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT20__DISP2_PIN13      IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT20__DISP2_PIN7       IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1   IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT21__DISP1_DAT21      IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT21__DISP2_PIN14      IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT21__DISP2_PIN8       IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0   IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT22__DISP1_DAT22      IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS      IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT22__DISP2_DAT16      IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1   IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT23__DISP1_DAT23      IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS      IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT23__DISP2_DAT17      IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS     IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_PIN3__DI1_PIN3            IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI1_PIN2__DI1_PIN2            IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI_GP2__DISP1_SER_CLK         IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI_GP2__DISP2_WAIT            IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0)
+#define _MX51_PAD_DI_GP3__CSI1_DATA_EN          IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0)
+#define _MX51_PAD_DI_GP3__DISP1_SER_DIO         IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0)
+#define _MX51_PAD_DI_GP3__FEC_TX_ER             IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN        IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0)
+#define _MX51_PAD_DI2_PIN4__DI2_PIN4            IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI2_PIN4__FEC_CRS             IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0)
+#define _MX51_PAD_DI2_PIN2__DI2_PIN2            IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI2_PIN2__FEC_MDC             IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DI2_PIN3__DI2_PIN3            IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI2_PIN3__FEC_MDIO            IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0)
+#define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK    IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1      IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0)
+#define _MX51_PAD_DI_GP4__DI2_PIN15             IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0)
+#define _MX51_PAD_DI_GP4__DISP1_SER_DIN         IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0)
+#define _MX51_PAD_DI_GP4__DISP2_PIN1            IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0)
+#define _MX51_PAD_DI_GP4__FEC_RDATA2            IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0)
+#define _MX51_PAD_DISP2_DAT0__DISP2_DAT0        IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT0__FEC_RDATA3        IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0)
+#define _MX51_PAD_DISP2_DAT0__KEY_COL6          IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0)
+#define _MX51_PAD_DISP2_DAT0__UART3_RXD         IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0)
+#define _MX51_PAD_DISP2_DAT0__USBH3_CLK         IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0)
+#define _MX51_PAD_DISP2_DAT1__DISP2_DAT1        IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT1__FEC_RX_ER         IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0)
+#define _MX51_PAD_DISP2_DAT1__KEY_COL7          IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0)
+#define _MX51_PAD_DISP2_DAT1__UART3_TXD         IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT1__USBH3_DIR         IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0)
+#define _MX51_PAD_DISP2_DAT2__DISP2_DAT2        IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT3__DISP2_DAT3        IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT4__DISP2_DAT4        IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT5__DISP2_DAT5        IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT6__DISP2_DAT6        IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT6__FEC_TDATA1        IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT6__GPIO1_19          IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT6__KEY_ROW4          IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0)
+#define _MX51_PAD_DISP2_DAT6__USBH3_STP         IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0)
+#define _MX51_PAD_DISP2_DAT7__DISP2_DAT7        IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT7__FEC_TDATA2        IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT7__GPIO1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT7__KEY_ROW5          IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0)
+#define _MX51_PAD_DISP2_DAT7__USBH3_NXT         IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0)
+#define _MX51_PAD_DISP2_DAT8__DISP2_DAT8        IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT8__FEC_TDATA3        IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT8__GPIO1_30          IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT8__KEY_ROW6          IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0)
+#define _MX51_PAD_DISP2_DAT8__USBH3_DATA0       IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0)
+#define _MX51_PAD_DISP2_DAT9__AUD6_RXC          IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0)
+#define _MX51_PAD_DISP2_DAT9__DISP2_DAT9        IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT9__FEC_TX_EN         IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT9__GPIO1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT9__USBH3_DATA1       IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0)
+#define _MX51_PAD_DISP2_DAT10__DISP2_DAT10      IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS     IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT10__FEC_COL          IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0)
+#define _MX51_PAD_DISP2_DAT10__KEY_ROW7         IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0)
+#define _MX51_PAD_DISP2_DAT10__USBH3_DATA2      IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0)
+#define _MX51_PAD_DISP2_DAT11__AUD6_TXD         IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0)
+#define _MX51_PAD_DISP2_DAT11__DISP2_DAT11      IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK       IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0)
+#define _MX51_PAD_DISP2_DAT11__GPIO1_10         IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT11__USBH3_DATA3      IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0)
+#define _MX51_PAD_DISP2_DAT12__AUD6_RXD         IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0)
+#define _MX51_PAD_DISP2_DAT12__DISP2_DAT12      IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT12__FEC_RX_DV        IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0)
+#define _MX51_PAD_DISP2_DAT12__USBH3_DATA4      IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0)
+#define _MX51_PAD_DISP2_DAT13__AUD6_TXC         IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0)
+#define _MX51_PAD_DISP2_DAT13__DISP2_DAT13      IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK       IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0)
+#define _MX51_PAD_DISP2_DAT13__USBH3_DATA5      IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0)
+#define _MX51_PAD_DISP2_DAT14__AUD6_TXFS        IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0)
+#define _MX51_PAD_DISP2_DAT14__DISP2_DAT14      IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT14__FEC_RDATA0       IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0)
+#define _MX51_PAD_DISP2_DAT14__USBH3_DATA6      IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0)
+#define _MX51_PAD_DISP2_DAT15__AUD6_RXFS        IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0)
+#define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS     IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT15__DISP2_DAT15      IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT15__FEC_TDATA0       IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0)
+#define _MX51_PAD_DISP2_DAT15__USBH3_DATA7      IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0)
+#define _MX51_PAD_SD1_CMD__AUD5_RXFS            IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0)
+#define _MX51_PAD_SD1_CMD__CSPI_MOSI            IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0)
+#define _MX51_PAD_SD1_CMD__SD1_CMD              IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_SD1_CLK__AUD5_RXC             IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0)
+#define _MX51_PAD_SD1_CLK__CSPI_SCLK            IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0)
+#define _MX51_PAD_SD1_CLK__SD1_CLK              IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_SD1_DATA0__AUD5_TXD           IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0)
+#define _MX51_PAD_SD1_DATA0__CSPI_MISO          IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0)
+#define _MX51_PAD_SD1_DATA0__SD1_DATA0          IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA0__EIM_DA0              IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA1__EIM_DA1              IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA2__EIM_DA2              IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA3__EIM_DA3              IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0)
+#define _MX51_PAD_SD1_DATA1__AUD5_RXD           IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0)
+#define _MX51_PAD_SD1_DATA1__SD1_DATA1          IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA4__EIM_DA4              IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA5__EIM_DA5              IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA6__EIM_DA6              IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA7__EIM_DA7              IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0)
+#define _MX51_PAD_SD1_DATA2__AUD5_TXC           IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0)
+#define _MX51_PAD_SD1_DATA2__SD1_DATA2          IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA10__EIM_DA10            IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA11__EIM_DA11            IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA8__EIM_DA8              IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA9__EIM_DA9              IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0)
+#define _MX51_PAD_SD1_DATA3__AUD5_TXFS          IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0)
+#define _MX51_PAD_SD1_DATA3__CSPI_SS1           IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0)
+#define _MX51_PAD_SD1_DATA3__SD1_DATA3          IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_0__CSPI_SS2             IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0)
+#define _MX51_PAD_GPIO1_0__GPIO1_0              IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_0__SD1_CD               IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_1__CSPI_MISO            IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0)
+#define _MX51_PAD_GPIO1_1__GPIO1_1              IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_1__SD1_WP               IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA12__EIM_DA12            IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA13__EIM_DA13            IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA14__EIM_DA14            IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0)
+#define _MX51_PAD_EIM_DA15__EIM_DA15            IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_CMD__CSPI_MOSI            IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0)
+#define _MX51_PAD_SD2_CMD__I2C1_SCL             IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0)
+#define _MX51_PAD_SD2_CMD__SD2_CMD              IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_CLK__CSPI_SCLK            IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0)
+#define _MX51_PAD_SD2_CLK__I2C1_SDA             IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0)
+#define _MX51_PAD_SD2_CLK__SD2_CLK              IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_DATA0__CSPI_MISO          IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0)
+#define _MX51_PAD_SD2_DATA0__SD1_DAT4           IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_DATA0__SD2_DATA0          IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_DATA1__SD1_DAT5           IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_DATA1__SD2_DATA1          IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_DATA1__USBH3_H2_DP        IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_DATA2__SD1_DAT6           IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_DATA2__SD2_DATA2          IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_DATA2__USBH3_H2_DM        IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_DATA3__CSPI_SS2           IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0)
+#define _MX51_PAD_SD2_DATA3__SD1_DAT7           IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0)
+#define _MX51_PAD_SD2_DATA3__SD2_DATA3          IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_2__CCM_OUT_2            IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_2__GPIO1_2              IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_2__I2C2_SCL             IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0)
+#define _MX51_PAD_GPIO1_2__PLL1_BYP             IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0)
+#define _MX51_PAD_GPIO1_2__PWM1_PWMO            IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_3__GPIO1_3              IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_3__I2C2_SDA             IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0)
+#define _MX51_PAD_GPIO1_3__PLL2_BYP             IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0)
+#define _MX51_PAD_GPIO1_3__PWM2_PWMO            IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0)
+#define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ    IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B  IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK        IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0)
+#define _MX51_PAD_GPIO1_4__EIM_RDY              IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0)
+#define _MX51_PAD_GPIO1_4__GPIO1_4              IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B         IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_5__CSI2_MCLK            IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_5__DISP2_PIN16          IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_5__GPIO1_5              IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B         IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_6__DISP2_PIN17          IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_6__GPIO1_6              IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_6__REF_EN_B             IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_7__CCM_OUT_0            IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_7__GPIO1_7              IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_7__SD2_WP               IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_7__SPDIF_OUT1           IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_8__CSI2_DATA_EN         IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0)
+#define _MX51_PAD_GPIO1_8__GPIO1_8              IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_8__SD2_CD               IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_8__USBH3_PWR            IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_9__CCM_OUT_1            IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_9__DISP2_D1_CS          IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_9__DISP2_SER_CS         IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_9__GPIO1_9              IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_9__SD2_LCTL             IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0)
+#define _MX51_PAD_GPIO1_9__USBH3_OC             IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0)
+
+/* The same pins as above but with the default pad control values applied */
+#define MX51_PAD_EIM_D16__AUD4_RXFS             (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D16__AUD5_TXD              (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D16__EIM_D16               (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D16__GPIO2_0               (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D16__I2C1_SDA              (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_EIM_D16__UART2_CTS             (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D16__USBH2_DATA0           (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D17__AUD5_RXD              (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D17__EIM_D17               (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D17__GPIO2_1               (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D17__UART2_RXD             (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D17__UART3_CTS             (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D17__USBH2_DATA1           (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D18__AUD5_TXC              (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D18__EIM_D18               (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D18__GPIO2_2               (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D18__UART2_TXD             (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D18__UART3_RTS             (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D18__USBH2_DATA2           (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D19__AUD4_RXC              (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D19__AUD5_TXFS             (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D19__EIM_D19               (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D19__GPIO2_3               (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D19__I2C1_SCL              (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_EIM_D19__UART2_RTS             (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D19__USBH2_DATA3           (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D20__AUD4_TXD              (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D20__EIM_D20               (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D20__GPIO2_4               (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB        (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D20__USBH2_DATA4           (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D21__AUD4_RXD              (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D21__EIM_D21               (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D21__GPIO2_5               (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB        (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D21__USBH2_DATA5           (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D22__AUD4_TXC              (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D22__EIM_D22               (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D22__GPIO2_6               (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D22__USBH2_DATA6           (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D23__AUD4_TXFS             (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D23__EIM_D23               (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D23__GPIO2_7               (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D23__SPDIF_OUT1            (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D23__USBH2_DATA7           (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D24__AUD6_RXFS             (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D24__EIM_D24               (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D24__GPIO2_8               (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D24__I2C2_SDA              (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_EIM_D24__UART3_CTS             (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D24__USBOTG_DATA0          (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D25__EIM_D25               (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D25__KEY_COL6              (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D25__UART2_CTS             (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D25__UART3_RXD             (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D25__USBOTG_DATA1          (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D26__EIM_D26               (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D26__KEY_COL7              (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D26__UART2_RTS             (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D26__UART3_TXD             (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D26__USBOTG_DATA2          (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D27__AUD6_RXC              (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D27__EIM_D27               (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D27__GPIO2_9               (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_D27__I2C2_SCL              (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_EIM_D27__UART3_RTS             (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_EIM_D27__USBOTG_DATA3          (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D28__AUD6_TXD              (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D28__EIM_D28               (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D28__KEY_ROW4              (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D28__USBOTG_DATA4          (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D29__AUD6_RXD              (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D29__EIM_D29               (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D29__KEY_ROW5              (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D29__USBOTG_DATA5          (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D30__AUD6_TXC              (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D30__EIM_D30               (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D30__KEY_ROW6              (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D30__USBOTG_DATA6          (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D31__AUD6_TXFS             (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D31__EIM_D31               (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D31__KEY_ROW7              (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_D31__USBOTG_DATA7          (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A16__EIM_A16               (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A16__GPIO2_10              (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0         (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A17__EIM_A17               (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A17__GPIO2_11              (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1         (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A18__BOOT_LPB0             (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A18__EIM_A18               (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A18__GPIO2_12              (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A19__BOOT_LPB1             (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A19__EIM_A19               (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A19__GPIO2_13              (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A20__BOOT_UART_SRC0        (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A20__EIM_A20               (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A20__GPIO2_14              (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A21__BOOT_UART_SRC1        (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A21__EIM_A21               (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A21__GPIO2_15              (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A22__EIM_A22               (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A22__GPIO2_16              (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A23__BOOT_HPN_EN           (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A23__EIM_A23               (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A23__GPIO2_17              (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A24__EIM_A24               (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A24__GPIO2_18              (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A24__USBH2_CLK             (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A25__DISP1_PIN4            (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A25__EIM_A25               (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A25__GPIO2_19              (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A25__USBH2_DIR             (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A26__CSI1_DATA_EN          (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A26__DISP2_EXT_CLK         (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A26__EIM_A26               (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A26__GPIO2_20              (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A26__USBH2_STP             (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A27__CSI2_DATA_EN          (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A27__DISP1_PIN1            (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A27__EIM_A27               (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_A27__GPIO2_21              (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_A27__USBH2_NXT             (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB0__EIM_EB0               (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB1__EIM_EB1               (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__AUD5_RXFS             (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__CSI1_D2               (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__EIM_EB2               (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__FEC_MDIO              (_MX51_PAD_EIM_EB2__FEC_MDIO | \
+                MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
+                PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
+#define MX51_PAD_EIM_EB2__GPIO2_22              (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_EB2__GPT_CMPOUT1           (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__AUD5_RXC              (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__CSI1_D3               (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__EIM_EB3               (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__FEC_RDATA1            (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__GPIO2_23              (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_EB3__GPT_CMPOUT2           (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_OE__EIM_OE                 (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_OE__GPIO2_24               (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS0__EIM_CS0               (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS0__GPIO2_25              (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS1__EIM_CS1               (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS1__GPIO2_26              (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__AUD5_TXD              (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__CSI1_D4               (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__EIM_CS2               (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__FEC_RDATA2            (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__GPIO2_27              (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS2__USBOTG_STP            (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__AUD5_RXD              (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__CSI1_D5               (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__EIM_CS3               (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__FEC_RDATA3            (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__GPIO2_28              (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS3__USBOTG_NXT            (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS4__AUD5_TXC              (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS4__CSI1_D6               (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS4__EIM_CS4               (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS4__FEC_RX_ER             (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
+#define MX51_PAD_EIM_CS4__GPIO2_29              (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS4__USBOTG_CLK            (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__AUD5_TXFS             (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__CSI1_D7               (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK         (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__EIM_CS5               (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__FEC_CRS               (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
+#define MX51_PAD_EIM_CS5__GPIO2_30              (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CS5__USBOTG_DIR            (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DTACK__EIM_DTACK           (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DTACK__GPIO2_31            (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_LBA__EIM_LBA               (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_LBA__GPIO3_1               (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_EIM_CRE__EIM_CRE               (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_CRE__GPIO3_2               (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DRAM_CS1__DRAM_CS1             (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WE_B__GPIO3_3            (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_WE_B__NANDF_WE_B         (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WE_B__PATA_DIOW          (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WE_B__SD3_DATA0          (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RE_B__GPIO3_4            (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RE_B__NANDF_RE_B         (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RE_B__PATA_DIOR          (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RE_B__SD3_DATA1          (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_ALE__GPIO3_5             (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_ALE__NANDF_ALE           (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN      (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CLE__GPIO3_6             (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CLE__NANDF_CLE           (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CLE__PATA_RESET_B        (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WP_B__GPIO3_7            (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_WP_B__NANDF_WP_B         (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WP_B__PATA_DMACK         (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_WP_B__SD3_DATA2          (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__ECSPI2_SS1          (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__GPIO3_8             (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__NANDF_RB0           (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__PATA_DMARQ          (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB0__SD3_DATA3           (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__CSPI_MOSI           (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__ECSPI2_RDY          (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__GPIO3_9             (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__NANDF_RB1           (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__PATA_IORDY          (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB1__SD4_CMD             (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__DISP2_WAIT          (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__FEC_COL             (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
+#define MX51_PAD_NANDF_RB2__GPIO3_10            (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__NANDF_RB2           (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__USBH3_H3_DP         (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB2__USBH3_NXT           (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__DISP1_WAIT          (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__FEC_RX_CLK          (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
+#define MX51_PAD_NANDF_RB3__GPIO3_11            (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__NANDF_RB3           (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__USBH3_CLK           (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RB3__USBH3_H3_DM         (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO_NAND__GPIO_NAND           (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_GPIO_NAND__PATA_INTRQ          (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS0__GPIO3_16            (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS0__NANDF_CS0           (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS1__GPIO3_17            (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS1__NANDF_CS1           (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__CSPI_SCLK           (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__FEC_TX_ER           (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS2__GPIO3_18            (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__NANDF_CS2           (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__PATA_CS_0           (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__SD4_CLK             (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS2__USBH3_H1_DP         (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__FEC_MDC             (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS3__GPIO3_19            (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__NANDF_CS3           (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__PATA_CS_1           (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__SD4_DAT0            (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS3__USBH3_H1_DM         (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__FEC_TDATA1          (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS4__GPIO3_20            (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__NANDF_CS4           (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__PATA_DA_0           (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__SD4_DAT1            (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS4__USBH3_STP           (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__FEC_TDATA2          (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS5__GPIO3_21            (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__NANDF_CS5           (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__PATA_DA_1           (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__SD4_DAT2            (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS5__USBH3_DIR           (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__CSPI_SS3            (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__FEC_TDATA3          (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS6__GPIO3_22            (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__NANDF_CS6           (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__PATA_DA_2           (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS6__SD4_DAT3            (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN           (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_CS7__GPIO3_23            (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS7__NANDF_CS7           (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_CS7__SD3_CLK             (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0      (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
+#define MX51_PAD_NANDF_RDY_INT__GPIO3_24        (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_D15__GPIO3_25            (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D15__NANDF_D15           (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D15__PATA_DATA15         (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D15__SD3_DAT7            (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D14__ECSPI2_SS3          (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_D14__GPIO3_26            (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D14__NANDF_D14           (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D14__PATA_DATA14         (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D14__SD3_DAT6            (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D13__ECSPI2_SS2          (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_D13__GPIO3_27            (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D13__NANDF_D13           (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D13__PATA_DATA13         (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D13__SD3_DAT5            (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D12__ECSPI2_SS1          (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_NANDF_D12__GPIO3_28            (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D12__NANDF_D12           (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D12__PATA_DATA12         (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D12__SD3_DAT4            (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D11__FEC_RX_DV           (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D11__GPIO3_29            (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D11__NANDF_D11           (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D11__PATA_DATA11         (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D11__SD3_DATA3           (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D10__GPIO3_30            (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D10__NANDF_D10           (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D10__PATA_DATA10         (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D10__SD3_DATA2           (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D9__FEC_RDATA0           (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
+#define MX51_PAD_NANDF_D9__GPIO3_31             (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D9__NANDF_D9             (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D9__PATA_DATA9           (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D9__SD3_DATA1            (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D8__FEC_TDATA0           (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_NANDF_D8__GPIO4_0              (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D8__NANDF_D8             (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D8__PATA_DATA8           (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D8__SD3_DATA0            (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D7__GPIO4_1              (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D7__NANDF_D7             (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D7__PATA_DATA7           (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D7__USBH3_DATA0          (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D6__GPIO4_2              (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D6__NANDF_D6             (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D6__PATA_DATA6           (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D6__SD4_LCTL             (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D6__USBH3_DATA1          (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D5__GPIO4_3              (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D5__NANDF_D5             (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D5__PATA_DATA5           (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D5__SD4_WP               (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D5__USBH3_DATA2          (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D4__GPIO4_4              (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D4__NANDF_D4             (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D4__PATA_DATA4           (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D4__SD4_CD               (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D4__USBH3_DATA3          (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D3__GPIO4_5              (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D3__NANDF_D3             (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D3__PATA_DATA3           (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D3__SD4_DAT4             (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D3__USBH3_DATA4          (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D2__GPIO4_6              (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D2__NANDF_D2             (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D2__PATA_DATA2           (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D2__SD4_DAT5             (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D2__USBH3_DATA5          (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D1__GPIO4_7              (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D1__NANDF_D1             (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D1__PATA_DATA1           (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D1__SD4_DAT6             (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D1__USBH3_DATA6          (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D0__GPIO4_8              (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_NANDF_D0__NANDF_D0             (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D0__PATA_DATA0           (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D0__SD4_DAT7             (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_NANDF_D0__USBH3_DATA7          (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D8__CSI1_D8               (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D8__GPIO3_12              (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI1_D9__CSI1_D9               (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D9__GPIO3_13              (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI1_D10__CSI1_D10             (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D11__CSI1_D11             (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D12__CSI1_D12             (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D13__CSI1_D13             (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D14__CSI1_D14             (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D15__CSI1_D15             (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D16__CSI1_D16             (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D17__CSI1_D17             (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D18__CSI1_D18             (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_D19__CSI1_D19             (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_VSYNC__GPIO3_14           (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_HSYNC__GPIO3_15           (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D12__CSI2_D12             (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D12__GPIO4_9              (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_D13__CSI2_D13             (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D13__GPIO4_10             (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_D14__CSI2_D14             (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D15__CSI2_D15             (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D16__CSI2_D16             (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D17__CSI2_D17             (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D18__CSI2_D18             (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D18__GPIO4_11             (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_D19__CSI2_D19             (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_D19__GPIO4_12             (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC         (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_VSYNC__GPIO4_13           (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC         (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_HSYNC__GPIO4_14           (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK       (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSI2_PIXCLK__GPIO4_15          (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_I2C1_CLK__GPIO4_16             (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_I2C1_CLK__I2C1_CLK             (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_I2C1_DAT__GPIO4_17             (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_I2C1_DAT__I2C1_DAT             (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD          (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_TXD__GPIO4_18          (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD          (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_RXD__GPIO4_19          (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_RXD__UART3_RXD         (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_CK__AUD3_TXC           (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_CK__GPIO4_20           (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS          (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_FS__GPIO4_21           (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_AUD3_BB_FS__UART3_TXD          (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_MOSI__GPIO4_22           (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_MOSI__I2C1_SDA           (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_CSPI1_MISO__AUD4_RXD           (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO        (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_MISO__GPIO4_23           (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS0__AUD4_TXC            (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0          (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS0__GPIO4_24            (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS1__AUD4_TXD            (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1          (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_SS1__GPIO4_25            (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_RDY__AUD4_TXFS           (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY          (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_RDY__GPIO4_26            (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_CSPI1_SCLK__GPIO4_27           (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_CSPI1_SCLK__I2C1_SCL           (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_UART1_RXD__GPIO4_28            (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART1_RXD__UART1_RXD           (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART1_TXD__GPIO4_29            (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART1_TXD__PWM2_PWMO           (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART1_TXD__UART1_TXD           (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART1_RTS__GPIO4_30            (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART1_RTS__UART1_RTS           (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART1_CTS__GPIO4_31            (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART1_CTS__UART1_CTS           (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART2_RXD__FIRI_TXD            (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART2_RXD__GPIO1_20            (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART2_RXD__UART2_RXD           (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART2_TXD__FIRI_RXD            (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART2_TXD__GPIO1_21            (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART2_TXD__UART2_TXD           (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART3_RXD__CSI1_D0             (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART3_RXD__GPIO1_22            (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART3_RXD__UART1_DTR           (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART3_RXD__UART3_RXD           (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART3_TXD__CSI1_D1             (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_UART3_TXD__GPIO1_23            (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_UART3_TXD__UART1_DSR           (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_UART3_TXD__UART3_TXD           (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_OWIRE_LINE__GPIO1_24           (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_OWIRE_LINE__OWIRE_LINE         (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_OWIRE_LINE__SPDIF_OUT          (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_ROW0__KEY_ROW0             (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_ROW1__KEY_ROW1             (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_ROW2__KEY_ROW2             (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_ROW3__KEY_ROW3             (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL0__KEY_COL0             (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL0__PLL1_BYP             (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL1__KEY_COL1             (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL1__PLL2_BYP             (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL2__KEY_COL2             (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL2__PLL3_BYP             (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL3__KEY_COL3             (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL4__I2C2_SCL             (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_KEY_COL4__KEY_COL4             (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL4__SPDIF_OUT1           (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL4__UART1_RI             (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_KEY_COL4__UART3_RTS            (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_KEY_COL5__I2C2_SDA             (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_KEY_COL5__KEY_COL5             (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_KEY_COL5__UART1_DCD            (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_KEY_COL5__UART3_CTS            (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_CLK__CSPI_SCLK           (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_CLK__GPIO1_25            (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_CLK__I2C2_SCL            (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_USBH1_CLK__USBH1_CLK           (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DIR__CSPI_MOSI           (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DIR__GPIO1_26            (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DIR__I2C2_SDA            (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_USBH1_DIR__USBH1_DIR           (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_STP__CSPI_RDY            (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_STP__GPIO1_27            (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_STP__UART3_RXD           (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_STP__USBH1_STP           (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_NXT__CSPI_MISO           (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_NXT__GPIO1_28            (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_NXT__UART3_TXD           (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_NXT__USBH1_NXT           (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA0__GPIO1_11          (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA0__UART2_CTS         (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA1__GPIO1_12          (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA1__UART2_RXD         (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA2__GPIO1_13          (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA2__UART2_TXD         (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA3__GPIO1_14          (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA3__UART2_RTS         (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA4__CSPI_SS0          (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA4__GPIO1_15          (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA5__CSPI_SS1          (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA5__GPIO1_16          (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA6__CSPI_SS3          (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA6__GPIO1_17          (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3        (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3        (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA7__GPIO1_18          (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
+#define MX51_PAD_DI1_PIN11__DI1_PIN11           (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN11__ECSPI1_SS2          (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_DI1_PIN11__GPIO3_0             (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN12__DI1_PIN12           (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN12__GPIO3_1             (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN13__DI1_PIN13           (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN13__GPIO3_2             (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DI1_D0_CS__DI1_D0_CS           (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_D0_CS__GPIO3_3             (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DI1_D1_CS__DI1_D1_CS           (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN14         (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_D1_CS__DISP1_PIN5          (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_D1_CS__GPIO3_4             (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1     (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5        (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6     (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6        (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17    (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7     (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7        (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK   (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16     (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8      (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS   (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISPB2_SER_RS__GPIO3_8         (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC       (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG    (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT8__BOOT_SRC0          (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT9__BOOT_SRC1          (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE   (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2    (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL      (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0     (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1     (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH    (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0   (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1   (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0  (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN11       (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT18__DISP2_PIN5        (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1  (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN12       (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT19__DISP2_PIN6        (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0    (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN13       (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT20__DISP2_PIN7        (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1    (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN14       (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT21__DISP2_PIN8        (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0    (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS       (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT22__DISP2_DAT16       (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1    (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS       (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT23__DISP2_DAT17       (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS      (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN3__DI1_PIN3             (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI1_PIN2__DI1_PIN2             (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP2__DISP1_SER_CLK          (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP2__DISP2_WAIT             (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP3__CSI1_DATA_EN           (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP3__DISP1_SER_DIO          (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP3__FEC_TX_ER              (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN         (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN4__DI2_PIN4             (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN4__FEC_CRS              (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN2__DI2_PIN2             (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN2__FEC_MDC              (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DI2_PIN3__DI2_PIN3             (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_PIN3__FEC_MDIO             (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP4__DI2_PIN15              (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP4__DISP1_SER_DIN          (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP4__DISP2_PIN1             (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DI_GP4__FEC_RDATA2             (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT0__FEC_RDATA3         (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT0__KEY_COL6           (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT0__UART3_RXD          (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT0__USBH3_CLK          (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT1__FEC_RX_ER          (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT1__KEY_COL7           (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT1__UART3_TXD          (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT1__USBH3_DIR          (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT6__DISP2_DAT6         (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT6__FEC_TDATA1         (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DISP2_DAT6__GPIO1_19           (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT6__KEY_ROW4           (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT6__USBH3_STP          (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT7__DISP2_DAT7         (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT7__FEC_TDATA2         (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DISP2_DAT7__GPIO1_29           (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT7__KEY_ROW5           (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT7__USBH3_NXT          (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT8__DISP2_DAT8         (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT8__FEC_TDATA3         (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DISP2_DAT8__GPIO1_30           (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT8__KEY_ROW6           (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT8__USBH3_DATA0        (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT9__AUD6_RXC           (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT9__DISP2_DAT9         (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT9__FEC_TX_EN          (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DISP2_DAT9__GPIO1_31           (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT9__USBH3_DATA1        (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS      (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT10__FEC_COL           (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT10__KEY_ROW7          (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT10__USBH3_DATA2       (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT11__AUD6_TXD          (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK        (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT11__GPIO1_10          (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT11__USBH3_DATA3       (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT12__AUD6_RXD          (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT12__FEC_RX_DV         (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT12__USBH3_DATA4       (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT13__AUD6_TXC          (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK        (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
+#define MX51_PAD_DISP2_DAT13__USBH3_DATA5       (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT14__AUD6_TXFS         (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT14__FEC_RDATA0        (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
+#define MX51_PAD_DISP2_DAT14__USBH3_DATA6       (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT15__AUD6_RXFS         (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS      (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_DISP2_DAT15__FEC_TDATA0        (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
+#define MX51_PAD_DISP2_DAT15__USBH3_DATA7       (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_CMD__AUD5_RXFS             (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_CMD__CSPI_MOSI             (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_CMD__SD1_CMD               (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD1_CLK__AUD5_RXC              (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_CLK__CSPI_SCLK             (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_CLK__SD1_CLK               (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
+#define MX51_PAD_SD1_DATA0__AUD5_TXD            (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA0__CSPI_MISO           (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA0__EIM_DA0               (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA1__EIM_DA1               (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA2__EIM_DA2               (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA3__EIM_DA3               (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA1__AUD5_RXD            (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA4__EIM_DA4               (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA5__EIM_DA5               (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA6__EIM_DA6               (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA7__EIM_DA7               (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA2__AUD5_TXC            (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA10__EIM_DA10             (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA11__EIM_DA11             (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA8__EIM_DA8               (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA9__EIM_DA9               (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA3__AUD5_TXFS           (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD1_DATA3__CSPI_SS1            (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_0__CSPI_SS2              (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_GPIO1_0__GPIO1_0               (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_0__SD1_CD                (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
+#define MX51_PAD_GPIO1_1__CSPI_MISO             (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_GPIO1_1__GPIO1_1               (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_1__SD1_WP                (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
+#define MX51_PAD_EIM_DA12__EIM_DA12             (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA13__EIM_DA13             (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA14__EIM_DA14             (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_EIM_DA15__EIM_DA15             (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_CMD__CSPI_MOSI             (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD2_CMD__I2C1_SCL              (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_SD2_CMD__SD2_CMD               (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
+#define MX51_PAD_SD2_CLK__CSPI_SCLK             (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD2_CLK__I2C1_SDA              (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_SD2_CLK__SD2_CLK               (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
+#define MX51_PAD_SD2_DATA0__CSPI_MISO           (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD2_DATA0__SD1_DAT4            (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA1__SD1_DAT5            (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA1__USBH3_H2_DP         (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA2__SD1_DAT6            (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA2__USBH3_H2_DM         (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA3__CSPI_SS2            (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
+#define MX51_PAD_SD2_DATA3__SD1_DAT7            (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_2__CCM_OUT_2             (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_2__GPIO1_2               (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_2__I2C2_SCL              (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_GPIO1_2__PLL1_BYP              (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_2__PWM1_PWMO             (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_3__GPIO1_3               (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_3__I2C2_SDA              (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
+#define MX51_PAD_GPIO1_3__PLL2_BYP              (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_3__PWM2_PWMO             (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK         (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_4__EIM_RDY               (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_4__GPIO1_4               (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_5__CSI2_MCLK             (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_5__DISP2_PIN16           (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_5__GPIO1_5               (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_6__DISP2_PIN17           (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_6__GPIO1_6               (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_6__REF_EN_B              (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_7__CCM_OUT_0             (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_7__GPIO1_7               (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_7__SD2_WP                (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
+#define MX51_PAD_GPIO1_7__SPDIF_OUT1            (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_8__CSI2_DATA_EN          (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_8__GPIO1_8               (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_8__SD2_CD                (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
+#define MX51_PAD_GPIO1_8__USBH3_PWR             (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__CCM_OUT_1             (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__DISP2_D1_CS           (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__DISP2_SER_CS          (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__GPIO1_9               (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__SD2_LCTL              (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX51_PAD_GPIO1_9__USBH3_OC              (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
 
 #endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
new file mode 100644
index 000000000000..5deee019c29e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc..
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_IOMUX_MX53_H__
+#define __MACH_IOMUX_MX53_H__
+
+#include <mach/iomux-v3.h>
+
+/*
+ * various IOMUX alternate output functions (1-7)
+ */
+typedef enum iomux_config {
+        IOMUX_CONFIG_ALT0,
+        IOMUX_CONFIG_ALT1,
+        IOMUX_CONFIG_ALT2,
+        IOMUX_CONFIG_ALT3,
+        IOMUX_CONFIG_ALT4,
+        IOMUX_CONFIG_ALT5,
+        IOMUX_CONFIG_ALT6,
+        IOMUX_CONFIG_ALT7,
+        IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
+        IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
+} iomux_pin_cfg_t;
+
+/* These 2 defines are for pins that may not have a mux register, but could
+ * have a pad setting register, and vice-versa. */
+#define NON_MUX_I       0x00
+#define NON_PAD_I       0x00
+
+#define MX53_UART_PAD_CTRL              (PAD_CTL_PKE | PAD_CTL_PUE |    \
+                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+/* UART1 */
+#define MX53_PAD_CSI0_D10__UART1_TXD    IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_CSI0_D11__UART1_RXD    IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_DIOW__UART1_TXD    IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_DMACK__UART1_RXD   IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL)
+
+/* UART2 */
+#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD       IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_DMARQ__UART2_TXD   IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_DIOR__UART2_RTS    IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_INTRQ__UART2_CTS   IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL)
+
+/* UART3 */
+#define MX53_PAD_ATA_CS_0__UART3_TXD    IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_CS_1__UART3_RXD    IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_DA_1__UART3_CTS    IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL)
+#define MX53_PAD_ATA_DA_2__UART3_RTS    IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
+
+#define MX53_PAD_GPIO_19__GPIO_4_5              IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL0__GPIO_4_6             IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW0__GPIO_4_7             IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL1__GPIO_4_8             IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW1__GPIO_4_9             IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL2__GPIO_4_10            IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW2__GPIO_4_11    IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL3__GPIO_4_12            IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW3__GPIO_4_13    IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_COL4__GPIO_4_14            IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_KEY_ROW4__GPIO_4_15    IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD       IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16        IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN15__GPIO_4_17   IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN2__GPIO_4_18            IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN3__GPIO_4_19            IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DI0_PIN4__GPIO_4_20            IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT0__GPIO_4_21  IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT1__GPIO_4_22  IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT2__GPIO_4_23  IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT3__GPIO_4_24  IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT4__GPIO_4_25  IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT5__GPIO_4_26  IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT6__GPIO_4_27  IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT7__GPIO_4_28  IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT8__GPIO_4_29  IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT9__GPIO_4_30  IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT11__GPIO_5_5  IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT12__GPIO_5_6  IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT13__GPIO_5_7  IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT14__GPIO_5_8  IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT15__GPIO_5_9  IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_MCLK__GPIO_5_19   IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20        IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_VSYNC__GPIO_5_21  IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D4__GPIO_5_22             IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D5__GPIO_5_23             IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D6__GPIO_5_24             IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D7__GPIO_5_25             IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D8__GPIO_5_26             IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D9__GPIO_5_27             IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D10__GPIO_5_28            IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D11__GPIO_5_29            IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D12__GPIO_5_30            IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D13__GPIO_5_31            IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D14__GPIO_6_0             IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D15__GPIO_6_1             IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D16__GPIO_6_2             IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D17__GPIO_6_3             IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D18__GPIO_6_4             IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_CSI0_D19__GPIO_6_5             IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_CSI0__NVCC_CSI0   IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_TMS__JTAG_TMS             IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_MOD__JTAG_MOD             IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_TDI__JTAG_TDI             IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_TCK__JTAG_TCK             IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_JTAG_TDO__JTAG_TDO             IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A25__GPIO_5_2              IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB2__GPIO_2_30             IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D16__GPIO_3_16             IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D17__GPIO_3_17             IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D18__GPIO_3_18             IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D19__GPIO_3_19             IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D20__GPIO_3_20             IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D21__GPIO_3_21             IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D22__GPIO_3_22             IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D23__GPIO_3_23             IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB3__GPIO_2_31             IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D24__GPIO_3_24             IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D25__GPIO_3_25             IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D26__GPIO_3_26             IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D27__GPIO_3_27             IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D28__GPIO_3_28             IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D29__GPIO_3_29             IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D30__GPIO_3_30             IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_D31__GPIO_3_31             IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_EIM1__NVCC_EIM1   IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A24__GPIO_5_4              IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A23__GPIO_6_6              IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A21__GPIO_2_17             IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A20__GPIO_2_18             IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A19__GPIO_2_19             IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A18__GPIO_2_20             IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A17__GPIO_2_21             IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_A16__GPIO_2_22             IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS0__GPIO_2_23             IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_CS1__GPIO_2_24             IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_OE__GPIO_2_25              IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_RW__GPIO_2_26              IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_LBA__GPIO_2_27             IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_EIM4__NVCC_EIM4   IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB0__GPIO_2_28             IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_EB1__GPIO_2_29             IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA0__GPIO_3_0              IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA1__GPIO_3_1              IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA2__GPIO_3_2              IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA3__GPIO_3_3              IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA4__GPIO_3_4              IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA5__GPIO_3_5              IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA6__GPIO_3_6              IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA7__GPIO_3_7              IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA8__GPIO_3_8              IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA9__GPIO_3_9              IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA10__GPIO_3_10            IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA11__GPIO_3_11            IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA12__GPIO_3_12            IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA13__GPIO_3_13            IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA14__GPIO_3_14            IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_DA15__GPIO_3_15            IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WE_B__GPIO_6_12  IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RE_B__GPIO_6_13  IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_WAIT__GPIO_5_0             IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_EIM_BCLK__EIM_BCLK             IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_EIM7__NVCC_EIM7   IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_10__GPIO_4_0              IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_11__GPIO_4_1              IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_12__GPIO_4_2              IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_13__GPIO_4_3              IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_14__GPIO_4_4              IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_DQM3__DRAM_DQM3   IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1       IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_DQM2__DRAM_DQM2   IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1       IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1       IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_CAS__DRAM_CAS             IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0       IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0       IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_DQM0__DRAM_DQM0   IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_RAS__DRAM_RAS             IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0       IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_DRAM_DQM1__DRAM_DQM1   IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ       IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ   IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CLE__GPIO_6_7            IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_ALE__GPIO_6_8    IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_WP_B__GPIO_6_9   IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_RB0__GPIO_6_10   IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS0__GPIO_6_11   IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS1__GPIO_6_14   IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS2__GPIO_6_15   IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NANDF_CS3__GPIO_6_16   IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDIO__GPIO_1_22            IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RX_ER__GPIO_1_24   IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_CRS_DV__GPIO_1_25  IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD1__GPIO_1_26            IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_RXD0__GPIO_1_27            IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TX_EN__GPIO_1_28   IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD1__GPIO_1_29            IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_TXD0__GPIO_1_30            IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_FEC_MDC__GPIO_1_31             IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_FEC__NVCC_FEC             IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DIOW__GPIO_6_17    IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DMACK__GPIO_6_18   IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DMARQ__GPIO_7_0    IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1        IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_INTRQ__GPIO_7_2            IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DIOR__GPIO_7_3             IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_RESET_B__GPIO_7_4  IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_IORDY__GPIO_7_5            IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DA_0__GPIO_7_6             IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DA_1__GPIO_7_7             IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DA_2__GPIO_7_8             IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_CS_0__GPIO_7_9             IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_CS_1__GPIO_7_10            IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_ATA2__NVCC_ATA2   IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA0__GPIO_2_0    IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA1__GPIO_2_1    IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA2__GPIO_2_2    IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA3__GPIO_2_3    IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA4__GPIO_2_4    IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA5__GPIO_2_5    IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA6__GPIO_2_6    IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA7__GPIO_2_7    IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA8__GPIO_2_8    IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA9__GPIO_2_9    IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA10__GPIO_2_10  IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA11__GPIO_2_11  IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA12__GPIO_2_12  IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA13__GPIO_2_13  IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA14__GPIO_2_14  IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_ATA_DATA15__GPIO_2_15  IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_ATA0__NVCC_ATA0   IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA0__GPIO_1_16   IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA1__GPIO_1_17   IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CMD__GPIO_1_18             IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA2__GPIO_1_19   IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_CLK__GPIO_1_20             IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD1_DATA3__GPIO_1_21   IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_SD1__NVCC_SD1             IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CLK__GPIO_1_10             IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_CMD__GPIO_1_11             IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA3__GPIO_1_12   IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA2__GPIO_1_13   IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA1__GPIO_1_14   IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_SD2_DATA0__GPIO_1_15   IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_SD2__NVCC_SD2             IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_0__GPIO_1_0               IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_1__GPIO_1_1               IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_9__GPIO_1_9               IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_3__GPIO_1_3               IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_6__GPIO_1_6               IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_2__GPIO_1_2               IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_4__GPIO_1_4               IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_5__GPIO_1_5               IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_7__GPIO_1_7               IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__GPIO_1_8               IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_16__GPIO_7_11             IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_17__GPIO_7_12             IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_18__GPIO_7_13             IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_NVCC_GPIO__NVCC_GPIO   IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_POR_B__POR_B                   IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_TEST_MODE__TEST_MODE   IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_ADDDS__GRP_ADDDS   IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL       IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDRPK__GRP_DDRPK   IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3   IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE       IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_B0DS__GRP_B0DS             IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_B1DS__GRP_B1DS             IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_CTLDS__GRP_CTLDS   IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE     IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_B2DS__GRP_B2DS             IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+#define MX53_PAD_GRP_B3DS__GRP_B3DS             IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
+
+#endif  /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 0880a4a1aed1..2277b01c855d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -42,28 +42,44 @@
  * If <padname> or <padmode> refers to a GPIO, it is named
  * GPIO_<unit>_<num>
  *
- */
-
-struct pad_desc {
-        unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */
-        unsigned mux_mode:8;
-        unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */
-#define NO_PAD_CTRL     (1 << 16)
-        unsigned pad_ctrl:17;
-        unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */
-        unsigned select_input:3;
-};
-
-#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \
-                _select_input, _pad_ctrl)                               \
-                {                                                       \
-                        .mux_ctrl_ofs     = _mux_ctrl_ofs,              \
-                        .mux_mode         = _mux_mode,                  \
-                        .pad_ctrl_ofs     = _pad_ctrl_ofs,              \
-                        .pad_ctrl         = _pad_ctrl,                  \
-                        .select_input_ofs = _select_input_ofs,          \
-                        .select_input     = _select_input,              \
-                }
+ * IOMUX/PAD Bit field definitions
+ *
+ * MUX_CTRL_OFS:            0..11 (12)
+ * PAD_CTRL_OFS:           12..23 (12)
+ * SEL_INPUT_OFS:          24..35 (12)
+ * MUX_MODE + SION:        36..40  (5)
+ * PAD_CTRL + NO_PAD_CTRL: 41..57 (17)
+ * SEL_INP:                58..61  (4)
+ * reserved:                 63    (1)
+*/
+
+typedef u64 iomux_v3_cfg_t;
+
+#define MUX_CTRL_OFS_SHIFT      0
+#define MUX_CTRL_OFS_MASK       ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
+#define MUX_PAD_CTRL_OFS_SHIFT  12
+#define MUX_PAD_CTRL_OFS_MASK   ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)
+#define MUX_SEL_INPUT_OFS_SHIFT 24
+#define MUX_SEL_INPUT_OFS_MASK  ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)
+
+#define MUX_MODE_SHIFT          36
+#define MUX_MODE_MASK           ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
+#define MUX_PAD_CTRL_SHIFT      41
+#define MUX_PAD_CTRL_MASK       ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
+#define NO_PAD_CTRL             ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 16))
+#define MUX_SEL_INPUT_SHIFT     58
+#define MUX_SEL_INPUT_MASK      ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
+
+#define MUX_PAD_CTRL(x)         ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
+
+#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
+                _sel_input, _pad_ctrl)                                  \
+        (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) |      \
+                ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) |       \
+                ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
+                ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) |   \
+                ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
+                ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
 
 /*
  * Use to set PAD control
@@ -107,13 +123,13 @@ struct pad_desc {
 /*
  * setups a single pad in the iomuxer
  */
-int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
+int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 
 /*
  * setups mutliple pads
  * convenient way to call the above function with tables
  */
-int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
+int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
 
 /*
  * Initialise the iomux controller
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 86781f7b0c0c..58a49cc83797 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -23,13 +23,17 @@
 #define MXC_GPIO_IRQ_START      MXC_INTERNAL_IRQS
 
 /* these are ordered by size to support multi-SoC kernels */
-#if defined CONFIG_ARCH_MX2
+#if defined CONFIG_ARCH_MX53
+#define MXC_GPIO_IRQS           (32 * 7)
+#elif defined CONFIG_ARCH_MX2
+#define MXC_GPIO_IRQS           (32 * 6)
+#elif defined CONFIG_ARCH_MX50
 #define MXC_GPIO_IRQS           (32 * 6)
 #elif defined CONFIG_ARCH_MX1
 #define MXC_GPIO_IRQS           (32 * 4)
 #elif defined CONFIG_ARCH_MX25
 #define MXC_GPIO_IRQS           (32 * 4)
-#elif defined CONFIG_ARCH_MX5
+#elif defined CONFIG_ARCH_MX51
 #define MXC_GPIO_IRQS           (32 * 4)
 #elif defined CONFIG_ARCH_MXC91231
 #define MXC_GPIO_IRQS           (32 * 4)
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 564ec9dbc93d..83861408133f 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -16,7 +16,9 @@
 #define MX25_PHYS_OFFSET        UL(0x80000000)
 #define MX27_PHYS_OFFSET        UL(0xa0000000)
 #define MX3x_PHYS_OFFSET        UL(0x80000000)
+#define MX50_PHYS_OFFSET        UL(0x70000000)
 #define MX51_PHYS_OFFSET        UL(0x90000000)
+#define MX53_PHYS_OFFSET        UL(0x70000000)
 #define MXC91231_PHYS_OFFSET    UL(0x90000000)
 
 #if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
@@ -32,8 +34,12 @@
 #  define PHYS_OFFSET           MX3x_PHYS_OFFSET
 # elif defined CONFIG_ARCH_MXC91231
 #  define PHYS_OFFSET           MXC91231_PHYS_OFFSET
-# elif defined CONFIG_ARCH_MX5
+# elif defined CONFIG_ARCH_MX50
+#  define PHYS_OFFSET           MX50_PHYS_OFFSET
+# elif defined CONFIG_ARCH_MX51
 #  define PHYS_OFFSET           MX51_PHYS_OFFSET
+# elif defined CONFIG_ARCH_MX53
+#  define PHYS_OFFSET           MX53_PHYS_OFFSET
 # endif
 #endif
 
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 641b24618239..75d96214b831 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -19,7 +19,6 @@
  */
 #define MX1_IO_BASE_ADDR        0x00200000
 #define MX1_IO_SIZE             SZ_1M
-#define MX1_IO_BASE_ADDR_VIRT   VMALLOC_END
 
 #define MX1_CS0_PHYS            0x10000000
 #define MX1_CS0_SIZE            0x02000000
@@ -66,6 +65,10 @@
 #define MX1_CCM_BASE_ADDR               (0x1B000 + MX1_IO_BASE_ADDR)
 #define MX1_SCM_BASE_ADDR               (0x1B804 + MX1_IO_BASE_ADDR)
 #define MX1_GPIO_BASE_ADDR              (0x1C000 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO1_BASE_ADDR             (0x1C000 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO2_BASE_ADDR             (0x1C100 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO3_BASE_ADDR             (0x1C200 + MX1_IO_BASE_ADDR)
+#define MX1_GPIO4_BASE_ADDR             (0x1C300 + MX1_IO_BASE_ADDR)
 #define MX1_EIM_BASE_ADDR               (0x20000 + MX1_IO_BASE_ADDR)
 #define MX1_SDRAMC_BASE_ADDR            (0x21000 + MX1_IO_BASE_ADDR)
 #define MX1_MMA_BASE_ADDR               (0x22000 + MX1_IO_BASE_ADDR)
@@ -73,12 +76,12 @@
 #define MX1_CSI_BASE_ADDR               (0x24000 + MX1_IO_BASE_ADDR)
 
 /* macro to get at IO space when running virtually */
-#define MX1_IO_ADDRESS(x) (                                             \
-        IMX_IO_ADDRESS(x, MX1_IO))
+#define MX1_IO_P2V(x)                   IMX_IO_P2V(x)
+#define MX1_IO_ADDRESS(x)               IOMEM(MX1_IO_P2V(x))
 
 /* fixed interrput numbers */
 #define MX1_INT_SOFTINT         0
-#define MX1_CSI_INT             6
+#define MX1_INT_CSI             6
 #define MX1_DSPA_MAC_INT        7
 #define MX1_DSPA_INT            8
 #define MX1_COMP_INT            9
@@ -115,13 +118,13 @@
 #define MX1_SSI_RX_INT          44
 #define MX1_SSI_RX_ERR_INT      45
 #define MX1_TOUCH_INT           46
-#define MX1_USBD_INT0           47
-#define MX1_USBD_INT1           48
-#define MX1_USBD_INT2           49
-#define MX1_USBD_INT3           50
-#define MX1_USBD_INT4           51
-#define MX1_USBD_INT5           52
-#define MX1_USBD_INT6           53
+#define MX1_INT_USBD0           47
+#define MX1_INT_USBD1           48
+#define MX1_INT_USBD2           49
+#define MX1_INT_USBD3           50
+#define MX1_INT_USBD4           51
+#define MX1_INT_USBD5           52
+#define MX1_INT_USBD6           53
 #define MX1_BTSYS_INT           55
 #define MX1_BTTIM_INT           56
 #define MX1_BTWUI_INT           57
@@ -164,134 +167,6 @@
  * to not break drivers/usb/gadget/imx_udc.  Should go
  * away after this driver uses the new name.
  */
-#define USBD_INT0               MX1_USBD_INT0
-
-#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
-/* these should go away */
-#define IMX_IO_PHYS MX1_IO_BASE_ADDR
-#define IMX_IO_SIZE MX1_IO_SIZE
-#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT
-#define IMX_CS0_PHYS MX1_CS0_PHYS
-#define IMX_CS0_SIZE MX1_CS0_SIZE
-#define IMX_CS1_PHYS MX1_CS1_PHYS
-#define IMX_CS1_SIZE MX1_CS1_SIZE
-#define IMX_CS2_PHYS MX1_CS2_PHYS
-#define IMX_CS2_SIZE MX1_CS2_SIZE
-#define IMX_CS3_PHYS MX1_CS3_PHYS
-#define IMX_CS3_SIZE MX1_CS3_SIZE
-#define IMX_CS4_PHYS MX1_CS4_PHYS
-#define IMX_CS4_SIZE MX1_CS4_SIZE
-#define IMX_CS5_PHYS MX1_CS5_PHYS
-#define IMX_CS5_SIZE MX1_CS5_SIZE
-#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR
-#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR
-#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR
-#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR
-#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR
-#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR
-#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR
-#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR
-#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR
-#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR
-#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR
-#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR
-#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR
-#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR
-#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR
-#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR
-#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR
-#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR
-#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR
-#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR
-#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR
-#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR
-#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR
-#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR
-#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR
-#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR
-#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR
-#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR
-#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR
-#define IO_ADDRESS(x) MX1_IO_ADDRESS(x)
-#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
-#define INT_SOFTINT MX1_INT_SOFTINT
-#define CSI_INT MX1_CSI_INT
-#define DSPA_MAC_INT MX1_DSPA_MAC_INT
-#define DSPA_INT MX1_DSPA_INT
-#define COMP_INT MX1_COMP_INT
-#define MSHC_XINT MX1_MSHC_XINT
-#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA
-#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB
-#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC
-#define LCDC_INT MX1_LCDC_INT
-#define SIM_INT MX1_SIM_INT
-#define SIM_DATA_INT MX1_SIM_DATA_INT
-#define RTC_INT MX1_RTC_INT
-#define RTC_SAMINT MX1_RTC_SAMINT
-#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR
-#define UART2_MINT_RTS MX1_UART2_MINT_RTS
-#define UART2_MINT_DTR MX1_UART2_MINT_DTR
-#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC
-#define UART2_MINT_TX MX1_UART2_MINT_TX
-#define UART2_MINT_RX MX1_UART2_MINT_RX
-#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR
-#define UART1_MINT_RTS MX1_UART1_MINT_RTS
-#define UART1_MINT_DTR MX1_UART1_MINT_DTR
-#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC
-#define UART1_MINT_TX MX1_UART1_MINT_TX
-#define UART1_MINT_RX MX1_UART1_MINT_RX
-#define VOICE_DAC_INT MX1_VOICE_DAC_INT
-#define VOICE_ADC_INT MX1_VOICE_ADC_INT
-#define PEN_DATA_INT MX1_PEN_DATA_INT
-#define PWM_INT MX1_PWM_INT
-#define SDHC_INT MX1_SDHC_INT
-#define I2C_INT MX1_INT_I2C
-#define CSPI_INT MX1_CSPI_INT
-#define SSI_TX_INT MX1_SSI_TX_INT
-#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
-#define SSI_RX_INT MX1_SSI_RX_INT
-#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT
-#define TOUCH_INT MX1_TOUCH_INT
-#define USBD_INT1 MX1_USBD_INT1
-#define USBD_INT2 MX1_USBD_INT2
-#define USBD_INT3 MX1_USBD_INT3
-#define USBD_INT4 MX1_USBD_INT4
-#define USBD_INT5 MX1_USBD_INT5
-#define USBD_INT6 MX1_USBD_INT6
-#define BTSYS_INT MX1_BTSYS_INT
-#define BTTIM_INT MX1_BTTIM_INT
-#define BTWUI_INT MX1_BTWUI_INT
-#define TIM2_INT MX1_TIM2_INT
-#define TIM1_INT MX1_TIM1_INT
-#define DMA_ERR MX1_DMA_ERR
-#define DMA_INT MX1_DMA_INT
-#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD
-#define WDT_INT MX1_WDT_INT
-#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T
-#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R
-#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T
-#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R
-#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT
-#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R
-#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC
-#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT
-#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN
-#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC
-#define DMA_REQ_EXT MX1_DMA_REQ_EXT
-#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC
-#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R
-#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T
-#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T
-#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R
-#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC
-#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC
-#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x)
-#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R
-#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T
-#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T
-#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R
-#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T
-#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R
-#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */
+#define USBD_INT0               MX1_INT_USBD0
 
 #endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 8bc59720b6e4..6cd049ebbd8d 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -26,7 +26,6 @@
 #define __MACH_MX21_H__
 
 #define MX21_AIPI_BASE_ADDR             0x10000000
-#define MX21_AIPI_BASE_ADDR_VIRT        0xf4000000
 #define MX21_AIPI_SIZE                  SZ_1M
 #define MX21_DMA_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x01000)
 #define MX21_WDOG_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x02000)
@@ -49,6 +48,12 @@
 #define MX21_SDHC1_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x13000)
 #define MX21_SDHC2_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x14000)
 #define MX21_GPIO_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x15000)
+#define MX21_GPIO1_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x000)
+#define MX21_GPIO2_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x100)
+#define MX21_GPIO3_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x200)
+#define MX21_GPIO4_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x300)
+#define MX21_GPIO5_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x400)
+#define MX21_GPIO6_BASE_ADDR                    (MX21_GPIO_BASE_ADDR + 0x500)
 #define MX21_AUDMUX_BASE_ADDR                   (MX21_AIPI_BASE_ADDR + 0x16000)
 #define MX21_CSPI3_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x17000)
 #define MX21_LCDC_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x21000)
@@ -64,7 +69,6 @@
 #define MX21_AVIC_BASE_ADDR             0x10040000
 
 #define MX21_SAHB1_BASE_ADDR            0x80000000
-#define MX21_SAHB1_BASE_ADDR_VIRT       0xf4100000
 #define MX21_SAHB1_SIZE                 SZ_1M
 #define MX21_CSI_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x0000)
 
@@ -82,7 +86,6 @@
 
 /* NAND, SDRAM, WEIM etc controllers */
 #define MX21_X_MEMC_BASE_ADDR           0xdf000000
-#define MX21_X_MEMC_BASE_ADDR_VIRT      0xf4200000
 #define MX21_X_MEMC_SIZE                SZ_256K
 
 #define MX21_SDRAMC_BASE_ADDR           (MX21_X_MEMC_BASE_ADDR + 0x0000)
@@ -92,10 +95,8 @@
 
 #define MX21_IRAM_BASE_ADDR             0xffffe800      /* internal ram */
 
-#define MX21_IO_ADDRESS(x) (                                            \
-        IMX_IO_ADDRESS(x, MX21_AIPI) ?:                                 \
-        IMX_IO_ADDRESS(x, MX21_SAHB1) ?:                                \
-        IMX_IO_ADDRESS(x, MX21_X_MEMC))
+#define MX21_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX21_IO_ADDRESS(x)              IOMEM(MX21_IO_P2V(x))
 
 /* fixed interrupt numbers */
 #define MX21_INT_CSPI3          6
@@ -184,39 +185,4 @@
 #define MX21_DMA_REQ_CSI_STAT   30
 #define MX21_DMA_REQ_CSI_RX     31
 
-#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
-/* these should go away */
-#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
-#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
-#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
-#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
-#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
-#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
-#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
-#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
-#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
-#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
-#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
-#define X_MEMC_SIZE MX21_X_MEMC_SIZE
-#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
-#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
-#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
-#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
-#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
-#define MXC_INT_FIRI MX21_INT_FIRI
-#define MXC_INT_BMI MX21_INT_BMI
-#define MXC_INT_EMMAENC MX21_INT_EMMAENC
-#define MXC_INT_EMMADEC MX21_INT_EMMADEC
-#define MXC_INT_USBWKUP MX21_INT_USBWKUP
-#define MXC_INT_USBDMA MX21_INT_USBDMA
-#define MXC_INT_USBHOST MX21_INT_USBHOST
-#define MXC_INT_USBFUNC MX21_INT_USBFUNC
-#define MXC_INT_USBMNP MX21_INT_USBMNP
-#define MXC_INT_USBCTRL MX21_INT_USBCTRL
-#define MXC_INT_USBCTRL MX21_INT_USBCTRL
-#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
-#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
-#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
-#endif
-
 #endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index cf46a45b0d4e..087cd7ac8d52 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -2,13 +2,10 @@
 #define __MACH_MX25_H__
 
 #define MX25_AIPS1_BASE_ADDR            0x43f00000
-#define MX25_AIPS1_BASE_ADDR_VIRT       0xfc000000
 #define MX25_AIPS1_SIZE                 SZ_1M
 #define MX25_AIPS2_BASE_ADDR            0x53f00000
-#define MX25_AIPS2_BASE_ADDR_VIRT       0xfc200000
 #define MX25_AIPS2_SIZE                 SZ_1M
 #define MX25_AVIC_BASE_ADDR             0x68000000
-#define MX25_AVIC_BASE_ADDR_VIRT        0xfc400000
 #define MX25_AVIC_SIZE                  SZ_1M
 
 #define MX25_I2C1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x80000)
@@ -21,20 +18,15 @@
 
 #define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
 #define MX25_GPT1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0x90000)
+#define MX25_GPIO4_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0x9c000)
+#define MX25_PWM2_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xa0000)
+#define MX25_GPIO3_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xa4000)
+#define MX25_PWM3_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xa8000)
+#define MX25_PWM4_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xc8000)
+#define MX25_GPIO1_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xcc000)
+#define MX25_GPIO2_BASE_ADDR            (MX25_AIPS2_BASE_ADDR + 0xd0000)
 #define MX25_WDOG_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xdc000)
-
-#define MX25_GPIO1_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
-#define MX25_GPIO2_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
-#define MX25_GPIO3_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
-#define MX25_GPIO4_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
-
-#define MX25_IO_ADDRESS(x) (                                    \
-        IMX_IO_ADDRESS(x, MX25_AIPS1) ?:                        \
-        IMX_IO_ADDRESS(x, MX25_AIPS2) ?:                        \
-        IMX_IO_ADDRESS(x, MX25_AVIC))
-
-#define MX25_AIPS1_IO_ADDRESS(x) \
-        (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
+#define MX25_PWM1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xe0000)
 
 #define MX25_UART1_BASE_ADDR            0x43f90000
 #define MX25_UART2_BASE_ADDR            0x43f94000
@@ -55,9 +47,19 @@
 #define MX25_LCDC_BASE_ADDR             0x53fbc000
 #define MX25_KPP_BASE_ADDR              0x43fa8000
 #define MX25_SDMA_BASE_ADDR             0x53fd4000
-#define MX25_OTG_BASE_ADDR              0x53ff4000
+#define MX25_USB_BASE_ADDR              0x53ff4000
+#define MX25_USB_OTG_BASE_ADDR                  (MX25_USB_BASE_ADDR + 0x0000)
+/*
+ * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
+ * for the host controller.  Early documentation drafts specified 0x400 and
+ * Freescale internal sources confirm only the latter value to work.
+ */
+#define MX25_USB_HS_BASE_ADDR                   (MX25_USB_BASE_ADDR + 0x0400)
 #define MX25_CSI_BASE_ADDR              0x53ff8000
 
+#define MX25_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX25_IO_ADDRESS(x)              IOMEM(MX25_IO_P2V(x))
+
 #define MX25_INT_CSPI3          0
 #define MX25_INT_I2C1           3
 #define MX25_INT_I2C2           4
@@ -69,18 +71,28 @@
 #define MX25_INT_SSI1           12
 #define MX25_INT_CSPI2          13
 #define MX25_INT_CSPI1          14
+#define MX25_INT_GPIO3          16
 #define MX25_INT_CSI            17
 #define MX25_INT_UART3          18
+#define MX25_INT_GPIO4          23
 #define MX25_INT_KPP            24
 #define MX25_INT_DRYICE         25
+#define MX25_INT_PWM1           26
 #define MX25_INT_UART2          32
 #define MX25_INT_NFC            33
 #define MX25_INT_SDMA           34
+#define MX25_INT_USB_HS         35
+#define MX25_INT_PWM2           36
+#define MX25_INT_USB_OTG        37
 #define MX25_INT_LCDC           39
 #define MX25_INT_UART5          40
+#define MX25_INT_PWM3           41
+#define MX25_INT_PWM4           42
 #define MX25_INT_CAN1           43
 #define MX25_INT_CAN2           44
 #define MX25_INT_UART1          45
+#define MX25_INT_GPIO2          51
+#define MX25_INT_GPIO1          52
 #define MX25_INT_FEC            57
 
 #define MX25_DMA_REQ_SSI2_RX1   22
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 2237ba2e5351..cbc43ad5ef48 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -29,7 +29,6 @@
 #endif
 
 #define MX27_AIPI_BASE_ADDR             0x10000000
-#define MX27_AIPI_BASE_ADDR_VIRT        0xf4000000
 #define MX27_AIPI_SIZE                  SZ_1M
 #define MX27_DMA_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x01000)
 #define MX27_WDOG_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x02000)
@@ -52,6 +51,12 @@
 #define MX27_SDHC1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x13000)
 #define MX27_SDHC2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x14000)
 #define MX27_GPIO_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x15000)
+#define MX27_GPIO1_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x000)
+#define MX27_GPIO2_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x100)
+#define MX27_GPIO3_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x200)
+#define MX27_GPIO4_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x300)
+#define MX27_GPIO5_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x400)
+#define MX27_GPIO6_BASE_ADDR                    (MX27_GPIO_BASE_ADDR + 0x500)
 #define MX27_AUDMUX_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x16000)
 #define MX27_CSPI3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x17000)
 #define MX27_MSHC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x18000)
@@ -65,11 +70,13 @@
 #define MX27_LCDC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x21000)
 #define MX27_SLCDC_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x22000)
 #define MX27_VPU_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x23000)
-#define MX27_USBOTG_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x24000)
-#define MX27_OTG_BASE_ADDR                      MX27_USBOTG_BASE_ADDR
+#define MX27_USB_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x24000)
+#define MX27_USB_OTG_BASE_ADDR                  (MX27_USB_BASE_ADDR + 0x0000)
+#define MX27_USB_HS1_BASE_ADDR                  (MX27_USB_BASE_ADDR + 0x0200)
+#define MX27_USB_HS2_BASE_ADDR                  (MX27_USB_BASE_ADDR + 0x0400)
 #define MX27_SAHARA_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x25000)
-#define MX27_EMMA_PP_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x26000)
-#define MX27_EMMA_PRP_BASE_ADDR                 (MX27_AIPI_BASE_ADDR + 0x26400)
+#define MX27_EMMAPP_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x26000)
+#define MX27_EMMAPRP_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x26400)
 #define MX27_CCM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x27000)
 #define MX27_SYSCTRL_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x27800)
 #define MX27_IIM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x28000)
@@ -87,7 +94,6 @@
 #define MX27_ROMP_BASE_ADDR             0x10041000
 
 #define MX27_SAHB1_BASE_ADDR            0x80000000
-#define MX27_SAHB1_BASE_ADDR_VIRT       0xf4100000
 #define MX27_SAHB1_SIZE                 SZ_1M
 #define MX27_CSI_BASE_ADDR                      (MX27_SAHB1_BASE_ADDR + 0x0000)
 #define MX27_ATA_BASE_ADDR                      (MX27_SAHB1_BASE_ADDR + 0x1000)
@@ -105,7 +111,6 @@
 
 /* NAND, SDRAM, WEIM, M3IF, EMI controllers */
 #define MX27_X_MEMC_BASE_ADDR           0xd8000000
-#define MX27_X_MEMC_BASE_ADDR_VIRT      0xf4200000
 #define MX27_X_MEMC_SIZE                SZ_1M
 #define MX27_NFC_BASE_ADDR                      (MX27_X_MEMC_BASE_ADDR)
 #define MX27_SDRAMC_BASE_ADDR                   (MX27_X_MEMC_BASE_ADDR + 0x1000)
@@ -123,10 +128,8 @@
 /* IRAM */
 #define MX27_IRAM_BASE_ADDR             0xffff4c00      /* internal ram */
 
-#define MX27_IO_ADDRESS(x) (                                            \
-        IMX_IO_ADDRESS(x, MX27_AIPI) ?:                                 \
-        IMX_IO_ADDRESS(x, MX27_SAHB1) ?:                                \
-        IMX_IO_ADDRESS(x, MX27_X_MEMC))
+#define MX27_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX27_IO_ADDRESS(x)              IOMEM(MX27_IO_P2V(x))
 
 #ifndef __ASSEMBLER__
 static inline void mx27_setup_weimcs(size_t cs,
@@ -192,9 +195,9 @@ static inline void mx27_setup_weimcs(size_t cs,
 #define MX27_INT_EMMAPRP        51
 #define MX27_INT_EMMAPP         52
 #define MX27_INT_VPU            53
-#define MX27_INT_USB1           54
-#define MX27_INT_USB2           55
-#define MX27_INT_USB3           56
+#define MX27_INT_USB_HS1        54
+#define MX27_INT_USB_HS2        55
+#define MX27_INT_USB_OTG        56
 #define MX27_INT_SCC_SMN        57
 #define MX27_INT_SCC_SCM        58
 #define MX27_INT_SAHARA         59
@@ -241,82 +244,8 @@ static inline void mx27_setup_weimcs(size_t cs,
 #define MX27_DMA_REQ_SDHC3      36
 #define MX27_DMA_REQ_NFC        37
 
-/* silicon revisions specific to i.MX27 */
-#define CHIP_REV_1_0            0x00
-#define CHIP_REV_2_0            0x01
-
 #ifndef __ASSEMBLY__
 extern int mx27_revision(void);
 #endif
 
-#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
-/* these should go away */
-#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
-#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
-#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
-#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
-#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
-#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
-#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
-#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
-#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
-#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
-#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
-#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
-#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
-#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
-#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
-#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
-#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
-#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
-#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
-#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
-#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
-#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
-#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
-#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
-#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
-#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
-#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
-#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
-#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
-#define X_MEMC_SIZE MX27_X_MEMC_SIZE
-#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
-#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
-#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
-#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
-#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
-#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
-#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
-#define MXC_INT_I2C2 MX27_INT_I2C2
-#define MXC_INT_GPT6 MX27_INT_GPT6
-#define MXC_INT_GPT5 MX27_INT_GPT5
-#define MXC_INT_GPT4 MX27_INT_GPT4
-#define MXC_INT_RTIC MX27_INT_RTIC
-#define MXC_INT_SDHC MX27_INT_SDHC
-#define MXC_INT_SDHC3 MX27_INT_SDHC3
-#define MXC_INT_ATA MX27_INT_ATA
-#define MXC_INT_UART6 MX27_INT_UART6
-#define MXC_INT_UART5 MX27_INT_UART5
-#define MXC_INT_FEC MX27_INT_FEC
-#define MXC_INT_VPU MX27_INT_VPU
-#define MXC_INT_USB1 MX27_INT_USB1
-#define MXC_INT_USB2 MX27_INT_USB2
-#define MXC_INT_USB3 MX27_INT_USB3
-#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
-#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
-#define MXC_INT_SAHARA MX27_INT_SAHARA
-#define MXC_INT_IIM MX27_INT_IIM
-#define MXC_INT_CCM MX27_INT_CCM
-#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
-#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
-#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
-#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
-#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
-#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
-#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
-#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
-#define DMA_REQ_NFC MX27_DMA_REQ_NFC
-#endif
-
 #endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index afb895a0b5b8..6d07839fdec2 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -27,7 +27,6 @@
 
 /* Register offsets */
 #define MX2x_AIPI_BASE_ADDR             0x10000000
-#define MX2x_AIPI_BASE_ADDR_VIRT        0xf4000000
 #define MX2x_AIPI_SIZE                  SZ_1M
 #define MX2x_DMA_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x01000)
 #define MX2x_WDOG_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x02000)
@@ -65,43 +64,9 @@
 #define MX2x_AVIC_BASE_ADDR             0x10040000
 
 #define MX2x_SAHB1_BASE_ADDR            0x80000000
-#define MX2x_SAHB1_BASE_ADDR_VIRT       0xf4100000
 #define MX2x_SAHB1_SIZE                 SZ_1M
 #define MX2x_CSI_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x0000)
 
-/*
- * This macro defines the physical to virtual address mapping for all the
- * peripheral modules. It is used by passing in the physical address as x
- * and returning the virtual address. If the physical address is not mapped,
- * it returns 0xDEADBEEF
- */
-#define IO_ADDRESS(x)   \
-        (void __force __iomem *) \
-        (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
-                AIPI_IO_ADDRESS(x) : \
-        ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
-                SAHB1_IO_ADDRESS(x) : \
-        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
-                X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
-
-/* define the address mapping macros: in physical address order */
-#define AIPI_IO_ADDRESS(x)  \
-        (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
-
-#define AVIC_IO_ADDRESS(x)      AIPI_IO_ADDRESS(x)
-
-#define SAHB1_IO_ADDRESS(x)  \
-        (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
-
-#define CS4_IO_ADDRESS(x)  \
-        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
-
-#define X_MEMC_IO_ADDRESS(x)  \
-        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
-
-#define PCMCIA_IO_ADDRESS(x) \
-        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
-
 /* fixed interrupt numbers */
 #define MX2x_INT_CSPI3          6
 #define MX2x_INT_GPIO           8
@@ -176,118 +141,4 @@
 #define MX2x_DMA_REQ_CSI_STAT   30
 #define MX2x_DMA_REQ_CSI_RX     31
 
-#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
-/* these should go away */
-#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
-#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
-#define AIPI_SIZE MX2x_AIPI_SIZE
-#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
-#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
-#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
-#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
-#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
-#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
-#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
-#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
-#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
-#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
-#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
-#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
-#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
-#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
-#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
-#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
-#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
-#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
-#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
-#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
-#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
-#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
-#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
-#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
-#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
-#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
-#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
-#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
-#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
-#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
-#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
-#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
-#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
-#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
-#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
-#define SAHB1_SIZE MX2x_SAHB1_SIZE
-#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
-#define MXC_INT_CSPI3 MX2x_INT_CSPI3
-#define MXC_INT_GPIO MX2x_INT_GPIO
-#define MXC_INT_SDHC2 MX2x_INT_SDHC2
-#define MXC_INT_SDHC1 MX2x_INT_SDHC1
-#define MXC_INT_I2C MX2x_INT_I2C
-#define MXC_INT_SSI2 MX2x_INT_SSI2
-#define MXC_INT_SSI1 MX2x_INT_SSI1
-#define MXC_INT_CSPI2 MX2x_INT_CSPI2
-#define MXC_INT_CSPI1 MX2x_INT_CSPI1
-#define MXC_INT_UART4 MX2x_INT_UART4
-#define MXC_INT_UART3 MX2x_INT_UART3
-#define MXC_INT_UART2 MX2x_INT_UART2
-#define MXC_INT_UART1 MX2x_INT_UART1
-#define MXC_INT_KPP MX2x_INT_KPP
-#define MXC_INT_RTC MX2x_INT_RTC
-#define MXC_INT_PWM MX2x_INT_PWM
-#define MXC_INT_GPT3 MX2x_INT_GPT3
-#define MXC_INT_GPT2 MX2x_INT_GPT2
-#define MXC_INT_GPT1 MX2x_INT_GPT1
-#define MXC_INT_WDOG MX2x_INT_WDOG
-#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
-#define MXC_INT_NANDFC MX2x_INT_NANDFC
-#define MXC_INT_CSI MX2x_INT_CSI
-#define MXC_INT_DMACH0 MX2x_INT_DMACH0
-#define MXC_INT_DMACH1 MX2x_INT_DMACH1
-#define MXC_INT_DMACH2 MX2x_INT_DMACH2
-#define MXC_INT_DMACH3 MX2x_INT_DMACH3
-#define MXC_INT_DMACH4 MX2x_INT_DMACH4
-#define MXC_INT_DMACH5 MX2x_INT_DMACH5
-#define MXC_INT_DMACH6 MX2x_INT_DMACH6
-#define MXC_INT_DMACH7 MX2x_INT_DMACH7
-#define MXC_INT_DMACH8 MX2x_INT_DMACH8
-#define MXC_INT_DMACH9 MX2x_INT_DMACH9
-#define MXC_INT_DMACH10 MX2x_INT_DMACH10
-#define MXC_INT_DMACH11 MX2x_INT_DMACH11
-#define MXC_INT_DMACH12 MX2x_INT_DMACH12
-#define MXC_INT_DMACH13 MX2x_INT_DMACH13
-#define MXC_INT_DMACH14 MX2x_INT_DMACH14
-#define MXC_INT_DMACH15 MX2x_INT_DMACH15
-#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
-#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
-#define MXC_INT_SLCDC MX2x_INT_SLCDC
-#define MXC_INT_LCDC MX2x_INT_LCDC
-#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
-#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
-#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
-#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
-#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
-#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
-#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
-#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
-#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
-#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
-#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
-#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
-#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
-#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
-#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
-#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
-#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
-#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
-#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
-#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
-#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
-#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
-#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
-#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
-#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
-#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
-#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
-#endif
-
 #endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 61cfe827498b..79e7fc01bb59 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -15,7 +15,6 @@
 #define MX31_L2CC_SIZE                  SZ_1M
 
 #define MX31_AIPS1_BASE_ADDR            0x43f00000
-#define MX31_AIPS1_BASE_ADDR_VIRT       0xfc000000
 #define MX31_AIPS1_SIZE                 SZ_1M
 #define MX31_MAX_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x04000)
 #define MX31_EVTMON_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0x08000)
@@ -25,7 +24,10 @@
 #define MX31_ECT_CTIO_BASE_ADDR                 (MX31_AIPS1_BASE_ADDR + 0x18000)
 #define MX31_I2C1_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x80000)
 #define MX31_I2C3_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x84000)
-#define MX31_OTG_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define MX31_USB_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define MX31_USB_OTG_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0000)
+#define MX31_USB_HS1_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0200)
+#define MX31_USB_HS2_BASE_ADDR                  (MX31_USB_BASE_ADDR + 0x0400)
 #define MX31_ATA_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x8c000)
 #define MX31_UART1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x90000)
 #define MX31_UART2_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x94000)
@@ -41,10 +43,9 @@
 #define MX31_ECT_IP2_BASE_ADDR                  (MX31_AIPS1_BASE_ADDR + 0xbc000)
 
 #define MX31_SPBA0_BASE_ADDR            0x50000000
-#define MX31_SPBA0_BASE_ADDR_VIRT       0xfc100000
 #define MX31_SPBA0_SIZE                 SZ_1M
-#define MX31_MMC_SDHC1_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x04000)
-#define MX31_MMC_SDHC2_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x08000)
+#define MX31_SDHC1_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x04000)
+#define MX31_SDHC2_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x08000)
 #define MX31_UART3_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x0c000)
 #define MX31_CSPI2_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x10000)
 #define MX31_SSI2_BASE_ADDR                     (MX31_SPBA0_BASE_ADDR + 0x14000)
@@ -55,7 +56,6 @@
 #define MX31_SPBA_CTRL_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x3c000)
 
 #define MX31_AIPS2_BASE_ADDR            0x53f00000
-#define MX31_AIPS2_BASE_ADDR_VIRT       0xfc200000
 #define MX31_AIPS2_SIZE                 SZ_1M
 #define MX31_CCM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0x80000)
 #define MX31_CSPI3_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x84000)
@@ -84,7 +84,6 @@
 #define MX31_ROMP_SIZE                  SZ_1M
 
 #define MX31_AVIC_BASE_ADDR             0x68000000
-#define MX31_AVIC_BASE_ADDR_VIRT        0xfc400000
 #define MX31_AVIC_SIZE                  SZ_1M
 
 #define MX31_IPU_MEM_BASE_ADDR          0x70000000
@@ -97,15 +96,14 @@
 #define MX31_CS3_BASE_ADDR              0xb2000000
 
 #define MX31_CS4_BASE_ADDR              0xb4000000
-#define MX31_CS4_BASE_ADDR_VIRT         0xf4000000
+#define MX31_CS4_BASE_ADDR_VIRT         0xf6000000
 #define MX31_CS4_SIZE                   SZ_32M
 
 #define MX31_CS5_BASE_ADDR              0xb6000000
-#define MX31_CS5_BASE_ADDR_VIRT         0xf6000000
+#define MX31_CS5_BASE_ADDR_VIRT         0xf8000000
 #define MX31_CS5_SIZE                   SZ_32M
 
 #define MX31_X_MEMC_BASE_ADDR           0xb8000000
-#define MX31_X_MEMC_BASE_ADDR_VIRT      0xfc320000
 #define MX31_X_MEMC_SIZE                SZ_64K
 #define MX31_NFC_BASE_ADDR                      (MX31_X_MEMC_BASE_ADDR + 0x0000)
 #define MX31_ESDCTL_BASE_ADDR                   (MX31_X_MEMC_BASE_ADDR + 0x1000)
@@ -121,12 +119,8 @@
 
 #define MX31_PCMCIA_MEM_BASE_ADDR       0xbc000000
 
-#define MX31_IO_ADDRESS(x) (                                            \
-        IMX_IO_ADDRESS(x, MX31_AIPS1) ?:                                \
-        IMX_IO_ADDRESS(x, MX31_AIPS2) ?:                                \
-        IMX_IO_ADDRESS(x, MX31_AVIC) ?:                                 \
-        IMX_IO_ADDRESS(x, MX31_X_MEMC) ?:                               \
-        IMX_IO_ADDRESS(x, MX31_SPBA0))
+#define MX31_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX31_IO_ADDRESS(x)              IOMEM(MX31_IO_P2V(x))
 
 #ifndef __ASSEMBLER__
 static inline void mx31_setup_weimcs(size_t cs,
@@ -143,8 +137,8 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_MPEG4_ENCODER  5
 #define MX31_INT_RTIC           6
 #define MX31_INT_FIRI           7
-#define MX31_INT_MMC_SDHC2      8
-#define MX31_INT_MMC_SDHC1      9
+#define MX31_INT_SDHC2          8
+#define MX31_INT_SDHC1          9
 #define MX31_INT_I2C1           10
 #define MX31_INT_SSI2           11
 #define MX31_INT_SSI1           12
@@ -170,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_UART2          32
 #define MX31_INT_NFC            33
 #define MX31_INT_SDMA           34
-#define MX31_INT_USB1           35
-#define MX31_INT_USB2           36
-#define MX31_INT_USB3           37
-#define MX31_INT_USB4           38
+#define MX31_INT_USB_HS1        35
+#define MX31_INT_USB_HS2        36
+#define MX31_INT_USB_OTG        37
 #define MX31_INT_MSHC1          39
 #define MX31_INT_MSHC2          40
 #define MX31_INT_IPU_ERR        41
@@ -197,6 +190,8 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_EXT_WDOG       62
 #define MX31_INT_EXT_TV         63
 
+#define MX31_DMA_REQ_SDHC1      20
+#define MX31_DMA_REQ_SDHC2      21
 #define MX31_DMA_REQ_SSI2_RX1   22
 #define MX31_DMA_REQ_SSI2_TX1   23
 #define MX31_DMA_REQ_SSI2_RX0   24
@@ -208,52 +203,4 @@ static inline void mx31_setup_weimcs(size_t cs,
 
 #define MX31_PROD_SIGNATURE             0x1     /* For MX31 */
 
-/* silicon revisions specific to i.MX31 */
-#define MX31_CHIP_REV_1_0               0x10
-#define MX31_CHIP_REV_1_1               0x11
-#define MX31_CHIP_REV_1_2               0x12
-#define MX31_CHIP_REV_1_3               0x13
-#define MX31_CHIP_REV_2_0               0x20
-#define MX31_CHIP_REV_2_1               0x21
-#define MX31_CHIP_REV_2_2               0x22
-#define MX31_CHIP_REV_2_3               0x23
-#define MX31_CHIP_REV_3_0               0x30
-#define MX31_CHIP_REV_3_1               0x31
-#define MX31_CHIP_REV_3_2               0x32
-
-#define MX31_SYSTEM_REV_MIN             MX31_CHIP_REV_1_0
-#define MX31_SYSTEM_REV_NUM             3
-
-#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
-/* these should go away */
-#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
-#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
-#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
-#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
-#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
-#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
-#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
-#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
-#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
-#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
-#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
-#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
-#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
-#define MXC_INT_FIRI MX31_INT_FIRI
-#define MXC_INT_MBX MX31_INT_MBX
-#define MXC_INT_CSPI3 MX31_INT_CSPI3
-#define MXC_INT_SIM2 MX31_INT_SIM2
-#define MXC_INT_SIM1 MX31_INT_SIM1
-#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
-#define MXC_INT_USB1 MX31_INT_USB1
-#define MXC_INT_USB2 MX31_INT_USB2
-#define MXC_INT_USB3 MX31_INT_USB3
-#define MXC_INT_USB4 MX31_INT_USB4
-#define MXC_INT_MSHC2 MX31_INT_MSHC2
-#define MXC_INT_UART4 MX31_INT_UART4
-#define MXC_INT_UART5 MX31_INT_UART5
-#define MXC_INT_CCM MX31_INT_CCM
-#define MXC_INT_PCMCIA MX31_INT_PCMCIA
-#endif
-
 #endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 6267cff6035d..d13dbfeef08a 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -11,7 +11,6 @@
 #define MX35_L2CC_SIZE                  SZ_1M
 
 #define MX35_AIPS1_BASE_ADDR            0x43f00000
-#define MX35_AIPS1_BASE_ADDR_VIRT       0xfc000000
 #define MX35_AIPS1_SIZE                 SZ_1M
 #define MX35_MAX_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0x04000)
 #define MX35_EVTMON_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0x08000)
@@ -33,7 +32,6 @@
 #define MX35_ECT_IP2_BASE_ADDR                  (MX35_AIPS1_BASE_ADDR + 0xbc000)
 
 #define MX35_SPBA0_BASE_ADDR            0x50000000
-#define MX35_SPBA0_BASE_ADDR_VIRT       0xfc100000
 #define MX35_SPBA0_SIZE                 SZ_1M
 #define MX35_UART3_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x0c000)
 #define MX35_CSPI2_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x10000)
@@ -44,7 +42,6 @@
 #define MX35_SPBA_CTRL_BASE_ADDR                (MX35_SPBA0_BASE_ADDR + 0x3c000)
 
 #define MX35_AIPS2_BASE_ADDR            0x53f00000
-#define MX35_AIPS2_BASE_ADDR_VIRT       0xfc200000
 #define MX35_AIPS2_SIZE                 SZ_1M
 #define MX35_CCM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0x80000)
 #define MX35_GPT1_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0x90000)
@@ -68,15 +65,19 @@
 #define MX35_CAN2_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe8000)
 #define MX35_RTIC_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xec000)
 #define MX35_IIM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xf0000)
-
-#define MX35_OTG_BASE_ADDR              0x53ff4000
+#define MX35_USB_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xf4000)
+#define MX35_USB_OTG_BASE_ADDR                  (MX35_USB_BASE_ADDR + 0x0000)
+/*
+ * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
+ * HS.  When host support was implemented only a preliminary document was
+ * available, which told 0x400.  This works fine.
+ */
+#define MX35_USB_HS_BASE_ADDR                   (MX35_USB_BASE_ADDR + 0x0400)
 
 #define MX35_ROMP_BASE_ADDR             0x60000000
-#define MX35_ROMP_BASE_ADDR_VIRT        0xfc500000
 #define MX35_ROMP_SIZE                  SZ_1M
 
 #define MX35_AVIC_BASE_ADDR             0x68000000
-#define MX35_AVIC_BASE_ADDR_VIRT        0xfc400000
 #define MX35_AVIC_SIZE                  SZ_1M
 
 /*
@@ -92,18 +93,17 @@
 #define MX35_CS3_BASE_ADDR              0xb2000000
 
 #define MX35_CS4_BASE_ADDR              0xb4000000
-#define MX35_CS4_BASE_ADDR_VIRT         0xf4000000
+#define MX35_CS4_BASE_ADDR_VIRT         0xf6000000
 #define MX35_CS4_SIZE                   SZ_32M
 
 #define MX35_CS5_BASE_ADDR              0xb6000000
-#define MX35_CS5_BASE_ADDR_VIRT         0xf6000000
+#define MX35_CS5_BASE_ADDR_VIRT         0xf8000000
 #define MX35_CS5_SIZE                   SZ_32M
 
 /*
  * NAND, SDRAM, WEIM, M3IF, EMI controllers
  */
 #define MX35_X_MEMC_BASE_ADDR           0xb8000000
-#define MX35_X_MEMC_BASE_ADDR_VIRT      0xfc320000
 #define MX35_X_MEMC_SIZE                SZ_64K
 #define MX35_ESDCTL_BASE_ADDR                   (MX35_X_MEMC_BASE_ADDR + 0x1000)
 #define MX35_WEIM_BASE_ADDR                     (MX35_X_MEMC_BASE_ADDR + 0x2000)
@@ -114,12 +114,8 @@
 #define MX35_NFC_BASE_ADDR              0xbb000000
 #define MX35_PCMCIA_MEM_BASE_ADDR       0xbc000000
 
-#define MX35_IO_ADDRESS(x) (                                            \
-        IMX_IO_ADDRESS(x, MX35_AIPS1) ?:                                \
-        IMX_IO_ADDRESS(x, MX35_AIPS2) ?:                                \
-        IMX_IO_ADDRESS(x, MX35_AVIC) ?:                                 \
-        IMX_IO_ADDRESS(x, MX35_X_MEMC) ?:                               \
-        IMX_IO_ADDRESS(x, MX35_SPBA0))
+#define MX35_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX35_IO_ADDRESS(x)              IOMEM(MX35_IO_P2V(x))
 
 /*
  * Interrupt numbers
@@ -153,8 +149,8 @@
 #define MX35_INT_UART2          32
 #define MX35_INT_NFC            33
 #define MX35_INT_SDMA           34
-#define MX35_INT_USBHS          35
-#define MX35_INT_USBOTG         37
+#define MX35_INT_USB_HS         35
+#define MX35_INT_USB_OTG        37
 #define MX35_INT_MSHC1          39
 #define MX35_INT_ESAI           40
 #define MX35_INT_IPU_ERR        41
@@ -190,23 +186,4 @@
 
 #define MX35_PROD_SIGNATURE             0x1     /* For MX31 */
 
-#define MX35_SYSTEM_REV_MIN             MX3x_CHIP_REV_1_0
-#define MX35_SYSTEM_REV_NUM             3
-
-#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
-/* these should go away */
-#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
-#define MXC_INT_OWIRE MX35_INT_OWIRE
-#define MXC_INT_GPU2D MX35_INT_GPU2D
-#define MXC_INT_ASRC MX35_INT_ASRC
-#define MXC_INT_USBHS MX35_INT_USBHS
-#define MXC_INT_USBOTG MX35_INT_USBOTG
-#define MXC_INT_ESAI MX35_INT_ESAI
-#define MXC_INT_CAN1 MX35_INT_CAN1
-#define MXC_INT_CAN2 MX35_INT_CAN2
-#define MXC_INT_MLB MX35_INT_MLB
-#define MXC_INT_SPDIF MX35_INT_SPDIF
-#define MXC_INT_FEC MX35_INT_FEC
-#endif
-
 #endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index d1bd26d7b8a6..388a407d72d6 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -44,7 +44,6 @@
  * AIPS 1
  */
 #define MX3x_AIPS1_BASE_ADDR            0x43f00000
-#define MX3x_AIPS1_BASE_ADDR_VIRT       0xfc000000
 #define MX3x_AIPS1_SIZE                 SZ_1M
 #define MX3x_MAX_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0x04000)
 #define MX3x_EVTMON_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0x08000)
@@ -69,7 +68,6 @@
  * SPBA global module enabled #0
  */
 #define MX3x_SPBA0_BASE_ADDR            0x50000000
-#define MX3x_SPBA0_BASE_ADDR_VIRT       0xfc100000
 #define MX3x_SPBA0_SIZE                 SZ_1M
 #define MX3x_UART3_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x0c000)
 #define MX3x_CSPI2_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x10000)
@@ -82,7 +80,6 @@
  * AIPS 2
  */
 #define MX3x_AIPS2_BASE_ADDR            0x53f00000
-#define MX3x_AIPS2_BASE_ADDR_VIRT       0xfc200000
 #define MX3x_AIPS2_SIZE                 SZ_1M
 #define MX3x_CCM_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0x80000)
 #define MX3x_GPT1_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0x90000)
@@ -105,11 +102,9 @@
  * ROMP and AVIC
  */
 #define MX3x_ROMP_BASE_ADDR             0x60000000
-#define MX3x_ROMP_BASE_ADDR_VIRT        0xfc500000
 #define MX3x_ROMP_SIZE                  SZ_1M
 
 #define MX3x_AVIC_BASE_ADDR             0x68000000
-#define MX3x_AVIC_BASE_ADDR_VIRT        0xfc400000
 #define MX3x_AVIC_SIZE                  SZ_1M
 
 /*
@@ -125,18 +120,17 @@
 #define MX3x_CS3_BASE_ADDR              0xb2000000
 
 #define MX3x_CS4_BASE_ADDR              0xb4000000
-#define MX3x_CS4_BASE_ADDR_VIRT         0xf4000000
+#define MX3x_CS4_BASE_ADDR_VIRT         0xf6000000
 #define MX3x_CS4_SIZE                   SZ_32M
 
 #define MX3x_CS5_BASE_ADDR              0xb6000000
-#define MX3x_CS5_BASE_ADDR_VIRT         0xf6000000
+#define MX3x_CS5_BASE_ADDR_VIRT         0xf8000000
 #define MX3x_CS5_SIZE                   SZ_32M
 
 /*
  * NAND, SDRAM, WEIM, M3IF, EMI controllers
  */
 #define MX3x_X_MEMC_BASE_ADDR           0xb8000000
-#define MX3x_X_MEMC_BASE_ADDR_VIRT      0xfc320000
 #define MX3x_X_MEMC_SIZE                SZ_64K
 #define MX3x_ESDCTL_BASE_ADDR                   (MX3x_X_MEMC_BASE_ADDR + 0x1000)
 #define MX3x_WEIM_BASE_ADDR                     (MX3x_X_MEMC_BASE_ADDR + 0x2000)
@@ -146,56 +140,6 @@
 
 #define MX3x_PCMCIA_MEM_BASE_ADDR       0xbc000000
 
-/*!
- * This macro defines the physical to virtual address mapping for all the
- * peripheral modules. It is used by passing in the physical address as x
- * and returning the virtual address. If the physical address is not mapped,
- * it returns 0xDEADBEEF
- */
-#define IO_ADDRESS(x)   \
-        (void __force __iomem *) \
-        (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
-        ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
-        ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
-        ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
-        ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
-        ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
-        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
-        0xDEADBEEF)
-
-/*
- * define the address mapping macros: in physical address order
- */
-#define L2CC_IO_ADDRESS(x)  \
-        (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
-
-#define AIPS1_IO_ADDRESS(x)  \
-        (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
-
-#define SPBA0_IO_ADDRESS(x)  \
-        (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
-
-#define AIPS2_IO_ADDRESS(x)  \
-        (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
-
-#define ROMP_IO_ADDRESS(x)  \
-        (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
-
-#define AVIC_IO_ADDRESS(x)  \
-        (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
-
-#define CS4_IO_ADDRESS(x)  \
-        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
-
-#define CS5_IO_ADDRESS(x)  \
-        (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)
-
-#define X_MEMC_IO_ADDRESS(x)  \
-        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
-
-#define PCMCIA_IO_ADDRESS(x) \
-        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
-
 /*
  * Interrupt numbers
  */
@@ -240,22 +184,6 @@
 
 #define MX3x_PROD_SIGNATURE             0x1     /* For MX31 */
 
-/* silicon revisions specific to i.MX31 and i.MX35 */
-#define MX3x_CHIP_REV_1_0               0x10
-#define MX3x_CHIP_REV_1_1               0x11
-#define MX3x_CHIP_REV_1_2               0x12
-#define MX3x_CHIP_REV_1_3               0x13
-#define MX3x_CHIP_REV_2_0               0x20
-#define MX3x_CHIP_REV_2_1               0x21
-#define MX3x_CHIP_REV_2_2               0x22
-#define MX3x_CHIP_REV_2_3               0x23
-#define MX3x_CHIP_REV_3_0               0x30
-#define MX3x_CHIP_REV_3_1               0x31
-#define MX3x_CHIP_REV_3_2               0x32
-
-#define MX3x_SYSTEM_REV_MIN             MX3x_CHIP_REV_1_0
-#define MX3x_SYSTEM_REV_NUM             3
-
 /* Mandatory defines used globally */
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
@@ -277,126 +205,4 @@ static inline int mx35_revision(void)
 }
 #endif
 
-#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
-/* these should go away */
-#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
-#define L2CC_SIZE MX3x_L2CC_SIZE
-#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
-#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
-#define AIPS1_SIZE MX3x_AIPS1_SIZE
-#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
-#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
-#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
-#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
-#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
-#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
-#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
-#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
-#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
-#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
-#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
-#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
-#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
-#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
-#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
-#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
-#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
-#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
-#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
-#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
-#define SPBA0_SIZE MX3x_SPBA0_SIZE
-#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
-#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
-#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
-#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
-#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
-#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
-#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
-#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
-#define AIPS2_SIZE MX3x_AIPS2_SIZE
-#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
-#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
-#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
-#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
-#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
-#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
-#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
-#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
-#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
-#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
-#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
-#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
-#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
-#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
-#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
-#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
-#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
-#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
-#define ROMP_SIZE MX3x_ROMP_SIZE
-#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
-#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
-#define AVIC_SIZE MX3x_AVIC_SIZE
-#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
-#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
-#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
-#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
-#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
-#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
-#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
-#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
-#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
-#define CS4_SIZE MX3x_CS4_SIZE
-#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
-#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
-#define CS5_SIZE MX3x_CS5_SIZE
-#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
-#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
-#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
-#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
-#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
-#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
-#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
-#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
-#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
-#define MXC_INT_I2C3 MX3x_INT_I2C3
-#define MXC_INT_I2C2 MX3x_INT_I2C2
-#define MXC_INT_RTIC MX3x_INT_RTIC
-#define MXC_INT_I2C MX3x_INT_I2C
-#define MXC_INT_CSPI2 MX3x_INT_CSPI2
-#define MXC_INT_CSPI1 MX3x_INT_CSPI1
-#define MXC_INT_ATA MX3x_INT_ATA
-#define MXC_INT_UART3 MX3x_INT_UART3
-#define MXC_INT_IIM MX3x_INT_IIM
-#define MXC_INT_RNGA MX3x_INT_RNGA
-#define MXC_INT_EVTMON MX3x_INT_EVTMON
-#define MXC_INT_KPP MX3x_INT_KPP
-#define MXC_INT_RTC MX3x_INT_RTC
-#define MXC_INT_PWM MX3x_INT_PWM
-#define MXC_INT_EPIT2 MX3x_INT_EPIT2
-#define MXC_INT_EPIT1 MX3x_INT_EPIT1
-#define MXC_INT_GPT MX3x_INT_GPT
-#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
-#define MXC_INT_UART2 MX3x_INT_UART2
-#define MXC_INT_NANDFC MX3x_INT_NANDFC
-#define MXC_INT_SDMA MX3x_INT_SDMA
-#define MXC_INT_MSHC1 MX3x_INT_MSHC1
-#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
-#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
-#define MXC_INT_UART1 MX3x_INT_UART1
-#define MXC_INT_ECT MX3x_INT_ECT
-#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
-#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
-#define MXC_INT_GPIO2 MX3x_INT_GPIO2
-#define MXC_INT_GPIO1 MX3x_INT_GPIO1
-#define MXC_INT_WDOG MX3x_INT_WDOG
-#define MXC_INT_GPIO3 MX3x_INT_GPIO3
-#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
-#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
-#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
-#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
-#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
-#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
-#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
-#endif
-
 #endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
new file mode 100644
index 000000000000..aaec2a6e7b3a
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -0,0 +1,285 @@
+#ifndef __MACH_MX50_H__
+#define __MACH_MX50_H__
+
+/*
+ * IROM
+ */
+#define MX50_IROM_BASE_ADDR             0x0
+#define MX50_IROM_SIZE                  SZ_64K
+
+/* TZIC */
+#define MX50_TZIC_BASE_ADDR             0x0fffc000
+#define MX50_TZIC_SIZE                  SZ_16K
+
+/*
+ * IRAM
+ */
+#define MX50_IRAM_BASE_ADDR     0xf8000000      /* internal ram */
+#define MX50_IRAM_PARTITIONS    16
+#define MX50_IRAM_SIZE          (MX50_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
+
+/*
+ * Databahn
+ */
+#define MX50_DATABAHN_BASE_ADDR                 0x14000000
+
+/*
+ * Graphics Memory of GPU
+ */
+#define MX50_GPU2D_BASE_ADDR            0x20000000
+
+#define MX50_DEBUG_BASE_ADDR            0x40000000
+#define MX50_DEBUG_SIZE                 SZ_1M
+#define MX50_ETB_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x00001000)
+#define MX50_ETM_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x00002000)
+#define MX50_TPIU_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00003000)
+#define MX50_CTI0_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00004000)
+#define MX50_CTI1_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00005000)
+#define MX50_CTI2_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00006000)
+#define MX50_CTI3_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x00007000)
+#define MX50_CORTEX_DBG_BASE_ADDR       (MX50_DEBUG_BASE_ADDR + 0x00008000)
+
+#define MX50_APBHDMA_BASE_ADDR          (MX50_DEBUG_BASE_ADDR + 0x01000000)
+#define MX50_OCOTP_CTRL_BASE_ADDR       (MX50_DEBUG_BASE_ADDR + 0x01002000)
+#define MX50_DIGCTL_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x01004000)
+#define MX50_GPMI_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01006000)
+#define MX50_BCH_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x01008000)
+#define MX50_ELCDIF_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x0100a000)
+#define MX50_EPXP_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x0100c000)
+#define MX50_DCP_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x0100e000)
+#define MX50_EPDC_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01010000)
+#define MX50_QOSC_BASE_ADDR             (MX50_DEBUG_BASE_ADDR + 0x01012000)
+#define MX50_PERFMON_BASE_ADDR          (MX50_DEBUG_BASE_ADDR + 0x01014000)
+#define MX50_SSP_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x01016000)
+#define MX50_ANATOP_BASE_ADDR           (MX50_DEBUG_BASE_ADDR + 0x01018000)
+#define MX50_NIC_BASE_ADDR              (MX50_DEBUG_BASE_ADDR + 0x08000000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define MX50_SPBA0_BASE_ADDR            0x50000000
+#define MX50_SPBA0_SIZE                 SZ_1M
+
+#define MX50_MMC_SDHC1_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00004000)
+#define MX50_MMC_SDHC2_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00008000)
+#define MX50_UART3_BASE_ADDR            (MX50_SPBA0_BASE_ADDR + 0x0000c000)
+#define MX50_CSPI1_BASE_ADDR            (MX50_SPBA0_BASE_ADDR + 0x00010000)
+#define MX50_SSI2_BASE_ADDR             (MX50_SPBA0_BASE_ADDR + 0x00014000)
+#define MX50_MMC_SDHC3_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00020000)
+#define MX50_MMC_SDHC4_BASE_ADDR        (MX50_SPBA0_BASE_ADDR + 0x00024000)
+
+/*
+ * AIPS 1
+ */
+#define MX50_AIPS1_BASE_ADDR    0x53f00000
+#define MX50_AIPS1_SIZE         SZ_1M
+
+#define MX50_OTG_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x00080000)
+#define MX50_GPIO1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00084000)
+#define MX50_GPIO2_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00088000)
+#define MX50_GPIO3_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x0008c000)
+#define MX50_GPIO4_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x00090000)
+#define MX50_KPP_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x00094000)
+#define MX50_WDOG_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x00098000)
+#define MX50_GPT1_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000a0000)
+#define MX50_SRTC_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000a4000)
+#define MX50_IOMUXC_BASE_ADDR   (MX50_AIPS1_BASE_ADDR + 0x000a8000)
+#define MX50_EPIT1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000ac000)
+#define MX50_PWM1_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000b4000)
+#define MX50_PWM2_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000b8000)
+#define MX50_UART1_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000bc000)
+#define MX50_UART2_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000c0000)
+#define MX50_SRC_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d0000)
+#define MX50_CCM_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d4000)
+#define MX50_GPC_BASE_ADDR      (MX50_AIPS1_BASE_ADDR + 0x000d8000)
+#define MX50_GPIO5_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000dc000)
+#define MX50_GPIO6_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000e0000)
+#define MX50_I2C3_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000ec000)
+#define MX50_UART4_BASE_ADDR    (MX50_AIPS1_BASE_ADDR + 0x000f0000)
+
+#define MX50_MSHC_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000f4000)
+#define MX50_RNGB_BASE_ADDR     (MX50_AIPS1_BASE_ADDR + 0x000f8000)
+
+/*
+ * AIPS 2
+ */
+#define MX50_AIPS2_BASE_ADDR    0x63f00000
+#define MX50_AIPS2_SIZE         SZ_1M
+
+#define MX50_PLL1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00080000)
+#define MX50_PLL2_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00084000)
+#define MX50_PLL3_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x00088000)
+#define MX50_UART5_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x00090000)
+#define MX50_AHBMAX_BASE_ADDR   (MX50_AIPS2_BASE_ADDR + 0x00094000)
+#define MX50_ARM_BASE_ADDR      (MX50_AIPS2_BASE_ADDR + 0x000a0000)
+#define MX50_OWIRE_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000a4000)
+#define MX50_CSPI2_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000ac000)
+#define MX50_SDMA_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000b0000)
+#define MX50_ROMCP_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000b8000)
+#define MX50_CSPI3_BASE_ADDR    (MX50_AIPS2_BASE_ADDR + 0x000c0000)
+#define MX50_I2C2_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000c4000)
+#define MX50_I2C1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000c8000)
+#define MX50_SSI1_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000cc000)
+#define MX50_AUDMUX_BASE_ADDR   (MX50_AIPS2_BASE_ADDR + 0x000d0000)
+#define MX50_WEIM_BASE_ADDR     (MX50_AIPS2_BASE_ADDR + 0x000d8000)
+#define MX50_FEC_BASE_ADDR      (MX50_AIPS2_BASE_ADDR + 0x000ec000)
+
+/*
+ * Memory regions and CS
+ */
+#define MX50_CSD0_BASE_ADDR             0x70000000
+#define MX50_CSD1_BASE_ADDR             0xb0000000
+#define MX50_CS0_BASE_ADDR              0xf0000000
+
+#define MX50_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX50_IO_ADDRESS(x)              IOMEM(MX50_IO_P2V(x))
+
+/*
+ * defines for SPBA modules
+ */
+#define MX50_SPBA_SDHC1         0x04
+#define MX50_SPBA_SDHC2         0x08
+#define MX50_SPBA_UART3         0x0c
+#define MX50_SPBA_CSPI1         0x10
+#define MX50_SPBA_SSI2          0x14
+#define MX50_SPBA_SDHC3         0x20
+#define MX50_SPBA_SDHC4         0x24
+#define MX50_SPBA_SPDIF         0x28
+#define MX50_SPBA_ATA           0x30
+#define MX50_SPBA_SLIM          0x34
+#define MX50_SPBA_HSI2C         0x38
+#define MX50_SPBA_CTRL          0x3c
+
+/*
+ * DMA request assignments
+ */
+#define MX50_DMA_REQ_GPC                1
+#define MX50_DMA_REQ_ATA_UART4_RX       2
+#define MX50_DMA_REQ_ATA_UART4_TX       3
+#define MX50_DMA_REQ_CSPI1_RX           6
+#define MX50_DMA_REQ_CSPI1_TX           7
+#define MX50_DMA_REQ_CSPI2_RX           8
+#define MX50_DMA_REQ_CSPI2_TX           9
+#define MX50_DMA_REQ_I2C3_SDHC3         10
+#define MX50_DMA_REQ_SDHC4              11
+#define MX50_DMA_REQ_UART2_FIRI_RX      12
+#define MX50_DMA_REQ_UART2_FIRI_TX      13
+#define MX50_DMA_REQ_EXT0               14
+#define MX50_DMA_REQ_EXT1               15
+#define MX50_DMA_REQ_UART5_RX           16
+#define MX50_DMA_REQ_UART5_TX           17
+#define MX50_DMA_REQ_UART1_RX           18
+#define MX50_DMA_REQ_UART1_TX           19
+#define MX50_DMA_REQ_I2C1_SDHC1         20
+#define MX50_DMA_REQ_I2C2_SDHC2         21
+#define MX50_DMA_REQ_SSI2_RX2           22
+#define MX50_DMA_REQ_SSI2_TX2           23
+#define MX50_DMA_REQ_SSI2_RX1           24
+#define MX50_DMA_REQ_SSI2_TX1           25
+#define MX50_DMA_REQ_SSI1_RX2           26
+#define MX50_DMA_REQ_SSI1_TX2           27
+#define MX50_DMA_REQ_SSI1_RX1           28
+#define MX50_DMA_REQ_SSI1_TX1           29
+#define MX50_DMA_REQ_CSPI_RX            38
+#define MX50_DMA_REQ_CSPI_TX            39
+#define MX50_DMA_REQ_UART3_RX           42
+#define MX50_DMA_REQ_UART3_TX           43
+
+/*
+ * Interrupt numbers
+ */
+#define MX50_INT_MMC_SDHC1      1
+#define MX50_INT_MMC_SDHC2      2
+#define MX50_INT_MMC_SDHC3      3
+#define MX50_INT_MMC_SDHC4      4
+#define MX50_INT_DAP            5
+#define MX50_INT_SDMA           6
+#define MX50_INT_IOMUX          7
+#define MX50_INT_UART4          13
+#define MX50_INT_USB_H1         14
+#define MX50_INT_USB_OTG        18
+#define MX50_INT_DATABAHN       19
+#define MX50_INT_ELCDIF         20
+#define MX50_INT_EPXP           21
+#define MX50_INT_SRTC_NTZ       24
+#define MX50_INT_SRTC_TZ        25
+#define MX50_INT_EPDC           27
+#define MX50_INT_NIC            28
+#define MX50_INT_SSI1           29
+#define MX50_INT_SSI2           30
+#define MX50_INT_UART1          31
+#define MX50_INT_UART2          32
+#define MX50_INT_UART3          33
+#define MX50_INT_RESV34         34
+#define MX50_INT_RESV35         35
+#define MX50_INT_CSPI1          36
+#define MX50_INT_CSPI2          37
+#define MX50_INT_CSPI           38
+#define MX50_INT_GPT            39
+#define MX50_INT_EPIT1          40
+#define MX50_INT_GPIO1_INT7     42
+#define MX50_INT_GPIO1_INT6     43
+#define MX50_INT_GPIO1_INT5     44
+#define MX50_INT_GPIO1_INT4     45
+#define MX50_INT_GPIO1_INT3     46
+#define MX50_INT_GPIO1_INT2     47
+#define MX50_INT_GPIO1_INT1     48
+#define MX50_INT_GPIO1_INT0     49
+#define MX50_INT_GPIO1_LOW      50
+#define MX50_INT_GPIO1_HIGH     51
+#define MX50_INT_GPIO2_LOW      52
+#define MX50_INT_GPIO2_HIGH     53
+#define MX50_INT_GPIO3_LOW      54
+#define MX50_INT_GPIO3_HIGH     55
+#define MX50_INT_GPIO4_LOW      56
+#define MX50_INT_GPIO4_HIGH     57
+#define MX50_INT_WDOG1          58
+#define MX50_INT_KPP            60
+#define MX50_INT_PWM1           61
+#define MX50_INT_I2C1           62
+#define MX50_INT_I2C2           63
+#define MX50_INT_I2C3           64
+#define MX50_INT_RESV65         65
+#define MX50_INT_DCDC           66
+#define MX50_INT_THERMAL_ALARM  67
+#define MX50_INT_ANA3           68
+#define MX50_INT_ANA4           69
+#define MX50_INT_CCM1           71
+#define MX50_INT_CCM2           72
+#define MX50_INT_GPC1           73
+#define MX50_INT_GPC2           74
+#define MX50_INT_SRC            75
+#define MX50_INT_NM             76
+#define MX50_INT_PMU            77
+#define MX50_INT_CTI_IRQ        78
+#define MX50_INT_CTI1_TG0       79
+#define MX50_INT_CTI1_TG1       80
+#define MX50_INT_GPU2_IRQ       84
+#define MX50_INT_GPU2_BUSY      85
+#define MX50_INT_UART5          86
+#define MX50_INT_FEC            87
+#define MX50_INT_OWIRE          88
+#define MX50_INT_CTI1_TG2       89
+#define MX50_INT_SJC            90
+#define MX50_INT_DCP_CHAN1_3    91
+#define MX50_INT_DCP_CHAN0      92
+#define MX50_INT_PWM2           94
+#define MX50_INT_RNGB           97
+#define MX50_INT_CTI1_TG3       98
+#define MX50_INT_RAWNAND_BCH    100
+#define MX50_INT_RAWNAND_GPMI   102
+#define MX50_INT_GPIO5_LOW      103
+#define MX50_INT_GPIO5_HIGH     104
+#define MX50_INT_GPIO6_LOW      105
+#define MX50_INT_GPIO6_HIGH     106
+#define MX50_INT_MSHC           109
+#define MX50_INT_APBHDMA_CHAN0  110
+#define MX50_INT_APBHDMA_CHAN1  111
+#define MX50_INT_APBHDMA_CHAN2  112
+#define MX50_INT_APBHDMA_CHAN3  113
+#define MX50_INT_APBHDMA_CHAN4  114
+#define MX50_INT_APBHDMA_CHAN5  115
+#define MX50_INT_APBHDMA_CHAN6  116
+#define MX50_INT_APBHDMA_CHAN7  117
+
+#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 2af7a1056fc1..873807f96d70 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -2,31 +2,6 @@
 #define __MACH_MX51_H__
 
 /*
- * MX51 memory map:
- *
- *
- * Virt         Phys            Size    What
- * ---------------------------------------------------------------------------
- * fa3e0000     1ffe0000        128K    IRAM (SCCv2 RAM)
- *              30000000        256M    GPU
- *              40000000        512M    IPU
- * fa200000     60000000        1M      DEBUG
- * fb100000     70000000        1M      SPBA 0
- * fb000000     73f00000        1M      AIPS 1
- * fb200000     83f00000        1M      AIPS 2
- *              8fffc000        16K     TZIC (interrupt controller)
- *              90000000        256M    CSD0 SDRAM/DDR
- *              a0000000        256M    CSD1 SDRAM/DDR
- *              b0000000        128M    CS0 Flash
- *              b8000000        128M    CS1 Flash
- *              c0000000        128M    CS2 Flash
- *              c8000000        64M     CS3 Flash
- *              cc000000        32M     CS4 SRAM
- *              ce000000        32M     CS5 SRAM
- *              cfff0000        64K     NFC (NAND Flash AXI)
- */
-
-/*
  * IROM
  */
 #define MX51_IROM_BASE_ADDR             0x0
@@ -36,7 +11,6 @@
  * IRAM
  */
 #define MX51_IRAM_BASE_ADDR             0x1ffe0000      /* internal ram */
-#define MX51_IRAM_BASE_ADDR_VIRT        0xfa3e0000
 #define MX51_IRAM_PARTITIONS            16
 #define MX51_IRAM_SIZE          (MX51_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
 
@@ -45,7 +19,6 @@
 #define MX51_IPU_CTRL_BASE_ADDR         0x40000000
 
 #define MX51_DEBUG_BASE_ADDR            0x60000000
-#define MX51_DEBUG_BASE_ADDR_VIRT       0xfa200000
 #define MX51_DEBUG_SIZE                 SZ_1M
 
 #define MX51_ETB_BASE_ADDR              (MX51_DEBUG_BASE_ADDR + 0x01000)
@@ -61,7 +34,6 @@
  * SPBA global module enabled #0
  */
 #define MX51_SPBA0_BASE_ADDR            0x70000000
-#define MX51_SPBA0_BASE_ADDR_VIRT       0xfb100000
 #define MX51_SPBA0_SIZE                 SZ_1M
 
 #define MX51_ESDHC1_BASE_ADDR           (MX51_SPBA0_BASE_ADDR + 0x04000)
@@ -81,7 +53,6 @@
  * AIPS 1
  */
 #define MX51_AIPS1_BASE_ADDR            0x73f00000
-#define MX51_AIPS1_BASE_ADDR_VIRT       0xfb000000
 #define MX51_AIPS1_SIZE                 SZ_1M
 
 #define MX51_OTG_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x80000)
@@ -90,7 +61,7 @@
 #define MX51_GPIO3_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x8c000)
 #define MX51_GPIO4_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x90000)
 #define MX51_KPP_BASE_ADDR              (MX51_AIPS1_BASE_ADDR + 0x94000)
-#define MX51_WDOG_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0x98000)
+#define MX51_WDOG1_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x98000)
 #define MX51_WDOG2_BASE_ADDR            (MX51_AIPS1_BASE_ADDR + 0x9c000)
 #define MX51_GPT1_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa0000)
 #define MX51_SRTC_BASE_ADDR             (MX51_AIPS1_BASE_ADDR + 0xa4000)
@@ -109,7 +80,6 @@
  * AIPS 2
  */
 #define MX51_AIPS2_BASE_ADDR            0x83f00000
-#define MX51_AIPS2_BASE_ADDR_VIRT       0xfb200000
 #define MX51_AIPS2_SIZE                 SZ_1M
 
 #define MX51_PLL1_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0x80000)
@@ -139,7 +109,7 @@
 #define MX51_MIPI_HSC_BASE_ADDR         (MX51_AIPS2_BASE_ADDR + 0xdc000)
 #define MX51_ATA_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe0000)
 #define MX51_SIM_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe4000)
-#define MX51_SSI3BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xe8000)
+#define MX51_SSI3_BASE_ADDR             (MX51_AIPS2_BASE_ADDR + 0xe8000)
 #define MX51_FEC_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xec000)
 #define MX51_TVE_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf0000)
 #define MX51_VPU_BASE_ADDR              (MX51_AIPS2_BASE_ADDR + 0xf4000)
@@ -163,16 +133,8 @@
 #define MX51_GPU2D_BASE_ADDR            0xd0000000
 #define MX51_TZIC_BASE_ADDR             0xe0000000
 
-#define MX51_IO_ADDRESS(x) (                                            \
-        IMX_IO_ADDRESS(x, MX51_IRAM) ?:                                 \
-        IMX_IO_ADDRESS(x, MX51_DEBUG) ?:                                \
-        IMX_IO_ADDRESS(x, MX51_SPBA0) ?:                                \
-        IMX_IO_ADDRESS(x, MX51_AIPS1) ?:                                \
-        IMX_IO_ADDRESS(x, MX51_AIPS2))
-
-/* This is currently used in <mach/debug-macro.S>, but should go away */
-#define MX51_AIPS1_IO_ADDRESS(x)  \
-        (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
+#define MX51_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX51_IO_ADDRESS(x)              IOMEM(MX51_IO_P2V(x))
 
 /*
  * defines for SPBA modules
@@ -261,9 +223,9 @@
 #define MX51_DMA_REQ_EMI_WR             32
 #define MX51_DMA_REQ_CTI2_1             33
 #define MX51_DMA_REQ_EPIT2              34
-#define MX51_DMA_REQ_SSI3_RX2           35
+#define MX51_DMA_REQ_SSI3_RX1           35
 #define MX51_DMA_REQ_IPU                36
-#define MX51_DMA_REQ_SSI3_TX2           37
+#define MX51_DMA_REQ_SSI3_TX1           37
 #define MX51_DMA_REQ_CSPI_RX            38
 #define MX51_DMA_REQ_CSPI_TX            39
 #define MX51_DMA_REQ_SDHC3              40
@@ -272,8 +234,8 @@
 #define MX51_DMA_REQ_UART3_RX           43
 #define MX51_DMA_REQ_UART3_TX           44
 #define MX51_DMA_REQ_SPDIF              45
-#define MX51_DMA_REQ_SSI3_RX1           46
-#define MX51_DMA_REQ_SSI3_TX1           47
+#define MX51_DMA_REQ_SSI3_RX0           46
+#define MX51_DMA_REQ_SSI3_TX0           47
 
 /*
  * Interrupt numbers
@@ -289,8 +251,8 @@
 #define MX51_MXC_INT_IOMUX              7
 #define MX51_INT_NFC                    8
 #define MX51_MXC_INT_VPU                9
-#define MX51_MXC_INT_IPU_ERR            10
-#define MX51_MXC_INT_IPU_SYN            11
+#define MX51_INT_IPU_ERR                10
+#define MX51_INT_IPU_SYN                11
 #define MX51_MXC_INT_GPU                12
 #define MX51_MXC_INT_RESV13             13
 #define MX51_MXC_INT_USB_H1             14
@@ -375,7 +337,7 @@
 #define MX51_MXC_INT_FIRI               93
 #define MX51_MXC_INT_PWM2               94
 #define MX51_MXC_INT_SLIM_EXP           95
-#define MX51_MXC_INT_SSI3               96
+#define MX51_INT_SSI3                   96
 #define MX51_MXC_INT_EMI_BOOT           97
 #define MX51_MXC_INT_CTI1_TG3           98
 #define MX51_MXC_INT_SMC_RX             99
@@ -383,19 +345,6 @@
 #define MX51_MXC_INT_EMI_NFC            101
 #define MX51_MXC_INT_GPU_IDLE           102
 
-/* silicon revisions specific to i.MX51 */
-#define MX51_CHIP_REV_1_0               0x10
-#define MX51_CHIP_REV_1_1               0x11
-#define MX51_CHIP_REV_1_2               0x12
-#define MX51_CHIP_REV_1_3               0x13
-#define MX51_CHIP_REV_2_0               0x20
-#define MX51_CHIP_REV_2_1               0x21
-#define MX51_CHIP_REV_2_2               0x22
-#define MX51_CHIP_REV_2_3               0x23
-#define MX51_CHIP_REV_3_0               0x30
-#define MX51_CHIP_REV_3_1               0x31
-#define MX51_CHIP_REV_3_2               0x32
-
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 extern int mx51_revision(void);
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
new file mode 100644
index 000000000000..9577cdbf7fad
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -0,0 +1,353 @@
+#ifndef __MACH_MX53_H__
+#define __MACH_MX53_H__
+
+/*
+ * IROM
+ */
+#define MX53_IROM_BASE_ADDR             0x0
+#define MX53_IROM_SIZE                  SZ_64K
+
+/* TZIC */
+#define MX53_TZIC_BASE_ADDR             0x0FFFC000
+
+/*
+ * AHCI SATA
+ */
+#define MX53_SATA_BASE_ADDR             0x10000000
+
+/*
+ * NFC
+ */
+#define MX53_NFC_AXI_BASE_ADDR  0xF7FF0000      /* NAND flash AXI */
+#define MX53_NFC_AXI_SIZE               SZ_64K
+
+/*
+ * IRAM
+ */
+#define MX53_IRAM_BASE_ADDR     0xF8000000      /* internal ram */
+#define MX53_IRAM_PARTITIONS    16
+#define MX53_IRAM_SIZE          (MX53_IRAM_PARTITIONS * SZ_8K)  /* 128KB */
+
+/*
+ * Graphics Memory of GPU
+ */
+#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
+#define MX53_GPU2D_BASE_ADDR            0x20000000
+#define MX53_GPU_BASE_ADDR              0x30000000
+#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
+
+#define MX53_DEBUG_BASE_ADDR            0x40000000
+#define MX53_DEBUG_SIZE         SZ_1M
+#define MX53_ETB_BASE_ADDR              (MX53_DEBUG_BASE_ADDR + 0x00001000)
+#define MX53_ETM_BASE_ADDR              (MX53_DEBUG_BASE_ADDR + 0x00002000)
+#define MX53_TPIU_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00003000)
+#define MX53_CTI0_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00004000)
+#define MX53_CTI1_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00005000)
+#define MX53_CTI2_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00006000)
+#define MX53_CTI3_BASE_ADDR             (MX53_DEBUG_BASE_ADDR + 0x00007000)
+#define MX53_CORTEX_DBG_BASE_ADDR       (MX53_DEBUG_BASE_ADDR + 0x00008000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define MX53_SPBA0_BASE_ADDR            0x50000000
+#define MX53_SPBA0_SIZE         SZ_1M
+
+#define MX53_MMC_SDHC1_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00004000)
+#define MX53_MMC_SDHC2_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00008000)
+#define MX53_UART3_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x0000C000)
+#define MX53_CSPI1_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x00010000)
+#define MX53_SSI2_BASE_ADDR             (MX53_SPBA0_BASE_ADDR + 0x00014000)
+#define MX53_MMC_SDHC3_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00020000)
+#define MX53_MMC_SDHC4_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00024000)
+#define MX53_SPDIF_BASE_ADDR            (MX53_SPBA0_BASE_ADDR + 0x00028000)
+#define MX53_ASRC_BASE_ADDR             (MX53_SPBA0_BASE_ADDR + 0x0002C000)
+#define MX53_ATA_DMA_BASE_ADDR  (MX53_SPBA0_BASE_ADDR + 0x00030000)
+#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
+#define MX53_HSI2C_DMA_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x00038000)
+#define MX53_SPBA_CTRL_BASE_ADDR        (MX53_SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 1
+ */
+#define MX53_AIPS1_BASE_ADDR    0x53F00000
+#define MX53_AIPS1_SIZE         SZ_1M
+
+#define MX53_OTG_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x00080000)
+#define MX53_GPIO1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00084000)
+#define MX53_GPIO2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00088000)
+#define MX53_GPIO3_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0008C000)
+#define MX53_GPIO4_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x00090000)
+#define MX53_KPP_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x00094000)
+#define MX53_WDOG_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x00098000)
+#define MX53_WDOG2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x0009C000)
+#define MX53_GPT1_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A0000)
+#define MX53_SRTC_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000A4000)
+#define MX53_IOMUXC_BASE_ADDR   (MX53_AIPS1_BASE_ADDR + 0x000A8000)
+#define MX53_EPIT1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000AC000)
+#define MX53_EPIT2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000B0000)
+#define MX53_PWM1_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000B4000)
+#define MX53_PWM2_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000B8000)
+#define MX53_UART1_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000BC000)
+#define MX53_UART2_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000C0000)
+#define MX53_SRC_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D0000)
+#define MX53_CCM_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D4000)
+#define MX53_GPC_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000D8000)
+#define MX53_GPIO5_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000DC000)
+#define MX53_GPIO6_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000E0000)
+#define MX53_GPIO7_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000E4000)
+#define MX53_ATA_BASE_ADDR      (MX53_AIPS1_BASE_ADDR + 0x000E8000)
+#define MX53_I2C3_BASE_ADDR     (MX53_AIPS1_BASE_ADDR + 0x000EC000)
+#define MX53_UART4_BASE_ADDR    (MX53_AIPS1_BASE_ADDR + 0x000F0000)
+
+/*
+ * AIPS 2
+ */
+#define MX53_AIPS2_BASE_ADDR            0x63F00000
+#define MX53_AIPS2_SIZE                 SZ_1M
+
+#define MX53_PLL1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00080000)
+#define MX53_PLL2_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00084000)
+#define MX53_PLL3_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x00088000)
+#define MX53_PLL4_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x0008C000)
+#define MX53_UART5_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x00090000)
+#define MX53_AHBMAX_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x00094000)
+#define MX53_IIM_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x00098000)
+#define MX53_CSU_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x0009C000)
+#define MX53_ARM_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000A0000)
+#define MX53_OWIRE_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000A4000)
+#define MX53_FIRI_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000A8000)
+#define MX53_CSPI2_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000AC000)
+#define MX53_SDMA_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000B0000)
+#define MX53_SCC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000B4000)
+#define MX53_ROMCP_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000B8000)
+#define MX53_RTIC_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000BC000)
+#define MX53_CSPI3_BASE_ADDR    (MX53_AIPS2_BASE_ADDR + 0x000C0000)
+#define MX53_I2C2_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C4000)
+#define MX53_I2C1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000C8000)
+#define MX53_SSI1_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000CC000)
+#define MX53_AUDMUX_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000D0000)
+#define MX53_RTC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000D4000)
+#define MX53_M4IF_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000D8000)
+#define MX53_ESDCTL_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000D9000)
+#define MX53_WEIM_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000DA000)
+#define MX53_NFC_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000DB000)
+#define MX53_EMI_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
+#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
+#define MX53_MLB_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000E4000)
+#define MX53_SSI3_BASE_ADDR     (MX53_AIPS2_BASE_ADDR + 0x000E8000)
+#define MX53_MXC_FEC_BASE_ADDR  (MX53_AIPS2_BASE_ADDR + 0x000EC000)
+#define MX53_TVE_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000F0000)
+#define MX53_VPU_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000F4000)
+#define MX53_SAHARA_BASE_ADDR   (MX53_AIPS2_BASE_ADDR + 0x000F8000)
+#define MX53_PTP_BASE_ADDR      (MX53_AIPS2_BASE_ADDR + 0x000FC000)
+
+/*
+ * Memory regions and CS
+ */
+#define MX53_CSD0_BASE_ADDR             0x90000000
+#define MX53_CSD1_BASE_ADDR             0xA0000000
+#define MX53_CS0_BASE_ADDR              0xB0000000
+#define MX53_CS1_BASE_ADDR              0xB8000000
+#define MX53_CS2_BASE_ADDR              0xC0000000
+#define MX53_CS3_BASE_ADDR              0xC8000000
+#define MX53_CS4_BASE_ADDR              0xCC000000
+#define MX53_CS5_BASE_ADDR              0xCE000000
+
+#define MX53_IO_P2V(x)                  IMX_IO_P2V(x)
+#define MX53_IO_ADDRESS(x)              IOMEM(MX53_IO_P2V(x))
+
+/*
+ * defines for SPBA modules
+ */
+#define MX53_SPBA_SDHC1 0x04
+#define MX53_SPBA_SDHC2 0x08
+#define MX53_SPBA_UART3 0x0C
+#define MX53_SPBA_CSPI1 0x10
+#define MX53_SPBA_SSI2          0x14
+#define MX53_SPBA_SDHC3 0x20
+#define MX53_SPBA_SDHC4 0x24
+#define MX53_SPBA_SPDIF 0x28
+#define MX53_SPBA_ATA           0x30
+#define MX53_SPBA_SLIM          0x34
+#define MX53_SPBA_HSI2C 0x38
+#define MX53_SPBA_CTRL          0x3C
+
+/*
+ * DMA request assignments
+ */
+#define MX53_DMA_REQ_SSI3_TX1           47
+#define MX53_DMA_REQ_SSI3_RX1           46
+#define MX53_DMA_REQ_SSI3_TX2           45
+#define MX53_DMA_REQ_SSI3_RX2           44
+#define MX53_DMA_REQ_UART3_TX   43
+#define MX53_DMA_REQ_UART3_RX   42
+#define MX53_DMA_REQ_ESAI_TX            41
+#define MX53_DMA_REQ_ESAI_RX            40
+#define MX53_DMA_REQ_CSPI_TX            39
+#define MX53_DMA_REQ_CSPI_RX            38
+#define MX53_DMA_REQ_ASRC_DMA6  37
+#define MX53_DMA_REQ_ASRC_DMA5  36
+#define MX53_DMA_REQ_ASRC_DMA4  35
+#define MX53_DMA_REQ_ASRC_DMA3  34
+#define MX53_DMA_REQ_ASRC_DMA2  33
+#define MX53_DMA_REQ_ASRC_DMA1  32
+#define MX53_DMA_REQ_EMI_WR             31
+#define MX53_DMA_REQ_EMI_RD             30
+#define MX53_DMA_REQ_SSI1_TX1           29
+#define MX53_DMA_REQ_SSI1_RX1           28
+#define MX53_DMA_REQ_SSI1_TX2           27
+#define MX53_DMA_REQ_SSI1_RX2           26
+#define MX53_DMA_REQ_SSI2_TX1           25
+#define MX53_DMA_REQ_SSI2_RX1           24
+#define MX53_DMA_REQ_SSI2_TX2           23
+#define MX53_DMA_REQ_SSI2_RX2           22
+#define MX53_DMA_REQ_I2C2_SDHC2 21
+#define MX53_DMA_REQ_I2C1_SDHC1 20
+#define MX53_DMA_REQ_UART1_TX   19
+#define MX53_DMA_REQ_UART1_RX   18
+#define MX53_DMA_REQ_UART5_TX   17
+#define MX53_DMA_REQ_UART5_RX   16
+#define MX53_DMA_REQ_SPDIF_TX           15
+#define MX53_DMA_REQ_SPDIF_RX           14
+#define MX53_DMA_REQ_UART2_FIRI_TX      13
+#define MX53_DMA_REQ_UART2_FIRI_RX      12
+#define MX53_DMA_REQ_SDHC4              11
+#define MX53_DMA_REQ_I2C3_SDHC3 10
+#define MX53_DMA_REQ_CSPI2_TX           9
+#define MX53_DMA_REQ_CSPI2_RX           8
+#define MX53_DMA_REQ_CSPI1_TX           7
+#define MX53_DMA_REQ_CSPI1_RX           6
+#define MX53_DMA_REQ_IPU                5
+#define MX53_DMA_REQ_ATA_TX_END 4
+#define MX53_DMA_REQ_ATA_UART4_TX       3
+#define MX53_DMA_REQ_ATA_UART4_RX       2
+#define MX53_DMA_REQ_GPC                1
+#define MX53_DMA_REQ_VPU                0
+
+/*
+ * Interrupt numbers
+ */
+#define MX53_INT_RESV0          0
+#define MX53_INT_MMC_SDHC1      1
+#define MX53_INT_MMC_SDHC2      2
+#define MX53_INT_MMC_SDHC3      3
+#define MX53_INT_MMC_SDHC4      4
+#define MX53_INT_RESV5  5
+#define MX53_INT_SDMA   6
+#define MX53_INT_IOMUX  7
+#define MX53_INT_NFC    8
+#define MX53_INT_VPU    9
+#define MX53_INT_IPU_ERR        10
+#define MX53_INT_IPU_SYN        11
+#define MX53_INT_GPU    12
+#define MX53_INT_RESV13 13
+#define MX53_INT_USB_H1 14
+#define MX53_INT_EMI    15
+#define MX53_INT_USB_H2 16
+#define MX53_INT_USB_H3 17
+#define MX53_INT_USB_OTG        18
+#define MX53_INT_SAHARA_H0      19
+#define MX53_INT_SAHARA_H1      20
+#define MX53_INT_SCC_SMN        21
+#define MX53_INT_SCC_STZ        22
+#define MX53_INT_SCC_SCM        23
+#define MX53_INT_SRTC_NTZ       24
+#define MX53_INT_SRTC_TZ        25
+#define MX53_INT_RTIC   26
+#define MX53_INT_CSU    27
+#define MX53_INT_SATA   28
+#define MX53_INT_SSI1   29
+#define MX53_INT_SSI2   30
+#define MX53_INT_UART1  31
+#define MX53_INT_UART2  32
+#define MX53_INT_UART3  33
+#define MX53_INT_RESV34 34
+#define MX53_INT_RESV35 35
+#define MX53_INT_CSPI1  36
+#define MX53_INT_CSPI2  37
+#define MX53_INT_CSPI   38
+#define MX53_INT_GPT    39
+#define MX53_INT_EPIT1  40
+#define MX53_INT_EPIT2  41
+#define MX53_INT_GPIO1_INT7     42
+#define MX53_INT_GPIO1_INT6     43
+#define MX53_INT_GPIO1_INT5     44
+#define MX53_INT_GPIO1_INT4     45
+#define MX53_INT_GPIO1_INT3     46
+#define MX53_INT_GPIO1_INT2     47
+#define MX53_INT_GPIO1_INT1     48
+#define MX53_INT_GPIO1_INT0     49
+#define MX53_INT_GPIO1_LOW      50
+#define MX53_INT_GPIO1_HIGH     51
+#define MX53_INT_GPIO2_LOW      52
+#define MX53_INT_GPIO2_HIGH     53
+#define MX53_INT_GPIO3_LOW      54
+#define MX53_INT_GPIO3_HIGH     55
+#define MX53_INT_GPIO4_LOW      56
+#define MX53_INT_GPIO4_HIGH     57
+#define MX53_INT_WDOG1  58
+#define MX53_INT_WDOG2  59
+#define MX53_INT_KPP    60
+#define MX53_INT_PWM1   61
+#define MX53_INT_I2C1   62
+#define MX53_INT_I2C2   63
+#define MX53_INT_I2C3   64
+#define MX53_INT_RESV65 65
+#define MX53_INT_RESV66 66
+#define MX53_INT_SPDIF  67
+#define MX53_INT_SIM_DAT        68
+#define MX53_INT_IIM    69
+#define MX53_INT_ATA    70
+#define MX53_INT_CCM1   71
+#define MX53_INT_CCM2   72
+#define MX53_INT_GPC1   73
+#define MX53_INT_GPC2   74
+#define MX53_INT_SRC    75
+#define MX53_INT_NM             76
+#define MX53_INT_PMU    77
+#define MX53_INT_CTI_IRQ        78
+#define MX53_INT_CTI1_TG0       79
+#define MX53_INT_CTI1_TG1       80
+#define MX53_INT_ESAI   81
+#define MX53_INT_CAN1   82
+#define MX53_INT_CAN2   83
+#define MX53_INT_GPU2_IRQ       84
+#define MX53_INT_GPU2_BUSY      85
+#define MX53_INT_RESV86 86
+#define MX53_INT_FEC    87
+#define MX53_INT_OWIRE  88
+#define MX53_INT_CTI1_TG2       89
+#define MX53_INT_SJC    90
+#define MX53_INT_TVE    92
+#define MX53_INT_FIRI   93
+#define MX53_INT_PWM2   94
+#define MX53_INT_SLIM_EXP       95
+#define MX53_INT_SSI3   96
+#define MX53_INT_EMI_BOOT       97
+#define MX53_INT_CTI1_TG3       98
+#define MX53_INT_SMC_RX 99
+#define MX53_INT_VPU_IDLE       100
+#define MX53_INT_EMI_NFC        101
+#define MX53_INT_GPU_IDLE       102
+#define MX53_INT_GPIO5_LOW      103
+#define MX53_INT_GPIO5_HIGH     104
+#define MX53_INT_GPIO6_LOW      105
+#define MX53_INT_GPIO6_HIGH     106
+#define MX53_INT_GPIO7_LOW      107
+#define MX53_INT_GPIO7_HIGH     108
+
+/* silicon revisions specific to i.MX53 */
+#define MX53_CHIP_REV_1_0               0x10
+#define MX53_CHIP_REV_1_1               0x11
+#define MX53_CHIP_REV_1_2               0x12
+#define MX53_CHIP_REV_1_3               0x13
+#define MX53_CHIP_REV_2_0               0x20
+#define MX53_CHIP_REV_2_1               0x21
+#define MX53_CHIP_REV_2_2               0x22
+#define MX53_CHIP_REV_2_3               0x23
+#define MX53_CHIP_REV_3_0               0x30
+#define MX53_CHIP_REV_3_1               0x31
+#define MX53_CHIP_REV_3_2               0x32
+
+#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a42c7207082d..04c7a26b1f26 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -32,9 +32,25 @@
 #define MXC_CPU_MX27            27
 #define MXC_CPU_MX31            31
 #define MXC_CPU_MX35            35
+#define MXC_CPU_MX50            50
 #define MXC_CPU_MX51            51
+#define MXC_CPU_MX53            53
 #define MXC_CPU_MXC91231        91231
 
+#define IMX_CHIP_REVISION_1_0           0x10
+#define IMX_CHIP_REVISION_1_1           0x11
+#define IMX_CHIP_REVISION_1_2           0x12
+#define IMX_CHIP_REVISION_1_3           0x13
+#define IMX_CHIP_REVISION_2_0           0x20
+#define IMX_CHIP_REVISION_2_1           0x21
+#define IMX_CHIP_REVISION_2_2           0x22
+#define IMX_CHIP_REVISION_2_3           0x23
+#define IMX_CHIP_REVISION_3_0           0x30
+#define IMX_CHIP_REVISION_3_1           0x31
+#define IMX_CHIP_REVISION_3_2           0x32
+#define IMX_CHIP_REVISION_3_3           0x33
+#define IMX_CHIP_REVISION_UNKNOWN       0xff
+
 #ifndef __ASSEMBLY__
 extern unsigned int __mxc_cpu_type;
 #endif
@@ -111,7 +127,19 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx35()          (0)
 #endif
 
-#ifdef CONFIG_ARCH_MX5
+#ifdef CONFIG_ARCH_MX50
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MX50
+# endif
+# define cpu_is_mx50()          (mxc_cpu_type == MXC_CPU_MX50)
+#else
+# define cpu_is_mx50()          (0)
+#endif
+
+#ifdef CONFIG_ARCH_MX51
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
 #  define mxc_cpu_type __mxc_cpu_type
@@ -123,6 +151,18 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx51()          (0)
 #endif
 
+#ifdef CONFIG_ARCH_MX53
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MX53
+# endif
+# define cpu_is_mx53()          (mxc_cpu_type == MXC_CPU_MX53)
+#else
+# define cpu_is_mx53()          (0)
+#endif
+
 #ifdef CONFIG_ARCH_MXC91231
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 0ca3101ebf36..765190fe6332 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -21,14 +21,12 @@
  * L2CC
  */
 #define MXC91231_L2CC_BASE_ADDR         0x30000000
-#define MXC91231_L2CC_BASE_ADDR_VIRT    0xF9000000
 #define MXC91231_L2CC_SIZE              SZ_64K
 
 /*
  * AIPS 1
  */
 #define MXC91231_AIPS1_BASE_ADDR        0x43F00000
-#define MXC91231_AIPS1_BASE_ADDR_VIRT   0xFC000000
 #define MXC91231_AIPS1_SIZE             SZ_1M
 
 #define MXC91231_AIPS1_CTRL_BASE_ADDR   MXC91231_AIPS1_BASE_ADDR
@@ -53,7 +51,6 @@
  * AIPS 2
  */
 #define MXC91231_AIPS2_BASE_ADDR        0x53F00000
-#define MXC91231_AIPS2_BASE_ADDR_VIRT   0xFC100000
 #define MXC91231_AIPS2_SIZE             SZ_1M
 
 #define MXC91231_GEMK_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
@@ -79,7 +76,6 @@
  * SPBA global module 0
  */
 #define MXC91231_SPBA0_BASE_ADDR        0x50000000
-#define MXC91231_SPBA0_BASE_ADDR_VIRT   0xFC200000
 #define MXC91231_SPBA0_SIZE             SZ_1M
 
 #define MXC91231_MMC_SDHC1_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x04000)
@@ -109,7 +105,6 @@
  * SPBA global module 1
  */
 #define MXC91231_SPBA1_BASE_ADDR        0x52000000
-#define MXC91231_SPBA1_BASE_ADDR_VIRT   0xFC300000
 #define MXC91231_SPBA1_SIZE             SZ_1M
 
 #define MXC91231_MQSPI_BASE_ADDR        (MXC91231_SPBA1_BASE_ADDR + 0x34000)
@@ -144,18 +139,15 @@
  * ROMP and AVIC
  */
 #define MXC91231_ROMP_BASE_ADDR         0x60000000
-#define MXC91231_ROMP_BASE_ADDR_VIRT    0xFC400000
 #define MXC91231_ROMP_SIZE              SZ_64K
 
 #define MXC91231_AVIC_BASE_ADDR         0x68000000
-#define MXC91231_AVIC_BASE_ADDR_VIRT    0xFC410000
 #define MXC91231_AVIC_SIZE              SZ_64K
 
 /*
  * NAND, SDRAM, WEIM, M3IF, EMI controllers
  */
 #define MXC91231_X_MEMC_BASE_ADDR       0xB8000000
-#define MXC91231_X_MEMC_BASE_ADDR_VIRT  0xFC420000
 #define MXC91231_X_MEMC_SIZE            SZ_64K
 
 #define MXC91231_NFC_BASE_ADDR          (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
@@ -183,19 +175,10 @@
 /*
  * This macro defines the physical to virtual address mapping for all the
  * peripheral modules. It is used by passing in the physical address as x
- * and returning the virtual address. If the physical address is not mapped,
- * it returns 0.
+ * and returning the virtual address.
  */
-
-#define MXC91231_IO_ADDRESS(x) (                                        \
-        IMX_IO_ADDRESS(x, MXC91231_L2CC) ?:                             \
-        IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?:                           \
-        IMX_IO_ADDRESS(x, MXC91231_ROMP) ?:                             \
-        IMX_IO_ADDRESS(x, MXC91231_AVIC) ?:                             \
-        IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?:                            \
-        IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?:                            \
-        IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?:                            \
-        IMX_IO_ADDRESS(x, MXC91231_AIPS2))
+#define MXC91231_IO_P2V(x)              IMX_IO_P2V(x)
+#define MXC91231_IO_ADDRESS(x)          IOMEM(MXC91231_IO_P2V(x))
 
 /*
  * Interrupt numbers
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 7fc5f9946199..a523a4079299 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -31,6 +31,7 @@
 #define MXC_USBCTRL_OFFSET              0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET     0x8
 #define MXC_USB_PHY_CTR_FUNC2_OFFSET    0xc
+#define MXC_USBH2CTRL_OFFSET            0x14
 
 #define MX5_USBOTHER_REGS_OFFSET        0x800
 
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h
index 9be112227ac4..913e0432e40e 100644
--- a/arch/arm/plat-mxc/include/mach/sdma.h
+++ b/arch/arm/plat-mxc/include/mach/sdma.h
@@ -2,16 +2,62 @@
 #define __MACH_MXC_SDMA_H__
 
 /**
+ * struct sdma_script_start_addrs - SDMA script start pointers
+ *
+ * start addresses of the different functions in the physical
+ * address space of the SDMA engine.
+ */
+struct sdma_script_start_addrs {
+        s32 ap_2_ap_addr;
+        s32 ap_2_bp_addr;
+        s32 ap_2_ap_fixed_addr;
+        s32 bp_2_ap_addr;
+        s32 loopback_on_dsp_side_addr;
+        s32 mcu_interrupt_only_addr;
+        s32 firi_2_per_addr;
+        s32 firi_2_mcu_addr;
+        s32 per_2_firi_addr;
+        s32 mcu_2_firi_addr;
+        s32 uart_2_per_addr;
+        s32 uart_2_mcu_addr;
+        s32 per_2_app_addr;
+        s32 mcu_2_app_addr;
+        s32 per_2_per_addr;
+        s32 uartsh_2_per_addr;
+        s32 uartsh_2_mcu_addr;
+        s32 per_2_shp_addr;
+        s32 mcu_2_shp_addr;
+        s32 ata_2_mcu_addr;
+        s32 mcu_2_ata_addr;
+        s32 app_2_per_addr;
+        s32 app_2_mcu_addr;
+        s32 shp_2_per_addr;
+        s32 shp_2_mcu_addr;
+        s32 mshc_2_mcu_addr;
+        s32 mcu_2_mshc_addr;
+        s32 spdif_2_mcu_addr;
+        s32 mcu_2_spdif_addr;
+        s32 asrc_2_mcu_addr;
+        s32 ext_mem_2_ipu_addr;
+        s32 descrambler_addr;
+        s32 dptc_dvfs_addr;
+        s32 utra_addr;
+        s32 ram_code_start_addr;
+};
+
+/**
  * struct sdma_platform_data - platform specific data for SDMA engine
  *
  * @sdma_version        The version of this SDMA engine
  * @cpu_name            used to generate the firmware name
  * @to_version          CPU Tape out version
+ * @script_addrs        SDMA scripts addresses in SDMA ROM
  */
 struct sdma_platform_data {
         int sdma_version;
         char *cpu_name;
         int to_version;
+        struct sdma_script_start_addrs *script_addrs;
 };
 
 #endif /* __MACH_MXC_SDMA_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 9dd9c2085aad..3a70ebf0477f 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -63,6 +63,8 @@ static inline void flush(void)
 #define MX3X_UART1_BASE_ADDR    0x43F90000
 #define MX3X_UART2_BASE_ADDR    0x43F94000
 #define MX51_UART1_BASE_ADDR    0x73fbc000
+#define MX50_UART1_BASE_ADDR    0x53fbc000
+#define MX53_UART1_BASE_ADDR    0x53fbc000
 
 static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 {
@@ -102,6 +104,12 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
         case MACH_TYPE_EUKREA_CPUIMX51SD:
                 uart_base = MX51_UART1_BASE_ADDR;
                 break;
+        case MACH_TYPE_MX50_RDP:
+                uart_base = MX50_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_MX53_EVK:
+                uart_base = MX53_UART1_BASE_ADDR;
+                break;
         default:
                 break;
         }
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index b318c6a222d5..99a9cdb9d6be 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -32,31 +32,38 @@
 static void __iomem *base;
 
 /*
- * setups a single pad in the iomuxer
+ * configures a single pad in the iomuxer
  */
-int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
+int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 {
-        if (pad->mux_ctrl_ofs)
-                __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
+        u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
+        u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+        u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
+        u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
+        u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
+        u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 
-        if (pad->select_input_ofs)
-                __raw_writel(pad->select_input,
-                                base + pad->select_input_ofs);
+        if (mux_ctrl_ofs)
+                __raw_writel(mux_mode, base + mux_ctrl_ofs);
+
+        if (sel_input_ofs)
+                __raw_writel(sel_input, base + sel_input_ofs);
+
+        if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+                __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
 
-        if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
-                __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
         return 0;
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
 
-int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
+int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
 {
-        struct pad_desc *p = pad_list;
+        iomux_v3_cfg_t *p = pad_list;
         int i;
         int ret;
 
         for (i = 0; i < count; i++) {
-                ret = mxc_iomux_v3_setup_pad(p);
+                ret = mxc_iomux_v3_setup_pad(*p);
                 if (ret)
                         return ret;
                 p++;
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
new file mode 100644
index 000000000000..0c799ac27730
--- /dev/null
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) BitBox Ltd 2010
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/irq.h>
+
+#include "irq-common.h"
+
+int imx_irq_set_priority(unsigned char irq, unsigned char prio)
+{
+        struct mxc_irq_chip *chip;
+        struct irq_chip *base;
+        int ret;
+
+        ret = -ENOSYS;
+
+        base = get_irq_chip(irq);
+        if (base) {
+                chip = container_of(base, struct mxc_irq_chip, base);
+                if (chip->set_priority)
+                        ret = chip->set_priority(irq, prio);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(imx_irq_set_priority);
+
+int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
+{
+        struct mxc_irq_chip *chip;
+        struct irq_chip *base;
+        int ret;
+
+        ret = -ENOSYS;
+
+        base = get_irq_chip(irq);
+        if (base) {
+                chip = container_of(base, struct mxc_irq_chip, base);
+                if (chip->set_irq_fiq)
+                        ret = chip->set_irq_fiq(irq, type);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(mxc_set_irq_fiq);
diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h
new file mode 100644
index 000000000000..7203543fb1b3
--- /dev/null
+++ b/arch/arm/plat-mxc/irq-common.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) BitBox Ltd 2010
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+
+#ifndef __PLAT_MXC_IRQ_COMMON_H__
+#define __PLAT_MXC_IRQ_COMMON_H__
+
+struct mxc_irq_chip
+{
+        struct irq_chip base;
+        int (*set_priority)(unsigned char irq, unsigned char prio);
+        int (*set_irq_fiq)(unsigned int irq, unsigned int type);
+};
+
+#endif
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 925bce4607e7..3455fc0575a6 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -26,6 +26,7 @@
 #include <mach/common.h>
 #include <asm/proc-fns.h>
 #include <asm/system.h>
+#include <asm/mach-types.h>
 
 static void __iomem *wdog_base;
 
@@ -42,12 +43,19 @@ void arch_reset(char mode, const char *cmd)
                 return;
         }
 #endif
+#ifdef CONFIG_MACH_MX51_EFIKAMX
+        if (machine_is_mx51_efikamx()) {
+                mx51_efikamx_reset();
+                return;
+        }
+#endif
+
         if (cpu_is_mx1()) {
                 wcr_enable = (1 << 0);
         } else {
                 struct clk *clk;
 
-                clk = clk_get_sys("imx-wdt.0", NULL);
+                clk = clk_get_sys("imx2-wdt.0", NULL);
                 if (!IS_ERR(clk))
                         clk_enable(clk);
                 wcr_enable = (1 << 2);
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index f9a1b059a76c..9f0c2610595e 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -120,7 +120,6 @@ static struct clocksource clocksource_mxc = {
         .rating         = 200,
         .read           = mx1_2_get_cycles,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 20,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -131,9 +130,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
         if (timer_is_v2())
                 clocksource_mxc.read = v2_get_cycles;
 
-        clocksource_mxc.mult = clocksource_hz2mult(c,
-                                        clocksource_mxc.shift);
-        clocksource_register(&clocksource_mxc);
+        clocksource_register_hz(&clocksource_mxc, c);
 
         return 0;
 }
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 3703ab28257f..e69ed8a8c203 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -21,6 +21,8 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 
+#include "irq-common.h"
+
 /*
  *****************************************
  * TZIC Registers                        *
@@ -47,6 +49,25 @@
 
 void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
 
+#ifdef CONFIG_FIQ
+static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
+{
+        unsigned int index, mask, value;
+
+        index = irq >> 5;
+        if (unlikely(index >= 4))
+                return -EINVAL;
+        mask = 1U << (irq & 0x1F);
+
+        value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
+        if (type)
+                value &= ~mask;
+        __raw_writel(value, tzic_base + TZIC_INTSEC0(index));
+
+        return 0;
+}
+#endif
+
 /**
  * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
  *
@@ -104,12 +125,17 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
         return 0;
 }
 
-static struct irq_chip mxc_tzic_chip = {
-        .name = "MXC_TZIC",
-        .ack = tzic_mask_irq,
-        .mask = tzic_mask_irq,
-        .unmask = tzic_unmask_irq,
-        .set_wake = tzic_set_wake_irq,
+static struct mxc_irq_chip mxc_tzic_chip = {
+        .base = {
+                .name = "MXC_TZIC",
+                .ack = tzic_mask_irq,
+                .mask = tzic_mask_irq,
+                .unmask = tzic_unmask_irq,
+                .set_wake = tzic_set_wake_irq,
+        },
+#ifdef CONFIG_FIQ
+        .set_irq_fiq = tzic_set_irq_fiq,
+#endif
 };
 
 /*
@@ -141,10 +167,16 @@ void __init tzic_init_irq(void __iomem *irqbase)
         /* all IRQ no FIQ Warning :: No selection */
 
         for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
-                set_irq_chip(i, &mxc_tzic_chip);
+                set_irq_chip(i, &mxc_tzic_chip.base);
                 set_irq_handler(i, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
+
+#ifdef CONFIG_FIQ
+        /* Initialize FIQ */
+        init_FIQ();
+#endif
+
         pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
 }
 
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
index 5da3f97c537b..187f4e84bb22 100644
--- a/arch/arm/plat-nomadik/Kconfig
+++ b/arch/arm/plat-nomadik/Kconfig
@@ -14,6 +14,7 @@ if PLAT_NOMADIK
 
 config HAS_MTU
         bool
+        select HAVE_SCHED_CLOCK
         help
           Support for Multi Timer Unit. MTU provides access
           to multiple interrupt generating programmable
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 85e6fd212a41..eda4e3a11a3d 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -119,7 +119,7 @@ static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
 }
 
 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
-                             pin_cfg_t cfg)
+                             pin_cfg_t cfg, bool sleep)
 {
         static const char *afnames[] = {
                 [NMK_GPIO_ALT_GPIO]     = "GPIO",
@@ -145,11 +145,34 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
         int output = PIN_DIR(cfg);
         int val = PIN_VAL(cfg);
 
-        dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s (%s%s)\n",
-                pin, afnames[af], pullnames[pull], slpmnames[slpm],
+        dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
+                pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
                 output ? "output " : "input",
                 output ? (val ? "high" : "low") : "");
 
+        if (sleep) {
+                int slpm_pull = PIN_SLPM_PULL(cfg);
+                int slpm_output = PIN_SLPM_DIR(cfg);
+                int slpm_val = PIN_SLPM_VAL(cfg);
+
+                /*
+                 * The SLPM_* values are normal values + 1 to allow zero to
+                 * mean "same as normal".
+                 */
+                if (slpm_pull)
+                        pull = slpm_pull - 1;
+                if (slpm_output)
+                        output = slpm_output - 1;
+                if (slpm_val)
+                        val = slpm_val - 1;
+
+                dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
+                        pin,
+                        slpm_pull ? pullnames[pull] : "same",
+                        slpm_output ? (output ? "output" : "input") : "same",
+                        slpm_val ? (val ? "high" : "low") : "same");
+        }
+
         if (output)
                 __nmk_gpio_make_output(nmk_chip, offset, val);
         else {
@@ -175,7 +198,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
  * side-effects.  The gpio can be manipulated later using standard GPIO API
  * calls.
  */
-int nmk_config_pin(pin_cfg_t cfg)
+int nmk_config_pin(pin_cfg_t cfg, bool sleep)
 {
         struct nmk_gpio_chip *nmk_chip;
         int gpio = PIN_NUM(cfg);
@@ -186,7 +209,7 @@ int nmk_config_pin(pin_cfg_t cfg)
                 return -EINVAL;
 
         spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg);
+        __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep);
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
 
         return 0;
@@ -207,7 +230,7 @@ int nmk_config_pins(pin_cfg_t *cfgs, int num)
         int i;
 
         for (i = 0; i < num; i++) {
-                int ret = nmk_config_pin(cfgs[i]);
+                ret = nmk_config_pin(cfgs[i], false);
                 if (ret)
                         break;
         }
@@ -216,6 +239,21 @@ int nmk_config_pins(pin_cfg_t *cfgs, int num)
 }
 EXPORT_SYMBOL(nmk_config_pins);
 
+int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
+{
+        int ret = 0;
+        int i;
+
+        for (i = 0; i < num; i++) {
+                ret = nmk_config_pin(cfgs[i], true);
+                if (ret)
+                        break;
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(nmk_config_pins_sleep);
+
 /**
  * nmk_gpio_set_slpm() - configure the sleep mode of a pin
  * @gpio: pin number
@@ -634,7 +672,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
 
         chip = &nmk_chip->chip;
         chip->base = pdata->first_gpio;
-        chip->label = pdata->name;
+        chip->label = pdata->name ?: dev_name(&dev->dev);
         chip->dev = &dev->dev;
         chip->owner = THIS_MODULE;
 
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 8c5ae3f2acf8..05a3936ae6d1 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -19,16 +19,22 @@
  *      bit  9..10 - Alternate Function Selection
  *      bit 11..12 - Pull up/down state
  *      bit     13 - Sleep mode behaviour
- *      bit     14 - (sleep mode) Direction
- *      bit     15 - (sleep mode) Value (if output)
+ *      bit     14 - Direction
+ *      bit     15 - Value (if output)
+ *      bit 16..18 - SLPM pull up/down state
+ *      bit 19..20 - SLPM direction
+ *      bit 21..22 - SLPM Value (if output)
  *
  * to facilitate the definition, the following macros are provided
  *
  * PIN_CFG_DEFAULT - default config (0):
  *                   pull up/down = disabled
  *                   sleep mode = input/wakeup
- *                   (sleep mode) direction = input
- *                   (sleep mode) value = low
+ *                   direction = input
+ *                   value = low
+ *                   SLPM direction = same as normal
+ *                   SLPM pull = same as normal
+ *                   SLPM value = same as normal
  *
  * PIN_CFG         - default config with alternate function
  * PIN_CFG_PULL    - default config with alternate function and pull up/down
@@ -75,30 +81,64 @@ typedef unsigned long pin_cfg_t;
 #define PIN_VAL_LOW             (0 << PIN_VAL_SHIFT)
 #define PIN_VAL_HIGH            (1 << PIN_VAL_SHIFT)
 
-/* Shortcuts.  Use these instead of separate DIR and VAL.  */
-#define PIN_INPUT               PIN_DIR_INPUT
+#define PIN_SLPM_PULL_SHIFT     16
+#define PIN_SLPM_PULL_MASK      (0x7 << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL(x)        \
+        (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_NONE      \
+        ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_UP        \
+        ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_DOWN      \
+        ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
+
+#define PIN_SLPM_DIR_SHIFT      19
+#define PIN_SLPM_DIR_MASK       (0x3 << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR(x)         \
+        (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_INPUT      ((1 + 0) << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_OUTPUT     ((1 + 1) << PIN_SLPM_DIR_SHIFT)
+
+#define PIN_SLPM_VAL_SHIFT      21
+#define PIN_SLPM_VAL_MASK       (0x3 << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL(x)         \
+        (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_LOW        ((1 + 0) << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_HIGH       ((1 + 1) << PIN_SLPM_VAL_SHIFT)
+
+/* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
+#define PIN_INPUT_PULLDOWN      (PIN_DIR_INPUT | PIN_PULL_DOWN)
+#define PIN_INPUT_PULLUP        (PIN_DIR_INPUT | PIN_PULL_UP)
+#define PIN_INPUT_NOPULL        (PIN_DIR_INPUT | PIN_PULL_NONE)
 #define PIN_OUTPUT_LOW          (PIN_DIR_OUTPUT | PIN_VAL_LOW)
 #define PIN_OUTPUT_HIGH         (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
 
-/*
- * These are the same as the ones above, but should make more sense to the
- * reader when seen along with a setting a pin to AF mode.
- */
-#define PIN_SLPM_INPUT          PIN_INPUT
-#define PIN_SLPM_OUTPUT_LOW     PIN_OUTPUT_LOW
-#define PIN_SLPM_OUTPUT_HIGH    PIN_OUTPUT_HIGH
+#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
+#define PIN_SLPM_INPUT_PULLUP   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
+#define PIN_SLPM_INPUT_NOPULL   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
+#define PIN_SLPM_OUTPUT_LOW     (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
+#define PIN_SLPM_OUTPUT_HIGH    (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
 
-#define PIN_CFG_DEFAULT         (PIN_PULL_NONE | PIN_SLPM_INPUT)
+#define PIN_CFG_DEFAULT         (0)
 
 #define PIN_CFG(num, alt)               \
         (PIN_CFG_DEFAULT |\
          (PIN_NUM(num) | PIN_##alt))
 
+#define PIN_CFG_INPUT(num, alt, pull)           \
+        (PIN_CFG_DEFAULT |\
+         (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
+
+#define PIN_CFG_OUTPUT(num, alt, val)           \
+        (PIN_CFG_DEFAULT |\
+         (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
+
 #define PIN_CFG_PULL(num, alt, pull)    \
         ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
          (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
 
-extern int nmk_config_pin(pin_cfg_t cfg);
+extern int nmk_config_pin(pin_cfg_t cfg, bool sleep);
 extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
+extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num);
 
 #endif
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index 63cdc6025bd7..41723402006b 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -17,9 +17,9 @@
 #include <linux/clk.h>
 #include <linux/jiffies.h>
 #include <linux/err.h>
-#include <linux/cnt32_to_63.h>
-#include <linux/timer.h>
+#include <linux/sched.h>
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 
 #include <plat/mtu.h>
 
@@ -52,81 +52,24 @@ static struct clocksource nmdk_clksrc = {
  * Override the global weak sched_clock symbol with this
  * local implementation which uses the clocksource to get some
  * better resolution when scheduling the kernel.
- *
- * Because the hardware timer period may be quite short
- * (32.3 secs on the 133 MHz MTU timer selection on ux500)
- * and because cnt32_to_63() needs to be called at least once per
- * half period to work properly, a kernel keepwarm() timer is set up
- * to ensure this requirement is always met.
- *
- * Also the sched_clock timer will wrap around at some point,
- * here we set it to run continously for a year.
  */
-#define SCHED_CLOCK_MIN_WRAP 3600*24*365
-static struct timer_list cnt32_to_63_keepwarm_timer;
-static u32 sched_mult;
-static u32 sched_shift;
+static DEFINE_CLOCK_DATA(cd);
 
 unsigned long long notrace sched_clock(void)
 {
-        u64 cycles;
+        u32 cyc;
 
         if (unlikely(!mtu_base))
                 return 0;
 
-        cycles = cnt32_to_63(-readl(mtu_base + MTU_VAL(0)));
-        /*
-         * sched_mult is guaranteed to be even so will
-         * shift out bit 63
-         */
-        return (cycles * sched_mult) >> sched_shift;
+        cyc = -readl(mtu_base + MTU_VAL(0));
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 }
 
-/* Just kick sched_clock every so often */
-static void cnt32_to_63_keepwarm(unsigned long data)
+static void notrace nomadik_update_sched_clock(void)
 {
-        mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
-        (void) sched_clock();
-}
-
-/*
- * Set up a timer to keep sched_clock():s 32_to_63 algorithm warm
- * once in half a 32bit timer wrap interval.
- */
-static void __init nmdk_sched_clock_init(unsigned long rate)
-{
-        u32 v;
-        unsigned long delta;
-        u64 days;
-
-        /* Find the apropriate mult and shift factors */
-        clocks_calc_mult_shift(&sched_mult, &sched_shift,
-                               rate, NSEC_PER_SEC, SCHED_CLOCK_MIN_WRAP);
-        /* We need to multiply by an even number to get rid of bit 63 */
-        if (sched_mult & 1)
-                sched_mult++;
-
-        /* Let's see what we get, take max counter and scale it */
-        days = (0xFFFFFFFFFFFFFFFFLLU * sched_mult) >> sched_shift;
-        do_div(days, NSEC_PER_SEC);
-        do_div(days, (3600*24));
-
-        pr_info("sched_clock: using %d bits @ %lu Hz wrap in %lu days\n",
-                (64 - sched_shift), rate, (unsigned long) days);
-
-        /*
-         * Program a timer to kick us at half 32bit wraparound
-         * Formula: seconds per wrap = (2^32) / f
-         */
-        v = 0xFFFFFFFFUL / rate;
-        /* We want half of the wrap time to keep cnt32_to_63 warm */
-        v /= 2;
-        pr_debug("sched_clock: prescaled timer rate: %lu Hz, "
-                 "initialize keepwarm timer every %d seconds\n", rate, v);
-        /* Convert seconds to jiffies */
-        delta = msecs_to_jiffies(v*1000);
-        setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, delta);
-        mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + delta));
+        u32 cyc = -readl(mtu_base + MTU_VAL(0));
+        update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 /* Clockevent device: use one-shot mode */
@@ -222,7 +165,6 @@ void __init nmdk_timer_init(void)
         } else {
                 cr |= MTU_CRn_PRESCALE_1;
         }
-        clocksource_calc_mult_shift(&nmdk_clksrc, rate, MTU_MIN_RANGE);
 
         /* Timer 0 is the free running clocksource */
         writel(cr, mtu_base + MTU_CR(0));
@@ -233,11 +175,11 @@ void __init nmdk_timer_init(void)
         /* Now the clock source is ready */
         nmdk_clksrc.read = nmdk_read_timer;
 
-        if (clocksource_register(&nmdk_clksrc))
+        if (clocksource_register_hz(&nmdk_clksrc, rate))
                 pr_err("timer: failed to initialize clock source %s\n",
                        nmdk_clksrc.name);
 
-        nmdk_sched_clock_init(rate);
+        init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);
 
         /* Timer 1 is used for events */
 
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 92c5bb7909f5..18fe3cb195dc 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -11,13 +11,14 @@ choice
 
 config ARCH_OMAP1
         bool "TI OMAP1"
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
         help
           "Systems based on omap7xx, omap15xx or omap16xx"
 
 config ARCH_OMAP2PLUS
         bool "TI OMAP2/3/4"
-        select COMMON_CLKDEV
+        select CLKDEV_LOOKUP
+        select OMAP_DM_TIMER
         help
           "Systems based on OMAP2, OMAP3 or OMAP4"
 
@@ -35,6 +36,37 @@ config OMAP_DEBUG_LEDS
         depends on OMAP_DEBUG_DEVICES
         default y if LEDS_CLASS
 
+config OMAP_SMARTREFLEX
+        bool "SmartReflex support"
+        depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
+        help
+          Say Y if you want to enable SmartReflex.
+
+          SmartReflex can perform continuous dynamic voltage
+          scaling around the nominal operating point voltage
+          according to silicon characteristics and operating
+          conditions. Enabling SmartReflex reduces power
+          consumption.
+
+          Please note, that by default SmartReflex is only
+          initialized. To enable the automatic voltage
+          compensation for vdd mpu  and vdd core from user space,
+          user must write 1 to
+                /debug/voltage/vdd_<X>/smartreflex/autocomp,
+          where X is mpu or core for OMAP3.
+          Optionallly autocompensation can be enabled in the kernel
+          by default during system init via the enable_on_init flag
+          which an be passed as platform data to the smartreflex driver.
+
+config OMAP_SMARTREFLEX_CLASS3
+        bool "Class 3 mode of Smartreflex Implementation"
+        depends on OMAP_SMARTREFLEX && TWL4030_CORE
+        help
+          Say Y to enable Class 3 implementation of Smartreflex
+
+          Class 3 implementation of Smartreflex employs continuous hardware
+          voltage calibration.
+
 config OMAP_RESET_CLOCKS
         bool "Reset unused clocks during boot"
         depends on ARCH_OMAP
@@ -109,6 +141,9 @@ config OMAP_IOMMU_DEBUG
 
          Say N unless you know you need this.
 
+config OMAP_IOMMU_IVA2
+        bool
+
 choice
         prompt "System timer"
         default OMAP_32K_TIMER if !ARCH_OMAP15XX
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 8722a136f3a5..ea4644021fb9 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -15,8 +15,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/clk.h>
-#include <linux/io.h>
 #include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sched.h>
+
+#include <asm/sched_clock.h>
 
 #include <plat/common.h>
 #include <plat/board.h>
@@ -45,7 +48,7 @@
 static u32 offset_32k __read_mostly;
 
 #ifdef CONFIG_ARCH_OMAP16XX
-static cycle_t omap16xx_32k_read(struct clocksource *cs)
+static cycle_t notrace omap16xx_32k_read(struct clocksource *cs)
 {
         return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
 }
@@ -54,7 +57,7 @@ static cycle_t omap16xx_32k_read(struct clocksource *cs)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP2420
-static cycle_t omap2420_32k_read(struct clocksource *cs)
+static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
 {
         return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
 }
@@ -63,7 +66,7 @@ static cycle_t omap2420_32k_read(struct clocksource *cs)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP2430
-static cycle_t omap2430_32k_read(struct clocksource *cs)
+static cycle_t notrace omap2430_32k_read(struct clocksource *cs)
 {
         return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
 }
@@ -72,7 +75,7 @@ static cycle_t omap2430_32k_read(struct clocksource *cs)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP3
-static cycle_t omap34xx_32k_read(struct clocksource *cs)
+static cycle_t notrace omap34xx_32k_read(struct clocksource *cs)
 {
         return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
 }
@@ -81,7 +84,7 @@ static cycle_t omap34xx_32k_read(struct clocksource *cs)
 #endif
 
 #ifdef CONFIG_ARCH_OMAP4
-static cycle_t omap44xx_32k_read(struct clocksource *cs)
+static cycle_t notrace omap44xx_32k_read(struct clocksource *cs)
 {
         return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
 }
@@ -93,7 +96,7 @@ static cycle_t omap44xx_32k_read(struct clocksource *cs)
  * Kernel assumes that sched_clock can be called early but may not have
  * things ready yet.
  */
-static cycle_t omap_32k_read_dummy(struct clocksource *cs)
+static cycle_t notrace omap_32k_read_dummy(struct clocksource *cs)
 {
         return 0;
 }
@@ -103,7 +106,6 @@ static struct clocksource clocksource_32k = {
         .rating         = 250,
         .read           = omap_32k_read_dummy,
         .mask           = CLOCKSOURCE_MASK(32),
-        .shift          = 10,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -111,10 +113,25 @@ static struct clocksource clocksource_32k = {
  * Returns current time from boot in nsecs. It's OK for this to wrap
  * around for now, as it's just a relative time stamp.
  */
-unsigned long long sched_clock(void)
+static DEFINE_CLOCK_DATA(cd);
+
+/*
+ * Constants generated by clocks_calc_mult_shift(m, s, 32768, NSEC_PER_SEC, 60).
+ * This gives a resolution of about 30us and a wrap period of about 36hrs.
+ */
+#define SC_MULT         4000000000u
+#define SC_SHIFT        17
+
+unsigned long long notrace sched_clock(void)
+{
+        u32 cyc = clocksource_32k.read(&clocksource_32k);
+        return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
+}
+
+static void notrace omap_update_sched_clock(void)
 {
-        return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
-                                  clocksource_32k.mult, clocksource_32k.shift);
+        u32 cyc = clocksource_32k.read(&clocksource_32k);
+        update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 /**
@@ -168,13 +185,13 @@ static int __init omap_init_clocksource_32k(void)
                 if (!IS_ERR(sync_32k_ick))
                         clk_enable(sync_32k_ick);
 
-                clocksource_32k.mult = clocksource_hz2mult(32768,
-                                            clocksource_32k.shift);
-
                 offset_32k = clocksource_32k.read(&clocksource_32k);
 
-                if (clocksource_register(&clocksource_32k))
+                if (clocksource_register_hz(&clocksource_32k, 32768))
                         printk(err, clocksource_32k.name);
+
+                init_fixed_sched_clock(&cd, omap_update_sched_clock, 32,
+                                       32768, SC_MULT, SC_SHIFT);
         }
         return 0;
 }
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index fc819120978d..10245b837c10 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -232,46 +232,6 @@ static void omap_init_uwire(void)
 static inline void omap_init_uwire(void) {}
 #endif
 
-/*-------------------------------------------------------------------------*/
-
-#if     defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
-
-static struct resource wdt_resources[] = {
-        {
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap_wdt_device = {
-        .name      = "omap_wdt",
-        .id          = -1,
-        .num_resources  = ARRAY_SIZE(wdt_resources),
-        .resource       = wdt_resources,
-};
-
-static void omap_init_wdt(void)
-{
-        if (cpu_is_omap16xx())
-                wdt_resources[0].start = 0xfffeb000;
-        else if (cpu_is_omap2420())
-                wdt_resources[0].start = 0x48022000; /* WDT2 */
-        else if (cpu_is_omap2430())
-                wdt_resources[0].start = 0x49016000; /* WDT2 */
-        else if (cpu_is_omap343x())
-                wdt_resources[0].start = 0x48314000; /* WDT2 */
-        else if (cpu_is_omap44xx())
-                wdt_resources[0].start = 0x4a314000;
-        else
-                return;
-
-        wdt_resources[0].end = wdt_resources[0].start + 0x4f;
-
-        (void) platform_device_register(&omap_wdt_device);
-}
-#else
-static inline void omap_init_wdt(void) {}
-#endif
-
 #if defined(CONFIG_TIDSPBRIDGE) || defined(CONFIG_TIDSPBRIDGE_MODULE)
 
 static phys_addr_t omap_dsp_phys_mempool_base;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 2c2826571d45..c4b2b478b1a5 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -15,6 +15,10 @@
  *
  * Support functions for the OMAP internal DMA channels.
  *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Converted DMA library into DMA platform driver.
+ *      - G, Manjunath Kondaiah <manjugk@ti.com>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
@@ -53,7 +57,11 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
 
 #define OMAP_FUNC_MUX_ARM_BASE          (0xfffe1000 + 0xec)
 
+static struct omap_system_dma_plat_info *p;
+static struct omap_dma_dev_attr *d;
+
 static int enable_1510_mode;
+static u32 errata;
 
 static struct omap_dma_global_context_registers {
         u32 dma_irqenable_l0;
@@ -61,27 +69,6 @@ static struct omap_dma_global_context_registers {
         u32 dma_gcr;
 } omap_dma_global_context;
 
-struct omap_dma_lch {
-        int next_lch;
-        int dev_id;
-        u16 saved_csr;
-        u16 enabled_irqs;
-        const char *dev_name;
-        void (*callback)(int lch, u16 ch_status, void *data);
-        void *data;
-
-#ifndef CONFIG_ARCH_OMAP1
-        /* required for Dynamic chaining */
-        int prev_linked_ch;
-        int next_linked_ch;
-        int state;
-        int chain_id;
-
-        int status;
-#endif
-        long flags;
-};
-
 struct dma_link_info {
         int *linked_dmach_q;
         int no_of_lchs_linked;
@@ -137,15 +124,6 @@ static int omap_dma_reserve_channels;
 
 static spinlock_t dma_chan_lock;
 static struct omap_dma_lch *dma_chan;
-static void __iomem *omap_dma_base;
-
-static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
-        INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
-        INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
-        INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
-        INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
-        INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
-};
 
 static inline void disable_lnk(int lch);
 static void omap_disable_channel_irq(int lch);
@@ -154,24 +132,6 @@ static inline void omap_enable_channel_irq(int lch);
 #define REVISIT_24XX()          printk(KERN_ERR "FIXME: no %s on 24xx\n", \
                                                 __func__);
 
-#define dma_read(reg)                                                   \
-({                                                                      \
-        u32 __val;                                                      \
-        if (cpu_class_is_omap1())                                       \
-                __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg);   \
-        else                                                            \
-                __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg);   \
-        __val;                                                          \
-})
-
-#define dma_write(val, reg)                                             \
-({                                                                      \
-        if (cpu_class_is_omap1())                                       \
-                __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
-        else                                                            \
-                __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg);   \
-})
-
 #ifdef CONFIG_ARCH_OMAP15XX
 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
 int omap_dma_in_1510_mode(void)
@@ -206,16 +166,6 @@ static inline void set_gdma_dev(int req, int dev)
 #define set_gdma_dev(req, dev)  do {} while (0)
 #endif
 
-/* Omap1 only */
-static void clear_lch_regs(int lch)
-{
-        int i;
-        void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
-
-        for (i = 0; i < 0x2c; i += 2)
-                __raw_writew(0, lch_base + i);
-}
-
 void omap_set_dma_priority(int lch, int dst_port, int priority)
 {
         unsigned long reg;
@@ -248,12 +198,12 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
         if (cpu_class_is_omap2()) {
                 u32 ccr;
 
-                ccr = dma_read(CCR(lch));
+                ccr = p->dma_read(CCR, lch);
                 if (priority)
                         ccr |= (1 << 6);
                 else
                         ccr &= ~(1 << 6);
-                dma_write(ccr, CCR(lch));
+                p->dma_write(ccr, CCR, lch);
         }
 }
 EXPORT_SYMBOL(omap_set_dma_priority);
@@ -264,31 +214,31 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
 {
         u32 l;
 
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
         l &= ~0x03;
         l |= data_type;
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 
         if (cpu_class_is_omap1()) {
                 u16 ccr;
 
-                ccr = dma_read(CCR(lch));
+                ccr = p->dma_read(CCR, lch);
                 ccr &= ~(1 << 5);
                 if (sync_mode == OMAP_DMA_SYNC_FRAME)
                         ccr |= 1 << 5;
-                dma_write(ccr, CCR(lch));
+                p->dma_write(ccr, CCR, lch);
 
-                ccr = dma_read(CCR2(lch));
+                ccr = p->dma_read(CCR2, lch);
                 ccr &= ~(1 << 2);
                 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
                         ccr |= 1 << 2;
-                dma_write(ccr, CCR2(lch));
+                p->dma_write(ccr, CCR2, lch);
         }
 
         if (cpu_class_is_omap2() && dma_trigger) {
                 u32 val;
 
-                val = dma_read(CCR(lch));
+                val = p->dma_read(CCR, lch);
 
                 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
                 val &= ~((1 << 23) | (3 << 19) | 0x1f);
@@ -313,11 +263,11 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                 } else {
                         val &= ~(1 << 24);      /* dest synch */
                 }
-                dma_write(val, CCR(lch));
+                p->dma_write(val, CCR, lch);
         }
 
-        dma_write(elem_count, CEN(lch));
-        dma_write(frame_count, CFN(lch));
+        p->dma_write(elem_count, CEN, lch);
+        p->dma_write(frame_count, CFN, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_transfer_params);
 
@@ -328,7 +278,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
         if (cpu_class_is_omap1()) {
                 u16 w;
 
-                w = dma_read(CCR2(lch));
+                w = p->dma_read(CCR2, lch);
                 w &= ~0x03;
 
                 switch (mode) {
@@ -343,23 +293,22 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
                 default:
                         BUG();
                 }
-                dma_write(w, CCR2(lch));
+                p->dma_write(w, CCR2, lch);
 
-                w = dma_read(LCH_CTRL(lch));
+                w = p->dma_read(LCH_CTRL, lch);
                 w &= ~0x0f;
                 /* Default is channel type 2D */
                 if (mode) {
-                        dma_write((u16)color, COLOR_L(lch));
-                        dma_write((u16)(color >> 16), COLOR_U(lch));
+                        p->dma_write(color, COLOR, lch);
                         w |= 1;         /* Channel type G */
                 }
-                dma_write(w, LCH_CTRL(lch));
+                p->dma_write(w, LCH_CTRL, lch);
         }
 
         if (cpu_class_is_omap2()) {
                 u32 val;
 
-                val = dma_read(CCR(lch));
+                val = p->dma_read(CCR, lch);
                 val &= ~((1 << 17) | (1 << 16));
 
                 switch (mode) {
@@ -374,10 +323,10 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
                 default:
                         BUG();
                 }
-                dma_write(val, CCR(lch));
+                p->dma_write(val, CCR, lch);
 
                 color &= 0xffffff;
-                dma_write(color, COLOR(lch));
+                p->dma_write(color, COLOR, lch);
         }
 }
 EXPORT_SYMBOL(omap_set_dma_color_mode);
@@ -387,10 +336,10 @@ void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
         if (cpu_class_is_omap2()) {
                 u32 csdp;
 
-                csdp = dma_read(CSDP(lch));
+                csdp = p->dma_read(CSDP, lch);
                 csdp &= ~(0x3 << 16);
                 csdp |= (mode << 16);
-                dma_write(csdp, CSDP(lch));
+                p->dma_write(csdp, CSDP, lch);
         }
 }
 EXPORT_SYMBOL(omap_set_dma_write_mode);
@@ -400,10 +349,10 @@ void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
         if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
                 u32 l;
 
-                l = dma_read(LCH_CTRL(lch));
+                l = p->dma_read(LCH_CTRL, lch);
                 l &= ~0x7;
                 l |= mode;
-                dma_write(l, LCH_CTRL(lch));
+                p->dma_write(l, LCH_CTRL, lch);
         }
 }
 EXPORT_SYMBOL(omap_set_dma_channel_mode);
@@ -418,27 +367,21 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
         if (cpu_class_is_omap1()) {
                 u16 w;
 
-                w = dma_read(CSDP(lch));
+                w = p->dma_read(CSDP, lch);
                 w &= ~(0x1f << 2);
                 w |= src_port << 2;
-                dma_write(w, CSDP(lch));
+                p->dma_write(w, CSDP, lch);
         }
 
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
         l &= ~(0x03 << 12);
         l |= src_amode << 12;
-        dma_write(l, CCR(lch));
-
-        if (cpu_class_is_omap1()) {
-                dma_write(src_start >> 16, CSSA_U(lch));
-                dma_write((u16)src_start, CSSA_L(lch));
-        }
+        p->dma_write(l, CCR, lch);
 
-        if (cpu_class_is_omap2())
-                dma_write(src_start, CSSA(lch));
+        p->dma_write(src_start, CSSA, lch);
 
-        dma_write(src_ei, CSEI(lch));
-        dma_write(src_fi, CSFI(lch));
+        p->dma_write(src_ei, CSEI, lch);
+        p->dma_write(src_fi, CSFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_params);
 
@@ -466,8 +409,8 @@ void omap_set_dma_src_index(int lch, int eidx, int fidx)
         if (cpu_class_is_omap2())
                 return;
 
-        dma_write(eidx, CSEI(lch));
-        dma_write(fidx, CSFI(lch));
+        p->dma_write(eidx, CSEI, lch);
+        p->dma_write(fidx, CSFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_index);
 
@@ -475,11 +418,11 @@ void omap_set_dma_src_data_pack(int lch, int enable)
 {
         u32 l;
 
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
         l &= ~(1 << 6);
         if (enable)
                 l |= (1 << 6);
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
 
@@ -488,7 +431,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
         unsigned int burst = 0;
         u32 l;
 
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
         l &= ~(0x03 << 7);
 
         switch (burst_mode) {
@@ -524,7 +467,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
         }
 
         l |= (burst << 7);
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
 
@@ -536,27 +479,21 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
         u32 l;
 
         if (cpu_class_is_omap1()) {
-                l = dma_read(CSDP(lch));
+                l = p->dma_read(CSDP, lch);
                 l &= ~(0x1f << 9);
                 l |= dest_port << 9;
-                dma_write(l, CSDP(lch));
+                p->dma_write(l, CSDP, lch);
         }
 
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
         l &= ~(0x03 << 14);
         l |= dest_amode << 14;
-        dma_write(l, CCR(lch));
-
-        if (cpu_class_is_omap1()) {
-                dma_write(dest_start >> 16, CDSA_U(lch));
-                dma_write(dest_start, CDSA_L(lch));
-        }
+        p->dma_write(l, CCR, lch);
 
-        if (cpu_class_is_omap2())
-                dma_write(dest_start, CDSA(lch));
+        p->dma_write(dest_start, CDSA, lch);
 
-        dma_write(dst_ei, CDEI(lch));
-        dma_write(dst_fi, CDFI(lch));
+        p->dma_write(dst_ei, CDEI, lch);
+        p->dma_write(dst_fi, CDFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_params);
 
@@ -565,8 +502,8 @@ void omap_set_dma_dest_index(int lch, int eidx, int fidx)
         if (cpu_class_is_omap2())
                 return;
 
-        dma_write(eidx, CDEI(lch));
-        dma_write(fidx, CDFI(lch));
+        p->dma_write(eidx, CDEI, lch);
+        p->dma_write(fidx, CDFI, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_index);
 
@@ -574,11 +511,11 @@ void omap_set_dma_dest_data_pack(int lch, int enable)
 {
         u32 l;
 
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
         l &= ~(1 << 13);
         if (enable)
                 l |= 1 << 13;
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
 
@@ -587,7 +524,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
         unsigned int burst = 0;
         u32 l;
 
-        l = dma_read(CSDP(lch));
+        l = p->dma_read(CSDP, lch);
         l &= ~(0x03 << 14);
 
         switch (burst_mode) {
@@ -620,7 +557,7 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
                 return;
         }
         l |= (burst << 14);
-        dma_write(l, CSDP(lch));
+        p->dma_write(l, CSDP, lch);
 }
 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 
@@ -630,18 +567,18 @@ static inline void omap_enable_channel_irq(int lch)
 
         /* Clear CSR */
         if (cpu_class_is_omap1())
-                status = dma_read(CSR(lch));
+                status = p->dma_read(CSR, lch);
         else if (cpu_class_is_omap2())
-                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 
         /* Enable some nice interrupts. */
-        dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
+        p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 }
 
 static void omap_disable_channel_irq(int lch)
 {
         if (cpu_class_is_omap2())
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
 }
 
 void omap_enable_dma_irq(int lch, u16 bits)
@@ -660,7 +597,7 @@ static inline void enable_lnk(int lch)
 {
         u32 l;
 
-        l = dma_read(CLNK_CTRL(lch));
+        l = p->dma_read(CLNK_CTRL, lch);
 
         if (cpu_class_is_omap1())
                 l &= ~(1 << 14);
@@ -675,18 +612,18 @@ static inline void enable_lnk(int lch)
                         l = dma_chan[lch].next_linked_ch | (1 << 15);
 #endif
 
-        dma_write(l, CLNK_CTRL(lch));
+        p->dma_write(l, CLNK_CTRL, lch);
 }
 
 static inline void disable_lnk(int lch)
 {
         u32 l;
 
-        l = dma_read(CLNK_CTRL(lch));
+        l = p->dma_read(CLNK_CTRL, lch);
 
         /* Disable interrupts */
         if (cpu_class_is_omap1()) {
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
                 /* Set the STOP_LNK bit */
                 l |= 1 << 14;
         }
@@ -697,7 +634,7 @@ static inline void disable_lnk(int lch)
                 l &= ~(1 << 15);
         }
 
-        dma_write(l, CLNK_CTRL(lch));
+        p->dma_write(l, CLNK_CTRL, lch);
         dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
 }
 
@@ -710,9 +647,9 @@ static inline void omap2_enable_irq_lch(int lch)
                 return;
 
         spin_lock_irqsave(&dma_chan_lock, flags);
-        val = dma_read(IRQENABLE_L0);
+        val = p->dma_read(IRQENABLE_L0, lch);
         val |= 1 << lch;
-        dma_write(val, IRQENABLE_L0);
+        p->dma_write(val, IRQENABLE_L0, lch);
         spin_unlock_irqrestore(&dma_chan_lock, flags);
 }
 
@@ -725,9 +662,9 @@ static inline void omap2_disable_irq_lch(int lch)
                 return;
 
         spin_lock_irqsave(&dma_chan_lock, flags);
-        val = dma_read(IRQENABLE_L0);
+        val = p->dma_read(IRQENABLE_L0, lch);
         val &= ~(1 << lch);
-        dma_write(val, IRQENABLE_L0);
+        p->dma_write(val, IRQENABLE_L0, lch);
         spin_unlock_irqrestore(&dma_chan_lock, flags);
 }
 
@@ -754,8 +691,8 @@ int omap_request_dma(int dev_id, const char *dev_name,
         chan = dma_chan + free_ch;
         chan->dev_id = dev_id;
 
-        if (cpu_class_is_omap1())
-                clear_lch_regs(free_ch);
+        if (p->clear_lch_regs)
+                p->clear_lch_regs(free_ch);
 
         if (cpu_class_is_omap2())
                 omap_clear_dma(free_ch);
@@ -792,17 +729,17 @@ int omap_request_dma(int dev_id, const char *dev_name,
                  * Disable the 1510 compatibility mode and set the sync device
                  * id.
                  */
-                dma_write(dev_id | (1 << 10), CCR(free_ch));
+                p->dma_write(dev_id | (1 << 10), CCR, free_ch);
         } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
-                dma_write(dev_id, CCR(free_ch));
+                p->dma_write(dev_id, CCR, free_ch);
         }
 
         if (cpu_class_is_omap2()) {
                 omap2_enable_irq_lch(free_ch);
                 omap_enable_channel_irq(free_ch);
                 /* Clear the CSR register and IRQ status register */
-                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
-                dma_write(1 << free_ch, IRQSTATUS_L0);
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
+                p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
         }
 
         *dma_ch_out = free_ch;
@@ -823,23 +760,23 @@ void omap_free_dma(int lch)
 
         if (cpu_class_is_omap1()) {
                 /* Disable all DMA interrupts for the channel. */
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
                 /* Make sure the DMA transfer is stopped. */
-                dma_write(0, CCR(lch));
+                p->dma_write(0, CCR, lch);
         }
 
         if (cpu_class_is_omap2()) {
                 omap2_disable_irq_lch(lch);
 
                 /* Clear the CSR register and IRQ status register */
-                dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
-                dma_write(1 << lch, IRQSTATUS_L0);
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
+                p->dma_write(1 << lch, IRQSTATUS_L0, lch);
 
                 /* Disable all DMA interrupts for the channel. */
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
 
                 /* Make sure the DMA transfer is stopped. */
-                dma_write(0, CCR(lch));
+                p->dma_write(0, CCR, lch);
                 omap_clear_dma(lch);
         }
 
@@ -880,7 +817,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
         reg |= (0x3 & tparams) << 12;
         reg |= (arb_rate & 0xff) << 16;
 
-        dma_write(reg, GCR);
+        p->dma_write(reg, GCR, 0);
 }
 EXPORT_SYMBOL(omap_dma_set_global_params);
 
@@ -903,14 +840,14 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
                 printk(KERN_ERR "Invalid channel id\n");
                 return -EINVAL;
         }
-        l = dma_read(CCR(lch));
+        l = p->dma_read(CCR, lch);
         l &= ~((1 << 6) | (1 << 26));
         if (cpu_is_omap2430() || cpu_is_omap34xx() ||  cpu_is_omap44xx())
                 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
         else
                 l |= ((read_prio & 0x1) << 6);
 
-        dma_write(l, CCR(lch));
+        p->dma_write(l, CCR, lch);
 
         return 0;
 }
@@ -925,25 +862,7 @@ void omap_clear_dma(int lch)
         unsigned long flags;
 
         local_irq_save(flags);
-
-        if (cpu_class_is_omap1()) {
-                u32 l;
-
-                l = dma_read(CCR(lch));
-                l &= ~OMAP_DMA_CCR_EN;
-                dma_write(l, CCR(lch));
-
-                /* Clear pending interrupts */
-                l = dma_read(CSR(lch));
-        }
-
-        if (cpu_class_is_omap2()) {
-                int i;
-                void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
-                for (i = 0; i < 0x44; i += 4)
-                        __raw_writel(0, lch_base + i);
-        }
-
+        p->clear_dma(lch);
         local_irq_restore(flags);
 }
 EXPORT_SYMBOL(omap_clear_dma);
@@ -957,13 +876,13 @@ void omap_start_dma(int lch)
          * before starting dma transfer.
          */
         if (cpu_is_omap15xx())
-                dma_write(0, CPC(lch));
+                p->dma_write(0, CPC, lch);
         else
-                dma_write(0, CDAC(lch));
+                p->dma_write(0, CDAC, lch);
 
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch;
-                char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
+                char dma_chan_link_map[dma_lch_count];
 
                 dma_chan_link_map[lch] = 1;
                 /* Set the link register of the first channel */
@@ -985,32 +904,18 @@ void omap_start_dma(int lch)
 
                         cur_lch = next_lch;
                 } while (next_lch != -1);
-        } else if (cpu_is_omap242x() ||
-                (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
-
-                /* Errata: Need to write lch even if not using chaining */
-                dma_write(lch, CLNK_CTRL(lch));
-        }
+        } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
+                p->dma_write(lch, CLNK_CTRL, lch);
 
         omap_enable_channel_irq(lch);
 
-        l = dma_read(CCR(lch));
-
-        /*
-         * Errata: Inter Frame DMA buffering issue (All OMAP2420 and
-         * OMAP2430ES1.0): DMA will wrongly buffer elements if packing and
-         * bursting is enabled. This might result in data gets stalled in
-         * FIFO at the end of the block.
-         * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
-         * guarantee no data will stay in the DMA FIFO in case inter frame
-         * buffering occurs.
-         */
-        if (cpu_is_omap2420() ||
-            (cpu_is_omap2430() && (omap_type() == OMAP2430_REV_ES1_0)))
-                l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
+        l = p->dma_read(CCR, lch);
 
+        if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
+                        l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
         l |= OMAP_DMA_CCR_EN;
-        dma_write(l, CCR(lch));
+
+        p->dma_write(l, CCR, lch);
 
         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
 }
@@ -1022,46 +927,46 @@ void omap_stop_dma(int lch)
 
         /* Disable all interrupts on the channel */
         if (cpu_class_is_omap1())
-                dma_write(0, CICR(lch));
+                p->dma_write(0, CICR, lch);
 
-        l = dma_read(CCR(lch));
-        /* OMAP3 Errata i541: sDMA FIFO draining does not finish */
-        if (cpu_is_omap34xx() && (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
+        l = p->dma_read(CCR, lch);
+        if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
+                        (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
                 int i = 0;
                 u32 sys_cf;
 
                 /* Configure No-Standby */
-                l = dma_read(OCP_SYSCONFIG);
+                l = p->dma_read(OCP_SYSCONFIG, lch);
                 sys_cf = l;
                 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
                 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
-                dma_write(l , OCP_SYSCONFIG);
+                p->dma_write(l , OCP_SYSCONFIG, 0);
 
-                l = dma_read(CCR(lch));
+                l = p->dma_read(CCR, lch);
                 l &= ~OMAP_DMA_CCR_EN;
-                dma_write(l, CCR(lch));
+                p->dma_write(l, CCR, lch);
 
                 /* Wait for sDMA FIFO drain */
-                l = dma_read(CCR(lch));
+                l = p->dma_read(CCR, lch);
                 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
                                         OMAP_DMA_CCR_WR_ACTIVE))) {
                         udelay(5);
                         i++;
-                        l = dma_read(CCR(lch));
+                        l = p->dma_read(CCR, lch);
                 }
                 if (i >= 100)
                         printk(KERN_ERR "DMA drain did not complete on "
                                         "lch %d\n", lch);
                 /* Restore OCP_SYSCONFIG */
-                dma_write(sys_cf, OCP_SYSCONFIG);
+                p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
         } else {
                 l &= ~OMAP_DMA_CCR_EN;
-                dma_write(l, CCR(lch));
+                p->dma_write(l, CCR, lch);
         }
 
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch = lch;
-                char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
+                char dma_chan_link_map[dma_lch_count];
 
                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
                 do {
@@ -1122,19 +1027,15 @@ dma_addr_t omap_get_dma_src_pos(int lch)
         dma_addr_t offset = 0;
 
         if (cpu_is_omap15xx())
-                offset = dma_read(CPC(lch));
+                offset = p->dma_read(CPC, lch);
         else
-                offset = dma_read(CSAC(lch));
+                offset = p->dma_read(CSAC, lch);
 
-        /*
-         * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
-         * read before the DMA controller finished disabling the channel.
-         */
-        if (!cpu_is_omap15xx() && offset == 0)
-                offset = dma_read(CSAC(lch));
+        if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
+                offset = p->dma_read(CSAC, lch);
 
         if (cpu_class_is_omap1())
-                offset |= (dma_read(CSSA_U(lch)) << 16);
+                offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
 
         return offset;
 }
@@ -1153,19 +1054,19 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
         dma_addr_t offset = 0;
 
         if (cpu_is_omap15xx())
-                offset = dma_read(CPC(lch));
+                offset = p->dma_read(CPC, lch);
         else
-                offset = dma_read(CDAC(lch));
+                offset = p->dma_read(CDAC, lch);
 
         /*
          * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
          * read before the DMA controller finished disabling the channel.
          */
         if (!cpu_is_omap15xx() && offset == 0)
-                offset = dma_read(CDAC(lch));
+                offset = p->dma_read(CDAC, lch);
 
         if (cpu_class_is_omap1())
-                offset |= (dma_read(CDSA_U(lch)) << 16);
+                offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
 
         return offset;
 }
@@ -1173,7 +1074,7 @@ EXPORT_SYMBOL(omap_get_dma_dst_pos);
 
 int omap_get_dma_active_status(int lch)
 {
-        return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
+        return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
 }
 EXPORT_SYMBOL(omap_get_dma_active_status);
 
@@ -1186,7 +1087,7 @@ int omap_dma_running(void)
                         return 1;
 
         for (lch = 0; lch < dma_chan_count; lch++)
-                if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
+                if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
                         return 1;
 
         return 0;
@@ -1201,8 +1102,8 @@ void omap_dma_link_lch(int lch_head, int lch_queue)
 {
         if (omap_dma_in_1510_mode()) {
                 if (lch_head == lch_queue) {
-                        dma_write(dma_read(CCR(lch_head)) | (3 << 8),
-                                                                CCR(lch_head));
+                        p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
+                                                                CCR, lch_head);
                         return;
                 }
                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -1228,8 +1129,8 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
 {
         if (omap_dma_in_1510_mode()) {
                 if (lch_head == lch_queue) {
-                        dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
-                                                                CCR(lch_head));
+                        p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
+                                                                CCR, lch_head);
                         return;
                 }
                 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -1255,8 +1156,6 @@ void omap_dma_unlink_lch(int lch_head, int lch_queue)
 }
 EXPORT_SYMBOL(omap_dma_unlink_lch);
 
-/*----------------------------------------------------------------------------*/
-
 #ifndef CONFIG_ARCH_OMAP1
 /* Create chain of DMA channesls */
 static void create_dma_lch_chain(int lch_head, int lch_queue)
@@ -1281,15 +1180,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
                                         lch_queue;
         }
 
-        l = dma_read(CLNK_CTRL(lch_head));
+        l = p->dma_read(CLNK_CTRL, lch_head);
         l &= ~(0x1f);
         l |= lch_queue;
-        dma_write(l, CLNK_CTRL(lch_head));
+        p->dma_write(l, CLNK_CTRL, lch_head);
 
-        l = dma_read(CLNK_CTRL(lch_queue));
+        l = p->dma_read(CLNK_CTRL, lch_queue);
         l &= ~(0x1f);
         l |= (dma_chan[lch_queue].next_linked_ch);
-        dma_write(l, CLNK_CTRL(lch_queue));
+        p->dma_write(l, CLNK_CTRL, lch_queue);
 }
 
 /**
@@ -1565,13 +1464,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
 
         /* Set the params to the free channel */
         if (src_start != 0)
-                dma_write(src_start, CSSA(lch));
+                p->dma_write(src_start, CSSA, lch);
         if (dest_start != 0)
-                dma_write(dest_start, CDSA(lch));
+                p->dma_write(dest_start, CDSA, lch);
 
         /* Write the buffer size */
-        dma_write(elem_count, CEN(lch));
-        dma_write(frame_count, CFN(lch));
+        p->dma_write(elem_count, CEN, lch);
+        p->dma_write(frame_count, CFN, lch);
 
         /*
          * If the chain is dynamically linked,
@@ -1604,8 +1503,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                                 enable_lnk(dma_chan[lch].prev_linked_ch);
                                 dma_chan[lch].state = DMA_CH_QUEUED;
                                 start_dma = 0;
-                                if (0 == ((1 << 7) & dma_read(
-                                        CCR(dma_chan[lch].prev_linked_ch)))) {
+                                if (0 == ((1 << 7) & p->dma_read(
+                                        CCR, dma_chan[lch].prev_linked_ch))) {
                                         disable_lnk(dma_chan[lch].
                                                     prev_linked_ch);
                                         pr_debug("\n prev ch is stopped\n");
@@ -1621,7 +1520,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                         }
                         omap_enable_channel_irq(lch);
 
-                        l = dma_read(CCR(lch));
+                        l = p->dma_read(CCR, lch);
 
                         if ((0 == (l & (1 << 24))))
                                 l &= ~(1 << 25);
@@ -1632,12 +1531,12 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
                                         l |= (1 << 7);
                                         dma_chan[lch].state = DMA_CH_STARTED;
                                         pr_debug("starting %d\n", lch);
-                                        dma_write(l, CCR(lch));
+                                        p->dma_write(l, CCR, lch);
                                 } else
                                         start_dma = 0;
                         } else {
                                 if (0 == (l & (1 << 7)))
-                                        dma_write(l, CCR(lch));
+                                        p->dma_write(l, CCR, lch);
                         }
                         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
                 }
@@ -1682,7 +1581,7 @@ int omap_start_dma_chain_transfers(int chain_id)
                 omap_enable_channel_irq(channels[0]);
         }
 
-        l = dma_read(CCR(channels[0]));
+        l = p->dma_read(CCR, channels[0]);
         l |= (1 << 7);
         dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
         dma_chan[channels[0]].state = DMA_CH_STARTED;
@@ -1691,7 +1590,7 @@ int omap_start_dma_chain_transfers(int chain_id)
                 l &= ~(1 << 25);
         else
                 l |= (1 << 25);
-        dma_write(l, CCR(channels[0]));
+        p->dma_write(l, CCR, channels[0]);
 
         dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
 
@@ -1711,7 +1610,7 @@ int omap_stop_dma_chain_transfers(int chain_id)
 {
         int *channels;
         u32 l, i;
-        u32 sys_cf;
+        u32 sys_cf = 0;
 
         /* Check for input params */
         if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
@@ -1726,22 +1625,20 @@ int omap_stop_dma_chain_transfers(int chain_id)
         }
         channels = dma_linked_lch[chain_id].linked_dmach_q;
 
-        /*
-         * DMA Errata:
-         * Special programming model needed to disable DMA before end of block
-         */
-        sys_cf = dma_read(OCP_SYSCONFIG);
-        l = sys_cf;
-        /* Middle mode reg set no Standby */
-        l &= ~((1 << 12)|(1 << 13));
-        dma_write(l, OCP_SYSCONFIG);
+        if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
+                sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
+                l = sys_cf;
+                /* Middle mode reg set no Standby */
+                l &= ~((1 << 12)|(1 << 13));
+                p->dma_write(l, OCP_SYSCONFIG, 0);
+        }
 
         for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
 
                 /* Stop the Channel transmission */
-                l = dma_read(CCR(channels[i]));
+                l = p->dma_read(CCR, channels[i]);
                 l &= ~(1 << 7);
-                dma_write(l, CCR(channels[i]));
+                p->dma_write(l, CCR, channels[i]);
 
                 /* Disable the link in all the channels */
                 disable_lnk(channels[i]);
@@ -1753,8 +1650,8 @@ int omap_stop_dma_chain_transfers(int chain_id)
         /* Reset the Queue pointers */
         OMAP_DMA_CHAIN_QINIT(chain_id);
 
-        /* Errata - put in the old value */
-        dma_write(sys_cf, OCP_SYSCONFIG);
+        if (IS_DMA_ERRATA(DMA_ERRATA_i88))
+                p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
 
         return 0;
 }
@@ -1796,8 +1693,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
         /* Get the current channel */
         lch = channels[dma_linked_lch[chain_id].q_head];
 
-        *ei = dma_read(CCEN(lch));
-        *fi = dma_read(CCFN(lch));
+        *ei = p->dma_read(CCEN, lch);
+        *fi = p->dma_read(CCFN, lch);
 
         return 0;
 }
@@ -1834,7 +1731,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
         /* Get the current channel */
         lch = channels[dma_linked_lch[chain_id].q_head];
 
-        return dma_read(CDAC(lch));
+        return p->dma_read(CDAC, lch);
 }
 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
 
@@ -1868,7 +1765,7 @@ int omap_get_dma_chain_src_pos(int chain_id)
         /* Get the current channel */
         lch = channels[dma_linked_lch[chain_id].q_head];
 
-        return dma_read(CSAC(lch));
+        return p->dma_read(CSAC, lch);
 }
 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
 #endif  /* ifndef CONFIG_ARCH_OMAP1 */
@@ -1885,7 +1782,7 @@ static int omap1_dma_handle_ch(int ch)
                 csr = dma_chan[ch].saved_csr;
                 dma_chan[ch].saved_csr = 0;
         } else
-                csr = dma_read(CSR(ch));
+                csr = p->dma_read(CSR, ch);
         if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
                 dma_chan[ch + 6].saved_csr = csr >> 7;
                 csr &= 0x7f;
@@ -1938,13 +1835,13 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
 
 static int omap2_dma_handle_ch(int ch)
 {
-        u32 status = dma_read(CSR(ch));
+        u32 status = p->dma_read(CSR, ch);
 
         if (!status) {
                 if (printk_ratelimit())
                         printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
                                 ch);
-                dma_write(1 << ch, IRQSTATUS_L0);
+                p->dma_write(1 << ch, IRQSTATUS_L0, ch);
                 return 0;
         }
         if (unlikely(dma_chan[ch].dev_id == -1)) {
@@ -1960,17 +1857,12 @@ static int omap2_dma_handle_ch(int ch)
         if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
                 printk(KERN_INFO "DMA transaction error with device %d\n",
                        dma_chan[ch].dev_id);
-                if (cpu_class_is_omap2()) {
-                        /*
-                         * Errata: sDMA Channel is not disabled
-                         * after a transaction error. So we explicitely
-                         * disable the channel
-                         */
+                if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
                         u32 ccr;
 
-                        ccr = dma_read(CCR(ch));
+                        ccr = p->dma_read(CCR, ch);
                         ccr &= ~OMAP_DMA_CCR_EN;
-                        dma_write(ccr, CCR(ch));
+                        p->dma_write(ccr, CCR, ch);
                         dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
                 }
         }
@@ -1981,16 +1873,16 @@ static int omap2_dma_handle_ch(int ch)
                 printk(KERN_INFO "DMA misaligned error with device %d\n",
                        dma_chan[ch].dev_id);
 
-        dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
-        dma_write(1 << ch, IRQSTATUS_L0);
+        p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, ch);
+        p->dma_write(1 << ch, IRQSTATUS_L0, ch);
         /* read back the register to flush the write */
-        dma_read(IRQSTATUS_L0);
+        p->dma_read(IRQSTATUS_L0, ch);
 
         /* If the ch is not chained then chain_id will be -1 */
         if (dma_chan[ch].chain_id != -1) {
                 int chain_id = dma_chan[ch].chain_id;
                 dma_chan[ch].state = DMA_CH_NOTSTARTED;
-                if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
+                if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
                         dma_chan[dma_chan[ch].next_linked_ch].state =
                                                         DMA_CH_STARTED;
                 if (dma_linked_lch[chain_id].chain_mode ==
@@ -2000,10 +1892,10 @@ static int omap2_dma_handle_ch(int ch)
                 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
                         OMAP_DMA_CHAIN_INCQHEAD(chain_id);
 
-                status = dma_read(CSR(ch));
+                status = p->dma_read(CSR, ch);
         }
 
-        dma_write(status, CSR(ch));
+        p->dma_write(status, CSR, ch);
 
         if (likely(dma_chan[ch].callback != NULL))
                 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
@@ -2017,13 +1909,13 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
         u32 val, enable_reg;
         int i;
 
-        val = dma_read(IRQSTATUS_L0);
+        val = p->dma_read(IRQSTATUS_L0, 0);
         if (val == 0) {
                 if (printk_ratelimit())
                         printk(KERN_WARNING "Spurious DMA IRQ\n");
                 return IRQ_HANDLED;
         }
-        enable_reg = dma_read(IRQENABLE_L0);
+        enable_reg = p->dma_read(IRQENABLE_L0, 0);
         val &= enable_reg; /* Dispatch only relevant interrupts */
         for (i = 0; i < dma_lch_count && val != 0; i++) {
                 if (val & 1)
@@ -2049,119 +1941,66 @@ static struct irqaction omap24xx_dma_irq;
 void omap_dma_global_context_save(void)
 {
         omap_dma_global_context.dma_irqenable_l0 =
-                dma_read(IRQENABLE_L0);
+                p->dma_read(IRQENABLE_L0, 0);
         omap_dma_global_context.dma_ocp_sysconfig =
-                dma_read(OCP_SYSCONFIG);
-        omap_dma_global_context.dma_gcr = dma_read(GCR);
+                p->dma_read(OCP_SYSCONFIG, 0);
+        omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
 }
 
 void omap_dma_global_context_restore(void)
 {
         int ch;
 
-        dma_write(omap_dma_global_context.dma_gcr, GCR);
-        dma_write(omap_dma_global_context.dma_ocp_sysconfig,
-                OCP_SYSCONFIG);
-        dma_write(omap_dma_global_context.dma_irqenable_l0,
-                IRQENABLE_L0);
+        p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
+        p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
+                OCP_SYSCONFIG, 0);
+        p->dma_write(omap_dma_global_context.dma_irqenable_l0,
+                IRQENABLE_L0, 0);
 
-        /*
-         * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
-         * after secure sram context save and restore. Hence we need to
-         * manually clear those IRQs to avoid spurious interrupts. This
-         * affects only secure devices.
-         */
-        if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
-                dma_write(0x3 , IRQSTATUS_L0);
+        if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
+                p->dma_write(0x3 , IRQSTATUS_L0, 0);
 
         for (ch = 0; ch < dma_chan_count; ch++)
                 if (dma_chan[ch].dev_id != -1)
                         omap_clear_dma(ch);
 }
 
-/*----------------------------------------------------------------------------*/
-
-static int __init omap_init_dma(void)
+static int __devinit omap_system_dma_probe(struct platform_device *pdev)
 {
-        unsigned long base;
-        int ch, r;
-
-        if (cpu_class_is_omap1()) {
-                base = OMAP1_DMA_BASE;
-                dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
-        } else if (cpu_is_omap24xx()) {
-                base = OMAP24XX_DMA4_BASE;
-                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
-        } else if (cpu_is_omap34xx()) {
-                base = OMAP34XX_DMA4_BASE;
-                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
-        } else if (cpu_is_omap44xx()) {
-                base = OMAP44XX_DMA4_BASE;
-                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
-        } else {
-                pr_err("DMA init failed for unsupported omap\n");
-                return -ENODEV;
+        int ch, ret = 0;
+        int dma_irq;
+        char irq_name[4];
+        int irq_rel;
+
+        p = pdev->dev.platform_data;
+        if (!p) {
+                dev_err(&pdev->dev, "%s: System DMA initialized without"
+                        "platform data\n", __func__);
+                return -EINVAL;
         }
 
-        omap_dma_base = ioremap(base, SZ_4K);
-        BUG_ON(!omap_dma_base);
+        d                       = p->dma_attr;
+        errata                  = p->errata;
 
-        if (cpu_class_is_omap2() && omap_dma_reserve_channels
+        if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
                         && (omap_dma_reserve_channels <= dma_lch_count))
-                dma_lch_count = omap_dma_reserve_channels;
+                d->lch_count    = omap_dma_reserve_channels;
 
-        dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
-                                GFP_KERNEL);
-        if (!dma_chan) {
-                r = -ENOMEM;
-                goto out_unmap;
-        }
+        dma_lch_count           = d->lch_count;
+        dma_chan_count          = dma_lch_count;
+        dma_chan                = d->chan;
+        enable_1510_mode        = d->dev_caps & ENABLE_1510_MODE;
 
         if (cpu_class_is_omap2()) {
                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
                                                 dma_lch_count, GFP_KERNEL);
                 if (!dma_linked_lch) {
-                        r = -ENOMEM;
-                        goto out_free;
+                        ret = -ENOMEM;
+                        goto exit_dma_lch_fail;
                 }
         }
 
-        if (cpu_is_omap15xx()) {
-                printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
-                dma_chan_count = 9;
-                enable_1510_mode = 1;
-        } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
-                printk(KERN_INFO "OMAP DMA hardware version %d\n",
-                       dma_read(HW_ID));
-                printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
-                       (dma_read(CAPS_0_U) << 16) |
-                       dma_read(CAPS_0_L),
-                       (dma_read(CAPS_1_U) << 16) |
-                       dma_read(CAPS_1_L),
-                       dma_read(CAPS_2), dma_read(CAPS_3),
-                       dma_read(CAPS_4));
-                if (!enable_1510_mode) {
-                        u16 w;
-
-                        /* Disable OMAP 3.0/3.1 compatibility mode. */
-                        w = dma_read(GSCR);
-                        w |= 1 << 3;
-                        dma_write(w, GSCR);
-                        dma_chan_count = 16;
-                } else
-                        dma_chan_count = 9;
-        } else if (cpu_class_is_omap2()) {
-                u8 revision = dma_read(REVISION) & 0xff;
-                printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
-                       revision >> 4, revision & 0xf);
-                dma_chan_count = dma_lch_count;
-        } else {
-                dma_chan_count = 0;
-                return 0;
-        }
-
         spin_lock_init(&dma_chan_lock);
-
         for (ch = 0; ch < dma_chan_count; ch++) {
                 omap_clear_dma(ch);
                 if (cpu_class_is_omap2())
@@ -2178,20 +2017,23 @@ static int __init omap_init_dma(void)
                          * request_irq() doesn't like dev_id (ie. ch) being
                          * zero, so we have to kludge around this.
                          */
-                        r = request_irq(omap1_dma_irq[ch],
+                        sprintf(&irq_name[0], "%d", ch);
+                        dma_irq = platform_get_irq_byname(pdev, irq_name);
+
+                        if (dma_irq < 0) {
+                                ret = dma_irq;
+                                goto exit_dma_irq_fail;
+                        }
+
+                        /* INT_DMA_LCD is handled in lcd_dma.c */
+                        if (dma_irq == INT_DMA_LCD)
+                                continue;
+
+                        ret = request_irq(dma_irq,
                                         omap1_dma_irq_handler, 0, "DMA",
                                         (void *) (ch + 1));
-                        if (r != 0) {
-                                int i;
-
-                                printk(KERN_ERR "unable to request IRQ %d "
-                                       "for DMA (error %d)\n",
-                                       omap1_dma_irq[ch], r);
-                                for (i = 0; i < ch; i++)
-                                        free_irq(omap1_dma_irq[i],
-                                                 (void *) (i + 1));
-                                goto out_free;
-                        }
+                        if (ret != 0)
+                                goto exit_dma_irq_fail;
                 }
         }
 
@@ -2200,46 +2042,91 @@ static int __init omap_init_dma(void)
                                 DMA_DEFAULT_FIFO_DEPTH, 0);
 
         if (cpu_class_is_omap2()) {
-                int irq;
-                if (cpu_is_omap44xx())
-                        irq = OMAP44XX_IRQ_SDMA_0;
-                else
-                        irq = INT_24XX_SDMA_IRQ0;
-                setup_irq(irq, &omap24xx_dma_irq);
-        }
-
-        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                /* Enable smartidle idlemodes and autoidle */
-                u32 v = dma_read(OCP_SYSCONFIG);
-                v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
-                                DMA_SYSCONFIG_SIDLEMODE_MASK |
-                                DMA_SYSCONFIG_AUTOIDLE);
-                v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
-                        DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
-                        DMA_SYSCONFIG_AUTOIDLE);
-                dma_write(v , OCP_SYSCONFIG);
-                /* reserve dma channels 0 and 1 in high security devices */
-                if (cpu_is_omap34xx() &&
-                        (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
-                        printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
-                                        "HS ROM code\n");
-                        dma_chan[0].dev_id = 0;
-                        dma_chan[1].dev_id = 1;
+                strcpy(irq_name, "0");
+                dma_irq = platform_get_irq_byname(pdev, irq_name);
+                if (dma_irq < 0) {
+                        dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
+                        goto exit_dma_lch_fail;
+                }
+                ret = setup_irq(dma_irq, &omap24xx_dma_irq);
+                if (ret) {
+                        dev_err(&pdev->dev, "set_up failed for IRQ %d"
+                                "for DMA (error %d)\n", dma_irq, ret);
+                        goto exit_dma_lch_fail;
                 }
         }
 
+        /* reserve dma channels 0 and 1 in high security devices */
+        if (cpu_is_omap34xx() &&
+                (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+                printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
+                                "HS ROM code\n");
+                dma_chan[0].dev_id = 0;
+                dma_chan[1].dev_id = 1;
+        }
+        p->show_dma_caps();
         return 0;
 
-out_free:
+exit_dma_irq_fail:
+        dev_err(&pdev->dev, "unable to request IRQ %d"
+                        "for DMA (error %d)\n", dma_irq, ret);
+        for (irq_rel = 0; irq_rel < ch; irq_rel++) {
+                dma_irq = platform_get_irq(pdev, irq_rel);
+                free_irq(dma_irq, (void *)(irq_rel + 1));
+        }
+
+exit_dma_lch_fail:
+        kfree(p);
+        kfree(d);
         kfree(dma_chan);
+        return ret;
+}
 
-out_unmap:
-        iounmap(omap_dma_base);
+static int __devexit omap_system_dma_remove(struct platform_device *pdev)
+{
+        int dma_irq;
 
-        return r;
+        if (cpu_class_is_omap2()) {
+                char irq_name[4];
+                strcpy(irq_name, "0");
+                dma_irq = platform_get_irq_byname(pdev, irq_name);
+                remove_irq(dma_irq, &omap24xx_dma_irq);
+        } else {
+                int irq_rel = 0;
+                for ( ; irq_rel < dma_chan_count; irq_rel++) {
+                        dma_irq = platform_get_irq(pdev, irq_rel);
+                        free_irq(dma_irq, (void *)(irq_rel + 1));
+                }
+        }
+        kfree(p);
+        kfree(d);
+        kfree(dma_chan);
+        return 0;
+}
+
+static struct platform_driver omap_system_dma_driver = {
+        .probe          = omap_system_dma_probe,
+        .remove         = omap_system_dma_remove,
+        .driver         = {
+                .name   = "omap_dma_system"
+        },
+};
+
+static int __init omap_system_dma_init(void)
+{
+        return platform_driver_register(&omap_system_dma_driver);
+}
+arch_initcall(omap_system_dma_init);
+
+static void __exit omap_system_dma_exit(void)
+{
+        platform_driver_unregister(&omap_system_dma_driver);
 }
 
-arch_initcall(omap_init_dma);
+MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
 
 /*
  * Reserve the omap SDMA channels using cmdline bootarg
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index c05c653d1674..1f98e0b94847 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -21,18 +21,18 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <mach/irqs.h>
 #include <mach/gpio.h>
 #include <asm/mach/irq.h>
-#include <plat/powerdomain.h>
 
 /*
  * OMAP1510 GPIO registers
  */
-#define OMAP1510_GPIO_BASE              0xfffce000
 #define OMAP1510_GPIO_DATA_INPUT        0x00
 #define OMAP1510_GPIO_DATA_OUTPUT       0x04
 #define OMAP1510_GPIO_DIR_CONTROL       0x08
@@ -46,10 +46,6 @@
 /*
  * OMAP1610 specific GPIO registers
  */
-#define OMAP1610_GPIO1_BASE             0xfffbe400
-#define OMAP1610_GPIO2_BASE             0xfffbec00
-#define OMAP1610_GPIO3_BASE             0xfffbb400
-#define OMAP1610_GPIO4_BASE             0xfffbbc00
 #define OMAP1610_GPIO_REVISION          0x0000
 #define OMAP1610_GPIO_SYSCONFIG         0x0010
 #define OMAP1610_GPIO_SYSSTATUS         0x0014
@@ -71,12 +67,6 @@
 /*
  * OMAP7XX specific GPIO registers
  */
-#define OMAP7XX_GPIO1_BASE              0xfffbc000
-#define OMAP7XX_GPIO2_BASE              0xfffbc800
-#define OMAP7XX_GPIO3_BASE              0xfffbd000
-#define OMAP7XX_GPIO4_BASE              0xfffbd800
-#define OMAP7XX_GPIO5_BASE              0xfffbe000
-#define OMAP7XX_GPIO6_BASE              0xfffbe800
 #define OMAP7XX_GPIO_DATA_INPUT         0x00
 #define OMAP7XX_GPIO_DATA_OUTPUT        0x04
 #define OMAP7XX_GPIO_DIR_CONTROL        0x08
@@ -84,25 +74,10 @@
 #define OMAP7XX_GPIO_INT_MASK           0x10
 #define OMAP7XX_GPIO_INT_STATUS         0x14
 
-#define OMAP1_MPUIO_VBASE               OMAP1_MPUIO_BASE
-
 /*
- * omap24xx specific GPIO registers
+ * omap2+ specific GPIO registers
  */
-#define OMAP242X_GPIO1_BASE             0x48018000
-#define OMAP242X_GPIO2_BASE             0x4801a000
-#define OMAP242X_GPIO3_BASE             0x4801c000
-#define OMAP242X_GPIO4_BASE             0x4801e000
-
-#define OMAP243X_GPIO1_BASE             0x4900C000
-#define OMAP243X_GPIO2_BASE             0x4900E000
-#define OMAP243X_GPIO3_BASE             0x49010000
-#define OMAP243X_GPIO4_BASE             0x49012000
-#define OMAP243X_GPIO5_BASE             0x480B6000
-
 #define OMAP24XX_GPIO_REVISION          0x0000
-#define OMAP24XX_GPIO_SYSCONFIG         0x0010
-#define OMAP24XX_GPIO_SYSSTATUS         0x0014
 #define OMAP24XX_GPIO_IRQSTATUS1        0x0018
 #define OMAP24XX_GPIO_IRQSTATUS2        0x0028
 #define OMAP24XX_GPIO_IRQENABLE2        0x002c
@@ -126,7 +101,6 @@
 #define OMAP24XX_GPIO_SETDATAOUT        0x0094
 
 #define OMAP4_GPIO_REVISION             0x0000
-#define OMAP4_GPIO_SYSCONFIG            0x0010
 #define OMAP4_GPIO_EOI                  0x0020
 #define OMAP4_GPIO_IRQSTATUSRAW0        0x0024
 #define OMAP4_GPIO_IRQSTATUSRAW1        0x0028
@@ -138,7 +112,6 @@
 #define OMAP4_GPIO_IRQSTATUSCLR1        0x0040
 #define OMAP4_GPIO_IRQWAKEN0            0x0044
 #define OMAP4_GPIO_IRQWAKEN1            0x0048
-#define OMAP4_GPIO_SYSSTATUS            0x0114
 #define OMAP4_GPIO_IRQENABLE1           0x011c
 #define OMAP4_GPIO_WAKE_EN              0x0120
 #define OMAP4_GPIO_IRQSTATUS2           0x0128
@@ -159,26 +132,6 @@
 #define OMAP4_GPIO_SETWKUENA            0x0184
 #define OMAP4_GPIO_CLEARDATAOUT         0x0190
 #define OMAP4_GPIO_SETDATAOUT           0x0194
-/*
- * omap34xx specific GPIO registers
- */
-
-#define OMAP34XX_GPIO1_BASE             0x48310000
-#define OMAP34XX_GPIO2_BASE             0x49050000
-#define OMAP34XX_GPIO3_BASE             0x49052000
-#define OMAP34XX_GPIO4_BASE             0x49054000
-#define OMAP34XX_GPIO5_BASE             0x49056000
-#define OMAP34XX_GPIO6_BASE             0x49058000
-
-/*
- * OMAP44XX  specific GPIO registers
- */
-#define OMAP44XX_GPIO1_BASE             0x4a310000
-#define OMAP44XX_GPIO2_BASE             0x48055000
-#define OMAP44XX_GPIO3_BASE             0x48057000
-#define OMAP44XX_GPIO4_BASE             0x48059000
-#define OMAP44XX_GPIO5_BASE             0x4805B000
-#define OMAP44XX_GPIO6_BASE             0x4805D000
 
 struct gpio_bank {
         unsigned long pbase;
@@ -190,14 +143,12 @@ struct gpio_bank {
         u32 suspend_wakeup;
         u32 saved_wakeup;
 #endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
         u32 non_wakeup_gpios;
         u32 enabled_non_wakeup_gpios;
 
         u32 saved_datain;
         u32 saved_fallingdetect;
         u32 saved_risingdetect;
-#endif
         u32 level_mask;
         u32 toggle_mask;
         spinlock_t lock;
@@ -205,104 +156,13 @@ struct gpio_bank {
         struct clk *dbck;
         u32 mod_usage;
         u32 dbck_enable_mask;
+        struct device *dev;
+        bool dbck_flag;
+        int stride;
 };
 
-#define METHOD_MPUIO            0
-#define METHOD_GPIO_1510        1
-#define METHOD_GPIO_1610        2
-#define METHOD_GPIO_7XX         3
-#define METHOD_GPIO_24XX        5
-#define METHOD_GPIO_44XX        6
-
-#ifdef CONFIG_ARCH_OMAP16XX
-static struct gpio_bank gpio_bank_1610[5] = {
-        { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
-                METHOD_MPUIO },
-        { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_1610 },
-        { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
-                METHOD_GPIO_1610 },
-        { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
-                METHOD_GPIO_1610 },
-        { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
-                METHOD_GPIO_1610 },
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP15XX
-static struct gpio_bank gpio_bank_1510[2] = {
-        { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
-                METHOD_MPUIO },
-        { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_1510 }
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-static struct gpio_bank gpio_bank_7xx[7] = {
-        { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
-                METHOD_MPUIO },
-        { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_7XX },
-        { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_7XX },
-        { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_7XX },
-        { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4,  IH_GPIO_BASE + 96,
-                METHOD_GPIO_7XX },
-        { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5,  IH_GPIO_BASE + 128,
-                METHOD_GPIO_7XX },
-        { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6,  IH_GPIO_BASE + 160,
-                METHOD_GPIO_7XX },
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-
-static struct gpio_bank gpio_bank_242x[4] = {
-        { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_24XX },
-        { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_24XX },
-        { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_24XX },
-        { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
-                METHOD_GPIO_24XX },
-};
-
-static struct gpio_bank gpio_bank_243x[5] = {
-        { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_24XX },
-        { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_24XX },
-        { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_24XX },
-        { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
-                METHOD_GPIO_24XX },
-        { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
-                METHOD_GPIO_24XX },
-};
-
-#endif
-
 #ifdef CONFIG_ARCH_OMAP3
-static struct gpio_bank gpio_bank_34xx[6] = {
-        { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
-                METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
-                METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
-                METHOD_GPIO_24XX },
-        { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
-                METHOD_GPIO_24XX },
-};
-
 struct omap3_gpio_regs {
-        u32 sysconfig;
         u32 irqenable1;
         u32 irqenable2;
         u32 wake_en;
@@ -318,26 +178,16 @@ struct omap3_gpio_regs {
 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
 #endif
 
-#ifdef CONFIG_ARCH_OMAP4
-static struct gpio_bank gpio_bank_44xx[6] = {
-        { OMAP44XX_GPIO1_BASE, NULL, OMAP44XX_IRQ_GPIO1, IH_GPIO_BASE,
-                METHOD_GPIO_44XX },
-        { OMAP44XX_GPIO2_BASE, NULL, OMAP44XX_IRQ_GPIO2, IH_GPIO_BASE + 32,
-                METHOD_GPIO_44XX },
-        { OMAP44XX_GPIO3_BASE, NULL, OMAP44XX_IRQ_GPIO3, IH_GPIO_BASE + 64,
-                METHOD_GPIO_44XX },
-        { OMAP44XX_GPIO4_BASE, NULL, OMAP44XX_IRQ_GPIO4, IH_GPIO_BASE + 96,
-                METHOD_GPIO_44XX },
-        { OMAP44XX_GPIO5_BASE, NULL, OMAP44XX_IRQ_GPIO5, IH_GPIO_BASE + 128,
-                METHOD_GPIO_44XX },
-        { OMAP44XX_GPIO6_BASE, NULL, OMAP44XX_IRQ_GPIO6, IH_GPIO_BASE + 160,
-                METHOD_GPIO_44XX },
-};
+/*
+ * TODO: Cleanup gpio_bank usage as it is having information
+ * related to all instances of the device
+ */
+static struct gpio_bank *gpio_bank;
 
-#endif
+static int bank_width;
 
-static struct gpio_bank *gpio_bank;
-static int gpio_bank_count;
+/* TODO: Analyze removing gpio_bank_count usage from driver code */
+int gpio_bank_count;
 
 static inline struct gpio_bank *get_gpio_bank(int gpio)
 {
@@ -417,7 +267,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP1
         case METHOD_MPUIO:
-                reg += OMAP_MPUIO_IO_CNTL;
+                reg += OMAP_MPUIO_IO_CNTL / bank->stride;
                 break;
 #endif
 #ifdef CONFIG_ARCH_OMAP15XX
@@ -465,7 +315,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP1
         case METHOD_MPUIO:
-                reg += OMAP_MPUIO_OUTPUT;
+                reg += OMAP_MPUIO_OUTPUT / bank->stride;
                 l = __raw_readl(reg);
                 if (enable)
                         l |= 1 << gpio;
@@ -537,7 +387,7 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP1
         case METHOD_MPUIO:
-                reg += OMAP_MPUIO_INPUT_LATCH;
+                reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
                 break;
 #endif
 #ifdef CONFIG_ARCH_OMAP15XX
@@ -583,7 +433,7 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP1
         case METHOD_MPUIO:
-                reg += OMAP_MPUIO_OUTPUT;
+                reg += OMAP_MPUIO_OUTPUT / bank->stride;
                 break;
 #endif
 #ifdef CONFIG_ARCH_OMAP15XX
@@ -642,6 +492,9 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
         u32                     val;
         u32                     l;
 
+        if (!bank->dbck_flag)
+                return;
+
         if (debounce < 32)
                 debounce = 0x01;
         else if (debounce > 7936)
@@ -651,7 +504,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
 
         l = 1 << get_gpio_index(gpio);
 
-        if (cpu_is_omap44xx())
+        if (bank->method == METHOD_GPIO_44XX)
                 reg += OMAP4_GPIO_DEBOUNCINGTIME;
         else
                 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
@@ -659,7 +512,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
         __raw_writel(debounce, reg);
 
         reg = bank->base;
-        if (cpu_is_omap44xx())
+        if (bank->method == METHOD_GPIO_44XX)
                 reg += OMAP4_GPIO_DEBOUNCENABLE;
         else
                 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
@@ -668,12 +521,10 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
 
         if (debounce) {
                 val |= l;
-                if (cpu_is_omap34xx() || cpu_is_omap44xx())
-                        clk_enable(bank->dbck);
+                clk_enable(bank->dbck);
         } else {
                 val &= ~l;
-                if (cpu_is_omap34xx() || cpu_is_omap44xx())
-                        clk_disable(bank->dbck);
+                clk_disable(bank->dbck);
         }
         bank->dbck_enable_mask = val;
 
@@ -769,7 +620,7 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
 
         switch (bank->method) {
         case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_INT_EDGE;
+                reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
                 break;
 #ifdef CONFIG_ARCH_OMAP15XX
         case METHOD_GPIO_1510:
@@ -803,7 +654,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP1
         case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_INT_EDGE;
+                reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
                 l = __raw_readl(reg);
                 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
                         bank->toggle_mask |= 1 << gpio;
@@ -989,7 +840,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP1
         case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_MASKIT;
+                reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
                 mask = 0xffff;
                 inv = 1;
                 break;
@@ -1046,7 +897,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP1
         case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_MASKIT;
+                reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
                 l = __raw_readl(reg);
                 if (enable)
                         l &= ~(gpio_mask);
@@ -1296,7 +1147,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         bank = get_irq_data(irq);
 #ifdef CONFIG_ARCH_OMAP1
         if (bank->method == METHOD_MPUIO)
-                isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
+                isr_reg = bank->base +
+                                OMAP_MPUIO_GPIO_INT / bank->stride;
 #endif
 #ifdef CONFIG_ARCH_OMAP15XX
         if (bank->method == METHOD_GPIO_1510)
@@ -1318,6 +1170,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         if (bank->method == METHOD_GPIO_44XX)
                 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
 #endif
+
+        if (WARN_ON(!isr_reg))
+                goto exit;
+
         while(1) {
                 u32 isr_saved, level_mask = 0;
                 u32 enabled;
@@ -1377,6 +1233,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         configured, we must unmask the bank interrupt only after
         handler(s) are executed in order to avoid spurious bank
         interrupt */
+exit:
         if (!unmasked)
                 desc->chip->unmask(irq);
 
@@ -1489,7 +1346,8 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
         struct gpio_bank        *bank = platform_get_drvdata(pdev);
-        void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
+        void __iomem            *mask_reg = bank->base +
+                                        OMAP_MPUIO_GPIO_MASKIT / bank->stride;
         unsigned long           flags;
 
         spin_lock_irqsave(&bank->lock, flags);
@@ -1504,7 +1362,8 @@ static int omap_mpuio_resume_noirq(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
         struct gpio_bank        *bank = platform_get_drvdata(pdev);
-        void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
+        void __iomem            *mask_reg = bank->base +
+                                        OMAP_MPUIO_GPIO_MASKIT / bank->stride;
         unsigned long           flags;
 
         spin_lock_irqsave(&bank->lock, flags);
@@ -1540,7 +1399,8 @@ static struct platform_device omap_mpuio_device = {
 
 static inline void mpuio_init(void)
 {
-        platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
+        struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
+        platform_set_drvdata(&omap_mpuio_device, bank);
 
         if (platform_driver_register(&omap_mpuio_driver) == 0)
                 (void) platform_device_register(&omap_mpuio_device);
@@ -1583,7 +1443,7 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
 
         switch (bank->method) {
         case METHOD_MPUIO:
-                reg += OMAP_MPUIO_IO_CNTL;
+                reg += OMAP_MPUIO_IO_CNTL / bank->stride;
                 break;
         case METHOD_GPIO_1510:
                 reg += OMAP1510_GPIO_DIR_CONTROL;
@@ -1645,6 +1505,13 @@ static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
         unsigned long flags;
 
         bank = container_of(chip, struct gpio_bank, chip);
+
+        if (!bank->dbck) {
+                bank->dbck = clk_get(bank->dev, "dbclk");
+                if (IS_ERR(bank->dbck))
+                        dev_err(bank->dev, "Could not get gpio dbck\n");
+        }
+
         spin_lock_irqsave(&bank->lock, flags);
         _set_gpio_debounce(bank, offset, debounce);
         spin_unlock_irqrestore(&bank->lock, flags);
@@ -1673,34 +1540,16 @@ static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
 
 /*---------------------------------------------------------------------*/
 
-static int initialized;
-#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
-static struct clk * gpio_ick;
-#endif
-
-#if defined(CONFIG_ARCH_OMAP2)
-static struct clk * gpio_fck;
-#endif
-
-#if defined(CONFIG_ARCH_OMAP2430)
-static struct clk * gpio5_ick;
-static struct clk * gpio5_fck;
-#endif
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
-#endif
-
-static void __init omap_gpio_show_rev(void)
+static void __init omap_gpio_show_rev(struct gpio_bank *bank)
 {
         u32 rev;
 
-        if (cpu_is_omap16xx())
-                rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
+        if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
+                rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
         else if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+                rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
         else if (cpu_is_omap44xx())
-                rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
+                rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
         else
                 return;
 
@@ -1713,250 +1562,190 @@ static void __init omap_gpio_show_rev(void)
  */
 static struct lock_class_key gpio_lock_class;
 
-static int __init _omap_gpio_init(void)
+static inline int init_gpio_info(struct platform_device *pdev)
 {
-        int i;
-        int gpio = 0;
-        struct gpio_bank *bank;
-        int bank_size = SZ_8K;  /* Module 4KB + L4 4KB except on omap1 */
-        char clk_name[11];
-
-        initialized = 1;
-
-#if defined(CONFIG_ARCH_OMAP1)
-        if (cpu_is_omap15xx()) {
-                gpio_ick = clk_get(NULL, "arm_gpio_ck");
-                if (IS_ERR(gpio_ick))
-                        printk("Could not get arm_gpio_ck\n");
-                else
-                        clk_enable(gpio_ick);
+        /* TODO: Analyze removing gpio_bank_count usage from driver code */
+        gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
+                                GFP_KERNEL);
+        if (!gpio_bank) {
+                dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
+                return -ENOMEM;
         }
-#endif
-#if defined(CONFIG_ARCH_OMAP2)
-        if (cpu_class_is_omap2()) {
-                gpio_ick = clk_get(NULL, "gpios_ick");
-                if (IS_ERR(gpio_ick))
-                        printk("Could not get gpios_ick\n");
-                else
-                        clk_enable(gpio_ick);
-                gpio_fck = clk_get(NULL, "gpios_fck");
-                if (IS_ERR(gpio_fck))
-                        printk("Could not get gpios_fck\n");
-                else
-                        clk_enable(gpio_fck);
+        return 0;
+}
 
-                /*
-                 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
-                 */
-#if defined(CONFIG_ARCH_OMAP2430)
-                if (cpu_is_omap2430()) {
-                        gpio5_ick = clk_get(NULL, "gpio5_ick");
-                        if (IS_ERR(gpio5_ick))
-                                printk("Could not get gpio5_ick\n");
-                        else
-                                clk_enable(gpio5_ick);
-                        gpio5_fck = clk_get(NULL, "gpio5_fck");
-                        if (IS_ERR(gpio5_fck))
-                                printk("Could not get gpio5_fck\n");
-                        else
-                                clk_enable(gpio5_fck);
+/* TODO: Cleanup cpu_is_* checks */
+static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
+{
+        if (cpu_class_is_omap2()) {
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(0xffffffff, bank->base +
+                                        OMAP4_GPIO_IRQSTATUSCLR0);
+                        __raw_writel(0x00000000, bank->base +
+                                         OMAP4_GPIO_DEBOUNCENABLE);
+                        /* Initialize interface clk ungated, module enabled */
+                        __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
+                } else if (cpu_is_omap34xx()) {
+                        __raw_writel(0x00000000, bank->base +
+                                        OMAP24XX_GPIO_IRQENABLE1);
+                        __raw_writel(0xffffffff, bank->base +
+                                        OMAP24XX_GPIO_IRQSTATUS1);
+                        __raw_writel(0x00000000, bank->base +
+                                        OMAP24XX_GPIO_DEBOUNCE_EN);
+
+                        /* Initialize interface clk ungated, module enabled */
+                        __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
+                } else if (cpu_is_omap24xx()) {
+                        static const u32 non_wakeup_gpios[] = {
+                                0xe203ffc0, 0x08700040
+                        };
+                        if (id < ARRAY_SIZE(non_wakeup_gpios))
+                                bank->non_wakeup_gpios = non_wakeup_gpios[id];
                 }
-#endif
-        }
-#endif
+        } else if (cpu_class_is_omap1()) {
+                if (bank_is_mpuio(bank))
+                        __raw_writew(0xffff, bank->base +
+                                OMAP_MPUIO_GPIO_MASKIT / bank->stride);
+                if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
+                        __raw_writew(0xffff, bank->base
+                                                + OMAP1510_GPIO_INT_MASK);
+                        __raw_writew(0x0000, bank->base
+                                                + OMAP1510_GPIO_INT_STATUS);
+                }
+                if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
+                        __raw_writew(0x0000, bank->base
+                                                + OMAP1610_GPIO_IRQENABLE1);
+                        __raw_writew(0xffff, bank->base
+                                                + OMAP1610_GPIO_IRQSTATUS1);
+                        __raw_writew(0x0014, bank->base
+                                                + OMAP1610_GPIO_SYSCONFIG);
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
-                        sprintf(clk_name, "gpio%d_ick", i + 1);
-                        gpio_iclks[i] = clk_get(NULL, clk_name);
-                        if (IS_ERR(gpio_iclks[i]))
-                                printk(KERN_ERR "Could not get %s\n", clk_name);
-                        else
-                                clk_enable(gpio_iclks[i]);
+                        /*
+                         * Enable system clock for GPIO module.
+                         * The CAM_CLK_CTRL *is* really the right place.
+                         */
+                        omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
+                                                ULPD_CAM_CLK_CTRL);
+                }
+                if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
+                        __raw_writel(0xffffffff, bank->base
+                                                + OMAP7XX_GPIO_INT_MASK);
+                        __raw_writel(0x00000000, bank->base
+                                                + OMAP7XX_GPIO_INT_STATUS);
                 }
         }
-#endif
+}
 
+static void __init omap_gpio_chip_init(struct gpio_bank *bank)
+{
+        int j;
+        static int gpio;
 
-#ifdef CONFIG_ARCH_OMAP15XX
-        if (cpu_is_omap15xx()) {
-                gpio_bank_count = 2;
-                gpio_bank = gpio_bank_1510;
-                bank_size = SZ_2K;
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-        if (cpu_is_omap16xx()) {
-                gpio_bank_count = 5;
-                gpio_bank = gpio_bank_1610;
-                bank_size = SZ_2K;
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        if (cpu_is_omap7xx()) {
-                gpio_bank_count = 7;
-                gpio_bank = gpio_bank_7xx;
-                bank_size = SZ_2K;
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP2
-        if (cpu_is_omap242x()) {
-                gpio_bank_count = 4;
-                gpio_bank = gpio_bank_242x;
-        }
-        if (cpu_is_omap243x()) {
-                gpio_bank_count = 5;
-                gpio_bank = gpio_bank_243x;
-        }
+        bank->mod_usage = 0;
+        /*
+         * REVISIT eventually switch from OMAP-specific gpio structs
+         * over to the generic ones
+         */
+        bank->chip.request = omap_gpio_request;
+        bank->chip.free = omap_gpio_free;
+        bank->chip.direction_input = gpio_input;
+        bank->chip.get = gpio_get;
+        bank->chip.direction_output = gpio_output;
+        bank->chip.set_debounce = gpio_debounce;
+        bank->chip.set = gpio_set;
+        bank->chip.to_irq = gpio_2irq;
+        if (bank_is_mpuio(bank)) {
+                bank->chip.label = "mpuio";
+#ifdef CONFIG_ARCH_OMAP16XX
+                bank->chip.dev = &omap_mpuio_device.dev;
 #endif
-#ifdef CONFIG_ARCH_OMAP3
-        if (cpu_is_omap34xx()) {
-                gpio_bank_count = OMAP34XX_NR_GPIOS;
-                gpio_bank = gpio_bank_34xx;
+                bank->chip.base = OMAP_MPUIO(0);
+        } else {
+                bank->chip.label = "gpio";
+                bank->chip.base = gpio;
+                gpio += bank_width;
         }
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        if (cpu_is_omap44xx()) {
-                gpio_bank_count = OMAP34XX_NR_GPIOS;
-                gpio_bank = gpio_bank_44xx;
+        bank->chip.ngpio = bank_width;
+
+        gpiochip_add(&bank->chip);
+
+        for (j = bank->virtual_irq_start;
+                     j < bank->virtual_irq_start + bank_width; j++) {
+                lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
+                set_irq_chip_data(j, bank);
+                if (bank_is_mpuio(bank))
+                        set_irq_chip(j, &mpuio_irq_chip);
+                else
+                        set_irq_chip(j, &gpio_irq_chip);
+                set_irq_handler(j, handle_simple_irq);
+                set_irq_flags(j, IRQF_VALID);
         }
-#endif
-        for (i = 0; i < gpio_bank_count; i++) {
-                int j, gpio_count = 16;
+        set_irq_chained_handler(bank->irq, gpio_irq_handler);
+        set_irq_data(bank->irq, bank);
+}
+
+static int __devinit omap_gpio_probe(struct platform_device *pdev)
+{
+        static int gpio_init_done;
+        struct omap_gpio_platform_data *pdata;
+        struct resource *res;
+        int id;
+        struct gpio_bank *bank;
 
-                bank = &gpio_bank[i];
-                spin_lock_init(&bank->lock);
+        if (!pdev->dev.platform_data)
+                return -EINVAL;
 
-                /* Static mapping, never released */
-                bank->base = ioremap(bank->pbase, bank_size);
-                if (!bank->base) {
-                        printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
-                        continue;
-                }
+        pdata = pdev->dev.platform_data;
 
-                if (bank_is_mpuio(bank))
-                        __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
-                if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
-                        __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
-                        __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
-                }
-                if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
-                        __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
-                        __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
-                        __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
-                }
-                if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
-                        __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
-                        __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
+        if (!gpio_init_done) {
+                int ret;
 
-                        gpio_count = 32; /* 7xx has 32-bit GPIOs */
-                }
+                ret = init_gpio_info(pdev);
+                if (ret)
+                        return ret;
+        }
 
-#ifdef CONFIG_ARCH_OMAP2PLUS
-                if ((bank->method == METHOD_GPIO_24XX) ||
-                                (bank->method == METHOD_GPIO_44XX)) {
-                        static const u32 non_wakeup_gpios[] = {
-                                0xe203ffc0, 0x08700040
-                        };
+        id = pdev->id;
+        bank = &gpio_bank[id];
 
-                        if (cpu_is_omap44xx()) {
-                                __raw_writel(0xffffffff, bank->base +
-                                                OMAP4_GPIO_IRQSTATUSCLR0);
-                                __raw_writew(0x0015, bank->base +
-                                                OMAP4_GPIO_SYSCONFIG);
-                                __raw_writel(0x00000000, bank->base +
-                                                 OMAP4_GPIO_DEBOUNCENABLE);
-                                /*
-                                 * Initialize interface clock ungated,
-                                 * module enabled
-                                 */
-                                __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
-                        } else {
-                                __raw_writel(0x00000000, bank->base +
-                                                OMAP24XX_GPIO_IRQENABLE1);
-                                __raw_writel(0xffffffff, bank->base +
-                                                OMAP24XX_GPIO_IRQSTATUS1);
-                                __raw_writew(0x0015, bank->base +
-                                                OMAP24XX_GPIO_SYSCONFIG);
-                                __raw_writel(0x00000000, bank->base +
-                                                OMAP24XX_GPIO_DEBOUNCE_EN);
-
-                                /*
-                                 * Initialize interface clock ungated,
-                                 * module enabled
-                                 */
-                                __raw_writel(0, bank->base +
-                                                OMAP24XX_GPIO_CTRL);
-                        }
-                        if (cpu_is_omap24xx() &&
-                            i < ARRAY_SIZE(non_wakeup_gpios))
-                                bank->non_wakeup_gpios = non_wakeup_gpios[i];
-                        gpio_count = 32;
-                }
-#endif
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (unlikely(!res)) {
+                dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
+                return -ENODEV;
+        }
 
-                bank->mod_usage = 0;
-                /* REVISIT eventually switch from OMAP-specific gpio structs
-                 * over to the generic ones
-                 */
-                bank->chip.request = omap_gpio_request;
-                bank->chip.free = omap_gpio_free;
-                bank->chip.direction_input = gpio_input;
-                bank->chip.get = gpio_get;
-                bank->chip.direction_output = gpio_output;
-                bank->chip.set_debounce = gpio_debounce;
-                bank->chip.set = gpio_set;
-                bank->chip.to_irq = gpio_2irq;
-                if (bank_is_mpuio(bank)) {
-                        bank->chip.label = "mpuio";
-#ifdef CONFIG_ARCH_OMAP16XX
-                        bank->chip.dev = &omap_mpuio_device.dev;
-#endif
-                        bank->chip.base = OMAP_MPUIO(0);
-                } else {
-                        bank->chip.label = "gpio";
-                        bank->chip.base = gpio;
-                        gpio += gpio_count;
-                }
-                bank->chip.ngpio = gpio_count;
+        bank->irq = res->start;
+        bank->virtual_irq_start = pdata->virtual_irq_start;
+        bank->method = pdata->bank_type;
+        bank->dev = &pdev->dev;
+        bank->dbck_flag = pdata->dbck_flag;
+        bank->stride = pdata->bank_stride;
+        bank_width = pdata->bank_width;
 
-                gpiochip_add(&bank->chip);
+        spin_lock_init(&bank->lock);
 
-                for (j = bank->virtual_irq_start;
-                     j < bank->virtual_irq_start + gpio_count; j++) {
-                        lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
-                        set_irq_chip_data(j, bank);
-                        if (bank_is_mpuio(bank))
-                                set_irq_chip(j, &mpuio_irq_chip);
-                        else
-                                set_irq_chip(j, &gpio_irq_chip);
-                        set_irq_handler(j, handle_simple_irq);
-                        set_irq_flags(j, IRQF_VALID);
-                }
-                set_irq_chained_handler(bank->irq, gpio_irq_handler);
-                set_irq_data(bank->irq, bank);
-
-                if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                        sprintf(clk_name, "gpio%d_dbck", i + 1);
-                        bank->dbck = clk_get(NULL, clk_name);
-                        if (IS_ERR(bank->dbck))
-                                printk(KERN_ERR "Could not get %s\n", clk_name);
-                }
+        /* Static mapping, never released */
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (unlikely(!res)) {
+                dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
+                return -ENODEV;
         }
 
-        /* Enable system clock for GPIO module.
-         * The CAM_CLK_CTRL *is* really the right place. */
-        if (cpu_is_omap16xx())
-                omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
+        bank->base = ioremap(res->start, resource_size(res));
+        if (!bank->base) {
+                dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
+                return -ENOMEM;
+        }
 
-        /* Enable autoidle for the OCP interface */
-        if (cpu_is_omap24xx())
-                omap_writel(1 << 0, 0x48019010);
-        if (cpu_is_omap34xx())
-                omap_writel(1 << 0, 0x48306814);
+        pm_runtime_enable(bank->dev);
+        pm_runtime_get_sync(bank->dev);
+
+        omap_gpio_mod_init(bank, id);
+        omap_gpio_chip_init(bank);
+        omap_gpio_show_rev(bank);
 
-        omap_gpio_show_rev();
+        if (!gpio_init_done)
+                gpio_init_done = 1;
 
         return 0;
 }
@@ -2074,7 +1863,7 @@ static struct sys_device omap_gpio_device = {
 
 static int workaround_enabled;
 
-void omap2_gpio_prepare_for_idle(int power_state)
+void omap2_gpio_prepare_for_idle(int off_mode)
 {
         int i, c = 0;
         int min = 0;
@@ -2090,7 +1879,7 @@ void omap2_gpio_prepare_for_idle(int power_state)
                 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
                         clk_disable(bank->dbck);
 
-                if (power_state > PWRDM_POWER_OFF)
+                if (!off_mode)
                         continue;
 
                 /* If going to OFF, remove triggering for all
@@ -2251,8 +2040,6 @@ void omap_gpio_save_context(void)
         /* saving banks from 2-6 only since GPIO1 is in WKUP */
         for (i = 1; i < gpio_bank_count; i++) {
                 struct gpio_bank *bank = &gpio_bank[i];
-                gpio_context[i].sysconfig =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
                 gpio_context[i].irqenable1 =
                         __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
                 gpio_context[i].irqenable2 =
@@ -2283,8 +2070,6 @@ void omap_gpio_restore_context(void)
 
         for (i = 1; i < gpio_bank_count; i++) {
                 struct gpio_bank *bank = &gpio_bank[i];
-                __raw_writel(gpio_context[i].sysconfig,
-                                bank->base + OMAP24XX_GPIO_SYSCONFIG);
                 __raw_writel(gpio_context[i].irqenable1,
                                 bank->base + OMAP24XX_GPIO_IRQENABLE1);
                 __raw_writel(gpio_context[i].irqenable2,
@@ -2309,25 +2094,28 @@ void omap_gpio_restore_context(void)
 }
 #endif
 
+static struct platform_driver omap_gpio_driver = {
+        .probe          = omap_gpio_probe,
+        .driver         = {
+                .name   = "omap_gpio",
+        },
+};
+
 /*
- * This may get called early from board specific init
- * for boards that have interrupts routed via FPGA.
+ * gpio driver register needs to be done before
+ * machine_init functions access gpio APIs.
+ * Hence omap_gpio_drv_reg() is a postcore_initcall.
  */
-int __init omap_gpio_init(void)
+static int __init omap_gpio_drv_reg(void)
 {
-        if (!initialized)
-                return _omap_gpio_init();
-        else
-                return 0;
+        return platform_driver_register(&omap_gpio_driver);
 }
+postcore_initcall(omap_gpio_drv_reg);
 
 static int __init omap_gpio_sysinit(void)
 {
         int ret = 0;
 
-        if (!initialized)
-                ret = _omap_gpio_init();
-
         mpuio_init();
 
 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a5ce4f0aad35..a4f8003de664 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -27,20 +27,20 @@
 #include <linux/platform_device.h>
 #include <linux/i2c.h>
 #include <linux/i2c-omap.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <mach/irqs.h>
 #include <plat/mux.h>
 #include <plat/i2c.h>
 #include <plat/omap-pm.h>
+#include <plat/omap_device.h>
 
 #define OMAP_I2C_SIZE           0x3f
 #define OMAP1_I2C_BASE          0xfffb3800
-#define OMAP2_I2C_BASE1         0x48070000
-#define OMAP2_I2C_BASE2         0x48072000
-#define OMAP2_I2C_BASE3         0x48060000
-#define OMAP4_I2C_BASE4         0x48350000
 
-static const char name[] = "i2c_omap";
+static const char name[] = "omap_i2c";
 
 #define I2C_RESOURCE_BUILDER(base, irq)                 \
         {                                               \
@@ -55,15 +55,6 @@ static const char name[] = "i2c_omap";
 
 static struct resource i2c_resources[][2] = {
         { I2C_RESOURCE_BUILDER(0, 0) },
-#if     defined(CONFIG_ARCH_OMAP2PLUS)
-        { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) },
-#endif
-#if     defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) },
-#endif
-#if     defined(CONFIG_ARCH_OMAP4)
-        { I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) },
-#endif
 };
 
 #define I2C_DEV_BUILDER(bus_id, res, data)              \
@@ -77,18 +68,11 @@ static struct resource i2c_resources[][2] = {
                 },                                      \
         }
 
-static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
+#define MAX_OMAP_I2C_HWMOD_NAME_LEN     16
+#define OMAP_I2C_MAX_CONTROLLERS 4
+static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
 static struct platform_device omap_i2c_devices[] = {
         I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
-#if     defined(CONFIG_ARCH_OMAP2PLUS)
-        I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
-#endif
-#if     defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-        I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
-#endif
-#if     defined(CONFIG_ARCH_OMAP4)
-        I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]),
-#endif
 };
 
 #define OMAP_I2C_CMDLINE_SETUP  (BIT(31))
@@ -109,35 +93,25 @@ static int __init omap_i2c_nr_ports(void)
         return ports;
 }
 
-/* Shared between omap2 and 3 */
-static resource_size_t omap2_i2c_irq[3] __initdata = {
-        INT_24XX_I2C1_IRQ,
-        INT_24XX_I2C2_IRQ,
-        INT_34XX_I2C3_IRQ,
-};
-
-static resource_size_t omap4_i2c_irq[4] __initdata = {
-        OMAP44XX_IRQ_I2C1,
-        OMAP44XX_IRQ_I2C2,
-        OMAP44XX_IRQ_I2C3,
-        OMAP44XX_IRQ_I2C4,
-};
-
-static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
+static inline int omap1_i2c_add_bus(int bus_id)
 {
-        struct omap_i2c_bus_platform_data *pd;
+        struct platform_device *pdev;
+        struct omap_i2c_bus_platform_data *pdata;
         struct resource *res;
 
-        pd = pdev->dev.platform_data;
+        omap1_i2c_mux_pins(bus_id);
+
+        pdev = &omap_i2c_devices[bus_id - 1];
         res = pdev->resource;
         res[0].start = OMAP1_I2C_BASE;
         res[0].end = res[0].start + OMAP_I2C_SIZE;
         res[1].start = INT_I2C;
-        omap1_i2c_mux_pins(bus_id);
+        pdata = &i2c_pdata[bus_id - 1];
 
         return platform_device_register(pdev);
 }
 
+
 /*
  * XXX This function is a temporary compatibility wrapper - only
  * needed until the I2C driver can be converted to call
@@ -148,52 +122,64 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
         omap_pm_set_max_mpu_wakeup_lat(dev, t);
 }
 
-static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
-{
-        struct resource *res;
-        resource_size_t *irq;
+static struct omap_device_pm_latency omap_i2c_latency[] = {
+        [0] = {
+                .deactivate_func        = omap_device_idle_hwmods,
+                .activate_func          = omap_device_enable_hwmods,
+                .flags                  = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+};
 
-        res = pdev->resource;
+#ifdef CONFIG_ARCH_OMAP2PLUS
+static inline int omap2_i2c_add_bus(int bus_id)
+{
+        int l;
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
+        struct omap_i2c_bus_platform_data *pdata;
 
-        if (!cpu_is_omap44xx())
-                irq = omap2_i2c_irq;
-        else
-                irq = omap4_i2c_irq;
+        omap2_i2c_mux_pins(bus_id);
 
-        if (bus_id == 1) {
-                res[0].start = OMAP2_I2C_BASE1;
-                res[0].end = res[0].start + OMAP_I2C_SIZE;
+        l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
+        WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
+                "String buffer overflow in I2C%d device setup\n", bus_id);
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                        pr_err("Could not look up %s\n", oh_name);
+                        return -EEXIST;
         }
 
-        res[1].start = irq[bus_id - 1];
-        omap2_i2c_mux_pins(bus_id);
-
+        pdata = &i2c_pdata[bus_id - 1];
         /*
          * When waiting for completion of a i2c transfer, we need to
          * set a wake up latency constraint for the MPU. This is to
          * ensure quick enough wakeup from idle, when transfer
          * completes.
+         * Only omap3 has support for constraints
          */
-        if (cpu_is_omap34xx()) {
-                struct omap_i2c_bus_platform_data *pd;
-
-                pd = pdev->dev.platform_data;
-                pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
-        }
-
-        return platform_device_register(pdev);
+        if (cpu_is_omap34xx())
+                pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
+        od = omap_device_build(name, bus_id, oh, pdata,
+                        sizeof(struct omap_i2c_bus_platform_data),
+                        omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0);
+        WARN(IS_ERR(od), "Could not build omap_device for %s\n", name);
+
+        return PTR_ERR(od);
 }
+#else
+static inline int omap2_i2c_add_bus(int bus_id)
+{
+        return 0;
+}
+#endif
 
 static int __init omap_i2c_add_bus(int bus_id)
 {
-        struct platform_device *pdev;
-
-        pdev = &omap_i2c_devices[bus_id - 1];
-
         if (cpu_class_is_omap1())
-                return omap1_i2c_add_bus(pdev, bus_id);
+                return omap1_i2c_add_bus(bus_id);
         else
-                return omap2_i2c_add_bus(pdev, bus_id);
+                return omap2_i2c_add_bus(bus_id);
 }
 
 /**
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index bb937f3fabed..256ab3f1ec8f 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -8,7 +8,7 @@
 #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_CLKDEV_OMAP_H
 
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 
 struct omap_clk {
         u16                             cpu;
@@ -31,18 +31,18 @@ struct omap_clk {
 #define CK_1510         (1 << 2)
 #define CK_16XX         (1 << 3)        /* 16xx, 17xx, 5912 */
 #define CK_242X         (1 << 4)
-#define CK_243X         (1 << 5)
-#define CK_3XXX         (1 << 6)        /* OMAP3 + AM3 common clocks*/
-#define CK_343X         (1 << 7)        /* OMAP34xx common clocks */
-#define CK_3430ES1      (1 << 8)        /* 34xxES1 only */
-#define CK_3430ES2      (1 << 9)        /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_3505         (1 << 10)
-#define CK_3517         (1 << 11)
-#define CK_36XX         (1 << 12)       /* OMAP36xx/37xx-specific clocks */
-#define CK_443X         (1 << 13)
+#define CK_243X         (1 << 5)        /* 243x, 253x */
+#define CK_3430ES1      (1 << 6)        /* 34xxES1 only */
+#define CK_3430ES2PLUS  (1 << 7)        /* 34xxES2, ES3, non-Sitara 35xx only */
+#define CK_3505         (1 << 8)
+#define CK_3517         (1 << 9)
+#define CK_36XX         (1 << 10)       /* 36xx/37xx-specific clocks */
+#define CK_443X         (1 << 11)
 
-#define CK_AM35XX       (CK_3505 | CK_3517)     /* all Sitara AM35xx */
 
+#define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
+#define CK_AM35XX       (CK_3505 | CK_3517)     /* all Sitara AM35xx */
+#define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
 
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index fef4696dcf67..8eb0adab19ea 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -49,13 +49,18 @@ struct clkops {
 /* struct clksel_rate.flags possibilities */
 #define RATE_IN_242X            (1 << 0)
 #define RATE_IN_243X            (1 << 1)
-#define RATE_IN_3XXX            (1 << 2)        /* rates common to all OMAP3 */
-#define RATE_IN_3430ES2         (1 << 3)        /* 3430ES2 rates only */
+#define RATE_IN_3430ES1         (1 << 2)        /* 3430ES1 rates only */
+#define RATE_IN_3430ES2PLUS     (1 << 3)        /* 3430 ES >= 2 rates only */
 #define RATE_IN_36XX            (1 << 4)
 #define RATE_IN_4430            (1 << 5)
 
 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
-#define RATE_IN_3430ES2PLUS     (RATE_IN_3430ES2 | RATE_IN_36XX)
+#define RATE_IN_34XX            (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
+#define RATE_IN_3XXX            (RATE_IN_34XX | RATE_IN_36XX)
+
+/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
+#define RATE_IN_3430ES2PLUS_36XX        (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
+
 
 /**
  * struct clksel_rate - register bitfield values corresponding to clk divisors
@@ -119,8 +124,7 @@ struct clksel {
  *
  * Possible values for @flags:
  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- * NO_DCO_SEL: don't program DCO (only for some J-type DPLLs)
-
+ *
  * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
  *
  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
@@ -156,6 +160,8 @@ struct dpll_data {
         u32                     autoidle_mask;
         u32                     freqsel_mask;
         u32                     idlest_mask;
+        u32                     dco_mask;
+        u32                     sddiv_mask;
         u8                      auto_recal_bit;
         u8                      recal_en_bit;
         u8                      recal_st_bit;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index a9d69a09920d..6b8088ec74af 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -27,6 +27,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
 #define __ARCH_ARM_MACH_OMAP_COMMON_H
 
+#include <linux/delay.h>
+
 #include <plat/i2c.h>
 
 struct sys_timer;
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 0cce4ca83aa0..d1c916fcf770 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -21,141 +21,15 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H
 
-/* Move omap4 specific defines to dma-44xx.h */
-#include "dma-44xx.h"
+#include <linux/platform_device.h>
 
-/* Hardware registers for omap1 */
-#define OMAP1_DMA_BASE                  (0xfffed800)
-
-#define OMAP1_DMA_GCR                   0x400
-#define OMAP1_DMA_GSCR                  0x404
-#define OMAP1_DMA_GRST                  0x408
-#define OMAP1_DMA_HW_ID                 0x442
-#define OMAP1_DMA_PCH2_ID               0x444
-#define OMAP1_DMA_PCH0_ID               0x446
-#define OMAP1_DMA_PCH1_ID               0x448
-#define OMAP1_DMA_PCHG_ID               0x44a
-#define OMAP1_DMA_PCHD_ID               0x44c
-#define OMAP1_DMA_CAPS_0_U              0x44e
-#define OMAP1_DMA_CAPS_0_L              0x450
-#define OMAP1_DMA_CAPS_1_U              0x452
-#define OMAP1_DMA_CAPS_1_L              0x454
-#define OMAP1_DMA_CAPS_2                0x456
-#define OMAP1_DMA_CAPS_3                0x458
-#define OMAP1_DMA_CAPS_4                0x45a
-#define OMAP1_DMA_PCH2_SR               0x460
-#define OMAP1_DMA_PCH0_SR               0x480
-#define OMAP1_DMA_PCH1_SR               0x482
-#define OMAP1_DMA_PCHD_SR               0x4c0
-
-/* Hardware registers for omap2 and omap3 */
-#define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
-#define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
-#define OMAP44XX_DMA4_BASE              (L4_44XX_BASE + 0x56000)
-
-#define OMAP_DMA4_REVISION              0x00
-#define OMAP_DMA4_GCR                   0x78
-#define OMAP_DMA4_IRQSTATUS_L0          0x08
-#define OMAP_DMA4_IRQSTATUS_L1          0x0c
-#define OMAP_DMA4_IRQSTATUS_L2          0x10
-#define OMAP_DMA4_IRQSTATUS_L3          0x14
-#define OMAP_DMA4_IRQENABLE_L0          0x18
-#define OMAP_DMA4_IRQENABLE_L1          0x1c
-#define OMAP_DMA4_IRQENABLE_L2          0x20
-#define OMAP_DMA4_IRQENABLE_L3          0x24
-#define OMAP_DMA4_SYSSTATUS             0x28
-#define OMAP_DMA4_OCP_SYSCONFIG         0x2c
-#define OMAP_DMA4_CAPS_0                0x64
-#define OMAP_DMA4_CAPS_2                0x6c
-#define OMAP_DMA4_CAPS_3                0x70
-#define OMAP_DMA4_CAPS_4                0x74
-
-#define OMAP1_LOGICAL_DMA_CH_COUNT      17
-#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT  32      /* REVISIT: Is this 32 + 2? */
-
-/* Common channel specific registers for omap1 */
-#define OMAP1_DMA_CH_BASE(n)            (0x40 * (n) + 0x00)
-#define OMAP1_DMA_CSDP(n)               (0x40 * (n) + 0x00)
-#define OMAP1_DMA_CCR(n)                (0x40 * (n) + 0x02)
-#define OMAP1_DMA_CICR(n)               (0x40 * (n) + 0x04)
-#define OMAP1_DMA_CSR(n)                (0x40 * (n) + 0x06)
-#define OMAP1_DMA_CEN(n)                (0x40 * (n) + 0x10)
-#define OMAP1_DMA_CFN(n)                (0x40 * (n) + 0x12)
-#define OMAP1_DMA_CSFI(n)               (0x40 * (n) + 0x14)
-#define OMAP1_DMA_CSEI(n)               (0x40 * (n) + 0x16)
-#define OMAP1_DMA_CPC(n)                (0x40 * (n) + 0x18)     /* 15xx only */
-#define OMAP1_DMA_CSAC(n)               (0x40 * (n) + 0x18)
-#define OMAP1_DMA_CDAC(n)               (0x40 * (n) + 0x1a)
-#define OMAP1_DMA_CDEI(n)               (0x40 * (n) + 0x1c)
-#define OMAP1_DMA_CDFI(n)               (0x40 * (n) + 0x1e)
-#define OMAP1_DMA_CLNK_CTRL(n)          (0x40 * (n) + 0x28)
-
-/* Common channel specific registers for omap2 */
-#define OMAP_DMA4_CH_BASE(n)            (0x60 * (n) + 0x80)
-#define OMAP_DMA4_CCR(n)                (0x60 * (n) + 0x80)
-#define OMAP_DMA4_CLNK_CTRL(n)          (0x60 * (n) + 0x84)
-#define OMAP_DMA4_CICR(n)               (0x60 * (n) + 0x88)
-#define OMAP_DMA4_CSR(n)                (0x60 * (n) + 0x8c)
-#define OMAP_DMA4_CSDP(n)               (0x60 * (n) + 0x90)
-#define OMAP_DMA4_CEN(n)                (0x60 * (n) + 0x94)
-#define OMAP_DMA4_CFN(n)                (0x60 * (n) + 0x98)
-#define OMAP_DMA4_CSEI(n)               (0x60 * (n) + 0xa4)
-#define OMAP_DMA4_CSFI(n)               (0x60 * (n) + 0xa8)
-#define OMAP_DMA4_CDEI(n)               (0x60 * (n) + 0xac)
-#define OMAP_DMA4_CDFI(n)               (0x60 * (n) + 0xb0)
-#define OMAP_DMA4_CSAC(n)               (0x60 * (n) + 0xb4)
-#define OMAP_DMA4_CDAC(n)               (0x60 * (n) + 0xb8)
-
-/* Channel specific registers only on omap1 */
-#define OMAP1_DMA_CSSA_L(n)             (0x40 * (n) + 0x08)
-#define OMAP1_DMA_CSSA_U(n)             (0x40 * (n) + 0x0a)
-#define OMAP1_DMA_CDSA_L(n)             (0x40 * (n) + 0x0c)
-#define OMAP1_DMA_CDSA_U(n)             (0x40 * (n) + 0x0e)
-#define OMAP1_DMA_COLOR_L(n)            (0x40 * (n) + 0x20)
-#define OMAP1_DMA_COLOR_U(n)            (0x40 * (n) + 0x22)
-#define OMAP1_DMA_CCR2(n)               (0x40 * (n) + 0x24)
-#define OMAP1_DMA_LCH_CTRL(n)           (0x40 * (n) + 0x2a)     /* not on 15xx */
-#define OMAP1_DMA_CCEN(n)               0
-#define OMAP1_DMA_CCFN(n)               0
-
-/* Channel specific registers only on omap2 */
-#define OMAP_DMA4_CSSA(n)               (0x60 * (n) + 0x9c)
-#define OMAP_DMA4_CDSA(n)               (0x60 * (n) + 0xa0)
-#define OMAP_DMA4_CCEN(n)               (0x60 * (n) + 0xbc)
-#define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
-#define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
-
-/* Additional registers available on OMAP4 */
-#define OMAP_DMA4_CDP(n)                (0x60 * (n) + 0xd0)
-#define OMAP_DMA4_CNDP(n)               (0x60 * (n) + 0xd4)
-#define OMAP_DMA4_CCDN(n)               (0x60 * (n) + 0xd8)
-
-/* Dummy defines to keep multi-omap compiles happy */
-#define OMAP1_DMA_REVISION              0
-#define OMAP1_DMA_IRQSTATUS_L0          0
-#define OMAP1_DMA_IRQENABLE_L0          0
-#define OMAP1_DMA_OCP_SYSCONFIG         0
-#define OMAP_DMA4_HW_ID                 0
-#define OMAP_DMA4_CAPS_0_L              0
-#define OMAP_DMA4_CAPS_0_U              0
-#define OMAP_DMA4_CAPS_1_L              0
-#define OMAP_DMA4_CAPS_1_U              0
-#define OMAP_DMA4_GSCR                  0
-#define OMAP_DMA4_CPC(n)                0
-
-#define OMAP_DMA4_LCH_CTRL(n)           0
-#define OMAP_DMA4_COLOR_L(n)            0
-#define OMAP_DMA4_COLOR_U(n)            0
-#define OMAP_DMA4_CCR2(n)               0
-#define OMAP1_DMA_CSSA(n)               0
-#define OMAP1_DMA_CDSA(n)               0
-#define OMAP_DMA4_CSSA_L(n)             0
-#define OMAP_DMA4_CSSA_U(n)             0
-#define OMAP_DMA4_CDSA_L(n)             0
-#define OMAP_DMA4_CDSA_U(n)             0
-#define OMAP1_DMA_COLOR(n)              0
+/*
+ * TODO: These dma channel defines should go away once all
+ * the omap drivers hwmod adapted.
+ */
 
-/*----------------------------------------------------------------------------*/
+/* Move omap4 specific defines to dma-44xx.h */
+#include "dma-44xx.h"
 
 /* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE              0
@@ -405,6 +279,63 @@
 #define DMA_CH_PRIO_HIGH                0x1
 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
 
+/* Errata handling */
+#define IS_DMA_ERRATA(id)               (errata & (id))
+#define SET_DMA_ERRATA(id)              (errata |= (id))
+
+#define DMA_ERRATA_IFRAME_BUFFERING     BIT(0x0)
+#define DMA_ERRATA_PARALLEL_CHANNELS    BIT(0x1)
+#define DMA_ERRATA_i378                 BIT(0x2)
+#define DMA_ERRATA_i541                 BIT(0x3)
+#define DMA_ERRATA_i88                  BIT(0x4)
+#define DMA_ERRATA_3_3                  BIT(0x5)
+#define DMA_ROMCODE_BUG                 BIT(0x6)
+
+/* Attributes for OMAP DMA Contrller */
+#define DMA_LINKED_LCH                  BIT(0x0)
+#define GLOBAL_PRIORITY                 BIT(0x1)
+#define RESERVE_CHANNEL                 BIT(0x2)
+#define IS_CSSA_32                      BIT(0x3)
+#define IS_CDSA_32                      BIT(0x4)
+#define IS_RW_PRIORITY                  BIT(0x5)
+#define ENABLE_1510_MODE                BIT(0x6)
+#define SRC_PORT                        BIT(0x7)
+#define DST_PORT                        BIT(0x8)
+#define SRC_INDEX                       BIT(0x9)
+#define DST_INDEX                       BIT(0xA)
+#define IS_BURST_ONLY4                  BIT(0xB)
+#define CLEAR_CSR_ON_READ               BIT(0xC)
+#define IS_WORD_16                      BIT(0xD)
+
+enum omap_reg_offsets {
+
+GCR,            GSCR,           GRST1,          HW_ID,
+PCH2_ID,        PCH0_ID,        PCH1_ID,        PCHG_ID,
+PCHD_ID,        CAPS_0,         CAPS_1,         CAPS_2,
+CAPS_3,         CAPS_4,         PCH2_SR,        PCH0_SR,
+PCH1_SR,        PCHD_SR,        REVISION,       IRQSTATUS_L0,
+IRQSTATUS_L1,   IRQSTATUS_L2,   IRQSTATUS_L3,   IRQENABLE_L0,
+IRQENABLE_L1,   IRQENABLE_L2,   IRQENABLE_L3,   SYSSTATUS,
+OCP_SYSCONFIG,
+
+/* omap1+ specific */
+CPC, CCR2, LCH_CTRL,
+
+/* Common registers for all omap's */
+CSDP,           CCR,            CICR,           CSR,
+CEN,            CFN,            CSFI,           CSEI,
+CSAC,           CDAC,           CDEI,
+CDFI,           CLNK_CTRL,
+
+/* Channel specific registers */
+CSSA,           CDSA,           COLOR,
+CCEN,           CCFN,
+
+/* omap3630 and omap4 specific */
+CDP,            CNDP,           CCDN,
+
+};
+
 enum omap_dma_burst_mode {
         OMAP_DMA_DATA_BURST_DIS = 0,
         OMAP_DMA_DATA_BURST_4,
@@ -470,6 +401,41 @@ struct omap_dma_channel_params {
 #endif
 };
 
+struct omap_dma_lch {
+        int next_lch;
+        int dev_id;
+        u16 saved_csr;
+        u16 enabled_irqs;
+        const char *dev_name;
+        void (*callback)(int lch, u16 ch_status, void *data);
+        void *data;
+        long flags;
+        /* required for Dynamic chaining */
+        int prev_linked_ch;
+        int next_linked_ch;
+        int state;
+        int chain_id;
+        int status;
+};
+
+struct omap_dma_dev_attr {
+        u32 dev_caps;
+        u16 lch_count;
+        u16 chan_count;
+        struct omap_dma_lch *chan;
+};
+
+/* System DMA platform data structure */
+struct omap_system_dma_plat_info {
+        struct omap_dma_dev_attr *dma_attr;
+        u32 errata;
+        void (*disable_irq_lch)(int lch);
+        void (*show_dma_caps)(void);
+        void (*clear_lch_regs)(int lch);
+        void (*clear_dma)(int lch);
+        void (*dma_write)(u32 val, int reg, int lch);
+        u32 (*dma_read)(int reg, int lch);
+};
 
 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
diff --git a/arch/arm/plat-omap/include/plat/fpga.h b/arch/arm/plat-omap/include/plat/fpga.h
index f1864a652f7a..ae39bcb3f5ba 100644
--- a/arch/arm/plat-omap/include/plat/fpga.h
+++ b/arch/arm/plat-omap/include/plat/fpga.h
@@ -19,11 +19,7 @@
 #ifndef __ASM_ARCH_OMAP_FPGA_H
 #define __ASM_ARCH_OMAP_FPGA_H
 
-#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
 extern void omap1510_fpga_init_irq(void);
-#else
-#define omap1510_fpga_init_irq()        (0)
-#endif
 
 #define fpga_read(reg)                  __raw_readb(reg)
 #define fpga_write(val, reg)            __raw_writeb(val, reg)
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index de1c604962eb..d6f9fa0f62af 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -27,26 +27,15 @@
 #define __ASM_ARCH_OMAP_GPIO_H
 
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <mach/irqs.h>
 
 #define OMAP1_MPUIO_BASE                        0xfffb5000
 
-#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
-
-#define OMAP_MPUIO_INPUT_LATCH          0x00
-#define OMAP_MPUIO_OUTPUT               0x02
-#define OMAP_MPUIO_IO_CNTL              0x04
-#define OMAP_MPUIO_KBR_LATCH            0x08
-#define OMAP_MPUIO_KBC                  0x0a
-#define OMAP_MPUIO_GPIO_EVENT_MODE      0x0c
-#define OMAP_MPUIO_GPIO_INT_EDGE        0x0e
-#define OMAP_MPUIO_KBD_INT              0x10
-#define OMAP_MPUIO_GPIO_INT             0x12
-#define OMAP_MPUIO_KBD_MASKIT           0x14
-#define OMAP_MPUIO_GPIO_MASKIT          0x16
-#define OMAP_MPUIO_GPIO_DEBOUNCING      0x18
-#define OMAP_MPUIO_LATCH                0x1a
-#else
+/*
+ * These are the omap15xx/16xx offsets. The omap7xx offset are
+ * OMAP_MPUIO_ / 2 offsets below.
+ */
 #define OMAP_MPUIO_INPUT_LATCH          0x00
 #define OMAP_MPUIO_OUTPUT               0x04
 #define OMAP_MPUIO_IO_CNTL              0x08
@@ -60,7 +49,6 @@
 #define OMAP_MPUIO_GPIO_MASKIT          0x2c
 #define OMAP_MPUIO_GPIO_DEBOUNCING      0x30
 #define OMAP_MPUIO_LATCH                0x34
-#endif
 
 #define OMAP34XX_NR_GPIOS               6
 
@@ -71,8 +59,30 @@
                                  IH_MPUIO_BASE + ((nr) & 0x0f) : \
                                  IH_GPIO_BASE + (nr))
 
-extern int omap_gpio_init(void);        /* Call from board init only */
-extern void omap2_gpio_prepare_for_idle(int power_state);
+#define METHOD_MPUIO            0
+#define METHOD_GPIO_1510        1
+#define METHOD_GPIO_1610        2
+#define METHOD_GPIO_7XX         3
+#define METHOD_GPIO_24XX        5
+#define METHOD_GPIO_44XX        6
+
+struct omap_gpio_dev_attr {
+        int bank_width;         /* GPIO bank width */
+        bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
+};
+
+struct omap_gpio_platform_data {
+        u16 virtual_irq_start;
+        int bank_type;
+        int bank_width;         /* GPIO bank width */
+        int bank_stride;        /* Only needed for omap1 MPUIO */
+        bool dbck_flag;         /* dbck required or not - True for OMAP3&4 */
+};
+
+/* TODO: Analyze removing gpio_bank_count usage from driver code */
+extern int gpio_bank_count;
+
+extern void omap2_gpio_prepare_for_idle(int off_mode);
 extern void omap2_gpio_resume_after_idle(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 9fd99b9e40ab..85ded598853e 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -80,12 +80,12 @@
 #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
 
 /*
- * Note that all values in this struct are in nanoseconds, while
- * the register values are in gpmc_fck cycles.
+ * Note that all values in this struct are in nanoseconds except sync_clk
+ * (which is in picoseconds), while the register values are in gpmc_fck cycles.
  */
 struct gpmc_timings {
-        /* Minimum clock period for synchronous mode */
-        u16 sync_clk;
+        /* Minimum clock period for synchronous mode (in picoseconds) */
+        u32 sync_clk;
 
         /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
         u16 cs_on;              /* Assertion time */
@@ -117,6 +117,7 @@ struct gpmc_timings {
 };
 
 extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
+extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
 extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
 extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
 extern unsigned long gpmc_get_fclk_period(void);
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 36a0befd6168..878d632c4092 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -36,6 +36,19 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
 }
 #endif
 
+/**
+ * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
+ * @fifo_depth: total controller FIFO size (in bytes)
+ * @flags: differences in hardware support capability
+ *
+ * @fifo_depth represents what exists on the hardware, not what is
+ * actually configured at runtime by the device driver.
+ */
+struct omap_i2c_dev_attr {
+        u8      fifo_depth;
+        u8      flags;
+};
+
 void __init omap1_i2c_mux_pins(int bus_id);
 void __init omap2_i2c_mux_pins(int bus_id);
 
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 128b549c2796..ef4106c13183 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -291,11 +291,12 @@ static inline void omap44xx_map_common_io(void)
 }
 #endif
 
-extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
-                                 struct omap_sdrc_params *sdrc_cs1);
+extern void omap2_init_common_infrastructure(void);
+extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
+                                      struct omap_sdrc_params *sdrc_cs1);
 
-#define __arch_ioremap(p,s,t)   omap_ioremap(p,s,t)
-#define __arch_iounmap(v)       omap_iounmap(v)
+#define __arch_ioremap  omap_ioremap
+#define __arch_iounmap  omap_iounmap
 
 void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
 void omap_iounmap(volatile void __iomem *addr);
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 33c7d41cb6a5..69230d685538 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -50,6 +50,8 @@ struct iommu {
         int (*isr)(struct iommu *obj);
 
         void *ctx; /* iommu context: registres saved area */
+        u32 da_start;
+        u32 da_end;
 };
 
 struct cr_regs {
@@ -103,6 +105,8 @@ struct iommu_platform_data {
         const char *name;
         const char *clk_name;
         const int nr_tlb_entries;
+        u32 da_start;
+        u32 da_end;
 };
 
 #if defined(CONFIG_ARCH_OMAP1)
@@ -152,6 +156,7 @@ extern void flush_iotlb_all(struct iommu *obj);
 extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
 extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
 
+extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
 extern struct iommu *iommu_get(const char *name);
 extern void iommu_put(struct iommu *obj);
 
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 65e20a686713..2910de921c52 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -77,7 +77,7 @@
 /*
  * OMAP-1610 specific IRQ numbers for interrupt handler 1
  */
-#define INT_1610_IH2_IRQ        0
+#define INT_1610_IH2_IRQ        INT_1510_IH2_IRQ
 #define INT_1610_IH2_FIQ        2
 #define INT_1610_McBSP2_TX      4
 #define INT_1610_McBSP2_RX      5
diff --git a/arch/arm/plat-omap/include/plat/keypad.h b/arch/arm/plat-omap/include/plat/keypad.h
index 3ae52ccc793c..793ce9d53294 100644
--- a/arch/arm/plat-omap/include/plat/keypad.h
+++ b/arch/arm/plat-omap/include/plat/keypad.h
@@ -10,16 +10,18 @@
 #ifndef ASMARM_ARCH_KEYPAD_H
 #define ASMARM_ARCH_KEYPAD_H
 
-#warning: Please update the board to use matrix_keypad.h instead
+#ifndef CONFIG_ARCH_OMAP1
+#warning Please update the board to use matrix-keypad driver
+#endif
+#include <linux/input/matrix_keypad.h>
 
 struct omap_kp_platform_data {
         int rows;
         int cols;
-        int *keymap;
-        unsigned int keymapsize;
-        unsigned int rep:1;
+        const struct matrix_keymap_data *keymap_data;
+        bool rep;
         unsigned long delay;
-        unsigned int dbounce:1;
+        bool dbounce;
         /* specific to OMAP242x*/
         unsigned int *row_gpios;
         unsigned int *col_gpios;
@@ -28,18 +30,21 @@ struct omap_kp_platform_data {
 /* Group (0..3) -- when multiple keys are pressed, only the
  * keys pressed in the same group are considered as pressed. This is
  * in order to workaround certain crappy HW designs that produce ghost
- * keypresses. */
-#define GROUP_0         (0 << 16)
-#define GROUP_1         (1 << 16)
-#define GROUP_2         (2 << 16)
-#define GROUP_3         (3 << 16)
+ * keypresses. Two free bits, not used by neither row/col nor keynum,
+ * must be available for use as group bits. The below GROUP_SHIFT
+ * macro definition is based on some prior knowledge of the
+ * matrix_keypad defined KEY() macro internals.
+ */
+#define GROUP_SHIFT     14
+#define GROUP_0         (0 << GROUP_SHIFT)
+#define GROUP_1         (1 << GROUP_SHIFT)
+#define GROUP_2         (2 << GROUP_SHIFT)
+#define GROUP_3         (3 << GROUP_SHIFT)
 #define GROUP_MASK      GROUP_3
+#if KEY_MAX & GROUP_MASK
+#error Group bits in conflict with keynum bits
+#endif
 
-#define KEY_PERSISTENT          0x00800000
-#define KEYNUM_MASK             0x00EFFFFF
-#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
-#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
-                                                KEY_PERSISTENT)
 
 #endif
 
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
new file mode 100644
index 000000000000..5e1949375422
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
+
+/* L4 CORE */
+#define OMAP3_L4_CORE_FW_I2C1_REGION                            21
+#define OMAP3_L4_CORE_FW_I2C1_TA_REGION                         22
+#define OMAP3_L4_CORE_FW_I2C2_REGION                            23
+#define OMAP3_L4_CORE_FW_I2C2_TA_REGION                         24
+#define OMAP3_L4_CORE_FW_I2C3_REGION                            73
+#define OMAP3_L4_CORE_FW_I2C3_TA_REGION                         74
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index 997656552109..cc3921e9059c 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -46,8 +46,8 @@ struct omap_mbox_queue {
         struct kfifo            fifo;
         struct work_struct      work;
         struct tasklet_struct   tasklet;
-        int     (*callback)(void *);
         struct omap_mbox        *mbox;
+        bool full;
 };
 
 struct omap_mbox {
@@ -57,13 +57,15 @@ struct omap_mbox {
         struct omap_mbox_ops    *ops;
         struct device           *dev;
         void                    *priv;
+        int                     use_count;
+        struct blocking_notifier_head   notifier;
 };
 
 int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
 void omap_mbox_init_seq(struct omap_mbox *);
 
-struct omap_mbox *omap_mbox_get(const char *);
-void omap_mbox_put(struct omap_mbox *);
+struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
+void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
 
 int omap_mbox_register(struct device *parent, struct omap_mbox **);
 int omap_mbox_unregister(void);
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h
index d5306bee44b2..f8d922fb5584 100644
--- a/arch/arm/plat-omap/include/plat/memory.h
+++ b/arch/arm/plat-omap/include/plat/memory.h
@@ -61,17 +61,17 @@
 #define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
 #define is_lbus_device(dev)     (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
 
-#define __arch_page_to_dma(dev, page)   \
-        ({ dma_addr_t __dma = page_to_phys(page); \
+#define __arch_pfn_to_dma(dev, pfn)     \
+        ({ dma_addr_t __dma = __pfn_to_phys(pfn); \
            if (is_lbus_device(dev)) \
                 __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
            __dma; })
 
-#define __arch_dma_to_page(dev, addr)   \
+#define __arch_dma_to_pfn(dev, addr)    \
         ({ dma_addr_t __dma = addr;                             \
            if (is_lbus_device(dev))                             \
                 __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET;      \
-           phys_to_page(__dma);                                 \
+           __phys_to_pfn(__dma);                                \
         })
 
 #define __arch_dma_to_virt(dev, addr)   ({ (void *) (is_lbus_device(dev) ? \
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index 728fbb9dd549..c0a752053039 100644
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
@@ -17,26 +17,7 @@
 #include <linux/device.h>
 #include <linux/cpufreq.h>
 #include <linux/clk.h>
-
-#include "powerdomain.h"
-
-/**
- * struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
- * @rate: target clock rate
- * @opp_id: OPP ID
- * @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
- *
- * Operating performance point data.  Can vary by OMAP chip and board.
- */
-struct omap_opp {
-        unsigned long rate;
-        u8 opp_id;
-        u16 min_vdd;
-};
-
-extern struct omap_opp *mpu_opps;
-extern struct omap_opp *dsp_opps;
-extern struct omap_opp *l3_opps;
+#include <linux/opp.h>
 
 /*
  * agent_id values for use with omap_pm_set_min_bus_tput():
@@ -59,9 +40,11 @@ extern struct omap_opp *l3_opps;
  * framework starts.  The "_if_" is to avoid name collisions with the
  * PM idle-loop code.
  */
-int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
-                                 struct omap_opp *dsp_opp_table,
-                                 struct omap_opp *l3_opp_table);
+#ifdef CONFIG_OMAP_PM_NONE
+#define omap_pm_if_early_init() 0
+#else
+int __init omap_pm_if_early_init(void);
+#endif
 
 /**
  * omap_pm_if_init - OMAP PM init code called after clock fw init
@@ -69,7 +52,11 @@ int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
  * The main initialization code.  OPP tables are passed in here.  The
  * "_if_" is to avoid name collisions with the PM idle-loop code.
  */
+#ifdef CONFIG_OMAP_PM_NONE
+#define omap_pm_if_init() 0
+#else
 int __init omap_pm_if_init(void);
+#endif
 
 /**
  * omap_pm_if_exit - OMAP PM exit code
@@ -363,9 +350,11 @@ unsigned long omap_pm_cpu_get_freq(void);
  * driver must restore device context.   If the number of context losses
  * exceeds the maximum positive integer, the function will wrap to 0 and
  * continue counting.  Returns the number of context losses for this device,
- * or -EINVAL upon error.
+ * or zero upon error.
  */
-int omap_pm_get_dev_context_loss_count(struct device *dev);
+u32 omap_pm_get_dev_context_loss_count(struct device *dev);
 
+void omap_pm_enable_off_mode(void);
+void omap_pm_disable_off_mode(void);
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index c8dae02f0704..2682043f5a5b 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -22,7 +22,7 @@
 
 #include <plat/mux.h>
 
-#define DRIVER_NAME     "omap-hsuart"
+#define DRIVER_NAME     "omap_uart"
 
 /*
  * Use tty device name as ttyO, [O -> OMAP]
@@ -31,20 +31,8 @@
  */
 #define OMAP_SERIAL_NAME        "ttyO"
 
-#define OMAP_MDR1_DISABLE       0x07
-#define OMAP_MDR1_MODE13X       0x03
-#define OMAP_MDR1_MODE16X       0x00
 #define OMAP_MODE13X_SPEED      230400
 
-/*
- * LCR = 0XBF: Switch to Configuration Mode B.
- * In configuration mode b allow access
- * to EFR,DLL,DLH.
- * Reference OMAP TRM Chapter 17
- * Section: 1.4.3 Mode Selection
- */
-#define OMAP_UART_LCR_CONF_MDB  0XBF
-
 /* WER = 0x7F
  * Enable module level wakeup in WER reg
  */
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index 8b3f12ff5cbc..ea2b8a6306e7 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -52,5 +52,10 @@
 #define OMAP4_MMU1_BASE                 0x55082000
 #define OMAP4_MMU2_BASE                 0x4A066000
 
+#define OMAP44XX_USBTLL_BASE            (L4_44XX_BASE + 0x62000)
+#define OMAP44XX_UHH_CONFIG_BASE        (L4_44XX_BASE + 0x64000)
+#define OMAP44XX_HSUSB_OHCI_BASE        (L4_44XX_BASE + 0x64800)
+#define OMAP44XX_HSUSB_EHCI_BASE        (L4_44XX_BASE + 0x64C00)
+
 #endif /* __ASM_ARCH_OMAP44XX_H */
 
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 28e2d1a78433..e4c349ff9fd8 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -107,6 +107,7 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od);
 int omap_device_align_pm_lat(struct platform_device *pdev,
                              u32 new_wakeup_lat_limit);
 struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
+u32 omap_device_get_context_loss_count(struct platform_device *pdev);
 
 /* Other */
 
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 7eaa8edf3b14..6864a997f2ca 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -23,7 +23,7 @@
  * - add pinmuxing
  * - init_conn_id_bit (CONNID_BIT_VECTOR)
  * - implement default hwmod SMS/SDRC flags?
- * - remove unused fields
+ * - move Linux-specific data ("non-ROM data") out
  *
  */
 #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
@@ -32,8 +32,9 @@
 #include <linux/kernel.h>
 #include <linux/list.h>
 #include <linux/ioport.h>
-#include <linux/mutex.h>
+#include <linux/spinlock.h>
 #include <plat/cpu.h>
+#include <plat/voltage.h>
 
 struct omap_device;
 
@@ -76,6 +77,20 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
 #define HWMOD_IDLEMODE_FORCE            (1 << 0)
 #define HWMOD_IDLEMODE_NO               (1 << 1)
 #define HWMOD_IDLEMODE_SMART            (1 << 2)
+/* Slave idle mode flag only */
+#define HWMOD_IDLEMODE_SMART_WKUP       (1 << 3)
+
+/**
+ * struct omap_hwmod_mux_info - hwmod specific mux configuration
+ * @pads:              array of omap_device_pad entries
+ * @nr_pads:           number of omap_device_pad entries
+ *
+ * Note that this is currently built during init as needed.
+ */
+struct omap_hwmod_mux_info {
+        int                             nr_pads;
+        struct omap_device_pad          *pads;
+};
 
 /**
  * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
@@ -159,7 +174,7 @@ struct omap_hwmod_omap2_firewall {
  * ADDR_MAP_ON_INIT: Map this address space during omap_hwmod init.
  * ADDR_TYPE_RT: Address space contains module register target data.
  */
-#define ADDR_MAP_ON_INIT        (1 << 0)
+#define ADDR_MAP_ON_INIT        (1 << 0)        /* XXX does not belong */
 #define ADDR_TYPE_RT            (1 << 1)
 
 /**
@@ -200,8 +215,6 @@ struct omap_hwmod_addr_space {
  * @fw: interface firewall data
  * @addr_cnt: ARRAY_SIZE(@addr)
  * @width: OCP data width
- * @thread_cnt: number of threads
- * @max_burst_len: maximum burst length in @width sized words (0 if unlimited)
  * @user: initiators using this interface (see OCP_USER_* macros above)
  * @flags: OCP interface flags (see OCPIF_* macros above)
  *
@@ -221,8 +234,6 @@ struct omap_hwmod_ocp_if {
         }                               fw;
         u8                              addr_cnt;
         u8                              width;
-        u8                              thread_cnt;
-        u8                              max_burst_len;
         u8                              user;
         u8                              flags;
 };
@@ -231,11 +242,12 @@ struct omap_hwmod_ocp_if {
 /* Macros for use in struct omap_hwmod_sysconfig */
 
 /* Flags for use in omap_hwmod_sysconfig.idlemodes */
-#define MASTER_STANDBY_SHIFT    2
+#define MASTER_STANDBY_SHIFT    4
 #define SLAVE_IDLE_SHIFT        0
 #define SIDLE_FORCE             (HWMOD_IDLEMODE_FORCE << SLAVE_IDLE_SHIFT)
 #define SIDLE_NO                (HWMOD_IDLEMODE_NO << SLAVE_IDLE_SHIFT)
 #define SIDLE_SMART             (HWMOD_IDLEMODE_SMART << SLAVE_IDLE_SHIFT)
+#define SIDLE_SMART_WKUP        (HWMOD_IDLEMODE_SMART_WKUP << SLAVE_IDLE_SHIFT)
 #define MSTANDBY_FORCE          (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
 #define MSTANDBY_NO             (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
 #define MSTANDBY_SMART          (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
@@ -357,14 +369,14 @@ struct omap_hwmod_omap4_prcm {
  * HWMOD_SWSUP_MSTDBY: omap_hwmod code should manually bring module in and out
  *     of standby, rather than relying on module smart-standby
  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
- *     SDRAM controller, etc.
+ *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
- *     controller, etc.
+ *     controller, etc. XXX probably belongs outside the main hwmod file
  * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
  *     when module is enabled, rather than the default, which is to
  *     enable autoidle
  * HWMOD_SET_DEFAULT_CLOCKACT: program CLOCKACTIVITY bits at startup
- * HWMOD_NO_IDLEST : this module does not have idle status - this is the case
+ * HWMOD_NO_IDLEST: this module does not have idle status - this is the case
  *     only for few initiator modules on OMAP2 & 3.
  * HWMOD_CONTROL_OPT_CLKS_IN_RESET: Enable all optional clocks during reset.
  *     This is needed for devices like DSS that require optional clocks enabled
@@ -415,14 +427,31 @@ struct omap_hwmod_omap4_prcm {
  * @name: name of the hwmod_class
  * @sysc: device SYSCONFIG/SYSSTATUS register data
  * @rev: revision of the IP class
+ * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
+ * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
  *
  * Represent the class of a OMAP hardware "modules" (e.g. timer,
  * smartreflex, gpio, uart...)
+ *
+ * @pre_shutdown is a function that will be run immediately before
+ * hwmod clocks are disabled, etc.  It is intended for use for hwmods
+ * like the MPU watchdog, which cannot be disabled with the standard
+ * omap_hwmod_shutdown().  The function should return 0 upon success,
+ * or some negative error upon failure.  Returning an error will cause
+ * omap_hwmod_shutdown() to abort the device shutdown and return an
+ * error.
+ *
+ * If @reset is defined, then the function it points to will be
+ * executed in place of the standard hwmod _reset() code in
+ * mach-omap2/omap_hwmod.c.  This is needed for IP blocks which have
+ * unusual reset sequences - usually processor IP blocks like the IVA.
  */
 struct omap_hwmod_class {
         const char                              *name;
         struct omap_hwmod_class_sysconfig       *sysc;
         u32                                     rev;
+        int                                     (*pre_shutdown)(struct omap_hwmod *oh);
+        int                                     (*reset)(struct omap_hwmod *oh);
 };
 
 /**
@@ -436,14 +465,14 @@ struct omap_hwmod_class {
  * @main_clk: main clock: OMAP clock name
  * @_clk: pointer to the main struct clk (filled in at runtime)
  * @opt_clks: other device clocks that drivers can request (0..*)
+ * @vdd_name: voltage domain name
+ * @voltdm: pointer to voltage domain (filled in at runtime)
  * @masters: ptr to array of OCP ifs that this hwmod can initiate on
  * @slaves: ptr to array of OCP ifs that this hwmod can respond on
  * @dev_attr: arbitrary device attributes that can be passed to the driver
  * @_sysc_cache: internal-use hwmod flags
  * @_mpu_rt_va: cached register target start address (internal use)
  * @_mpu_port_index: cached MPU register target slave ID (internal use)
- * @msuspendmux_reg_id: CONTROL_MSUSPENDMUX register ID (1-6)
- * @msuspendmux_shift: CONTROL_MSUSPENDMUX register bit shift
  * @mpu_irqs_cnt: number of @mpu_irqs
  * @sdma_reqs_cnt: number of @sdma_reqs
  * @opt_clks_cnt: number of @opt_clks
@@ -452,9 +481,10 @@ struct omap_hwmod_class {
  * @response_lat: device OCP response latency (in interface clock cycles)
  * @_int_flags: internal-use hwmod flags
  * @_state: internal-use hwmod state
+ * @_postsetup_state: internal-use state to leave the hwmod in after _setup()
  * @flags: hwmod flags (documented below)
  * @omap_chip: OMAP chips this hwmod is present on
- * @_mutex: mutex serializing operations on this hwmod
+ * @_lock: spinlock serializing operations on this hwmod
  * @node: list node for hwmod list (internal use)
  *
  * @main_clk refers to this module's "main clock," which for our
@@ -469,6 +499,7 @@ struct omap_hwmod {
         const char                      *name;
         struct omap_hwmod_class         *class;
         struct omap_device              *od;
+        struct omap_hwmod_mux_info      *mux;
         struct omap_hwmod_irq_info      *mpu_irqs;
         struct omap_hwmod_dma_info      *sdma_reqs;
         struct omap_hwmod_rst_info      *rst_lines;
@@ -479,17 +510,17 @@ struct omap_hwmod {
         const char                      *main_clk;
         struct clk                      *_clk;
         struct omap_hwmod_opt_clk       *opt_clks;
+        char                            *vdd_name;
+        struct voltagedomain            *voltdm;
         struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
         struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
         void                            *dev_attr;
         u32                             _sysc_cache;
         void __iomem                    *_mpu_rt_va;
-        struct mutex                    _mutex;
+        spinlock_t                      _lock;
         struct list_head                node;
         u16                             flags;
         u8                              _mpu_port_index;
-        u8                              msuspendmux_reg_id;
-        u8                              msuspendmux_shift;
         u8                              response_lat;
         u8                              mpu_irqs_cnt;
         u8                              sdma_reqs_cnt;
@@ -500,16 +531,15 @@ struct omap_hwmod {
         u8                              hwmods_cnt;
         u8                              _int_flags;
         u8                              _state;
+        u8                              _postsetup_state;
         const struct omap_chip_id       omap_chip;
 };
 
 int omap_hwmod_init(struct omap_hwmod **ohs);
-int omap_hwmod_register(struct omap_hwmod *oh);
-int omap_hwmod_unregister(struct omap_hwmod *oh);
 struct omap_hwmod *omap_hwmod_lookup(const char *name);
 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
                         void *data);
-int omap_hwmod_late_init(u8 skip_setup_idle);
+int omap_hwmod_late_init(void);
 
 int omap_hwmod_enable(struct omap_hwmod *oh);
 int _omap_hwmod_enable(struct omap_hwmod *oh);
@@ -556,6 +586,9 @@ int omap_hwmod_for_each_by_class(const char *classname,
                                            void *user),
                                  void *user);
 
+int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
+u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
+
 /*
  * Chip variant-specific hwmod init routines - XXX should be converted
  * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h
index ab77442e42ab..2fdf8c80d390 100644
--- a/arch/arm/plat-omap/include/plat/prcm.h
+++ b/arch/arm/plat-omap/include/plat/prcm.h
@@ -18,6 +18,10 @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * XXX This file is deprecated.  The PRCM is an OMAP2+-only subsystem,
+ * so this file doesn't belong in plat-omap/include/plat.  Please
+ * do not add anything new to this file.
  */
 
 #ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
@@ -28,22 +32,6 @@ void omap_prcm_arch_reset(char mode, const char *cmd);
 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
                          const char *name);
 
-#define START_PADCONF_SAVE 0x2
-#define PADCONF_SAVE_DONE  0x1
-
-void omap3_prcm_save_context(void);
-void omap3_prcm_restore_context(void);
-
-u32 prm_read_mod_reg(s16 module, u16 idx);
-void prm_write_mod_reg(u32 val, s16 module, u16 idx);
-u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
-u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask);
-u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
-u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
-u32 cm_read_mod_reg(s16 module, u16 idx);
-void cm_write_mod_reg(u32 val, s16 module, u16 idx);
-u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
-
 #endif
 
 
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index 19145f5c32ba..cec5d56db2eb 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -93,9 +93,12 @@
                         })
 
 #ifndef __ASSEMBLER__
+
+struct omap_board_data;
+
 extern void __init omap_serial_early_init(void);
 extern void omap_serial_init(void);
-extern void omap_serial_init_port(int port);
+extern void omap_serial_init_port(struct omap_board_data *bdata);
 extern int omap_uart_can_sleep(void);
 extern void omap_uart_check_wakeup(void);
 extern void omap_uart_prepare_suspend(void);
diff --git a/arch/arm/plat-omap/include/plat/smartreflex.h b/arch/arm/plat-omap/include/plat/smartreflex.h
new file mode 100644
index 000000000000..6568c885f37a
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/smartreflex.h
@@ -0,0 +1,245 @@
+/*
+ * OMAP Smartreflex Defines and Routines
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Kalle Jokiniemi
+ *
+ * Copyright (C) 2007 Texas Instruments, Inc.
+ * Lesly A M <x0080970@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
+#define __ASM_ARM_OMAP_SMARTREFLEX_H
+
+#include <linux/platform_device.h>
+#include <plat/voltage.h>
+
+/*
+ * Different Smartreflex IPs version. The v1 is the 65nm version used in
+ * OMAP3430. The v2 is the update for the 45nm version of the IP
+ * used in OMAP3630 and OMAP4430
+ */
+#define SR_TYPE_V1      1
+#define SR_TYPE_V2      2
+
+/* SMART REFLEX REG ADDRESS OFFSET */
+#define SRCONFIG                0x00
+#define SRSTATUS                0x04
+#define SENVAL                  0x08
+#define SENMIN                  0x0C
+#define SENMAX                  0x10
+#define SENAVG                  0x14
+#define AVGWEIGHT               0x18
+#define NVALUERECIPROCAL        0x1c
+#define SENERROR_V1             0x20
+#define ERRCONFIG_V1            0x24
+#define IRQ_EOI                 0x20
+#define IRQSTATUS_RAW           0x24
+#define IRQSTATUS               0x28
+#define IRQENABLE_SET           0x2C
+#define IRQENABLE_CLR           0x30
+#define SENERROR_V2             0x34
+#define ERRCONFIG_V2            0x38
+
+/* Bit/Shift Positions */
+
+/* SRCONFIG */
+#define SRCONFIG_ACCUMDATA_SHIFT        22
+#define SRCONFIG_SRCLKLENGTH_SHIFT      12
+#define SRCONFIG_SENNENABLE_V1_SHIFT    5
+#define SRCONFIG_SENPENABLE_V1_SHIFT    3
+#define SRCONFIG_SENNENABLE_V2_SHIFT    1
+#define SRCONFIG_SENPENABLE_V2_SHIFT    0
+#define SRCONFIG_CLKCTRL_SHIFT          0
+
+#define SRCONFIG_ACCUMDATA_MASK         (0x3ff << 22)
+
+#define SRCONFIG_SRENABLE               BIT(11)
+#define SRCONFIG_SENENABLE              BIT(10)
+#define SRCONFIG_ERRGEN_EN              BIT(9)
+#define SRCONFIG_MINMAXAVG_EN           BIT(8)
+#define SRCONFIG_DELAYCTRL              BIT(2)
+
+/* AVGWEIGHT */
+#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT   2
+#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT   0
+
+/* NVALUERECIPROCAL */
+#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
+#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
+#define NVALUERECIPROCAL_RNSENP_SHIFT   8
+#define NVALUERECIPROCAL_RNSENN_SHIFT   0
+
+/* ERRCONFIG */
+#define ERRCONFIG_ERRWEIGHT_SHIFT       16
+#define ERRCONFIG_ERRMAXLIMIT_SHIFT     8
+#define ERRCONFIG_ERRMINLIMIT_SHIFT     0
+
+#define SR_ERRWEIGHT_MASK               (0x07 << 16)
+#define SR_ERRMAXLIMIT_MASK             (0xff << 8)
+#define SR_ERRMINLIMIT_MASK             (0xff << 0)
+
+#define ERRCONFIG_VPBOUNDINTEN_V1       BIT(31)
+#define ERRCONFIG_VPBOUNDINTST_V1       BIT(30)
+#define ERRCONFIG_MCUACCUMINTEN         BIT(29)
+#define ERRCONFIG_MCUACCUMINTST         BIT(28)
+#define ERRCONFIG_MCUVALIDINTEN         BIT(27)
+#define ERRCONFIG_MCUVALIDINTST         BIT(26)
+#define ERRCONFIG_MCUBOUNDINTEN         BIT(25)
+#define ERRCONFIG_MCUBOUNDINTST         BIT(24)
+#define ERRCONFIG_MCUDISACKINTEN        BIT(23)
+#define ERRCONFIG_VPBOUNDINTST_V2       BIT(23)
+#define ERRCONFIG_MCUDISACKINTST        BIT(22)
+#define ERRCONFIG_VPBOUNDINTEN_V2       BIT(22)
+
+#define ERRCONFIG_STATUS_V1_MASK        (ERRCONFIG_VPBOUNDINTST_V1 | \
+                                        ERRCONFIG_MCUACCUMINTST | \
+                                        ERRCONFIG_MCUVALIDINTST | \
+                                        ERRCONFIG_MCUBOUNDINTST | \
+                                        ERRCONFIG_MCUDISACKINTST)
+/* IRQSTATUS */
+#define IRQSTATUS_MCUACCUMINT           BIT(3)
+#define IRQSTATUS_MCVALIDINT            BIT(2)
+#define IRQSTATUS_MCBOUNDSINT           BIT(1)
+#define IRQSTATUS_MCUDISABLEACKINT      BIT(0)
+
+/* IRQENABLE_SET and IRQENABLE_CLEAR */
+#define IRQENABLE_MCUACCUMINT           BIT(3)
+#define IRQENABLE_MCUVALIDINT           BIT(2)
+#define IRQENABLE_MCUBOUNDSINT          BIT(1)
+#define IRQENABLE_MCUDISABLEACKINT      BIT(0)
+
+/* Common Bit values */
+
+#define SRCLKLENGTH_12MHZ_SYSCLK        0x3c
+#define SRCLKLENGTH_13MHZ_SYSCLK        0x41
+#define SRCLKLENGTH_19MHZ_SYSCLK        0x60
+#define SRCLKLENGTH_26MHZ_SYSCLK        0x82
+#define SRCLKLENGTH_38MHZ_SYSCLK        0xC0
+
+/*
+ * 3430 specific values. Maybe these should be passed from board file or
+ * pmic structures.
+ */
+#define OMAP3430_SR_ACCUMDATA           0x1f4
+
+#define OMAP3430_SR1_SENPAVGWEIGHT      0x03
+#define OMAP3430_SR1_SENNAVGWEIGHT      0x03
+
+#define OMAP3430_SR2_SENPAVGWEIGHT      0x01
+#define OMAP3430_SR2_SENNAVGWEIGHT      0x01
+
+#define OMAP3430_SR_ERRWEIGHT           0x04
+#define OMAP3430_SR_ERRMAXLIMIT         0x02
+
+/**
+ * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
+ *                              pmic specific info to smartreflex driver
+ *
+ * @sr_pmic_init:       API to initialize smartreflex on the PMIC side.
+ */
+struct omap_sr_pmic_data {
+        void (*sr_pmic_init) (void);
+};
+
+#ifdef CONFIG_OMAP_SMARTREFLEX
+/*
+ * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
+ * The smartreflex class driver should pass the class type.
+ * Should be used to populate the class_type field of the
+ * omap_smartreflex_class_data structure.
+ */
+#define SR_CLASS1       0x1
+#define SR_CLASS2       0x2
+#define SR_CLASS3       0x3
+
+/**
+ * struct omap_sr_class_data - Smartreflex class driver info
+ *
+ * @enable:             API to enable a particular class smaartreflex.
+ * @disable:            API to disable a particular class smartreflex.
+ * @configure:          API to configure a particular class smartreflex.
+ * @notify:             API to notify the class driver about an event in SR.
+ *                      Not needed for class3.
+ * @notify_flags:       specify the events to be notified to the class driver
+ * @class_type:         specify which smartreflex class.
+ *                      Can be used by the SR driver to take any class
+ *                      based decisions.
+ */
+struct omap_sr_class_data {
+        int (*enable)(struct voltagedomain *voltdm);
+        int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
+        int (*configure)(struct voltagedomain *voltdm);
+        int (*notify)(struct voltagedomain *voltdm, u32 status);
+        u8 notify_flags;
+        u8 class_type;
+};
+
+/**
+ * struct omap_sr_nvalue_table  - Smartreflex n-target value info
+ *
+ * @efuse_offs: The offset of the efuse where n-target values are stored.
+ * @nvalue:     The n-target value.
+ */
+struct omap_sr_nvalue_table {
+        u32 efuse_offs;
+        u32 nvalue;
+};
+
+/**
+ * struct omap_sr_data - Smartreflex platform data.
+ *
+ * @ip_type:            Smartreflex IP type.
+ * @senp_mod:           SENPENABLE value for the sr
+ * @senn_mod:           SENNENABLE value for sr
+ * @nvalue_count:       Number of distinct nvalues in the nvalue table
+ * @enable_on_init:     whether this sr module needs to enabled at
+ *                      boot up or not.
+ * @nvalue_table:       table containing the  efuse offsets and nvalues
+ *                      corresponding to them.
+ * @voltdm:             Pointer to the voltage domain associated with the SR
+ */
+struct omap_sr_data {
+        int                             ip_type;
+        u32                             senp_mod;
+        u32                             senn_mod;
+        int                             nvalue_count;
+        bool                            enable_on_init;
+        struct omap_sr_nvalue_table     *nvalue_table;
+        struct voltagedomain            *voltdm;
+};
+
+/* Smartreflex module enable/disable interface */
+void omap_sr_enable(struct voltagedomain *voltdm);
+void omap_sr_disable(struct voltagedomain *voltdm);
+void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
+
+/* API to register the pmic specific data with the smartreflex driver. */
+void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
+
+/* Smartreflex driver hooks to be called from Smartreflex class driver */
+int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
+void sr_disable(struct voltagedomain *voltdm);
+int sr_configure_errgen(struct voltagedomain *voltdm);
+int sr_configure_minmax(struct voltagedomain *voltdm);
+
+/* API to register the smartreflex class driver with the smartreflex driver */
+int sr_register_class(struct omap_sr_class_data *class_data);
+#else
+static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
+static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
+static inline void omap_sr_disable_reset_volt(
+                struct voltagedomain *voltdm) {}
+static inline void omap_sr_register_pmic(
+                struct omap_sr_pmic_data *pmic_data) {}
+#endif
+#endif
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index ecd6a488c497..7a10257909ef 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,7 +18,6 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
-#include <asm/smp_mpidr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -29,9 +28,9 @@ extern u32 omap_read_auxcoreboot0(void);
 /*
  * We use Soft IRQ1 as the IPI
  */
-static inline void smp_cross_call(const struct cpumask *mask)
+static inline void smp_cross_call(const struct cpumask *mask, int ipi)
 {
-        gic_raise_softirq(mask, 1);
+        gic_raise_softirq(mask, ipi);
 }
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 5905100b29a1..9967d5e855c7 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -11,6 +11,7 @@
 #ifndef __ARCH_ARM_OMAP_SRAM_H
 #define __ARCH_ARM_OMAP_SRAM_H
 
+#ifndef __ASSEMBLY__
 extern void * omap_sram_push(void * start, unsigned long size);
 extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
 
@@ -74,4 +75,14 @@ extern void omap_push_sram_idle(void);
 static inline void omap_push_sram_idle(void) {}
 #endif /* CONFIG_PM */
 
+#endif /* __ASSEMBLY__ */
+
+/*
+ * OMAP2+: define the SRAM PA addresses.
+ * Used by the SRAM management code and the idle sleep code.
+ */
+#define OMAP2_SRAM_PA           0x40200000
+#define OMAP3_SRAM_PA           0x40200000
+#define OMAP4_SRAM_PA           0x40300000
+
 #endif
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 9036e374e0ac..ad98b85cae21 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -145,8 +145,11 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 /* omap3 based boards using UART3 */
                 DEBUG_LL_OMAP3(3, cm_t35);
                 DEBUG_LL_OMAP3(3, cm_t3517);
+                DEBUG_LL_OMAP3(3, craneboard);
+                DEBUG_LL_OMAP3(3, devkit8000);
                 DEBUG_LL_OMAP3(3, igep0020);
                 DEBUG_LL_OMAP3(3, igep0030);
+                DEBUG_LL_OMAP3(3, nokia_rm680);
                 DEBUG_LL_OMAP3(3, nokia_rx51);
                 DEBUG_LL_OMAP3(3, omap3517evm);
                 DEBUG_LL_OMAP3(3, omap3_beagle);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 59c7fe731f28..450a332f1009 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -11,6 +11,7 @@ enum ehci_hcd_omap_mode {
         EHCI_HCD_OMAP_MODE_UNKNOWN,
         EHCI_HCD_OMAP_MODE_PHY,
         EHCI_HCD_OMAP_MODE_TLL,
+        EHCI_HCD_OMAP_MODE_HSIC,
 };
 
 enum ohci_omap3_port_mode {
@@ -69,6 +70,10 @@ struct omap_musb_board_data {
         u8      mode;
         u16     power;
         unsigned extvbus:1;
+        void    (*set_phy_power)(u8 on);
+        void    (*clear_irq)(void);
+        void    (*set_mode)(u8 mode);
+        void    (*reset)(void);
 };
 
 enum musb_interface    {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
@@ -79,6 +84,11 @@ extern void usb_ehci_init(const struct ehci_hcd_omap_platform_data *pdata);
 
 extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
 
+extern int omap4430_phy_power(struct device *dev, int ID, int on);
+extern int omap4430_phy_set_clk(struct device *dev, int on);
+extern int omap4430_phy_init(struct device *dev);
+extern int omap4430_phy_exit(struct device *dev);
+
 #endif
 
 
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
new file mode 100644
index 000000000000..0ff123399f3b
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -0,0 +1,146 @@
+/*
+ * OMAP Voltage Management Routines
+ *
+ * Author: Thara Gopinath       <thara@ti.com>
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc.
+ * Thara Gopinath <thara@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
+#define __ARCH_ARM_MACH_OMAP2_VOLTAGE_H
+
+#define VOLTSCALE_VPFORCEUPDATE         1
+#define VOLTSCALE_VCBYPASS              2
+
+/*
+ * OMAP3 GENERIC setup times. Revisit to see if these needs to be
+ * passed from board or PMIC file
+ */
+#define OMAP3_CLKSETUP          0xff
+#define OMAP3_VOLTOFFSET        0xff
+#define OMAP3_VOLTSETUP2        0xff
+
+/* Voltage value defines */
+#define OMAP3430_VDD_MPU_OPP1_UV                975000
+#define OMAP3430_VDD_MPU_OPP2_UV                1075000
+#define OMAP3430_VDD_MPU_OPP3_UV                1200000
+#define OMAP3430_VDD_MPU_OPP4_UV                1270000
+#define OMAP3430_VDD_MPU_OPP5_UV                1350000
+
+#define OMAP3430_VDD_CORE_OPP1_UV               975000
+#define OMAP3430_VDD_CORE_OPP2_UV               1050000
+#define OMAP3430_VDD_CORE_OPP3_UV               1150000
+
+#define OMAP3630_VDD_MPU_OPP50_UV               1012500
+#define OMAP3630_VDD_MPU_OPP100_UV              1200000
+#define OMAP3630_VDD_MPU_OPP120_UV              1325000
+#define OMAP3630_VDD_MPU_OPP1G_UV               1375000
+
+#define OMAP3630_VDD_CORE_OPP50_UV              1000000
+#define OMAP3630_VDD_CORE_OPP100_UV             1200000
+
+#define OMAP4430_VDD_MPU_OPP50_UV               930000
+#define OMAP4430_VDD_MPU_OPP100_UV              1100000
+#define OMAP4430_VDD_MPU_OPPTURBO_UV            1260000
+#define OMAP4430_VDD_MPU_OPPNITRO_UV            1350000
+
+#define OMAP4430_VDD_IVA_OPP50_UV               930000
+#define OMAP4430_VDD_IVA_OPP100_UV              1100000
+#define OMAP4430_VDD_IVA_OPPTURBO_UV            1260000
+
+#define OMAP4430_VDD_CORE_OPP50_UV              930000
+#define OMAP4430_VDD_CORE_OPP100_UV             1100000
+
+/**
+ * struct voltagedomain - omap voltage domain global structure.
+ * @name:       Name of the voltage domain which can be used as a unique
+ *              identifier.
+ */
+struct voltagedomain {
+        char *name;
+};
+
+/* API to get the voltagedomain pointer */
+struct voltagedomain *omap_voltage_domain_lookup(char *name);
+
+/**
+ * struct omap_volt_data - Omap voltage specific data.
+ * @voltage_nominal:    The possible voltage value in uV
+ * @sr_efuse_offs:      The offset of the efuse register(from system
+ *                      control module base address) from where to read
+ *                      the n-target value for the smartreflex module.
+ * @sr_errminlimit:     Error min limit value for smartreflex. This value
+ *                      differs at differnet opp and thus is linked
+ *                      with voltage.
+ * @vp_errorgain:       Error gain value for the voltage processor. This
+ *                      field also differs according to the voltage/opp.
+ */
+struct omap_volt_data {
+        u32     volt_nominal;
+        u32     sr_efuse_offs;
+        u8      sr_errminlimit;
+        u8      vp_errgain;
+};
+
+/**
+ * struct omap_volt_pmic_info - PMIC specific data required by voltage driver.
+ * @slew_rate:  PMIC slew rate (in uv/us)
+ * @step_size:  PMIC voltage step size (in uv)
+ * @vsel_to_uv: PMIC API to convert vsel value to actual voltage in uV.
+ * @uv_to_vsel: PMIC API to convert voltage in uV to vsel value.
+ */
+struct omap_volt_pmic_info {
+        int slew_rate;
+        int step_size;
+        u32 on_volt;
+        u32 onlp_volt;
+        u32 ret_volt;
+        u32 off_volt;
+        u16 volt_setup_time;
+        u8 vp_erroroffset;
+        u8 vp_vstepmin;
+        u8 vp_vstepmax;
+        u8 vp_vddmin;
+        u8 vp_vddmax;
+        u8 vp_timeout_us;
+        u8 i2c_slave_addr;
+        u8 pmic_reg;
+        unsigned long (*vsel_to_uv) (const u8 vsel);
+        u8 (*uv_to_vsel) (unsigned long uV);
+};
+
+unsigned long omap_vp_get_curr_volt(struct voltagedomain *voltdm);
+void omap_vp_enable(struct voltagedomain *voltdm);
+void omap_vp_disable(struct voltagedomain *voltdm);
+int omap_voltage_scale_vdd(struct voltagedomain *voltdm,
+                unsigned long target_volt);
+void omap_voltage_reset(struct voltagedomain *voltdm);
+void omap_voltage_get_volttable(struct voltagedomain *voltdm,
+                struct omap_volt_data **volt_data);
+struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+                unsigned long volt);
+unsigned long omap_voltage_get_nom_volt(struct voltagedomain *voltdm);
+struct dentry *omap_voltage_get_dbgdir(struct voltagedomain *voltdm);
+#ifdef CONFIG_PM
+int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+                struct omap_volt_pmic_info *pmic_info);
+void omap_change_voltscale_method(struct voltagedomain *voltdm,
+                int voltscale_method);
+int omap_voltage_late_init(void);
+#else
+static inline int omap_voltage_register_pmic(struct voltagedomain *voltdm,
+                struct omap_volt_pmic_info *pmic_info) {}
+static inline  void omap_change_voltscale_method(struct voltagedomain *voltdm,
+                int voltscale_method) {}
+static inline int omap_voltage_late_init(void)
+{
+        return -EINVAL;
+}
+#endif
+
+#endif
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index b0078cf96281..f1295fafcd31 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -136,61 +136,3 @@ void omap_iounmap(volatile void __iomem *addr)
                 __iounmap(addr);
 }
 EXPORT_SYMBOL(omap_iounmap);
-
-/*
- * NOTE: Please use ioremap + __raw_read/write where possible instead of these
- */
-
-u8 omap_readb(u32 pa)
-{
-        if (cpu_class_is_omap1())
-                return __raw_readb(OMAP1_IO_ADDRESS(pa));
-        else
-                return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readb);
-
-u16 omap_readw(u32 pa)
-{
-        if (cpu_class_is_omap1())
-                return __raw_readw(OMAP1_IO_ADDRESS(pa));
-        else
-                return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readw);
-
-u32 omap_readl(u32 pa)
-{
-        if (cpu_class_is_omap1())
-                return __raw_readl(OMAP1_IO_ADDRESS(pa));
-        else
-                return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_readl);
-
-void omap_writeb(u8 v, u32 pa)
-{
-        if (cpu_class_is_omap1())
-                __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
-        else
-                __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writeb);
-
-void omap_writew(u16 v, u32 pa)
-{
-        if (cpu_class_is_omap1())
-                __raw_writew(v, OMAP1_IO_ADDRESS(pa));
-        else
-                __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writew);
-
-void omap_writel(u32 v, u32 pa)
-{
-        if (cpu_class_is_omap1())
-                __raw_writel(v, OMAP1_IO_ADDRESS(pa));
-        else
-                __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-EXPORT_SYMBOL(omap_writel);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 6cd151b31bc5..b1107c08da56 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -830,6 +830,28 @@ static int device_match_by_alias(struct device *dev, void *data)
 }
 
 /**
+ * iommu_set_da_range - Set a valid device address range
+ * @obj:                target iommu
+ * @start               Start of valid range
+ * @end                 End of valid range
+ **/
+int iommu_set_da_range(struct iommu *obj, u32 start, u32 end)
+{
+
+        if (!obj)
+                return -EFAULT;
+
+        if (end < start || !PAGE_ALIGN(start | end))
+                return -EINVAL;
+
+        obj->da_start = start;
+        obj->da_end = end;
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(iommu_set_da_range);
+
+/**
  * iommu_get - Get iommu handler
  * @name:       target iommu name
  **/
@@ -922,6 +944,8 @@ static int __devinit omap_iommu_probe(struct platform_device *pdev)
         obj->name = pdata->name;
         obj->dev = &pdev->dev;
         obj->ctx = (void *)obj + sizeof(*obj);
+        obj->da_start = pdata->da_start;
+        obj->da_end = pdata->da_end;
 
         mutex_init(&obj->iommu_lock);
         mutex_init(&obj->mmap_lock);
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index 8ce0de247c71..6dc1296c8c77 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -87,35 +87,43 @@ static size_t sgtable_len(const struct sg_table *sgt)
 }
 #define sgtable_ok(x)   (!!sgtable_len(x))
 
+static unsigned max_alignment(u32 addr)
+{
+        int i;
+        unsigned pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, };
+        for (i = 0; i < ARRAY_SIZE(pagesize) && addr & (pagesize[i] - 1); i++)
+                ;
+        return (i < ARRAY_SIZE(pagesize)) ? pagesize[i] : 0;
+}
+
 /*
  * calculate the optimal number sg elements from total bytes based on
  * iommu superpages
  */
-static unsigned int sgtable_nents(size_t bytes)
+static unsigned sgtable_nents(size_t bytes, u32 da, u32 pa)
 {
-        int i;
-        unsigned int nr_entries;
-        const unsigned long pagesize[] = { SZ_16M, SZ_1M, SZ_64K, SZ_4K, };
+        unsigned nr_entries = 0, ent_sz;
 
         if (!IS_ALIGNED(bytes, PAGE_SIZE)) {
                 pr_err("%s: wrong size %08x\n", __func__, bytes);
                 return 0;
         }
 
-        nr_entries = 0;
-        for (i = 0; i < ARRAY_SIZE(pagesize); i++) {
-                if (bytes >= pagesize[i]) {
-                        nr_entries += (bytes / pagesize[i]);
-                        bytes %= pagesize[i];
-                }
+        while (bytes) {
+                ent_sz = max_alignment(da | pa);
+                ent_sz = min_t(unsigned, ent_sz, iopgsz_max(bytes));
+                nr_entries++;
+                da += ent_sz;
+                pa += ent_sz;
+                bytes -= ent_sz;
         }
-        BUG_ON(bytes);
 
         return nr_entries;
 }
 
 /* allocate and initialize sg_table header(a kind of 'superblock') */
-static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags)
+static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags,
+                                                        u32 da, u32 pa)
 {
         unsigned int nr_entries;
         int err;
@@ -127,9 +135,8 @@ static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags)
         if (!IS_ALIGNED(bytes, PAGE_SIZE))
                 return ERR_PTR(-EINVAL);
 
-        /* FIXME: IOVMF_DA_FIXED should support 'superpages' */
-        if ((flags & IOVMF_LINEAR) && (flags & IOVMF_DA_ANON)) {
-                nr_entries = sgtable_nents(bytes);
+        if (flags & IOVMF_LINEAR) {
+                nr_entries = sgtable_nents(bytes, da, pa);
                 if (!nr_entries)
                         return ERR_PTR(-EINVAL);
         } else
@@ -273,13 +280,14 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
         alignement = PAGE_SIZE;
 
         if (flags & IOVMF_DA_ANON) {
-                /*
-                 * Reserve the first page for NULL
-                 */
-                start = PAGE_SIZE;
+                start = obj->da_start;
+
                 if (flags & IOVMF_LINEAR)
                         alignement = iopgsz_max(bytes);
                 start = roundup(start, alignement);
+        } else if (start < obj->da_start || start > obj->da_end ||
+                                        obj->da_end - start < bytes) {
+                return ERR_PTR(-EINVAL);
         }
 
         tmp = NULL;
@@ -289,19 +297,19 @@ static struct iovm_struct *alloc_iovm_area(struct iommu *obj, u32 da,
         prev_end = 0;
         list_for_each_entry(tmp, &obj->mmap, list) {
 
-                if (prev_end >= start)
+                if (prev_end > start)
                         break;
 
-                if (start + bytes < tmp->da_start)
+                if (tmp->da_start > start && (tmp->da_start - start) >= bytes)
                         goto found;
 
-                if (flags & IOVMF_DA_ANON)
+                if (tmp->da_end >= start && flags & IOVMF_DA_ANON)
                         start = roundup(tmp->da_end + 1, alignement);
 
                 prev_end = tmp->da_end;
         }
 
-        if ((start > prev_end) && (ULONG_MAX - start >= bytes))
+        if ((start >= prev_end) && (obj->da_end - start >= bytes))
                 goto found;
 
         dev_dbg(obj->dev, "%s: no space to fit %08x(%x) flags: %08x\n",
@@ -409,7 +417,8 @@ static inline void sgtable_drain_vmalloc(struct sg_table *sgt)
         BUG_ON(!sgt);
 }
 
-static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
+static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, u32 da,
+                                                                size_t len)
 {
         unsigned int i;
         struct scatterlist *sg;
@@ -418,9 +427,10 @@ static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
         va = phys_to_virt(pa);
 
         for_each_sg(sgt->sgl, sg, sgt->nents, i) {
-                size_t bytes;
+                unsigned bytes;
 
-                bytes = iopgsz_max(len);
+                bytes = max_alignment(da | pa);
+                bytes = min_t(unsigned, bytes, iopgsz_max(len));
 
                 BUG_ON(!iopgsz_ok(bytes));
 
@@ -429,6 +439,7 @@ static void sgtable_fill_kmalloc(struct sg_table *sgt, u32 pa, size_t len)
                  * 'pa' is cotinuous(linear).
                  */
                 pa += bytes;
+                da += bytes;
                 len -= bytes;
         }
         BUG_ON(len);
@@ -695,18 +706,18 @@ u32 iommu_vmalloc(struct iommu *obj, u32 da, size_t bytes, u32 flags)
         if (!va)
                 return -ENOMEM;
 
-        sgt = sgtable_alloc(bytes, flags);
+        flags &= IOVMF_HW_MASK;
+        flags |= IOVMF_DISCONT;
+        flags |= IOVMF_ALLOC;
+        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
+
+        sgt = sgtable_alloc(bytes, flags, da, 0);
         if (IS_ERR(sgt)) {
                 da = PTR_ERR(sgt);
                 goto err_sgt_alloc;
         }
         sgtable_fill_vmalloc(sgt, va);
 
-        flags &= IOVMF_HW_MASK;
-        flags |= IOVMF_DISCONT;
-        flags |= IOVMF_ALLOC;
-        flags |= (da ? IOVMF_DA_FIXED : IOVMF_DA_ANON);
-
         da = __iommu_vmap(obj, da, sgt, va, bytes, flags);
         if (IS_ERR_VALUE(da))
                 goto err_iommu_vmap;
@@ -746,11 +757,11 @@ static u32 __iommu_kmap(struct iommu *obj, u32 da, u32 pa, void *va,
 {
         struct sg_table *sgt;
 
-        sgt = sgtable_alloc(bytes, flags);
+        sgt = sgtable_alloc(bytes, flags, da, pa);
         if (IS_ERR(sgt))
                 return PTR_ERR(sgt);
 
-        sgtable_fill_kmalloc(sgt, pa, bytes);
+        sgtable_fill_kmalloc(sgt, pa, da, bytes);
 
         da = map_iommu_region(obj, da, sgt, va, bytes, flags);
         if (IS_ERR_VALUE(da)) {
@@ -811,7 +822,7 @@ void iommu_kunmap(struct iommu *obj, u32 da)
         struct sg_table *sgt;
         typedef void (*func_t)(const void *);
 
-        sgt = unmap_vm_area(obj, da, (func_t)__iounmap,
+        sgt = unmap_vm_area(obj, da, (func_t)iounmap,
                             IOVMF_LINEAR | IOVMF_MMIO);
         if (!sgt)
                 dev_dbg(obj->dev, "%s: No sgt\n", __func__);
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index d2fafb892f7f..459b319a9fad 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -28,12 +28,12 @@
 #include <linux/slab.h>
 #include <linux/kfifo.h>
 #include <linux/err.h>
+#include <linux/notifier.h>
 
 #include <plat/mailbox.h>
 
 static struct workqueue_struct *mboxd;
 static struct omap_mbox **mboxes;
-static bool rq_full;
 
 static int mbox_configured;
 static DEFINE_MUTEX(mbox_configured_lock);
@@ -93,20 +93,25 @@ int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
         struct omap_mbox_queue *mq = mbox->txq;
         int ret = 0, len;
 
-        spin_lock(&mq->lock);
+        spin_lock_bh(&mq->lock);
 
         if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
                 ret = -ENOMEM;
                 goto out;
         }
 
+        if (kfifo_is_empty(&mq->fifo) && !__mbox_poll_for_space(mbox)) {
+                mbox_fifo_write(mbox, msg);
+                goto out;
+        }
+
         len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
         WARN_ON(len != sizeof(msg));
 
         tasklet_schedule(&mbox->txq->tasklet);
 
 out:
-        spin_unlock(&mq->lock);
+        spin_unlock_bh(&mq->lock);
         return ret;
 }
 EXPORT_SYMBOL(omap_mbox_msg_send);
@@ -146,8 +151,14 @@ static void mbox_rx_work(struct work_struct *work)
                 len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
                 WARN_ON(len != sizeof(msg));
 
-                if (mq->callback)
-                        mq->callback((void *)msg);
+                blocking_notifier_call_chain(&mq->mbox->notifier, len,
+                                                                (void *)msg);
+                spin_lock_irq(&mq->lock);
+                if (mq->full) {
+                        mq->full = false;
+                        omap_mbox_enable_irq(mq->mbox, IRQ_RX);
+                }
+                spin_unlock_irq(&mq->lock);
         }
 }
 
@@ -170,7 +181,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
         while (!mbox_fifo_empty(mbox)) {
                 if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
                         omap_mbox_disable_irq(mbox, IRQ_RX);
-                        rq_full = true;
+                        mq->full = true;
                         goto nomem;
                 }
 
@@ -239,73 +250,77 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
         int ret = 0;
         struct omap_mbox_queue *mq;
 
-        if (mbox->ops->startup) {
-                mutex_lock(&mbox_configured_lock);
-                if (!mbox_configured)
+        mutex_lock(&mbox_configured_lock);
+        if (!mbox_configured++) {
+                if (likely(mbox->ops->startup)) {
                         ret = mbox->ops->startup(mbox);
-
-                if (ret) {
-                        mutex_unlock(&mbox_configured_lock);
-                        return ret;
-                }
-                mbox_configured++;
-                mutex_unlock(&mbox_configured_lock);
-        }
-
-        ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
-                                mbox->name, mbox);
-        if (ret) {
-                printk(KERN_ERR
-                        "failed to register mailbox interrupt:%d\n", ret);
-                goto fail_request_irq;
+                        if (unlikely(ret))
+                                goto fail_startup;
+                } else
+                        goto fail_startup;
         }
 
-        mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
-        if (!mq) {
-                ret = -ENOMEM;
-                goto fail_alloc_txq;
-        }
-        mbox->txq = mq;
+        if (!mbox->use_count++) {
+                ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
+                                                        mbox->name, mbox);
+                if (unlikely(ret)) {
+                        pr_err("failed to register mailbox interrupt:%d\n",
+                                                                        ret);
+                        goto fail_request_irq;
+                }
+                mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
+                if (!mq) {
+                        ret = -ENOMEM;
+                        goto fail_alloc_txq;
+                }
+                mbox->txq = mq;
 
-        mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
-        if (!mq) {
-                ret = -ENOMEM;
-                goto fail_alloc_rxq;
+                mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
+                if (!mq) {
+                        ret = -ENOMEM;
+                        goto fail_alloc_rxq;
+                }
+                mbox->rxq = mq;
+                mq->mbox = mbox;
         }
-        mbox->rxq = mq;
-
+        mutex_unlock(&mbox_configured_lock);
         return 0;
 
- fail_alloc_rxq:
+fail_alloc_rxq:
         mbox_queue_free(mbox->txq);
- fail_alloc_txq:
+fail_alloc_txq:
         free_irq(mbox->irq, mbox);
- fail_request_irq:
+fail_request_irq:
         if (mbox->ops->shutdown)
                 mbox->ops->shutdown(mbox);
-
+        mbox->use_count--;
+fail_startup:
+        mbox_configured--;
+        mutex_unlock(&mbox_configured_lock);
         return ret;
 }
 
 static void omap_mbox_fini(struct omap_mbox *mbox)
 {
-        free_irq(mbox->irq, mbox);
-        tasklet_kill(&mbox->txq->tasklet);
-        flush_work(&mbox->rxq->work);
-        mbox_queue_free(mbox->txq);
-        mbox_queue_free(mbox->rxq);
+        mutex_lock(&mbox_configured_lock);
+
+        if (!--mbox->use_count) {
+                free_irq(mbox->irq, mbox);
+                tasklet_kill(&mbox->txq->tasklet);
+                flush_work(&mbox->rxq->work);
+                mbox_queue_free(mbox->txq);
+                mbox_queue_free(mbox->rxq);
+        }
 
-        if (mbox->ops->shutdown) {
-                mutex_lock(&mbox_configured_lock);
-                if (mbox_configured > 0)
-                        mbox_configured--;
-                if (!mbox_configured)
+        if (likely(mbox->ops->shutdown)) {
+                if (!--mbox_configured)
                         mbox->ops->shutdown(mbox);
-                mutex_unlock(&mbox_configured_lock);
         }
+
+        mutex_unlock(&mbox_configured_lock);
 }
 
-struct omap_mbox *omap_mbox_get(const char *name)
+struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
 {
         struct omap_mbox *mbox;
         int ret;
@@ -324,12 +339,16 @@ struct omap_mbox *omap_mbox_get(const char *name)
         if (ret)
                 return ERR_PTR(-ENODEV);
 
+        if (nb)
+                blocking_notifier_chain_register(&mbox->notifier, nb);
+
         return mbox;
 }
 EXPORT_SYMBOL(omap_mbox_get);
 
-void omap_mbox_put(struct omap_mbox *mbox)
+void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb)
 {
+        blocking_notifier_chain_unregister(&mbox->notifier, nb);
         omap_mbox_fini(mbox);
 }
 EXPORT_SYMBOL(omap_mbox_put);
@@ -353,6 +372,8 @@ int omap_mbox_register(struct device *parent, struct omap_mbox **list)
                         ret = PTR_ERR(mbox->dev);
                         goto err_out;
                 }
+
+                BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier);
         }
         return 0;
 
@@ -391,7 +412,8 @@ static int __init omap_mbox_init(void)
 
         /* kfifo size sanity check: alignment and minimal size */
         mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
-        mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(mbox_msg_t));
+        mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
+                                                        sizeof(mbox_msg_t));
 
         return 0;
 }
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index eac4b978e9fd..b5a6e178a7f9 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -28,6 +28,8 @@
 #include <plat/dma.h>
 #include <plat/mcbsp.h>
 
+/* XXX These "sideways" includes are a sign that something is wrong */
+#include "../mach-omap2/cm2xxx_3xxx.h"
 #include "../mach-omap2/cm-regbits-34xx.h"
 
 struct omap_mcbsp **mcbsp_ptr;
@@ -234,9 +236,9 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
          * Sidetone uses McBSP ICLK - which must not idle when sidetones
          * are enabled or sidetones start sounding ugly.
          */
-        w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
         w &= ~(1 << (mcbsp->id - 2));
-        cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 
         /* Enable McBSP Sidetone */
         w = MCBSP_READ(mcbsp, SSELCR);
@@ -263,9 +265,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
         w = MCBSP_READ(mcbsp, SSELCR);
         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 
-        w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
+        w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
         w |= 1 << (mcbsp->id - 2);
-        cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
+        omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 }
 
 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
@@ -755,7 +757,7 @@ int omap_mcbsp_request(unsigned int id)
                 goto err_kfree;
         }
 
-        mcbsp->free = 0;
+        mcbsp->free = false;
         mcbsp->reg_cache = reg_cache;
         spin_unlock(&mcbsp->lock);
 
@@ -815,7 +817,7 @@ err_clk_disable:
         clk_disable(mcbsp->iclk);
 
         spin_lock(&mcbsp->lock);
-        mcbsp->free = 1;
+        mcbsp->free = true;
         mcbsp->reg_cache = NULL;
 err_kfree:
         spin_unlock(&mcbsp->lock);
@@ -858,7 +860,7 @@ void omap_mcbsp_free(unsigned int id)
         if (mcbsp->free)
                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
         else
-                mcbsp->free = 1;
+                mcbsp->free = true;
         mcbsp->reg_cache = NULL;
         spin_unlock(&mcbsp->lock);
 
@@ -1771,7 +1773,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
 
         spin_lock_init(&mcbsp->lock);
         mcbsp->id = id + 1;
-        mcbsp->free = 1;
+        mcbsp->free = true;
         mcbsp->dma_tx_lch = -1;
         mcbsp->dma_rx_lch = -1;
 
@@ -1836,17 +1838,11 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
 
                 omap34xx_device_exit(mcbsp);
 
-                clk_disable(mcbsp->fclk);
-                clk_disable(mcbsp->iclk);
                 clk_put(mcbsp->fclk);
                 clk_put(mcbsp->iclk);
 
                 iounmap(mcbsp->io_base);
-
-                mcbsp->fclk = NULL;
-                mcbsp->iclk = NULL;
-                mcbsp->free = 0;
-                mcbsp->dev = NULL;
+                kfree(mcbsp);
         }
 
         return 0;
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index e129ce80c53b..b0471bb2d47d 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -20,15 +20,14 @@
 #include <linux/init.h>
 #include <linux/cpufreq.h>
 #include <linux/device.h>
+#include <linux/platform_device.h>
 
 /* Interface documentation is in mach/omap-pm.h */
 #include <plat/omap-pm.h>
+#include <plat/omap_device.h>
 
-#include <plat/powerdomain.h>
-
-struct omap_opp *dsp_opps;
-struct omap_opp *mpu_opps;
-struct omap_opp *l3_opps;
+static bool off_mode_enabled;
+static u32 dummy_context_loss_counter;
 
 /*
  * Device-driver-originated constraints (via board-*.c files)
@@ -284,37 +283,70 @@ unsigned long omap_pm_cpu_get_freq(void)
         return 0;
 }
 
+/**
+ * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled
+ *
+ * Intended for use only by OMAP PM core code to notify this layer
+ * that off mode has been enabled.
+ */
+void omap_pm_enable_off_mode(void)
+{
+        off_mode_enabled = true;
+}
+
+/**
+ * omap_pm_disable_off_mode - notify OMAP PM that off-mode is disabled
+ *
+ * Intended for use only by OMAP PM core code to notify this layer
+ * that off mode has been disabled.
+ */
+void omap_pm_disable_off_mode(void)
+{
+        off_mode_enabled = false;
+}
+
 /*
  * Device context loss tracking
  */
 
-int omap_pm_get_dev_context_loss_count(struct device *dev)
+#ifdef CONFIG_ARCH_OMAP2PLUS
+
+u32 omap_pm_get_dev_context_loss_count(struct device *dev)
 {
-        if (!dev) {
-                WARN_ON(1);
-                return -EINVAL;
-        };
+        struct platform_device *pdev = to_platform_device(dev);
+        u32 count;
+
+        if (WARN_ON(!dev))
+                return 0;
+
+        if (dev->parent == &omap_device_parent) {
+                count = omap_device_get_context_loss_count(pdev);
+        } else {
+                WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device",
+                          dev_name(dev));
+                if (off_mode_enabled)
+                        dummy_context_loss_counter++;
+                count = dummy_context_loss_counter;
+        }
 
-        pr_debug("OMAP PM: returning context loss count for dev %s\n",
-                 dev_name(dev));
+        pr_debug("OMAP PM: context loss count for dev %s = %d\n",
+                 dev_name(dev), count);
 
-        /*
-         * Map the device to the powerdomain.  Return the powerdomain
-         * off counter.
-         */
+        return count;
+}
 
-        return 0;
+#else
+
+u32 omap_pm_get_dev_context_loss_count(struct device *dev)
+{
+        return dummy_context_loss_counter;
 }
 
+#endif
 
 /* Should be called before clk framework init */
-int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
-                                 struct omap_opp *dsp_opp_table,
-                                 struct omap_opp *l3_opp_table)
+int __init omap_pm_if_early_init(void)
 {
-        mpu_opps = mpu_opp_table;
-        dsp_opps = dsp_opp_table;
-        l3_opps = l3_opp_table;
         return 0;
 }
 
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index abe933cd8f09..57adb270767b 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -280,6 +280,34 @@ static void _add_optional_clock_alias(struct omap_device *od,
 /* Public functions for use by core code */
 
 /**
+ * omap_device_get_context_loss_count - get lost context count
+ * @od: struct omap_device *
+ *
+ * Using the primary hwmod, query the context loss count for this
+ * device.
+ *
+ * Callers should consider context for this device lost any time this
+ * function returns a value different than the value the caller got
+ * the last time it called this function.
+ *
+ * If any hwmods exist for the omap_device assoiated with @pdev,
+ * return the context loss counter for that hwmod, otherwise return
+ * zero.
+ */
+u32 omap_device_get_context_loss_count(struct platform_device *pdev)
+{
+        struct omap_device *od;
+        u32 ret = 0;
+
+        od = _find_by_pdev(pdev);
+
+        if (od->hwmods_cnt)
+                ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
+
+        return ret;
+}
+
+/**
  * omap_device_count_resources - count number of struct resource entries needed
  * @od: struct omap_device *
  *
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 74dac419d328..e26e50487d60 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -33,23 +33,21 @@
 
 #include "sram.h"
 #include "fb.h"
+
+/* XXX These "sideways" includes are a sign that something is wrong */
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-# include "../mach-omap2/prm.h"
-# include "../mach-omap2/cm.h"
+# include "../mach-omap2/prm2xxx_3xxx.h"
 # include "../mach-omap2/sdrc.h"
 #endif
 
 #define OMAP1_SRAM_PA           0x20000000
 #define OMAP1_SRAM_VA           VMALLOC_END
-#define OMAP2_SRAM_PA           0x40200000
-#define OMAP2_SRAM_PUB_PA       0x4020f800
+#define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
 #define OMAP2_SRAM_VA           0xfe400000
 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
-#define OMAP3_SRAM_PA           0x40200000
 #define OMAP3_SRAM_VA           0xfe400000
-#define OMAP3_SRAM_PUB_PA       0x40208000
+#define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
-#define OMAP4_SRAM_PA           0x40300000
 #define OMAP4_SRAM_VA           0xfe400000
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
@@ -270,7 +268,7 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
         _omap_sram_reprogram_clock(dpllctl, ckctl);
 }
 
-int __init omap1_sram_init(void)
+static int __init omap1_sram_init(void)
 {
         _omap_sram_reprogram_clock =
                         omap_sram_push(omap1_sram_reprogram_clock,
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 715a30177f28..c3da2478b2aa 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -13,11 +13,11 @@
 
 #include <linux/kernel.h>
 #include <linux/sched.h>
-#include <linux/cnt32_to_63.h>
 #include <linux/timer.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <asm/sched_clock.h>
 #include <asm/mach/time.h>
 #include <mach/bridge-regs.h>
 #include <mach/hardware.h>
@@ -44,52 +44,26 @@ static u32 ticks_per_jiffy;
 
 /*
  * Orion's sched_clock implementation. It has a resolution of
- * at least 7.5ns (133MHz TCLK) and a maximum value of 834 days.
- *
- * Because the hardware timer period is quite short (21 secs if
- * 200MHz TCLK) and because cnt32_to_63() needs to be called at
- * least once per half period to work properly, a kernel timer is
- * set up to ensure this requirement is always met.
+ * at least 7.5ns (133MHz TCLK).
  */
-#define TCLK2NS_SCALE_FACTOR 8
-
-static unsigned long tclk2ns_scale;
+static DEFINE_CLOCK_DATA(cd);
 
-unsigned long long sched_clock(void)
+unsigned long long notrace sched_clock(void)
 {
-        unsigned long long v = cnt32_to_63(0xffffffff - readl(TIMER0_VAL));
-        return (v * tclk2ns_scale) >> TCLK2NS_SCALE_FACTOR;
+        u32 cyc = 0xffffffff - readl(TIMER0_VAL);
+        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 }
 
-static struct timer_list cnt32_to_63_keepwarm_timer;
 
-static void cnt32_to_63_keepwarm(unsigned long data)
+static void notrace orion_update_sched_clock(void)
 {
-        mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
-        (void) sched_clock();
+        u32 cyc = 0xffffffff - readl(TIMER0_VAL);
+        update_sched_clock(&cd, cyc, (u32)~0);
 }
 
 static void __init setup_sched_clock(unsigned long tclk)
 {
-        unsigned long long v;
-        unsigned long data;
-
-        v = NSEC_PER_SEC;
-        v <<= TCLK2NS_SCALE_FACTOR;
-        v += tclk/2;
-        do_div(v, tclk);
-        /*
-         * We want an even value to automatically clear the top bit
-         * returned by cnt32_to_63() without an additional run time
-         * instruction. So if the LSB is 1 then round it up.
-         */
-        if (v & 1)
-                v++;
-        tclk2ns_scale = v;
-
-        data = (0xffffffffUL / tclk / 2 - 2) * HZ;
-        setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data);
-        mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data));
+        init_sched_clock(&cd, orion_update_sched_clock, 32, tclk);
 }
 
 /*
@@ -102,7 +76,6 @@ static cycle_t orion_clksrc_read(struct clocksource *cs)
 
 static struct clocksource orion_clksrc = {
         .name           = "orion_clocksource",
-        .shift          = 20,
         .rating         = 300,
         .read           = orion_clksrc_read,
         .mask           = CLOCKSOURCE_MASK(32),
@@ -245,8 +218,7 @@ void __init orion_time_init(unsigned int irq, unsigned int tclk)
         writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
         u = readl(TIMER_CTRL);
         writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
-        orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift);
-        clocksource_register(&orion_clksrc);
+        clocksource_register_hz(&orion_clksrc, tclk);
 
         /*
          * Setup clockevent timer (interrupt-driven.)
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index 4aacdd12c9cc..3aca5ba0f876 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -6,6 +6,7 @@ obj-y	:= dma.o
 
 obj-$(CONFIG_GENERIC_GPIO)      += gpio.o
 obj-$(CONFIG_PXA3xx)            += mfp.o
+obj-$(CONFIG_PXA95x)            += mfp.o
 obj-$(CONFIG_ARCH_MMP)          += mfp.o
 
 obj-$(CONFIG_HAVE_PWM)          += pwm.o
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
index 9e604c80618f..75f656471240 100644
--- a/arch/arm/plat-pxa/include/plat/mfp.h
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -423,7 +423,7 @@ typedef unsigned long mfp_cfg_t;
         ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
          (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
 
-#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP)
+#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) || defined(CONFIG_ARCH_MMP)
 /*
  * each MFP pin will have a MFPR register, since the offset of the
  * register varies between processors, the processor specific code
@@ -470,6 +470,6 @@ void mfp_write(int mfp, unsigned long mfpr_val);
 void mfp_config(unsigned long *mfp_cfgs, int num);
 void mfp_config_run(void);
 void mfp_config_lpm(void);
-#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */
+#endif /* CONFIG_PXA3xx || CONFIG_PXA95x || CONFIG_ARCH_MMP */
 
 #endif /* __ASM_PLAT_MFP_H */
diff --git a/arch/arm/plat-pxa/include/plat/ssp.h b/arch/arm/plat-pxa/include/plat/ssp.h
deleted file mode 100644
index fe43150690ed..000000000000
--- a/arch/arm/plat-pxa/include/plat/ssp.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- *  ssp.h
- *
- *  Copyright (C) 2003 Russell King, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This driver supports the following PXA CPU/SSP ports:-
- *
- *       PXA250     SSP
- *       PXA255     SSP, NSSP
- *       PXA26x     SSP, NSSP, ASSP
- *       PXA27x     SSP1, SSP2, SSP3
- *       PXA3xx     SSP1, SSP2, SSP3, SSP4
- */
-
-#ifndef __ASM_ARCH_SSP_H
-#define __ASM_ARCH_SSP_H
-
-#include <linux/list.h>
-#include <linux/io.h>
-
-/*
- * SSP Serial Port Registers
- * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
- * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
- */
-
-#define SSCR0           (0x00)  /* SSP Control Register 0 */
-#define SSCR1           (0x04)  /* SSP Control Register 1 */
-#define SSSR            (0x08)  /* SSP Status Register */
-#define SSITR           (0x0C)  /* SSP Interrupt Test Register */
-#define SSDR            (0x10)  /* SSP Data Write/Data Read Register */
-
-#define SSTO            (0x28)  /* SSP Time Out Register */
-#define SSPSP           (0x2C)  /* SSP Programmable Serial Protocol */
-#define SSTSA           (0x30)  /* SSP Tx Timeslot Active */
-#define SSRSA           (0x34)  /* SSP Rx Timeslot Active */
-#define SSTSS           (0x38)  /* SSP Timeslot Status */
-#define SSACD           (0x3C)  /* SSP Audio Clock Divider */
-#define SSACDD          (0x40)  /* SSP Audio Clock Dither Divider */
-
-/* Common PXA2xx bits first */
-#define SSCR0_DSS       (0x0000000f)    /* Data Size Select (mask) */
-#define SSCR0_DataSize(x)  ((x) - 1)    /* Data Size Select [4..16] */
-#define SSCR0_FRF       (0x00000030)    /* FRame Format (mask) */
-#define SSCR0_Motorola  (0x0 << 4)      /* Motorola's Serial Peripheral Interface (SPI) */
-#define SSCR0_TI        (0x1 << 4)      /* Texas Instruments' Synchronous Serial Protocol (SSP) */
-#define SSCR0_National  (0x2 << 4)      /* National Microwire */
-#define SSCR0_ECS       (1 << 6)        /* External clock select */
-#define SSCR0_SSE       (1 << 7)        /* Synchronous Serial Port Enable */
-#define SSCR0_SCR(x)    ((x) << 8)      /* Serial Clock Rate (mask) */
-
-/* PXA27x, PXA3xx */
-#define SSCR0_EDSS      (1 << 20)       /* Extended data size select */
-#define SSCR0_NCS       (1 << 21)       /* Network clock select */
-#define SSCR0_RIM       (1 << 22)       /* Receive FIFO overrrun interrupt mask */
-#define SSCR0_TUM       (1 << 23)       /* Transmit FIFO underrun interrupt mask */
-#define SSCR0_FRDC      (0x07000000)    /* Frame rate divider control (mask) */
-#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24)  /* Time slots per frame [1..8] */
-#define SSCR0_FPCKE     (1 << 29)       /* FIFO packing enable */
-#define SSCR0_ACS       (1 << 30)       /* Audio clock select */
-#define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
-
-
-#define SSCR1_RIE       (1 << 0)        /* Receive FIFO Interrupt Enable */
-#define SSCR1_TIE       (1 << 1)        /* Transmit FIFO Interrupt Enable */
-#define SSCR1_LBM       (1 << 2)        /* Loop-Back Mode */
-#define SSCR1_SPO       (1 << 3)        /* Motorola SPI SSPSCLK polarity setting */
-#define SSCR1_SPH       (1 << 4)        /* Motorola SPI SSPSCLK phase setting */
-#define SSCR1_MWDS      (1 << 5)        /* Microwire Transmit Data Size */
-#define SSCR1_TFT       (0x000003c0)    /* Transmit FIFO Threshold (mask) */
-#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
-#define SSCR1_RFT       (0x00003c00)    /* Receive FIFO Threshold (mask) */
-#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
-
-#define SSSR_TNF        (1 << 2)        /* Transmit FIFO Not Full */
-#define SSSR_RNE        (1 << 3)        /* Receive FIFO Not Empty */
-#define SSSR_BSY        (1 << 4)        /* SSP Busy */
-#define SSSR_TFS        (1 << 5)        /* Transmit FIFO Service Request */
-#define SSSR_RFS        (1 << 6)        /* Receive FIFO Service Request */
-#define SSSR_ROR        (1 << 7)        /* Receive FIFO Overrun */
-
-
-/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
-#define SSCR0_TISSP             (1 << 4)        /* TI Sync Serial Protocol */
-#define SSCR0_PSP               (3 << 4)        /* PSP - Programmable Serial Protocol */
-#define SSCR1_TTELP             (1 << 31)       /* TXD Tristate Enable Last Phase */
-#define SSCR1_TTE               (1 << 30)       /* TXD Tristate Enable */
-#define SSCR1_EBCEI             (1 << 29)       /* Enable Bit Count Error interrupt */
-#define SSCR1_SCFR              (1 << 28)       /* Slave Clock free Running */
-#define SSCR1_ECRA              (1 << 27)       /* Enable Clock Request A */
-#define SSCR1_ECRB              (1 << 26)       /* Enable Clock request B */
-#define SSCR1_SCLKDIR           (1 << 25)       /* Serial Bit Rate Clock Direction */
-#define SSCR1_SFRMDIR           (1 << 24)       /* Frame Direction */
-#define SSCR1_RWOT              (1 << 23)       /* Receive Without Transmit */
-#define SSCR1_TRAIL             (1 << 22)       /* Trailing Byte */
-#define SSCR1_TSRE              (1 << 21)       /* Transmit Service Request Enable */
-#define SSCR1_RSRE              (1 << 20)       /* Receive Service Request Enable */
-#define SSCR1_TINTE             (1 << 19)       /* Receiver Time-out Interrupt enable */
-#define SSCR1_PINTE             (1 << 18)       /* Peripheral Trailing Byte Interupt Enable */
-#define SSCR1_IFS               (1 << 16)       /* Invert Frame Signal */
-#define SSCR1_STRF              (1 << 15)       /* Select FIFO or EFWR */
-#define SSCR1_EFWR              (1 << 14)       /* Enable FIFO Write/Read */
-
-#define SSSR_BCE                (1 << 23)       /* Bit Count Error */
-#define SSSR_CSS                (1 << 22)       /* Clock Synchronisation Status */
-#define SSSR_TUR                (1 << 21)       /* Transmit FIFO Under Run */
-#define SSSR_EOC                (1 << 20)       /* End Of Chain */
-#define SSSR_TINT               (1 << 19)       /* Receiver Time-out Interrupt */
-#define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
-
-
-#define SSPSP_SCMODE(x)         ((x) << 0)      /* Serial Bit Rate Clock Mode */
-#define SSPSP_SFRMP             (1 << 2)        /* Serial Frame Polarity */
-#define SSPSP_ETDS              (1 << 3)        /* End of Transfer data State */
-#define SSPSP_STRTDLY(x)        ((x) << 4)      /* Start Delay */
-#define SSPSP_DMYSTRT(x)        ((x) << 7)      /* Dummy Start */
-#define SSPSP_SFRMDLY(x)        ((x) << 9)      /* Serial Frame Delay */
-#define SSPSP_SFRMWDTH(x)       ((x) << 16)     /* Serial Frame Width */
-#define SSPSP_DMYSTOP(x)        ((x) << 23)     /* Dummy Stop */
-#define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
-
-/* PXA3xx */
-#define SSPSP_EDMYSTRT(x)       ((x) << 26)     /* Extended Dummy Start */
-#define SSPSP_EDMYSTOP(x)       ((x) << 28)     /* Extended Dummy Stop */
-#define SSPSP_TIMING_MASK       (0x7f8001f0)
-
-#define SSACD_SCDB              (1 << 3)        /* SSPSYSCLK Divider Bypass */
-#define SSACD_ACPS(x)           ((x) << 4)      /* Audio clock PLL select */
-#define SSACD_ACDS(x)           ((x) << 0)      /* Audio clock divider select */
-#define SSACD_SCDX8             (1 << 7)        /* SYSCLK division ratio select */
-
-enum pxa_ssp_type {
-        SSP_UNDEFINED = 0,
-        PXA25x_SSP,  /* pxa 210, 250, 255, 26x */
-        PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
-        PXA27x_SSP,
-        PXA168_SSP,
-};
-
-struct ssp_device {
-        struct platform_device *pdev;
-        struct list_head        node;
-
-        struct clk      *clk;
-        void __iomem    *mmio_base;
-        unsigned long   phys_base;
-
-        const char      *label;
-        int             port_id;
-        int             type;
-        int             use_count;
-        int             irq;
-        int             drcmr_rx;
-        int             drcmr_tx;
-};
-
-/**
- * pxa_ssp_write_reg - Write to a SSP register
- *
- * @dev: SSP device to access
- * @reg: Register to write to
- * @val: Value to be written.
- */
-static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
-{
-        __raw_writel(val, dev->mmio_base + reg);
-}
-
-/**
- * pxa_ssp_read_reg - Read from a SSP register
- *
- * @dev: SSP device to access
- * @reg: Register to read from
- */
-static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
-{
-        return __raw_readl(dev->mmio_base + reg);
-}
-
-struct ssp_device *pxa_ssp_request(int port, const char *label);
-void pxa_ssp_free(struct ssp_device *);
-#endif /* __ASM_ARCH_SSP_H */
diff --git a/arch/arm/plat-pxa/ssp.c b/arch/arm/plat-pxa/ssp.c
index c6357e554aba..58b79809d20c 100644
--- a/arch/arm/plat-pxa/ssp.c
+++ b/arch/arm/plat-pxa/ssp.c
@@ -28,11 +28,11 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
+#include <linux/spi/pxa2xx_spi.h>
 #include <linux/io.h>
 
 #include <asm/irq.h>
 #include <mach/hardware.h>
-#include <plat/ssp.h>
 
 static DEFINE_MUTEX(ssp_lock);
 static LIST_HEAD(ssp_list);
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c
index 1ecc15bfe9d4..25a8fc7f512e 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq.c
+++ b/arch/arm/plat-s3c24xx/cpu-freq.c
@@ -21,7 +21,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/sysdev.h>
-#include <linux/kobject.h>
 #include <linux/sysfs.h>
 #include <linux/slab.h>
 
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index 298bafc0a52f..2572260f990f 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -15,7 +15,7 @@
 #define __PLAT_CLOCK_H
 
 #include <linux/list.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <linux/types.h>
 
 /* clk structure flags */
diff --git a/arch/arm/plat-spear/include/plat/keyboard.h b/arch/arm/plat-spear/include/plat/keyboard.h
new file mode 100644
index 000000000000..68b5394fc583
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/keyboard.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2010 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_KEYBOARD_H
+#define __PLAT_KEYBOARD_H
+
+#include <linux/bitops.h>
+#include <linux/input.h>
+#include <linux/input/matrix_keypad.h>
+#include <linux/types.h>
+
+#define DECLARE_KEYMAP(_name) \
+int _name[] = { \
+        KEY(0, 0, KEY_ESC), \
+        KEY(0, 1, KEY_1), \
+        KEY(0, 2, KEY_2), \
+        KEY(0, 3, KEY_3), \
+        KEY(0, 4, KEY_4), \
+        KEY(0, 5, KEY_5), \
+        KEY(0, 6, KEY_6), \
+        KEY(0, 7, KEY_7), \
+        KEY(0, 8, KEY_8), \
+        KEY(1, 0, KEY_9), \
+        KEY(1, 1, KEY_MINUS), \
+        KEY(1, 2, KEY_EQUAL), \
+        KEY(1, 3, KEY_BACKSPACE), \
+        KEY(1, 4, KEY_TAB), \
+        KEY(1, 5, KEY_Q), \
+        KEY(1, 6, KEY_W), \
+        KEY(1, 7, KEY_E), \
+        KEY(1, 8, KEY_R), \
+        KEY(2, 0, KEY_T), \
+        KEY(2, 1, KEY_Y), \
+        KEY(2, 2, KEY_U), \
+        KEY(2, 3, KEY_I), \
+        KEY(2, 4, KEY_O), \
+        KEY(2, 5, KEY_P), \
+        KEY(2, 6, KEY_LEFTBRACE), \
+        KEY(2, 7, KEY_RIGHTBRACE), \
+        KEY(2, 8, KEY_ENTER), \
+        KEY(3, 0, KEY_LEFTCTRL), \
+        KEY(3, 1, KEY_A), \
+        KEY(3, 2, KEY_S), \
+        KEY(3, 3, KEY_D), \
+        KEY(3, 4, KEY_F), \
+        KEY(3, 5, KEY_G), \
+        KEY(3, 6, KEY_H), \
+        KEY(3, 7, KEY_J), \
+        KEY(3, 8, KEY_K), \
+        KEY(4, 0, KEY_L), \
+        KEY(4, 1, KEY_SEMICOLON), \
+        KEY(4, 2, KEY_APOSTROPHE), \
+        KEY(4, 3, KEY_GRAVE), \
+        KEY(4, 4, KEY_LEFTSHIFT), \
+        KEY(4, 5, KEY_BACKSLASH), \
+        KEY(4, 6, KEY_Z), \
+        KEY(4, 7, KEY_X), \
+        KEY(4, 8, KEY_C), \
+        KEY(4, 0, KEY_L), \
+        KEY(4, 1, KEY_SEMICOLON), \
+        KEY(4, 2, KEY_APOSTROPHE), \
+        KEY(4, 3, KEY_GRAVE), \
+        KEY(4, 4, KEY_LEFTSHIFT), \
+        KEY(4, 5, KEY_BACKSLASH), \
+        KEY(4, 6, KEY_Z), \
+        KEY(4, 7, KEY_X), \
+        KEY(4, 8, KEY_C), \
+        KEY(4, 0, KEY_L), \
+        KEY(4, 1, KEY_SEMICOLON), \
+        KEY(4, 2, KEY_APOSTROPHE), \
+        KEY(4, 3, KEY_GRAVE), \
+        KEY(4, 4, KEY_LEFTSHIFT), \
+        KEY(4, 5, KEY_BACKSLASH), \
+        KEY(4, 6, KEY_Z), \
+        KEY(4, 7, KEY_X), \
+        KEY(4, 8, KEY_C), \
+        KEY(5, 0, KEY_V), \
+        KEY(5, 1, KEY_B), \
+        KEY(5, 2, KEY_N), \
+        KEY(5, 3, KEY_M), \
+        KEY(5, 4, KEY_COMMA), \
+        KEY(5, 5, KEY_DOT), \
+        KEY(5, 6, KEY_SLASH), \
+        KEY(5, 7, KEY_RIGHTSHIFT), \
+        KEY(5, 8, KEY_KPASTERISK), \
+        KEY(6, 0, KEY_LEFTALT), \
+        KEY(6, 1, KEY_SPACE), \
+        KEY(6, 2, KEY_CAPSLOCK), \
+        KEY(6, 3, KEY_F1), \
+        KEY(6, 4, KEY_F2), \
+        KEY(6, 5, KEY_F3), \
+        KEY(6, 6, KEY_F4), \
+        KEY(6, 7, KEY_F5), \
+        KEY(6, 8, KEY_F6), \
+        KEY(7, 0, KEY_F7), \
+        KEY(7, 1, KEY_F8), \
+        KEY(7, 2, KEY_F9), \
+        KEY(7, 3, KEY_F10), \
+        KEY(7, 4, KEY_NUMLOCK), \
+        KEY(7, 5, KEY_SCROLLLOCK), \
+        KEY(7, 6, KEY_KP7), \
+        KEY(7, 7, KEY_KP8), \
+        KEY(7, 8, KEY_KP9), \
+        KEY(8, 0, KEY_KPMINUS), \
+        KEY(8, 1, KEY_KP4), \
+        KEY(8, 2, KEY_KP5), \
+        KEY(8, 3, KEY_KP6), \
+        KEY(8, 4, KEY_KPPLUS), \
+        KEY(8, 5, KEY_KP1), \
+        KEY(8, 6, KEY_KP2), \
+        KEY(8, 7, KEY_KP3), \
+        KEY(8, 8, KEY_KP0), \
+}
+
+/**
+ * struct kbd_platform_data - spear keyboard platform data
+ * keymap: pointer to keymap data (table and size)
+ * rep: enables key autorepeat
+ *
+ * This structure is supposed to be used by platform code to supply
+ * keymaps to drivers that implement keyboards.
+ */
+struct kbd_platform_data {
+        const struct matrix_keymap_data *keymap;
+        bool rep;
+};
+
+/* This function is used to set platform data field of pdev->dev */
+static inline void
+kbd_set_plat_data(struct platform_device *pdev, struct kbd_platform_data *data)
+{
+        pdev->dev.platform_data = data;
+}
+
+#endif /* __PLAT_KEYBOARD_H */
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index ab211652e4ca..839c88df9994 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -81,8 +81,6 @@ static struct clocksource clksrc = {
         .rating = 200,          /* its a pretty decent clock */
         .read = clocksource_read_cycles,
         .mask = 0xFFFF,         /* 16 bits */
-        .mult = 0,              /* to be computed */
-        .shift = 0,             /* to be computed */
         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -105,10 +103,8 @@ static void spear_clocksource_init(void)
         val |= CTRL_ENABLE ;
         writew(val, gpt_base + CR(CLKSRC));
 
-        clocksource_calc_mult_shift(&clksrc, tick_rate, SPEAR_MIN_RANGE);
-
         /* register the clocksource */
-        clocksource_register(&clksrc);
+        clocksource_register_hz(&clksrc, tick_rate);
 }
 
 static struct clock_event_device clkevt = {
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
index e593a2a801c6..2e712e17ce72 100644
--- a/arch/arm/plat-stmp3xxx/clock.c
+++ b/arch/arm/plat-stmp3xxx/clock.c
@@ -25,9 +25,9 @@
 #include <linux/err.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/clkdev.h>
 
 #include <asm/mach-types.h>
-#include <asm/clkdev.h>
 #include <mach/platform.h>
 #include <mach/regs-clkctrl.h>
 
diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c
index 063c7bc0e740..c395630a6edc 100644
--- a/arch/arm/plat-stmp3xxx/timer.c
+++ b/arch/arm/plat-stmp3xxx/timer.c
@@ -89,7 +89,6 @@ static struct clocksource cksrc_stmp3xxx = {
         .rating         = 250,
         .read           = stmp3xxx_clock_read,
         .mask           = CLOCKSOURCE_MASK(16),
-        .shift          = 10,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -106,8 +105,6 @@ static struct irqaction stmp3xxx_timer_irq = {
  */
 static void __init stmp3xxx_init_timer(void)
 {
-        cksrc_stmp3xxx.mult = clocksource_hz2mult(CLOCK_TICK_RATE,
-                                cksrc_stmp3xxx.shift);
         ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
                                 ckevt_timrot.shift);
         ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
@@ -140,7 +137,7 @@ static void __init stmp3xxx_init_timer(void)
 
         setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
 
-        clocksource_register(&cksrc_stmp3xxx);
+        clocksource_register_hz(&cksrc_stmp3xxx, CLOCK_TICK_RATE);
         clockevents_register_device(&ckevt_timrot);
 }
 
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 5cf88e8427b1..16dde0819934 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,7 +1,7 @@
 obj-y   := clock.o
-obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
-obj-$(CONFIG_ARCH_REALVIEW) += sched-clock.o
-obj-$(CONFIG_ARCH_VERSATILE) += sched-clock.o
+ifneq ($(CONFIG_ARCH_INTEGRATOR),y)
+obj-y   += sched-clock.o
+endif
 ifeq ($(CONFIG_LEDS_CLASS),y)
 obj-$(CONFIG_ARCH_REALVIEW) += leds.o
 obj-$(CONFIG_ARCH_VERSATILE) += leds.o
diff --git a/arch/arm/plat-versatile/include/plat/sched_clock.h b/arch/arm/plat-versatile/include/plat/sched_clock.h
new file mode 100644
index 000000000000..5c3e4fc9fa0c
--- /dev/null
+++ b/arch/arm/plat-versatile/include/plat/sched_clock.h
@@ -0,0 +1,6 @@
+#ifndef ARM_PLAT_SCHED_CLOCK_H
+#define ARM_PLAT_SCHED_CLOCK_H
+
+void versatile_sched_clock_init(void __iomem *, unsigned long);
+
+#endif
diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatile/sched-clock.c
index 9768cf7e83d7..3d6a4c292cab 100644
--- a/arch/arm/plat-versatile/sched-clock.c
+++ b/arch/arm/plat-versatile/sched-clock.c
@@ -18,36 +18,41 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#include <linux/cnt32_to_63.h>
 #include <linux/io.h>
-#include <asm/div64.h>
+#include <linux/sched.h>
 
-#include <mach/hardware.h>
-#include <mach/platform.h>
+#include <asm/sched_clock.h>
+#include <plat/sched_clock.h>
 
-#ifdef VERSATILE_SYS_BASE
-#define REFCOUNTER      (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
-#endif
-
-#ifdef REALVIEW_SYS_BASE
-#define REFCOUNTER      (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_24MHz_OFFSET)
-#endif
+static DEFINE_CLOCK_DATA(cd);
+static void __iomem *ctr;
 
 /*
- * This is the Realview and Versatile sched_clock implementation.  This
- * has a resolution of 41.7ns, and a maximum value of about 35583 days.
- *
- * The return value is guaranteed to be monotonic in that range as
- * long as there is always less than 89 seconds between successive
- * calls to this function.
+ * Constants generated by clocks_calc_mult_shift(m, s, 24MHz, NSEC_PER_SEC, 60).
+ * This gives a resolution of about 41ns and a wrap period of about 178s.
  */
-unsigned long long sched_clock(void)
+#define SC_MULT         2796202667u
+#define SC_SHIFT        26
+
+unsigned long long notrace sched_clock(void)
 {
-        unsigned long long v = cnt32_to_63(readl(REFCOUNTER));
+        if (ctr) {
+                u32 cyc = readl(ctr);
+                return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0,
+                                                SC_MULT, SC_SHIFT);
+        } else
+                return 0;
+}
 
-        /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
-        v *= 125<<1;
-        do_div(v, 3<<1);
+static void notrace versatile_update_sched_clock(void)
+{
+        u32 cyc = readl(ctr);
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
 
-        return v;
+void __init versatile_sched_clock_init(void __iomem *reg, unsigned long rate)
+{
+        ctr = reg;
+        init_fixed_sched_clock(&cd, versatile_update_sched_clock,
+                               32, rate, SC_MULT, SC_SHIFT);
 }
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 8063a322c790..0797cb528b46 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -10,9 +10,12 @@
  */
 #include <linux/module.h>
 #include <linux/types.h>
+#include <linux/cpu.h>
 #include <linux/kernel.h>
+#include <linux/notifier.h>
 #include <linux/signal.h>
 #include <linux/sched.h>
+#include <linux/smp.h>
 #include <linux/init.h>
 
 #include <asm/cputype.h>
@@ -484,7 +487,24 @@ void vfp_flush_hwstate(struct thread_info *thread)
         put_cpu();
 }
 
-#include <linux/smp.h>
+/*
+ * VFP hardware can lose all context when a CPU goes offline.
+ * Safely clear our held state when a CPU has been killed, and
+ * re-enable access to VFP when the CPU comes back online.
+ *
+ * Both CPU_DYING and CPU_STARTING are called on the CPU which
+ * is being offlined/onlined.
+ */
+static int vfp_hotplug(struct notifier_block *b, unsigned long action,
+        void *hcpu)
+{
+        if (action == CPU_DYING || action == CPU_DYING_FROZEN) {
+                unsigned int cpu = (long)hcpu;
+                last_VFP_context[cpu] = NULL;
+        } else if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
+                vfp_enable(NULL);
+        return NOTIFY_OK;
+}
 
 /*
  * VFP support code initialisation.
@@ -514,6 +534,8 @@ static int __init vfp_init(void)
         else if (vfpsid & FPSID_NODOUBLE) {
                 printk("no double precision support\n");
         } else {
+                hotcpu_notifier(vfp_hotplug, 0);
+
                 smp_call_function(vfp_enable, NULL, 1);
 
                 VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT;  /* Extract the architecture version */
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 46738d49b7c8..46f42b2066e5 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -19,7 +19,7 @@ KBUILD_CFLAGS           += -mlong-calls
 endif
 KBUILD_AFLAGS           += $(call cc-option,-mno-fdpic)
 KBUILD_CFLAGS_MODULE    += -mlong-calls
-KBUILD_LDFLAGS_MODULE   += -m elf32bfin
+LDFLAGS                 += -m elf32bfin
 KALLSYMS         += --symbol-prefix=_
 
 KBUILD_DEFCONFIG := BF537-STAMP_defconfig
@@ -97,8 +97,11 @@ rev-$(CONFIG_BF_REV_0_6)  := 0.6
 rev-$(CONFIG_BF_REV_NONE) := none
 rev-$(CONFIG_BF_REV_ANY)  := any
 
-KBUILD_CFLAGS += -mcpu=$(cpu-y)-$(rev-y)
-KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y)
+CPU_REV := $(cpu-y)-$(rev-y)
+export CPU_REV
+
+KBUILD_CFLAGS += -mcpu=$(CPU_REV)
+KBUILD_AFLAGS += -mcpu=$(CPU_REV)
 
 # - we utilize the silicon rev from the toolchain, so move it over to the checkflags
 CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index 13d2dbd658e3..0a49279e3428 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -17,7 +17,7 @@ UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -a $(CONFIG_ROM_BASE) -x
 
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
-                   -C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' \
+                   -C $(2) -n '$(CPU_REV)-$(KERNELRELEASE)' \
                    -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
                    $(UIMAGE_OPTS-y) -d $< $@
 
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
new file mode 100644
index 000000000000..4cf451024fd8
--- /dev/null
+++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
@@ -0,0 +1,113 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_ELF_CORE is not set
+# CONFIG_FUTEX is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+CONFIG_SLAB=y
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_BF561=y
+CONFIG_SMP=y
+CONFIG_IRQ_TIMER0=10
+CONFIG_CLKIN_HZ=30000000
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
+CONFIG_BFIN_GPTIMERS=m
+CONFIG_C_CDPRIO=y
+CONFIG_BANK_3=0xAAC2
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+CONFIG_PM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_IRDA=m
+CONFIG_IRLAN=m
+CONFIG_IRCOMM=m
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRTTY_SIR=m
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_RAM=y
+CONFIG_MTD_ROM=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMC91X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT=m
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_BFIN_JTAG_COMM=m
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_SPI_BFIN=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_BFIN_WDT=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_JFFS2_FS=m
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_SMB_FS=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_MMRS=y
+CONFIG_DEBUG_HWERR=y
+CONFIG_EXACT_HWERR=y
+CONFIG_DEBUG_DOUBLEFAULT=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CPLB_INFO=y
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig
new file mode 100644
index 000000000000..0ebc7d9aa426
--- /dev/null
+++ b/arch/blackfin/configs/DNP5370_defconfig
@@ -0,0 +1,121 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="DNP5370"
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLOB=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_BF537=y
+CONFIG_BF_REV_0_3=y
+CONFIG_DNP5370=y
+CONFIG_IRQ_ERROR=7
+# CONFIG_CYCLES_CLOCKSOURCE is not set
+CONFIG_C_CDPRIO=y
+CONFIG_C_AMBEN_B0_B1_B2=y
+CONFIG_PM=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_LLC2=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=1
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_UCLINUX=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_NETDEVICES=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_BFIN_MAC=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_BFIN_DMA_INTERFACE is not set
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_BFIN_JTAG_COMM=y
+CONFIG_BFIN_JTAG_COMM_CONSOLE=y
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+CONFIG_SERIAL_BFIN_UART0=y
+CONFIG_LEGACY_PTY_COUNT=64
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_BLACKFIN_TWI=y
+CONFIG_SPI=y
+CONFIG_SPI_BFIN=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_SENSORS_LM75=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SPI=y
+CONFIG_DMADEVICES=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=850
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BOTH=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_LOCK_ALLOC=y
+CONFIG_DEBUG_KOBJECT=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_LIST=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_PAGE_POISONING=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_DOUBLEFAULT=y
+CONFIG_CPLB_INFO=y
+CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
new file mode 100644
index 000000000000..d51120744148
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_dma.h
@@ -0,0 +1,91 @@
+/*
+ * bfin_dma.h - Blackfin DMA defines/structures/etc...
+ *
+ * Copyright 2004-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BFIN_DMA_H__
+#define __ASM_BFIN_DMA_H__
+
+#include <linux/types.h>
+
+/* DMA_CONFIG Masks */
+#define DMAEN                   0x0001  /* DMA Channel Enable */
+#define WNR                             0x0002  /* Channel Direction (W/R*) */
+#define WDSIZE_8                0x0000  /* Transfer Word Size = 8 */
+#define WDSIZE_16               0x0004  /* Transfer Word Size = 16 */
+#define WDSIZE_32               0x0008  /* Transfer Word Size = 32 */
+#define DMA2D                   0x0010  /* DMA Mode (2D/1D*) */
+#define RESTART                 0x0020  /* DMA Buffer Clear */
+#define DI_SEL                  0x0040  /* Data Interrupt Timing Select */
+#define DI_EN                   0x0080  /* Data Interrupt Enable */
+#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1 */
+#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2 */
+#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3 */
+#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4 */
+#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5 */
+#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6 */
+#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7 */
+#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8 */
+#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9 */
+#define NDSIZE                  0x0f00  /* Next Descriptor Size */
+#define DMAFLOW                 0x7000  /* Flow Control */
+#define DMAFLOW_STOP    0x0000  /* Stop Mode */
+#define DMAFLOW_AUTO    0x1000  /* Autobuffer Mode */
+#define DMAFLOW_ARRAY   0x4000  /* Descriptor Array Mode */
+#define DMAFLOW_SMALL   0x6000  /* Small Model Descriptor List Mode */
+#define DMAFLOW_LARGE   0x7000  /* Large Model Descriptor List Mode */
+
+/* DMA_IRQ_STATUS Masks */
+#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status */
+#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status */
+#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator */
+#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator */
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+
+/*
+ * bfin dma registers layout
+ */
+struct bfin_dma_regs {
+        u32 next_desc_ptr;
+        u32 start_addr;
+        __BFP(config);
+        u32 __pad0;
+        __BFP(x_count);
+        __BFP(x_modify);
+        __BFP(y_count);
+        __BFP(y_modify);
+        u32 curr_desc_ptr;
+        u32 curr_addr;
+        __BFP(irq_status);
+        __BFP(peripheral_map);
+        __BFP(curr_x_count);
+        u32 __pad1;
+        __BFP(curr_y_count);
+        u32 __pad2;
+};
+
+/*
+ * bfin handshake mdma registers layout
+ */
+struct bfin_hmdma_regs {
+        __BFP(control);
+        __BFP(ecinit);
+        __BFP(bcinit);
+        __BFP(ecurgent);
+        __BFP(ecoverflow);
+        __BFP(ecount);
+        __BFP(bcount);
+};
+
+#undef __BFP
+
+#endif
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
new file mode 100644
index 000000000000..1ff9f1468c02
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -0,0 +1,275 @@
+/*
+ * bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_ASM_SERIAL_H__
+#define __BFIN_ASM_SERIAL_H__
+
+#include <linux/serial_core.h>
+#include <mach/anomaly.h>
+#include <mach/bfin_serial.h>
+
+#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
+    defined(CONFIG_BFIN_UART1_CTSRTS) || \
+    defined(CONFIG_BFIN_UART2_CTSRTS) || \
+    defined(CONFIG_BFIN_UART3_CTSRTS)
+# ifdef BFIN_UART_BF54X_STYLE
+#  define CONFIG_SERIAL_BFIN_HARD_CTSRTS
+# else
+#  define CONFIG_SERIAL_BFIN_CTSRTS
+# endif
+#endif
+
+struct circ_buf;
+struct timer_list;
+struct work_struct;
+
+struct bfin_serial_port {
+        struct uart_port port;
+        unsigned int old_status;
+        int status_irq;
+#ifndef BFIN_UART_BF54X_STYLE
+        unsigned int lsr;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        int tx_done;
+        int tx_count;
+        struct circ_buf rx_dma_buf;
+        struct timer_list rx_dma_timer;
+        int rx_dma_nrows;
+        unsigned int tx_dma_channel;
+        unsigned int rx_dma_channel;
+        struct work_struct tx_dma_workqueue;
+#elif ANOMALY_05000363
+        unsigned int anomaly_threshold;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+        int scts;
+#endif
+#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
+        defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
+        int cts_pin;
+        int rts_pin;
+#endif
+};
+
+/* UART_LCR Masks */
+#define WLS(x)                   (((x)-5) & 0x03)  /* Word Length Select */
+#define STB                      0x04  /* Stop Bits */
+#define PEN                      0x08  /* Parity Enable */
+#define EPS                      0x10  /* Even Parity Select */
+#define STP                      0x20  /* Stick Parity */
+#define SB                       0x40  /* Set Break */
+#define DLAB                     0x80  /* Divisor Latch Access */
+
+/* UART_LSR Masks */
+#define DR                       0x01  /* Data Ready */
+#define OE                       0x02  /* Overrun Error */
+#define PE                       0x04  /* Parity Error */
+#define FE                       0x08  /* Framing Error */
+#define BI                       0x10  /* Break Interrupt */
+#define THRE                     0x20  /* THR Empty */
+#define TEMT                     0x40  /* TSR and UART_THR Empty */
+#define TFI                      0x80  /* Transmission Finished Indicator */
+
+/* UART_IER Masks */
+#define ERBFI                    0x01  /* Enable Receive Buffer Full Interrupt */
+#define ETBEI                    0x02  /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI                     0x04  /* Enable RX Status Interrupt */
+#define EDSSI                    0x08  /* Enable Modem Status Interrupt */
+#define EDTPTI                   0x10  /* Enable DMA Transmit PIRQ Interrupt */
+#define ETFI                     0x20  /* Enable Transmission Finished Interrupt */
+#define ERFCI                    0x40  /* Enable Receive FIFO Count Interrupt */
+
+/* UART_MCR Masks */
+#define XOFF                     0x01  /* Transmitter Off */
+#define MRTS                     0x02  /* Manual Request To Send */
+#define RFIT                     0x04  /* Receive FIFO IRQ Threshold */
+#define RFRT                     0x08  /* Receive FIFO RTS Threshold */
+#define LOOP_ENA                 0x10  /* Loopback Mode Enable */
+#define FCPOL                    0x20  /* Flow Control Pin Polarity */
+#define ARTS                     0x40  /* Automatic Request To Send */
+#define ACTS                     0x80  /* Automatic Clear To Send */
+
+/* UART_MSR Masks */
+#define SCTS                     0x01  /* Sticky CTS */
+#define CTS                      0x10  /* Clear To Send */
+#define RFCS                     0x20  /* Receive FIFO Count Status */
+
+/* UART_GCTL Masks */
+#define UCEN                     0x01  /* Enable UARTx Clocks */
+#define IREN                     0x02  /* Enable IrDA Mode */
+#define TPOLC                    0x04  /* IrDA TX Polarity Change */
+#define RPOLC                    0x08  /* IrDA RX Polarity Change */
+#define FPE                      0x10  /* Force Parity Error On Transmit */
+#define FFE                      0x20  /* Force Framing Error On Transmit */
+
+#ifdef BFIN_UART_BF54X_STYLE
+# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)        */
+# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)       */
+# define OFFSET_GCTL             0x08  /* Global Control Register         */
+# define OFFSET_LCR              0x0C  /* Line Control Register           */
+# define OFFSET_MCR              0x10  /* Modem Control Register          */
+# define OFFSET_LSR              0x14  /* Line Status Register            */
+# define OFFSET_MSR              0x18  /* Modem Status Register           */
+# define OFFSET_SCR              0x1C  /* SCR Scratch Register            */
+# define OFFSET_IER_SET          0x20  /* Set Interrupt Enable Register   */
+# define OFFSET_IER_CLEAR        0x24  /* Clear Interrupt Enable Register */
+# define OFFSET_THR              0x28  /* Transmit Holding register       */
+# define OFFSET_RBR              0x2C  /* Receive Buffer register         */
+#else /* BF533 style */
+# define OFFSET_THR              0x00  /* Transmit Holding register         */
+# define OFFSET_RBR              0x00  /* Receive Buffer register           */
+# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)          */
+# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)         */
+# define OFFSET_IER              0x04  /* Interrupt Enable Register         */
+# define OFFSET_IIR              0x08  /* Interrupt Identification Register */
+# define OFFSET_LCR              0x0C  /* Line Control Register             */
+# define OFFSET_MCR              0x10  /* Modem Control Register            */
+# define OFFSET_LSR              0x14  /* Line Status Register              */
+# define OFFSET_MSR              0x18  /* Modem Status Register             */
+# define OFFSET_SCR              0x1C  /* SCR Scratch Register              */
+# define OFFSET_GCTL             0x24  /* Global Control Register           */
+/* code should not need IIR, so force build error if they use it */
+# undef OFFSET_IIR
+#endif
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+struct bfin_uart_regs {
+#ifdef BFIN_UART_BF54X_STYLE
+        __BFP(dll);
+        __BFP(dlh);
+        __BFP(gctl);
+        __BFP(lcr);
+        __BFP(mcr);
+        __BFP(lsr);
+        __BFP(msr);
+        __BFP(scr);
+        __BFP(ier_set);
+        __BFP(ier_clear);
+        __BFP(thr);
+        __BFP(rbr);
+#else
+        union {
+                u16 dll;
+                u16 thr;
+                const u16 rbr;
+        };
+        const u16 __pad0;
+        union {
+                u16 dlh;
+                u16 ier;
+        };
+        const u16 __pad1;
+        const __BFP(iir);
+        __BFP(lcr);
+        __BFP(mcr);
+        __BFP(lsr);
+        __BFP(msr);
+        __BFP(scr);
+        const u32 __pad2;
+        __BFP(gctl);
+#endif
+};
+#undef __BFP
+
+#ifndef port_membase
+# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
+#endif
+
+#define UART_GET_CHAR(p)      bfin_read16(port_membase(p) + OFFSET_RBR)
+#define UART_GET_DLL(p)       bfin_read16(port_membase(p) + OFFSET_DLL)
+#define UART_GET_DLH(p)       bfin_read16(port_membase(p) + OFFSET_DLH)
+#define UART_GET_GCTL(p)      bfin_read16(port_membase(p) + OFFSET_GCTL)
+#define UART_GET_LCR(p)       bfin_read16(port_membase(p) + OFFSET_LCR)
+#define UART_GET_MCR(p)       bfin_read16(port_membase(p) + OFFSET_MCR)
+#define UART_GET_MSR(p)       bfin_read16(port_membase(p) + OFFSET_MSR)
+
+#define UART_PUT_CHAR(p, v)   bfin_write16(port_membase(p) + OFFSET_THR, v)
+#define UART_PUT_DLL(p, v)    bfin_write16(port_membase(p) + OFFSET_DLL, v)
+#define UART_PUT_DLH(p, v)    bfin_write16(port_membase(p) + OFFSET_DLH, v)
+#define UART_PUT_GCTL(p, v)   bfin_write16(port_membase(p) + OFFSET_GCTL, v)
+#define UART_PUT_LCR(p, v)    bfin_write16(port_membase(p) + OFFSET_LCR, v)
+#define UART_PUT_MCR(p, v)    bfin_write16(port_membase(p) + OFFSET_MCR, v)
+
+#ifdef BFIN_UART_BF54X_STYLE
+
+#define UART_CLEAR_IER(p, v)  bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
+#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER_SET)
+#define UART_SET_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
+
+#define UART_CLEAR_DLAB(p)    /* MMRs not muxed on BF54x */
+#define UART_SET_DLAB(p)      /* MMRs not muxed on BF54x */
+
+#define UART_CLEAR_LSR(p)     bfin_write16(port_membase(p) + OFFSET_LSR, -1)
+#define UART_GET_LSR(p)       bfin_read16(port_membase(p) + OFFSET_LSR)
+#define UART_PUT_LSR(p, v)    bfin_write16(port_membase(p) + OFFSET_LSR, v)
+
+/* This handles hard CTS/RTS */
+#define BFIN_UART_CTSRTS_HARD
+#define UART_CLEAR_SCTS(p)      bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
+#define UART_GET_CTS(x)         (UART_GET_MSR(x) & CTS)
+#define UART_DISABLE_RTS(x)     UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
+#define UART_ENABLE_RTS(x)      UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
+#define UART_ENABLE_INTS(x, v)  UART_SET_IER(x, v)
+#define UART_DISABLE_INTS(x)    UART_CLEAR_IER(x, 0xF)
+
+#else /* BF533 style */
+
+#define UART_CLEAR_IER(p, v)  UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
+#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER)
+#define UART_PUT_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER, v)
+#define UART_SET_IER(p, v)    UART_PUT_IER(p, UART_GET_IER(p) | (v))
+
+#define UART_CLEAR_DLAB(p)    do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
+#define UART_SET_DLAB(p)      do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
+
+#ifndef put_lsr_cache
+# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
+#endif
+#ifndef get_lsr_cache
+# define get_lsr_cache(p)    (((struct bfin_serial_port *)(p))->lsr)
+#endif
+
+/* The hardware clears the LSR bits upon read, so we need to cache
+ * some of the more fun bits in software so they don't get lost
+ * when checking the LSR in other code paths (TX).
+ */
+static inline void UART_CLEAR_LSR(void *p)
+{
+        put_lsr_cache(p, 0);
+        bfin_write16(port_membase(p) + OFFSET_LSR, -1);
+}
+static inline unsigned int UART_GET_LSR(void *p)
+{
+        unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
+        put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
+        return lsr | get_lsr_cache(p);
+}
+static inline void UART_PUT_LSR(void *p, uint16_t val)
+{
+        put_lsr_cache(p, get_lsr_cache(p) & ~val);
+}
+
+/* This handles soft CTS/RTS */
+#define UART_GET_CTS(x)        gpio_get_value((x)->cts_pin)
+#define UART_DISABLE_RTS(x)    gpio_set_value((x)->rts_pin, 1)
+#define UART_ENABLE_RTS(x)     gpio_set_value((x)->rts_pin, 0)
+#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+#define UART_DISABLE_INTS(x)   UART_PUT_IER(x, 0)
+
+#endif
+
+#ifndef BFIN_UART_TX_FIFO_SIZE
+# define BFIN_UART_TX_FIFO_SIZE 2
+#endif
+
+#endif /* __BFIN_ASM_SERIAL_H__ */
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 3f7ef4d97791..29f4fd886174 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -108,7 +108,9 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 #define smp_mb__before_clear_bit()      barrier()
 #define smp_mb__after_clear_bit()       barrier()
 
+#define test_bit __skip_test_bit
 #include <asm-generic/bitops/non-atomic.h>
+#undef test_bit
 
 #endif /* CONFIG_SMP */
 
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index bd0641a267f1..568885a2c286 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -7,6 +7,8 @@
 #ifndef __ARCH_BLACKFIN_CACHE_H
 #define __ARCH_BLACKFIN_CACHE_H
 
+#include <linux/linkage.h>      /* for asmlinkage */
+
 /*
  * Bytes per L1 cache line
  * Blackfin loads 32 bytes for cache
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 2666ff8ea952..77135b62818e 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -11,6 +11,9 @@
 
 #include <asm/blackfin.h>       /* for SSYNC() */
 #include <asm/sections.h>       /* for _ramend */
+#ifdef CONFIG_SMP
+#include <asm/smp.h>
+#endif
 
 extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
 extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index eedf3ca65ba2..d9dbc1a53534 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -14,40 +14,7 @@
 #include <asm/blackfin.h>
 #include <asm/page.h>
 #include <asm-generic/dma.h>
-
-/* DMA_CONFIG Masks */
-#define DMAEN                   0x0001  /* DMA Channel Enable */
-#define WNR                             0x0002  /* Channel Direction (W/R*) */
-#define WDSIZE_8                0x0000  /* Transfer Word Size = 8 */
-#define WDSIZE_16               0x0004  /* Transfer Word Size = 16 */
-#define WDSIZE_32               0x0008  /* Transfer Word Size = 32 */
-#define DMA2D                   0x0010  /* DMA Mode (2D/1D*) */
-#define RESTART                 0x0020  /* DMA Buffer Clear */
-#define DI_SEL                  0x0040  /* Data Interrupt Timing Select */
-#define DI_EN                   0x0080  /* Data Interrupt Enable */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1 */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2 */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3 */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4 */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5 */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6 */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7 */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8 */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9 */
-#define NDSIZE                  0x0f00  /* Next Descriptor Size */
-#define DMAFLOW                 0x7000  /* Flow Control */
-#define DMAFLOW_STOP    0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO    0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY   0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL   0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE   0x7000  /* Large Model Descriptor List Mode */
-
-/* DMA_IRQ_STATUS Masks */
-#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status */
-#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status */
-#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator */
-#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator */
+#include <asm/bfin_dma.h>
 
 /*-------------------------
  * config reg bits value
@@ -149,7 +116,7 @@ void blackfin_dma_resume(void);
 *       DMA API's
 *******************************************************************************/
 extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS];
+extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
 extern int channel2irq(unsigned int channel);
 
 static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index efcc3aebeae4..3047120cfcff 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -9,6 +9,8 @@
 #ifndef _BLACKFIN_DPMC_H_
 #define _BLACKFIN_DPMC_H_
 
+#include <mach/pll.h>
+
 /* PLL_CTL Masks */
 #define DF                      0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
 #define PLL_OFF                 0x0002  /* PLL Not Powered */
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 234fbac17ec1..dccae26805b0 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,148 +7,48 @@
 #ifndef _BFIN_IO_H
 #define _BFIN_IO_H
 
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
 #include <linux/compiler.h>
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the bfin architecture, we just read/write the
- * memory location directly.
- */
-#ifndef __ASSEMBLY__
-
-static inline unsigned char readb(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ (
-                "cli %1;"
-                "NOP; NOP; SSYNC;"
-                "%0 = b [%2] (z);"
-                "sti %1;"
-                : "=d"(val), "=d"(tmp)
-                : "a"(addr)
-        );
-
-        return (unsigned char) val;
-}
-
-static inline unsigned short readw(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ (
-                "cli %1;"
-                "NOP; NOP; SSYNC;"
-                "%0 = w [%2] (z);"
-                "sti %1;"
-                : "=d"(val), "=d"(tmp)
-                : "a"(addr)
-        );
-
-        return (unsigned short) val;
-}
-
-static inline unsigned int readl(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ (
-                "cli %1;"
-                "NOP; NOP; SSYNC;"
-                "%0 = [%2];"
-                "sti %1;"
-                : "=d"(val), "=d"(tmp)
-                : "a"(addr)
-        );
-
-        return val;
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+#define DECLARE_BFIN_RAW_READX(size, type, asm, asm_sign) \
+static inline type __raw_read##size(const volatile void __iomem *addr) \
+{ \
+        unsigned int val; \
+        int tmp; \
+        __asm__ __volatile__ ( \
+                "cli %1;" \
+                "NOP; NOP; SSYNC;" \
+                "%0 = "#asm" [%2] "#asm_sign";" \
+                "sti %1;" \
+                : "=d"(val), "=d"(tmp) \
+                : "a"(addr) \
+        ); \
+        return (type) val; \
 }
-
-#endif /*  __ASSEMBLY__ */
-
-#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define memset_io(a, b, c)      memset((void *)(a), (b), (c))
-#define memcpy_fromio(a, b, c)  memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a, b, c)    memcpy((void *)(a), (b), (c))
-
-/* Convert "I/O port addresses" to actual addresses.  i.e. ugly casts. */
-#define __io(port) ((void *)(unsigned long)(port))
-
-#define inb(port)    readb(__io(port))
-#define inw(port)    readw(__io(port))
-#define inl(port)    readl(__io(port))
-#define outb(x, port) writeb(x, __io(port))
-#define outw(x, port) writew(x, __io(port))
-#define outl(x, port) writel(x, __io(port))
-
-#define inb_p(port)    inb(__io(port))
-#define inw_p(port)    inw(__io(port))
-#define inl_p(port)    inl(__io(port))
-#define outb_p(x, port) outb(x, __io(port))
-#define outw_p(x, port) outw(x, __io(port))
-#define outl_p(x, port) outl(x, __io(port))
-
-#define ioread8_rep(a, d, c)    readsb(a, d, c)
-#define ioread16_rep(a, d, c)   readsw(a, d, c)
-#define ioread32_rep(a, d, c)   readsl(a, d, c)
-#define iowrite8_rep(a, s, c)   writesb(a, s, c)
-#define iowrite16_rep(a, s, c)  writesw(a, s, c)
-#define iowrite32_rep(a, s, c)  writesl(a, s, c)
-
-#define ioread8(x)                      readb(x)
-#define ioread16(x)                     readw(x)
-#define ioread32(x)                     readl(x)
-#define iowrite8(val, x)                writeb(val, x)
-#define iowrite16(val, x)               writew(val, x)
-#define iowrite32(val, x)               writel(val, x)
-
-/**
- * I/O write barrier
- *
- * Ensure ordering of I/O space writes. This will make sure that writes
- * following the barrier will arrive after all previous writes.
- */
-#define mmiowb() do { SSYNC(); wmb(); } while (0)
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/* Values for nocacheflag and cmode */
-#define IOMAP_NOCACHE_SER               1
-
-#ifndef __ASSEMBLY__
+DECLARE_BFIN_RAW_READX(b, u8, b, (z))
+#define __raw_readb __raw_readb
+DECLARE_BFIN_RAW_READX(w, u16, w, (z))
+#define __raw_readw __raw_readw
+DECLARE_BFIN_RAW_READX(l, u32, , )
+#define __raw_readl __raw_readl
 
 extern void outsb(unsigned long port, const void *addr, unsigned long count);
 extern void outsw(unsigned long port, const void *addr, unsigned long count);
 extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
 extern void outsl(unsigned long port, const void *addr, unsigned long count);
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
 
 extern void insb(unsigned long port, void *addr, unsigned long count);
 extern void insw(unsigned long port, void *addr, unsigned long count);
 extern void insw_8(unsigned long port, void *addr, unsigned long count);
 extern void insl(unsigned long port, void *addr, unsigned long count);
 extern void insl_16(unsigned long port, void *addr, unsigned long count);
+#define insb insb
+#define insw insw
+#define insl insl
 
 extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
 extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
@@ -158,108 +58,14 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count);
 extern void dma_insw(unsigned long port, void *addr, unsigned short count);
 extern void dma_insl(unsigned long port, void *addr, unsigned short count);
 
-static inline void readsl(const void __iomem *addr, void *buf, int len)
-{
-        insl((unsigned long)addr, buf, len);
-}
-
-static inline void readsw(const void __iomem *addr, void *buf, int len)
-{
-        insw((unsigned long)addr, buf, len);
-}
-
-static inline void readsb(const void __iomem *addr, void *buf, int len)
-{
-        insb((unsigned long)addr, buf, len);
-}
-
-static inline void writesl(const void __iomem *addr, const void *buf, int len)
-{
-        outsl((unsigned long)addr, buf, len);
-}
-
-static inline void writesw(const void __iomem *addr, const void *buf, int len)
-{
-        outsw((unsigned long)addr, buf, len);
-}
-
-static inline void writesb(const void __iomem *addr, const void *buf, int len)
-{
-        outsb((unsigned long)addr, buf, len);
-}
-
-/*
- * Map some physical address range into the kernel address space.
- */
-static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
-                                int cacheflag)
-{
-        return (void __iomem *)physaddr;
-}
-
-/*
- * Unmap a ioremap()ed region again
- */
-static inline void iounmap(void *addr)
-{
-}
-
-/*
- * __iounmap unmaps nearly everything, so be careful
- * it doesn't free currently pointer/page tables anymore but it
- * wans't used anyway and might be added later.
- */
-static inline void __iounmap(void *addr, unsigned long size)
-{
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
+/**
+ * I/O write barrier
+ *
+ * Ensure ordering of I/O space writes. This will make sure that writes
+ * following the barrier will arrive after all previous writes.
  */
-static inline void kernel_set_cachemode(void *addr, unsigned long size,
-                                        int cmode)
-{
-}
-
-static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void __iomem *ioremap_nocache(unsigned long physaddr,
-                                            unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
+#define mmiowb() do { SSYNC(); wmb(); } while (0)
 
-extern void blkfin_inv_cache_all(void);
+#include <asm-generic/io.h>
 
 #endif
-
-#define ioport_map(port, nr)            ((void __iomem*)(port))
-#define ioport_unmap(addr)
-
-/* Pages to physical address... */
-#define page_to_bus(page)       ((page - mem_map) << PAGE_SHIFT)
-
-#define phys_to_virt(vaddr)     ((void *) (vaddr))
-#define virt_to_phys(vaddr)     ((unsigned long) (vaddr))
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* _BFIN_IO_H */
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 41c4d70544ef..3365cb97f539 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -13,9 +13,6 @@
 #ifdef CONFIG_SMP
 # include <asm/pda.h>
 # include <asm/processor.h>
-/* Forward decl needed due to cdef inter dependencies */
-static inline uint32_t __pure bfin_dspid(void);
-# define blackfin_core_id() (bfin_dspid() & 0xff)
 # define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
 #else
 extern unsigned long bfin_irq_flags;
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
index aea880274de7..8af7772e84cc 100644
--- a/arch/blackfin/include/asm/processor.h
+++ b/arch/blackfin/include/asm/processor.h
@@ -14,7 +14,7 @@
 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
 
 #include <asm/ptrace.h>
-#include <asm/blackfin.h>
+#include <mach/blackfin.h>
 
 static inline unsigned long rdusp(void)
 {
@@ -134,6 +134,8 @@ static inline uint32_t __pure bfin_dspid(void)
         return bfin_read_DSPID();
 }
 
+#define blackfin_core_id() (bfin_dspid() & 0xff)
+
 static inline uint32_t __pure bfin_compiled_revid(void)
 {
 #if defined(CONFIG_BF_REV_0_0)
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index 1942ccfedbe0..1f286e71c21f 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -17,12 +17,12 @@ asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
 asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
 asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
 asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
-asmlinkage void arch_read_lock_asm(volatile int *ptr);
-asmlinkage int arch_read_trylock_asm(volatile int *ptr);
-asmlinkage void arch_read_unlock_asm(volatile int *ptr);
-asmlinkage void arch_write_lock_asm(volatile int *ptr);
-asmlinkage int arch_write_trylock_asm(volatile int *ptr);
-asmlinkage void arch_write_unlock_asm(volatile int *ptr);
+asmlinkage void __raw_read_lock_asm(volatile int *ptr);
+asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
+asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
+asmlinkage void __raw_write_lock_asm(volatile int *ptr);
+asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
+asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
 
 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
@@ -64,32 +64,36 @@ static inline int arch_write_can_lock(arch_rwlock_t *rw)
 
 static inline void arch_read_lock(arch_rwlock_t *rw)
 {
-        arch_read_lock_asm(&rw->lock);
+        __raw_read_lock_asm(&rw->lock);
 }
 
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+
 static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
-        return arch_read_trylock_asm(&rw->lock);
+        return __raw_read_trylock_asm(&rw->lock);
 }
 
 static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
-        arch_read_unlock_asm(&rw->lock);
+        __raw_read_unlock_asm(&rw->lock);
 }
 
 static inline void arch_write_lock(arch_rwlock_t *rw)
 {
-        arch_write_lock_asm(&rw->lock);
+        __raw_write_lock_asm(&rw->lock);
 }
 
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
 static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
-        return arch_write_trylock_asm(&rw->lock);
+        return __raw_write_trylock_asm(&rw->lock);
 }
 
 static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
-        arch_write_unlock_asm(&rw->lock);
+        __raw_write_unlock_asm(&rw->lock);
 }
 
 #define arch_spin_relax(lock)   cpu_relax()
diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h
new file mode 100644
index 000000000000..382178b361af
--- /dev/null
+++ b/arch/blackfin/include/mach-common/pll.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2005-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _MACH_COMMON_PLL_H
+#define _MACH_COMMON_PLL_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/blackfin.h>
+#include <asm/irqflags.h>
+
+#ifndef bfin_iwr_restore
+static inline void
+bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
+{
+#ifdef SIC_IWR
+        bfin_write_SIC_IWR(iwr0);
+#else
+        bfin_write_SIC_IWR0(iwr0);
+# ifdef SIC_IWR1
+        bfin_write_SIC_IWR1(iwr1);
+# endif
+# ifdef SIC_IWR2
+        bfin_write_SIC_IWR2(iwr2);
+# endif
+#endif
+}
+#endif
+
+#ifndef bfin_iwr_save
+static inline void
+bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
+              unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
+{
+#ifdef SIC_IWR
+        *iwr0 = bfin_read_SIC_IWR();
+#else
+        *iwr0 = bfin_read_SIC_IWR0();
+# ifdef SIC_IWR1
+        *iwr1 = bfin_read_SIC_IWR1();
+# endif
+# ifdef SIC_IWR2
+        *iwr2 = bfin_read_SIC_IWR2();
+# endif
+#endif
+        bfin_iwr_restore(niwr0, niwr1, niwr2);
+}
+#endif
+
+static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1, iwr2;
+
+        if (val == bfin_read_PLL_CTL())
+                return;
+
+        flags = hard_local_irq_save();
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
+
+        bfin_write16(addr, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_iwr_restore(iwr0, iwr1, iwr2);
+        hard_local_irq_restore(flags);
+}
+
+/* Writing to PLL_CTL initiates a PLL relock sequence */
+static inline void bfin_write_PLL_CTL(unsigned int val)
+{
+        _bfin_write_pll_relock(PLL_CTL, val);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence */
+static inline void bfin_write_VR_CTL(unsigned int val)
+{
+        _bfin_write_pll_relock(VR_CTL, val);
+}
+
+#endif
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h
new file mode 100644
index 000000000000..9f78a761c40a
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-a.h
@@ -0,0 +1,25 @@
+/*
+ * Port A Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_A__
+#define __BFIN_PERIPHERAL_PORT_A__
+
+#define PA0             (1 << 0)
+#define PA1             (1 << 1)
+#define PA2             (1 << 2)
+#define PA3             (1 << 3)
+#define PA4             (1 << 4)
+#define PA5             (1 << 5)
+#define PA6             (1 << 6)
+#define PA7             (1 << 7)
+#define PA8             (1 << 8)
+#define PA9             (1 << 9)
+#define PA10            (1 << 10)
+#define PA11            (1 << 11)
+#define PA12            (1 << 12)
+#define PA13            (1 << 13)
+#define PA14            (1 << 14)
+#define PA15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h
new file mode 100644
index 000000000000..b81702f09ec6
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-b.h
@@ -0,0 +1,25 @@
+/*
+ * Port B Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_B__
+#define __BFIN_PERIPHERAL_PORT_B__
+
+#define PB0             (1 << 0)
+#define PB1             (1 << 1)
+#define PB2             (1 << 2)
+#define PB3             (1 << 3)
+#define PB4             (1 << 4)
+#define PB5             (1 << 5)
+#define PB6             (1 << 6)
+#define PB7             (1 << 7)
+#define PB8             (1 << 8)
+#define PB9             (1 << 9)
+#define PB10            (1 << 10)
+#define PB11            (1 << 11)
+#define PB12            (1 << 12)
+#define PB13            (1 << 13)
+#define PB14            (1 << 14)
+#define PB15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h
new file mode 100644
index 000000000000..3cc665e0ba08
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-c.h
@@ -0,0 +1,25 @@
+/*
+ * Port C Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_C__
+#define __BFIN_PERIPHERAL_PORT_C__
+
+#define PC0             (1 << 0)
+#define PC1             (1 << 1)
+#define PC2             (1 << 2)
+#define PC3             (1 << 3)
+#define PC4             (1 << 4)
+#define PC5             (1 << 5)
+#define PC6             (1 << 6)
+#define PC7             (1 << 7)
+#define PC8             (1 << 8)
+#define PC9             (1 << 9)
+#define PC10            (1 << 10)
+#define PC11            (1 << 11)
+#define PC12            (1 << 12)
+#define PC13            (1 << 13)
+#define PC14            (1 << 14)
+#define PC15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h
new file mode 100644
index 000000000000..868c6a01f1b2
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-d.h
@@ -0,0 +1,25 @@
+/*
+ * Port D Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_D__
+#define __BFIN_PERIPHERAL_PORT_D__
+
+#define PD0             (1 << 0)
+#define PD1             (1 << 1)
+#define PD2             (1 << 2)
+#define PD3             (1 << 3)
+#define PD4             (1 << 4)
+#define PD5             (1 << 5)
+#define PD6             (1 << 6)
+#define PD7             (1 << 7)
+#define PD8             (1 << 8)
+#define PD9             (1 << 9)
+#define PD10            (1 << 10)
+#define PD11            (1 << 11)
+#define PD12            (1 << 12)
+#define PD13            (1 << 13)
+#define PD14            (1 << 14)
+#define PD15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h
new file mode 100644
index 000000000000..c88b0d0dd443
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-e.h
@@ -0,0 +1,25 @@
+/*
+ * Port E Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_E__
+#define __BFIN_PERIPHERAL_PORT_E__
+
+#define PE0             (1 << 0)
+#define PE1             (1 << 1)
+#define PE2             (1 << 2)
+#define PE3             (1 << 3)
+#define PE4             (1 << 4)
+#define PE5             (1 << 5)
+#define PE6             (1 << 6)
+#define PE7             (1 << 7)
+#define PE8             (1 << 8)
+#define PE9             (1 << 9)
+#define PE10            (1 << 10)
+#define PE11            (1 << 11)
+#define PE12            (1 << 12)
+#define PE13            (1 << 13)
+#define PE14            (1 << 14)
+#define PE15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h
new file mode 100644
index 000000000000..d6af20633278
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-f.h
@@ -0,0 +1,25 @@
+/*
+ * Port F Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_F__
+#define __BFIN_PERIPHERAL_PORT_F__
+
+#define PF0             (1 << 0)
+#define PF1             (1 << 1)
+#define PF2             (1 << 2)
+#define PF3             (1 << 3)
+#define PF4             (1 << 4)
+#define PF5             (1 << 5)
+#define PF6             (1 << 6)
+#define PF7             (1 << 7)
+#define PF8             (1 << 8)
+#define PF9             (1 << 9)
+#define PF10            (1 << 10)
+#define PF11            (1 << 11)
+#define PF12            (1 << 12)
+#define PF13            (1 << 13)
+#define PF14            (1 << 14)
+#define PF15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h
new file mode 100644
index 000000000000..09355d333c0e
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-g.h
@@ -0,0 +1,25 @@
+/*
+ * Port G Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_G__
+#define __BFIN_PERIPHERAL_PORT_G__
+
+#define PG0             (1 << 0)
+#define PG1             (1 << 1)
+#define PG2             (1 << 2)
+#define PG3             (1 << 3)
+#define PG4             (1 << 4)
+#define PG5             (1 << 5)
+#define PG6             (1 << 6)
+#define PG7             (1 << 7)
+#define PG8             (1 << 8)
+#define PG9             (1 << 9)
+#define PG10            (1 << 10)
+#define PG11            (1 << 11)
+#define PG12            (1 << 12)
+#define PG13            (1 << 13)
+#define PG14            (1 << 14)
+#define PG15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h
new file mode 100644
index 000000000000..fa3910c6fbd4
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-h.h
@@ -0,0 +1,25 @@
+/*
+ * Port H Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_H__
+#define __BFIN_PERIPHERAL_PORT_H__
+
+#define PH0             (1 << 0)
+#define PH1             (1 << 1)
+#define PH2             (1 << 2)
+#define PH3             (1 << 3)
+#define PH4             (1 << 4)
+#define PH5             (1 << 5)
+#define PH6             (1 << 6)
+#define PH7             (1 << 7)
+#define PH8             (1 << 8)
+#define PH9             (1 << 9)
+#define PH10            (1 << 10)
+#define PH11            (1 << 11)
+#define PH12            (1 << 12)
+#define PH13            (1 << 13)
+#define PH14            (1 << 14)
+#define PH15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h
new file mode 100644
index 000000000000..f176f08af624
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-i.h
@@ -0,0 +1,25 @@
+/*
+ * Port I Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_I__
+#define __BFIN_PERIPHERAL_PORT_I__
+
+#define PI0             (1 << 0)
+#define PI1             (1 << 1)
+#define PI2             (1 << 2)
+#define PI3             (1 << 3)
+#define PI4             (1 << 4)
+#define PI5             (1 << 5)
+#define PI6             (1 << 6)
+#define PI7             (1 << 7)
+#define PI8             (1 << 8)
+#define PI9             (1 << 9)
+#define PI10            (1 << 10)
+#define PI11            (1 << 11)
+#define PI12            (1 << 12)
+#define PI13            (1 << 13)
+#define PI14            (1 << 14)
+#define PI15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h
new file mode 100644
index 000000000000..924123ecec5a
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-j.h
@@ -0,0 +1,25 @@
+/*
+ * Port J Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_J__
+#define __BFIN_PERIPHERAL_PORT_J__
+
+#define PJ0             (1 << 0)
+#define PJ1             (1 << 1)
+#define PJ2             (1 << 2)
+#define PJ3             (1 << 3)
+#define PJ4             (1 << 4)
+#define PJ5             (1 << 5)
+#define PJ6             (1 << 6)
+#define PJ7             (1 << 7)
+#define PJ8             (1 << 8)
+#define PJ9             (1 << 9)
+#define PJ10            (1 << 10)
+#define PJ11            (1 << 11)
+#define PJ12            (1 << 12)
+#define PJ13            (1 << 13)
+#define PJ14            (1 << 14)
+#define PJ15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index bfe75af4e8bd..886e00014d75 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -116,7 +116,7 @@ void __init generate_cplb_tables_all(void)
             ((_ramend - uncached_end) >= 1 * 1024 * 1024))
                 dcplb_bounds[i_d].eaddr = uncached_end;
         else
-                dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024);
+                dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
         dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
         /* DMA uncached region.  */
         if (DMA_UNCACHED_REGION) {
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index edae461b1c54..eb92592fd80c 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -345,6 +345,23 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags)
 }
 #endif
 
+#ifdef CONFIG_IPIPE
+static unsigned long kgdb_arch_imask;
+#endif
+
+void kgdb_post_primary_code(struct pt_regs *regs, int e_vector, int err_code)
+{
+        if (kgdb_single_step)
+                preempt_enable();
+
+#ifdef CONFIG_IPIPE
+        if (kgdb_arch_imask) {
+                cpu_pda[raw_smp_processor_id()].ex_imask = kgdb_arch_imask;
+                kgdb_arch_imask = 0;
+        }
+#endif
+}
+
 int kgdb_arch_handle_exception(int vector, int signo,
                                int err_code, char *remcom_in_buffer,
                                char *remcom_out_buffer,
@@ -388,6 +405,12 @@ int kgdb_arch_handle_exception(int vector, int signo,
                          * kgdb_single_step > 0 means in single step mode
                          */
                         kgdb_single_step = i + 1;
+
+                        preempt_disable();
+#ifdef CONFIG_IPIPE
+                        kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
+                        cpu_pda[raw_smp_processor_id()].ex_imask = 0;
+#endif
                 }
 
                 bfin_correct_hw_break();
@@ -448,6 +471,9 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
 int kgdb_arch_init(void)
 {
         kgdb_single_step = 0;
+#ifdef CONFIG_IPIPE
+        kgdb_arch_imask = 0;
+#endif
 
         bfin_remove_all_hw_break();
         return 0;
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
index 08c0236acf3c..2a6e9dbb62a5 100644
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -95,6 +95,10 @@ static int __init kgdbtest_init(void)
 {
         struct proc_dir_entry *entry;
 
+#if L2_LENGTH
+        num2 = 0;
+#endif
+
         entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
         if (entry == NULL)
                 return -ENOMEM;
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index b894c8abe7ec..c0ccadcfa44e 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -104,24 +104,23 @@ static const unsigned short bfin_mac_peripherals[] = {
 
 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
         {
-                .addr = 1,
-                .irq = IRQ_MAC_PHYINT,
-        },
-        {
-                .addr = 2,
-                .irq = IRQ_MAC_PHYINT,
-        },
-        {
+#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
                 .addr = 3,
+#else
+                .addr = 1,
+#endif
                 .irq = IRQ_MAC_PHYINT,
         },
 };
 
 static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
-        .phydev_number = 3,
+        .phydev_number = 1,
         .phydev_data = bfin_phydev_data,
         .phy_mode = PHY_INTERFACE_MODE_MII,
         .mac_peripherals = bfin_mac_peripherals,
+#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
+        .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
+#endif
 };
 
 static struct platform_device bfin_mii_bus = {
@@ -453,7 +452,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -496,7 +495,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -636,9 +635,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -670,9 +669,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index e6ce1d7c523a..50fc5c89e379 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -377,7 +377,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -420,7 +420,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -547,9 +547,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -581,9 +581,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c
index 78b43605a0b5..bcd1fbc8c543 100644
--- a/arch/blackfin/mach-bf518/dma.c
+++ b/arch/blackfin/mach-bf518/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      2
+
+#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
index 970d310021e7..f6d924ac0c44 100644
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
-#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
-#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
-#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
-#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
-#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
@@ -54,50 +27,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port port;
-        unsigned int old_status;
-        int status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int tx_done;
-        int tx_count;
-        struct circ_buf rx_dma_buf;
-        struct timer_list rx_dma_timer;
-        int rx_dma_nrows;
-        unsigned int tx_dma_channel;
-        unsigned int rx_dma_channel;
-        struct work_struct tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list cts_timer;
-        int cts_pin;
-        int rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long uart_base_addr;
         int uart_irq;
@@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
index 9053462be4b1..a8828863226e 100644
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -1,61 +1,43 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_BLACKFIN_H_
 #define _MACH_BLACKFIN_H_
 
 #include "bf518.h"
-#include "defBF512.h"
 #include "anomaly.h"
 
-#if defined(CONFIG_BF518)
-#include "defBF518.h"
+#include <asm/def_LPBlackfin.h>
+#ifdef CONFIG_BF512
+# include "defBF512.h"
 #endif
-
-#if defined(CONFIG_BF516)
-#include "defBF516.h"
-#endif
-
-#if defined(CONFIG_BF514)
-#include "defBF514.h"
+#ifdef CONFIG_BF514
+# include "defBF514.h"
 #endif
-
-#if defined(CONFIG_BF512)
-#include "defBF512.h"
+#ifdef CONFIG_BF516
+# include "defBF516.h"
 #endif
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF512.h"
-
-#if defined(CONFIG_BF518)
-#include "cdefBF518.h"
+#ifdef CONFIG_BF518
+# include "defBF518.h"
 #endif
 
-#if defined(CONFIG_BF516)
-#include "cdefBF516.h"
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# ifdef CONFIG_BF512
+#  include "cdefBF512.h"
+# endif
+# ifdef CONFIG_BF514
+#  include "cdefBF514.h"
+# endif
+# ifdef CONFIG_BF516
+#  include "cdefBF516.h"
+# endif
+# ifdef CONFIG_BF518
+#  include "cdefBF518.h"
+# endif
 #endif
 
-#if defined(CONFIG_BF514)
-#include "cdefBF514.h"
-#endif
-#endif
-
-#define BFIN_UART_NR_PORTS      2
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
 #endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
index 493020d0a65a..b657d37a3402 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,15 +7,1037 @@
 #ifndef _CDEF_BF512_H
 #define _CDEF_BF512_H
 
-/* include all Core registers and bit definitions */
-#include "defBF512.h"
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
+#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
+#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
 
-/* include core specific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define bfin_read_SWRST()                       bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
+#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
 
-/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "cdefBF51x_base.h"
+#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
+#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
+#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
+#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
+
+#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
+
+#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
+#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
+#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
+
+#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
+#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
+#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
+
+/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
+
+#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
+#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
+#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
+
+/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
+#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
+#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
+#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
+#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
+#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
+#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
+#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
+
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
+
+#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
+
+#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
+
+#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
+
+#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
+
+#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
+
+#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
+
+#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
+
+#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
+#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
+#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
+#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
+#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
+#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
+#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
+#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
+#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
+#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
+#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
+
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
+#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX)
+#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX)
+#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
+
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
+#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX)
+#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX)
+#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
+#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
+
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define bfin_read_DMAC_TC_PER()                 bfin_read16(DMAC_TC_PER)
+#define bfin_write_DMAC_TC_PER(val)             bfin_write16(DMAC_TC_PER, val)
+#define bfin_read_DMAC_TC_CNT()                 bfin_read16(DMAC_TC_CNT)
+#define bfin_write_DMAC_TC_CNT(val)             bfin_write16(DMAC_TC_CNT, val)
+
+/* DMA Controller                                                                                                                                       */
+#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
+#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
+#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
+#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
+#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
+#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
+#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
+#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
+#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
+#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
+#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
+#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
+#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
+#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
+#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
+#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
+#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
+#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
+#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
+#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
+#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
+#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
+#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
+#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
+#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
+#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
+#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
+#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
+#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
+#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
+#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
+#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
+#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
+#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
+#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
+#define bfin_clear_PPI_STATUS()                 bfin_write_PPI_STATUS(0xFFFF)
+#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
+#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
+#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
+#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
+#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
+#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
+#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
+#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
+#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
+#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
+#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
+#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
+#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
+#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
+#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
+#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
+#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
+#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
+#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
+#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
+#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
+#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
+#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
+#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
+#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
+#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
+#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
+#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
+#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
+#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
+#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
+#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
+#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
+#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
+#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
+#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
+#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
+#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
+#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
+#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
+#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
+#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
+
+/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
+#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
+#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
+#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
+#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
+#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
+#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
+
+#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
+
+/* ==== end from cdefBF534.h ==== */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+
+#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
+#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
+#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
+
+#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
+#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
+#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
+#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
+#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
+#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
+#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
+#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
+#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
+#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
+#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
+#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
+#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
+#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
+#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
+#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
+#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
+#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
+#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
+#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
+#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
+#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
+#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
+
+/* HOST Port Registers */
+
+#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
+#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
+#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
+
+/* Counter Registers */
+
+#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
+#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
+#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
+#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
+#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
+#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
+#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
+#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
+
+/* Security Registers */
+
+#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
+#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
+#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
 
 #endif /* _CDEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
index 108fa4bde277..dc988668203e 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,9 +7,6 @@
 #ifndef _CDEF_BF514_H
 #define _CDEF_BF514_H
 
-/* include all Core registers and bit definitions */
-#include "defBF514.h"
-
 /* BF514 is BF512 + RSI */
 #include "cdefBF512.h"
 
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
index 2751592ef1c1..142e45cbc253 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,9 +7,6 @@
 #ifndef _CDEF_BF516_H
 #define _CDEF_BF516_H
 
-/* include all Core registers and bit definitions */
-#include "defBF516.h"
-
 /* BF516 is BF514 + EMAC */
 #include "cdefBF514.h"
 
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
index 7fb7f0eab990..e638197bf8b1 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,9 +7,6 @@
 #ifndef _CDEF_BF518_H
 #define _CDEF_BF518_H
 
-/* include all Core registers and bit definitions */
-#include "defBF518.h"
-
 /* BF518 is BF516 + IEEE-1588 */
 #include "cdefBF516.h"
 
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
deleted file mode 100644
index e16969f24ffd..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ /dev/null
@@ -1,1061 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF52X_H
-#define _CDEF_BF52X_H
-
-#include <asm/blackfin.h>
-
-#include "defBF51x_base.h"
-
-/* Include core specific register pointer definitions                                                           */
-#include <asm/cdef_LPBlackfin.h>
-
-/* ==== begin from cdefBF534.h ==== */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define bfin_read_SWRST()                       bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
-#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
-#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
-#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
-#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
-#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define bfin_read_DMA_TC_PER()                  bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)              bfin_write16(DMA_TC_PER, val)
-#define bfin_read_DMA_TC_CNT()                  bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)              bfin_write16(DMA_TC_CNT, val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TCPER()                   bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)               bfin_write16(DMA_TCPER, val)
-#define bfin_read_DMA_TCCNT()                   bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)               bfin_write16(DMA_TCCNT, val)
-
-/* DMA Controller                                                                                                                                       */
-#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
-#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS()                 bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
-#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
-#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
-#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
-#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
-
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
index 9b505bb0cb2d..27285823fb25 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,12 +7,1388 @@
 #ifndef _DEF_BF512_H
 #define _DEF_BF512_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
+/* ************************************************************** */
+/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x    */
+/* ************************************************************** */
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
+#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
+#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register                           */
+#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
+#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
+#define CHIPID                          0xFFC00014      /* Device ID Register */
 
-/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "defBF51x_base.h"
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                                */
+#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
+#define SYSCR                           0xFFC00104      /* System Configuration Register                                */
+#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register                      */
+
+#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
+#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                              */
+#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                              */
+#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                              */
+#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                              */
+#define SIC_ISR0                        0xFFC00120      /* Interrupt Status Register                                    */
+#define SIC_IWR0                        0xFFC00124      /* Interrupt Wakeup Register                                    */
+
+/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
+#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
+#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
+#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
+#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
+#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
+#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
+
+
+/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
+#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
+#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
+#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
+#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
+#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
+#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
+#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
+#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
+#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
+#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
+#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
+#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
+#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
+#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
+#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
+#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
+#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
+#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
+#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
+#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
+
+/* SPI0 Controller                      (0xFFC00500 - 0xFFC005FF)                                                       */
+#define SPI0_REGBASE                    0xFFC00500
+#define SPI0_CTL                        0xFFC00500      /* SPI Control Register                                         */
+#define SPI0_FLG                        0xFFC00504      /* SPI Flag register                                            */
+#define SPI0_STAT                       0xFFC00508      /* SPI Status register                                          */
+#define SPI0_TDBR                       0xFFC0050C      /* SPI Transmit Data Buffer Register                            */
+#define SPI0_RDBR                       0xFFC00510      /* SPI Receive Data Buffer Register                             */
+#define SPI0_BAUD                       0xFFC00514      /* SPI Baud rate Register                                       */
+#define SPI0_SHADOW                     0xFFC00518      /* SPI_RDBR Shadow Register                                     */
+
+/* SPI1 Controller                      (0xFFC03400 - 0xFFC034FF)                                                       */
+#define SPI1_REGBASE                    0xFFC03400
+#define SPI1_CTL                        0xFFC03400      /* SPI Control Register                                         */
+#define SPI1_FLG                        0xFFC03404      /* SPI Flag register                                            */
+#define SPI1_STAT                       0xFFC03408      /* SPI Status register                                          */
+#define SPI1_TDBR                       0xFFC0340C      /* SPI Transmit Data Buffer Register                            */
+#define SPI1_RDBR                       0xFFC03410      /* SPI Receive Data Buffer Register                             */
+#define SPI1_BAUD                       0xFFC03414      /* SPI Baud rate Register                                       */
+#define SPI1_SHADOW                     0xFFC03418      /* SPI_RDBR Shadow Register                                     */
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
+#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
+#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
+#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
+
+#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
+#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
+#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
+#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
+
+#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
+#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
+#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
+#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
+
+#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
+#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
+#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
+#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
+
+#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
+#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
+#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
+#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
+
+#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
+#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
+#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
+#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
+
+#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
+#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
+#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
+#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
+
+#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
+#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
+#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
+#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
+
+#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
+#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
+#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
+#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
+#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
+#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
+#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
+#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
+#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
+#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
+#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
+#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
+#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
+#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
+#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
+#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
+#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
+#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
+#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
+#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
+#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
+#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
+#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
+#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
+#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
+#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
+#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
+#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
+#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
+#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
+#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
+#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
+#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
+#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
+#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
+#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
+#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
+#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
+#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
+#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
+#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
+#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
+#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
+#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
+#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
+#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
+#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
+#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
+#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
+#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
+#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
+#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
+#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
+#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
+#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
+#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
+#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
+#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
+#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
+#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
+#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define DMAC_TC_PER                     0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMAC_TC_CNT                     0xFFC00B10      /* Traffic Control Current Counts Register      */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
+#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
+#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
+#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
+#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
+#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
+#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
+#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
+#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
+#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
+#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
+#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
+#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
+#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
+
+#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
+#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
+#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
+#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
+#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
+#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
+#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
+#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
+#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
+#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
+#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
+#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
+#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
+
+#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
+#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
+#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
+#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
+#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
+#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
+#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
+#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
+#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
+#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
+#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
+#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
+#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
+
+#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
+#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
+#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
+#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
+#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
+#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
+#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
+#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
+#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
+#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
+#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
+#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
+#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
+
+#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
+#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
+#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
+#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
+#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
+#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
+#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
+#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
+#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
+#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
+#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
+#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
+#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
+
+#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
+#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
+#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
+#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
+#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
+#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
+#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
+#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
+#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
+#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
+#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
+#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
+#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
+
+#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
+#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
+#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
+#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
+#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
+#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
+#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
+#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
+#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
+#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
+#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
+#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
+#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
+
+#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
+#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
+#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
+#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
+#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
+#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
+#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
+#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
+#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
+#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
+#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
+#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
+#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
+
+#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
+#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
+#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
+#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
+#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
+#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
+#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
+#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
+#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
+#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
+#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
+#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
+#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
+
+#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
+#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
+#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
+#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
+#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
+#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
+#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
+#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
+#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
+#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
+#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
+#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
+#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
+
+#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
+#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
+#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
+#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
+#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
+#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
+#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
+#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
+#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
+#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
+#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
+#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
+#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
+
+#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
+#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
+#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
+#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
+#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
+#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
+#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
+#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
+#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
+#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
+#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
+#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
+#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
+
+#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
+#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
+#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
+#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
+#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
+#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
+#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
+#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
+#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
+#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
+#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
+#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
+#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
+
+#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
+#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
+#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
+#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
+#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
+#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
+#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
+#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
+#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
+#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
+#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
+#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
+#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
+
+#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
+#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
+#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
+#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
+#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
+#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
+#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
+#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
+#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
+#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
+#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
+#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
+#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
+
+#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
+#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
+#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
+#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
+#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
+#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
+#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
+#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
+#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
+#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
+#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
+#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
+#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define TWI0_REGBASE                    0xFFC01400
+#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI0_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
+#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI0_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
+#define TWI0_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
+#define TWI0_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI0_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI0_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
+#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
+#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
+#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
+#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
+#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
+#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
+#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
+#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
+#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
+#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
+#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
+#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
+#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
+#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
+#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
+#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
+#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
+#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
+#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
+#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
+#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
+#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
+#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
+#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
+#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
+#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
+#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
+#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
+#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
+#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
+#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
+#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
+#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
+#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
+#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
+#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
+#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
+#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
+#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
+#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
+#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
+#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
+
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
+#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
+#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
+#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
+#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
+#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
+#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
+#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
+#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshold Register          */
+#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
+#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
+#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
+
+#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
+#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
+#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
+#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshold Register          */
+#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
+#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
+#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
+
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+#define PORTF_MUX               0xFFC03210      /* Port F mux control */
+#define PORTG_MUX               0xFFC03214      /* Port G mux control */
+#define PORTH_MUX               0xFFC03218      /* Port H mux control */
+#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
+#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
+#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
+#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
+#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
+#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
+#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
+#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
+#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
+#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
+#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
+#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
+
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* SWRST Masks                                                                                                                                          */
+#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
+#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
+#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
+#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
+#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
+
+/* SYSCR Masks                                                                                                                                                          */
+#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
+#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
+
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
+
+#if 0
+#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
+
+#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
+#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
+#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */
+#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */
+#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */
+#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
+#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
+
+#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
+#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
+#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
+#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */
+#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
+#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
+#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
+#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
+
+#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
+#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
+#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
+#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
+#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
+#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
+#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
+#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
+#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
+#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
+
+#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
+#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
+#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
+#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
+#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
+#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
+#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
+#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
+#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
+#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
+#endif
+
+/* SIC_IAR0 Macros                                                                                                                      */
+#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
+#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
+#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
+#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
+#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
+#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
+#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
+#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
+
+/* SIC_IAR1 Macros                                                                                                                      */
+#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
+#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
+#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
+#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
+#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
+#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
+#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
+#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
+
+/* SIC_IAR2 Macros                                                                                                                      */
+#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
+#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
+#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
+#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
+#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
+#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
+#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
+#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
+
+/* SIC_IAR3 Macros                                                                                                                      */
+#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
+#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
+#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
+#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
+#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
+#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
+#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
+#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
+
+
+/* SIC_IMASK Masks                                                                                                                                              */
+#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
+#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
+#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
+#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
+
+/* SIC_IWR Masks                                                                                                                                                */
+#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
+#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
+#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
+#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
+
+/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
+/* TIMER_ENABLE Masks                                                                                                   */
+#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
+#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
+#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
+#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
+#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
+#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
+#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
+#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
+
+/* TIMER_DISABLE Masks                                                                                                  */
+#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
+#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
+#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
+#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
+#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
+#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
+#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
+#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
+
+/* TIMER_STATUS Masks                                                                                                   */
+#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
+#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
+#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
+#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
+#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
+#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
+#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
+#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
+#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
+#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
+#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
+#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
+#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
+#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
+#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
+#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
+#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
+#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
+#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
+#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
+#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
+#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
+#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
+#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks                                                                                                  */
+#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
+#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
+#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
+#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
+#define PERIOD_CNT              0x0008  /* Period Count                                                 */
+#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
+#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
+#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
+#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
+#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
+#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
+#define ERR_TYP                 0xC000  /* Error Type                                                   */
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
+/* EBIU_AMGCTL Masks                                                                                                                                    */
+#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
+#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
+#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
+#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
+#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
+#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
+
+/* EBIU_AMBCTL0 Masks                                                                                                                                   */
+#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
+#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
+#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
+#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
+#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
+#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
+#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
+#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
+#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
+#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
+#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
+#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
+#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
+#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
+#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
+#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
+#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
+#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
+#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
+#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
+#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
+#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
+#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
+#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
+#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
+#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
+#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
+#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
+#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
+#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
+#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
+#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
+#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
+#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
+#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
+#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
+
+#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
+#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
+#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
+#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
+#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
+#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
+#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
+#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
+#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
+#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
+#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
+#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
+#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
+#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
+#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
+#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
+#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
+#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
+#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
+#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
+#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
+#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
+#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
+#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
+#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
+#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
+#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
+#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
+#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
+#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
+#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
+#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
+#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
+#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
+#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
+#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
+#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
+#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
+#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
+#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
+#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
+
+/* EBIU_AMBCTL1 Masks                                                                                                                                   */
+#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
+#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
+#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
+#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
+#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
+#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
+#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
+#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
+#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
+#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
+#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
+#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
+#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
+#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
+#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
+#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
+#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
+#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
+#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
+#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
+#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
+#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
+#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
+#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
+#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
+#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
+#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
+#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
+#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
+#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
+#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
+#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
+#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
+#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
+#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
+#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
+
+#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
+#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
+#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
+#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
+#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
+#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
+#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
+#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
+#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
+#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
+#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
+#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
+#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
+#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
+#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
+#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
+#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
+#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
+#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
+#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
+#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
+#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
+#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
+#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
+#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
+#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
+#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
+#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
+#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
+#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
+#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
+#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
+#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
+#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
+#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
+#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
+
+
+/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
+/* EBIU_SDGCTL Masks                                                                                                                                                    */
+#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
+#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
+#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
+#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
+#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
+#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
+#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
+#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
+#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
+#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
+#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
+#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
+#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
+#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
+#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
+#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
+#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
+#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
+#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
+#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
+#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
+#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
+#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
+#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
+#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
+#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
+#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
+#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
+#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
+#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
+#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
+#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
+#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
+#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
+#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
+#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
+#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
+#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
+#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
+#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
+#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
+#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
+#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
+#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
+
+/* EBIU_SDBCTL Masks                                                                                                                                            */
+#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
+#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
+#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
+#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
+#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
+#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
+#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
+#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
+#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
+#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
+#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
+
+/* EBIU_SDSTAT Masks                                                                                                            */
+#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
+#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
+#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
+#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
+#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
+#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
+
+
+/* **************************  DMA CONTROLLER MASKS  ********************************/
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
+#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
+#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
+#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
+#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
+#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
+#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
+#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
+#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
+#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
+#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
+#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
+#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
+#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
+#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
+
+/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
+/*  PPI_CONTROL Masks                                                                                                   */
+#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
+#define PORT_DIR                0x0002          /* PPI Port Direction                           */
+#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
+#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
+#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
+#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
+#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
+#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
+#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
+#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
+#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
+#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
+#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
+#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
+#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
+#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
+#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
+#define DLENGTH                 0x3800          /* PPI Data Length  */
+#define POLC                    0x4000          /* PPI Clock Polarity                           */
+#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
+
+/* PPI_STATUS Masks                                                                                                             */
+#define FLD                             0x0400          /* Field Indicator                                      */
+#define FT_ERR                  0x0800          /* Frame Track Error                            */
+#define OVR                             0x1000          /* FIFO Overflow Error                          */
+#define UNDR                    0x2000          /* FIFO Underrun Error                          */
+#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
+#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
+
+
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
+#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
+
+/* TWI_PRESCALE Masks                                                                                                                   */
+#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
+#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
+#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
+
+/* TWI_SLAVE_CTL Masks                                                                                                                  */
+#define SEN                     0x0001          /* Slave Enable                                                                 */
+#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
+#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
+#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
+
+/* TWI_SLAVE_STAT Masks                                                                                                                 */
+#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002          /* General Call Indicator                                               */
+
+/* TWI_MASTER_CTL Masks                                                                                                 */
+#define MEN                     0x0001          /* Master Mode Enable                                           */
+#define MADD_LEN        0x0002          /* Master Address Length                                        */
+#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
+#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
+#define STOP            0x0010          /* Issue Stop Condition                                         */
+#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
+#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
+#define SDAOVR          0x4000          /* Serial Data Override                                         */
+#define SCLOVR          0x8000          /* Serial Clock Override                                        */
+
+/* TWI_MASTER_STAT Masks                                                                                                                */
+#define MPROG           0x0001          /* Master Transfer In Progress                                  */
+#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
+#define ANAK            0x0004          /* Address Not Acknowledged                                             */
+#define DNAK            0x0008          /* Data Not Acknowledged                                                */
+#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
+#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
+#define SDASEN          0x0040          /* Serial Data Sense                                                    */
+#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
+#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
+#define SINIT           0x0001          /* Slave Transfer Initiated     */
+#define SCOMP           0x0002          /* Slave Transfer Complete      */
+#define SERR            0x0004          /* Slave Transfer Error         */
+#define SOVF            0x0008          /* Slave Overflow                       */
+#define MCOMP           0x0010          /* Master Transfer Complete     */
+#define MERR            0x0020          /* Master Transfer Error        */
+#define XMTSERV         0x0040          /* Transmit FIFO Service        */
+#define RCVSERV         0x0080          /* Receive FIFO Service         */
+
+/* TWI_FIFO_CTRL Masks                                                                                          */
+#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
+#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
+#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
+#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
+
+/* TWI_FIFO_STAT Masks                                                                                                                  */
+#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
+#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
+#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
+#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
+
+#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
+#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
+#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
+#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
+
+
+/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
+/* PORT_MUX Masks                                                                                                                       */
+#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
+#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
+#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
+
+#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
+#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
+#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
+#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
+
+#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
+#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
+#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
+
+#define PFTE                    0x0010                  /* Port F Timer Enable                          */
+#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
+#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
+
+#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
+#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
+#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
+
+#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
+#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
+#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
+
+#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
+#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
+#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
+
+#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
+#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
+#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
+
+#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
+#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
+#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
+
+#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
+#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
+#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
+
+#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
+#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
+#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
+
+
+/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
+/* HDMAx_CTL Masks                                                                                                              */
+#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
+#define REP                     0x0002  /* HDMA Request Polarity                                        */
+#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
+#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
+#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
+#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
+#define DRQ                     0x0300  /* HDMA Request Type                                            */
+#define DRQ_NONE        0x0000  /*              No Request                                                      */
+#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
+#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
+#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
+#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
+#define PS                      0x2000  /* HDMA Pin Status                                                      */
+#define OI                      0x4000  /* Overflow Interrupt Generated                         */
+#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
+
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define PGDE_UART   PFDE_UART
+#define PGDE_DMA    PFDE_DMA
+#define CKELOW          SCKELOW
+
+/* HOST Port Registers */
+
+#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
+#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
+#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
+
+/* Counter Registers */
+
+#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
+#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
+#define                       CNT_STATUS  0xffc03508   /* Status Register */
+#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
+#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
+#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
+#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
+#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
+
+/* OTP/FUSE Registers */
+
+#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
+#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
+#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
+#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
+
+/* Security Registers */
+
+#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
+#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
+#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+
+/* Motor Control PWM Registers */
+
+#define                         PWM_CTRL  0xffc03700   /* PWM Control Register */
+#define                         PWM_STAT  0xffc03704   /* PWM Status Register */
+#define                           PWM_TM  0xffc03708   /* PWM Period Register */
+#define                           PWM_DT  0xffc0370c   /* PWM Dead Time Register */
+#define                         PWM_GATE  0xffc03710   /* PWM Chopping Control */
+#define                          PWM_CHA  0xffc03714   /* PWM Channel A Duty Control */
+#define                          PWM_CHB  0xffc03718   /* PWM Channel B Duty Control */
+#define                          PWM_CHC  0xffc0371c   /* PWM Channel C Duty Control */
+#define                          PWM_SEG  0xffc03720   /* PWM Crossover and Output Enable */
+#define                       PWM_SYNCWT  0xffc03724   /* PWM Sync Pluse Width Control */
+#define                         PWM_CHAL  0xffc03728   /* PWM Channel AL Duty Control (SR mode only) */
+#define                         PWM_CHBL  0xffc0372c   /* PWM Channel BL Duty Control (SR mode only) */
+#define                         PWM_CHCL  0xffc03730   /* PWM Channel CL Duty Control (SR mode only) */
+#define                          PWM_LSI  0xffc03734   /* PWM Low Side Invert (SR mode only) */
+#define                        PWM_STAT2  0xffc03738   /* PWM Status Register 2 */
+
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for HOST_CONTROL */
+
+#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
+#define                  HOST_CNTR_nHOST_EN  0x0
+#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
+#define                 HOST_CNTR_nHOST_END  0x0
+#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
+#define                HOST_CNTR_nDATA_SIZE  0x0
+#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
+#define                 HOST_CNTR_nHOST_RST  0x0
+#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
+#define                 HOST_CNTR_nHRDY_OVR  0x0
+#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
+#define                 HOST_CNTR_nINT_MODE  0x0
+#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
+#define                   HOST_CNTR_ nBT_EN  0x0
+#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
+#define                      HOST_CNTR_nEHW  0x0
+#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
+#define                      HOST_CNTR_nEHR  0x0
+#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
+#define                      HOST_CNTR_nBDR  0x0
+
+/* Bit masks for HOST_STATUS */
+
+#define                     HOST_STAT_READY  0x1        /* DMA Ready */
+#define                    HOST_STAT_nREADY  0x0
+#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
+#define                 HOST_STAT_nFIFOFULL  0x0
+#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
+#define                HOST_STAT_nFIFOEMPTY  0x0
+#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
+#define                 HOST_STAT_nCOMPLETE  0x0
+#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
+#define                     HOST_STAT_nHSHK  0x0
+#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
+#define                  HOST_STAT_nTIMEOUT  0x0
+#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
+#define                     HOST_STAT_nHIRQ  0x0
+#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
+#define               HOST_STAT_nALLOW_CNFG  0x0
+#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
+#define                  HOST_STAT_nDMA_DIR  0x0
+#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
+#define                      HOST_STAT_nBTE  0x0
+#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
+#define              HOST_STAT_nHOSTRD_DONE  0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
+
+/* Bit masks for SECURE_SYSSWT */
+
+#define                   EMUDABL  0x1        /* Emulation Disable. */
+#define                  nEMUDABL  0x0
+#define                   RSTDABL  0x2        /* Reset Disable */
+#define                  nRSTDABL  0x0
+#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
+#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
+#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
+#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
+#define                  nDMA0OVR  0x0
+#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
+#define                  nDMA1OVR  0x0
+#define                    EMUOVR  0x4000     /* Emulation Override */
+#define                   nEMUOVR  0x0
+#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
+#define                   nOTPSEN  0x0
+#define                    L2DABL  0x70000    /* L2 Memory Disable. */
+
+/* Bit masks for SECURE_CONTROL */
+
+#define                   SECURE0  0x1        /* SECURE 0 */
+#define                  nSECURE0  0x0
+#define                   SECURE1  0x2        /* SECURE 1 */
+#define                  nSECURE1  0x0
+#define                   SECURE2  0x4        /* SECURE 2 */
+#define                  nSECURE2  0x0
+#define                   SECURE3  0x8        /* SECURE 3 */
+#define                  nSECURE3  0x0
+
+/* Bit masks for SECURE_STATUS */
+
+#define                   SECMODE  0x3        /* Secured Mode Control State */
+#define                       NMI  0x4        /* Non Maskable Interrupt */
+#define                      nNMI  0x0
+#define                   AFVALID  0x8        /* Authentication Firmware Valid */
+#define                  nAFVALID  0x0
+#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
+#define                   nAFEXIT  0x0
+#define                   SECSTAT  0xe0       /* Secure Status */
 
 #endif /* _DEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
deleted file mode 100644
index 5f84913dcd91..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ /dev/null
@@ -1,1495 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF51X_H
-#define _DEF_BF51X_H
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x    */
-/* ************************************************************** */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
-#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
-#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register                           */
-#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
-#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
-#define CHIPID                          0xFFC00014      /* Device ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                                */
-#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
-#define SYSCR                           0xFFC00104      /* System Configuration Register                                */
-#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register                      */
-
-#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
-#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                              */
-#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                              */
-#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                              */
-#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                              */
-#define SIC_ISR0                        0xFFC00120      /* Interrupt Status Register                                    */
-#define SIC_IWR0                        0xFFC00124      /* Interrupt Wakeup Register                                    */
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
-#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
-#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
-#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
-#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
-#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
-#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
-#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
-#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
-#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
-#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
-#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
-#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
-#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
-#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
-#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
-#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
-#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
-#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
-#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
-#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
-#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
-#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
-#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
-#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
-#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
-
-/* SPI0 Controller                      (0xFFC00500 - 0xFFC005FF)                                                       */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI0_CTL                        0xFFC00500      /* SPI Control Register                                         */
-#define SPI0_FLG                        0xFFC00504      /* SPI Flag register                                            */
-#define SPI0_STAT                       0xFFC00508      /* SPI Status register                                          */
-#define SPI0_TDBR                       0xFFC0050C      /* SPI Transmit Data Buffer Register                            */
-#define SPI0_RDBR                       0xFFC00510      /* SPI Receive Data Buffer Register                             */
-#define SPI0_BAUD                       0xFFC00514      /* SPI Baud rate Register                                       */
-#define SPI0_SHADOW                     0xFFC00518      /* SPI_RDBR Shadow Register                                     */
-
-/* SPI1 Controller                      (0xFFC03400 - 0xFFC034FF)                                                       */
-#define SPI1_REGBASE                    0xFFC03400
-#define SPI1_CTL                        0xFFC03400      /* SPI Control Register                                         */
-#define SPI1_FLG                        0xFFC03404      /* SPI Flag register                                            */
-#define SPI1_STAT                       0xFFC03408      /* SPI Status register                                          */
-#define SPI1_TDBR                       0xFFC0340C      /* SPI Transmit Data Buffer Register                            */
-#define SPI1_RDBR                       0xFFC03410      /* SPI Receive Data Buffer Register                             */
-#define SPI1_BAUD                       0xFFC03414      /* SPI Baud rate Register                                       */
-#define SPI1_SHADOW                     0xFFC03418      /* SPI_RDBR Shadow Register                                     */
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
-#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
-#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
-#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
-
-#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
-#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
-#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
-#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
-
-#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
-#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
-#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
-#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
-
-#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
-#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
-#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
-#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
-
-#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
-#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
-#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
-#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
-
-#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
-#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
-#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
-#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
-
-#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
-#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
-#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
-#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
-
-#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
-#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
-#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
-#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
-
-#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
-#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
-#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
-#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
-#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
-#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
-#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
-#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
-#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
-#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
-#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
-#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
-#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
-#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
-#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
-#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
-#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
-#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
-#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
-#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
-#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
-#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
-#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
-#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
-#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
-#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
-#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
-#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
-#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
-#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
-#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
-#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
-#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
-#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
-#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
-#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
-#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
-#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
-#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
-#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
-#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
-#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
-#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
-#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
-#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
-#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
-#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
-#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
-#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
-#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
-#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
-#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
-#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
-#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
-#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
-#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
-#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
-#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
-#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
-#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
-#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
-#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
-#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
-#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
-#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
-
-#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
-#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
-#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
-#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
-#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
-#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
-#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
-#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
-#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
-#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
-#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
-#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
-#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
-
-#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
-#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
-#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
-#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
-#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
-#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
-#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
-#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
-#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
-#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
-#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
-#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
-#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
-
-#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
-#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
-#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
-#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
-#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
-#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
-#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
-#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
-#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
-#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
-#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
-#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
-#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
-
-#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
-#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
-#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
-#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
-#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
-#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
-#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
-#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
-#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
-#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
-#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
-#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
-#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
-
-#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
-#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
-#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
-#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
-#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
-#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
-#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
-#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
-#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
-#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
-#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
-#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
-#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
-
-#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
-#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
-#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
-#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
-#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
-#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
-#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
-#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
-#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
-#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
-#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
-#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
-#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
-
-#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
-#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
-#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
-#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
-#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
-#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
-#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
-#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
-#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
-#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
-#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
-#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
-#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
-
-#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
-#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
-#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
-#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
-#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
-#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
-#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
-#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
-#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
-#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
-#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
-#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
-#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
-
-#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
-#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
-#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
-#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
-#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
-#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
-#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
-#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
-#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
-#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
-#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
-#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
-#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
-
-#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
-#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
-#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
-#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
-#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
-#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
-#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
-#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
-#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
-#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
-#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
-#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
-#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
-
-#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
-#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
-#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
-#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
-#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
-#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
-#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
-#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
-#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
-#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
-#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
-#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
-#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
-
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
-#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
-#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
-#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
-#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
-#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
-#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
-#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
-#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
-
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
-#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
-#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
-#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
-#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
-#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
-#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
-#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
-#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
-
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
-#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
-#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
-#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
-#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
-#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
-#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
-#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
-#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
-
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
-#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
-#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
-#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
-#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
-#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
-#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
-#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
-#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-#define TWI0_REGBASE                    0xFFC01400
-#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI0_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
-#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI0_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
-#define TWI0_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
-#define TWI0_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI0_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI0_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
-#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
-#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
-#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
-#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
-#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
-#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
-#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
-#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
-#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
-#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
-#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
-#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
-#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
-#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
-#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
-#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
-#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
-#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
-#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
-#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
-#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
-#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
-#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
-#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
-#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
-#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
-#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
-#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
-#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
-#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
-#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
-#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
-#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
-#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
-#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
-#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
-#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
-#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
-#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
-#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
-#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
-#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
-
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
-#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
-#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
-#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
-#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
-#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
-#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
-#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
-#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshold Register          */
-#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
-#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
-#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
-
-#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
-#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
-#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
-#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshold Register          */
-#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
-#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
-#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
-
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX               0xFFC03210      /* Port F mux control */
-#define PORTG_MUX               0xFFC03214      /* Port G mux control */
-#define PORTH_MUX               0xFFC03218      /* Port H mux control */
-#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
-#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
-#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
-#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
-#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
-#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
-#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
-#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* SWRST Masks                                                                                                                                          */
-#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
-#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
-
-/* SYSCR Masks                                                                                                                                                          */
-#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
-#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
-
-#if 0
-#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
-
-#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */
-#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */
-#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */
-#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
-#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
-
-#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
-#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
-#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
-#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */
-#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
-#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
-#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
-#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
-
-#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
-#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
-#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
-#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
-#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
-#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
-#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
-#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
-#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
-#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
-
-#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
-#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
-#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
-#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
-#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
-#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
-#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
-#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
-#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
-#endif
-
-/* SIC_IAR0 Macros                                                                                                                      */
-#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
-#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
-#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
-#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
-#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
-#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
-#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
-#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
-
-/* SIC_IAR1 Macros                                                                                                                      */
-#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
-#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
-#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
-#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
-#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
-#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
-#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
-#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
-
-/* SIC_IAR2 Macros                                                                                                                      */
-#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
-#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
-#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
-#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
-#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
-#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
-#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
-#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
-
-/* SIC_IAR3 Macros                                                                                                                      */
-#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
-#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
-#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
-#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
-#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
-#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
-#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
-#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
-
-
-/* SIC_IMASK Masks                                                                                                                                              */
-#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
-#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
-#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
-#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
-
-/* SIC_IWR Masks                                                                                                                                                */
-#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
-#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
-
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
-#define STB                     0x04                            /* Stop Bits                    */
-#define PEN                     0x08                            /* Parity Enable                */
-#define EPS                     0x10                            /* Even Parity Select   */
-#define STP                     0x20                            /* Stick Parity                 */
-#define SB                      0x40                            /* Set Break                    */
-#define DLAB            0x80                            /* Divisor Latch Access */
-
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA        0x10    /* Loopback Mode Enable */
-#define LOOP_ENA_P      0x04
-
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04            /* Enable RX Status Interrupt                           */
-
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01            /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02            /* UART_THR empty                               */
-#define IIR_RX_READY    0x04            /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06            /* Receive line status                          */
-#define IIR_STATUS      0x06            /* Highest Priority Pending Interrupt   */
-
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01            /* Enable UARTx Clocks                          */
-#define IREN            0x02            /* Enable IrDA Mode                                     */
-#define TPOLC           0x04            /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08            /* IrDA RX Polarity Change                      */
-#define FPE                     0x10            /* Force Parity Error On Transmit       */
-#define FFE                     0x20            /* Force Framing Error On Transmit      */
-
-
-/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
-/* TIMER_ENABLE Masks                                                                                                   */
-#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
-#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
-#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
-#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
-#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
-#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
-#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
-#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
-
-/* TIMER_DISABLE Masks                                                                                                  */
-#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
-#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
-#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
-#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
-#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
-#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
-#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
-#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
-
-/* TIMER_STATUS Masks                                                                                                   */
-#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
-#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
-#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
-#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
-#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
-#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
-#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
-#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
-#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
-#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
-#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
-#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
-#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
-#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
-#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
-#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
-#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
-#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
-#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
-#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
-#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
-#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
-#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
-#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks                                                                                                  */
-#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
-#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
-#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
-#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
-#define PERIOD_CNT              0x0008  /* Period Count                                                 */
-#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
-#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
-#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
-#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
-#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
-#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
-#define ERR_TYP                 0xC000  /* Error Type                                                   */
-
-
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks                                                                                                                                    */
-#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
-#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
-#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
-#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
-#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
-
-/* EBIU_AMBCTL0 Masks                                                                                                                                   */
-#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
-#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
-#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
-#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
-#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
-#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
-#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
-#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
-#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
-#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
-#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
-#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
-#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
-#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
-#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
-#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
-#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
-#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
-#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
-#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
-#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
-#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
-#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
-#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
-#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
-#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
-#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
-#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
-#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
-#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
-#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
-#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
-#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
-#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
-#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
-#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
-
-#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
-#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
-#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
-#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
-#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
-#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
-#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
-#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
-#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
-#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
-#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
-#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
-#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
-#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
-#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
-#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
-#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
-#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
-#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
-#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
-#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
-#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
-#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
-#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
-#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
-#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
-#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
-#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
-#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
-#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
-#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
-#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
-#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
-#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
-#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
-#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
-#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
-#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
-#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
-#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
-#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
-
-/* EBIU_AMBCTL1 Masks                                                                                                                                   */
-#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
-#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
-#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
-#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
-#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
-#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
-#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
-#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
-#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
-#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
-#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
-#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
-#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
-#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
-#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
-#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
-#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
-#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
-#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
-#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
-#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
-#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
-#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
-#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
-#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
-#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
-#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
-#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
-#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
-#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
-#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
-#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
-#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
-#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
-#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
-#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
-
-#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
-#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
-#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
-#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
-#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
-#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
-#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
-#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
-#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
-#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
-#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
-#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
-#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
-#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
-#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
-#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
-#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
-#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
-#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
-#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
-#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
-#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
-#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
-#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
-#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
-#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
-#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
-#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
-#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
-#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
-#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
-#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
-#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
-#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
-#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
-#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
-
-
-/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
-/* EBIU_SDGCTL Masks                                                                                                                                                    */
-#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
-#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
-#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
-#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
-#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
-#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
-#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
-#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
-#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
-#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
-#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
-#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
-
-/* EBIU_SDBCTL Masks                                                                                                                                            */
-#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
-#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
-#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
-#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
-#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
-#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
-#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
-#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
-#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
-#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
-#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
-
-/* EBIU_SDSTAT Masks                                                                                                            */
-#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
-#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
-#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
-#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
-#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
-#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
-
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
-#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
-#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
-#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
-#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
-#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
-#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
-#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
-#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
-#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
-#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
-#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
-#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
-#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
-
-/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/*  PPI_CONTROL Masks                                                                                                   */
-#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
-#define PORT_DIR                0x0002          /* PPI Port Direction                           */
-#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
-#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
-#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
-#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
-#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
-#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
-#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
-#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
-#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
-#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
-#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
-#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
-#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
-#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
-#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
-#define DLENGTH                 0x3800          /* PPI Data Length  */
-#define POLC                    0x4000          /* PPI Clock Polarity                           */
-#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
-
-/* PPI_STATUS Masks                                                                                                             */
-#define FLD                             0x0400          /* Field Indicator                                      */
-#define FT_ERR                  0x0800          /* Frame Track Error                            */
-#define OVR                             0x1000          /* FIFO Overflow Error                          */
-#define UNDR                    0x2000          /* FIFO Underrun Error                          */
-#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
-#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
-#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTL Masks                                                                                                                  */
-#define SEN                     0x0001          /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTL Masks                                                                                                 */
-#define MEN                     0x0001          /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002          /* Master Address Length                                        */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010          /* Issue Stop Condition                                         */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000          /* Serial Data Override                                         */
-#define SCLOVR          0x8000          /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001          /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004          /* Address Not Acknowledged                                             */
-#define DNAK            0x0008          /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
-#define SDASEN          0x0040          /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001          /* Slave Transfer Initiated     */
-#define SCOMP           0x0002          /* Slave Transfer Complete      */
-#define SERR            0x0004          /* Slave Transfer Error         */
-#define SOVF            0x0008          /* Slave Overflow                       */
-#define MCOMP           0x0010          /* Master Transfer Complete     */
-#define MERR            0x0020          /* Master Transfer Error        */
-#define XMTSERV         0x0040          /* Transmit FIFO Service        */
-#define RCVSERV         0x0080          /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
-
-
-/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
-/* PORT_MUX Masks                                                                                                                       */
-#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
-#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
-#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
-
-#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
-#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
-#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
-#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
-
-#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
-#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
-#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
-
-#define PFTE                    0x0010                  /* Port F Timer Enable                          */
-#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
-#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
-
-#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
-#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
-#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
-
-#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
-#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
-#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
-
-#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
-#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
-#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
-
-#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
-#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
-#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
-
-#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
-#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
-#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
-
-#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
-#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
-#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
-
-#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
-#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
-#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
-
-
-/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
-/* HDMAx_CTL Masks                                                                                                              */
-#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
-#define REP                     0x0002  /* HDMA Request Polarity                                        */
-#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
-#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
-#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
-#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
-#define DRQ                     0x0300  /* HDMA Request Type                                            */
-#define DRQ_NONE        0x0000  /*              No Request                                                      */
-#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
-#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
-#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
-#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
-#define PS                      0x2000  /* HDMA Pin Status                                                      */
-#define OI                      0x4000  /* Overflow Interrupt Generated                         */
-#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART   PFDE_UART
-#define PGDE_DMA    PFDE_DMA
-#define CKELOW          SCKELOW
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
-#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
-#define                       CNT_STATUS  0xffc03508   /* Status Register */
-#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
-#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
-#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
-#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
-#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
-#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
-#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
-#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
-#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
-#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Motor Control PWM Registers */
-
-#define                         PWM_CTRL  0xffc03700   /* PWM Control Register */
-#define                         PWM_STAT  0xffc03704   /* PWM Status Register */
-#define                           PWM_TM  0xffc03708   /* PWM Period Register */
-#define                           PWM_DT  0xffc0370c   /* PWM Dead Time Register */
-#define                         PWM_GATE  0xffc03710   /* PWM Chopping Control */
-#define                          PWM_CHA  0xffc03714   /* PWM Channel A Duty Control */
-#define                          PWM_CHB  0xffc03718   /* PWM Channel B Duty Control */
-#define                          PWM_CHC  0xffc0371c   /* PWM Channel C Duty Control */
-#define                          PWM_SEG  0xffc03720   /* PWM Crossover and Output Enable */
-#define                       PWM_SYNCWT  0xffc03724   /* PWM Sync Pluse Width Control */
-#define                         PWM_CHAL  0xffc03728   /* PWM Channel AL Duty Control (SR mode only) */
-#define                         PWM_CHBL  0xffc0372c   /* PWM Channel BL Duty Control (SR mode only) */
-#define                         PWM_CHCL  0xffc03730   /* PWM Channel CL Duty Control (SR mode only) */
-#define                          PWM_LSI  0xffc03734   /* PWM Low Side Invert (SR mode only) */
-#define                        PWM_STAT2  0xffc03738   /* PWM Status Register 2 */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
-#define                  HOST_CNTR_nHOST_EN  0x0
-#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
-#define                 HOST_CNTR_nHOST_END  0x0
-#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
-#define                HOST_CNTR_nDATA_SIZE  0x0
-#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
-#define                 HOST_CNTR_nHOST_RST  0x0
-#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
-#define                 HOST_CNTR_nHRDY_OVR  0x0
-#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
-#define                 HOST_CNTR_nINT_MODE  0x0
-#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
-#define                   HOST_CNTR_ nBT_EN  0x0
-#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
-#define                      HOST_CNTR_nEHW  0x0
-#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
-#define                      HOST_CNTR_nEHR  0x0
-#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
-#define                      HOST_CNTR_nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                     HOST_STAT_READY  0x1        /* DMA Ready */
-#define                    HOST_STAT_nREADY  0x0
-#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
-#define                 HOST_STAT_nFIFOFULL  0x0
-#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
-#define                HOST_STAT_nFIFOEMPTY  0x0
-#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
-#define                 HOST_STAT_nCOMPLETE  0x0
-#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
-#define                     HOST_STAT_nHSHK  0x0
-#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
-#define                  HOST_STAT_nTIMEOUT  0x0
-#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
-#define                     HOST_STAT_nHIRQ  0x0
-#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               HOST_STAT_nALLOW_CNFG  0x0
-#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
-#define                  HOST_STAT_nDMA_DIR  0x0
-#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
-#define                      HOST_STAT_nBTE  0x0
-#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
-#define              HOST_STAT_nHOSTRD_DONE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                  nEMUDABL  0x0
-#define                   RSTDABL  0x2        /* Reset Disable */
-#define                  nRSTDABL  0x0
-#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
-#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
-#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
-#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                  nDMA0OVR  0x0
-#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                  nDMA1OVR  0x0
-#define                    EMUOVR  0x4000     /* Emulation Override */
-#define                   nEMUOVR  0x0
-#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                   nOTPSEN  0x0
-#define                    L2DABL  0x70000    /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define                   SECURE0  0x1        /* SECURE 0 */
-#define                  nSECURE0  0x0
-#define                   SECURE1  0x2        /* SECURE 1 */
-#define                  nSECURE1  0x0
-#define                   SECURE2  0x4        /* SECURE 2 */
-#define                  nSECURE2  0x0
-#define                   SECURE3  0x8        /* SECURE 3 */
-#define                  nSECURE3  0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define                   SECMODE  0x3        /* Secured Mode Control State */
-#define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                      nNMI  0x0
-#define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                  nAFVALID  0x0
-#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   nAFEXIT  0x0
-#define                   SECSTAT  0xe0       /* Secure Status */
-
-
-
-#endif /* _DEF_BF51X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h
index 9af6ce0f6321..b480705bfc2e 100644
--- a/arch/blackfin/mach-bf518/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf518/include/mach/gpio.h
@@ -55,4 +55,8 @@
 #define PORT_G GPIO_PG0
 #define PORT_H GPIO_PH0
 
+#include <mach-common/ports-f.h>
+#include <mach-common/ports-g.h>
+#include <mach-common/ports-h.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h
index d5502988896b..94cca674d835 100644
--- a/arch/blackfin/mach-bf518/include/mach/pll.h
+++ b/arch/blackfin/mach-bf518/include/mach/pll.h
@@ -1,63 +1 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index fc767ac76381..ccab4c689dc3 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -67,6 +67,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -83,7 +84,7 @@ static struct musb_hdrc_platform_data musb_plat = {
 static u64 musb_dmamask = ~(u32)0;
 
 static struct platform_device musb_device = {
-        .name           = "musb_hdrc",
+        .name           = "musb-blackfin",
         .id             = 0,
         .dev = {
                 .dma_mask               = &musb_dmamask,
@@ -419,7 +420,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -474,7 +475,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -627,9 +628,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -661,9 +662,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 2c31af7a320a..c9d6dc88f0e6 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -82,11 +82,13 @@ static struct resource musb_resources[] = {
                 .start  = IRQ_USB_INT0,
                 .end    = IRQ_USB_INT0,
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "mc"
         },
         [2] = { /* DMA IRQ */
                 .start  = IRQ_USB_DMA,
                 .end    = IRQ_USB_DMA,
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "dma"
         },
 };
 
@@ -102,6 +104,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -118,7 +121,7 @@ static struct musb_hdrc_platform_data musb_plat = {
 static u64 musb_dmamask = ~(u32)0;
 
 static struct platform_device musb_device = {
-        .name           = "musb_hdrc",
+        .name           = "musb-blackfin",
         .id             = 0,
         .dev = {
                 .dma_mask               = &musb_dmamask,
@@ -612,7 +615,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -667,7 +670,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -799,9 +802,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -833,9 +836,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 9a736a850c5c..b7101aa6e3aa 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -46,11 +46,13 @@ static struct resource musb_resources[] = {
                 .start  = IRQ_USB_INT0,
                 .end    = IRQ_USB_INT0,
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "mc"
         },
         [2] = { /* DMA IRQ */
                 .start  = IRQ_USB_DMA,
                 .end    = IRQ_USB_DMA,
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "dma"
         },
 };
 
@@ -66,6 +68,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -82,7 +85,7 @@ static struct musb_hdrc_platform_data musb_plat = {
 static u64 musb_dmamask = ~(u32)0;
 
 static struct platform_device musb_device = {
-        .name           = "musb_hdrc",
+        .name           = "musb-blackfin",
         .id             = 0,
         .dev = {
                 .dma_mask               = &musb_dmamask,
@@ -497,7 +500,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -552,7 +555,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -679,9 +682,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -713,9 +716,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 9222bc00bbd3..2cd2ff6f3043 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -86,11 +86,13 @@ static struct resource musb_resources[] = {
                 .start  = IRQ_USB_INT0,
                 .end    = IRQ_USB_INT0,
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "mc"
         },
         [2] = { /* DMA IRQ */
                 .start  = IRQ_USB_DMA,
                 .end    = IRQ_USB_DMA,
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "dma"
         },
 };
 
@@ -106,6 +108,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -122,7 +125,7 @@ static struct musb_hdrc_platform_data musb_plat = {
 static u64 musb_dmamask = ~(u32)0;
 
 static struct platform_device musb_device = {
-        .name           = "musb_hdrc",
+        .name           = "musb-blackfin",
         .id             = 0,
         .dev = {
                 .dma_mask               = &musb_dmamask,
@@ -706,7 +709,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -761,7 +764,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -960,6 +963,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
                 I2C_BOARD_INFO("ad5252", 0x2f),
         },
 #endif
+#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
+        {
+                I2C_BOARD_INFO("adau1373", 0x1A),
+        },
+#endif
 };
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -982,9 +990,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -1016,9 +1024,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index 9ec575729e2c..18d303dd5627 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -91,7 +91,7 @@ static struct musb_hdrc_platform_data musb_plat = {
 static u64 musb_dmamask = ~(u32)0;
 
 static struct platform_device musb_device = {
-        .name           = "musb_hdrc",
+        .name           = "musb-blackfin",
         .id             = 0,
         .dev = {
                 .dma_mask               = &musb_dmamask,
@@ -193,7 +193,7 @@ static unsigned gpio_addr_inputs[] = {
         GPIO_PG1, GPIO_PH9, GPIO_PH10
 };
 
-static struct gpio_decoder_platfrom_data spi_decoded_cs = {
+static struct gpio_decoder_platform_data spi_decoded_cs = {
         .base           = EXP_GPIO_SPISEL_BASE,
         .input_addrs    = gpio_addr_inputs,
         .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
@@ -586,7 +586,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -642,7 +642,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -799,9 +799,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -834,9 +834,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
index 7bc7577d6c4f..1fabdefea73a 100644
--- a/arch/blackfin/mach-bf527/dma.c
+++ b/arch/blackfin/mach-bf527/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      2
+
+#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
index c1d55b878b45..960e08919def 100644
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
-#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
-#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
-#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
-#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
-#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
@@ -54,50 +27,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port port;
-        unsigned int old_status;
-        int status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int tx_done;
-        int tx_count;
-        struct circ_buf rx_dma_buf;
-        struct timer_list rx_dma_timer;
-        int rx_dma_nrows;
-        unsigned int tx_dma_channel;
-        unsigned int rx_dma_channel;
-        struct work_struct tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list cts_timer;
-        int cts_pin;
-        int rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long uart_base_addr;
         int uart_irq;
@@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
index f714c5de3073..e1d279274487 100644
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -1,49 +1,37 @@
 /*
- * Copyright 2007-2009 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_BLACKFIN_H_
 #define _MACH_BLACKFIN_H_
 
 #include "bf527.h"
-#include "defBF522.h"
 #include "anomaly.h"
 
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-#include "defBF527.h"
+#include <asm/def_LPBlackfin.h>
+#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
+# include "defBF522.h"
 #endif
-
 #if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-#include "defBF525.h"
+# include "defBF525.h"
 #endif
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF522.h"
-
 #if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-#include "cdefBF527.h"
+# include "defBF527.h"
 #endif
 
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-#include "cdefBF525.h"
-#endif
+#if !defined(__ASSEMBLY__)
+# include <asm/cdef_LPBlackfin.h>
+# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
+#  include "cdefBF522.h"
+# endif
+# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
+#  include "cdefBF525.h"
+# endif
+# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
+#  include "cdefBF527.h"
+# endif
 #endif
 
-#define BFIN_UART_NR_PORTS      2
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
 #endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
index 1079af8c7aef..618dfcdfa91a 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
@@ -1,21 +1,1095 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _CDEF_BF522_H
 #define _CDEF_BF522_H
 
-/* include all Core registers and bit definitions */
-#include "defBF522.h"
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
+#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
+#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
 
-/* include core specific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define bfin_read_SWRST()                       bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
+#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
 
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "cdefBF52x_base.h"
+#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
+#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
+#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
+#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
+
+#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
+
+#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
+#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
+#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
+
+#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
+#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
+#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
+
+/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
+
+#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
+#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
+#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
+
+/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
+#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
+#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
+#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
+#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
+#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
+#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
+#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
+
+
+/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
+#define bfin_read_SPI_CTL()                     bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)                 bfin_write16(SPI_CTL, val)
+#define bfin_read_SPI_FLG()                     bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)                 bfin_write16(SPI_FLG, val)
+#define bfin_read_SPI_STAT()                    bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)                bfin_write16(SPI_STAT, val)
+#define bfin_read_SPI_TDBR()                    bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)                bfin_write16(SPI_TDBR, val)
+#define bfin_read_SPI_RDBR()                    bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)                bfin_write16(SPI_RDBR, val)
+#define bfin_read_SPI_BAUD()                    bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)                bfin_write16(SPI_BAUD, val)
+#define bfin_read_SPI_SHADOW()                  bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)              bfin_write16(SPI_SHADOW, val)
+
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
+
+#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
+
+#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
+
+#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
+
+#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
+
+#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
+
+#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
+
+#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
+
+#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
+#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
+#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
+#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
+#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
+#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
+#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
+#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
+#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
+#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
+#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
+
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
+#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX)
+#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX)
+#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
+
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
+#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX)
+#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX)
+#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
+#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
+
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define bfin_read_DMAC_TC_PER()                 bfin_read16(DMAC_TC_PER)
+#define bfin_write_DMAC_TC_PER(val)             bfin_write16(DMAC_TC_PER, val)
+#define bfin_read_DMAC_TC_CNT()                 bfin_read16(DMAC_TC_CNT)
+#define bfin_write_DMAC_TC_CNT(val)             bfin_write16(DMAC_TC_CNT, val)
+
+/* DMA Controller                                                                                                                                       */
+#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
+#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
+#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
+#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
+#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
+#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
+#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
+#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
+#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
+#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
+#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
+#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
+#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
+#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
+#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
+#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
+#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
+#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
+#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
+#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
+#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
+#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
+#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
+#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
+#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
+#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
+#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
+#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
+#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
+#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
+#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
+#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
+#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
+#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
+#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
+#define bfin_clear_PPI_STATUS()                 bfin_write_PPI_STATUS(0xFFFF)
+#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
+#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
+#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
+#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
+#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
+#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
+#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
+#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
+#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
+#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
+#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
+#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
+#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
+#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
+#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
+#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
+#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
+#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
+#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
+#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
+#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
+#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
+#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
+#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
+#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
+#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
+#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
+#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
+#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
+#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
+#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
+#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
+#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
+#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
+#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
+#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
+#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
+#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
+#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
+#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
+#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
+#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
+
+/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
+#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
+#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
+#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
+#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
+#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
+#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
+
+#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
+
+/* ==== end from cdefBF534.h ==== */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+
+#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
+#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
+#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
+
+#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
+#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
+#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
+#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
+#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
+#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
+#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
+#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
+#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
+#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
+#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
+#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
+#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
+#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
+#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
+#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
+#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
+#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
+#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
+#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
+#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
+#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
+#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
+
+/* HOST Port Registers */
+
+#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
+#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
+#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
+
+/* Counter Registers */
+
+#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
+#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
+#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
+#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
+#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
+#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
+#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
+#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
+
+/* Security Registers */
+
+#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
+#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
+#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
+
+/* NFC Registers */
+
+#define bfin_read_NFC_CTL()                     bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)                 bfin_write16(NFC_CTL, val)
+#define bfin_read_NFC_STAT()                    bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)                bfin_write16(NFC_STAT, val)
+#define bfin_read_NFC_IRQSTAT()                 bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)             bfin_write16(NFC_IRQSTAT, val)
+#define bfin_read_NFC_IRQMASK()                 bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)             bfin_write16(NFC_IRQMASK, val)
+#define bfin_read_NFC_ECC0()                    bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)                bfin_write16(NFC_ECC0, val)
+#define bfin_read_NFC_ECC1()                    bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)                bfin_write16(NFC_ECC1, val)
+#define bfin_read_NFC_ECC2()                    bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)                bfin_write16(NFC_ECC2, val)
+#define bfin_read_NFC_ECC3()                    bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)                bfin_write16(NFC_ECC3, val)
+#define bfin_read_NFC_COUNT()                   bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)               bfin_write16(NFC_COUNT, val)
+#define bfin_read_NFC_RST()                     bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)                 bfin_write16(NFC_RST, val)
+#define bfin_read_NFC_PGCTL()                   bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)               bfin_write16(NFC_PGCTL, val)
+#define bfin_read_NFC_READ()                    bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)                bfin_write16(NFC_READ, val)
+#define bfin_read_NFC_ADDR()                    bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)                bfin_write16(NFC_ADDR, val)
+#define bfin_read_NFC_CMD()                     bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)                 bfin_write16(NFC_CMD, val)
+#define bfin_read_NFC_DATA_WR()                 bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)             bfin_write16(NFC_DATA_WR, val)
+#define bfin_read_NFC_DATA_RD()                 bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)             bfin_write16(NFC_DATA_RD, val)
 
 #endif /* _CDEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
index d7e2751c6bcc..d90a85b6b6b9 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
@@ -1,15 +1,12 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _CDEF_BF525_H
 #define _CDEF_BF525_H
 
-/* include all Core registers and bit definitions */
-#include "defBF525.h"
-
 /* BF525 is BF522 + USB */
 #include "cdefBF522.h"
 
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
index c7ba544d50b6..eb22f5866105 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
@@ -1,15 +1,12 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _CDEF_BF527_H
 #define _CDEF_BF527_H
 
-/* include all Core registers and bit definitions */
-#include "defBF527.h"
-
 /* BF527 is BF525 + EMAC */
 #include "cdefBF525.h"
 
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
deleted file mode 100644
index 3048b52bf46a..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ /dev/null
@@ -1,1113 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF52X_H
-#define _CDEF_BF52X_H
-
-#include <asm/blackfin.h>
-
-#include "defBF52x_base.h"
-
-/* Include core specific register pointer definitions                                                           */
-#include <asm/cdef_LPBlackfin.h>
-
-/* ==== begin from cdefBF534.h ==== */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define bfin_read_SWRST()                       bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
-#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
-
-
-/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
-#define bfin_read_SPI_CTL()                     bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)                 bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()                     bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)                 bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()                    bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)                bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()                    bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)                bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()                    bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)                bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()                    bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)                bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()                  bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)              bfin_write16(SPI_SHADOW, val)
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
-#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
-#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
-#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
-#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define bfin_read_DMA_TC_PER()                  bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)              bfin_write16(DMA_TC_PER, val)
-#define bfin_read_DMA_TC_CNT()                  bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)              bfin_write16(DMA_TC_CNT, val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TCPER()                   bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)               bfin_write16(DMA_TCPER, val)
-#define bfin_read_DMA_TCCNT()                   bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)               bfin_write16(DMA_TCCNT, val)
-
-/* DMA Controller                                                                                                                                       */
-#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
-#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS()                 bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
-#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
-#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
-#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
-#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL()                     bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)                 bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()                    bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)                bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()                 bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)             bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()                 bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)             bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()                    bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)                bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()                    bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)                bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()                    bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)                bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()                    bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)                bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()                   bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)               bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()                     bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)                 bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()                   bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)               bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()                    bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)                bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()                    bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)                bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()                     bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)                 bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()                 bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)             bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()                 bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)             bfin_write16(NFC_DATA_RD, val)
-
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index cb139a254810..89f5420ee6cd 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,12 +7,1393 @@
 #ifndef _DEF_BF522_H
 #define _DEF_BF522_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
+/* ************************************************************** */
+/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
+/* ************************************************************** */
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
+/* ==== begin from defBF534.h ==== */
 
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "defBF52x_base.h"
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
+#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
+#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
+#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
+#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
+#define CHIPID        0xFFC00014  /* Device ID Register */
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
+#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
+#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
+
+#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
+#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
+#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
+#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
+#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
+#define SIC_ISR0                                0xFFC00120      /* Interrupt Status Register                            */
+#define SIC_IWR0                                0xFFC00124      /* Interrupt Wakeup Register                            */
+
+/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
+#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
+#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
+#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
+#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
+#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
+#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
+
+
+/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
+#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
+#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
+#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
+#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
+#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
+#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
+#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
+#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
+#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
+#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
+#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
+#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
+#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
+#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
+#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
+#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
+#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
+#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
+#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
+#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
+
+
+/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
+#define SPI0_REGBASE                    0xFFC00500
+#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
+#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
+#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
+#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
+#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
+#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
+#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
+
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
+#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
+#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
+#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
+
+#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
+#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
+#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
+#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
+
+#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
+#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
+#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
+#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
+
+#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
+#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
+#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
+#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
+
+#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
+#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
+#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
+#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
+
+#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
+#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
+#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
+#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
+
+#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
+#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
+#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
+#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
+
+#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
+#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
+#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
+#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
+
+#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
+#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
+#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
+#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
+#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
+#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
+#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
+#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
+#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
+#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
+#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
+#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
+#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
+#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
+#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
+#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
+#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
+#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
+
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
+#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
+#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
+#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
+#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
+#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
+#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
+#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
+#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
+#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
+#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
+#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
+#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
+#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
+#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
+#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
+#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
+#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
+#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
+
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
+#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
+#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
+#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
+#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
+#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
+#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
+#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
+#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
+#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
+#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
+#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
+#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
+#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
+#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
+#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
+#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
+#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
+#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
+#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
+#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
+#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
+#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
+#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
+#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
+#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
+
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define DMAC_TC_PER                     0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMAC_TC_CNT                     0xFFC00B10      /* Traffic Control Current Counts Register      */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
+#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
+#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
+#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
+#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
+#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
+#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
+#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
+#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
+#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
+#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
+#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
+#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
+#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
+
+#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
+#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
+#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
+#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
+#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
+#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
+#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
+#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
+#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
+#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
+#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
+#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
+#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
+
+#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
+#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
+#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
+#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
+#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
+#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
+#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
+#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
+#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
+#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
+#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
+#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
+#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
+
+#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
+#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
+#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
+#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
+#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
+#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
+#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
+#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
+#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
+#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
+#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
+#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
+#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
+
+#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
+#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
+#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
+#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
+#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
+#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
+#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
+#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
+#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
+#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
+#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
+#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
+#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
+
+#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
+#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
+#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
+#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
+#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
+#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
+#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
+#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
+#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
+#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
+#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
+#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
+#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
+
+#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
+#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
+#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
+#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
+#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
+#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
+#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
+#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
+#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
+#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
+#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
+#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
+#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
+
+#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
+#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
+#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
+#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
+#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
+#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
+#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
+#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
+#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
+#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
+#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
+#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
+#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
+
+#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
+#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
+#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
+#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
+#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
+#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
+#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
+#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
+#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
+#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
+#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
+#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
+#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
+
+#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
+#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
+#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
+#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
+#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
+#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
+#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
+#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
+#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
+#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
+#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
+#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
+#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
+
+#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
+#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
+#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
+#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
+#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
+#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
+#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
+#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
+#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
+#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
+#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
+#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
+#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
+
+#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
+#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
+#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
+#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
+#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
+#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
+#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
+#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
+#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
+#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
+#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
+#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
+#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
+
+#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
+#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
+#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
+#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
+#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
+#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
+#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
+#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
+#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
+#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
+#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
+#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
+#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
+
+#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
+#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
+#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
+#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
+#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
+#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
+#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
+#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
+#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
+#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
+#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
+#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
+#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
+
+#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
+#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
+#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
+#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
+#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
+#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
+#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
+#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
+#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
+#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
+#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
+#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
+#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
+
+#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
+#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
+#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
+#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
+#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
+#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
+#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
+#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
+#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
+#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
+#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
+#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
+#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define TWI0_REGBASE                    0xFFC01400
+#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI0_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
+#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI0_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
+#define TWI0_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
+#define TWI0_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI0_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI0_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
+#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
+#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
+#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
+#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
+#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
+#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
+#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
+#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
+#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
+#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
+#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
+#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
+#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
+#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
+#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
+#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
+#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
+#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
+#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
+#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
+#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
+#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
+#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
+#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
+#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
+#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
+#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
+#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
+#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
+#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
+#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
+#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
+#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
+#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
+#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
+#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
+#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
+#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
+#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
+#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
+#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
+#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
+
+
+/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
+#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
+#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
+#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
+#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
+#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
+#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
+#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
+#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshold Register          */
+#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
+#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
+#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
+
+#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
+#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
+#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
+#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshold Register          */
+#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
+#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
+#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+#define PORTF_MUX               0xFFC03210      /* Port F mux control */
+#define PORTG_MUX               0xFFC03214      /* Port G mux control */
+#define PORTH_MUX               0xFFC03218      /* Port H mux control */
+#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
+#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
+#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
+#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
+#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
+#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
+#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
+#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
+#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
+#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
+#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
+#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
+
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* SWRST Masks                                                                                                                                          */
+#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
+#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
+#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
+#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
+#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
+
+/* SYSCR Masks                                                                                                                                                          */
+#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
+#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
+
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
+
+#if 0
+#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
+
+#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
+#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
+#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */
+#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */
+#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */
+#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
+#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
+
+#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
+#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
+#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
+#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */
+#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
+#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
+#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
+#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
+
+#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
+#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
+#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
+#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
+#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
+#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
+#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
+#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
+#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
+#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
+
+#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
+#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
+#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
+#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
+#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
+#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
+#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
+#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
+#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
+#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
+#endif
+
+/* SIC_IAR0 Macros                                                                                                                      */
+#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
+#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
+#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
+#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
+#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
+#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
+#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
+#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
+
+/* SIC_IAR1 Macros                                                                                                                      */
+#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
+#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
+#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
+#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
+#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
+#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
+#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
+#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
+
+/* SIC_IAR2 Macros                                                                                                                      */
+#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
+#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
+#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
+#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
+#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
+#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
+#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
+#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
+
+/* SIC_IAR3 Macros                                                                                                                      */
+#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
+#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
+#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
+#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
+#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
+#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
+#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
+#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
+
+
+/* SIC_IMASK Masks                                                                                                                                              */
+#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
+#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
+#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
+#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
+
+/* SIC_IWR Masks                                                                                                                                                */
+#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
+#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
+#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
+#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
+
+/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
+/* TIMER_ENABLE Masks                                                                                                   */
+#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
+#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
+#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
+#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
+#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
+#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
+#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
+#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
+
+/* TIMER_DISABLE Masks                                                                                                  */
+#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
+#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
+#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
+#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
+#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
+#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
+#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
+#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
+
+/* TIMER_STATUS Masks                                                                                                   */
+#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
+#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
+#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
+#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
+#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
+#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
+#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
+#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
+#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
+#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
+#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
+#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
+#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
+#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
+#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
+#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
+#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
+#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
+#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
+#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
+#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
+#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
+#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
+#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks                                                                                                  */
+#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
+#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
+#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
+#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
+#define PERIOD_CNT              0x0008  /* Period Count                                                 */
+#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
+#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
+#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
+#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
+#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
+#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
+#define ERR_TYP                 0xC000  /* Error Type                                                   */
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
+/* EBIU_AMGCTL Masks                                                                                                                                    */
+#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
+#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
+#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
+#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
+#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
+#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
+
+/* EBIU_AMBCTL0 Masks                                                                                                                                   */
+#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
+#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
+#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
+#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
+#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
+#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
+#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
+#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
+#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
+#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
+#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
+#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
+#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
+#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
+#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
+#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
+#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
+#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
+#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
+#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
+#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
+#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
+#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
+#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
+#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
+#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
+#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
+#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
+#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
+#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
+#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
+#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
+#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
+#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
+#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
+#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
+
+#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
+#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
+#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
+#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
+#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
+#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
+#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
+#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
+#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
+#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
+#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
+#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
+#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
+#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
+#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
+#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
+#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
+#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
+#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
+#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
+#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
+#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
+#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
+#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
+#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
+#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
+#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
+#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
+#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
+#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
+#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
+#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
+#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
+#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
+#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
+#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
+#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
+#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
+#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
+#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
+#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
+
+/* EBIU_AMBCTL1 Masks                                                                                                                                   */
+#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
+#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
+#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
+#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
+#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
+#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
+#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
+#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
+#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
+#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
+#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
+#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
+#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
+#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
+#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
+#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
+#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
+#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
+#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
+#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
+#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
+#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
+#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
+#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
+#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
+#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
+#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
+#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
+#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
+#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
+#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
+#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
+#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
+#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
+#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
+#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
+
+#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
+#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
+#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
+#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
+#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
+#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
+#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
+#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
+#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
+#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
+#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
+#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
+#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
+#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
+#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
+#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
+#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
+#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
+#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
+#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
+#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
+#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
+#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
+#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
+#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
+#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
+#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
+#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
+#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
+#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
+#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
+#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
+#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
+#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
+#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
+#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
+
+
+/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
+/* EBIU_SDGCTL Masks                                                                                                                                                    */
+#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
+#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
+#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
+#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
+#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
+#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
+#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
+#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
+#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
+#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
+#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
+#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
+#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
+#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
+#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
+#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
+#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
+#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
+#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
+#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
+#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
+#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
+#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
+#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
+#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
+#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
+#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
+#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
+#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
+#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
+#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
+#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
+#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
+#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
+#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
+#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
+#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
+#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
+#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
+#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
+#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
+#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
+#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
+#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
+
+/* EBIU_SDBCTL Masks                                                                                                                                            */
+#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
+#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
+#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
+#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
+#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
+#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
+#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
+#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
+#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
+#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
+#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
+
+/* EBIU_SDSTAT Masks                                                                                                            */
+#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
+#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
+#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
+#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
+#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
+#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
+
+
+/* **************************  DMA CONTROLLER MASKS  ********************************/
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
+#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
+#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
+#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
+#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
+#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
+#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
+#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
+#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
+#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
+#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
+#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
+#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
+#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
+#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
+
+/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
+/*  PPI_CONTROL Masks                                                                                                   */
+#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
+#define PORT_DIR                0x0002          /* PPI Port Direction                           */
+#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
+#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
+#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
+#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
+#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
+#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
+#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
+#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
+#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
+#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
+#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
+#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
+#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
+#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
+#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
+#define DLENGTH                 0x3800          /* PPI Data Length  */
+#define POLC                    0x4000          /* PPI Clock Polarity                           */
+#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
+
+/* PPI_STATUS Masks                                                                                                             */
+#define FLD                             0x0400          /* Field Indicator                                      */
+#define FT_ERR                  0x0800          /* Frame Track Error                            */
+#define OVR                             0x1000          /* FIFO Overflow Error                          */
+#define UNDR                    0x2000          /* FIFO Underrun Error                          */
+#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
+#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
+
+
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
+#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
+
+/* TWI_PRESCALE Masks                                                                                                                   */
+#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
+#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
+#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
+
+/* TWI_SLAVE_CTL Masks                                                                                                                  */
+#define SEN                     0x0001          /* Slave Enable                                                                 */
+#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
+#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
+#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
+
+/* TWI_SLAVE_STAT Masks                                                                                                                 */
+#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002          /* General Call Indicator                                               */
+
+/* TWI_MASTER_CTL Masks                                                                                                 */
+#define MEN                     0x0001          /* Master Mode Enable                                           */
+#define MADD_LEN        0x0002          /* Master Address Length                                        */
+#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
+#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
+#define STOP            0x0010          /* Issue Stop Condition                                         */
+#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
+#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
+#define SDAOVR          0x4000          /* Serial Data Override                                         */
+#define SCLOVR          0x8000          /* Serial Clock Override                                        */
+
+/* TWI_MASTER_STAT Masks                                                                                                                */
+#define MPROG           0x0001          /* Master Transfer In Progress                                  */
+#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
+#define ANAK            0x0004          /* Address Not Acknowledged                                             */
+#define DNAK            0x0008          /* Data Not Acknowledged                                                */
+#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
+#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
+#define SDASEN          0x0040          /* Serial Data Sense                                                    */
+#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
+#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
+#define SINIT           0x0001          /* Slave Transfer Initiated     */
+#define SCOMP           0x0002          /* Slave Transfer Complete      */
+#define SERR            0x0004          /* Slave Transfer Error         */
+#define SOVF            0x0008          /* Slave Overflow                       */
+#define MCOMP           0x0010          /* Master Transfer Complete     */
+#define MERR            0x0020          /* Master Transfer Error        */
+#define XMTSERV         0x0040          /* Transmit FIFO Service        */
+#define RCVSERV         0x0080          /* Receive FIFO Service         */
+
+/* TWI_FIFO_CTRL Masks                                                                                          */
+#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
+#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
+#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
+#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
+
+/* TWI_FIFO_STAT Masks                                                                                                                  */
+#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
+#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
+#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
+#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
+
+#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
+#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
+#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
+#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
+
+
+/* Omit CAN masks from defBF534.h */
+
+/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
+/* PORT_MUX Masks                                                                                                                       */
+#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
+#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
+#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
+
+#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
+#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
+#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
+#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
+
+#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
+#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
+#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
+
+#define PFTE                    0x0010                  /* Port F Timer Enable                          */
+#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
+#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
+
+#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
+#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
+#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
+
+#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
+#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
+#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
+
+#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
+#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
+#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
+
+#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
+#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
+#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
+
+#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
+#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
+#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
+
+#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
+#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
+#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
+
+#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
+#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
+#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
+
+
+/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
+/* HDMAx_CTL Masks                                                                                                              */
+#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
+#define REP                     0x0002  /* HDMA Request Polarity                                        */
+#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
+#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
+#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
+#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
+#define DRQ                     0x0300  /* HDMA Request Type                                            */
+#define DRQ_NONE        0x0000  /*              No Request                                                      */
+#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
+#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
+#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
+#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
+#define PS                      0x2000  /* HDMA Pin Status                                                      */
+#define OI                      0x4000  /* Overflow Interrupt Generated                         */
+#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
+
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define PGDE_UART   PFDE_UART
+#define PGDE_DMA    PFDE_DMA
+#define CKELOW          SCKELOW
+
+/* ==== end from defBF534.h ==== */
+
+/* HOST Port Registers */
+
+#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
+#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
+#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
+
+/* Counter Registers */
+
+#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
+#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
+#define                       CNT_STATUS  0xffc03508   /* Status Register */
+#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
+#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
+#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
+#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
+#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
+
+/* OTP/FUSE Registers */
+
+#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
+#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
+#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
+#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
+
+/* Security Registers */
+
+#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
+#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
+#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+
+/* NFC Registers */
+
+#define                          NFC_CTL  0xffc03700   /* NAND Control Register */
+#define                         NFC_STAT  0xffc03704   /* NAND Status Register */
+#define                      NFC_IRQSTAT  0xffc03708   /* NAND Interrupt Status Register */
+#define                      NFC_IRQMASK  0xffc0370c   /* NAND Interrupt Mask Register */
+#define                         NFC_ECC0  0xffc03710   /* NAND ECC Register 0 */
+#define                         NFC_ECC1  0xffc03714   /* NAND ECC Register 1 */
+#define                         NFC_ECC2  0xffc03718   /* NAND ECC Register 2 */
+#define                         NFC_ECC3  0xffc0371c   /* NAND ECC Register 3 */
+#define                        NFC_COUNT  0xffc03720   /* NAND ECC Count Register */
+#define                          NFC_RST  0xffc03724   /* NAND ECC Reset Register */
+#define                        NFC_PGCTL  0xffc03728   /* NAND Page Control Register */
+#define                         NFC_READ  0xffc0372c   /* NAND Read Data Register */
+#define                         NFC_ADDR  0xffc03740   /* NAND Address Register */
+#define                          NFC_CMD  0xffc03744   /* NAND Command Register */
+#define                      NFC_DATA_WR  0xffc03748   /* NAND Data Write Register */
+#define                      NFC_DATA_RD  0xffc0374c   /* NAND Data Read Register */
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for HOST_CONTROL */
+
+#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
+#define                  HOST_CNTR_nHOST_EN  0x0
+#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
+#define                 HOST_CNTR_nHOST_END  0x0
+#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
+#define                HOST_CNTR_nDATA_SIZE  0x0
+#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
+#define                 HOST_CNTR_nHOST_RST  0x0
+#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
+#define                 HOST_CNTR_nHRDY_OVR  0x0
+#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
+#define                 HOST_CNTR_nINT_MODE  0x0
+#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
+#define                   HOST_CNTR_ nBT_EN  0x0
+#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
+#define                      HOST_CNTR_nEHW  0x0
+#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
+#define                      HOST_CNTR_nEHR  0x0
+#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
+#define                      HOST_CNTR_nBDR  0x0
+
+/* Bit masks for HOST_STATUS */
+
+#define                     HOST_STAT_READY  0x1        /* DMA Ready */
+#define                    HOST_STAT_nREADY  0x0
+#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
+#define                 HOST_STAT_nFIFOFULL  0x0
+#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
+#define                HOST_STAT_nFIFOEMPTY  0x0
+#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
+#define                 HOST_STAT_nCOMPLETE  0x0
+#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
+#define                     HOST_STAT_nHSHK  0x0
+#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
+#define                  HOST_STAT_nTIMEOUT  0x0
+#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
+#define                     HOST_STAT_nHIRQ  0x0
+#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
+#define               HOST_STAT_nALLOW_CNFG  0x0
+#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
+#define                  HOST_STAT_nDMA_DIR  0x0
+#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
+#define                      HOST_STAT_nBTE  0x0
+#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
+#define              HOST_STAT_nHOSTRD_DONE  0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
+
+/* Bit masks for SECURE_SYSSWT */
+
+#define                   EMUDABL  0x1        /* Emulation Disable. */
+#define                  nEMUDABL  0x0
+#define                   RSTDABL  0x2        /* Reset Disable */
+#define                  nRSTDABL  0x0
+#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
+#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
+#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
+#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
+#define                  nDMA0OVR  0x0
+#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
+#define                  nDMA1OVR  0x0
+#define                    EMUOVR  0x4000     /* Emulation Override */
+#define                   nEMUOVR  0x0
+#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
+#define                   nOTPSEN  0x0
+#define                    L2DABL  0x70000    /* L2 Memory Disable. */
+
+/* Bit masks for SECURE_CONTROL */
+
+#define                   SECURE0  0x1        /* SECURE 0 */
+#define                  nSECURE0  0x0
+#define                   SECURE1  0x2        /* SECURE 1 */
+#define                  nSECURE1  0x0
+#define                   SECURE2  0x4        /* SECURE 2 */
+#define                  nSECURE2  0x0
+#define                   SECURE3  0x8        /* SECURE 3 */
+#define                  nSECURE3  0x0
+
+/* Bit masks for SECURE_STATUS */
+
+#define                   SECMODE  0x3        /* Secured Mode Control State */
+#define                       NMI  0x4        /* Non Maskable Interrupt */
+#define                      nNMI  0x0
+#define                   AFVALID  0x8        /* Authentication Firmware Valid */
+#define                  nAFVALID  0x0
+#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
+#define                   nAFEXIT  0x0
+#define                   SECSTAT  0xe0       /* Secure Status */
 
 #endif /* _DEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
index c136f7032962..cc383adfdffa 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
index 4dd58fb33156..05369a92fbc8 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
deleted file mode 100644
index 09475034c6a1..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ /dev/null
@@ -1,1506 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF52X_H
-#define _DEF_BF52X_H
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
-/* ************************************************************** */
-
-/* ==== begin from defBF534.h ==== */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
-#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
-#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
-#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
-#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
-#define CHIPID        0xFFC00014  /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
-#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
-#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
-
-#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
-#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
-#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
-#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
-#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
-#define SIC_ISR0                                0xFFC00120      /* Interrupt Status Register                            */
-#define SIC_IWR0                                0xFFC00124      /* Interrupt Wakeup Register                            */
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
-#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
-#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
-#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
-#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
-#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
-#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
-#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
-#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
-#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
-#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
-#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
-#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
-#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
-#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
-#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
-#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
-#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
-#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
-#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
-#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
-#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
-#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
-#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
-#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
-#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
-
-
-/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
-#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
-#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
-#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
-#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
-#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
-#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
-#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
-#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
-#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
-
-#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
-#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
-#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
-#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
-
-#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
-#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
-#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
-#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
-
-#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
-#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
-#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
-#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
-
-#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
-#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
-#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
-#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
-
-#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
-#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
-#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
-#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
-
-#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
-#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
-#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
-#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
-
-#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
-#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
-#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
-#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
-
-#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
-#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
-#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
-#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
-#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
-#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
-#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
-#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
-#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
-#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
-#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
-#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
-#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
-#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
-#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
-#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
-#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
-#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
-#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
-#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
-#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
-#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
-#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
-#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
-#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
-#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
-#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
-#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
-#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
-#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
-#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
-#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
-#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
-#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
-#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
-#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
-#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
-#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
-#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
-#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
-#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
-#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
-#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
-#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
-#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
-#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
-#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
-#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
-#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
-#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
-#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
-#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
-
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
-#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
-#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
-#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
-#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
-#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
-#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
-#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
-#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
-#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
-#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
-#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
-#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
-#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
-
-#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
-#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
-#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
-#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
-#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
-#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
-#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
-#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
-#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
-#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
-#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
-#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
-#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
-
-#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
-#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
-#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
-#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
-#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
-#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
-#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
-#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
-#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
-#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
-#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
-#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
-#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
-
-#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
-#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
-#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
-#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
-#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
-#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
-#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
-#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
-#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
-#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
-#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
-#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
-#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
-
-#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
-#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
-#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
-#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
-#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
-#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
-#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
-#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
-#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
-#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
-#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
-#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
-#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
-
-#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
-#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
-#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
-#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
-#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
-#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
-#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
-#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
-#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
-#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
-#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
-#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
-#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
-
-#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
-#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
-#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
-#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
-#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
-#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
-#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
-#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
-#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
-#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
-#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
-#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
-#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
-
-#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
-#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
-#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
-#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
-#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
-#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
-#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
-#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
-#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
-#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
-#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
-#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
-#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
-
-#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
-#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
-#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
-#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
-#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
-#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
-#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
-#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
-#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
-#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
-#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
-#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
-#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
-
-#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
-#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
-#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
-#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
-#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
-#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
-#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
-#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
-#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
-#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
-#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
-#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
-#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
-
-#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
-#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
-#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
-#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
-#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
-#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
-#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
-#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
-#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
-#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
-#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
-#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
-#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
-
-#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
-#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
-#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
-#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
-#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
-#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
-#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
-#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
-#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
-#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
-#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
-#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
-#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
-
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
-#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
-#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
-#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
-#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
-#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
-#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
-#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
-#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
-
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
-#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
-#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
-#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
-#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
-#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
-#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
-#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
-#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
-
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
-#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
-#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
-#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
-#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
-#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
-#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
-#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
-#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
-
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
-#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
-#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
-#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
-#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
-#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
-#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
-#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
-#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-#define TWI0_REGBASE                    0xFFC01400
-#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI0_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
-#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI0_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
-#define TWI0_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
-#define TWI0_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI0_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI0_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
-#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
-#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
-#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
-#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
-#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
-#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
-#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
-#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
-#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
-#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
-#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
-#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
-#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
-#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
-#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
-#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
-#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
-#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
-#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
-#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
-#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
-#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
-#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
-#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
-#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
-#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
-#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
-#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
-#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
-#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
-#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
-#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
-#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
-#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
-#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
-#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
-#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
-#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
-#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
-#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
-#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
-#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
-
-
-/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
-#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
-#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
-#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
-#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
-#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
-#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
-#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
-#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshold Register          */
-#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
-#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
-#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
-
-#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
-#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
-#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
-#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshold Register          */
-#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
-#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
-#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX               0xFFC03210      /* Port F mux control */
-#define PORTG_MUX               0xFFC03214      /* Port G mux control */
-#define PORTH_MUX               0xFFC03218      /* Port H mux control */
-#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
-#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
-#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
-#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
-#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
-#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
-#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
-#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* SWRST Masks                                                                                                                                          */
-#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
-#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
-
-/* SYSCR Masks                                                                                                                                                          */
-#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
-#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
-
-#if 0
-#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
-
-#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */
-#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */
-#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */
-#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
-#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
-
-#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
-#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
-#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
-#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */
-#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
-#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
-#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
-#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
-
-#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
-#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
-#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
-#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
-#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
-#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
-#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
-#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
-#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
-#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
-
-#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
-#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
-#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
-#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
-#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
-#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
-#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
-#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
-#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
-#endif
-
-/* SIC_IAR0 Macros                                                                                                                      */
-#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
-#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
-#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
-#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
-#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
-#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
-#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
-#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
-
-/* SIC_IAR1 Macros                                                                                                                      */
-#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
-#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
-#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
-#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
-#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
-#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
-#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
-#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
-
-/* SIC_IAR2 Macros                                                                                                                      */
-#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
-#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
-#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
-#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
-#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
-#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
-#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
-#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
-
-/* SIC_IAR3 Macros                                                                                                                      */
-#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
-#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
-#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
-#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
-#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
-#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
-#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
-#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
-
-
-/* SIC_IMASK Masks                                                                                                                                              */
-#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
-#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
-#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
-#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
-
-/* SIC_IWR Masks                                                                                                                                                */
-#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
-#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
-
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
-#define STB                     0x04                            /* Stop Bits                    */
-#define PEN                     0x08                            /* Parity Enable                */
-#define EPS                     0x10                            /* Even Parity Select   */
-#define STP                     0x20                            /* Stick Parity                 */
-#define SB                      0x40                            /* Set Break                    */
-#define DLAB            0x80                            /* Divisor Latch Access */
-
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA        0x10    /* Loopback Mode Enable */
-#define LOOP_ENA_P      0x04
-
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04            /* Enable RX Status Interrupt                           */
-
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01            /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02            /* UART_THR empty                               */
-#define IIR_RX_READY    0x04            /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06            /* Receive line status                          */
-#define IIR_STATUS      0x06            /* Highest Priority Pending Interrupt   */
-
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01            /* Enable UARTx Clocks                          */
-#define IREN            0x02            /* Enable IrDA Mode                                     */
-#define TPOLC           0x04            /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08            /* IrDA RX Polarity Change                      */
-#define FPE                     0x10            /* Force Parity Error On Transmit       */
-#define FFE                     0x20            /* Force Framing Error On Transmit      */
-
-
-/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
-/* TIMER_ENABLE Masks                                                                                                   */
-#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
-#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
-#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
-#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
-#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
-#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
-#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
-#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
-
-/* TIMER_DISABLE Masks                                                                                                  */
-#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
-#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
-#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
-#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
-#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
-#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
-#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
-#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
-
-/* TIMER_STATUS Masks                                                                                                   */
-#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
-#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
-#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
-#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
-#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
-#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
-#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
-#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
-#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
-#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
-#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
-#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
-#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
-#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
-#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
-#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
-#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
-#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
-#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
-#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
-#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
-#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
-#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
-#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks                                                                                                  */
-#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
-#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
-#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
-#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
-#define PERIOD_CNT              0x0008  /* Period Count                                                 */
-#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
-#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
-#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
-#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
-#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
-#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
-#define ERR_TYP                 0xC000  /* Error Type                                                   */
-
-
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-#define PH8             0x0100
-#define PH9             0x0200
-#define PH10    0x0400
-#define PH11    0x0800
-#define PH12    0x1000
-#define PH13    0x2000
-#define PH14    0x4000
-#define PH15    0x8000
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks                                                                                                                                    */
-#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
-#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
-#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
-#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
-#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
-
-/* EBIU_AMBCTL0 Masks                                                                                                                                   */
-#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
-#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
-#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
-#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
-#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
-#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
-#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
-#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
-#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
-#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
-#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
-#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
-#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
-#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
-#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
-#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
-#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
-#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
-#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
-#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
-#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
-#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
-#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
-#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
-#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
-#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
-#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
-#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
-#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
-#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
-#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
-#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
-#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
-#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
-#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
-#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
-
-#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
-#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
-#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
-#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
-#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
-#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
-#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
-#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
-#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
-#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
-#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
-#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
-#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
-#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
-#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
-#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
-#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
-#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
-#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
-#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
-#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
-#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
-#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
-#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
-#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
-#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
-#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
-#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
-#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
-#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
-#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
-#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
-#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
-#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
-#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
-#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
-#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
-#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
-#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
-#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
-#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
-
-/* EBIU_AMBCTL1 Masks                                                                                                                                   */
-#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
-#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
-#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
-#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
-#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
-#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
-#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
-#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
-#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
-#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
-#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
-#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
-#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
-#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
-#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
-#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
-#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
-#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
-#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
-#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
-#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
-#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
-#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
-#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
-#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
-#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
-#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
-#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
-#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
-#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
-#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
-#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
-#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
-#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
-#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
-#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
-
-#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
-#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
-#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
-#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
-#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
-#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
-#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
-#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
-#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
-#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
-#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
-#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
-#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
-#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
-#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
-#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
-#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
-#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
-#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
-#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
-#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
-#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
-#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
-#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
-#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
-#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
-#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
-#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
-#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
-#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
-#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
-#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
-#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
-#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
-#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
-#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
-
-
-/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
-/* EBIU_SDGCTL Masks                                                                                                                                                    */
-#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
-#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
-#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
-#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
-#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
-#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
-#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
-#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
-#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
-#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
-#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
-#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
-
-/* EBIU_SDBCTL Masks                                                                                                                                            */
-#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
-#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
-#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
-#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
-#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
-#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
-#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
-#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
-#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
-#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
-#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
-
-/* EBIU_SDSTAT Masks                                                                                                            */
-#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
-#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
-#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
-#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
-#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
-#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
-
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
-#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
-#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
-#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
-#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
-#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
-#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
-#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
-#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
-#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
-#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
-#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
-#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
-#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
-
-/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/*  PPI_CONTROL Masks                                                                                                   */
-#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
-#define PORT_DIR                0x0002          /* PPI Port Direction                           */
-#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
-#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
-#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
-#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
-#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
-#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
-#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
-#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
-#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
-#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
-#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
-#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
-#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
-#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
-#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
-#define DLENGTH                 0x3800          /* PPI Data Length  */
-#define POLC                    0x4000          /* PPI Clock Polarity                           */
-#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
-
-/* PPI_STATUS Masks                                                                                                             */
-#define FLD                             0x0400          /* Field Indicator                                      */
-#define FT_ERR                  0x0800          /* Frame Track Error                            */
-#define OVR                             0x1000          /* FIFO Overflow Error                          */
-#define UNDR                    0x2000          /* FIFO Underrun Error                          */
-#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
-#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
-#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTL Masks                                                                                                                  */
-#define SEN                     0x0001          /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTL Masks                                                                                                 */
-#define MEN                     0x0001          /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002          /* Master Address Length                                        */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010          /* Issue Stop Condition                                         */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000          /* Serial Data Override                                         */
-#define SCLOVR          0x8000          /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001          /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004          /* Address Not Acknowledged                                             */
-#define DNAK            0x0008          /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
-#define SDASEN          0x0040          /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001          /* Slave Transfer Initiated     */
-#define SCOMP           0x0002          /* Slave Transfer Complete      */
-#define SERR            0x0004          /* Slave Transfer Error         */
-#define SOVF            0x0008          /* Slave Overflow                       */
-#define MCOMP           0x0010          /* Master Transfer Complete     */
-#define MERR            0x0020          /* Master Transfer Error        */
-#define XMTSERV         0x0040          /* Transmit FIFO Service        */
-#define RCVSERV         0x0080          /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
-
-
-/* Omit CAN masks from defBF534.h */
-
-/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
-/* PORT_MUX Masks                                                                                                                       */
-#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
-#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
-#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
-
-#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
-#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
-#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
-#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
-
-#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
-#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
-#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
-
-#define PFTE                    0x0010                  /* Port F Timer Enable                          */
-#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
-#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
-
-#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
-#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
-#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
-
-#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
-#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
-#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
-
-#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
-#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
-#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
-
-#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
-#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
-#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
-
-#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
-#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
-#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
-
-#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
-#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
-#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
-
-#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
-#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
-#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
-
-
-/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
-/* HDMAx_CTL Masks                                                                                                              */
-#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
-#define REP                     0x0002  /* HDMA Request Polarity                                        */
-#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
-#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
-#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
-#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
-#define DRQ                     0x0300  /* HDMA Request Type                                            */
-#define DRQ_NONE        0x0000  /*              No Request                                                      */
-#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
-#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
-#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
-#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
-#define PS                      0x2000  /* HDMA Pin Status                                                      */
-#define OI                      0x4000  /* Overflow Interrupt Generated                         */
-#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART   PFDE_UART
-#define PGDE_DMA    PFDE_DMA
-#define CKELOW          SCKELOW
-
-/* ==== end from defBF534.h ==== */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
-#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
-#define                       CNT_STATUS  0xffc03508   /* Status Register */
-#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
-#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
-#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
-#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
-#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
-#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
-#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
-#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
-#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
-#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* NFC Registers */
-
-#define                          NFC_CTL  0xffc03700   /* NAND Control Register */
-#define                         NFC_STAT  0xffc03704   /* NAND Status Register */
-#define                      NFC_IRQSTAT  0xffc03708   /* NAND Interrupt Status Register */
-#define                      NFC_IRQMASK  0xffc0370c   /* NAND Interrupt Mask Register */
-#define                         NFC_ECC0  0xffc03710   /* NAND ECC Register 0 */
-#define                         NFC_ECC1  0xffc03714   /* NAND ECC Register 1 */
-#define                         NFC_ECC2  0xffc03718   /* NAND ECC Register 2 */
-#define                         NFC_ECC3  0xffc0371c   /* NAND ECC Register 3 */
-#define                        NFC_COUNT  0xffc03720   /* NAND ECC Count Register */
-#define                          NFC_RST  0xffc03724   /* NAND ECC Reset Register */
-#define                        NFC_PGCTL  0xffc03728   /* NAND Page Control Register */
-#define                         NFC_READ  0xffc0372c   /* NAND Read Data Register */
-#define                         NFC_ADDR  0xffc03740   /* NAND Address Register */
-#define                          NFC_CMD  0xffc03744   /* NAND Command Register */
-#define                      NFC_DATA_WR  0xffc03748   /* NAND Data Write Register */
-#define                      NFC_DATA_RD  0xffc0374c   /* NAND Data Read Register */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
-#define                  HOST_CNTR_nHOST_EN  0x0
-#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
-#define                 HOST_CNTR_nHOST_END  0x0
-#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
-#define                HOST_CNTR_nDATA_SIZE  0x0
-#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
-#define                 HOST_CNTR_nHOST_RST  0x0
-#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
-#define                 HOST_CNTR_nHRDY_OVR  0x0
-#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
-#define                 HOST_CNTR_nINT_MODE  0x0
-#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
-#define                   HOST_CNTR_ nBT_EN  0x0
-#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
-#define                      HOST_CNTR_nEHW  0x0
-#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
-#define                      HOST_CNTR_nEHR  0x0
-#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
-#define                      HOST_CNTR_nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                     HOST_STAT_READY  0x1        /* DMA Ready */
-#define                    HOST_STAT_nREADY  0x0
-#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
-#define                 HOST_STAT_nFIFOFULL  0x0
-#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
-#define                HOST_STAT_nFIFOEMPTY  0x0
-#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
-#define                 HOST_STAT_nCOMPLETE  0x0
-#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
-#define                     HOST_STAT_nHSHK  0x0
-#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
-#define                  HOST_STAT_nTIMEOUT  0x0
-#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
-#define                     HOST_STAT_nHIRQ  0x0
-#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               HOST_STAT_nALLOW_CNFG  0x0
-#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
-#define                  HOST_STAT_nDMA_DIR  0x0
-#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
-#define                      HOST_STAT_nBTE  0x0
-#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
-#define              HOST_STAT_nHOSTRD_DONE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                  nEMUDABL  0x0
-#define                   RSTDABL  0x2        /* Reset Disable */
-#define                  nRSTDABL  0x0
-#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
-#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
-#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
-#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                  nDMA0OVR  0x0
-#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                  nDMA1OVR  0x0
-#define                    EMUOVR  0x4000     /* Emulation Override */
-#define                   nEMUOVR  0x0
-#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                   nOTPSEN  0x0
-#define                    L2DABL  0x70000    /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define                   SECURE0  0x1        /* SECURE 0 */
-#define                  nSECURE0  0x0
-#define                   SECURE1  0x2        /* SECURE 1 */
-#define                  nSECURE1  0x0
-#define                   SECURE2  0x4        /* SECURE 2 */
-#define                  nSECURE2  0x0
-#define                   SECURE3  0x8        /* SECURE 3 */
-#define                  nSECURE3  0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define                   SECMODE  0x3        /* Secured Mode Control State */
-#define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                      nNMI  0x0
-#define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                  nAFVALID  0x0
-#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   nAFEXIT  0x0
-#define                   SECSTAT  0xe0       /* Secure Status */
-
-#endif /* _DEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
index f80c2995efdb..fba606b699c3 100644
--- a/arch/blackfin/mach-bf527/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf527/include/mach/gpio.h
@@ -62,4 +62,8 @@
 #define PORT_G GPIO_PG0
 #define PORT_H GPIO_PH0
 
+#include <mach-common/ports-f.h>
+#include <mach-common/ports-g.h>
+#include <mach-common/ports-h.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
index 24f1d7c02325..94cca674d835 100644
--- a/arch/blackfin/mach-bf527/include/mach/pll.h
+++ b/arch/blackfin/mach-bf527/include/mach/pll.h
@@ -1,63 +1 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 2ce7b16faee1..d4bfcea56828 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -286,7 +286,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 20c102285bef..87b5af3693c1 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -25,7 +25,6 @@
 #include <asm/bfin5xx_spi.h>
 #include <asm/portmux.h>
 #include <asm/dpmc.h>
-#include <mach/fio_flag.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -225,7 +224,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -290,9 +289,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -324,9 +323,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
@@ -476,10 +475,16 @@ static int __init blackstamp_init(void)
                 return ret;
 
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
-        /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */
-        bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0);
-        bfin_write_FIO_FLAG_S(PF0);
-        SSYNC();
+        /*
+         * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
+         * the bfin-async-map driver takes care of flipping between
+         * flash and ethernet when necessary.
+         */
+        ret = gpio_request(GPIO_PF0, "enet_cpld");
+        if (!ret) {
+                gpio_direction_output(GPIO_PF0, 1);
+                gpio_free(GPIO_PF0);
+        }
 #endif
 
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index adbe62a81e25..4d5604eaa7c2 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -271,7 +271,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -336,9 +336,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -370,9 +370,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index a1cb8e7c1010..b67b91d82242 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -349,7 +349,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 5ba4b02a12eb..f869a3711480 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -22,7 +22,6 @@
 #include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 #include <asm/portmux.h>
-#include <mach/fio_flag.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -174,7 +173,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -295,15 +294,7 @@ static int __init ip0x_init(void)
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
-                int j = 1 << bfin_spi_board_info[i].chip_select;
-                /* set spi cs to 1 */
-                bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
-                bfin_write_FIO_FLAG_S(j);
-        }
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
 
         return 0;
 }
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index b3b1cdea2703..43224ef00b8c 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -24,7 +24,6 @@
 #include <asm/reboot.h>
 #include <asm/portmux.h>
 #include <asm/dpmc.h>
-#include <mach/fio_flag.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -354,7 +353,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -419,9 +418,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -453,9 +452,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
@@ -674,10 +673,16 @@ static int __init stamp_init(void)
                 return ret;
 
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
-        /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */
-        bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0);
-        bfin_write_FIO_FLAG_S(PF0);
-        SSYNC();
+        /*
+         * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
+         * the bfin-async-map driver takes care of flipping between
+         * flash and ethernet when necessary.
+         */
+        ret = gpio_request(GPIO_PF0, "enet_cpld");
+        if (!ret) {
+                gpio_direction_output(GPIO_PF0, 1);
+                gpio_free(GPIO_PF0);
+        }
 #endif
 
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
@@ -713,7 +718,6 @@ void __init native_machine_early_platform_add_devices(void)
 void native_machine_restart(char *cmd)
 {
         /* workaround pull up on cpld / flash pin not being strong enough */
-        bfin_write_FIO_INEN(~PF0);
-        bfin_write_FIO_DIR(PF0);
-        bfin_write_FIO_FLAG_C(PF0);
+        gpio_request(GPIO_PF0, "flash_cpld");
+        gpio_direction_output(GPIO_PF0, 0);
 }
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
index 4a14a46a9a68..1f5988d43139 100644
--- a/arch/blackfin/mach-bf533/dma.c
+++ b/arch/blackfin/mach-bf533/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..08072c86d5dc
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      1
+
+#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
index 9e1f3defb6bc..45dcaa4f3e41 100644
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #ifdef CONFIG_BFIN_UART0_CTSRTS
 # define CONFIG_SERIAL_BFIN_CTSRTS
 # ifndef CONFIG_UART0_CTS_PIN
@@ -44,51 +17,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        int                     status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#else
-# if ANOMALY_05000363
-        unsigned int anomaly_threshold;
-# endif
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int                     cts_pin;
-        int                     rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long   uart_base_addr;
         int             uart_irq;
@@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
index f4bd6df5d968..e366207fbf12 100644
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -1,7 +1,7 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_BLACKFIN_H_
@@ -10,26 +10,14 @@
 #define BF533_FAMILY
 
 #include "bf533.h"
-#include "defBF532.h"
 #include "anomaly.h"
 
-#if !defined(__ASSEMBLY__)
-#include "cdefBF532.h"
-#endif
-
-#define BFIN_UART_NR_PORTS      1
+#include <asm/def_LPBlackfin.h>
+#include "defBF532.h"
 
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# include "cdefBF532.h"
+#endif
 
-#endif                          /* _MACH_BLACKFIN_H_ */
+#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index 401e524f5321..fd0cbe4df21a 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later
  */
@@ -7,9 +7,6 @@
 #ifndef _CDEF_BF532_H
 #define _CDEF_BF532_H
 
-/*include core specific register pointer definitions*/
-#include <asm/cdef_LPBlackfin.h>
-
 /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
 #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
 #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
@@ -66,16 +63,10 @@
 #define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)
 
 /* DMA Traffic controls */
-#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TC_PER()               bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)           bfin_write16(DMA_TC_PER,val)
-#define bfin_read_DMA_TC_CNT()               bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)           bfin_write16(DMA_TC_CNT,val)
+#define bfin_read_DMAC_TC_PER()              bfin_read16(DMAC_TC_PER)
+#define bfin_write_DMAC_TC_PER(val)          bfin_write16(DMAC_TC_PER,val)
+#define bfin_read_DMAC_TC_CNT()              bfin_read16(DMAC_TC_CNT)
+#define bfin_write_DMAC_TC_CNT(val)          bfin_write16(DMAC_TC_CNT,val)
 
 /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
 #define bfin_read_FIO_DIR()                  bfin_read16(FIO_DIR)
@@ -105,6 +96,47 @@
 #define bfin_read_FIO_MASKB_T()              bfin_read16(FIO_MASKB_T)
 #define bfin_write_FIO_MASKB_T(val)          bfin_write16(FIO_MASKB_T,val)
 
+#if ANOMALY_05000311
+/* Keep at the CPP expansion to avoid circular header dependency loops */
+#define BFIN_WRITE_FIO_FLAG(name, val) \
+        do { \
+                unsigned long __flags; \
+                __flags = hard_local_irq_save(); \
+                bfin_write16(FIO_FLAG_##name, val); \
+                bfin_read_CHIPID(); \
+                hard_local_irq_restore(__flags); \
+        } while (0)
+#define bfin_write_FIO_FLAG_D(val)           BFIN_WRITE_FIO_FLAG(D, val)
+#define bfin_write_FIO_FLAG_C(val)           BFIN_WRITE_FIO_FLAG(C, val)
+#define bfin_write_FIO_FLAG_S(val)           BFIN_WRITE_FIO_FLAG(S, val)
+#define bfin_write_FIO_FLAG_T(val)           BFIN_WRITE_FIO_FLAG(T, val)
+
+#define BFIN_READ_FIO_FLAG(name) \
+        ({ \
+                unsigned long __flags; \
+                u16 __ret; \
+                __flags = hard_local_irq_save(); \
+                __ret = bfin_read16(FIO_FLAG_##name); \
+                bfin_read_CHIPID(); \
+                hard_local_irq_restore(__flags); \
+                __ret; \
+        })
+#define bfin_read_FIO_FLAG_D()               BFIN_READ_FIO_FLAG(D)
+#define bfin_read_FIO_FLAG_C()               BFIN_READ_FIO_FLAG(C)
+#define bfin_read_FIO_FLAG_S()               BFIN_READ_FIO_FLAG(S)
+#define bfin_read_FIO_FLAG_T()               BFIN_READ_FIO_FLAG(T)
+
+#else
+#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D, val)
+#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C, val)
+#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S, val)
+#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T, val)
+#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
+#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
+#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
+#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
+#endif
+
 /* DMA Controller */
 #define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
@@ -647,7 +679,4 @@
 #define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)
 #define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)
 
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
 #endif                          /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 3adb0b44e597..2376d5393511 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -1,7 +1,7 @@
 /*
  * System & MMR bit and Address definitions for ADSP-BF532
  *
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -9,9 +9,6 @@
 #ifndef _DEF_BF532_H
 #define _DEF_BF532_H
 
-/* include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
 /*********************************************************************************** */
 /* System MMR Register Map */
 /*********************************************************************************** */
@@ -182,12 +179,8 @@
 #define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register */
 
 /* DMA Traffic controls */
-#define DMA_TC_PER 0xFFC00B0C   /* Traffic Control Periods Register */
-#define DMA_TC_CNT 0xFFC00B10   /* Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER 0xFFC00B0C    /* Traffic Control Periods Register */
-#define DMA_TCCNT 0xFFC00B10    /* Traffic Control Current Counts Register */
+#define DMAC_TC_PER 0xFFC00B0C  /* Traffic Control Periods Register */
+#define DMAC_TC_CNT 0xFFC00B10  /* Traffic Control Current Counts Register */
 
 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
 #define DMA0_CONFIG             0xFFC00C08      /* DMA Channel 0 Configuration Register */
@@ -432,83 +425,6 @@
 #define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
 
-/* ***************************** UART CONTROLLER MASKS ********************** */
-
-/* UART_LCR Register */
-
-#define DLAB    0x80
-#define SB      0x40
-#define STP      0x20
-#define EPS     0x10
-#define PEN     0x08
-#define STB     0x04
-#define WLS(x)  ((x-5) & 0x03)
-
-#define DLAB_P  0x07
-#define SB_P    0x06
-#define STP_P   0x05
-#define EPS_P   0x04
-#define PEN_P   0x03
-#define STB_P   0x02
-#define WLS_P1  0x01
-#define WLS_P0  0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA        0x10
-#define LOOP_ENA_P      0x04
-
-/* UART_LSR Register */
-#define TEMT    0x40
-#define THRE    0x20
-#define BI      0x10
-#define FE      0x08
-#define PE      0x04
-#define OE      0x02
-#define DR      0x01
-
-#define TEMP_P  0x06
-#define THRE_P  0x05
-#define BI_P    0x04
-#define FE_P    0x03
-#define PE_P    0x02
-#define OE_P    0x01
-#define DR_P    0x00
-
-/* UART_IER Register */
-#define ELSI    0x04
-#define ETBEI   0x02
-#define ERBFI   0x01
-
-#define ELSI_P  0x02
-#define ETBEI_P 0x01
-#define ERBFI_P 0x00
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define NINT            0x01
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-#define NINT_P          0x00
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UART_GCTL Register */
-#define FFE     0x20
-#define FPE     0x10
-#define RPOLC   0x08
-#define TPOLC   0x04
-#define IREN    0x02
-#define UCEN    0x01
-
-#define FFE_P   0x05
-#define FPE_P   0x04
-#define RPOLC_P 0x03
-#define TPOLC_P 0x02
-#define IREN_P  0x01
-#define UCEN_P  0x00
-
 /*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
 
 /*  PPI_CONTROL Masks         */
@@ -643,44 +559,6 @@
 #define ERR_TYP_P0              0x0E
 #define ERR_TYP_P1              0x0F
 
-/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-#define PF0         0x0001
-#define PF1         0x0002
-#define PF2         0x0004
-#define PF3         0x0008
-#define PF4         0x0010
-#define PF5         0x0020
-#define PF6         0x0040
-#define PF7         0x0080
-#define PF8         0x0100
-#define PF9         0x0200
-#define PF10        0x0400
-#define PF11        0x0800
-#define PF12        0x1000
-#define PF13        0x2000
-#define PF14        0x4000
-#define PF15        0x8000
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
-#define PF0_P         0
-#define PF1_P         1
-#define PF2_P         2
-#define PF3_P         3
-#define PF4_P         4
-#define PF5_P         5
-#define PF6_P         6
-#define PF7_P         7
-#define PF8_P         8
-#define PF9_P         9
-#define PF10_P        10
-#define PF11_P        11
-#define PF12_P        12
-#define PF13_P        13
-#define PF14_P        14
-#define PF15_P        15
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
 
 /* AMGCTL Masks */
diff --git a/arch/blackfin/mach-bf533/include/mach/fio_flag.h b/arch/blackfin/mach-bf533/include/mach/fio_flag.h
deleted file mode 100644
index d0bfba0b083b..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/fio_flag.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_FIO_FLAG_H
-#define _MACH_FIO_FLAG_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-#if ANOMALY_05000311
-#define BFIN_WRITE_FIO_FLAG(name) \
-static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
-{ \
-        unsigned long flags; \
-        flags = hard_local_irq_save(); \
-        bfin_write16(FIO_FLAG_##name, val); \
-        bfin_read_CHIPID(); \
-        hard_local_irq_restore(flags); \
-}
-BFIN_WRITE_FIO_FLAG(D)
-BFIN_WRITE_FIO_FLAG(C)
-BFIN_WRITE_FIO_FLAG(S)
-BFIN_WRITE_FIO_FLAG(T)
-
-#define BFIN_READ_FIO_FLAG(name) \
-static inline u16 bfin_read_FIO_FLAG_##name(void) \
-{ \
-        unsigned long flags; \
-        u16 ret; \
-        flags = hard_local_irq_save(); \
-        ret = bfin_read16(FIO_FLAG_##name); \
-        bfin_read_CHIPID(); \
-        hard_local_irq_restore(flags); \
-        return ret; \
-}
-BFIN_READ_FIO_FLAG(D)
-BFIN_READ_FIO_FLAG(C)
-BFIN_READ_FIO_FLAG(S)
-BFIN_READ_FIO_FLAG(T)
-
-#else
-#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D, val)
-#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C, val)
-#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S, val)
-#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T, val)
-#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
-#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
-#endif
-
-#endif /* _MACH_FIO_FLAG_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h
index e02416db4b00..cce4f8fb3785 100644
--- a/arch/blackfin/mach-bf533/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf533/include/mach/gpio.h
@@ -28,4 +28,6 @@
 
 #define PORT_F GPIO_PF0
 
+#include <mach-common/ports-f.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h
index 169c106d0edb..94cca674d835 100644
--- a/arch/blackfin/mach-bf533/include/mach/pll.h
+++ b/arch/blackfin/mach-bf533/include/mach/pll.h
@@ -1,57 +1 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 44132fda63be..a44bf3a1816e 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -39,4 +39,10 @@ config CAMSIG_MINOTAUR
         help
           Board supply package for CSP Minotaur
 
+config DNP5370
+        bool "SSV Dil/NetPC DNP/5370"
+        depends on (BF537)
+        help
+          Board supply package for DNP/5370 DIL64 module
+
 endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 7e6aa4e5b205..fe42258fe1f4 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
 obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM)  += tcm_bf537.o
 obj-$(CONFIG_PNAV10)                   += pnav10.o
 obj-$(CONFIG_CAMSIG_MINOTAUR)          += minotaur.o
+obj-$(CONFIG_DNP5370)                  += dnp5370.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 836698c4ee54..2c776e188a94 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -373,7 +373,7 @@ static struct resource bfin_uart0_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -434,7 +434,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -545,9 +545,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -579,9 +579,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index 2a85670273cb..085661175ec7 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -510,9 +510,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -544,9 +544,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
new file mode 100644
index 000000000000..e1e9ea02ad89
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -0,0 +1,418 @@
+/*
+ * This is the configuration for SSV Dil/NetPC DNP/5370 board.
+ *
+ * DIL module:         http://www.dilnetpc.com/dnp0086.htm
+ * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
+ *
+ * Copyright 2010 3ality Digital Systems
+ * Copyright 2005 National ICT Australia (NICTA)
+ * Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/spi/mmc_spi.h>
+#include <linux/phy.h>
+#include <asm/dma.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/reboot.h>
+#include <asm/portmux.h>
+#include <asm/dpmc.h>
+
+/*
+ * Name the Board for the /proc/cpuinfo
+ */
+const char bfin_board_name[] = "DNP/5370";
+#define FLASH_MAC               0x202f0000
+#define CONFIG_MTD_PHYSMAP_LEN  0x300000
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+static struct platform_device rtc_device = {
+        .name = "rtc-bfin",
+        .id   = -1,
+};
+#endif
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#include <linux/bfin_mac.h>
+static const unsigned short bfin_mac_peripherals[] = P_RMII0;
+
+static struct bfin_phydev_platform_data bfin_phydev_data[] = {
+        {
+                .addr = 1,
+                .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
+        },
+};
+
+static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
+        .phydev_number   = 1,
+        .phydev_data     = bfin_phydev_data,
+        .phy_mode        = PHY_INTERFACE_MODE_RMII,
+        .mac_peripherals = bfin_mac_peripherals,
+};
+
+static struct platform_device bfin_mii_bus = {
+        .name = "bfin_mii_bus",
+        .dev = {
+                .platform_data = &bfin_mii_bus_data,
+        }
+};
+
+static struct platform_device bfin_mac_device = {
+        .name = "bfin_mac",
+        .dev = {
+                .platform_data = &bfin_mii_bus,
+        }
+};
+#endif
+
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition asmb_flash_partitions[] = {
+        {
+                .name       = "bootloader(nor)",
+                .size       = 0x30000,
+                .offset     = 0,
+        }, {
+                .name       = "linux kernel and rootfs(nor)",
+                .size       = 0x300000 - 0x30000 - 0x10000,
+                .offset     = MTDPART_OFS_APPEND,
+        }, {
+                .name       = "MAC address(nor)",
+                .size       = 0x10000,
+                .offset     = MTDPART_OFS_APPEND,
+                .mask_flags = MTD_WRITEABLE,
+        }
+};
+
+static struct physmap_flash_data asmb_flash_data = {
+        .width      = 1,
+        .parts      = asmb_flash_partitions,
+        .nr_parts   = ARRAY_SIZE(asmb_flash_partitions),
+};
+
+static struct resource asmb_flash_resource = {
+        .start = 0x20000000,
+        .end   = 0x202fffff,
+        .flags = IORESOURCE_MEM,
+};
+
+/* 4 MB NOR flash attached to async memory banks 0-2,
+ * therefore only 3 MB visible.
+ */
+static struct platform_device asmb_flash_device = {
+        .name     = "physmap-flash",
+        .id       = 0,
+        .dev = {
+                .platform_data = &asmb_flash_data,
+        },
+        .num_resources = 1,
+        .resource      = &asmb_flash_resource,
+};
+#endif
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+
+#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+
+#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
+
+static int bfin_mmc_spi_init(struct device *dev,
+        irqreturn_t (*detect_int)(int, void *), void *data)
+{
+        return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
+                IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
+}
+
+static void bfin_mmc_spi_exit(struct device *dev, void *data)
+{
+        free_irq(MMC_SPI_CARD_DETECT_INT, data);
+}
+
+static struct bfin5xx_spi_chip mmc_spi_chip_info = {
+        .enable_dma    = 0,      /* use no dma transfer with this chip*/
+        .bits_per_word = 8,
+};
+
+static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
+        .init = bfin_mmc_spi_init,
+        .exit = bfin_mmc_spi_exit,
+        .detect_delay = 100, /* msecs */
+};
+#endif
+
+#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
+/* This mapping is for at45db642 it has 1056 page size,
+ * partition size and offset should be page aligned
+ */
+static struct mtd_partition bfin_spi_dataflash_partitions[] = {
+        {
+                .name   = "JFFS2 dataflash(nor)",
+#ifdef CONFIG_MTD_PAGESIZE_1024
+                .offset = 0x40000,
+                .size   = 0x7C0000,
+#else
+                .offset = 0x0,
+                .size   = 0x840000,
+#endif
+        }
+};
+
+static struct flash_platform_data bfin_spi_dataflash_data = {
+        .name     = "mtd_dataflash",
+        .parts    = bfin_spi_dataflash_partitions,
+        .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
+        .type     = "mtd_dataflash",
+};
+
+static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
+        .enable_dma    = 0,      /* use no dma transfer with this chip*/
+        .bits_per_word = 8,
+};
+#endif
+
+static struct spi_board_info bfin_spi_board_info[] __initdata = {
+/* SD/MMC card reader at SPI bus */
+#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+        {
+                .modalias        = "mmc_spi",
+                .max_speed_hz    = 20000000,
+                .bus_num         = 0,
+                .chip_select     = 1,
+                .platform_data   = &bfin_mmc_spi_pdata,
+                .controller_data = &mmc_spi_chip_info,
+                .mode            = SPI_MODE_3,
+        },
+#endif
+
+/* 8 Megabyte Atmel NOR flash chip at SPI bus */
+#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
+        {
+        .modalias        = "mtd_dataflash",
+        .max_speed_hz    = 16700000,
+        .bus_num         = 0,
+        .chip_select     = 2,
+        .platform_data   = &bfin_spi_dataflash_data,
+        .controller_data = &spi_dataflash_chip_info,
+        .mode            = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
+        },
+#endif
+};
+
+/* SPI controller data */
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct bfin5xx_spi_master spi_bfin_master_info = {
+        .num_chipselect = 8,
+        .enable_dma     = 1,  /* master has the ability to do dma transfer */
+        .pin_req        = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
+};
+
+static struct platform_device spi_bfin_master_device = {
+        .name          = "bfin-spi",
+        .id            = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource      = bfin_spi0_resource,
+        .dev           = {
+                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+        },
+};
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#ifdef CONFIG_SERIAL_BFIN_UART0
+static struct resource bfin_uart0_resources[] = {
+        {
+                .start = UART0_THR,
+                .end = UART0_GCTL+2,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_UART0_ERROR,
+                .end = IRQ_UART0_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_TX,
+                .end = CH_UART0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static unsigned short bfin_uart0_peripherals[] = {
+        P_UART0_TX, P_UART0_RX, 0
+};
+
+static struct platform_device bfin_uart0_device = {
+        .name = "bfin-uart",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_uart0_resources),
+        .resource = bfin_uart0_resources,
+        .dev = {
+                .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
+        },
+};
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_UART1
+static struct resource bfin_uart1_resources[] = {
+        {
+                .start = UART1_THR,
+                .end   = UART1_GCTL+2,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART1_RX,
+                .end   = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_UART1_ERROR,
+                .end   = IRQ_UART1_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_TX,
+                .end   = CH_UART1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end   = CH_UART1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static unsigned short bfin_uart1_peripherals[] = {
+        P_UART1_TX, P_UART1_RX, 0
+};
+
+static struct platform_device bfin_uart1_device = {
+        .name          = "bfin-uart",
+        .id            = 1,
+        .num_resources = ARRAY_SIZE(bfin_uart1_resources),
+        .resource      = bfin_uart1_resources,
+        .dev = {
+                .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
+        },
+};
+#endif
+#endif
+
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static struct resource bfin_twi0_resource[] = {
+        [0] = {
+                .start = TWI0_REGBASE,
+                .end   = TWI0_REGBASE + 0xff,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI,
+                .end   = IRQ_TWI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c_bfin_twi_device = {
+        .name          = "i2c-bfin-twi",
+        .id            = 0,
+        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
+        .resource      = bfin_twi0_resource,
+};
+#endif
+
+static struct platform_device *dnp5370_devices[] __initdata = {
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        &bfin_uart0_device,
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        &bfin_uart1_device,
+#endif
+#endif
+
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+        &asmb_flash_device,
+#endif
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+        &bfin_mii_bus,
+        &bfin_mac_device,
+#endif
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+        &spi_bfin_master_device,
+#endif
+
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+        &i2c_bfin_twi_device,
+#endif
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+        &rtc_device,
+#endif
+
+};
+
+static int __init dnp5370_init(void)
+{
+        printk(KERN_INFO "DNP/5370: registering device resources\n");
+        platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
+        printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
+               ARRAY_SIZE(bfin_spi_board_info));
+        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
+        printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
+        return 0;
+}
+arch_initcall(dnp5370_init);
+
+/*
+ * Currently the MAC address is saved in Flash by U-Boot
+ */
+void bfin_get_ether_addr(char *addr)
+{
+        *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
+        *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
+}
+EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index 49800518412c..bfb3671a78da 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -263,7 +263,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -306,7 +306,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -419,9 +419,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -453,9 +453,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index b95807894e25..9389f03e3b0a 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -367,7 +367,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -410,7 +410,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 3aa344ce8e52..2c69785a7bbe 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -289,7 +289,7 @@ static struct platform_device isp1362_hcd_device = {
 #endif
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
-unsigned short bfin_can_peripherals[] = {
+static unsigned short bfin_can_peripherals[] = {
         P_CAN0_RX, P_CAN0_TX, 0
 };
 
@@ -693,7 +693,7 @@ static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
 #endif
 
 #if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE)
-unsigned short ad2s120x_platform_data[] = {
+static unsigned short ad2s120x_platform_data[] = {
         /* used as SAMPLE and RDVEL */
         GPIO_PF5, GPIO_PF6, 0
 };
@@ -705,7 +705,7 @@ static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
 #endif
 
 #if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE)
-unsigned short ad2s1210_platform_data[] = {
+static unsigned short ad2s1210_platform_data[] = {
         /* use as SAMPLE, A0, A1 */
         GPIO_PF7, GPIO_PF8, GPIO_PF9,
 # if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
@@ -1717,7 +1717,7 @@ static struct resource bfin_uart0_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -1760,7 +1760,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -2447,9 +2447,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -2481,9 +2481,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 31498add1a42..0761b201abca 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -512,9 +512,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -546,9 +546,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
index 5c8c4ed517bb..5c62e99c9fac 100644
--- a/arch/blackfin/mach-bf537/dma.c
+++ b/arch/blackfin/mach-bf537/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      2
+
+#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
index 635c91c526a3..3e955dba8951 100644
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
@@ -54,49 +27,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        int                     status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int             cts_pin;
-        int             rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long   uart_base_addr;
         int             uart_irq;
@@ -145,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index a12d4b6a221d..baa096fc724a 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -1,7 +1,7 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_BLACKFIN_H_
@@ -10,34 +10,24 @@
 #define BF537_FAMILY
 
 #include "bf537.h"
-#include "defBF534.h"
 #include "anomaly.h"
 
+#include <asm/def_LPBlackfin.h>
+#ifdef CONFIG_BF534
+# include "defBF534.h"
+#endif
 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-#include "defBF537.h"
+# include "defBF537.h"
 #endif
 
 #if !defined(__ASSEMBLY__)
-#include "cdefBF534.h"
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-#include "cdefBF537.h"
+# include <asm/cdef_LPBlackfin.h>
+# ifdef CONFIG_BF534
+#  include "cdefBF534.h"
+# endif
+# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
+#  include "cdefBF537.h"
+# endif
 #endif
-#endif
-
-#define BFIN_UART_NR_PORTS      2
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
 
 #endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index fbeb35e14135..563ede907336 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF534_H
 #define _CDEF_BF534_H
 
-#include <asm/blackfin.h>
-
-/* Include all Core registers and bit definitions                                                                       */
-#include "defBF534.h"
-
-/* Include core specific register pointer definitions                                                           */
-#include <asm/cdef_LPBlackfin.h>
-
 /* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
 #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
 #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
@@ -355,16 +347,10 @@
 #define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
 
 /* DMA Traffic Control Registers                                                                                                        */
-#define bfin_read_DMA_TC_PER()                bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)            bfin_write16(DMA_TC_PER,val)
-#define bfin_read_DMA_TC_CNT()                bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)            bfin_write16(DMA_TC_CNT,val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
+#define bfin_read_DMAC_TC_PER()              bfin_read16(DMAC_TC_PER)
+#define bfin_write_DMAC_TC_PER(val)          bfin_write16(DMAC_TC_PER,val)
+#define bfin_read_DMAC_TC_CNT()              bfin_read16(DMAC_TC_CNT)
+#define bfin_write_DMAC_TC_CNT(val)          bfin_write16(DMAC_TC_CNT,val)
 
 /* DMA Controller                                                                                                                                       */
 #define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
@@ -1747,7 +1733,4 @@
 #define bfin_read_HMDMA1_BCOUNT()            bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)        bfin_write16(HMDMA1_BCOUNT,val)
 
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
 #endif                          /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
index 9363c3990421..19ec21ea150a 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later
  */
@@ -10,9 +10,6 @@
 /* Include MMRs Common to BF534                                                                 */
 #include "cdefBF534.h"
 
-/* Include all Core registers and bit definitions                                                                       */
-#include "defBF537.h"
-
 /* Include Macro "Defines" For EMAC (Unique to BF536/BF537              */
 /* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF)                                               */
 #define bfin_read_EMAC_OPMODE()              bfin_read32(EMAC_OPMODE)
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 0323e6bacdae..32529a03b266 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,9 +7,6 @@
 #ifndef _DEF_BF534_H
 #define _DEF_BF534_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
 /************************************************************************************
 ** System MMR Register Map
 *************************************************************************************/
@@ -193,12 +190,8 @@
 #define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
 
 /* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
+#define DMAC_TC_PER                     0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMAC_TC_CNT                     0xFFC00B10      /* Traffic Control Current Counts Register      */
 
 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
 #define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
@@ -1029,48 +1022,6 @@
 #define IWR_ENABLE(x)   (1 << ((x)&0x1F))       /* Wakeup Enable Peripheral #x          */
 #define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
 
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select   */
-#define STB                     0x04    /* Stop Bits                    */
-#define PEN                     0x08    /* Parity Enable                */
-#define EPS                     0x10    /* Even Parity Select   */
-#define STP                     0x20    /* Stick Parity                 */
-#define SB                      0x40    /* Set Break                    */
-#define DLAB            0x80    /* Divisor Latch Access */
-
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA                0x10    /* Loopback Mode Enable         */
-#define LOOP_ENA_P      0x04
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01    /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02    /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04    /* Enable RX Status Interrupt                           */
-
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01    /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01    /* Enable UARTx Clocks                          */
-#define IREN            0x02    /* Enable IrDA Mode                                     */
-#define TPOLC           0x04    /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08    /* IrDA RX Polarity Change                      */
-#define FPE                     0x10    /* Force Parity Error On Transmit       */
-#define FFE                     0x20    /* Force Framing Error On Transmit      */
-
 /*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
 /* TIMER_ENABLE Masks                                                                                                   */
 #define TIMEN0                  0x0001  /* Enable Timer 0                                       */
@@ -1141,62 +1092,6 @@
 #define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
 #define ERR_TYP                 0xC000  /* Error Type                                                   */
 
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-#define PH8             0x0100
-#define PH9             0x0200
-#define PH10    0x0400
-#define PH11    0x0800
-#define PH12    0x1000
-#define PH13    0x2000
-#define PH14    0x4000
-#define PH15    0x8000
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
 /* EBIU_AMGCTL Masks                                                                                                                                    */
 #define AMCKEN                  0x0001  /* Enable CLKOUT                                                                        */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
index 8cb5d5cf0c94..3d471d752684 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,9 +7,6 @@
 #ifndef _DEF_BF537_H
 #define _DEF_BF537_H
 
-/* Include all Core registers and bit definitions*/
-#include <asm/cdef_LPBlackfin.h>
-
 /* Include all MMR and bit defines common to BF534 */
 #include "defBF534.h"
 
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
index f80c2995efdb..fba606b699c3 100644
--- a/arch/blackfin/mach-bf537/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf537/include/mach/gpio.h
@@ -62,4 +62,8 @@
 #define PORT_G GPIO_PG0
 #define PORT_H GPIO_PH0
 
+#include <mach-common/ports-f.h>
+#include <mach-common/ports-g.h>
+#include <mach-common/ports-h.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
index 169c106d0edb..94cca674d835 100644
--- a/arch/blackfin/mach-bf537/include/mach/pll.h
+++ b/arch/blackfin/mach-bf537/include/mach/pll.h
@@ -1,57 +1 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index c6fb0a52f849..e61424ef35eb 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -82,7 +82,7 @@ static struct resource bfin_uart0_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -125,7 +125,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -168,7 +168,7 @@ static struct resource bfin_uart2_resources[] = {
         },
 };
 
-unsigned short bfin_uart2_peripherals[] = {
+static unsigned short bfin_uart2_peripherals[] = {
         P_UART2_TX, P_UART2_RX, 0
 };
 
@@ -282,9 +282,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -316,9 +316,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
@@ -350,7 +350,7 @@ static struct resource bfin_sport2_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport2_peripherals[] = {
+static unsigned short bfin_sport2_peripherals[] = {
         P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
         P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
 };
@@ -384,7 +384,7 @@ static struct resource bfin_sport3_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport3_peripherals[] = {
+static unsigned short bfin_sport3_peripherals[] = {
         P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
         P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
 };
@@ -402,7 +402,7 @@ static struct platform_device bfin_sport3_uart_device = {
 #endif
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
-unsigned short bfin_can_peripherals[] = {
+static unsigned short bfin_can_peripherals[] = {
         P_CAN0_RX, P_CAN0_TX, 0
 };
 
diff --git a/arch/blackfin/mach-bf538/dma.c b/arch/blackfin/mach-bf538/dma.c
index 5dc022589214..cce8ef5a5cec 100644
--- a/arch/blackfin/mach-bf538/dma.c
+++ b/arch/blackfin/mach-bf538/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
@@ -32,14 +32,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA17_NEXT_DESC_PTR,
         (struct dma_register *) DMA18_NEXT_DESC_PTR,
         (struct dma_register *) DMA19_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA0_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA0_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA0_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA0_S1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
 };
 EXPORT_SYMBOL(dma_io_base_addr);
 
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..c66e2760aad3
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      3
+
+#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
index 5c148142f041..beb502e9cb33 100644
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later.
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
-#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
-#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
-#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
-#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
-#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
@@ -54,50 +27,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        int                     status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int             cts_pin;
-        int             rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long   uart_base_addr;
         int             uart_irq;
@@ -160,3 +89,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 08b5eabb1ed5..791d08400cf0 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -10,31 +10,24 @@
 #define BF538_FAMILY
 
 #include "bf538.h"
-#include "defBF539.h"
 #include "anomaly.h"
 
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF538.h"
-
-#if defined(CONFIG_BF539)
-#include "cdefBF539.h"
+#include <asm/def_LPBlackfin.h>
+#ifdef CONFIG_BF538
+# include "defBF538.h"
 #endif
+#ifdef CONFIG_BF539
+# include "defBF539.h"
 #endif
 
-#define BFIN_UART_NR_PORTS      3
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# ifdef CONFIG_BF538
+#  include "cdefBF538.h"
+# endif
+# ifdef CONFIG_BF539
+#  include "cdefBF539.h"
+# endif
+#endif
 
 #endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 085b06b8c0a5..f6a56792180b 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF538_H
 #define _CDEF_BF538_H
 
-#include <asm/blackfin.h>
-
-/*include all Core registers and bit definitions*/
-#include "defBF539.h"
-
-/*include core specific register pointer definitions*/
-#include <asm/cdef_LPBlackfin.h>
-
 #define bfin_writePTR(addr, val) bfin_write32(addr, val)
 
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
@@ -487,10 +479,10 @@
 #define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
 #define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
 #define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA0_TC_PER()        bfin_read16(DMA0_TC_PER)
-#define bfin_write_DMA0_TC_PER(val)    bfin_write16(DMA0_TC_PER, val)
-#define bfin_read_DMA0_TC_CNT()        bfin_read16(DMA0_TC_CNT)
-#define bfin_write_DMA0_TC_CNT(val)    bfin_write16(DMA0_TC_CNT, val)
+#define bfin_read_DMAC0_TC_PER()       bfin_read16(DMAC0_TC_PER)
+#define bfin_write_DMAC0_TC_PER(val)   bfin_write16(DMAC0_TC_PER, val)
+#define bfin_read_DMAC0_TC_CNT()       bfin_read16(DMAC0_TC_CNT)
+#define bfin_write_DMAC0_TC_CNT(val)   bfin_write16(DMAC0_TC_CNT, val)
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
 #define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
@@ -699,10 +691,10 @@
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_TC_PER()        bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val)    bfin_write16(DMA1_TC_PER, val)
-#define bfin_read_DMA1_TC_CNT()        bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val)    bfin_write16(DMA1_TC_CNT, val)
+#define bfin_read_DMAC1_TC_PER()       bfin_read16(DMAC1_TC_PER)
+#define bfin_write_DMAC1_TC_PER(val)   bfin_write16(DMAC1_TC_PER, val)
+#define bfin_read_DMAC1_TC_CNT()       bfin_read16(DMAC1_TC_CNT)
+#define bfin_write_DMAC1_TC_CNT(val)   bfin_write16(DMAC1_TC_CNT, val)
 #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
 #define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
@@ -1015,273 +1007,214 @@
 #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
 #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
 #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_D0_START_ADDR() bfin_readPTR(MDMA0_D0_START_ADDR)
-#define bfin_write_MDMA0_D0_START_ADDR(val) bfin_writePTR(MDMA0_D0_START_ADDR, val)
-#define bfin_read_MDMA0_D0_CONFIG()    bfin_read16(MDMA0_D0_CONFIG)
-#define bfin_write_MDMA0_D0_CONFIG(val) bfin_write16(MDMA0_D0_CONFIG, val)
-#define bfin_read_MDMA0_D0_X_COUNT()   bfin_read16(MDMA0_D0_X_COUNT)
-#define bfin_write_MDMA0_D0_X_COUNT(val) bfin_write16(MDMA0_D0_X_COUNT, val)
-#define bfin_read_MDMA0_D0_X_MODIFY()  bfin_read16(MDMA0_D0_X_MODIFY)
-#define bfin_write_MDMA0_D0_X_MODIFY(val) bfin_write16(MDMA0_D0_X_MODIFY, val)
-#define bfin_read_MDMA0_D0_Y_COUNT()   bfin_read16(MDMA0_D0_Y_COUNT)
-#define bfin_write_MDMA0_D0_Y_COUNT(val) bfin_write16(MDMA0_D0_Y_COUNT, val)
-#define bfin_read_MDMA0_D0_Y_MODIFY()  bfin_read16(MDMA0_D0_Y_MODIFY)
-#define bfin_write_MDMA0_D0_Y_MODIFY(val) bfin_write16(MDMA0_D0_Y_MODIFY, val)
-#define bfin_read_MDMA0_D0_CURR_DESC_PTR() bfin_readPTR(MDMA0_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_D0_CURR_ADDR() bfin_readPTR(MDMA0_D0_CURR_ADDR)
-#define bfin_write_MDMA0_D0_CURR_ADDR(val) bfin_writePTR(MDMA0_D0_CURR_ADDR, val)
-#define bfin_read_MDMA0_D0_IRQ_STATUS() bfin_read16(MDMA0_D0_IRQ_STATUS)
-#define bfin_write_MDMA0_D0_IRQ_STATUS(val) bfin_write16(MDMA0_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_D0_PERIPHERAL_MAP() bfin_read16(MDMA0_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_D0_CURR_X_COUNT() bfin_read16(MDMA0_D0_CURR_X_COUNT)
-#define bfin_write_MDMA0_D0_CURR_X_COUNT(val) bfin_write16(MDMA0_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_D0_CURR_Y_COUNT() bfin_read16(MDMA0_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_D0_CURR_Y_COUNT(val) bfin_write16(MDMA0_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_S0_START_ADDR() bfin_readPTR(MDMA0_S0_START_ADDR)
-#define bfin_write_MDMA0_S0_START_ADDR(val) bfin_writePTR(MDMA0_S0_START_ADDR, val)
-#define bfin_read_MDMA0_S0_CONFIG()    bfin_read16(MDMA0_S0_CONFIG)
-#define bfin_write_MDMA0_S0_CONFIG(val) bfin_write16(MDMA0_S0_CONFIG, val)
-#define bfin_read_MDMA0_S0_X_COUNT()   bfin_read16(MDMA0_S0_X_COUNT)
-#define bfin_write_MDMA0_S0_X_COUNT(val) bfin_write16(MDMA0_S0_X_COUNT, val)
-#define bfin_read_MDMA0_S0_X_MODIFY()  bfin_read16(MDMA0_S0_X_MODIFY)
-#define bfin_write_MDMA0_S0_X_MODIFY(val) bfin_write16(MDMA0_S0_X_MODIFY, val)
-#define bfin_read_MDMA0_S0_Y_COUNT()   bfin_read16(MDMA0_S0_Y_COUNT)
-#define bfin_write_MDMA0_S0_Y_COUNT(val) bfin_write16(MDMA0_S0_Y_COUNT, val)
-#define bfin_read_MDMA0_S0_Y_MODIFY()  bfin_read16(MDMA0_S0_Y_MODIFY)
-#define bfin_write_MDMA0_S0_Y_MODIFY(val) bfin_write16(MDMA0_S0_Y_MODIFY, val)
-#define bfin_read_MDMA0_S0_CURR_DESC_PTR() bfin_readPTR(MDMA0_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_S0_CURR_ADDR() bfin_readPTR(MDMA0_S0_CURR_ADDR)
-#define bfin_write_MDMA0_S0_CURR_ADDR(val) bfin_writePTR(MDMA0_S0_CURR_ADDR, val)
-#define bfin_read_MDMA0_S0_IRQ_STATUS() bfin_read16(MDMA0_S0_IRQ_STATUS)
-#define bfin_write_MDMA0_S0_IRQ_STATUS(val) bfin_write16(MDMA0_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_S0_PERIPHERAL_MAP() bfin_read16(MDMA0_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_S0_CURR_X_COUNT() bfin_read16(MDMA0_S0_CURR_X_COUNT)
-#define bfin_write_MDMA0_S0_CURR_X_COUNT(val) bfin_write16(MDMA0_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_S0_CURR_Y_COUNT() bfin_read16(MDMA0_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_S0_CURR_Y_COUNT(val) bfin_write16(MDMA0_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_D1_START_ADDR() bfin_readPTR(MDMA0_D1_START_ADDR)
-#define bfin_write_MDMA0_D1_START_ADDR(val) bfin_writePTR(MDMA0_D1_START_ADDR, val)
-#define bfin_read_MDMA0_D1_CONFIG()    bfin_read16(MDMA0_D1_CONFIG)
-#define bfin_write_MDMA0_D1_CONFIG(val) bfin_write16(MDMA0_D1_CONFIG, val)
-#define bfin_read_MDMA0_D1_X_COUNT()   bfin_read16(MDMA0_D1_X_COUNT)
-#define bfin_write_MDMA0_D1_X_COUNT(val) bfin_write16(MDMA0_D1_X_COUNT, val)
-#define bfin_read_MDMA0_D1_X_MODIFY()  bfin_read16(MDMA0_D1_X_MODIFY)
-#define bfin_write_MDMA0_D1_X_MODIFY(val) bfin_write16(MDMA0_D1_X_MODIFY, val)
-#define bfin_read_MDMA0_D1_Y_COUNT()   bfin_read16(MDMA0_D1_Y_COUNT)
-#define bfin_write_MDMA0_D1_Y_COUNT(val) bfin_write16(MDMA0_D1_Y_COUNT, val)
-#define bfin_read_MDMA0_D1_Y_MODIFY()  bfin_read16(MDMA0_D1_Y_MODIFY)
-#define bfin_write_MDMA0_D1_Y_MODIFY(val) bfin_write16(MDMA0_D1_Y_MODIFY, val)
-#define bfin_read_MDMA0_D1_CURR_DESC_PTR() bfin_readPTR(MDMA0_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA0_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_D1_CURR_ADDR() bfin_readPTR(MDMA0_D1_CURR_ADDR)
-#define bfin_write_MDMA0_D1_CURR_ADDR(val) bfin_writePTR(MDMA0_D1_CURR_ADDR, val)
-#define bfin_read_MDMA0_D1_IRQ_STATUS() bfin_read16(MDMA0_D1_IRQ_STATUS)
-#define bfin_write_MDMA0_D1_IRQ_STATUS(val) bfin_write16(MDMA0_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA0_D1_PERIPHERAL_MAP() bfin_read16(MDMA0_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_D1_CURR_X_COUNT() bfin_read16(MDMA0_D1_CURR_X_COUNT)
-#define bfin_write_MDMA0_D1_CURR_X_COUNT(val) bfin_write16(MDMA0_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_D1_CURR_Y_COUNT() bfin_read16(MDMA0_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA0_D1_CURR_Y_COUNT(val) bfin_write16(MDMA0_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_S1_START_ADDR() bfin_readPTR(MDMA0_S1_START_ADDR)
-#define bfin_write_MDMA0_S1_START_ADDR(val) bfin_writePTR(MDMA0_S1_START_ADDR, val)
-#define bfin_read_MDMA0_S1_CONFIG()    bfin_read16(MDMA0_S1_CONFIG)
-#define bfin_write_MDMA0_S1_CONFIG(val) bfin_write16(MDMA0_S1_CONFIG, val)
-#define bfin_read_MDMA0_S1_X_COUNT()   bfin_read16(MDMA0_S1_X_COUNT)
-#define bfin_write_MDMA0_S1_X_COUNT(val) bfin_write16(MDMA0_S1_X_COUNT, val)
-#define bfin_read_MDMA0_S1_X_MODIFY()  bfin_read16(MDMA0_S1_X_MODIFY)
-#define bfin_write_MDMA0_S1_X_MODIFY(val) bfin_write16(MDMA0_S1_X_MODIFY, val)
-#define bfin_read_MDMA0_S1_Y_COUNT()   bfin_read16(MDMA0_S1_Y_COUNT)
-#define bfin_write_MDMA0_S1_Y_COUNT(val) bfin_write16(MDMA0_S1_Y_COUNT, val)
-#define bfin_read_MDMA0_S1_Y_MODIFY()  bfin_read16(MDMA0_S1_Y_MODIFY)
-#define bfin_write_MDMA0_S1_Y_MODIFY(val) bfin_write16(MDMA0_S1_Y_MODIFY, val)
-#define bfin_read_MDMA0_S1_CURR_DESC_PTR() bfin_readPTR(MDMA0_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA0_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_S1_CURR_ADDR() bfin_readPTR(MDMA0_S1_CURR_ADDR)
-#define bfin_write_MDMA0_S1_CURR_ADDR(val) bfin_writePTR(MDMA0_S1_CURR_ADDR, val)
-#define bfin_read_MDMA0_S1_IRQ_STATUS() bfin_read16(MDMA0_S1_IRQ_STATUS)
-#define bfin_write_MDMA0_S1_IRQ_STATUS(val) bfin_write16(MDMA0_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA0_S1_PERIPHERAL_MAP() bfin_read16(MDMA0_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_S1_CURR_X_COUNT() bfin_read16(MDMA0_S1_CURR_X_COUNT)
-#define bfin_write_MDMA0_S1_CURR_X_COUNT(val) bfin_write16(MDMA0_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_S1_CURR_Y_COUNT() bfin_read16(MDMA0_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA0_S1_CURR_Y_COUNT(val) bfin_write16(MDMA0_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
-#define bfin_read_MDMA1_D0_CONFIG()    bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
-#define bfin_read_MDMA1_D0_X_COUNT()   bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
-#define bfin_read_MDMA1_D0_X_MODIFY()  bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
-#define bfin_read_MDMA1_D0_Y_COUNT()   bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_Y_MODIFY()  bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
-#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
-#define bfin_read_MDMA1_S0_CONFIG()    bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
-#define bfin_read_MDMA1_S0_X_COUNT()   bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
-#define bfin_read_MDMA1_S0_X_MODIFY()  bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
-#define bfin_read_MDMA1_S0_Y_COUNT()   bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_Y_MODIFY()  bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
-#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
-#define bfin_read_MDMA1_D1_CONFIG()    bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
-#define bfin_read_MDMA1_D1_X_COUNT()   bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
-#define bfin_read_MDMA1_D1_X_MODIFY()  bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
-#define bfin_read_MDMA1_D1_Y_COUNT()   bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_Y_MODIFY()  bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
-#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
-#define bfin_read_MDMA1_S1_CONFIG()    bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
-#define bfin_read_MDMA1_S1_X_COUNT()   bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
-#define bfin_read_MDMA1_S1_X_MODIFY()  bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
-#define bfin_read_MDMA1_S1_Y_COUNT()   bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_Y_MODIFY()  bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
-#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
-
-#define bfin_read_MDMA_S0_CONFIG()  bfin_read_MDMA0_S0_CONFIG()
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA0_S0_CONFIG(val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()  bfin_read_MDMA0_S0_IRQ_STATUS()
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA0_S0_IRQ_STATUS(val)
-#define bfin_read_MDMA_S0_X_MODIFY()  bfin_read_MDMA0_S0_X_MODIFY()
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA0_S0_X_MODIFY(val)
-#define bfin_read_MDMA_S0_Y_MODIFY()  bfin_read_MDMA0_S0_Y_MODIFY()
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA0_S0_Y_MODIFY(val)
-#define bfin_read_MDMA_S0_X_COUNT()  bfin_read_MDMA0_S0_X_COUNT()
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA0_S0_X_COUNT(val)
-#define bfin_read_MDMA_S0_Y_COUNT()  bfin_read_MDMA0_S0_Y_COUNT()
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA0_S0_Y_COUNT(val)
-#define bfin_read_MDMA_S0_START_ADDR()  bfin_read_MDMA0_S0_START_ADDR()
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA0_S0_START_ADDR(val)
-#define bfin_read_MDMA_D0_CONFIG()  bfin_read_MDMA0_D0_CONFIG()
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA0_D0_CONFIG(val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()  bfin_read_MDMA0_D0_IRQ_STATUS()
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA0_D0_IRQ_STATUS(val)
-#define bfin_read_MDMA_D0_X_MODIFY()  bfin_read_MDMA0_D0_X_MODIFY()
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA0_D0_X_MODIFY(val)
-#define bfin_read_MDMA_D0_Y_MODIFY()  bfin_read_MDMA0_D0_Y_MODIFY()
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA0_D0_Y_MODIFY(val)
-#define bfin_read_MDMA_D0_X_COUNT()  bfin_read_MDMA0_D0_X_COUNT()
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA0_D0_X_COUNT(val)
-#define bfin_read_MDMA_D0_Y_COUNT()  bfin_read_MDMA0_D0_Y_COUNT()
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA0_D0_Y_COUNT(val)
-#define bfin_read_MDMA_D0_START_ADDR()  bfin_read_MDMA0_D0_START_ADDR()
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA0_D0_START_ADDR(val)
-
-#define bfin_read_MDMA_S1_CONFIG()  bfin_read_MDMA0_S1_CONFIG()
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA0_S1_CONFIG(val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()  bfin_read_MDMA0_S1_IRQ_STATUS()
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA0_S1_IRQ_STATUS(val)
-#define bfin_read_MDMA_S1_X_MODIFY()  bfin_read_MDMA0_S1_X_MODIFY()
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA0_S1_X_MODIFY(val)
-#define bfin_read_MDMA_S1_Y_MODIFY()  bfin_read_MDMA0_S1_Y_MODIFY()
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA0_S1_Y_MODIFY(val)
-#define bfin_read_MDMA_S1_X_COUNT()  bfin_read_MDMA0_S1_X_COUNT()
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA0_S1_X_COUNT(val)
-#define bfin_read_MDMA_S1_Y_COUNT()  bfin_read_MDMA0_S1_Y_COUNT()
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA0_S1_Y_COUNT(val)
-#define bfin_read_MDMA_S1_START_ADDR()  bfin_read_MDMA0_S1_START_ADDR()
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA0_S1_START_ADDR(val)
-#define bfin_read_MDMA_D1_CONFIG()  bfin_read_MDMA0_D1_CONFIG()
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA0_D1_CONFIG(val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()  bfin_read_MDMA0_D1_IRQ_STATUS()
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA0_D1_IRQ_STATUS(val)
-#define bfin_read_MDMA_D1_X_MODIFY()  bfin_read_MDMA0_D1_X_MODIFY()
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA0_D1_X_MODIFY(val)
-#define bfin_read_MDMA_D1_Y_MODIFY()  bfin_read_MDMA0_D1_Y_MODIFY()
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA0_D1_Y_MODIFY(val)
-#define bfin_read_MDMA_D1_X_COUNT()  bfin_read_MDMA0_D1_X_COUNT()
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA0_D1_X_COUNT(val)
-#define bfin_read_MDMA_D1_Y_COUNT()  bfin_read_MDMA0_D1_Y_COUNT()
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA0_D1_Y_COUNT(val)
-#define bfin_read_MDMA_D1_START_ADDR()  bfin_read_MDMA0_D1_START_ADDR()
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA0_D1_START_ADDR(val)
-
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define bfin_read_MDMA_D0_CONFIG()    bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_X_COUNT()   bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY()  bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define bfin_read_MDMA_D0_Y_COUNT()   bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_Y_MODIFY()  bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define bfin_read_MDMA_S0_CONFIG()    bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_X_COUNT()   bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY()  bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define bfin_read_MDMA_S0_Y_COUNT()   bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_Y_MODIFY()  bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define bfin_read_MDMA_D1_CONFIG()    bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_X_COUNT()   bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY()  bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define bfin_read_MDMA_D1_Y_COUNT()   bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_Y_MODIFY()  bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define bfin_read_MDMA_S1_CONFIG()    bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_X_COUNT()   bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY()  bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define bfin_read_MDMA_S1_Y_COUNT()   bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_Y_MODIFY()  bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define bfin_read_MDMA_D2_CONFIG()    bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define bfin_read_MDMA_D2_X_COUNT()   bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define bfin_read_MDMA_D2_X_MODIFY()  bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define bfin_read_MDMA_D2_Y_COUNT()   bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define bfin_read_MDMA_D2_Y_MODIFY()  bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define bfin_read_MDMA_S2_CONFIG()    bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define bfin_read_MDMA_S2_X_COUNT()   bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define bfin_read_MDMA_S2_X_MODIFY()  bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define bfin_read_MDMA_S2_Y_COUNT()   bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define bfin_read_MDMA_S2_Y_MODIFY()  bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define bfin_read_MDMA_D3_CONFIG()    bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define bfin_read_MDMA_D3_X_COUNT()   bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define bfin_read_MDMA_D3_X_MODIFY()  bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define bfin_read_MDMA_D3_Y_COUNT()   bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define bfin_read_MDMA_D3_Y_MODIFY()  bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define bfin_read_MDMA_S3_CONFIG()    bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define bfin_read_MDMA_S3_X_COUNT()   bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define bfin_read_MDMA_S3_X_MODIFY()  bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define bfin_read_MDMA_S3_Y_COUNT()   bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define bfin_read_MDMA_S3_Y_MODIFY()  bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
 #define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
 #define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
 #define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
@@ -2024,7 +1957,4 @@
 #define bfin_read_CAN_MB31_ID1()       bfin_read16(CAN_MB31_ID1)
 #define bfin_write_CAN_MB31_ID1(val)   bfin_write16(CAN_MB31_ID1, val)
 
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
 #endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
index 198c4bbc8e5d..acc15f3aba38 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
@@ -1,6 +1,7 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
+/*
+ * Copyright 2008-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _CDEF_BF539_H
@@ -9,7 +10,6 @@
 /* Include MMRs Common to BF538                                                                 */
 #include "cdefBF538.h"
 
-
 #define bfin_read_MXVR_CONFIG()        bfin_read16(MXVR_CONFIG)
 #define bfin_write_MXVR_CONFIG(val)    bfin_write16(MXVR_CONFIG, val)
 #define bfin_read_MXVR_PLL_CTL_0()     bfin_read32(MXVR_PLL_CTL_0)
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h
new file mode 100644
index 000000000000..d27f81d6c4b1
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/defBF538.h
@@ -0,0 +1,1825 @@
+/*
+ * Copyright 2008-2010 Analog Devices Inc.
+ *
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
+ */
+
+#ifndef _DEF_BF538_H
+#define _DEF_BF538_H
+
+/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL                 0xFFC00000      /* PLL Control register (16-bit) */
+#define PLL_DIV                 0xFFC00004      /* PLL Divide Register (16-bit) */
+#define VR_CTL                  0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT                0xFFC0000C      /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT             0xFFC00010      /* PLL Lock     Count register (16-bit) */
+#define CHIPID                  0xFFC00014      /* Chip ID Register */
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST                   0xFFC00100  /* Software Reset Register (16-bit) */
+#define SYSCR                   0xFFC00104  /* System Configuration registe */
+#define SIC_RVECT               0xFFC00108
+#define SIC_IMASK0              0xFFC0010C  /* Interrupt Mask Register */
+#define SIC_IAR0                0xFFC00110  /* Interrupt Assignment Register 0 */
+#define SIC_IAR1                0xFFC00114  /* Interrupt Assignment Register 1 */
+#define SIC_IAR2                0xFFC00118  /* Interrupt Assignment Register 2 */
+#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3 */
+#define SIC_ISR0                        0xFFC00120  /* Interrupt Status Register */
+#define SIC_IWR0                        0xFFC00124  /* Interrupt Wakeup Register */
+#define SIC_IMASK1                      0xFFC00128      /* Interrupt Mask Register 1 */
+#define SIC_ISR1                        0xFFC0012C      /* Interrupt Status Register 1 */
+#define SIC_IWR1                        0xFFC00130      /* Interrupt Wakeup Register 1 */
+#define SIC_IAR4                        0xFFC00134      /* Interrupt Assignment Register 4 */
+#define SIC_IAR5                        0xFFC00138      /* Interrupt Assignment Register 5 */
+#define SIC_IAR6                        0xFFC0013C      /* Interrupt Assignment Register 6 */
+
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL        0xFFC00200  /* Watchdog Control Register */
+#define WDOG_CNT        0xFFC00204  /* Watchdog Count Register */
+#define WDOG_STAT       0xFFC00208  /* Watchdog Status Register */
+
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT        0xFFC00300  /* RTC Status Register */
+#define RTC_ICTL        0xFFC00304  /* RTC Interrupt Control Register */
+#define RTC_ISTAT       0xFFC00308  /* RTC Interrupt Status Register */
+#define RTC_SWCNT       0xFFC0030C  /* RTC Stopwatch Count Register */
+#define RTC_ALARM       0xFFC00310  /* RTC Alarm Time Register */
+#define RTC_FAST        0xFFC00314  /* RTC Prescaler Enable Register */
+#define RTC_PREN                0xFFC00314  /* RTC Prescaler Enable Register (alternate macro) */
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART0_THR             0xFFC00400  /* Transmit Holding register */
+#define UART0_RBR             0xFFC00400  /* Receive Buffer register */
+#define UART0_DLL             0xFFC00400  /* Divisor Latch (Low-Byte) */
+#define UART0_IER             0xFFC00404  /* Interrupt Enable Register */
+#define UART0_DLH             0xFFC00404  /* Divisor Latch (High-Byte) */
+#define UART0_IIR             0xFFC00408  /* Interrupt Identification Register */
+#define UART0_LCR             0xFFC0040C  /* Line Control Register */
+#define UART0_MCR                        0xFFC00410  /* Modem Control Register */
+#define UART0_LSR             0xFFC00414  /* Line Status Register */
+#define UART0_SCR             0xFFC0041C  /* SCR Scratch Register */
+#define UART0_GCTL                   0xFFC00424  /* Global Control Register */
+
+
+/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
+
+#define SPI0_CTL                        0xFFC00500  /* SPI0 Control Register */
+#define SPI0_FLG                        0xFFC00504  /* SPI0 Flag register */
+#define SPI0_STAT                       0xFFC00508  /* SPI0 Status register */
+#define SPI0_TDBR                       0xFFC0050C  /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                       0xFFC00510  /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                       0xFFC00514  /* SPI0 Baud rate Register */
+#define SPI0_SHADOW                     0xFFC00518  /* SPI0_RDBR Shadow Register */
+#define SPI0_REGBASE                    SPI0_CTL
+
+
+/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG                   0xFFC00600     /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                          0xFFC00604     /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                   0xFFC00608     /* Timer 0 Period Register */
+#define TIMER0_WIDTH                    0xFFC0060C     /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG                   0xFFC00610      /*  Timer 1 Configuration Register   */
+#define TIMER1_COUNTER                  0xFFC00614      /*  Timer 1 Counter Register         */
+#define TIMER1_PERIOD                   0xFFC00618      /*  Timer 1 Period Register          */
+#define TIMER1_WIDTH                    0xFFC0061C      /*  Timer 1 Width Register           */
+
+#define TIMER2_CONFIG                   0xFFC00620      /* Timer 2 Configuration Register   */
+#define TIMER2_COUNTER                  0xFFC00624      /* Timer 2 Counter Register         */
+#define TIMER2_PERIOD                   0xFFC00628      /* Timer 2 Period Register          */
+#define TIMER2_WIDTH                    0xFFC0062C      /* Timer 2 Width Register           */
+
+#define TIMER_ENABLE                            0xFFC00640      /* Timer Enable Register */
+#define TIMER_DISABLE                           0xFFC00644      /* Timer Disable Register */
+#define TIMER_STATUS                            0xFFC00648      /* Timer Status Register */
+
+
+/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
+#define FIO_FLAG_D                              0xFFC00700  /* Flag Mask to directly specify state of pins */
+#define FIO_FLAG_C                      0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
+#define FIO_FLAG_S                      0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
+#define FIO_FLAG_T                                      0xFFC0070C  /* Flag Mask to directly toggle state of pins */
+#define FIO_MASKA_D                     0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
+#define FIO_MASKA_C                     0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
+#define FIO_MASKA_S                     0xFFC00718  /* Flag Mask Interrupt A Register (set) */
+#define FIO_MASKA_T                     0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
+#define FIO_MASKB_D                     0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
+#define FIO_MASKB_C                     0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
+#define FIO_MASKB_S                     0xFFC00728  /* Flag Mask Interrupt B Register (set) */
+#define FIO_MASKB_T                     0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
+#define FIO_DIR                         0xFFC00730  /* Peripheral Flag Direction Register */
+#define FIO_POLAR                       0xFFC00734  /* Flag Source Polarity Register */
+#define FIO_EDGE                        0xFFC00738  /* Flag Source Sensitivity Register */
+#define FIO_BOTH                        0xFFC0073C  /* Flag Set on BOTH Edges Register */
+#define FIO_INEN                                        0xFFC00740  /* Flag Input Enable Register  */
+
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1                             0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                             0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                  0xFFC00808  /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV                   0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX                       0xFFC00810  /* SPORT0 TX Data Register */
+#define SPORT0_RX                       0xFFC00818  /* SPORT0 RX Data Register */
+#define SPORT0_RCR1                             0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2                             0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV                  0xFFC00828  /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV                   0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT                     0xFFC00830  /* SPORT0 Status Register */
+#define SPORT0_CHNL                     0xFFC00834  /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1                    0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2                    0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0                    0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                    0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                    0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                    0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0                    0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1                    0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2                    0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3                    0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1                             0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                             0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                  0xFFC00908  /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV                   0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX                       0xFFC00910  /* SPORT1 TX Data Register */
+#define SPORT1_RX                       0xFFC00918  /* SPORT1 RX Data Register */
+#define SPORT1_RCR1                             0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2                             0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV                  0xFFC00928  /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV                   0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT                     0xFFC00930  /* SPORT1 Status Register */
+#define SPORT1_CHNL                     0xFFC00934  /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1                    0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2                    0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0                    0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                    0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                    0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                    0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0                    0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1                    0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2                    0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3                    0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+/* Asynchronous Memory Controller  */
+#define EBIU_AMGCTL                     0xFFC00A00  /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0            0xFFC00A04  /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1            0xFFC00A08  /* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller */
+#define EBIU_SDGCTL                     0xFFC00A10  /* SDRAM Global Control Register */
+#define EBIU_SDBCTL                     0xFFC00A14  /* SDRAM Bank Control Register */
+#define EBIU_SDRRC                      0xFFC00A18  /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT                     0xFFC00A1C  /* SDRAM Status Register */
+
+
+
+/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
+
+#define DMAC0_TC_PER                    0xFFC00B0C      /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TC_CNT                    0xFFC00B10      /* DMA Controller 0 Traffic Control Current Counts Register */
+
+
+
+/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF)                                                    */
+
+#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register */
+
+#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register */
+
+#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register */
+
+#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register */
+
+#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register */
+
+#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register */
+
+#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register */
+
+#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register */
+
+#define MDMA_D0_NEXT_DESC_PTR   0xFFC00E00      /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR              0xFFC00E04      /* MemDMA0 Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                  0xFFC00E08      /* MemDMA0 Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT         0xFFC00E10      /* MemDMA0 Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY                0xFFC00E14      /* MemDMA0 Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT         0xFFC00E18      /* MemDMA0 Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY                0xFFC00E1C      /* MemDMA0 Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR   0xFFC00E20      /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR               0xFFC00E24      /* MemDMA0 Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS              0xFFC00E28      /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP  0xFFC00E2C      /* MemDMA0 Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT    0xFFC00E30      /* MemDMA0 Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT    0xFFC00E38      /* MemDMA0 Stream 0 Destination Current Y Count Register */
+
+#define MDMA_S0_NEXT_DESC_PTR   0xFFC00E40      /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR              0xFFC00E44      /* MemDMA0 Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                  0xFFC00E48      /* MemDMA0 Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT         0xFFC00E50      /* MemDMA0 Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY                0xFFC00E54      /* MemDMA0 Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT         0xFFC00E58      /* MemDMA0 Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY                0xFFC00E5C      /* MemDMA0 Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR   0xFFC00E60      /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR               0xFFC00E64      /* MemDMA0 Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS              0xFFC00E68      /* MemDMA0 Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP  0xFFC00E6C      /* MemDMA0 Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT    0xFFC00E70      /* MemDMA0 Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT    0xFFC00E78      /* MemDMA0 Stream 0 Source Current Y Count Register */
+
+#define MDMA_D1_NEXT_DESC_PTR   0xFFC00E80      /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR              0xFFC00E84      /* MemDMA0 Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                  0xFFC00E88      /* MemDMA0 Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT         0xFFC00E90      /* MemDMA0 Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY                0xFFC00E94      /* MemDMA0 Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT         0xFFC00E98      /* MemDMA0 Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY                0xFFC00E9C      /* MemDMA0 Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR   0xFFC00EA0      /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR               0xFFC00EA4      /* MemDMA0 Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS              0xFFC00EA8      /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP  0xFFC00EAC      /* MemDMA0 Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT    0xFFC00EB0      /* MemDMA0 Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT    0xFFC00EB8      /* MemDMA0 Stream 1 Destination Current Y Count Register */
+
+#define MDMA_S1_NEXT_DESC_PTR   0xFFC00EC0      /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR              0xFFC00EC4      /* MemDMA0 Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                  0xFFC00EC8      /* MemDMA0 Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT         0xFFC00ED0      /* MemDMA0 Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY                0xFFC00ED4      /* MemDMA0 Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT         0xFFC00ED8      /* MemDMA0 Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY                0xFFC00EDC      /* MemDMA0 Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR   0xFFC00EE0      /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR               0xFFC00EE4      /* MemDMA0 Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS              0xFFC00EE8      /* MemDMA0 Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP  0xFFC00EEC      /* MemDMA0 Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT    0xFFC00EF0      /* MemDMA0 Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT    0xFFC00EF8      /* MemDMA0 Stream 1 Source Current Y Count Register */
+
+
+/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register */
+
+
+/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF)                        */
+#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register */
+#define TWI0_CONTROL            0xFFC01404      /* TWI0 Master Internal Time Reference Register */
+#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register */
+#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register */
+#define TWI0_MASTER_CTL 0xFFC01414      /* Master Mode Control Register */
+#define TWI0_MASTER_STAT        0xFFC01418      /* Master Mode Status Register */
+#define TWI0_MASTER_ADDR        0xFFC0141C      /* Master Mode Address Register */
+#define TWI0_INT_STAT           0xFFC01420      /* TWI0 Master Interrupt Register */
+#define TWI0_INT_MASK           0xFFC01424      /* TWI0 Master Interrupt Mask Register */
+#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register */
+#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register */
+#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register */
+
+#define TWI0_REGBASE            TWI0_CLKDIV
+
+/* the following are for backwards compatibility */
+#define TWI0_PRESCALE    TWI0_CONTROL
+#define TWI0_INT_SRC     TWI0_INT_STAT
+#define TWI0_INT_ENABLE  TWI0_INT_MASK
+
+
+/* General-Purpose Ports  (0xFFC01500 - 0xFFC015FF)      */
+
+/* GPIO Port C Register Names */
+#define PORTCIO_FER                     0xFFC01500      /* GPIO Pin Port C Configuration Register */
+#define PORTCIO                         0xFFC01510      /* GPIO Pin Port C Data Register */
+#define PORTCIO_CLEAR                   0xFFC01520      /* Clear GPIO Pin Port C Register */
+#define PORTCIO_SET                     0xFFC01530      /* Set GPIO Pin Port C Register */
+#define PORTCIO_TOGGLE                  0xFFC01540      /* Toggle GPIO Pin Port C Register */
+#define PORTCIO_DIR                     0xFFC01550      /* GPIO Pin Port C Direction Register */
+#define PORTCIO_INEN                    0xFFC01560      /* GPIO Pin Port C Input Enable Register */
+
+/* GPIO Port D Register Names */
+#define PORTDIO_FER                     0xFFC01504      /* GPIO Pin Port D Configuration Register */
+#define PORTDIO                         0xFFC01514      /* GPIO Pin Port D Data Register */
+#define PORTDIO_CLEAR                   0xFFC01524      /* Clear GPIO Pin Port D Register */
+#define PORTDIO_SET                     0xFFC01534      /* Set GPIO Pin Port D Register */
+#define PORTDIO_TOGGLE                  0xFFC01544      /* Toggle GPIO Pin Port D Register */
+#define PORTDIO_DIR                     0xFFC01554      /* GPIO Pin Port D Direction Register */
+#define PORTDIO_INEN                    0xFFC01564      /* GPIO Pin Port D Input Enable Register */
+
+/* GPIO Port E Register Names */
+#define PORTEIO_FER                     0xFFC01508      /* GPIO Pin Port E Configuration Register */
+#define PORTEIO                         0xFFC01518      /* GPIO Pin Port E Data Register */
+#define PORTEIO_CLEAR                   0xFFC01528      /* Clear GPIO Pin Port E Register */
+#define PORTEIO_SET                     0xFFC01538      /* Set GPIO Pin Port E Register */
+#define PORTEIO_TOGGLE                  0xFFC01548      /* Toggle GPIO Pin Port E Register */
+#define PORTEIO_DIR                     0xFFC01558      /* GPIO Pin Port E Direction Register */
+#define PORTEIO_INEN                    0xFFC01568      /* GPIO Pin Port E Input Enable Register */
+
+/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
+
+#define DMAC1_TC_PER                    0xFFC01B0C      /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TC_CNT                    0xFFC01B10      /* DMA Controller 1 Traffic Control Current Counts Register */
+
+
+
+/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF)                                                    */
+#define DMA8_NEXT_DESC_PTR              0xFFC01C00      /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                 0xFFC01C04      /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                             0xFFC01C08      /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                    0xFFC01C10      /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                   0xFFC01C14      /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                    0xFFC01C18      /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                   0xFFC01C1C      /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR              0xFFC01C20      /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                  0xFFC01C24      /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                 0xFFC01C28      /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP             0xFFC01C2C      /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT               0xFFC01C30      /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT               0xFFC01C38      /* DMA Channel 8 Current Y Count Register */
+
+#define DMA9_NEXT_DESC_PTR              0xFFC01C40      /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                 0xFFC01C44      /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                             0xFFC01C48      /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                    0xFFC01C50      /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                   0xFFC01C54      /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                    0xFFC01C58      /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                   0xFFC01C5C      /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR              0xFFC01C60      /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                  0xFFC01C64      /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                 0xFFC01C68      /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP             0xFFC01C6C      /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT               0xFFC01C70      /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT               0xFFC01C78      /* DMA Channel 9 Current Y Count Register */
+
+#define DMA10_NEXT_DESC_PTR             0xFFC01C80      /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR                0xFFC01C84      /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                    0xFFC01C88      /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                   0xFFC01C90      /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                  0xFFC01C94      /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                   0xFFC01C98      /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                  0xFFC01C9C      /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR             0xFFC01CA0      /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                 0xFFC01CA4      /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS                0xFFC01CA8      /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP    0xFFC01CAC      /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT              0xFFC01CB0      /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT              0xFFC01CB8      /* DMA Channel 10 Current Y Count Register */
+
+#define DMA11_NEXT_DESC_PTR             0xFFC01CC0      /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR                0xFFC01CC4      /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                    0xFFC01CC8      /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                   0xFFC01CD0      /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                  0xFFC01CD4      /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                   0xFFC01CD8      /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                  0xFFC01CDC      /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR             0xFFC01CE0      /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                 0xFFC01CE4      /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS                0xFFC01CE8      /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP    0xFFC01CEC      /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT              0xFFC01CF0      /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT              0xFFC01CF8      /* DMA Channel 11 Current Y Count Register */
+
+#define DMA12_NEXT_DESC_PTR             0xFFC01D00      /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR                0xFFC01D04      /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                    0xFFC01D08      /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                   0xFFC01D10      /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                  0xFFC01D14      /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                   0xFFC01D18      /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                  0xFFC01D1C      /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR             0xFFC01D20      /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                 0xFFC01D24      /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS                0xFFC01D28      /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP    0xFFC01D2C      /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT              0xFFC01D30      /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT              0xFFC01D38      /* DMA Channel 12 Current Y Count Register */
+
+#define DMA13_NEXT_DESC_PTR             0xFFC01D40      /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR                0xFFC01D44      /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                    0xFFC01D48      /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                   0xFFC01D50      /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                  0xFFC01D54      /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                   0xFFC01D58      /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                  0xFFC01D5C      /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR             0xFFC01D60      /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                 0xFFC01D64      /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS                0xFFC01D68      /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP    0xFFC01D6C      /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT              0xFFC01D70      /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT              0xFFC01D78      /* DMA Channel 13 Current Y Count Register */
+
+#define DMA14_NEXT_DESC_PTR             0xFFC01D80      /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR                0xFFC01D84      /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                    0xFFC01D88      /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                   0xFFC01D90      /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                  0xFFC01D94      /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                   0xFFC01D98      /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                  0xFFC01D9C      /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR             0xFFC01DA0      /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                 0xFFC01DA4      /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS                0xFFC01DA8      /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP    0xFFC01DAC      /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT              0xFFC01DB0      /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT              0xFFC01DB8      /* DMA Channel 14 Current Y Count Register */
+
+#define DMA15_NEXT_DESC_PTR             0xFFC01DC0      /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR                0xFFC01DC4      /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                    0xFFC01DC8      /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                   0xFFC01DD0      /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                  0xFFC01DD4      /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                   0xFFC01DD8      /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                  0xFFC01DDC      /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR             0xFFC01DE0      /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                 0xFFC01DE4      /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS                0xFFC01DE8      /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP    0xFFC01DEC      /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT              0xFFC01DF0      /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT              0xFFC01DF8      /* DMA Channel 15 Current Y Count Register */
+
+#define DMA16_NEXT_DESC_PTR             0xFFC01E00      /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR                0xFFC01E04      /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                    0xFFC01E08      /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                   0xFFC01E10      /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                  0xFFC01E14      /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                   0xFFC01E18      /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                  0xFFC01E1C      /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR             0xFFC01E20      /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                 0xFFC01E24      /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS                0xFFC01E28      /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP    0xFFC01E2C      /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT              0xFFC01E30      /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT              0xFFC01E38      /* DMA Channel 16 Current Y Count Register */
+
+#define DMA17_NEXT_DESC_PTR             0xFFC01E40      /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR                0xFFC01E44      /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                    0xFFC01E48      /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                   0xFFC01E50      /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                  0xFFC01E54      /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                   0xFFC01E58      /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                  0xFFC01E5C      /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR             0xFFC01E60      /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                 0xFFC01E64      /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS                0xFFC01E68      /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP    0xFFC01E6C      /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT              0xFFC01E70      /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT              0xFFC01E78      /* DMA Channel 17 Current Y Count Register */
+
+#define DMA18_NEXT_DESC_PTR             0xFFC01E80      /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR                0xFFC01E84      /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                    0xFFC01E88      /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                   0xFFC01E90      /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                  0xFFC01E94      /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                   0xFFC01E98      /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                  0xFFC01E9C      /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR             0xFFC01EA0      /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                 0xFFC01EA4      /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS                0xFFC01EA8      /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP    0xFFC01EAC      /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT              0xFFC01EB0      /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT              0xFFC01EB8      /* DMA Channel 18 Current Y Count Register */
+
+#define DMA19_NEXT_DESC_PTR             0xFFC01EC0      /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR                0xFFC01EC4      /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                    0xFFC01EC8      /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                   0xFFC01ED0      /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                  0xFFC01ED4      /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                   0xFFC01ED8      /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                  0xFFC01EDC      /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR             0xFFC01EE0      /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                 0xFFC01EE4      /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS                0xFFC01EE8      /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP    0xFFC01EEC      /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT              0xFFC01EF0      /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT              0xFFC01EF8      /* DMA Channel 19 Current Y Count Register */
+
+#define MDMA_D2_NEXT_DESC_PTR   0xFFC01F00      /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR              0xFFC01F04      /* MemDMA1 Stream 0 Destination Start Address Register */
+#define MDMA_D2_CONFIG                  0xFFC01F08      /* MemDMA1 Stream 0 Destination Configuration Register */
+#define MDMA_D2_X_COUNT         0xFFC01F10      /* MemDMA1 Stream 0 Destination X Count Register */
+#define MDMA_D2_X_MODIFY                0xFFC01F14      /* MemDMA1 Stream 0 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT         0xFFC01F18      /* MemDMA1 Stream 0 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY                0xFFC01F1C      /* MemDMA1 Stream 0 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR   0xFFC01F20      /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR               0xFFC01F24      /* MemDMA1 Stream 0 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS              0xFFC01F28      /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP  0xFFC01F2C      /* MemDMA1 Stream 0 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT    0xFFC01F30      /* MemDMA1 Stream 0 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT    0xFFC01F38      /* MemDMA1 Stream 0 Destination Current Y Count Register */
+
+#define MDMA_S2_NEXT_DESC_PTR   0xFFC01F40      /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR              0xFFC01F44      /* MemDMA1 Stream 0 Source Start Address Register */
+#define MDMA_S2_CONFIG                  0xFFC01F48      /* MemDMA1 Stream 0 Source Configuration Register */
+#define MDMA_S2_X_COUNT         0xFFC01F50      /* MemDMA1 Stream 0 Source X Count Register */
+#define MDMA_S2_X_MODIFY                0xFFC01F54      /* MemDMA1 Stream 0 Source X Modify Register */
+#define MDMA_S2_Y_COUNT         0xFFC01F58      /* MemDMA1 Stream 0 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY                0xFFC01F5C      /* MemDMA1 Stream 0 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR   0xFFC01F60      /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR               0xFFC01F64      /* MemDMA1 Stream 0 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS              0xFFC01F68      /* MemDMA1 Stream 0 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP  0xFFC01F6C      /* MemDMA1 Stream 0 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT    0xFFC01F70      /* MemDMA1 Stream 0 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT    0xFFC01F78      /* MemDMA1 Stream 0 Source Current Y Count Register */
+
+#define MDMA_D3_NEXT_DESC_PTR   0xFFC01F80      /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR              0xFFC01F84      /* MemDMA1 Stream 1 Destination Start Address Register */
+#define MDMA_D3_CONFIG                  0xFFC01F88      /* MemDMA1 Stream 1 Destination Configuration Register */
+#define MDMA_D3_X_COUNT         0xFFC01F90      /* MemDMA1 Stream 1 Destination X Count Register */
+#define MDMA_D3_X_MODIFY                0xFFC01F94      /* MemDMA1 Stream 1 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT         0xFFC01F98      /* MemDMA1 Stream 1 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY                0xFFC01F9C      /* MemDMA1 Stream 1 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR   0xFFC01FA0      /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR               0xFFC01FA4      /* MemDMA1 Stream 1 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS              0xFFC01FA8      /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP  0xFFC01FAC      /* MemDMA1 Stream 1 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT    0xFFC01FB0      /* MemDMA1 Stream 1 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT    0xFFC01FB8      /* MemDMA1 Stream 1 Destination Current Y Count Register */
+
+#define MDMA_S3_NEXT_DESC_PTR   0xFFC01FC0      /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR              0xFFC01FC4      /* MemDMA1 Stream 1 Source Start Address Register */
+#define MDMA_S3_CONFIG                  0xFFC01FC8      /* MemDMA1 Stream 1 Source Configuration Register */
+#define MDMA_S3_X_COUNT         0xFFC01FD0      /* MemDMA1 Stream 1 Source X Count Register */
+#define MDMA_S3_X_MODIFY                0xFFC01FD4      /* MemDMA1 Stream 1 Source X Modify Register */
+#define MDMA_S3_Y_COUNT         0xFFC01FD8      /* MemDMA1 Stream 1 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY                0xFFC01FDC      /* MemDMA1 Stream 1 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR   0xFFC01FE0      /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR               0xFFC01FE4      /* MemDMA1 Stream 1 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS              0xFFC01FE8      /* MemDMA1 Stream 1 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP  0xFFC01FEC      /* MemDMA1 Stream 1 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT    0xFFC01FF0      /* MemDMA1 Stream 1 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT    0xFFC01FF8      /* MemDMA1 Stream 1 Source Current Y Count Register */
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)        */
+#define UART1_THR                       0xFFC02000      /* Transmit Holding register */
+#define UART1_RBR                       0xFFC02000      /* Receive Buffer register */
+#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte) */
+#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register */
+#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte) */
+#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register */
+#define UART1_LCR                       0xFFC0200C      /* Line Control Register */
+#define UART1_MCR                       0xFFC02010      /* Modem Control Register */
+#define UART1_LSR                       0xFFC02014      /* Line Status Register */
+#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register */
+#define UART1_GCTL                      0xFFC02024      /* Global Control Register */
+
+
+/* UART2 Controller             (0xFFC02100 - 0xFFC021FF)        */
+#define UART2_THR                       0xFFC02100      /* Transmit Holding register */
+#define UART2_RBR                       0xFFC02100      /* Receive Buffer register */
+#define UART2_DLL                       0xFFC02100      /* Divisor Latch (Low-Byte) */
+#define UART2_IER                       0xFFC02104      /* Interrupt Enable Register */
+#define UART2_DLH                       0xFFC02104      /* Divisor Latch (High-Byte) */
+#define UART2_IIR                       0xFFC02108      /* Interrupt Identification Register */
+#define UART2_LCR                       0xFFC0210C      /* Line Control Register */
+#define UART2_MCR                       0xFFC02110      /* Modem Control Register */
+#define UART2_LSR                       0xFFC02114      /* Line Status Register */
+#define UART2_SCR                       0xFFC0211C      /* SCR Scratch Register */
+#define UART2_GCTL                      0xFFC02124      /* Global Control Register */
+
+
+/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF)                        */
+#define TWI1_CLKDIV                     0xFFC02200      /* Serial Clock Divider Register */
+#define TWI1_CONTROL            0xFFC02204      /* TWI1 Master Internal Time Reference Register */
+#define TWI1_SLAVE_CTL          0xFFC02208      /* Slave Mode Control Register */
+#define TWI1_SLAVE_STAT         0xFFC0220C      /* Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR         0xFFC02210      /* Slave Mode Address Register */
+#define TWI1_MASTER_CTL 0xFFC02214      /* Master Mode Control Register */
+#define TWI1_MASTER_STAT        0xFFC02218      /* Master Mode Status Register */
+#define TWI1_MASTER_ADDR        0xFFC0221C      /* Master Mode Address Register */
+#define TWI1_INT_STAT           0xFFC02220      /* TWI1 Master Interrupt Register */
+#define TWI1_INT_MASK           0xFFC02224      /* TWI1 Master Interrupt Mask Register */
+#define TWI1_FIFO_CTL           0xFFC02228      /* FIFO Control Register */
+#define TWI1_FIFO_STAT          0xFFC0222C      /* FIFO Status Register */
+#define TWI1_XMT_DATA8          0xFFC02280      /* FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16         0xFFC02284      /* FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8          0xFFC02288      /* FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16         0xFFC0228C      /* FIFO Receive Data Double Byte Register */
+#define TWI1_REGBASE            TWI1_CLKDIV
+
+
+/* the following are for backwards compatibility */
+#define TWI1_PRESCALE     TWI1_CONTROL
+#define TWI1_INT_SRC      TWI1_INT_STAT
+#define TWI1_INT_ENABLE   TWI1_INT_MASK
+
+
+/* SPI1 Controller              (0xFFC02300 - 0xFFC023FF)        */
+#define SPI1_CTL                        0xFFC02300  /* SPI1 Control Register */
+#define SPI1_FLG                        0xFFC02304  /* SPI1 Flag register */
+#define SPI1_STAT                       0xFFC02308  /* SPI1 Status register */
+#define SPI1_TDBR                       0xFFC0230C  /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                       0xFFC02310  /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                       0xFFC02314  /* SPI1 Baud rate Register */
+#define SPI1_SHADOW                     0xFFC02318  /* SPI1_RDBR Shadow Register */
+#define SPI1_REGBASE                    SPI1_CTL
+
+/* SPI2 Controller              (0xFFC02400 - 0xFFC024FF)        */
+#define SPI2_CTL                        0xFFC02400  /* SPI2 Control Register */
+#define SPI2_FLG                        0xFFC02404  /* SPI2 Flag register */
+#define SPI2_STAT                       0xFFC02408  /* SPI2 Status register */
+#define SPI2_TDBR                       0xFFC0240C  /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR                       0xFFC02410  /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD                       0xFFC02414  /* SPI2 Baud rate Register */
+#define SPI2_SHADOW                     0xFFC02418  /* SPI2_RDBR Shadow Register */
+#define SPI2_REGBASE                    SPI2_CTL
+
+/* SPORT2 Controller            (0xFFC02500 - 0xFFC025FF)                        */
+#define SPORT2_TCR1                     0xFFC02500      /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                     0xFFC02504      /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV          0xFFC02508      /* SPORT2 Transmit Clock Divider */
+#define SPORT2_TFSDIV           0xFFC0250C      /* SPORT2 Transmit Frame Sync Divider */
+#define SPORT2_TX                       0xFFC02510      /* SPORT2 TX Data Register */
+#define SPORT2_RX                       0xFFC02518      /* SPORT2 RX Data Register */
+#define SPORT2_RCR1                     0xFFC02520      /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_RCR2                     0xFFC02524      /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_RCLKDIV          0xFFC02528      /* SPORT2 Receive Clock Divider */
+#define SPORT2_RFSDIV           0xFFC0252C      /* SPORT2 Receive Frame Sync Divider */
+#define SPORT2_STAT                     0xFFC02530      /* SPORT2 Status Register */
+#define SPORT2_CHNL                     0xFFC02534      /* SPORT2 Current Channel Register */
+#define SPORT2_MCMC1            0xFFC02538      /* SPORT2 Multi-Channel Configuration Register 1 */
+#define SPORT2_MCMC2            0xFFC0253C      /* SPORT2 Multi-Channel Configuration Register 2 */
+#define SPORT2_MTCS0            0xFFC02540      /* SPORT2 Multi-Channel Transmit Select Register 0 */
+#define SPORT2_MTCS1            0xFFC02544      /* SPORT2 Multi-Channel Transmit Select Register 1 */
+#define SPORT2_MTCS2            0xFFC02548      /* SPORT2 Multi-Channel Transmit Select Register 2 */
+#define SPORT2_MTCS3            0xFFC0254C      /* SPORT2 Multi-Channel Transmit Select Register 3 */
+#define SPORT2_MRCS0            0xFFC02550      /* SPORT2 Multi-Channel Receive Select Register 0 */
+#define SPORT2_MRCS1            0xFFC02554      /* SPORT2 Multi-Channel Receive Select Register 1 */
+#define SPORT2_MRCS2            0xFFC02558      /* SPORT2 Multi-Channel Receive Select Register 2 */
+#define SPORT2_MRCS3            0xFFC0255C      /* SPORT2 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT3 Controller            (0xFFC02600 - 0xFFC026FF)                        */
+#define SPORT3_TCR1                     0xFFC02600      /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                     0xFFC02604      /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV          0xFFC02608      /* SPORT3 Transmit Clock Divider */
+#define SPORT3_TFSDIV           0xFFC0260C      /* SPORT3 Transmit Frame Sync Divider */
+#define SPORT3_TX                       0xFFC02610      /* SPORT3 TX Data Register */
+#define SPORT3_RX                       0xFFC02618      /* SPORT3 RX Data Register */
+#define SPORT3_RCR1                     0xFFC02620      /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_RCR2                     0xFFC02624      /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_RCLKDIV          0xFFC02628      /* SPORT3 Receive Clock Divider */
+#define SPORT3_RFSDIV           0xFFC0262C      /* SPORT3 Receive Frame Sync Divider */
+#define SPORT3_STAT                     0xFFC02630      /* SPORT3 Status Register */
+#define SPORT3_CHNL                     0xFFC02634      /* SPORT3 Current Channel Register */
+#define SPORT3_MCMC1            0xFFC02638      /* SPORT3 Multi-Channel Configuration Register 1 */
+#define SPORT3_MCMC2            0xFFC0263C      /* SPORT3 Multi-Channel Configuration Register 2 */
+#define SPORT3_MTCS0            0xFFC02640      /* SPORT3 Multi-Channel Transmit Select Register 0 */
+#define SPORT3_MTCS1            0xFFC02644      /* SPORT3 Multi-Channel Transmit Select Register 1 */
+#define SPORT3_MTCS2            0xFFC02648      /* SPORT3 Multi-Channel Transmit Select Register 2 */
+#define SPORT3_MTCS3            0xFFC0264C      /* SPORT3 Multi-Channel Transmit Select Register 3 */
+#define SPORT3_MRCS0            0xFFC02650      /* SPORT3 Multi-Channel Receive Select Register 0 */
+#define SPORT3_MRCS1            0xFFC02654      /* SPORT3 Multi-Channel Receive Select Register 1 */
+#define SPORT3_MRCS2            0xFFC02658      /* SPORT3 Multi-Channel Receive Select Register 2 */
+#define SPORT3_MRCS3            0xFFC0265C      /* SPORT3 Multi-Channel Receive Select Register 3 */
+
+
+/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                */
+/* For Mailboxes 0-15                                                                                    */
+#define CAN_MC1                         0xFFC02A00      /* Mailbox config reg 1  */
+#define CAN_MD1                         0xFFC02A04      /* Mailbox direction reg 1 */
+#define CAN_TRS1                        0xFFC02A08      /* Transmit Request Set reg 1 */
+#define CAN_TRR1                        0xFFC02A0C      /* Transmit Request Reset reg 1 */
+#define CAN_TA1                         0xFFC02A10      /* Transmit Acknowledge reg 1 */
+#define CAN_AA1                         0xFFC02A14      /* Transmit Abort Acknowledge reg 1 */
+#define CAN_RMP1                        0xFFC02A18      /* Receive Message Pending reg 1 */
+#define CAN_RML1                        0xFFC02A1C      /* Receive Message Lost reg 1 */
+#define CAN_MBTIF1                      0xFFC02A20      /* Mailbox Transmit Interrupt Flag reg 1 */
+#define CAN_MBRIF1                      0xFFC02A24      /* Mailbox Receive  Interrupt Flag reg 1 */
+#define CAN_MBIM1                       0xFFC02A28      /* Mailbox Interrupt Mask reg 1 */
+#define CAN_RFH1                        0xFFC02A2C      /* Remote Frame Handling reg 1 */
+#define CAN_OPSS1                       0xFFC02A30      /* Overwrite Protection Single Shot Xmission reg 1 */
+
+/* For Mailboxes 16-31                                                                                   */
+#define CAN_MC2                         0xFFC02A40      /* Mailbox config reg 2  */
+#define CAN_MD2                         0xFFC02A44      /* Mailbox direction reg 2 */
+#define CAN_TRS2                        0xFFC02A48      /* Transmit Request Set reg 2 */
+#define CAN_TRR2                        0xFFC02A4C      /* Transmit Request Reset reg 2 */
+#define CAN_TA2                         0xFFC02A50      /* Transmit Acknowledge reg 2 */
+#define CAN_AA2                         0xFFC02A54      /* Transmit Abort Acknowledge reg 2 */
+#define CAN_RMP2                        0xFFC02A58      /* Receive Message Pending reg 2 */
+#define CAN_RML2                        0xFFC02A5C      /* Receive Message Lost reg 2 */
+#define CAN_MBTIF2                      0xFFC02A60      /* Mailbox Transmit Interrupt Flag reg 2 */
+#define CAN_MBRIF2                      0xFFC02A64      /* Mailbox Receive  Interrupt Flag reg 2 */
+#define CAN_MBIM2                       0xFFC02A68      /* Mailbox Interrupt Mask reg 2 */
+#define CAN_RFH2                        0xFFC02A6C      /* Remote Frame Handling reg 2 */
+#define CAN_OPSS2                       0xFFC02A70      /* Overwrite Protection Single Shot Xmission reg 2 */
+
+#define CAN_CLOCK                       0xFFC02A80      /* Bit Timing Configuration register 0 */
+#define CAN_TIMING                      0xFFC02A84      /* Bit Timing Configuration register 1 */
+
+#define CAN_DEBUG                       0xFFC02A88      /* Debug Register                */
+/* the following is for backwards compatibility */
+#define CAN_CNF          CAN_DEBUG
+
+#define CAN_STATUS                      0xFFC02A8C      /* Global Status Register */
+#define CAN_CEC                         0xFFC02A90      /* Error Counter Register */
+#define CAN_GIS                         0xFFC02A94      /* Global Interrupt Status Register */
+#define CAN_GIM                         0xFFC02A98      /* Global Interrupt Mask Register */
+#define CAN_GIF                         0xFFC02A9C      /* Global Interrupt Flag Register */
+#define CAN_CONTROL                     0xFFC02AA0      /* Master Control Register */
+#define CAN_INTR                        0xFFC02AA4      /* Interrupt Pending Register */
+#define CAN_MBTD                        0xFFC02AAC      /* Mailbox Temporary Disable Feature */
+#define CAN_EWR                         0xFFC02AB0      /* Programmable Warning Level */
+#define CAN_ESR                         0xFFC02AB4      /* Error Status Register */
+#define CAN_UCCNT                       0xFFC02AC4      /* Universal Counter     */
+#define CAN_UCRC                        0xFFC02AC8      /* Universal Counter Reload/Capture Register */
+#define CAN_UCCNF                       0xFFC02ACC      /* Universal Counter Configuration Register */
+
+/* Mailbox Acceptance Masks                                      */
+#define CAN_AM00L                       0xFFC02B00      /* Mailbox 0 Low Acceptance Mask */
+#define CAN_AM00H                       0xFFC02B04      /* Mailbox 0 High Acceptance Mask */
+#define CAN_AM01L                       0xFFC02B08      /* Mailbox 1 Low Acceptance Mask */
+#define CAN_AM01H                       0xFFC02B0C      /* Mailbox 1 High Acceptance Mask */
+#define CAN_AM02L                       0xFFC02B10      /* Mailbox 2 Low Acceptance Mask */
+#define CAN_AM02H                       0xFFC02B14      /* Mailbox 2 High Acceptance Mask */
+#define CAN_AM03L                       0xFFC02B18      /* Mailbox 3 Low Acceptance Mask */
+#define CAN_AM03H                       0xFFC02B1C      /* Mailbox 3 High Acceptance Mask */
+#define CAN_AM04L                       0xFFC02B20      /* Mailbox 4 Low Acceptance Mask */
+#define CAN_AM04H                       0xFFC02B24      /* Mailbox 4 High Acceptance Mask */
+#define CAN_AM05L                       0xFFC02B28      /* Mailbox 5 Low Acceptance Mask */
+#define CAN_AM05H                       0xFFC02B2C      /* Mailbox 5 High Acceptance Mask */
+#define CAN_AM06L                       0xFFC02B30      /* Mailbox 6 Low Acceptance Mask */
+#define CAN_AM06H                       0xFFC02B34      /* Mailbox 6 High Acceptance Mask */
+#define CAN_AM07L                       0xFFC02B38      /* Mailbox 7 Low Acceptance Mask */
+#define CAN_AM07H                       0xFFC02B3C      /* Mailbox 7 High Acceptance Mask */
+#define CAN_AM08L                       0xFFC02B40      /* Mailbox 8 Low Acceptance Mask */
+#define CAN_AM08H                       0xFFC02B44      /* Mailbox 8 High Acceptance Mask */
+#define CAN_AM09L                       0xFFC02B48      /* Mailbox 9 Low Acceptance Mask */
+#define CAN_AM09H                       0xFFC02B4C      /* Mailbox 9 High Acceptance Mask */
+#define CAN_AM10L                       0xFFC02B50      /* Mailbox 10 Low Acceptance Mask */
+#define CAN_AM10H                       0xFFC02B54      /* Mailbox 10 High Acceptance Mask */
+#define CAN_AM11L                       0xFFC02B58      /* Mailbox 11 Low Acceptance Mask */
+#define CAN_AM11H                       0xFFC02B5C      /* Mailbox 11 High Acceptance Mask */
+#define CAN_AM12L                       0xFFC02B60      /* Mailbox 12 Low Acceptance Mask */
+#define CAN_AM12H                       0xFFC02B64      /* Mailbox 12 High Acceptance Mask */
+#define CAN_AM13L                       0xFFC02B68      /* Mailbox 13 Low Acceptance Mask */
+#define CAN_AM13H                       0xFFC02B6C      /* Mailbox 13 High Acceptance Mask */
+#define CAN_AM14L                       0xFFC02B70      /* Mailbox 14 Low Acceptance Mask */
+#define CAN_AM14H                       0xFFC02B74      /* Mailbox 14 High Acceptance Mask */
+#define CAN_AM15L                       0xFFC02B78      /* Mailbox 15 Low Acceptance Mask */
+#define CAN_AM15H                       0xFFC02B7C      /* Mailbox 15 High Acceptance Mask */
+
+#define CAN_AM16L                       0xFFC02B80      /* Mailbox 16 Low Acceptance Mask */
+#define CAN_AM16H                       0xFFC02B84      /* Mailbox 16 High Acceptance Mask */
+#define CAN_AM17L                       0xFFC02B88      /* Mailbox 17 Low Acceptance Mask */
+#define CAN_AM17H                       0xFFC02B8C      /* Mailbox 17 High Acceptance Mask */
+#define CAN_AM18L                       0xFFC02B90      /* Mailbox 18 Low Acceptance Mask */
+#define CAN_AM18H                       0xFFC02B94      /* Mailbox 18 High Acceptance Mask */
+#define CAN_AM19L                       0xFFC02B98      /* Mailbox 19 Low Acceptance Mask */
+#define CAN_AM19H                       0xFFC02B9C      /* Mailbox 19 High Acceptance Mask */
+#define CAN_AM20L                       0xFFC02BA0      /* Mailbox 20 Low Acceptance Mask */
+#define CAN_AM20H                       0xFFC02BA4      /* Mailbox 20 High Acceptance Mask */
+#define CAN_AM21L                       0xFFC02BA8      /* Mailbox 21 Low Acceptance Mask */
+#define CAN_AM21H                       0xFFC02BAC      /* Mailbox 21 High Acceptance Mask */
+#define CAN_AM22L                       0xFFC02BB0      /* Mailbox 22 Low Acceptance Mask */
+#define CAN_AM22H                       0xFFC02BB4      /* Mailbox 22 High Acceptance Mask */
+#define CAN_AM23L                       0xFFC02BB8      /* Mailbox 23 Low Acceptance Mask */
+#define CAN_AM23H                       0xFFC02BBC      /* Mailbox 23 High Acceptance Mask */
+#define CAN_AM24L                       0xFFC02BC0      /* Mailbox 24 Low Acceptance Mask */
+#define CAN_AM24H                       0xFFC02BC4      /* Mailbox 24 High Acceptance Mask */
+#define CAN_AM25L                       0xFFC02BC8      /* Mailbox 25 Low Acceptance Mask */
+#define CAN_AM25H                       0xFFC02BCC      /* Mailbox 25 High Acceptance Mask */
+#define CAN_AM26L                       0xFFC02BD0      /* Mailbox 26 Low Acceptance Mask */
+#define CAN_AM26H                       0xFFC02BD4      /* Mailbox 26 High Acceptance Mask */
+#define CAN_AM27L                       0xFFC02BD8      /* Mailbox 27 Low Acceptance Mask */
+#define CAN_AM27H                       0xFFC02BDC      /* Mailbox 27 High Acceptance Mask */
+#define CAN_AM28L                       0xFFC02BE0      /* Mailbox 28 Low Acceptance Mask */
+#define CAN_AM28H                       0xFFC02BE4      /* Mailbox 28 High Acceptance Mask */
+#define CAN_AM29L                       0xFFC02BE8      /* Mailbox 29 Low Acceptance Mask */
+#define CAN_AM29H                       0xFFC02BEC      /* Mailbox 29 High Acceptance Mask */
+#define CAN_AM30L                       0xFFC02BF0      /* Mailbox 30 Low Acceptance Mask */
+#define CAN_AM30H                       0xFFC02BF4      /* Mailbox 30 High Acceptance Mask */
+#define CAN_AM31L                       0xFFC02BF8      /* Mailbox 31 Low Acceptance Mask */
+#define CAN_AM31H                       0xFFC02BFC      /* Mailbox 31 High Acceptance Mask */
+
+/* CAN Acceptance Mask Macros */
+#define CAN_AM_L(x)                     (CAN_AM00L+((x)*0x8))
+#define CAN_AM_H(x)                     (CAN_AM00H+((x)*0x8))
+
+/* Mailbox Registers                                                                     */
+#define CAN_MB00_DATA0          0xFFC02C00      /* Mailbox 0 Data Word 0 [15:0] Register */
+#define CAN_MB00_DATA1          0xFFC02C04      /* Mailbox 0 Data Word 1 [31:16] Register */
+#define CAN_MB00_DATA2          0xFFC02C08      /* Mailbox 0 Data Word 2 [47:32] Register */
+#define CAN_MB00_DATA3          0xFFC02C0C      /* Mailbox 0 Data Word 3 [63:48] Register */
+#define CAN_MB00_LENGTH         0xFFC02C10      /* Mailbox 0 Data Length Code Register */
+#define CAN_MB00_TIMESTAMP      0xFFC02C14      /* Mailbox 0 Time Stamp Value Register */
+#define CAN_MB00_ID0            0xFFC02C18      /* Mailbox 0 Identifier Low Register */
+#define CAN_MB00_ID1            0xFFC02C1C      /* Mailbox 0 Identifier High Register */
+
+#define CAN_MB01_DATA0          0xFFC02C20      /* Mailbox 1 Data Word 0 [15:0] Register */
+#define CAN_MB01_DATA1          0xFFC02C24      /* Mailbox 1 Data Word 1 [31:16] Register */
+#define CAN_MB01_DATA2          0xFFC02C28      /* Mailbox 1 Data Word 2 [47:32] Register */
+#define CAN_MB01_DATA3          0xFFC02C2C      /* Mailbox 1 Data Word 3 [63:48] Register */
+#define CAN_MB01_LENGTH         0xFFC02C30      /* Mailbox 1 Data Length Code Register */
+#define CAN_MB01_TIMESTAMP      0xFFC02C34      /* Mailbox 1 Time Stamp Value Register */
+#define CAN_MB01_ID0            0xFFC02C38      /* Mailbox 1 Identifier Low Register */
+#define CAN_MB01_ID1            0xFFC02C3C      /* Mailbox 1 Identifier High Register */
+
+#define CAN_MB02_DATA0          0xFFC02C40      /* Mailbox 2 Data Word 0 [15:0] Register */
+#define CAN_MB02_DATA1          0xFFC02C44      /* Mailbox 2 Data Word 1 [31:16] Register */
+#define CAN_MB02_DATA2          0xFFC02C48      /* Mailbox 2 Data Word 2 [47:32] Register */
+#define CAN_MB02_DATA3          0xFFC02C4C      /* Mailbox 2 Data Word 3 [63:48] Register */
+#define CAN_MB02_LENGTH         0xFFC02C50      /* Mailbox 2 Data Length Code Register */
+#define CAN_MB02_TIMESTAMP      0xFFC02C54      /* Mailbox 2 Time Stamp Value Register */
+#define CAN_MB02_ID0            0xFFC02C58      /* Mailbox 2 Identifier Low Register */
+#define CAN_MB02_ID1            0xFFC02C5C      /* Mailbox 2 Identifier High Register */
+
+#define CAN_MB03_DATA0          0xFFC02C60      /* Mailbox 3 Data Word 0 [15:0] Register */
+#define CAN_MB03_DATA1          0xFFC02C64      /* Mailbox 3 Data Word 1 [31:16] Register */
+#define CAN_MB03_DATA2          0xFFC02C68      /* Mailbox 3 Data Word 2 [47:32] Register */
+#define CAN_MB03_DATA3          0xFFC02C6C      /* Mailbox 3 Data Word 3 [63:48] Register */
+#define CAN_MB03_LENGTH         0xFFC02C70      /* Mailbox 3 Data Length Code Register */
+#define CAN_MB03_TIMESTAMP      0xFFC02C74      /* Mailbox 3 Time Stamp Value Register */
+#define CAN_MB03_ID0            0xFFC02C78      /* Mailbox 3 Identifier Low Register */
+#define CAN_MB03_ID1            0xFFC02C7C      /* Mailbox 3 Identifier High Register */
+
+#define CAN_MB04_DATA0          0xFFC02C80      /* Mailbox 4 Data Word 0 [15:0] Register */
+#define CAN_MB04_DATA1          0xFFC02C84      /* Mailbox 4 Data Word 1 [31:16] Register */
+#define CAN_MB04_DATA2          0xFFC02C88      /* Mailbox 4 Data Word 2 [47:32] Register */
+#define CAN_MB04_DATA3          0xFFC02C8C      /* Mailbox 4 Data Word 3 [63:48] Register */
+#define CAN_MB04_LENGTH         0xFFC02C90      /* Mailbox 4 Data Length Code Register */
+#define CAN_MB04_TIMESTAMP      0xFFC02C94      /* Mailbox 4 Time Stamp Value Register */
+#define CAN_MB04_ID0            0xFFC02C98      /* Mailbox 4 Identifier Low Register */
+#define CAN_MB04_ID1            0xFFC02C9C      /* Mailbox 4 Identifier High Register */
+
+#define CAN_MB05_DATA0          0xFFC02CA0      /* Mailbox 5 Data Word 0 [15:0] Register */
+#define CAN_MB05_DATA1          0xFFC02CA4      /* Mailbox 5 Data Word 1 [31:16] Register */
+#define CAN_MB05_DATA2          0xFFC02CA8      /* Mailbox 5 Data Word 2 [47:32] Register */
+#define CAN_MB05_DATA3          0xFFC02CAC      /* Mailbox 5 Data Word 3 [63:48] Register */
+#define CAN_MB05_LENGTH         0xFFC02CB0      /* Mailbox 5 Data Length Code Register */
+#define CAN_MB05_TIMESTAMP      0xFFC02CB4      /* Mailbox 5 Time Stamp Value Register */
+#define CAN_MB05_ID0            0xFFC02CB8      /* Mailbox 5 Identifier Low Register */
+#define CAN_MB05_ID1            0xFFC02CBC      /* Mailbox 5 Identifier High Register */
+
+#define CAN_MB06_DATA0          0xFFC02CC0      /* Mailbox 6 Data Word 0 [15:0] Register */
+#define CAN_MB06_DATA1          0xFFC02CC4      /* Mailbox 6 Data Word 1 [31:16] Register */
+#define CAN_MB06_DATA2          0xFFC02CC8      /* Mailbox 6 Data Word 2 [47:32] Register */
+#define CAN_MB06_DATA3          0xFFC02CCC      /* Mailbox 6 Data Word 3 [63:48] Register */
+#define CAN_MB06_LENGTH         0xFFC02CD0      /* Mailbox 6 Data Length Code Register */
+#define CAN_MB06_TIMESTAMP      0xFFC02CD4      /* Mailbox 6 Time Stamp Value Register */
+#define CAN_MB06_ID0            0xFFC02CD8      /* Mailbox 6 Identifier Low Register */
+#define CAN_MB06_ID1            0xFFC02CDC      /* Mailbox 6 Identifier High Register */
+
+#define CAN_MB07_DATA0          0xFFC02CE0      /* Mailbox 7 Data Word 0 [15:0] Register */
+#define CAN_MB07_DATA1          0xFFC02CE4      /* Mailbox 7 Data Word 1 [31:16] Register */
+#define CAN_MB07_DATA2          0xFFC02CE8      /* Mailbox 7 Data Word 2 [47:32] Register */
+#define CAN_MB07_DATA3          0xFFC02CEC      /* Mailbox 7 Data Word 3 [63:48] Register */
+#define CAN_MB07_LENGTH         0xFFC02CF0      /* Mailbox 7 Data Length Code Register */
+#define CAN_MB07_TIMESTAMP      0xFFC02CF4      /* Mailbox 7 Time Stamp Value Register */
+#define CAN_MB07_ID0            0xFFC02CF8      /* Mailbox 7 Identifier Low Register */
+#define CAN_MB07_ID1            0xFFC02CFC      /* Mailbox 7 Identifier High Register */
+
+#define CAN_MB08_DATA0          0xFFC02D00      /* Mailbox 8 Data Word 0 [15:0] Register */
+#define CAN_MB08_DATA1          0xFFC02D04      /* Mailbox 8 Data Word 1 [31:16] Register */
+#define CAN_MB08_DATA2          0xFFC02D08      /* Mailbox 8 Data Word 2 [47:32] Register */
+#define CAN_MB08_DATA3          0xFFC02D0C      /* Mailbox 8 Data Word 3 [63:48] Register */
+#define CAN_MB08_LENGTH         0xFFC02D10      /* Mailbox 8 Data Length Code Register */
+#define CAN_MB08_TIMESTAMP      0xFFC02D14      /* Mailbox 8 Time Stamp Value Register */
+#define CAN_MB08_ID0            0xFFC02D18      /* Mailbox 8 Identifier Low Register */
+#define CAN_MB08_ID1            0xFFC02D1C      /* Mailbox 8 Identifier High Register */
+
+#define CAN_MB09_DATA0          0xFFC02D20      /* Mailbox 9 Data Word 0 [15:0] Register */
+#define CAN_MB09_DATA1          0xFFC02D24      /* Mailbox 9 Data Word 1 [31:16] Register */
+#define CAN_MB09_DATA2          0xFFC02D28      /* Mailbox 9 Data Word 2 [47:32] Register */
+#define CAN_MB09_DATA3          0xFFC02D2C      /* Mailbox 9 Data Word 3 [63:48] Register */
+#define CAN_MB09_LENGTH         0xFFC02D30      /* Mailbox 9 Data Length Code Register */
+#define CAN_MB09_TIMESTAMP      0xFFC02D34      /* Mailbox 9 Time Stamp Value Register */
+#define CAN_MB09_ID0            0xFFC02D38      /* Mailbox 9 Identifier Low Register */
+#define CAN_MB09_ID1            0xFFC02D3C      /* Mailbox 9 Identifier High Register */
+
+#define CAN_MB10_DATA0          0xFFC02D40      /* Mailbox 10 Data Word 0 [15:0] Register */
+#define CAN_MB10_DATA1          0xFFC02D44      /* Mailbox 10 Data Word 1 [31:16] Register */
+#define CAN_MB10_DATA2          0xFFC02D48      /* Mailbox 10 Data Word 2 [47:32] Register */
+#define CAN_MB10_DATA3          0xFFC02D4C      /* Mailbox 10 Data Word 3 [63:48] Register */
+#define CAN_MB10_LENGTH         0xFFC02D50      /* Mailbox 10 Data Length Code Register */
+#define CAN_MB10_TIMESTAMP      0xFFC02D54      /* Mailbox 10 Time Stamp Value Register */
+#define CAN_MB10_ID0            0xFFC02D58      /* Mailbox 10 Identifier Low Register */
+#define CAN_MB10_ID1            0xFFC02D5C      /* Mailbox 10 Identifier High Register */
+
+#define CAN_MB11_DATA0          0xFFC02D60      /* Mailbox 11 Data Word 0 [15:0] Register */
+#define CAN_MB11_DATA1          0xFFC02D64      /* Mailbox 11 Data Word 1 [31:16] Register */
+#define CAN_MB11_DATA2          0xFFC02D68      /* Mailbox 11 Data Word 2 [47:32] Register */
+#define CAN_MB11_DATA3          0xFFC02D6C      /* Mailbox 11 Data Word 3 [63:48] Register */
+#define CAN_MB11_LENGTH         0xFFC02D70      /* Mailbox 11 Data Length Code Register */
+#define CAN_MB11_TIMESTAMP      0xFFC02D74      /* Mailbox 11 Time Stamp Value Register */
+#define CAN_MB11_ID0            0xFFC02D78      /* Mailbox 11 Identifier Low Register */
+#define CAN_MB11_ID1            0xFFC02D7C      /* Mailbox 11 Identifier High Register */
+
+#define CAN_MB12_DATA0          0xFFC02D80      /* Mailbox 12 Data Word 0 [15:0] Register */
+#define CAN_MB12_DATA1          0xFFC02D84      /* Mailbox 12 Data Word 1 [31:16] Register */
+#define CAN_MB12_DATA2          0xFFC02D88      /* Mailbox 12 Data Word 2 [47:32] Register */
+#define CAN_MB12_DATA3          0xFFC02D8C      /* Mailbox 12 Data Word 3 [63:48] Register */
+#define CAN_MB12_LENGTH         0xFFC02D90      /* Mailbox 12 Data Length Code Register */
+#define CAN_MB12_TIMESTAMP      0xFFC02D94      /* Mailbox 12 Time Stamp Value Register */
+#define CAN_MB12_ID0            0xFFC02D98      /* Mailbox 12 Identifier Low Register */
+#define CAN_MB12_ID1            0xFFC02D9C      /* Mailbox 12 Identifier High Register */
+
+#define CAN_MB13_DATA0          0xFFC02DA0      /* Mailbox 13 Data Word 0 [15:0] Register */
+#define CAN_MB13_DATA1          0xFFC02DA4      /* Mailbox 13 Data Word 1 [31:16] Register */
+#define CAN_MB13_DATA2          0xFFC02DA8      /* Mailbox 13 Data Word 2 [47:32] Register */
+#define CAN_MB13_DATA3          0xFFC02DAC      /* Mailbox 13 Data Word 3 [63:48] Register */
+#define CAN_MB13_LENGTH         0xFFC02DB0      /* Mailbox 13 Data Length Code Register */
+#define CAN_MB13_TIMESTAMP      0xFFC02DB4      /* Mailbox 13 Time Stamp Value Register */
+#define CAN_MB13_ID0            0xFFC02DB8      /* Mailbox 13 Identifier Low Register */
+#define CAN_MB13_ID1            0xFFC02DBC      /* Mailbox 13 Identifier High Register */
+
+#define CAN_MB14_DATA0          0xFFC02DC0      /* Mailbox 14 Data Word 0 [15:0] Register */
+#define CAN_MB14_DATA1          0xFFC02DC4      /* Mailbox 14 Data Word 1 [31:16] Register */
+#define CAN_MB14_DATA2          0xFFC02DC8      /* Mailbox 14 Data Word 2 [47:32] Register */
+#define CAN_MB14_DATA3          0xFFC02DCC      /* Mailbox 14 Data Word 3 [63:48] Register */
+#define CAN_MB14_LENGTH         0xFFC02DD0      /* Mailbox 14 Data Length Code Register */
+#define CAN_MB14_TIMESTAMP      0xFFC02DD4      /* Mailbox 14 Time Stamp Value Register */
+#define CAN_MB14_ID0            0xFFC02DD8      /* Mailbox 14 Identifier Low Register */
+#define CAN_MB14_ID1            0xFFC02DDC      /* Mailbox 14 Identifier High Register */
+
+#define CAN_MB15_DATA0          0xFFC02DE0      /* Mailbox 15 Data Word 0 [15:0] Register */
+#define CAN_MB15_DATA1          0xFFC02DE4      /* Mailbox 15 Data Word 1 [31:16] Register */
+#define CAN_MB15_DATA2          0xFFC02DE8      /* Mailbox 15 Data Word 2 [47:32] Register */
+#define CAN_MB15_DATA3          0xFFC02DEC      /* Mailbox 15 Data Word 3 [63:48] Register */
+#define CAN_MB15_LENGTH         0xFFC02DF0      /* Mailbox 15 Data Length Code Register */
+#define CAN_MB15_TIMESTAMP      0xFFC02DF4      /* Mailbox 15 Time Stamp Value Register */
+#define CAN_MB15_ID0            0xFFC02DF8      /* Mailbox 15 Identifier Low Register */
+#define CAN_MB15_ID1            0xFFC02DFC      /* Mailbox 15 Identifier High Register */
+
+#define CAN_MB16_DATA0          0xFFC02E00      /* Mailbox 16 Data Word 0 [15:0] Register */
+#define CAN_MB16_DATA1          0xFFC02E04      /* Mailbox 16 Data Word 1 [31:16] Register */
+#define CAN_MB16_DATA2          0xFFC02E08      /* Mailbox 16 Data Word 2 [47:32] Register */
+#define CAN_MB16_DATA3          0xFFC02E0C      /* Mailbox 16 Data Word 3 [63:48] Register */
+#define CAN_MB16_LENGTH         0xFFC02E10      /* Mailbox 16 Data Length Code Register */
+#define CAN_MB16_TIMESTAMP      0xFFC02E14      /* Mailbox 16 Time Stamp Value Register */
+#define CAN_MB16_ID0            0xFFC02E18      /* Mailbox 16 Identifier Low Register */
+#define CAN_MB16_ID1            0xFFC02E1C      /* Mailbox 16 Identifier High Register */
+
+#define CAN_MB17_DATA0          0xFFC02E20      /* Mailbox 17 Data Word 0 [15:0] Register */
+#define CAN_MB17_DATA1          0xFFC02E24      /* Mailbox 17 Data Word 1 [31:16] Register */
+#define CAN_MB17_DATA2          0xFFC02E28      /* Mailbox 17 Data Word 2 [47:32] Register */
+#define CAN_MB17_DATA3          0xFFC02E2C      /* Mailbox 17 Data Word 3 [63:48] Register */
+#define CAN_MB17_LENGTH         0xFFC02E30      /* Mailbox 17 Data Length Code Register */
+#define CAN_MB17_TIMESTAMP      0xFFC02E34      /* Mailbox 17 Time Stamp Value Register */
+#define CAN_MB17_ID0            0xFFC02E38      /* Mailbox 17 Identifier Low Register */
+#define CAN_MB17_ID1            0xFFC02E3C      /* Mailbox 17 Identifier High Register */
+
+#define CAN_MB18_DATA0          0xFFC02E40      /* Mailbox 18 Data Word 0 [15:0] Register */
+#define CAN_MB18_DATA1          0xFFC02E44      /* Mailbox 18 Data Word 1 [31:16] Register */
+#define CAN_MB18_DATA2          0xFFC02E48      /* Mailbox 18 Data Word 2 [47:32] Register */
+#define CAN_MB18_DATA3          0xFFC02E4C      /* Mailbox 18 Data Word 3 [63:48] Register */
+#define CAN_MB18_LENGTH         0xFFC02E50      /* Mailbox 18 Data Length Code Register */
+#define CAN_MB18_TIMESTAMP      0xFFC02E54      /* Mailbox 18 Time Stamp Value Register */
+#define CAN_MB18_ID0            0xFFC02E58      /* Mailbox 18 Identifier Low Register */
+#define CAN_MB18_ID1            0xFFC02E5C      /* Mailbox 18 Identifier High Register */
+
+#define CAN_MB19_DATA0          0xFFC02E60      /* Mailbox 19 Data Word 0 [15:0] Register */
+#define CAN_MB19_DATA1          0xFFC02E64      /* Mailbox 19 Data Word 1 [31:16] Register */
+#define CAN_MB19_DATA2          0xFFC02E68      /* Mailbox 19 Data Word 2 [47:32] Register */
+#define CAN_MB19_DATA3          0xFFC02E6C      /* Mailbox 19 Data Word 3 [63:48] Register */
+#define CAN_MB19_LENGTH         0xFFC02E70      /* Mailbox 19 Data Length Code Register */
+#define CAN_MB19_TIMESTAMP      0xFFC02E74      /* Mailbox 19 Time Stamp Value Register */
+#define CAN_MB19_ID0            0xFFC02E78      /* Mailbox 19 Identifier Low Register */
+#define CAN_MB19_ID1            0xFFC02E7C      /* Mailbox 19 Identifier High Register */
+
+#define CAN_MB20_DATA0          0xFFC02E80      /* Mailbox 20 Data Word 0 [15:0] Register */
+#define CAN_MB20_DATA1          0xFFC02E84      /* Mailbox 20 Data Word 1 [31:16] Register */
+#define CAN_MB20_DATA2          0xFFC02E88      /* Mailbox 20 Data Word 2 [47:32] Register */
+#define CAN_MB20_DATA3          0xFFC02E8C      /* Mailbox 20 Data Word 3 [63:48] Register */
+#define CAN_MB20_LENGTH         0xFFC02E90      /* Mailbox 20 Data Length Code Register */
+#define CAN_MB20_TIMESTAMP      0xFFC02E94      /* Mailbox 20 Time Stamp Value Register */
+#define CAN_MB20_ID0            0xFFC02E98      /* Mailbox 20 Identifier Low Register */
+#define CAN_MB20_ID1            0xFFC02E9C      /* Mailbox 20 Identifier High Register */
+
+#define CAN_MB21_DATA0          0xFFC02EA0      /* Mailbox 21 Data Word 0 [15:0] Register */
+#define CAN_MB21_DATA1          0xFFC02EA4      /* Mailbox 21 Data Word 1 [31:16] Register */
+#define CAN_MB21_DATA2          0xFFC02EA8      /* Mailbox 21 Data Word 2 [47:32] Register */
+#define CAN_MB21_DATA3          0xFFC02EAC      /* Mailbox 21 Data Word 3 [63:48] Register */
+#define CAN_MB21_LENGTH         0xFFC02EB0      /* Mailbox 21 Data Length Code Register */
+#define CAN_MB21_TIMESTAMP      0xFFC02EB4      /* Mailbox 21 Time Stamp Value Register */
+#define CAN_MB21_ID0            0xFFC02EB8      /* Mailbox 21 Identifier Low Register */
+#define CAN_MB21_ID1            0xFFC02EBC      /* Mailbox 21 Identifier High Register */
+
+#define CAN_MB22_DATA0          0xFFC02EC0      /* Mailbox 22 Data Word 0 [15:0] Register */
+#define CAN_MB22_DATA1          0xFFC02EC4      /* Mailbox 22 Data Word 1 [31:16] Register */
+#define CAN_MB22_DATA2          0xFFC02EC8      /* Mailbox 22 Data Word 2 [47:32] Register */
+#define CAN_MB22_DATA3          0xFFC02ECC      /* Mailbox 22 Data Word 3 [63:48] Register */
+#define CAN_MB22_LENGTH         0xFFC02ED0      /* Mailbox 22 Data Length Code Register */
+#define CAN_MB22_TIMESTAMP      0xFFC02ED4      /* Mailbox 22 Time Stamp Value Register */
+#define CAN_MB22_ID0            0xFFC02ED8      /* Mailbox 22 Identifier Low Register */
+#define CAN_MB22_ID1            0xFFC02EDC      /* Mailbox 22 Identifier High Register */
+
+#define CAN_MB23_DATA0          0xFFC02EE0      /* Mailbox 23 Data Word 0 [15:0] Register */
+#define CAN_MB23_DATA1          0xFFC02EE4      /* Mailbox 23 Data Word 1 [31:16] Register */
+#define CAN_MB23_DATA2          0xFFC02EE8      /* Mailbox 23 Data Word 2 [47:32] Register */
+#define CAN_MB23_DATA3          0xFFC02EEC      /* Mailbox 23 Data Word 3 [63:48] Register */
+#define CAN_MB23_LENGTH         0xFFC02EF0      /* Mailbox 23 Data Length Code Register */
+#define CAN_MB23_TIMESTAMP      0xFFC02EF4      /* Mailbox 23 Time Stamp Value Register */
+#define CAN_MB23_ID0            0xFFC02EF8      /* Mailbox 23 Identifier Low Register */
+#define CAN_MB23_ID1            0xFFC02EFC      /* Mailbox 23 Identifier High Register */
+
+#define CAN_MB24_DATA0          0xFFC02F00      /* Mailbox 24 Data Word 0 [15:0] Register */
+#define CAN_MB24_DATA1          0xFFC02F04      /* Mailbox 24 Data Word 1 [31:16] Register */
+#define CAN_MB24_DATA2          0xFFC02F08      /* Mailbox 24 Data Word 2 [47:32] Register */
+#define CAN_MB24_DATA3          0xFFC02F0C      /* Mailbox 24 Data Word 3 [63:48] Register */
+#define CAN_MB24_LENGTH         0xFFC02F10      /* Mailbox 24 Data Length Code Register */
+#define CAN_MB24_TIMESTAMP      0xFFC02F14      /* Mailbox 24 Time Stamp Value Register */
+#define CAN_MB24_ID0            0xFFC02F18      /* Mailbox 24 Identifier Low Register */
+#define CAN_MB24_ID1            0xFFC02F1C      /* Mailbox 24 Identifier High Register */
+
+#define CAN_MB25_DATA0          0xFFC02F20      /* Mailbox 25 Data Word 0 [15:0] Register */
+#define CAN_MB25_DATA1          0xFFC02F24      /* Mailbox 25 Data Word 1 [31:16] Register */
+#define CAN_MB25_DATA2          0xFFC02F28      /* Mailbox 25 Data Word 2 [47:32] Register */
+#define CAN_MB25_DATA3          0xFFC02F2C      /* Mailbox 25 Data Word 3 [63:48] Register */
+#define CAN_MB25_LENGTH         0xFFC02F30      /* Mailbox 25 Data Length Code Register */
+#define CAN_MB25_TIMESTAMP      0xFFC02F34      /* Mailbox 25 Time Stamp Value Register */
+#define CAN_MB25_ID0            0xFFC02F38      /* Mailbox 25 Identifier Low Register */
+#define CAN_MB25_ID1            0xFFC02F3C      /* Mailbox 25 Identifier High Register */
+
+#define CAN_MB26_DATA0          0xFFC02F40      /* Mailbox 26 Data Word 0 [15:0] Register */
+#define CAN_MB26_DATA1          0xFFC02F44      /* Mailbox 26 Data Word 1 [31:16] Register */
+#define CAN_MB26_DATA2          0xFFC02F48      /* Mailbox 26 Data Word 2 [47:32] Register */
+#define CAN_MB26_DATA3          0xFFC02F4C      /* Mailbox 26 Data Word 3 [63:48] Register */
+#define CAN_MB26_LENGTH         0xFFC02F50      /* Mailbox 26 Data Length Code Register */
+#define CAN_MB26_TIMESTAMP      0xFFC02F54      /* Mailbox 26 Time Stamp Value Register */
+#define CAN_MB26_ID0            0xFFC02F58      /* Mailbox 26 Identifier Low Register */
+#define CAN_MB26_ID1            0xFFC02F5C      /* Mailbox 26 Identifier High Register */
+
+#define CAN_MB27_DATA0          0xFFC02F60      /* Mailbox 27 Data Word 0 [15:0] Register */
+#define CAN_MB27_DATA1          0xFFC02F64      /* Mailbox 27 Data Word 1 [31:16] Register */
+#define CAN_MB27_DATA2          0xFFC02F68      /* Mailbox 27 Data Word 2 [47:32] Register */
+#define CAN_MB27_DATA3          0xFFC02F6C      /* Mailbox 27 Data Word 3 [63:48] Register */
+#define CAN_MB27_LENGTH         0xFFC02F70      /* Mailbox 27 Data Length Code Register */
+#define CAN_MB27_TIMESTAMP      0xFFC02F74      /* Mailbox 27 Time Stamp Value Register */
+#define CAN_MB27_ID0            0xFFC02F78      /* Mailbox 27 Identifier Low Register */
+#define CAN_MB27_ID1            0xFFC02F7C      /* Mailbox 27 Identifier High Register */
+
+#define CAN_MB28_DATA0          0xFFC02F80      /* Mailbox 28 Data Word 0 [15:0] Register */
+#define CAN_MB28_DATA1          0xFFC02F84      /* Mailbox 28 Data Word 1 [31:16] Register */
+#define CAN_MB28_DATA2          0xFFC02F88      /* Mailbox 28 Data Word 2 [47:32] Register */
+#define CAN_MB28_DATA3          0xFFC02F8C      /* Mailbox 28 Data Word 3 [63:48] Register */
+#define CAN_MB28_LENGTH         0xFFC02F90      /* Mailbox 28 Data Length Code Register */
+#define CAN_MB28_TIMESTAMP      0xFFC02F94      /* Mailbox 28 Time Stamp Value Register */
+#define CAN_MB28_ID0            0xFFC02F98      /* Mailbox 28 Identifier Low Register */
+#define CAN_MB28_ID1            0xFFC02F9C      /* Mailbox 28 Identifier High Register */
+
+#define CAN_MB29_DATA0          0xFFC02FA0      /* Mailbox 29 Data Word 0 [15:0] Register */
+#define CAN_MB29_DATA1          0xFFC02FA4      /* Mailbox 29 Data Word 1 [31:16] Register */
+#define CAN_MB29_DATA2          0xFFC02FA8      /* Mailbox 29 Data Word 2 [47:32] Register */
+#define CAN_MB29_DATA3          0xFFC02FAC      /* Mailbox 29 Data Word 3 [63:48] Register */
+#define CAN_MB29_LENGTH         0xFFC02FB0      /* Mailbox 29 Data Length Code Register */
+#define CAN_MB29_TIMESTAMP      0xFFC02FB4      /* Mailbox 29 Time Stamp Value Register */
+#define CAN_MB29_ID0            0xFFC02FB8      /* Mailbox 29 Identifier Low Register */
+#define CAN_MB29_ID1            0xFFC02FBC      /* Mailbox 29 Identifier High Register */
+
+#define CAN_MB30_DATA0          0xFFC02FC0      /* Mailbox 30 Data Word 0 [15:0] Register */
+#define CAN_MB30_DATA1          0xFFC02FC4      /* Mailbox 30 Data Word 1 [31:16] Register */
+#define CAN_MB30_DATA2          0xFFC02FC8      /* Mailbox 30 Data Word 2 [47:32] Register */
+#define CAN_MB30_DATA3          0xFFC02FCC      /* Mailbox 30 Data Word 3 [63:48] Register */
+#define CAN_MB30_LENGTH         0xFFC02FD0      /* Mailbox 30 Data Length Code Register */
+#define CAN_MB30_TIMESTAMP      0xFFC02FD4      /* Mailbox 30 Time Stamp Value Register */
+#define CAN_MB30_ID0            0xFFC02FD8      /* Mailbox 30 Identifier Low Register */
+#define CAN_MB30_ID1            0xFFC02FDC      /* Mailbox 30 Identifier High Register */
+
+#define CAN_MB31_DATA0          0xFFC02FE0      /* Mailbox 31 Data Word 0 [15:0] Register */
+#define CAN_MB31_DATA1          0xFFC02FE4      /* Mailbox 31 Data Word 1 [31:16] Register */
+#define CAN_MB31_DATA2          0xFFC02FE8      /* Mailbox 31 Data Word 2 [47:32] Register */
+#define CAN_MB31_DATA3          0xFFC02FEC      /* Mailbox 31 Data Word 3 [63:48] Register */
+#define CAN_MB31_LENGTH         0xFFC02FF0      /* Mailbox 31 Data Length Code Register */
+#define CAN_MB31_TIMESTAMP      0xFFC02FF4      /* Mailbox 31 Time Stamp Value Register */
+#define CAN_MB31_ID0            0xFFC02FF8      /* Mailbox 31 Identifier Low Register */
+#define CAN_MB31_ID1            0xFFC02FFC      /* Mailbox 31 Identifier High Register */
+
+/* CAN Mailbox Area Macros */
+#define CAN_MB_ID1(x)           (CAN_MB00_ID1+((x)*0x20))
+#define CAN_MB_ID0(x)           (CAN_MB00_ID0+((x)*0x20))
+#define CAN_MB_TIMESTAMP(x)     (CAN_MB00_TIMESTAMP+((x)*0x20))
+#define CAN_MB_LENGTH(x)        (CAN_MB00_LENGTH+((x)*0x20))
+#define CAN_MB_DATA3(x)         (CAN_MB00_DATA3+((x)*0x20))
+#define CAN_MB_DATA2(x)         (CAN_MB00_DATA2+((x)*0x20))
+#define CAN_MB_DATA1(x)         (CAN_MB00_DATA1+((x)*0x20))
+#define CAN_MB_DATA0(x)         (CAN_MB00_DATA0+((x)*0x20))
+
+
+/*********************************************************************************** */
+/* System MMR Register Bits and Macros */
+/******************************************************************************* */
+
+/* SWRST Mask */
+#define SYSTEM_RESET    0x0007  /* Initiates A System Software Reset */
+#define DOUBLE_FAULT    0x0008  /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE    0x2000  /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG              0x4000  /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE  0x8000  /* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks                                                                                                   */
+#define BMODE                   0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins */
+#define NOBOOT                  0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
+
+/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
+#define PLL_WAKEUP_IRQ          0x00000001      /* PLL Wakeup Interrupt Request */
+#define DMAC0_ERR_IRQ           0x00000002      /* DMA Controller 0 Error Interrupt Request */
+#define PPI_ERR_IRQ             0x00000004      /* PPI Error Interrupt Request */
+#define SPORT0_ERR_IRQ          0x00000008      /* SPORT0 Error Interrupt Request */
+#define SPORT1_ERR_IRQ          0x00000010      /* SPORT1 Error Interrupt Request */
+#define SPI0_ERR_IRQ            0x00000020      /* SPI0 Error Interrupt Request */
+#define UART0_ERR_IRQ           0x00000040      /* UART0 Error Interrupt Request */
+#define RTC_IRQ                 0x00000080      /* Real-Time Clock Interrupt Request */
+#define DMA0_IRQ                0x00000100      /* DMA Channel 0 (PPI) Interrupt Request */
+#define DMA1_IRQ                0x00000200      /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
+#define DMA2_IRQ                0x00000400      /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
+#define DMA3_IRQ                0x00000800      /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
+#define DMA4_IRQ                0x00001000      /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
+#define DMA5_IRQ                0x00002000      /* DMA Channel 5 (SPI) Interrupt Request */
+#define DMA6_IRQ                0x00004000      /* DMA Channel 6 (UART RX) Interrupt Request */
+#define DMA7_IRQ                0x00008000      /* DMA Channel 7 (UART TX) Interrupt Request */
+#define TIMER0_IRQ              0x00010000      /* Timer 0 Interrupt Request */
+#define TIMER1_IRQ              0x00020000      /* Timer 1 Interrupt Request */
+#define TIMER2_IRQ              0x00040000      /* Timer 2 Interrupt Request */
+#define PFA_IRQ                 0x00080000      /* Programmable Flag Interrupt Request A */
+#define PFB_IRQ                 0x00100000      /* Programmable Flag Interrupt Request B */
+#define MDMA0_0_IRQ             0x00200000      /* MemDMA0 Stream 0 Interrupt Request */
+#define MDMA0_1_IRQ             0x00400000      /* MemDMA0 Stream 1 Interrupt Request */
+#define WDOG_IRQ                0x00800000      /* Software Watchdog Timer Interrupt Request */
+#define DMAC1_ERR_IRQ           0x01000000      /* DMA Controller 1 Error Interrupt Request */
+#define SPORT2_ERR_IRQ          0x02000000      /* SPORT2 Error Interrupt Request */
+#define SPORT3_ERR_IRQ          0x04000000      /* SPORT3 Error Interrupt Request */
+#define MXVR_SD_IRQ             0x08000000      /* MXVR Synchronous Data Interrupt Request */
+#define SPI1_ERR_IRQ            0x10000000      /* SPI1 Error Interrupt Request */
+#define SPI2_ERR_IRQ            0x20000000      /* SPI2 Error Interrupt Request */
+#define UART1_ERR_IRQ           0x40000000      /* UART1 Error Interrupt Request */
+#define UART2_ERR_IRQ           0x80000000      /* UART2 Error Interrupt Request */
+
+/* the following are for backwards compatibility */
+#define DMA0_ERR_IRQ            DMAC0_ERR_IRQ
+#define DMA1_ERR_IRQ            DMAC1_ERR_IRQ
+
+
+/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1   */
+#define CAN_ERR_IRQ                     0x00000001      /* CAN Error Interrupt Request */
+#define DMA8_IRQ                        0x00000002      /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
+#define DMA9_IRQ                        0x00000004      /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
+#define DMA10_IRQ                       0x00000008      /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
+#define DMA11_IRQ                       0x00000010      /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
+#define DMA12_IRQ                       0x00000020      /* DMA Channel 12 Interrupt Request */
+#define DMA13_IRQ                       0x00000040      /* DMA Channel 13 Interrupt Request */
+#define DMA14_IRQ                       0x00000080      /* DMA Channel 14 (SPI1) Interrupt Request */
+#define DMA15_IRQ                       0x00000100      /* DMA Channel 15 (SPI2) Interrupt Request */
+#define DMA16_IRQ                       0x00000200      /* DMA Channel 16 (UART1 RX) Interrupt Request */
+#define DMA17_IRQ                       0x00000400      /* DMA Channel 17 (UART1 TX) Interrupt Request */
+#define DMA18_IRQ                       0x00000800      /* DMA Channel 18 (UART2 RX) Interrupt Request */
+#define DMA19_IRQ                       0x00001000      /* DMA Channel 19 (UART2 TX) Interrupt Request */
+#define TWI0_IRQ                        0x00002000      /* TWI0 Interrupt Request */
+#define TWI1_IRQ                        0x00004000      /* TWI1 Interrupt Request */
+#define CAN_RX_IRQ                      0x00008000      /* CAN Receive Interrupt Request */
+#define CAN_TX_IRQ                      0x00010000      /* CAN Transmit Interrupt Request */
+#define MDMA1_0_IRQ                     0x00020000      /* MemDMA1 Stream 0 Interrupt Request */
+#define MDMA1_1_IRQ                     0x00040000      /* MemDMA1 Stream 1 Interrupt Request */
+#define MXVR_STAT_IRQ                   0x00080000      /* MXVR Status Interrupt Request */
+#define MXVR_CM_IRQ                     0x00100000      /* MXVR Control Message Interrupt Request */
+#define MXVR_AP_IRQ                     0x00200000      /* MXVR Asynchronous Packet Interrupt */
+
+/* the following are for backwards compatibility */
+#define MDMA0_IRQ               MDMA1_0_IRQ
+#define MDMA1_IRQ               MDMA1_1_IRQ
+
+#ifdef _MISRA_RULES
+#define _MF15 0xFu
+#define _MF7 7u
+#else
+#define _MF15 0xF
+#define _MF7 7
+#endif /* _MISRA_RULES */
+
+/* SIC_IMASKx Masks                                                                                      */
+#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts */
+#ifdef _MISRA_RULES
+#define SIC_MASK(x)             (1 << ((x)&0x1Fu))                                      /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x)   (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Unmask Peripheral #x interrupt */
+#else
+#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
+
+/* SIC_IWRx Masks                                                                                        */
+#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals */
+#ifdef _MISRA_RULES
+#define IWR_ENABLE(x)   (1 << ((x)&0x1Fu))                                      /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Wakeup Disable Peripheral #x */
+#else
+#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
+
+/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
+/*  PPI_CONTROL Masks         */
+#define PORT_EN         0x0001  /* PPI Port Enable  */
+#define PORT_DIR        0x0002  /* PPI Port Direction       */
+#define XFR_TYPE        0x000C  /* PPI Transfer Type  */
+#define PORT_CFG        0x0030  /* PPI Port Configuration */
+#define FLD_SEL         0x0040  /* PPI Active Field Select */
+#define PACK_EN         0x0080  /* PPI Packing Mode */
+/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
+#define SKIP_EN         0x0200  /* PPI Skip Element Enable */
+#define SKIP_EO         0x0400  /* PPI Skip Even/Odd Elements */
+#define DLENGTH         0x3800  /* PPI Data Length  */
+#define DLEN_8          0x0          /* PPI Data Length mask for DLEN=8 */
+#define DLEN_10         0x0800          /* Data Length = 10 Bits */
+#define DLEN_11         0x1000          /* Data Length = 11 Bits */
+#define DLEN_12         0x1800          /* Data Length = 12 Bits */
+#define DLEN_13         0x2000          /* Data Length = 13 Bits */
+#define DLEN_14         0x2800          /* Data Length = 14 Bits */
+#define DLEN_15         0x3000          /* Data Length = 15 Bits */
+#define DLEN_16         0x3800          /* Data Length = 16 Bits */
+#ifdef _MISRA_RULES
+#define DLEN(x)         ((((x)-9u) & 0x07u) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
+#else
+#define DLEN(x)         ((((x)-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
+#endif /* _MISRA_RULES */
+#define POL                     0xC000  /* PPI Signal Polarities       */
+#define POLC            0x4000          /* PPI Clock Polarity */
+#define POLS            0x8000          /* PPI Frame Sync Polarity */
+
+
+/* PPI_STATUS Masks                                          */
+#define FLD                     0x0400  /* Field Indicator   */
+#define FT_ERR          0x0800  /* Frame Track Error */
+#define OVR                     0x1000  /* FIFO Overflow Error */
+#define UNDR            0x2000  /* FIFO Underrun Error */
+#define ERR_DET         0x4000  /* Error Detected Indicator */
+#define ERR_NCOR        0x8000  /* Error Not Corrected Indicator */
+
+
+/* **********  DMA CONTROLLER MASKS  ***********************/
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+
+#define CTYPE                   0x0040  /* DMA Channel Type Indicator */
+#define CTYPE_P                 0x6             /* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8                   0x0080  /* DMA 8-bit Operation Indicator   */
+#define PCAP16                  0x0100  /* DMA 16-bit Operation Indicator */
+#define PCAP32                  0x0200  /* DMA 32-bit Operation Indicator */
+#define PCAPWR                  0x0400  /* DMA Write Operation Indicator */
+#define PCAPRD                  0x0800  /* DMA Read Operation Indicator */
+#define PMAP                    0xF000  /* DMA Peripheral Map Field */
+
+/* PMAP Encodings For DMA Controller 0 */
+#define PMAP_PPI                0x0000  /* PMAP PPI Port DMA */
+#define PMAP_SPORT0RX   0x1000  /* PMAP SPORT0 Receive DMA */
+#define PMAP_SPORT0TX   0x2000  /* PMAP SPORT0 Transmit DMA */
+#define PMAP_SPORT1RX   0x3000  /* PMAP SPORT1 Receive DMA */
+#define PMAP_SPORT1TX   0x4000  /* PMAP SPORT1 Transmit DMA */
+#define PMAP_SPI0               0x5000  /* PMAP SPI DMA */
+#define PMAP_UART0RX            0x6000  /* PMAP UART Receive DMA */
+#define PMAP_UART0TX            0x7000  /* PMAP UART Transmit DMA */
+
+/* PMAP Encodings For DMA Controller 1 */
+#define PMAP_SPORT2RX       0x0000  /* PMAP SPORT2 Receive DMA */
+#define PMAP_SPORT2TX       0x1000  /* PMAP SPORT2 Transmit DMA */
+#define PMAP_SPORT3RX       0x2000  /* PMAP SPORT3 Receive DMA */
+#define PMAP_SPORT3TX       0x3000  /* PMAP SPORT3 Transmit DMA */
+#define PMAP_SPI1           0x6000  /* PMAP SPI1 DMA */
+#define PMAP_SPI2           0x7000  /* PMAP SPI2 DMA */
+#define PMAP_UART1RX        0x8000  /* PMAP UART1 Receive DMA */
+#define PMAP_UART1TX        0x9000  /* PMAP UART1 Transmit DMA */
+#define PMAP_UART2RX        0xA000  /* PMAP UART2 Receive DMA */
+#define PMAP_UART2TX        0xB000  /* PMAP UART2 Transmit DMA */
+
+
+/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
+/* PWM Timer bit definitions */
+/* TIMER_ENABLE Register */
+#define TIMEN0                  0x0001  /* Enable Timer 0 */
+#define TIMEN1                  0x0002  /* Enable Timer 1 */
+#define TIMEN2                  0x0004  /* Enable Timer 2 */
+
+#define TIMEN0_P                0x00
+#define TIMEN1_P                0x01
+#define TIMEN2_P                0x02
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0                 0x0001  /* Disable Timer 0 */
+#define TIMDIS1                 0x0002  /* Disable Timer 1 */
+#define TIMDIS2                 0x0004  /* Disable Timer 2 */
+
+#define TIMDIS0_P               0x00
+#define TIMDIS1_P               0x01
+#define TIMDIS2_P               0x02
+
+/* TIMER_STATUS Register */
+#define TIMIL0                  0x0001  /* Timer 0 Interrupt */
+#define TIMIL1                  0x0002  /* Timer 1 Interrupt */
+#define TIMIL2                  0x0004  /* Timer 2 Interrupt */
+#define TOVF_ERR0               0x0010  /* Timer 0 Counter Overflow */
+#define TOVF_ERR1               0x0020  /* Timer 1 Counter Overflow */
+#define TOVF_ERR2               0x0040  /* Timer 2 Counter Overflow */
+#define TRUN0                   0x1000  /* Timer 0 Slave Enable Status */
+#define TRUN1                   0x2000  /* Timer 1 Slave Enable Status */
+#define TRUN2                   0x4000  /* Timer 2 Slave Enable Status */
+
+#define TIMIL0_P                0x00
+#define TIMIL1_P                0x01
+#define TIMIL2_P                0x02
+#define TOVF_ERR0_P             0x04
+#define TOVF_ERR1_P             0x05
+#define TOVF_ERR2_P             0x06
+#define TRUN0_P                 0x0C
+#define TRUN1_P                 0x0D
+#define TRUN2_P                 0x0E
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0               TOVF_ERR0
+#define TOVL_ERR1               TOVF_ERR1
+#define TOVL_ERR2               TOVF_ERR2
+#define TOVL_ERR0_P             TOVF_ERR0_P
+#define TOVL_ERR1_P     TOVF_ERR1_P
+#define TOVL_ERR2_P     TOVF_ERR2_P
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT                 0x0001
+#define WDTH_CAP                0x0002
+#define EXT_CLK                 0x0003
+#define PULSE_HI                0x0004
+#define PERIOD_CNT              0x0008
+#define IRQ_ENA                 0x0010
+#define TIN_SEL                 0x0020
+#define OUT_DIS                 0x0040
+#define CLK_SEL                 0x0080
+#define TOGGLE_HI               0x0100
+#define EMU_RUN                 0x0200
+#ifdef _MISRA_RULES
+#define ERR_TYP(x)              (((x) & 0x03u) << 14)
+#else
+#define ERR_TYP(x)              (((x) & 0x03) << 14)
+#endif /* _MISRA_RULES */
+
+#define TMODE_P0                0x00
+#define TMODE_P1                0x01
+#define PULSE_HI_P              0x02
+#define PERIOD_CNT_P    0x03
+#define IRQ_ENA_P               0x04
+#define TIN_SEL_P               0x05
+#define OUT_DIS_P               0x06
+#define CLK_SEL_P               0x07
+#define TOGGLE_HI_P             0x08
+#define EMU_RUN_P               0x09
+#define ERR_TYP_P0              0x0E
+#define ERR_TYP_P1              0x0F
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
+/* EBIU_AMGCTL Masks */
+#define AMCKEN          0x0001  /* Enable CLKOUT */
+#define AMBEN_NONE      0x0000  /* All Banks Disabled */
+#define AMBEN_B0        0x0002  /* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1     0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2  0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL       0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+#define CDPRIO          0x0100  /* DMA has priority over core for external accesses */
+
+/* EBIU_AMGCTL Bit Positions */
+#define AMCKEN_P                0x0000  /* Enable CLKOUT */
+#define AMBEN_P0                0x0001  /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1                0x0002  /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
+#define AMBEN_P2                0x0003  /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN                 0x00000001  /* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL                0x00000002  /* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1                  0x00000004  /* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2                  0x00000008  /* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3                  0x0000000C  /* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4                  0x00000000  /* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1                  0x00000010  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2                  0x00000020  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3                  0x00000030  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4                  0x00000000  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1                  0x00000040  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2                  0x00000080  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3                  0x000000C0  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0                  0x00000000  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1                 0x00000100  /* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2                 0x00000200  /* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3                 0x00000300  /* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4                 0x00000400  /* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5                 0x00000500  /* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6                 0x00000600  /* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7                 0x00000700  /* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8                 0x00000800  /* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9                 0x00000900  /* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10                0x00000A00  /* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11                0x00000B00  /* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12                0x00000C00  /* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13                0x00000D00  /* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14                0x00000E00  /* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15                0x00000F00  /* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1                 0x00001000  /* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2                 0x00002000  /* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3                 0x00003000  /* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4                 0x00004000  /* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5                 0x00005000  /* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6                 0x00006000  /* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7                 0x00007000  /* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8                 0x00008000  /* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9                 0x00009000  /* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10                0x0000A000  /* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11                0x0000B000  /* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12                0x0000C000  /* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13                0x0000D000  /* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14                0x0000E000  /* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15                0x0000F000  /* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN                 0x00010000  /* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL                0x00020000  /* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1                  0x00040000  /* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2                  0x00080000  /* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3                  0x000C0000  /* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4                  0x00000000  /* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1                  0x00100000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2                  0x00200000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3                  0x00300000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4                  0x00000000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1                  0x00400000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2                  0x00800000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3                  0x00C00000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0                  0x00000000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1                 0x01000000  /* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2                 0x02000000  /* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3                 0x03000000  /* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4                 0x04000000  /* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5                 0x05000000  /* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6                 0x06000000  /* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7                 0x07000000  /* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8                 0x08000000  /* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9                 0x09000000  /* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10                0x0A000000  /* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11                0x0B000000  /* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12                0x0C000000  /* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13                0x0D000000  /* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14                0x0E000000  /* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15                0x0F000000  /* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1                 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2                 0x20000000  /* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3                 0x30000000  /* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4                 0x40000000  /* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5                 0x50000000  /* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6                 0x60000000  /* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7                 0x70000000  /* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8                 0x80000000  /* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9                 0x90000000  /* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10                0xA0000000  /* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11                0xB0000000  /* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12                0xC0000000  /* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13                0xD0000000  /* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14                0xE0000000  /* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15                0xF0000000  /* Bank 1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN                 0x00000001  /* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL                0x00000002  /* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1                  0x00000004  /* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2                  0x00000008  /* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3                  0x0000000C  /* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4                  0x00000000  /* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1                  0x00000010  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2                  0x00000020  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3                  0x00000030  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4                  0x00000000  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1                  0x00000040  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2                  0x00000080  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3                  0x000000C0  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0                  0x00000000  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1                 0x00000100  /* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2                 0x00000200  /* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3                 0x00000300  /* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4                 0x00000400  /* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5                 0x00000500  /* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6                 0x00000600  /* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7                 0x00000700  /* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8                 0x00000800  /* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9                 0x00000900  /* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10                0x00000A00  /* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11                0x00000B00  /* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12                0x00000C00  /* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13                0x00000D00  /* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14                0x00000E00  /* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15                0x00000F00  /* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1                 0x00001000  /* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2                 0x00002000  /* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3                 0x00003000  /* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4                 0x00004000  /* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5                 0x00005000  /* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6                 0x00006000  /* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7                 0x00007000  /* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8                 0x00008000  /* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9                 0x00009000  /* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10                0x0000A000  /* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11                0x0000B000  /* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12                0x0000C000  /* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13                0x0000D000  /* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14                0x0000E000  /* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15                0x0000F000  /* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN                 0x00010000  /* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL                0x00020000  /* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1                  0x00040000  /* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2                  0x00080000  /* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3                  0x000C0000  /* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4                  0x00000000  /* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1                  0x00100000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2                  0x00200000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3                  0x00300000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4                  0x00000000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1                  0x00400000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2                  0x00800000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3                  0x00C00000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0                  0x00000000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1                 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2                 0x02000000  /* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3                 0x03000000  /* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4                 0x04000000  /* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5                 0x05000000  /* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6                 0x06000000  /* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7                 0x07000000  /* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8                 0x08000000  /* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9                 0x09000000  /* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10                0x0A000000  /* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11                0x0B000000  /* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12                0x0C000000  /* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13                0x0D000000  /* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14                0x0E000000  /* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15                0x0F000000  /* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1                 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2                 0x20000000  /* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3                 0x30000000  /* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4                 0x40000000  /* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5                 0x50000000  /* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6                 0x60000000  /* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7                 0x70000000  /* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8                 0x80000000  /* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9                 0x90000000  /* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10                0xA0000000  /* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11                0xB0000000  /* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12                0xC0000000  /* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13                0xD0000000  /* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14                0xE0000000  /* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15                0xF0000000  /* Bank 3 Write Access Time = 15 cycles */
+
+/* **********************  SDRAM CONTROLLER MASKS  *************************** */
+/* EBIU_SDGCTL Masks */
+#define SCTLE                   0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2                    0x00000008 /* SDRAM CAS latency = 2 cycles */
+#define CL_3                    0x0000000C /* SDRAM CAS latency = 3 cycles */
+#define PFE                             0x00000010 /* Enable SDRAM prefetch */
+#define PFP                             0x00000020 /* Prefetch has priority over AMC requests */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1                  0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2                  0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3                  0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4                  0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5                  0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6                  0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7                  0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8                  0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9                  0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10                 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11                 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12                 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13                 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14                 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15                 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1                   0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2                   0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3                   0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4                   0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5                   0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6                   0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7                   0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1                  0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2                  0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3                  0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4                  0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5                  0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6                  0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7                  0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1                   0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2                   0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3                   0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD                   0x00200000 /*Power-up start delay */
+#define PSM                             0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS                             0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS                    0x01000000 /* Start SDRAM self-refresh mode */
+#define EBUFE                   0x02000000 /* Enable external buffering timing */
+#define FBBRW                   0x04000000 /* Fast back-to-back read write enable */
+#define EMREN                   0x10000000 /* Extended mode register enable */
+#define TCSR                    0x20000000 /* Temp compensated self refresh value 85 deg C */
+#define CDDBG                   0x40000000 /* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE                             0x00000001 /* Enable SDRAM external bank */
+#define EBSZ_16                 0x00000000 /* SDRAM external bank size = 16MB */
+#define EBSZ_32                 0x00000002 /* SDRAM external bank size = 32MB */
+#define EBSZ_64                 0x00000004 /* SDRAM external bank size = 64MB */
+#define EBSZ_128                0x00000006 /* SDRAM external bank size = 128MB */
+#define EBSZ_256                0x00000008 /* SDRAM External Bank Size = 256MB */
+#define EBSZ_512                0x0000000A /* SDRAM External Bank Size = 512MB */
+#define EBCAW_8                 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9                 0x00000010 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10                0x00000020 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11                0x00000030 /* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI                    0x00000001 /* SDRAM controller is idle */
+#define SDSRA                   0x00000002 /* SDRAM SDRAM self refresh is active */
+#define SDPUA                   0x00000004 /* SDRAM power up active  */
+#define SDRS                    0x00000008 /* SDRAM is in reset state */
+#define SDEASE                  0x00000010 /* SDRAM EAB sticky error status - W1C */
+#define BGSTAT                  0x00000020 /* Bus granted */
+
+
+/*  ********************  TWO-WIRE INTERFACE (TWIx) MASKS  ***********************/
+/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
+#ifdef _MISRA_RULES
+#define CLKLOW(x)       ((x) & 0xFFu)           /* Periods Clock Is Held Low */
+#define CLKHI(y)        (((y)&0xFFu)<<0x8)      /* Periods Before New Clock Low */
+#else
+#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low */
+#endif /* _MISRA_RULES */
+
+/* TWIx_PRESCALE Masks                                                           */
+#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz) */
+#define TWI_ENA         0x0080          /* TWI Enable            */
+#define SCCB            0x0200          /* SCCB Compatibility Enable */
+
+/* TWIx_SLAVE_CTRL Masks                                                                 */
+#define SEN                     0x0001          /* Slave Enable          */
+#define SADD_LEN        0x0002          /* Slave Address Length */
+#define STDVAL          0x0004          /* Slave Transmit Data Valid */
+#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010          /* General Call Adrress Matching Enabled */
+
+/* TWIx_SLAVE_STAT Masks                                                                 */
+#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002          /* General Call Indicator */
+
+/* TWIx_MASTER_CTRL Masks                                                */
+#define MEN                     0x0001          /* Master Mode Enable */
+#define MADD_LEN        0x0002          /* Master Address Length */
+#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*) */
+#define FAST            0x0008          /* Use Fast Mode Timing Specs */
+#define STOP            0x0010          /* Issue Stop Condition */
+#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer */
+#define DCNT            0x3FC0          /* Data Bytes To Transfer */
+#define SDAOVR          0x4000          /* Serial Data Override */
+#define SCLOVR          0x8000          /* Serial Clock Override */
+
+/* TWIx_MASTER_STAT Masks                                                        */
+#define MPROG           0x0001          /* Master Transfer In Progress */
+#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted) */
+#define ANAK            0x0004          /* Address Not Acknowledged */
+#define DNAK            0x0008          /* Data Not Acknowledged */
+#define BUFRDERR        0x0010          /* Buffer Read Error */
+#define BUFWRERR        0x0020          /* Buffer Write Error */
+#define SDASEN          0x0040          /* Serial Data Sense */
+#define SCLSEN          0x0080          /* Serial Clock Sense */
+#define BUSBUSY         0x0100          /* Bus Busy Indicator */
+
+/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
+#define SINIT           0x0001          /* Slave Transfer Initiated */
+#define SCOMP           0x0002          /* Slave Transfer Complete */
+#define SERR            0x0004          /* Slave Transfer Error */
+#define SOVF            0x0008          /* Slave Overflow */
+#define MCOMP           0x0010          /* Master Transfer Complete */
+#define MERR            0x0020          /* Master Transfer Error */
+#define XMTSERV         0x0040          /* Transmit FIFO Service */
+#define RCVSERV         0x0080          /* Receive FIFO Service */
+
+/* TWIx_FIFO_CTL Masks                                   */
+#define XMTFLUSH        0x0001          /* Transmit Buffer Flush */
+#define RCVFLUSH        0x0002          /* Receive Buffer Flush */
+#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length */
+#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length */
+
+/* TWIx_FIFO_STAT Masks                                                          */
+#define XMTSTAT         0x0003          /* Transmit FIFO Status */
+#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty */
+#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write */
+#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write) */
+
+#define RCVSTAT         0x000C          /* Receive FIFO Status */
+#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty */
+#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read */
+#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read) */
+
+#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 7a8ac5f44204..8100bcd01a0d 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1,859 +1,13 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
 
-/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF538/9 */
-
 #ifndef _DEF_BF539_H
 #define _DEF_BF539_H
 
-/* include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL                 0xFFC00000      /* PLL Control register (16-bit) */
-#define PLL_DIV                 0xFFC00004      /* PLL Divide Register (16-bit) */
-#define VR_CTL                  0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT                0xFFC0000C      /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT             0xFFC00010      /* PLL Lock     Count register (16-bit) */
-#define CHIPID                  0xFFC00014      /* Chip ID Register */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST                   0xFFC00100  /* Software Reset Register (16-bit) */
-#define SYSCR                   0xFFC00104  /* System Configuration registe */
-#define SIC_RVECT               0xFFC00108
-#define SIC_IMASK0              0xFFC0010C  /* Interrupt Mask Register */
-#define SIC_IAR0                0xFFC00110  /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                0xFFC00114  /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                0xFFC00118  /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3 */
-#define SIC_ISR0                        0xFFC00120  /* Interrupt Status Register */
-#define SIC_IWR0                        0xFFC00124  /* Interrupt Wakeup Register */
-#define SIC_IMASK1                      0xFFC00128      /* Interrupt Mask Register 1 */
-#define SIC_ISR1                        0xFFC0012C      /* Interrupt Status Register 1 */
-#define SIC_IWR1                        0xFFC00130      /* Interrupt Wakeup Register 1 */
-#define SIC_IAR4                        0xFFC00134      /* Interrupt Assignment Register 4 */
-#define SIC_IAR5                        0xFFC00138      /* Interrupt Assignment Register 5 */
-#define SIC_IAR6                        0xFFC0013C      /* Interrupt Assignment Register 6 */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL        0xFFC00200  /* Watchdog Control Register */
-#define WDOG_CNT        0xFFC00204  /* Watchdog Count Register */
-#define WDOG_STAT       0xFFC00208  /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT        0xFFC00300  /* RTC Status Register */
-#define RTC_ICTL        0xFFC00304  /* RTC Interrupt Control Register */
-#define RTC_ISTAT       0xFFC00308  /* RTC Interrupt Status Register */
-#define RTC_SWCNT       0xFFC0030C  /* RTC Stopwatch Count Register */
-#define RTC_ALARM       0xFFC00310  /* RTC Alarm Time Register */
-#define RTC_FAST        0xFFC00314  /* RTC Prescaler Enable Register */
-#define RTC_PREN                0xFFC00314  /* RTC Prescaler Enable Register (alternate macro) */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR             0xFFC00400  /* Transmit Holding register */
-#define UART0_RBR             0xFFC00400  /* Receive Buffer register */
-#define UART0_DLL             0xFFC00400  /* Divisor Latch (Low-Byte) */
-#define UART0_IER             0xFFC00404  /* Interrupt Enable Register */
-#define UART0_DLH             0xFFC00404  /* Divisor Latch (High-Byte) */
-#define UART0_IIR             0xFFC00408  /* Interrupt Identification Register */
-#define UART0_LCR             0xFFC0040C  /* Line Control Register */
-#define UART0_MCR                        0xFFC00410  /* Modem Control Register */
-#define UART0_LSR             0xFFC00414  /* Line Status Register */
-#define UART0_SCR             0xFFC0041C  /* SCR Scratch Register */
-#define UART0_GCTL                   0xFFC00424  /* Global Control Register */
-
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-
-#define SPI0_CTL                        0xFFC00500  /* SPI0 Control Register */
-#define SPI0_FLG                        0xFFC00504  /* SPI0 Flag register */
-#define SPI0_STAT                       0xFFC00508  /* SPI0 Status register */
-#define SPI0_TDBR                       0xFFC0050C  /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                       0xFFC00510  /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                       0xFFC00514  /* SPI0 Baud rate Register */
-#define SPI0_SHADOW                     0xFFC00518  /* SPI0_RDBR Shadow Register */
-#define SPI0_REGBASE                    SPI0_CTL
-
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG                   0xFFC00600     /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                          0xFFC00604     /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                   0xFFC00608     /* Timer 0 Period Register */
-#define TIMER0_WIDTH                    0xFFC0060C     /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG                   0xFFC00610      /*  Timer 1 Configuration Register   */
-#define TIMER1_COUNTER                  0xFFC00614      /*  Timer 1 Counter Register         */
-#define TIMER1_PERIOD                   0xFFC00618      /*  Timer 1 Period Register          */
-#define TIMER1_WIDTH                    0xFFC0061C      /*  Timer 1 Width Register           */
-
-#define TIMER2_CONFIG                   0xFFC00620      /* Timer 2 Configuration Register   */
-#define TIMER2_COUNTER                  0xFFC00624      /* Timer 2 Counter Register         */
-#define TIMER2_PERIOD                   0xFFC00628      /* Timer 2 Period Register          */
-#define TIMER2_WIDTH                    0xFFC0062C      /* Timer 2 Width Register           */
-
-#define TIMER_ENABLE                            0xFFC00640      /* Timer Enable Register */
-#define TIMER_DISABLE                           0xFFC00644      /* Timer Disable Register */
-#define TIMER_STATUS                            0xFFC00648      /* Timer Status Register */
-
-
-/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
-#define FIO_FLAG_D                              0xFFC00700  /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C                      0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S                      0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T                                      0xFFC0070C  /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D                     0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C                     0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S                     0xFFC00718  /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T                     0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D                     0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C                     0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S                     0xFFC00728  /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T                     0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR                         0xFFC00730  /* Peripheral Flag Direction Register */
-#define FIO_POLAR                       0xFFC00734  /* Flag Source Polarity Register */
-#define FIO_EDGE                        0xFFC00738  /* Flag Source Sensitivity Register */
-#define FIO_BOTH                        0xFFC0073C  /* Flag Set on BOTH Edges Register */
-#define FIO_INEN                                        0xFFC00740  /* Flag Input Enable Register  */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1                             0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                             0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                  0xFFC00808  /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                   0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                       0xFFC00810  /* SPORT0 TX Data Register */
-#define SPORT0_RX                       0xFFC00818  /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                             0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                             0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                  0xFFC00828  /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                   0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                     0xFFC00830  /* SPORT0 Status Register */
-#define SPORT0_CHNL                     0xFFC00834  /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                    0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                    0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                    0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                    0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                    0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                    0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                    0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                    0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                    0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                    0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1                             0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                             0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                  0xFFC00908  /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                   0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                       0xFFC00910  /* SPORT1 TX Data Register */
-#define SPORT1_RX                       0xFFC00918  /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                             0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                             0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                  0xFFC00928  /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                   0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                     0xFFC00930  /* SPORT1 Status Register */
-#define SPORT1_CHNL                     0xFFC00934  /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                    0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                    0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                    0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                    0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                    0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                    0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                    0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                    0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                    0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                    0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-/* Asynchronous Memory Controller  */
-#define EBIU_AMGCTL                     0xFFC00A00  /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0            0xFFC00A04  /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1            0xFFC00A08  /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller */
-#define EBIU_SDGCTL                     0xFFC00A10  /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                     0xFFC00A14  /* SDRAM Bank Control Register */
-#define EBIU_SDRRC                      0xFFC00A18  /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT                     0xFFC00A1C  /* SDRAM Status Register */
-
-
-
-/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
-
-#define DMAC0_TC_PER                    0xFFC00B0C      /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT                    0xFFC00B10      /* DMA Controller 0 Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA0_TCPER                      DMAC0_TC_PER
-#define DMA0_TCCNT                      DMAC0_TC_CNT
-
-
-/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF)                                                    */
-
-#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register */
-
-#define MDMA0_D0_NEXT_DESC_PTR  0xFFC00E00      /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA0_D0_START_ADDR             0xFFC00E04      /* MemDMA0 Stream 0 Destination Start Address Register */
-#define MDMA0_D0_CONFIG                 0xFFC00E08      /* MemDMA0 Stream 0 Destination Configuration Register */
-#define MDMA0_D0_X_COUNT                0xFFC00E10      /* MemDMA0 Stream 0 Destination X Count Register */
-#define MDMA0_D0_X_MODIFY               0xFFC00E14      /* MemDMA0 Stream 0 Destination X Modify Register */
-#define MDMA0_D0_Y_COUNT                0xFFC00E18      /* MemDMA0 Stream 0 Destination Y Count Register */
-#define MDMA0_D0_Y_MODIFY               0xFFC00E1C      /* MemDMA0 Stream 0 Destination Y Modify Register */
-#define MDMA0_D0_CURR_DESC_PTR  0xFFC00E20      /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA0_D0_CURR_ADDR              0xFFC00E24      /* MemDMA0 Stream 0 Destination Current Address Register */
-#define MDMA0_D0_IRQ_STATUS             0xFFC00E28      /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
-#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C      /* MemDMA0 Stream 0 Destination Peripheral Map Register */
-#define MDMA0_D0_CURR_X_COUNT   0xFFC00E30      /* MemDMA0 Stream 0 Destination Current X Count Register */
-#define MDMA0_D0_CURR_Y_COUNT   0xFFC00E38      /* MemDMA0 Stream 0 Destination Current Y Count Register */
-
-#define MDMA0_S0_NEXT_DESC_PTR  0xFFC00E40      /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA0_S0_START_ADDR             0xFFC00E44      /* MemDMA0 Stream 0 Source Start Address Register */
-#define MDMA0_S0_CONFIG                 0xFFC00E48      /* MemDMA0 Stream 0 Source Configuration Register */
-#define MDMA0_S0_X_COUNT                0xFFC00E50      /* MemDMA0 Stream 0 Source X Count Register */
-#define MDMA0_S0_X_MODIFY               0xFFC00E54      /* MemDMA0 Stream 0 Source X Modify Register */
-#define MDMA0_S0_Y_COUNT                0xFFC00E58      /* MemDMA0 Stream 0 Source Y Count Register */
-#define MDMA0_S0_Y_MODIFY               0xFFC00E5C      /* MemDMA0 Stream 0 Source Y Modify Register */
-#define MDMA0_S0_CURR_DESC_PTR  0xFFC00E60      /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA0_S0_CURR_ADDR              0xFFC00E64      /* MemDMA0 Stream 0 Source Current Address Register */
-#define MDMA0_S0_IRQ_STATUS             0xFFC00E68      /* MemDMA0 Stream 0 Source Interrupt/Status Register */
-#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C      /* MemDMA0 Stream 0 Source Peripheral Map Register */
-#define MDMA0_S0_CURR_X_COUNT   0xFFC00E70      /* MemDMA0 Stream 0 Source Current X Count Register */
-#define MDMA0_S0_CURR_Y_COUNT   0xFFC00E78      /* MemDMA0 Stream 0 Source Current Y Count Register */
-
-#define MDMA0_D1_NEXT_DESC_PTR  0xFFC00E80      /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA0_D1_START_ADDR             0xFFC00E84      /* MemDMA0 Stream 1 Destination Start Address Register */
-#define MDMA0_D1_CONFIG                 0xFFC00E88      /* MemDMA0 Stream 1 Destination Configuration Register */
-#define MDMA0_D1_X_COUNT                0xFFC00E90      /* MemDMA0 Stream 1 Destination X Count Register */
-#define MDMA0_D1_X_MODIFY               0xFFC00E94      /* MemDMA0 Stream 1 Destination X Modify Register */
-#define MDMA0_D1_Y_COUNT                0xFFC00E98      /* MemDMA0 Stream 1 Destination Y Count Register */
-#define MDMA0_D1_Y_MODIFY               0xFFC00E9C      /* MemDMA0 Stream 1 Destination Y Modify Register */
-#define MDMA0_D1_CURR_DESC_PTR  0xFFC00EA0      /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA0_D1_CURR_ADDR              0xFFC00EA4      /* MemDMA0 Stream 1 Destination Current Address Register */
-#define MDMA0_D1_IRQ_STATUS             0xFFC00EA8      /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
-#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC      /* MemDMA0 Stream 1 Destination Peripheral Map Register */
-#define MDMA0_D1_CURR_X_COUNT   0xFFC00EB0      /* MemDMA0 Stream 1 Destination Current X Count Register */
-#define MDMA0_D1_CURR_Y_COUNT   0xFFC00EB8      /* MemDMA0 Stream 1 Destination Current Y Count Register */
-
-#define MDMA0_S1_NEXT_DESC_PTR  0xFFC00EC0      /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA0_S1_START_ADDR             0xFFC00EC4      /* MemDMA0 Stream 1 Source Start Address Register */
-#define MDMA0_S1_CONFIG                 0xFFC00EC8      /* MemDMA0 Stream 1 Source Configuration Register */
-#define MDMA0_S1_X_COUNT                0xFFC00ED0      /* MemDMA0 Stream 1 Source X Count Register */
-#define MDMA0_S1_X_MODIFY               0xFFC00ED4      /* MemDMA0 Stream 1 Source X Modify Register */
-#define MDMA0_S1_Y_COUNT                0xFFC00ED8      /* MemDMA0 Stream 1 Source Y Count Register */
-#define MDMA0_S1_Y_MODIFY               0xFFC00EDC      /* MemDMA0 Stream 1 Source Y Modify Register */
-#define MDMA0_S1_CURR_DESC_PTR  0xFFC00EE0      /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA0_S1_CURR_ADDR              0xFFC00EE4      /* MemDMA0 Stream 1 Source Current Address Register */
-#define MDMA0_S1_IRQ_STATUS             0xFFC00EE8      /* MemDMA0 Stream 1 Source Interrupt/Status Register */
-#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC      /* MemDMA0 Stream 1 Source Peripheral Map Register */
-#define MDMA0_S1_CURR_X_COUNT   0xFFC00EF0      /* MemDMA0 Stream 1 Source Current X Count Register */
-#define MDMA0_S1_CURR_Y_COUNT   0xFFC00EF8      /* MemDMA0 Stream 1 Source Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR MDMA0_D0_NEXT_DESC_PTR
-#define MDMA_D0_START_ADDR MDMA0_D0_START_ADDR
-#define MDMA_D0_CONFIG MDMA0_D0_CONFIG
-#define MDMA_D0_X_COUNT MDMA0_D0_X_COUNT
-#define MDMA_D0_X_MODIFY MDMA0_D0_X_MODIFY
-#define MDMA_D0_Y_COUNT MDMA0_D0_Y_COUNT
-#define MDMA_D0_Y_MODIFY MDMA0_D0_Y_MODIFY
-#define MDMA_D0_CURR_DESC_PTR MDMA0_D0_CURR_DESC_PTR
-#define MDMA_D0_CURR_ADDR MDMA0_D0_CURR_ADDR
-#define MDMA_D0_IRQ_STATUS MDMA0_D0_IRQ_STATUS
-#define MDMA_D0_PERIPHERAL_MAP MDMA0_D0_PERIPHERAL_MAP
-#define MDMA_D0_CURR_X_COUNT MDMA0_D0_CURR_X_COUNT
-#define MDMA_D0_CURR_Y_COUNT MDMA0_D0_CURR_Y_COUNT
-
-#define MDMA_S0_NEXT_DESC_PTR MDMA0_S0_NEXT_DESC_PTR
-#define MDMA_S0_START_ADDR MDMA0_S0_START_ADDR
-#define MDMA_S0_CONFIG MDMA0_S0_CONFIG
-#define MDMA_S0_X_COUNT MDMA0_S0_X_COUNT
-#define MDMA_S0_X_MODIFY MDMA0_S0_X_MODIFY
-#define MDMA_S0_Y_COUNT MDMA0_S0_Y_COUNT
-#define MDMA_S0_Y_MODIFY MDMA0_S0_Y_MODIFY
-#define MDMA_S0_CURR_DESC_PTR MDMA0_S0_CURR_DESC_PTR
-#define MDMA_S0_CURR_ADDR MDMA0_S0_CURR_ADDR
-#define MDMA_S0_IRQ_STATUS MDMA0_S0_IRQ_STATUS
-#define MDMA_S0_PERIPHERAL_MAP MDMA0_S0_PERIPHERAL_MAP
-#define MDMA_S0_CURR_X_COUNT MDMA0_S0_CURR_X_COUNT
-#define MDMA_S0_CURR_Y_COUNT MDMA0_S0_CURR_Y_COUNT
-
-#define MDMA_D1_NEXT_DESC_PTR MDMA0_D1_NEXT_DESC_PTR
-#define MDMA_D1_START_ADDR MDMA0_D1_START_ADDR
-#define MDMA_D1_CONFIG MDMA0_D1_CONFIG
-#define MDMA_D1_X_COUNT MDMA0_D1_X_COUNT
-#define MDMA_D1_X_MODIFY MDMA0_D1_X_MODIFY
-#define MDMA_D1_Y_COUNT MDMA0_D1_Y_COUNT
-#define MDMA_D1_Y_MODIFY MDMA0_D1_Y_MODIFY
-#define MDMA_D1_CURR_DESC_PTR MDMA0_D1_CURR_DESC_PTR
-#define MDMA_D1_CURR_ADDR MDMA0_D1_CURR_ADDR
-#define MDMA_D1_IRQ_STATUS MDMA0_D1_IRQ_STATUS
-#define MDMA_D1_PERIPHERAL_MAP MDMA0_D1_PERIPHERAL_MAP
-#define MDMA_D1_CURR_X_COUNT MDMA0_D1_CURR_X_COUNT
-#define MDMA_D1_CURR_Y_COUNT MDMA0_D1_CURR_Y_COUNT
-
-#define MDMA_S1_NEXT_DESC_PTR MDMA0_S1_NEXT_DESC_PTR
-#define MDMA_S1_START_ADDR MDMA0_S1_START_ADDR
-#define MDMA_S1_CONFIG MDMA0_S1_CONFIG
-#define MDMA_S1_X_COUNT MDMA0_S1_X_COUNT
-#define MDMA_S1_X_MODIFY MDMA0_S1_X_MODIFY
-#define MDMA_S1_Y_COUNT MDMA0_S1_Y_COUNT
-#define MDMA_S1_Y_MODIFY MDMA0_S1_Y_MODIFY
-#define MDMA_S1_CURR_DESC_PTR MDMA0_S1_CURR_DESC_PTR
-#define MDMA_S1_CURR_ADDR MDMA0_S1_CURR_ADDR
-#define MDMA_S1_IRQ_STATUS MDMA0_S1_IRQ_STATUS
-#define MDMA_S1_PERIPHERAL_MAP MDMA0_S1_PERIPHERAL_MAP
-#define MDMA_S1_CURR_X_COUNT MDMA0_S1_CURR_X_COUNT
-#define MDMA_S1_CURR_Y_COUNT MDMA0_S1_CURR_Y_COUNT
-
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF)                        */
-#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register */
-#define TWI0_CONTROL            0xFFC01404      /* TWI0 Master Internal Time Reference Register */
-#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414      /* Master Mode Control Register */
-#define TWI0_MASTER_STAT        0xFFC01418      /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR        0xFFC0141C      /* Master Mode Address Register */
-#define TWI0_INT_STAT           0xFFC01420      /* TWI0 Master Interrupt Register */
-#define TWI0_INT_MASK           0xFFC01424      /* TWI0 Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register */
-#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register */
-#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register */
-
-#define TWI0_REGBASE            TWI0_CLKDIV
-
-/* the following are for backwards compatibility */
-#define TWI0_PRESCALE    TWI0_CONTROL
-#define TWI0_INT_SRC     TWI0_INT_STAT
-#define TWI0_INT_ENABLE  TWI0_INT_MASK
-
-
-/* General-Purpose Ports  (0xFFC01500 - 0xFFC015FF)      */
-
-/* GPIO Port C Register Names */
-#define PORTCIO_FER                     0xFFC01500      /* GPIO Pin Port C Configuration Register */
-#define PORTCIO                         0xFFC01510      /* GPIO Pin Port C Data Register */
-#define PORTCIO_CLEAR                   0xFFC01520      /* Clear GPIO Pin Port C Register */
-#define PORTCIO_SET                     0xFFC01530      /* Set GPIO Pin Port C Register */
-#define PORTCIO_TOGGLE                  0xFFC01540      /* Toggle GPIO Pin Port C Register */
-#define PORTCIO_DIR                     0xFFC01550      /* GPIO Pin Port C Direction Register */
-#define PORTCIO_INEN                    0xFFC01560      /* GPIO Pin Port C Input Enable Register */
-
-/* GPIO Port D Register Names */
-#define PORTDIO_FER                     0xFFC01504      /* GPIO Pin Port D Configuration Register */
-#define PORTDIO                         0xFFC01514      /* GPIO Pin Port D Data Register */
-#define PORTDIO_CLEAR                   0xFFC01524      /* Clear GPIO Pin Port D Register */
-#define PORTDIO_SET                     0xFFC01534      /* Set GPIO Pin Port D Register */
-#define PORTDIO_TOGGLE                  0xFFC01544      /* Toggle GPIO Pin Port D Register */
-#define PORTDIO_DIR                     0xFFC01554      /* GPIO Pin Port D Direction Register */
-#define PORTDIO_INEN                    0xFFC01564      /* GPIO Pin Port D Input Enable Register */
-
-/* GPIO Port E Register Names */
-#define PORTEIO_FER                     0xFFC01508      /* GPIO Pin Port E Configuration Register */
-#define PORTEIO                         0xFFC01518      /* GPIO Pin Port E Data Register */
-#define PORTEIO_CLEAR                   0xFFC01528      /* Clear GPIO Pin Port E Register */
-#define PORTEIO_SET                     0xFFC01538      /* Set GPIO Pin Port E Register */
-#define PORTEIO_TOGGLE                  0xFFC01548      /* Toggle GPIO Pin Port E Register */
-#define PORTEIO_DIR                     0xFFC01558      /* GPIO Pin Port E Direction Register */
-#define PORTEIO_INEN                    0xFFC01568      /* GPIO Pin Port E Input Enable Register */
-
-/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
-
-#define DMAC1_TC_PER                    0xFFC01B0C      /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT                    0xFFC01B10      /* DMA Controller 1 Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA1_TCPER                      DMAC1_TC_PER
-#define DMA1_TCCNT                      DMAC1_TC_CNT
-
-
-/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF)                                                    */
-#define DMA8_NEXT_DESC_PTR              0xFFC01C00      /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                 0xFFC01C04      /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                             0xFFC01C08      /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                    0xFFC01C10      /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                   0xFFC01C14      /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                    0xFFC01C18      /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                   0xFFC01C1C      /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR              0xFFC01C20      /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                  0xFFC01C24      /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                 0xFFC01C28      /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP             0xFFC01C2C      /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT               0xFFC01C30      /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT               0xFFC01C38      /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR              0xFFC01C40      /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                 0xFFC01C44      /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                             0xFFC01C48      /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                    0xFFC01C50      /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                   0xFFC01C54      /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                    0xFFC01C58      /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                   0xFFC01C5C      /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR              0xFFC01C60      /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                  0xFFC01C64      /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                 0xFFC01C68      /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP             0xFFC01C6C      /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT               0xFFC01C70      /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT               0xFFC01C78      /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR             0xFFC01C80      /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR                0xFFC01C84      /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                    0xFFC01C88      /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                   0xFFC01C90      /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                  0xFFC01C94      /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                   0xFFC01C98      /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                  0xFFC01C9C      /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR             0xFFC01CA0      /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                 0xFFC01CA4      /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS                0xFFC01CA8      /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP    0xFFC01CAC      /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT              0xFFC01CB0      /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT              0xFFC01CB8      /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR             0xFFC01CC0      /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR                0xFFC01CC4      /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                    0xFFC01CC8      /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                   0xFFC01CD0      /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                  0xFFC01CD4      /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                   0xFFC01CD8      /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                  0xFFC01CDC      /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR             0xFFC01CE0      /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                 0xFFC01CE4      /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS                0xFFC01CE8      /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP    0xFFC01CEC      /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT              0xFFC01CF0      /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT              0xFFC01CF8      /* DMA Channel 11 Current Y Count Register */
-
-#define DMA12_NEXT_DESC_PTR             0xFFC01D00      /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR                0xFFC01D04      /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG                    0xFFC01D08      /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT                   0xFFC01D10      /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY                  0xFFC01D14      /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT                   0xFFC01D18      /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY                  0xFFC01D1C      /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR             0xFFC01D20      /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR                 0xFFC01D24      /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS                0xFFC01D28      /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP    0xFFC01D2C      /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT              0xFFC01D30      /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT              0xFFC01D38      /* DMA Channel 12 Current Y Count Register */
-
-#define DMA13_NEXT_DESC_PTR             0xFFC01D40      /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR                0xFFC01D44      /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG                    0xFFC01D48      /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT                   0xFFC01D50      /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY                  0xFFC01D54      /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT                   0xFFC01D58      /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY                  0xFFC01D5C      /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR             0xFFC01D60      /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR                 0xFFC01D64      /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS                0xFFC01D68      /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP    0xFFC01D6C      /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT              0xFFC01D70      /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT              0xFFC01D78      /* DMA Channel 13 Current Y Count Register */
-
-#define DMA14_NEXT_DESC_PTR             0xFFC01D80      /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR                0xFFC01D84      /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG                    0xFFC01D88      /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT                   0xFFC01D90      /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY                  0xFFC01D94      /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT                   0xFFC01D98      /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY                  0xFFC01D9C      /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR             0xFFC01DA0      /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR                 0xFFC01DA4      /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS                0xFFC01DA8      /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP    0xFFC01DAC      /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT              0xFFC01DB0      /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT              0xFFC01DB8      /* DMA Channel 14 Current Y Count Register */
-
-#define DMA15_NEXT_DESC_PTR             0xFFC01DC0      /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR                0xFFC01DC4      /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG                    0xFFC01DC8      /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT                   0xFFC01DD0      /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY                  0xFFC01DD4      /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT                   0xFFC01DD8      /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY                  0xFFC01DDC      /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR             0xFFC01DE0      /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR                 0xFFC01DE4      /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS                0xFFC01DE8      /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP    0xFFC01DEC      /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT              0xFFC01DF0      /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT              0xFFC01DF8      /* DMA Channel 15 Current Y Count Register */
-
-#define DMA16_NEXT_DESC_PTR             0xFFC01E00      /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR                0xFFC01E04      /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG                    0xFFC01E08      /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT                   0xFFC01E10      /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY                  0xFFC01E14      /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT                   0xFFC01E18      /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY                  0xFFC01E1C      /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR             0xFFC01E20      /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR                 0xFFC01E24      /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS                0xFFC01E28      /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP    0xFFC01E2C      /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT              0xFFC01E30      /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT              0xFFC01E38      /* DMA Channel 16 Current Y Count Register */
-
-#define DMA17_NEXT_DESC_PTR             0xFFC01E40      /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR                0xFFC01E44      /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG                    0xFFC01E48      /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT                   0xFFC01E50      /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY                  0xFFC01E54      /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT                   0xFFC01E58      /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY                  0xFFC01E5C      /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR             0xFFC01E60      /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR                 0xFFC01E64      /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS                0xFFC01E68      /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP    0xFFC01E6C      /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT              0xFFC01E70      /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT              0xFFC01E78      /* DMA Channel 17 Current Y Count Register */
-
-#define DMA18_NEXT_DESC_PTR             0xFFC01E80      /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR                0xFFC01E84      /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG                    0xFFC01E88      /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT                   0xFFC01E90      /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY                  0xFFC01E94      /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT                   0xFFC01E98      /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY                  0xFFC01E9C      /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR             0xFFC01EA0      /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR                 0xFFC01EA4      /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS                0xFFC01EA8      /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP    0xFFC01EAC      /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT              0xFFC01EB0      /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT              0xFFC01EB8      /* DMA Channel 18 Current Y Count Register */
-
-#define DMA19_NEXT_DESC_PTR             0xFFC01EC0      /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR                0xFFC01EC4      /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG                    0xFFC01EC8      /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT                   0xFFC01ED0      /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY                  0xFFC01ED4      /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT                   0xFFC01ED8      /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY                  0xFFC01EDC      /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR             0xFFC01EE0      /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR                 0xFFC01EE4      /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS                0xFFC01EE8      /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP    0xFFC01EEC      /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT              0xFFC01EF0      /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT              0xFFC01EF8      /* DMA Channel 19 Current Y Count Register */
-
-#define MDMA1_D0_NEXT_DESC_PTR  0xFFC01F00      /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA1_D0_START_ADDR             0xFFC01F04      /* MemDMA1 Stream 0 Destination Start Address Register */
-#define MDMA1_D0_CONFIG                 0xFFC01F08      /* MemDMA1 Stream 0 Destination Configuration Register */
-#define MDMA1_D0_X_COUNT                0xFFC01F10      /* MemDMA1 Stream 0 Destination X Count Register */
-#define MDMA1_D0_X_MODIFY               0xFFC01F14      /* MemDMA1 Stream 0 Destination X Modify Register */
-#define MDMA1_D0_Y_COUNT                0xFFC01F18      /* MemDMA1 Stream 0 Destination Y Count Register */
-#define MDMA1_D0_Y_MODIFY               0xFFC01F1C      /* MemDMA1 Stream 0 Destination Y Modify Register */
-#define MDMA1_D0_CURR_DESC_PTR  0xFFC01F20      /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA1_D0_CURR_ADDR              0xFFC01F24      /* MemDMA1 Stream 0 Destination Current Address Register */
-#define MDMA1_D0_IRQ_STATUS             0xFFC01F28      /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
-#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C      /* MemDMA1 Stream 0 Destination Peripheral Map Register */
-#define MDMA1_D0_CURR_X_COUNT   0xFFC01F30      /* MemDMA1 Stream 0 Destination Current X Count Register */
-#define MDMA1_D0_CURR_Y_COUNT   0xFFC01F38      /* MemDMA1 Stream 0 Destination Current Y Count Register */
-
-#define MDMA1_S0_NEXT_DESC_PTR  0xFFC01F40      /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA1_S0_START_ADDR             0xFFC01F44      /* MemDMA1 Stream 0 Source Start Address Register */
-#define MDMA1_S0_CONFIG                 0xFFC01F48      /* MemDMA1 Stream 0 Source Configuration Register */
-#define MDMA1_S0_X_COUNT                0xFFC01F50      /* MemDMA1 Stream 0 Source X Count Register */
-#define MDMA1_S0_X_MODIFY               0xFFC01F54      /* MemDMA1 Stream 0 Source X Modify Register */
-#define MDMA1_S0_Y_COUNT                0xFFC01F58      /* MemDMA1 Stream 0 Source Y Count Register */
-#define MDMA1_S0_Y_MODIFY               0xFFC01F5C      /* MemDMA1 Stream 0 Source Y Modify Register */
-#define MDMA1_S0_CURR_DESC_PTR  0xFFC01F60      /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA1_S0_CURR_ADDR              0xFFC01F64      /* MemDMA1 Stream 0 Source Current Address Register */
-#define MDMA1_S0_IRQ_STATUS             0xFFC01F68      /* MemDMA1 Stream 0 Source Interrupt/Status Register */
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C      /* MemDMA1 Stream 0 Source Peripheral Map Register */
-#define MDMA1_S0_CURR_X_COUNT   0xFFC01F70      /* MemDMA1 Stream 0 Source Current X Count Register */
-#define MDMA1_S0_CURR_Y_COUNT   0xFFC01F78      /* MemDMA1 Stream 0 Source Current Y Count Register */
-
-#define MDMA1_D1_NEXT_DESC_PTR  0xFFC01F80      /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA1_D1_START_ADDR             0xFFC01F84      /* MemDMA1 Stream 1 Destination Start Address Register */
-#define MDMA1_D1_CONFIG                 0xFFC01F88      /* MemDMA1 Stream 1 Destination Configuration Register */
-#define MDMA1_D1_X_COUNT                0xFFC01F90      /* MemDMA1 Stream 1 Destination X Count Register */
-#define MDMA1_D1_X_MODIFY               0xFFC01F94      /* MemDMA1 Stream 1 Destination X Modify Register */
-#define MDMA1_D1_Y_COUNT                0xFFC01F98      /* MemDMA1 Stream 1 Destination Y Count Register */
-#define MDMA1_D1_Y_MODIFY               0xFFC01F9C      /* MemDMA1 Stream 1 Destination Y Modify Register */
-#define MDMA1_D1_CURR_DESC_PTR  0xFFC01FA0      /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA1_D1_CURR_ADDR              0xFFC01FA4      /* MemDMA1 Stream 1 Destination Current Address Register */
-#define MDMA1_D1_IRQ_STATUS             0xFFC01FA8      /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC      /* MemDMA1 Stream 1 Destination Peripheral Map Register */
-#define MDMA1_D1_CURR_X_COUNT   0xFFC01FB0      /* MemDMA1 Stream 1 Destination Current X Count Register */
-#define MDMA1_D1_CURR_Y_COUNT   0xFFC01FB8      /* MemDMA1 Stream 1 Destination Current Y Count Register */
-
-#define MDMA1_S1_NEXT_DESC_PTR  0xFFC01FC0      /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA1_S1_START_ADDR             0xFFC01FC4      /* MemDMA1 Stream 1 Source Start Address Register */
-#define MDMA1_S1_CONFIG                 0xFFC01FC8      /* MemDMA1 Stream 1 Source Configuration Register */
-#define MDMA1_S1_X_COUNT                0xFFC01FD0      /* MemDMA1 Stream 1 Source X Count Register */
-#define MDMA1_S1_X_MODIFY               0xFFC01FD4      /* MemDMA1 Stream 1 Source X Modify Register */
-#define MDMA1_S1_Y_COUNT                0xFFC01FD8      /* MemDMA1 Stream 1 Source Y Count Register */
-#define MDMA1_S1_Y_MODIFY               0xFFC01FDC      /* MemDMA1 Stream 1 Source Y Modify Register */
-#define MDMA1_S1_CURR_DESC_PTR  0xFFC01FE0      /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA1_S1_CURR_ADDR              0xFFC01FE4      /* MemDMA1 Stream 1 Source Current Address Register */
-#define MDMA1_S1_IRQ_STATUS             0xFFC01FE8      /* MemDMA1 Stream 1 Source Interrupt/Status Register */
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC      /* MemDMA1 Stream 1 Source Peripheral Map Register */
-#define MDMA1_S1_CURR_X_COUNT   0xFFC01FF0      /* MemDMA1 Stream 1 Source Current X Count Register */
-#define MDMA1_S1_CURR_Y_COUNT   0xFFC01FF8      /* MemDMA1 Stream 1 Source Current Y Count Register */
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)        */
-#define UART1_THR                       0xFFC02000      /* Transmit Holding register */
-#define UART1_RBR                       0xFFC02000      /* Receive Buffer register */
-#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte) */
-#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register */
-#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte) */
-#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register */
-#define UART1_LCR                       0xFFC0200C      /* Line Control Register */
-#define UART1_MCR                       0xFFC02010      /* Modem Control Register */
-#define UART1_LSR                       0xFFC02014      /* Line Status Register */
-#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register */
-#define UART1_GCTL                      0xFFC02024      /* Global Control Register */
-
-
-/* UART2 Controller             (0xFFC02100 - 0xFFC021FF)        */
-#define UART2_THR                       0xFFC02100      /* Transmit Holding register */
-#define UART2_RBR                       0xFFC02100      /* Receive Buffer register */
-#define UART2_DLL                       0xFFC02100      /* Divisor Latch (Low-Byte) */
-#define UART2_IER                       0xFFC02104      /* Interrupt Enable Register */
-#define UART2_DLH                       0xFFC02104      /* Divisor Latch (High-Byte) */
-#define UART2_IIR                       0xFFC02108      /* Interrupt Identification Register */
-#define UART2_LCR                       0xFFC0210C      /* Line Control Register */
-#define UART2_MCR                       0xFFC02110      /* Modem Control Register */
-#define UART2_LSR                       0xFFC02114      /* Line Status Register */
-#define UART2_SCR                       0xFFC0211C      /* SCR Scratch Register */
-#define UART2_GCTL                      0xFFC02124      /* Global Control Register */
-
-
-/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF)                        */
-#define TWI1_CLKDIV                     0xFFC02200      /* Serial Clock Divider Register */
-#define TWI1_CONTROL            0xFFC02204      /* TWI1 Master Internal Time Reference Register */
-#define TWI1_SLAVE_CTL          0xFFC02208      /* Slave Mode Control Register */
-#define TWI1_SLAVE_STAT         0xFFC0220C      /* Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR         0xFFC02210      /* Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214      /* Master Mode Control Register */
-#define TWI1_MASTER_STAT        0xFFC02218      /* Master Mode Status Register */
-#define TWI1_MASTER_ADDR        0xFFC0221C      /* Master Mode Address Register */
-#define TWI1_INT_STAT           0xFFC02220      /* TWI1 Master Interrupt Register */
-#define TWI1_INT_MASK           0xFFC02224      /* TWI1 Master Interrupt Mask Register */
-#define TWI1_FIFO_CTL           0xFFC02228      /* FIFO Control Register */
-#define TWI1_FIFO_STAT          0xFFC0222C      /* FIFO Status Register */
-#define TWI1_XMT_DATA8          0xFFC02280      /* FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16         0xFFC02284      /* FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8          0xFFC02288      /* FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16         0xFFC0228C      /* FIFO Receive Data Double Byte Register */
-#define TWI1_REGBASE            TWI1_CLKDIV
-
-
-/* the following are for backwards compatibility */
-#define TWI1_PRESCALE     TWI1_CONTROL
-#define TWI1_INT_SRC      TWI1_INT_STAT
-#define TWI1_INT_ENABLE   TWI1_INT_MASK
-
-
-/* SPI1 Controller              (0xFFC02300 - 0xFFC023FF)        */
-#define SPI1_CTL                        0xFFC02300  /* SPI1 Control Register */
-#define SPI1_FLG                        0xFFC02304  /* SPI1 Flag register */
-#define SPI1_STAT                       0xFFC02308  /* SPI1 Status register */
-#define SPI1_TDBR                       0xFFC0230C  /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR                       0xFFC02310  /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD                       0xFFC02314  /* SPI1 Baud rate Register */
-#define SPI1_SHADOW                     0xFFC02318  /* SPI1_RDBR Shadow Register */
-#define SPI1_REGBASE                    SPI1_CTL
-
-/* SPI2 Controller              (0xFFC02400 - 0xFFC024FF)        */
-#define SPI2_CTL                        0xFFC02400  /* SPI2 Control Register */
-#define SPI2_FLG                        0xFFC02404  /* SPI2 Flag register */
-#define SPI2_STAT                       0xFFC02408  /* SPI2 Status register */
-#define SPI2_TDBR                       0xFFC0240C  /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR                       0xFFC02410  /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD                       0xFFC02414  /* SPI2 Baud rate Register */
-#define SPI2_SHADOW                     0xFFC02418  /* SPI2_RDBR Shadow Register */
-#define SPI2_REGBASE                    SPI2_CTL
-
-/* SPORT2 Controller            (0xFFC02500 - 0xFFC025FF)                        */
-#define SPORT2_TCR1                     0xFFC02500      /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2                     0xFFC02504      /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV          0xFFC02508      /* SPORT2 Transmit Clock Divider */
-#define SPORT2_TFSDIV           0xFFC0250C      /* SPORT2 Transmit Frame Sync Divider */
-#define SPORT2_TX                       0xFFC02510      /* SPORT2 TX Data Register */
-#define SPORT2_RX                       0xFFC02518      /* SPORT2 RX Data Register */
-#define SPORT2_RCR1                     0xFFC02520      /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_RCR2                     0xFFC02524      /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_RCLKDIV          0xFFC02528      /* SPORT2 Receive Clock Divider */
-#define SPORT2_RFSDIV           0xFFC0252C      /* SPORT2 Receive Frame Sync Divider */
-#define SPORT2_STAT                     0xFFC02530      /* SPORT2 Status Register */
-#define SPORT2_CHNL                     0xFFC02534      /* SPORT2 Current Channel Register */
-#define SPORT2_MCMC1            0xFFC02538      /* SPORT2 Multi-Channel Configuration Register 1 */
-#define SPORT2_MCMC2            0xFFC0253C      /* SPORT2 Multi-Channel Configuration Register 2 */
-#define SPORT2_MTCS0            0xFFC02540      /* SPORT2 Multi-Channel Transmit Select Register 0 */
-#define SPORT2_MTCS1            0xFFC02544      /* SPORT2 Multi-Channel Transmit Select Register 1 */
-#define SPORT2_MTCS2            0xFFC02548      /* SPORT2 Multi-Channel Transmit Select Register 2 */
-#define SPORT2_MTCS3            0xFFC0254C      /* SPORT2 Multi-Channel Transmit Select Register 3 */
-#define SPORT2_MRCS0            0xFFC02550      /* SPORT2 Multi-Channel Receive Select Register 0 */
-#define SPORT2_MRCS1            0xFFC02554      /* SPORT2 Multi-Channel Receive Select Register 1 */
-#define SPORT2_MRCS2            0xFFC02558      /* SPORT2 Multi-Channel Receive Select Register 2 */
-#define SPORT2_MRCS3            0xFFC0255C      /* SPORT2 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT3 Controller            (0xFFC02600 - 0xFFC026FF)                        */
-#define SPORT3_TCR1                     0xFFC02600      /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2                     0xFFC02604      /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV          0xFFC02608      /* SPORT3 Transmit Clock Divider */
-#define SPORT3_TFSDIV           0xFFC0260C      /* SPORT3 Transmit Frame Sync Divider */
-#define SPORT3_TX                       0xFFC02610      /* SPORT3 TX Data Register */
-#define SPORT3_RX                       0xFFC02618      /* SPORT3 RX Data Register */
-#define SPORT3_RCR1                     0xFFC02620      /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_RCR2                     0xFFC02624      /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_RCLKDIV          0xFFC02628      /* SPORT3 Receive Clock Divider */
-#define SPORT3_RFSDIV           0xFFC0262C      /* SPORT3 Receive Frame Sync Divider */
-#define SPORT3_STAT                     0xFFC02630      /* SPORT3 Status Register */
-#define SPORT3_CHNL                     0xFFC02634      /* SPORT3 Current Channel Register */
-#define SPORT3_MCMC1            0xFFC02638      /* SPORT3 Multi-Channel Configuration Register 1 */
-#define SPORT3_MCMC2            0xFFC0263C      /* SPORT3 Multi-Channel Configuration Register 2 */
-#define SPORT3_MTCS0            0xFFC02640      /* SPORT3 Multi-Channel Transmit Select Register 0 */
-#define SPORT3_MTCS1            0xFFC02644      /* SPORT3 Multi-Channel Transmit Select Register 1 */
-#define SPORT3_MTCS2            0xFFC02648      /* SPORT3 Multi-Channel Transmit Select Register 2 */
-#define SPORT3_MTCS3            0xFFC0264C      /* SPORT3 Multi-Channel Transmit Select Register 3 */
-#define SPORT3_MRCS0            0xFFC02650      /* SPORT3 Multi-Channel Receive Select Register 0 */
-#define SPORT3_MRCS1            0xFFC02654      /* SPORT3 Multi-Channel Receive Select Register 1 */
-#define SPORT3_MRCS2            0xFFC02658      /* SPORT3 Multi-Channel Receive Select Register 2 */
-#define SPORT3_MRCS3            0xFFC0265C      /* SPORT3 Multi-Channel Receive Select Register 3 */
-
+#include "defBF538.h"
 
 /* Media Transceiver (MXVR)   (0xFFC02700 - 0xFFC028FF) */
 
@@ -995,1249 +149,4 @@
 #define MXVR_BLOCK_CNT        0xFFC028C0  /* MXVR Block Counter */
 #define MXVR_PLL_CTL_2        0xFFC028C4  /* MXVR Phase Lock Loop Control Register 2 */
 
-
-/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                */
-/* For Mailboxes 0-15                                                                                    */
-#define CAN_MC1                         0xFFC02A00      /* Mailbox config reg 1  */
-#define CAN_MD1                         0xFFC02A04      /* Mailbox direction reg 1 */
-#define CAN_TRS1                        0xFFC02A08      /* Transmit Request Set reg 1 */
-#define CAN_TRR1                        0xFFC02A0C      /* Transmit Request Reset reg 1 */
-#define CAN_TA1                         0xFFC02A10      /* Transmit Acknowledge reg 1 */
-#define CAN_AA1                         0xFFC02A14      /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1                        0xFFC02A18      /* Receive Message Pending reg 1 */
-#define CAN_RML1                        0xFFC02A1C      /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1                      0xFFC02A20      /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1                      0xFFC02A24      /* Mailbox Receive  Interrupt Flag reg 1 */
-#define CAN_MBIM1                       0xFFC02A28      /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1                        0xFFC02A2C      /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1                       0xFFC02A30      /* Overwrite Protection Single Shot Xmission reg 1 */
-
-/* For Mailboxes 16-31                                                                                   */
-#define CAN_MC2                         0xFFC02A40      /* Mailbox config reg 2  */
-#define CAN_MD2                         0xFFC02A44      /* Mailbox direction reg 2 */
-#define CAN_TRS2                        0xFFC02A48      /* Transmit Request Set reg 2 */
-#define CAN_TRR2                        0xFFC02A4C      /* Transmit Request Reset reg 2 */
-#define CAN_TA2                         0xFFC02A50      /* Transmit Acknowledge reg 2 */
-#define CAN_AA2                         0xFFC02A54      /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2                        0xFFC02A58      /* Receive Message Pending reg 2 */
-#define CAN_RML2                        0xFFC02A5C      /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2                      0xFFC02A60      /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2                      0xFFC02A64      /* Mailbox Receive  Interrupt Flag reg 2 */
-#define CAN_MBIM2                       0xFFC02A68      /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2                        0xFFC02A6C      /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2                       0xFFC02A70      /* Overwrite Protection Single Shot Xmission reg 2 */
-
-#define CAN_CLOCK                       0xFFC02A80      /* Bit Timing Configuration register 0 */
-#define CAN_TIMING                      0xFFC02A84      /* Bit Timing Configuration register 1 */
-
-#define CAN_DEBUG                       0xFFC02A88      /* Debug Register                */
-/* the following is for backwards compatibility */
-#define CAN_CNF          CAN_DEBUG
-
-#define CAN_STATUS                      0xFFC02A8C      /* Global Status Register */
-#define CAN_CEC                         0xFFC02A90      /* Error Counter Register */
-#define CAN_GIS                         0xFFC02A94      /* Global Interrupt Status Register */
-#define CAN_GIM                         0xFFC02A98      /* Global Interrupt Mask Register */
-#define CAN_GIF                         0xFFC02A9C      /* Global Interrupt Flag Register */
-#define CAN_CONTROL                     0xFFC02AA0      /* Master Control Register */
-#define CAN_INTR                        0xFFC02AA4      /* Interrupt Pending Register */
-#define CAN_MBTD                        0xFFC02AAC      /* Mailbox Temporary Disable Feature */
-#define CAN_EWR                         0xFFC02AB0      /* Programmable Warning Level */
-#define CAN_ESR                         0xFFC02AB4      /* Error Status Register */
-#define CAN_UCCNT                       0xFFC02AC4      /* Universal Counter     */
-#define CAN_UCRC                        0xFFC02AC8      /* Universal Counter Reload/Capture Register */
-#define CAN_UCCNF                       0xFFC02ACC      /* Universal Counter Configuration Register */
-
-/* Mailbox Acceptance Masks                                      */
-#define CAN_AM00L                       0xFFC02B00      /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H                       0xFFC02B04      /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L                       0xFFC02B08      /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H                       0xFFC02B0C      /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L                       0xFFC02B10      /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H                       0xFFC02B14      /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L                       0xFFC02B18      /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H                       0xFFC02B1C      /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L                       0xFFC02B20      /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H                       0xFFC02B24      /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L                       0xFFC02B28      /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H                       0xFFC02B2C      /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L                       0xFFC02B30      /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H                       0xFFC02B34      /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L                       0xFFC02B38      /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H                       0xFFC02B3C      /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L                       0xFFC02B40      /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H                       0xFFC02B44      /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L                       0xFFC02B48      /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H                       0xFFC02B4C      /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L                       0xFFC02B50      /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H                       0xFFC02B54      /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L                       0xFFC02B58      /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H                       0xFFC02B5C      /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L                       0xFFC02B60      /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H                       0xFFC02B64      /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L                       0xFFC02B68      /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H                       0xFFC02B6C      /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L                       0xFFC02B70      /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H                       0xFFC02B74      /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L                       0xFFC02B78      /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H                       0xFFC02B7C      /* Mailbox 15 High Acceptance Mask */
-
-#define CAN_AM16L                       0xFFC02B80      /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H                       0xFFC02B84      /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L                       0xFFC02B88      /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H                       0xFFC02B8C      /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L                       0xFFC02B90      /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H                       0xFFC02B94      /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L                       0xFFC02B98      /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H                       0xFFC02B9C      /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L                       0xFFC02BA0      /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H                       0xFFC02BA4      /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L                       0xFFC02BA8      /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H                       0xFFC02BAC      /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L                       0xFFC02BB0      /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H                       0xFFC02BB4      /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L                       0xFFC02BB8      /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H                       0xFFC02BBC      /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L                       0xFFC02BC0      /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H                       0xFFC02BC4      /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L                       0xFFC02BC8      /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H                       0xFFC02BCC      /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L                       0xFFC02BD0      /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H                       0xFFC02BD4      /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L                       0xFFC02BD8      /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H                       0xFFC02BDC      /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L                       0xFFC02BE0      /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H                       0xFFC02BE4      /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L                       0xFFC02BE8      /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H                       0xFFC02BEC      /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L                       0xFFC02BF0      /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H                       0xFFC02BF4      /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L                       0xFFC02BF8      /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H                       0xFFC02BFC      /* Mailbox 31 High Acceptance Mask */
-
-/* CAN Acceptance Mask Macros */
-#define CAN_AM_L(x)                     (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x)                     (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers                                                                     */
-#define CAN_MB00_DATA0          0xFFC02C00      /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1          0xFFC02C04      /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2          0xFFC02C08      /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3          0xFFC02C0C      /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH         0xFFC02C10      /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP      0xFFC02C14      /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0            0xFFC02C18      /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1            0xFFC02C1C      /* Mailbox 0 Identifier High Register */
-
-#define CAN_MB01_DATA0          0xFFC02C20      /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1          0xFFC02C24      /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2          0xFFC02C28      /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3          0xFFC02C2C      /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH         0xFFC02C30      /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP      0xFFC02C34      /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0            0xFFC02C38      /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1            0xFFC02C3C      /* Mailbox 1 Identifier High Register */
-
-#define CAN_MB02_DATA0          0xFFC02C40      /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1          0xFFC02C44      /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2          0xFFC02C48      /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3          0xFFC02C4C      /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH         0xFFC02C50      /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP      0xFFC02C54      /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0            0xFFC02C58      /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1            0xFFC02C5C      /* Mailbox 2 Identifier High Register */
-
-#define CAN_MB03_DATA0          0xFFC02C60      /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1          0xFFC02C64      /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2          0xFFC02C68      /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3          0xFFC02C6C      /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH         0xFFC02C70      /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP      0xFFC02C74      /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0            0xFFC02C78      /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1            0xFFC02C7C      /* Mailbox 3 Identifier High Register */
-
-#define CAN_MB04_DATA0          0xFFC02C80      /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1          0xFFC02C84      /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2          0xFFC02C88      /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3          0xFFC02C8C      /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH         0xFFC02C90      /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP      0xFFC02C94      /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0            0xFFC02C98      /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1            0xFFC02C9C      /* Mailbox 4 Identifier High Register */
-
-#define CAN_MB05_DATA0          0xFFC02CA0      /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1          0xFFC02CA4      /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2          0xFFC02CA8      /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3          0xFFC02CAC      /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH         0xFFC02CB0      /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP      0xFFC02CB4      /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0            0xFFC02CB8      /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1            0xFFC02CBC      /* Mailbox 5 Identifier High Register */
-
-#define CAN_MB06_DATA0          0xFFC02CC0      /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1          0xFFC02CC4      /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2          0xFFC02CC8      /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3          0xFFC02CCC      /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH         0xFFC02CD0      /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP      0xFFC02CD4      /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0            0xFFC02CD8      /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1            0xFFC02CDC      /* Mailbox 6 Identifier High Register */
-
-#define CAN_MB07_DATA0          0xFFC02CE0      /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1          0xFFC02CE4      /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2          0xFFC02CE8      /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3          0xFFC02CEC      /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH         0xFFC02CF0      /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP      0xFFC02CF4      /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0            0xFFC02CF8      /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1            0xFFC02CFC      /* Mailbox 7 Identifier High Register */
-
-#define CAN_MB08_DATA0          0xFFC02D00      /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1          0xFFC02D04      /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2          0xFFC02D08      /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3          0xFFC02D0C      /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH         0xFFC02D10      /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP      0xFFC02D14      /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0            0xFFC02D18      /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1            0xFFC02D1C      /* Mailbox 8 Identifier High Register */
-
-#define CAN_MB09_DATA0          0xFFC02D20      /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1          0xFFC02D24      /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2          0xFFC02D28      /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3          0xFFC02D2C      /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH         0xFFC02D30      /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP      0xFFC02D34      /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0            0xFFC02D38      /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1            0xFFC02D3C      /* Mailbox 9 Identifier High Register */
-
-#define CAN_MB10_DATA0          0xFFC02D40      /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1          0xFFC02D44      /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2          0xFFC02D48      /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3          0xFFC02D4C      /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH         0xFFC02D50      /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP      0xFFC02D54      /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0            0xFFC02D58      /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1            0xFFC02D5C      /* Mailbox 10 Identifier High Register */
-
-#define CAN_MB11_DATA0          0xFFC02D60      /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1          0xFFC02D64      /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2          0xFFC02D68      /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3          0xFFC02D6C      /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH         0xFFC02D70      /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP      0xFFC02D74      /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0            0xFFC02D78      /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1            0xFFC02D7C      /* Mailbox 11 Identifier High Register */
-
-#define CAN_MB12_DATA0          0xFFC02D80      /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1          0xFFC02D84      /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2          0xFFC02D88      /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3          0xFFC02D8C      /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH         0xFFC02D90      /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP      0xFFC02D94      /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0            0xFFC02D98      /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1            0xFFC02D9C      /* Mailbox 12 Identifier High Register */
-
-#define CAN_MB13_DATA0          0xFFC02DA0      /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1          0xFFC02DA4      /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2          0xFFC02DA8      /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3          0xFFC02DAC      /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH         0xFFC02DB0      /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP      0xFFC02DB4      /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0            0xFFC02DB8      /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1            0xFFC02DBC      /* Mailbox 13 Identifier High Register */
-
-#define CAN_MB14_DATA0          0xFFC02DC0      /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1          0xFFC02DC4      /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2          0xFFC02DC8      /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3          0xFFC02DCC      /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH         0xFFC02DD0      /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP      0xFFC02DD4      /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0            0xFFC02DD8      /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1            0xFFC02DDC      /* Mailbox 14 Identifier High Register */
-
-#define CAN_MB15_DATA0          0xFFC02DE0      /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1          0xFFC02DE4      /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2          0xFFC02DE8      /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3          0xFFC02DEC      /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH         0xFFC02DF0      /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP      0xFFC02DF4      /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0            0xFFC02DF8      /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1            0xFFC02DFC      /* Mailbox 15 Identifier High Register */
-
-#define CAN_MB16_DATA0          0xFFC02E00      /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1          0xFFC02E04      /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2          0xFFC02E08      /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3          0xFFC02E0C      /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH         0xFFC02E10      /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP      0xFFC02E14      /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0            0xFFC02E18      /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1            0xFFC02E1C      /* Mailbox 16 Identifier High Register */
-
-#define CAN_MB17_DATA0          0xFFC02E20      /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1          0xFFC02E24      /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2          0xFFC02E28      /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3          0xFFC02E2C      /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH         0xFFC02E30      /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP      0xFFC02E34      /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0            0xFFC02E38      /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1            0xFFC02E3C      /* Mailbox 17 Identifier High Register */
-
-#define CAN_MB18_DATA0          0xFFC02E40      /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1          0xFFC02E44      /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2          0xFFC02E48      /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3          0xFFC02E4C      /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH         0xFFC02E50      /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP      0xFFC02E54      /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0            0xFFC02E58      /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1            0xFFC02E5C      /* Mailbox 18 Identifier High Register */
-
-#define CAN_MB19_DATA0          0xFFC02E60      /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1          0xFFC02E64      /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2          0xFFC02E68      /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3          0xFFC02E6C      /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH         0xFFC02E70      /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP      0xFFC02E74      /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0            0xFFC02E78      /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1            0xFFC02E7C      /* Mailbox 19 Identifier High Register */
-
-#define CAN_MB20_DATA0          0xFFC02E80      /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1          0xFFC02E84      /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2          0xFFC02E88      /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3          0xFFC02E8C      /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH         0xFFC02E90      /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP      0xFFC02E94      /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0            0xFFC02E98      /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1            0xFFC02E9C      /* Mailbox 20 Identifier High Register */
-
-#define CAN_MB21_DATA0          0xFFC02EA0      /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1          0xFFC02EA4      /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2          0xFFC02EA8      /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3          0xFFC02EAC      /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH         0xFFC02EB0      /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP      0xFFC02EB4      /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0            0xFFC02EB8      /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1            0xFFC02EBC      /* Mailbox 21 Identifier High Register */
-
-#define CAN_MB22_DATA0          0xFFC02EC0      /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1          0xFFC02EC4      /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2          0xFFC02EC8      /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3          0xFFC02ECC      /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH         0xFFC02ED0      /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP      0xFFC02ED4      /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0            0xFFC02ED8      /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1            0xFFC02EDC      /* Mailbox 22 Identifier High Register */
-
-#define CAN_MB23_DATA0          0xFFC02EE0      /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1          0xFFC02EE4      /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2          0xFFC02EE8      /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3          0xFFC02EEC      /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH         0xFFC02EF0      /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP      0xFFC02EF4      /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0            0xFFC02EF8      /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1            0xFFC02EFC      /* Mailbox 23 Identifier High Register */
-
-#define CAN_MB24_DATA0          0xFFC02F00      /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1          0xFFC02F04      /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2          0xFFC02F08      /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3          0xFFC02F0C      /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH         0xFFC02F10      /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP      0xFFC02F14      /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0            0xFFC02F18      /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1            0xFFC02F1C      /* Mailbox 24 Identifier High Register */
-
-#define CAN_MB25_DATA0          0xFFC02F20      /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1          0xFFC02F24      /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2          0xFFC02F28      /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3          0xFFC02F2C      /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH         0xFFC02F30      /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP      0xFFC02F34      /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0            0xFFC02F38      /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1            0xFFC02F3C      /* Mailbox 25 Identifier High Register */
-
-#define CAN_MB26_DATA0          0xFFC02F40      /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1          0xFFC02F44      /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2          0xFFC02F48      /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3          0xFFC02F4C      /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH         0xFFC02F50      /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP      0xFFC02F54      /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0            0xFFC02F58      /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1            0xFFC02F5C      /* Mailbox 26 Identifier High Register */
-
-#define CAN_MB27_DATA0          0xFFC02F60      /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1          0xFFC02F64      /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2          0xFFC02F68      /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3          0xFFC02F6C      /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH         0xFFC02F70      /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP      0xFFC02F74      /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0            0xFFC02F78      /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1            0xFFC02F7C      /* Mailbox 27 Identifier High Register */
-
-#define CAN_MB28_DATA0          0xFFC02F80      /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1          0xFFC02F84      /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2          0xFFC02F88      /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3          0xFFC02F8C      /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH         0xFFC02F90      /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP      0xFFC02F94      /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0            0xFFC02F98      /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1            0xFFC02F9C      /* Mailbox 28 Identifier High Register */
-
-#define CAN_MB29_DATA0          0xFFC02FA0      /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1          0xFFC02FA4      /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2          0xFFC02FA8      /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3          0xFFC02FAC      /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH         0xFFC02FB0      /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP      0xFFC02FB4      /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0            0xFFC02FB8      /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1            0xFFC02FBC      /* Mailbox 29 Identifier High Register */
-
-#define CAN_MB30_DATA0          0xFFC02FC0      /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1          0xFFC02FC4      /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2          0xFFC02FC8      /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3          0xFFC02FCC      /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH         0xFFC02FD0      /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP      0xFFC02FD4      /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0            0xFFC02FD8      /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1            0xFFC02FDC      /* Mailbox 30 Identifier High Register */
-
-#define CAN_MB31_DATA0          0xFFC02FE0      /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1          0xFFC02FE4      /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2          0xFFC02FE8      /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3          0xFFC02FEC      /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH         0xFFC02FF0      /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP      0xFFC02FF4      /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0            0xFFC02FF8      /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1            0xFFC02FFC      /* Mailbox 31 Identifier High Register */
-
-/* CAN Mailbox Area Macros */
-#define CAN_MB_ID1(x)           (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x)           (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x)     (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x)        (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x)         (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x)         (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x)         (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x)         (CAN_MB00_DATA0+((x)*0x20))
-
-
-/*********************************************************************************** */
-/* System MMR Register Bits and Macros */
-/******************************************************************************* */
-
-/* SWRST Mask */
-#define SYSTEM_RESET    0x0007  /* Initiates A System Software Reset */
-#define DOUBLE_FAULT    0x0008  /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE    0x2000  /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG              0x4000  /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE  0x8000  /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks                                                                                                   */
-#define BMODE                   0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT                  0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
-#define PLL_WAKEUP_IRQ          0x00000001      /* PLL Wakeup Interrupt Request */
-#define DMAC0_ERR_IRQ           0x00000002      /* DMA Controller 0 Error Interrupt Request */
-#define PPI_ERR_IRQ             0x00000004      /* PPI Error Interrupt Request */
-#define SPORT0_ERR_IRQ          0x00000008      /* SPORT0 Error Interrupt Request */
-#define SPORT1_ERR_IRQ          0x00000010      /* SPORT1 Error Interrupt Request */
-#define SPI0_ERR_IRQ            0x00000020      /* SPI0 Error Interrupt Request */
-#define UART0_ERR_IRQ           0x00000040      /* UART0 Error Interrupt Request */
-#define RTC_IRQ                 0x00000080      /* Real-Time Clock Interrupt Request */
-#define DMA0_IRQ                0x00000100      /* DMA Channel 0 (PPI) Interrupt Request */
-#define DMA1_IRQ                0x00000200      /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
-#define DMA2_IRQ                0x00000400      /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
-#define DMA3_IRQ                0x00000800      /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
-#define DMA4_IRQ                0x00001000      /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
-#define DMA5_IRQ                0x00002000      /* DMA Channel 5 (SPI) Interrupt Request */
-#define DMA6_IRQ                0x00004000      /* DMA Channel 6 (UART RX) Interrupt Request */
-#define DMA7_IRQ                0x00008000      /* DMA Channel 7 (UART TX) Interrupt Request */
-#define TIMER0_IRQ              0x00010000      /* Timer 0 Interrupt Request */
-#define TIMER1_IRQ              0x00020000      /* Timer 1 Interrupt Request */
-#define TIMER2_IRQ              0x00040000      /* Timer 2 Interrupt Request */
-#define PFA_IRQ                 0x00080000      /* Programmable Flag Interrupt Request A */
-#define PFB_IRQ                 0x00100000      /* Programmable Flag Interrupt Request B */
-#define MDMA0_0_IRQ             0x00200000      /* MemDMA0 Stream 0 Interrupt Request */
-#define MDMA0_1_IRQ             0x00400000      /* MemDMA0 Stream 1 Interrupt Request */
-#define WDOG_IRQ                0x00800000      /* Software Watchdog Timer Interrupt Request */
-#define DMAC1_ERR_IRQ           0x01000000      /* DMA Controller 1 Error Interrupt Request */
-#define SPORT2_ERR_IRQ          0x02000000      /* SPORT2 Error Interrupt Request */
-#define SPORT3_ERR_IRQ          0x04000000      /* SPORT3 Error Interrupt Request */
-#define MXVR_SD_IRQ             0x08000000      /* MXVR Synchronous Data Interrupt Request */
-#define SPI1_ERR_IRQ            0x10000000      /* SPI1 Error Interrupt Request */
-#define SPI2_ERR_IRQ            0x20000000      /* SPI2 Error Interrupt Request */
-#define UART1_ERR_IRQ           0x40000000      /* UART1 Error Interrupt Request */
-#define UART2_ERR_IRQ           0x80000000      /* UART2 Error Interrupt Request */
-
-/* the following are for backwards compatibility */
-#define DMA0_ERR_IRQ            DMAC0_ERR_IRQ
-#define DMA1_ERR_IRQ            DMAC1_ERR_IRQ
-
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1   */
-#define CAN_ERR_IRQ                     0x00000001      /* CAN Error Interrupt Request */
-#define DMA8_IRQ                        0x00000002      /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
-#define DMA9_IRQ                        0x00000004      /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
-#define DMA10_IRQ                       0x00000008      /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
-#define DMA11_IRQ                       0x00000010      /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
-#define DMA12_IRQ                       0x00000020      /* DMA Channel 12 Interrupt Request */
-#define DMA13_IRQ                       0x00000040      /* DMA Channel 13 Interrupt Request */
-#define DMA14_IRQ                       0x00000080      /* DMA Channel 14 (SPI1) Interrupt Request */
-#define DMA15_IRQ                       0x00000100      /* DMA Channel 15 (SPI2) Interrupt Request */
-#define DMA16_IRQ                       0x00000200      /* DMA Channel 16 (UART1 RX) Interrupt Request */
-#define DMA17_IRQ                       0x00000400      /* DMA Channel 17 (UART1 TX) Interrupt Request */
-#define DMA18_IRQ                       0x00000800      /* DMA Channel 18 (UART2 RX) Interrupt Request */
-#define DMA19_IRQ                       0x00001000      /* DMA Channel 19 (UART2 TX) Interrupt Request */
-#define TWI0_IRQ                        0x00002000      /* TWI0 Interrupt Request */
-#define TWI1_IRQ                        0x00004000      /* TWI1 Interrupt Request */
-#define CAN_RX_IRQ                      0x00008000      /* CAN Receive Interrupt Request */
-#define CAN_TX_IRQ                      0x00010000      /* CAN Transmit Interrupt Request */
-#define MDMA1_0_IRQ                     0x00020000      /* MemDMA1 Stream 0 Interrupt Request */
-#define MDMA1_1_IRQ                     0x00040000      /* MemDMA1 Stream 1 Interrupt Request */
-#define MXVR_STAT_IRQ                   0x00080000      /* MXVR Status Interrupt Request */
-#define MXVR_CM_IRQ                     0x00100000      /* MXVR Control Message Interrupt Request */
-#define MXVR_AP_IRQ                     0x00200000      /* MXVR Asynchronous Packet Interrupt */
-
-/* the following are for backwards compatibility */
-#define MDMA0_IRQ               MDMA1_0_IRQ
-#define MDMA1_IRQ               MDMA1_1_IRQ
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* SIC_IMASKx Masks                                                                                      */
-#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x)             (1 << ((x)&0x1Fu))                                      /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x)   (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Unmask Peripheral #x interrupt */
-#else
-#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWRx Masks                                                                                        */
-#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x)   (1 << ((x)&0x1Fu))                                      /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x */
-#endif /* _MISRA_RULES */
-
-
-/* ***************************** UART CONTROLLER MASKS ********************** */
-/* UARTx_LCR Register */
-#ifdef _MISRA_RULES
-#define WLS(x)          (((x)-5u) & 0x03u)      /* Word Length Select */
-#else
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
-#endif /* _MISRA_RULES */
-#define STB                     0x04                            /* Stop Bits */
-#define PEN                     0x08                            /* Parity Enable */
-#define EPS                     0x10                            /* Even Parity Select */
-#define STP                     0x20                            /* Stick Parity */
-#define SB                      0x40                            /* Set Break */
-#define DLAB            0x80                            /* Divisor Latch Access */
-
-#define DLAB_P          0x07
-#define SB_P            0x06
-#define STP_P           0x05
-#define EPS_P           0x04
-#define PEN_P           0x03
-#define STB_P           0x02
-#define WLS_P1          0x01
-#define WLS_P0          0x00
-
-/* UARTx_MCR Register */
-#define LOOP_ENA        0x10    /* Loopback Mode Enable */
-#define LOOP_ENA_P      0x04
-/* Deprecated UARTx_MCR Mask                     */
-
-/* UARTx_LSR Register */
-#define DR                      0x01    /* Data Ready */
-#define OE                      0x02    /* Overrun Error */
-#define PE                      0x04    /* Parity Error */
-#define FE                      0x08    /* Framing Error */
-#define BI                      0x10    /* Break Interrupt */
-#define THRE            0x20    /* THR Empty */
-#define TEMT            0x40    /* TSR and UART_THR Empty */
-
-#define TEMP_P          0x06
-#define THRE_P          0x05
-#define BI_P            0x04
-#define FE_P            0x03
-#define PE_P            0x02
-#define OE_P            0x01
-#define DR_P            0x00
-
-/* UARTx_IER Register */
-#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt */
-#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt */
-#define ELSI            0x04            /* Enable RX Status Interrupt */
-
-#define ELSI_P          0x02
-#define ETBEI_P         0x01
-#define ERBFI_P         0x00
-
-/* UARTx_IIR Register */
-#define NINT            0x01
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-#define NINT_P          0x00
-
-/* UARTx_GCTL Register */
-#define UCEN            0x01            /* Enable UARTx Clocks */
-#define IREN            0x02            /* Enable IrDA Mode */
-#define TPOLC           0x04            /* IrDA TX Polarity Change */
-#define RPOLC           0x08            /* IrDA RX Polarity Change */
-#define FPE                     0x10            /* Force Parity Error On Transmit */
-#define FFE                     0x20            /* Force Framing Error On Transmit */
-
-#define FFE_P           0x05
-#define FPE_P           0x04
-#define RPOLC_P         0x03
-#define TPOLC_P         0x02
-#define IREN_P          0x01
-#define UCEN_P          0x00
-
-
-/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
-/*  PPI_CONTROL Masks         */
-#define PORT_EN         0x0001  /* PPI Port Enable  */
-#define PORT_DIR        0x0002  /* PPI Port Direction       */
-#define XFR_TYPE        0x000C  /* PPI Transfer Type  */
-#define PORT_CFG        0x0030  /* PPI Port Configuration */
-#define FLD_SEL         0x0040  /* PPI Active Field Select */
-#define PACK_EN         0x0080  /* PPI Packing Mode */
-/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN         0x0200  /* PPI Skip Element Enable */
-#define SKIP_EO         0x0400  /* PPI Skip Even/Odd Elements */
-#define DLENGTH         0x3800  /* PPI Data Length  */
-#define DLEN_8          0x0          /* PPI Data Length mask for DLEN=8 */
-#define DLEN_10         0x0800          /* Data Length = 10 Bits */
-#define DLEN_11         0x1000          /* Data Length = 11 Bits */
-#define DLEN_12         0x1800          /* Data Length = 12 Bits */
-#define DLEN_13         0x2000          /* Data Length = 13 Bits */
-#define DLEN_14         0x2800          /* Data Length = 14 Bits */
-#define DLEN_15         0x3000          /* Data Length = 15 Bits */
-#define DLEN_16         0x3800          /* Data Length = 16 Bits */
-#ifdef _MISRA_RULES
-#define DLEN(x)         ((((x)-9u) & 0x07u) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#else
-#define DLEN(x)         ((((x)-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#endif /* _MISRA_RULES */
-#define POL                     0xC000  /* PPI Signal Polarities       */
-#define POLC            0x4000          /* PPI Clock Polarity */
-#define POLS            0x8000          /* PPI Frame Sync Polarity */
-
-
-/* PPI_STATUS Masks                                          */
-#define FLD                     0x0400  /* Field Indicator   */
-#define FT_ERR          0x0800  /* Frame Track Error */
-#define OVR                     0x1000  /* FIFO Overflow Error */
-#define UNDR            0x2000  /* FIFO Underrun Error */
-#define ERR_DET         0x4000  /* Error Detected Indicator */
-#define ERR_NCOR        0x8000  /* Error Not Corrected Indicator */
-
-
-/* **********  DMA CONTROLLER MASKS  ***********************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator */
-#define CTYPE_P                 0x6             /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8                   0x0080  /* DMA 8-bit Operation Indicator   */
-#define PCAP16                  0x0100  /* DMA 16-bit Operation Indicator */
-#define PCAP32                  0x0200  /* DMA 32-bit Operation Indicator */
-#define PCAPWR                  0x0400  /* DMA Write Operation Indicator */
-#define PCAPRD                  0x0800  /* DMA Read Operation Indicator */
-#define PMAP                    0xF000  /* DMA Peripheral Map Field */
-
-/* PMAP Encodings For DMA Controller 0 */
-#define PMAP_PPI                0x0000  /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX   0x1000  /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX   0x2000  /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX   0x3000  /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX   0x4000  /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI0               0x5000  /* PMAP SPI DMA */
-#define PMAP_UART0RX            0x6000  /* PMAP UART Receive DMA */
-#define PMAP_UART0TX            0x7000  /* PMAP UART Transmit DMA */
-
-/* PMAP Encodings For DMA Controller 1 */
-#define PMAP_SPORT2RX       0x0000  /* PMAP SPORT2 Receive DMA */
-#define PMAP_SPORT2TX       0x1000  /* PMAP SPORT2 Transmit DMA */
-#define PMAP_SPORT3RX       0x2000  /* PMAP SPORT3 Receive DMA */
-#define PMAP_SPORT3TX       0x3000  /* PMAP SPORT3 Transmit DMA */
-#define PMAP_SPI1           0x6000  /* PMAP SPI1 DMA */
-#define PMAP_SPI2           0x7000  /* PMAP SPI2 DMA */
-#define PMAP_UART1RX        0x8000  /* PMAP UART1 Receive DMA */
-#define PMAP_UART1TX        0x9000  /* PMAP UART1 Transmit DMA */
-#define PMAP_UART2RX        0xA000  /* PMAP UART2 Receive DMA */
-#define PMAP_UART2TX        0xB000  /* PMAP UART2 Transmit DMA */
-
-
-/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
-/* PWM Timer bit definitions */
-/* TIMER_ENABLE Register */
-#define TIMEN0                  0x0001  /* Enable Timer 0 */
-#define TIMEN1                  0x0002  /* Enable Timer 1 */
-#define TIMEN2                  0x0004  /* Enable Timer 2 */
-
-#define TIMEN0_P                0x00
-#define TIMEN1_P                0x01
-#define TIMEN2_P                0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0                 0x0001  /* Disable Timer 0 */
-#define TIMDIS1                 0x0002  /* Disable Timer 1 */
-#define TIMDIS2                 0x0004  /* Disable Timer 2 */
-
-#define TIMDIS0_P               0x00
-#define TIMDIS1_P               0x01
-#define TIMDIS2_P               0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0                  0x0001  /* Timer 0 Interrupt */
-#define TIMIL1                  0x0002  /* Timer 1 Interrupt */
-#define TIMIL2                  0x0004  /* Timer 2 Interrupt */
-#define TOVF_ERR0               0x0010  /* Timer 0 Counter Overflow */
-#define TOVF_ERR1               0x0020  /* Timer 1 Counter Overflow */
-#define TOVF_ERR2               0x0040  /* Timer 2 Counter Overflow */
-#define TRUN0                   0x1000  /* Timer 0 Slave Enable Status */
-#define TRUN1                   0x2000  /* Timer 1 Slave Enable Status */
-#define TRUN2                   0x4000  /* Timer 2 Slave Enable Status */
-
-#define TIMIL0_P                0x00
-#define TIMIL1_P                0x01
-#define TIMIL2_P                0x02
-#define TOVF_ERR0_P             0x04
-#define TOVF_ERR1_P             0x05
-#define TOVF_ERR2_P             0x06
-#define TRUN0_P                 0x0C
-#define TRUN1_P                 0x0D
-#define TRUN2_P                 0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0               TOVF_ERR0
-#define TOVL_ERR1               TOVF_ERR1
-#define TOVL_ERR2               TOVF_ERR2
-#define TOVL_ERR0_P             TOVF_ERR0_P
-#define TOVL_ERR1_P     TOVF_ERR1_P
-#define TOVL_ERR2_P     TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT                 0x0001
-#define WDTH_CAP                0x0002
-#define EXT_CLK                 0x0003
-#define PULSE_HI                0x0004
-#define PERIOD_CNT              0x0008
-#define IRQ_ENA                 0x0010
-#define TIN_SEL                 0x0020
-#define OUT_DIS                 0x0040
-#define CLK_SEL                 0x0080
-#define TOGGLE_HI               0x0100
-#define EMU_RUN                 0x0200
-#ifdef _MISRA_RULES
-#define ERR_TYP(x)              (((x) & 0x03u) << 14)
-#else
-#define ERR_TYP(x)              (((x) & 0x03) << 14)
-#endif /* _MISRA_RULES */
-
-#define TMODE_P0                0x00
-#define TMODE_P1                0x01
-#define PULSE_HI_P              0x02
-#define PERIOD_CNT_P    0x03
-#define IRQ_ENA_P               0x04
-#define TIN_SEL_P               0x05
-#define OUT_DIS_P               0x06
-#define CLK_SEL_P               0x07
-#define TOGGLE_HI_P             0x08
-#define EMU_RUN_P               0x09
-#define ERR_TYP_P0              0x0E
-#define ERR_TYP_P1              0x0F
-
-
-/*/ ******************   GENERAL-PURPOSE I/O  ********************* */
-/*  Flag I/O (FIO_) Masks */
-#define PF0                     0x0001
-#define PF1                     0x0002
-#define PF2                     0x0004
-#define PF3                     0x0008
-#define PF4                     0x0010
-#define PF5                     0x0020
-#define PF6                     0x0040
-#define PF7                     0x0080
-#define PF8                     0x0100
-#define PF9                     0x0200
-#define PF10            0x0400
-#define PF11            0x0800
-#define PF12            0x1000
-#define PF13            0x2000
-#define PF14            0x4000
-#define PF15            0x8000
-
-/*  PORT F BIT POSITIONS */
-#define PF0_P           0x0
-#define PF1_P           0x1
-#define PF2_P           0x2
-#define PF3_P           0x3
-#define PF4_P           0x4
-#define PF5_P           0x5
-#define PF6_P           0x6
-#define PF7_P           0x7
-#define PF8_P           0x8
-#define PF9_P           0x9
-#define PF10_P          0xA
-#define PF11_P          0xB
-#define PF12_P          0xC
-#define PF13_P          0xD
-#define PF14_P          0xE
-#define PF15_P          0xF
-
-
-/*******************   GPIO MASKS  *********************/
-/* Port C Masks */
-#define PC0             0x0001
-#define PC1             0x0002
-#define PC4             0x0010
-#define PC5             0x0020
-#define PC6             0x0040
-#define PC7             0x0080
-#define PC8             0x0100
-#define PC9             0x0200
-/* Port C Bit Positions */
-#define PC0_P   0x0
-#define PC1_P   0x1
-#define PC4_P   0x4
-#define PC5_P   0x5
-#define PC6_P   0x6
-#define PC7_P   0x7
-#define PC8_P   0x8
-#define PC9_P   0x9
-
-/* Port D */
-#define PD0             0x0001
-#define PD1             0x0002
-#define PD2             0x0004
-#define PD3             0x0008
-#define PD4             0x0010
-#define PD5             0x0020
-#define PD6             0x0040
-#define PD7             0x0080
-#define PD8             0x0100
-#define PD9             0x0200
-#define PD10    0x0400
-#define PD11    0x0800
-#define PD12    0x1000
-#define PD13    0x2000
-#define PD14    0x4000
-#define PD15    0x8000
-/* Port D Bit Positions */
-#define PD0_P   0x0
-#define PD1_P   0x1
-#define PD2_P   0x2
-#define PD3_P   0x3
-#define PD4_P   0x4
-#define PD5_P   0x5
-#define PD6_P   0x6
-#define PD7_P   0x7
-#define PD8_P   0x8
-#define PD9_P   0x9
-#define PD10_P  0xA
-#define PD11_P  0xB
-#define PD12_P  0xC
-#define PD13_P  0xD
-#define PD14_P  0xE
-#define PD15_P  0xF
-
-/* Port E */
-#define PE0             0x0001
-#define PE1             0x0002
-#define PE2             0x0004
-#define PE3             0x0008
-#define PE4             0x0010
-#define PE5             0x0020
-#define PE6             0x0040
-#define PE7             0x0080
-#define PE8             0x0100
-#define PE9             0x0200
-#define PE10    0x0400
-#define PE11    0x0800
-#define PE12    0x1000
-#define PE13    0x2000
-#define PE14    0x4000
-#define PE15    0x8000
-/* Port E Bit Positions */
-#define PE0_P   0x0
-#define PE1_P   0x1
-#define PE2_P   0x2
-#define PE3_P   0x3
-#define PE4_P   0x4
-#define PE5_P   0x5
-#define PE6_P   0x6
-#define PE7_P   0x7
-#define PE8_P   0x8
-#define PE9_P   0x9
-#define PE10_P  0xA
-#define PE11_P  0xB
-#define PE12_P  0xC
-#define PE13_P  0xD
-#define PE14_P  0xE
-#define PE15_P  0xF
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
-/* EBIU_AMGCTL Masks */
-#define AMCKEN          0x0001  /* Enable CLKOUT */
-#define AMBEN_NONE      0x0000  /* All Banks Disabled */
-#define AMBEN_B0        0x0002  /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1     0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2  0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL       0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define CDPRIO          0x0100  /* DMA has priority over core for external accesses */
-
-/* EBIU_AMGCTL Bit Positions */
-#define AMCKEN_P                0x0000  /* Enable CLKOUT */
-#define AMBEN_P0                0x0001  /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1                0x0002  /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
-#define AMBEN_P2                0x0003  /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN                 0x00000001  /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL                0x00000002  /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1                  0x00000004  /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2                  0x00000008  /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3                  0x0000000C  /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4                  0x00000000  /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1                  0x00000010  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2                  0x00000020  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3                  0x00000030  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4                  0x00000000  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1                  0x00000040  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2                  0x00000080  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3                  0x000000C0  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0                  0x00000000  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1                 0x00000100  /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2                 0x00000200  /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3                 0x00000300  /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4                 0x00000400  /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5                 0x00000500  /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6                 0x00000600  /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7                 0x00000700  /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8                 0x00000800  /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9                 0x00000900  /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10                0x00000A00  /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11                0x00000B00  /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12                0x00000C00  /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13                0x00000D00  /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14                0x00000E00  /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15                0x00000F00  /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1                 0x00001000  /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2                 0x00002000  /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3                 0x00003000  /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4                 0x00004000  /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5                 0x00005000  /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6                 0x00006000  /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7                 0x00007000  /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8                 0x00008000  /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9                 0x00009000  /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10                0x0000A000  /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11                0x0000B000  /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12                0x0000C000  /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13                0x0000D000  /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14                0x0000E000  /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15                0x0000F000  /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN                 0x00010000  /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL                0x00020000  /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1                  0x00040000  /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2                  0x00080000  /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3                  0x000C0000  /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4                  0x00000000  /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1                  0x00100000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2                  0x00200000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3                  0x00300000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4                  0x00000000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1                  0x00400000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2                  0x00800000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3                  0x00C00000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0                  0x00000000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1                 0x01000000  /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2                 0x02000000  /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3                 0x03000000  /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4                 0x04000000  /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5                 0x05000000  /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6                 0x06000000  /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7                 0x07000000  /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8                 0x08000000  /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9                 0x09000000  /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10                0x0A000000  /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11                0x0B000000  /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12                0x0C000000  /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13                0x0D000000  /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14                0x0E000000  /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15                0x0F000000  /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1                 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2                 0x20000000  /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3                 0x30000000  /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4                 0x40000000  /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5                 0x50000000  /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6                 0x60000000  /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7                 0x70000000  /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8                 0x80000000  /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9                 0x90000000  /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10                0xA0000000  /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11                0xB0000000  /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12                0xC0000000  /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13                0xD0000000  /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14                0xE0000000  /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15                0xF0000000  /* Bank 1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN                 0x00000001  /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL                0x00000002  /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1                  0x00000004  /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2                  0x00000008  /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3                  0x0000000C  /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4                  0x00000000  /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1                  0x00000010  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2                  0x00000020  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3                  0x00000030  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4                  0x00000000  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1                  0x00000040  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2                  0x00000080  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3                  0x000000C0  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0                  0x00000000  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1                 0x00000100  /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2                 0x00000200  /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3                 0x00000300  /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4                 0x00000400  /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5                 0x00000500  /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6                 0x00000600  /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7                 0x00000700  /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8                 0x00000800  /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9                 0x00000900  /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10                0x00000A00  /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11                0x00000B00  /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12                0x00000C00  /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13                0x00000D00  /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14                0x00000E00  /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15                0x00000F00  /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1                 0x00001000  /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2                 0x00002000  /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3                 0x00003000  /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4                 0x00004000  /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5                 0x00005000  /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6                 0x00006000  /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7                 0x00007000  /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8                 0x00008000  /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9                 0x00009000  /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10                0x0000A000  /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11                0x0000B000  /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12                0x0000C000  /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13                0x0000D000  /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14                0x0000E000  /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15                0x0000F000  /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN                 0x00010000  /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL                0x00020000  /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1                  0x00040000  /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2                  0x00080000  /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3                  0x000C0000  /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4                  0x00000000  /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1                  0x00100000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2                  0x00200000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3                  0x00300000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4                  0x00000000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1                  0x00400000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2                  0x00800000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3                  0x00C00000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0                  0x00000000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1                 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2                 0x02000000  /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3                 0x03000000  /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4                 0x04000000  /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5                 0x05000000  /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6                 0x06000000  /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7                 0x07000000  /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8                 0x08000000  /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9                 0x09000000  /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10                0x0A000000  /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11                0x0B000000  /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12                0x0C000000  /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13                0x0D000000  /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14                0x0E000000  /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15                0x0F000000  /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1                 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2                 0x20000000  /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3                 0x30000000  /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4                 0x40000000  /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5                 0x50000000  /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6                 0x60000000  /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7                 0x70000000  /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8                 0x80000000  /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9                 0x90000000  /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10                0xA0000000  /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11                0xB0000000  /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12                0xC0000000  /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13                0xD0000000  /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14                0xE0000000  /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15                0xF0000000  /* Bank 3 Write Access Time = 15 cycles */
-
-/* **********************  SDRAM CONTROLLER MASKS  *************************** */
-/* EBIU_SDGCTL Masks */
-#define SCTLE                   0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2                    0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3                    0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE                             0x00000010 /* Enable SDRAM prefetch */
-#define PFP                             0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1                  0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2                  0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3                  0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4                  0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5                  0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6                  0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7                  0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8                  0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9                  0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10                 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11                 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12                 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13                 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14                 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15                 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1                   0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2                   0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3                   0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4                   0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5                   0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6                   0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7                   0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1                  0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2                  0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3                  0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4                  0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5                  0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6                  0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7                  0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1                   0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2                   0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3                   0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD                   0x00200000 /*Power-up start delay */
-#define PSM                             0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS                             0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS                    0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE                   0x02000000 /* Enable external buffering timing */
-#define FBBRW                   0x04000000 /* Fast back-to-back read write enable */
-#define EMREN                   0x10000000 /* Extended mode register enable */
-#define TCSR                    0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG                   0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE                             0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16                 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32                 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64                 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128                0x00000006 /* SDRAM external bank size = 128MB */
-#define EBSZ_256                0x00000008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512                0x0000000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8                 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9                 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10                0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11                0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI                    0x00000001 /* SDRAM controller is idle */
-#define SDSRA                   0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA                   0x00000004 /* SDRAM power up active  */
-#define SDRS                    0x00000008 /* SDRAM is in reset state */
-#define SDEASE                  0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT                  0x00000020 /* Bus granted */
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWIx) MASKS  ***********************/
-/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
-#ifdef _MISRA_RULES
-#define CLKLOW(x)       ((x) & 0xFFu)           /* Periods Clock Is Held Low */
-#define CLKHI(y)        (((y)&0xFFu)<<0x8)      /* Periods Before New Clock Low */
-#else
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low */
-#endif /* _MISRA_RULES */
-
-/* TWIx_PRESCALE Masks                                                           */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz) */
-#define TWI_ENA         0x0080          /* TWI Enable            */
-#define SCCB            0x0200          /* SCCB Compatibility Enable */
-
-/* TWIx_SLAVE_CTRL Masks                                                                 */
-#define SEN                     0x0001          /* Slave Enable          */
-#define SADD_LEN        0x0002          /* Slave Address Length */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled */
-
-/* TWIx_SLAVE_STAT Masks                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator */
-
-/* TWIx_MASTER_CTRL Masks                                                */
-#define MEN                     0x0001          /* Master Mode Enable */
-#define MADD_LEN        0x0002          /* Master Address Length */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*) */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs */
-#define STOP            0x0010          /* Issue Stop Condition */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer */
-#define SDAOVR          0x4000          /* Serial Data Override */
-#define SCLOVR          0x8000          /* Serial Clock Override */
-
-/* TWIx_MASTER_STAT Masks                                                        */
-#define MPROG           0x0001          /* Master Transfer In Progress */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted) */
-#define ANAK            0x0004          /* Address Not Acknowledged */
-#define DNAK            0x0008          /* Data Not Acknowledged */
-#define BUFRDERR        0x0010          /* Buffer Read Error */
-#define BUFWRERR        0x0020          /* Buffer Write Error */
-#define SDASEN          0x0040          /* Serial Data Sense */
-#define SCLSEN          0x0080          /* Serial Clock Sense */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator */
-
-/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
-#define SINIT           0x0001          /* Slave Transfer Initiated */
-#define SCOMP           0x0002          /* Slave Transfer Complete */
-#define SERR            0x0004          /* Slave Transfer Error */
-#define SOVF            0x0008          /* Slave Overflow */
-#define MCOMP           0x0010          /* Master Transfer Complete */
-#define MERR            0x0020          /* Master Transfer Error */
-#define XMTSERV         0x0040          /* Transmit FIFO Service */
-#define RCVSERV         0x0080          /* Receive FIFO Service */
-
-/* TWIx_FIFO_CTL Masks                                   */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length */
-
-/* TWIx_FIFO_STAT Masks                                                          */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write) */
-
-#define RCVSTAT         0x000C          /* Receive FIFO Status */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read) */
-
 #endif /* _DEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index bd9adb7183da..8a5beeece996 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -70,4 +70,9 @@
 #define PORT_D GPIO_PD0
 #define PORT_E GPIO_PE0
 
+#include <mach-common/ports-c.h>
+#include <mach-common/ports-d.h>
+#include <mach-common/ports-e.h>
+#include <mach-common/ports-f.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h
index b30bbcd412a7..94cca674d835 100644
--- a/arch/blackfin/mach-bf538/include/mach/pll.h
+++ b/arch/blackfin/mach-bf538/include/mach/pll.h
@@ -1,63 +1 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index f0c0eef95ba8..d11502ac5623 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -156,7 +156,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -211,7 +211,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX,
 #ifdef CONFIG_BFIN_UART1_CTSRTS
         P_UART1_RTS, P_UART1_CTS,
@@ -258,7 +258,7 @@ static struct resource bfin_uart2_resources[] = {
         },
 };
 
-unsigned short bfin_uart2_peripherals[] = {
+static unsigned short bfin_uart2_peripherals[] = {
         P_UART2_TX, P_UART2_RX, 0
 };
 
@@ -313,7 +313,7 @@ static struct resource bfin_uart3_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart3_peripherals[] = {
+static unsigned short bfin_uart3_peripherals[] = {
         P_UART3_TX, P_UART3_RX,
 #ifdef CONFIG_BFIN_UART3_CTSRTS
         P_UART3_RTS, P_UART3_CTS,
@@ -482,11 +482,13 @@ static struct resource musb_resources[] = {
                 .start  = IRQ_USB_INT0,
                 .end    = IRQ_USB_INT0,
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "mc"
         },
         [2] = { /* DMA IRQ */
                 .start  = IRQ_USB_DMA,
                 .end    = IRQ_USB_DMA,
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "dma"
         },
 };
 
@@ -502,6 +504,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -518,7 +521,7 @@ static struct musb_hdrc_platform_data musb_plat = {
 static u64 musb_dmamask = ~(u32)0;
 
 static struct platform_device musb_device = {
-        .name           = "musb_hdrc",
+        .name           = "musb-blackfin",
         .id             = 0,
         .dev = {
                 .dma_mask               = &musb_dmamask,
@@ -550,9 +553,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -584,9 +587,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
@@ -618,7 +621,7 @@ static struct resource bfin_sport2_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport2_peripherals[] = {
+static unsigned short bfin_sport2_peripherals[] = {
         P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
         P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
 };
@@ -652,7 +655,7 @@ static struct resource bfin_sport3_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport3_peripherals[] = {
+static unsigned short bfin_sport3_peripherals[] = {
         P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
         P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
 };
@@ -754,7 +757,7 @@ static struct platform_device bf54x_sdh_device = {
 #endif
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
-unsigned short bfin_can_peripherals[] = {
+static unsigned short bfin_can_peripherals[] = {
         P_CAN0_RX, P_CAN0_TX, 0
 };
 
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 216e26999af9..ce5a2bb147dc 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -261,7 +261,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -316,7 +316,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX,
 #ifdef CONFIG_BFIN_UART1_CTSRTS
         P_UART1_RTS, P_UART1_CTS,
@@ -363,7 +363,7 @@ static struct resource bfin_uart2_resources[] = {
         },
 };
 
-unsigned short bfin_uart2_peripherals[] = {
+static unsigned short bfin_uart2_peripherals[] = {
         P_UART2_TX, P_UART2_RX, 0
 };
 
@@ -418,7 +418,7 @@ static struct resource bfin_uart3_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart3_peripherals[] = {
+static unsigned short bfin_uart3_peripherals[] = {
         P_UART3_TX, P_UART3_RX,
 #ifdef CONFIG_BFIN_UART3_CTSRTS
         P_UART3_RTS, P_UART3_CTS,
@@ -587,11 +587,13 @@ static struct resource musb_resources[] = {
                 .start  = IRQ_USB_INT0,
                 .end    = IRQ_USB_INT0,
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "mc"
         },
         [2] = { /* DMA IRQ */
                 .start  = IRQ_USB_DMA,
                 .end    = IRQ_USB_DMA,
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "dma"
         },
 };
 
@@ -607,6 +609,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -623,7 +626,7 @@ static struct musb_hdrc_platform_data musb_plat = {
 static u64 musb_dmamask = ~(u32)0;
 
 static struct platform_device musb_device = {
-        .name           = "musb_hdrc",
+        .name           = "musb-blackfin",
         .id             = 0,
         .dev = {
                 .dma_mask               = &musb_dmamask,
@@ -655,9 +658,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -689,9 +692,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
@@ -723,7 +726,7 @@ static struct resource bfin_sport2_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport2_peripherals[] = {
+static unsigned short bfin_sport2_peripherals[] = {
         P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
         P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
 };
@@ -757,7 +760,7 @@ static struct resource bfin_sport3_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport3_peripherals[] = {
+static unsigned short bfin_sport3_peripherals[] = {
         P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
         P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
 };
@@ -775,7 +778,7 @@ static struct platform_device bfin_sport3_uart_device = {
 #endif
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
-unsigned short bfin_can_peripherals[] = {
+static unsigned short bfin_can_peripherals[] = {
         P_CAN0_RX, P_CAN0_TX, 0
 };
 
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
index 888b9cc0b822..69ead33cbf91 100644
--- a/arch/blackfin/mach-bf548/dma.c
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..a77109f99720
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
@@ -0,0 +1,16 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      4
+
+#define BFIN_UART_BF54X_STYLE
+
+#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
index dd44aa75fe72..0d94edaaaa2e 100644
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -4,72 +4,14 @@
  * Licensed under the GPL-2 or later.
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-#define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
-#define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
-#define UART_CLEAR_IER(uart,v)  bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-#define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
-#define UART_CLEAR_SCTS(uart)   bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
-
-#define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
-#define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
-
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
-#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
         defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
 # define CONFIG_SERIAL_BFIN_HARD_CTSRTS
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        int                     status_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
-        int                     scts;
-        int                     cts_pin;
-        int                     rts_pin;
-#endif
-};
-
 struct bfin_serial_res {
         unsigned long   uart_base_addr;
         int             uart_irq;
@@ -148,3 +90,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 5684030ccc21..72da721a77f5 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2009 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -10,58 +10,40 @@
 #include "bf548.h"
 #include "anomaly.h"
 
+#include <asm/def_LPBlackfin.h>
 #ifdef CONFIG_BF542
-#include "defBF542.h"
+# include "defBF542.h"
 #endif
-
 #ifdef CONFIG_BF544
-#include "defBF544.h"
+# include "defBF544.h"
 #endif
-
 #ifdef CONFIG_BF547
-#include "defBF547.h"
+# include "defBF547.h"
 #endif
-
 #ifdef CONFIG_BF548
-#include "defBF548.h"
+# include "defBF548.h"
 #endif
-
 #ifdef CONFIG_BF549
-#include "defBF549.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-#ifdef CONFIG_BF542
-#include "cdefBF542.h"
+# include "defBF549.h"
+#endif
+
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# ifdef CONFIG_BF542
+#  include "cdefBF542.h"
+# endif
+# ifdef CONFIG_BF544
+#  include "cdefBF544.h"
+# endif
+# ifdef CONFIG_BF547
+#  include "cdefBF547.h"
+# endif
+# ifdef CONFIG_BF548
+#  include "cdefBF548.h"
+# endif
+# ifdef CONFIG_BF549
+#  include "cdefBF549.h"
+# endif
 #endif
-#ifdef CONFIG_BF544
-#include "cdefBF544.h"
-#endif
-#ifdef CONFIG_BF547
-#include "cdefBF547.h"
-#endif
-#ifdef CONFIG_BF548
-#include "cdefBF548.h"
-#endif
-#ifdef CONFIG_BF549
-#include "cdefBF549.h"
-#endif
-
-#endif
-
-#define BFIN_UART_NR_PORTS      4
-
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_GCTL             0x08    /* Global Control Register              */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
-#define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
-#define OFFSET_THR              0x28    /* Transmit Holding register            */
-#define OFFSET_RBR              0x2C    /* Receive Buffer register              */
 
 #endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
index 42f4a9469549..d09c19cd1b7b 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF542_H
 #define _CDEF_BF542_H
 
-/* include all Core registers and bit definitions */
-#include "defBF542.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
-
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
index 2207799575ff..33ec8102ceda 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF544_H
 #define _CDEF_BF544_H
 
-/* include all Core registers and bit definitions */
-#include "defBF544.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
-
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
index bc650e6ea482..bcb9726dea54 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF547_H
 #define _CDEF_BF547_H
 
-/* include all Core registers and bit definitions */
-#include "defBF547.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
-
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
index 3523e08f7968..bae67a65633e 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF548_H
 #define _CDEF_BF548_H
 
-/* include all Core registers and bit definitions */
-#include "defBF548.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
index 80201ed41f80..002136ad5a44 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF549_H
 #define _CDEF_BF549_H
 
-/* include all Core registers and bit definitions */
-#include "defBF549.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index deaf5d6542d5..50c89c8052f3 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,10 +7,6 @@
 #ifndef _CDEF_BF54X_H
 #define _CDEF_BF54X_H
 
-#include <asm/blackfin.h>
-
-#include "defBF54x_base.h"
-
 /* ************************************************************** */
 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
 /* ************************************************************** */
@@ -2633,22 +2629,5 @@
 
 /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
 
-/* legacy definitions */
-#define bfin_read_EBIU_AMCBCTL0         bfin_read_EBIU_AMBCTL0
-#define bfin_write_EBIU_AMCBCTL0        bfin_write_EBIU_AMBCTL0
-#define bfin_read_EBIU_AMCBCTL1         bfin_read_EBIU_AMBCTL1
-#define bfin_write_EBIU_AMCBCTL1        bfin_write_EBIU_AMBCTL1
-#define bfin_read_PINT0_IRQ             bfin_read_PINT0_REQUEST
-#define bfin_write_PINT0_IRQ            bfin_write_PINT0_REQUEST
-#define bfin_read_PINT1_IRQ             bfin_read_PINT1_REQUEST
-#define bfin_write_PINT1_IRQ            bfin_write_PINT1_REQUEST
-#define bfin_read_PINT2_IRQ             bfin_read_PINT2_REQUEST
-#define bfin_write_PINT2_IRQ            bfin_write_PINT2_REQUEST
-#define bfin_read_PINT3_IRQ             bfin_read_PINT3_REQUEST
-#define bfin_write_PINT3_IRQ            bfin_write_PINT3_REQUEST
-
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
 #endif /* _CDEF_BF54X_H */
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
index abf5f750dd8b..629bf216e2b5 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,11 +7,6 @@
 #ifndef _DEF_BF542_H
 #define _DEF_BF542_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
-
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index e2771094de02..642468c1bcb1 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,11 +7,6 @@
 #ifndef _DEF_BF544_H
 #define _DEF_BF544_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
-
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index be21ba5b3aa8..2f3337cd311e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,11 +7,6 @@
 #ifndef _DEF_BF547_H
 #define _DEF_BF547_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
-
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index 3fb33b040ab7..3c7f1b69349e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,11 +7,6 @@
 #ifndef _DEF_BF548_H
 #define _DEF_BF548_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index 5a04e6d4017e..9a45cb6b30da 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,11 +7,6 @@
 #ifndef _DEF_BF549_H
 #define _DEF_BF549_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 78f91103f175..0867c2bedb43 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -1615,14 +1615,14 @@
 #define                     CTYPE  0x40       /* DMA Channel Type */
 #define                      PMAP  0xf000     /* Peripheral Mapped To This Channel */
 
-/* Bit masks for DMACx_TCPER */
+/* Bit masks for DMACx_TC_PER */
 
 #define        DCB_TRAFFIC_PERIOD  0xf        /* DCB Traffic Control Period */
 #define        DEB_TRAFFIC_PERIOD  0xf0       /* DEB Traffic Control Period */
 #define        DAB_TRAFFIC_PERIOD  0x700      /* DAB Traffic Control Period */
 #define   MDMA_ROUND_ROBIN_PERIOD  0xf800     /* MDMA Round Robin Period */
 
-/* Bit masks for DMACx_TCCNT */
+/* Bit masks for DMACx_TC_CNT */
 
 #define         DCB_TRAFFIC_COUNT  0xf        /* DCB Traffic Control Count */
 #define         DEB_TRAFFIC_COUNT  0xf0       /* DEB Traffic Control Count */
@@ -2172,68 +2172,6 @@
 
 #define                 RCVDATA16  0xffff     /* Receive FIFO 16-Bit Data */
 
-/* Bit masks for UARTx_LCR */
-
-#if 0
-/* conflicts with legacy one in last section */
-#define                       WLS  0x3        /* Word Length Select */
-#endif
-#define                       STB  0x4        /* Stop Bits */
-#define                       PEN  0x8        /* Parity Enable */
-#define                       EPS  0x10       /* Even Parity Select */
-#define                       STP  0x20       /* Sticky Parity */
-#define                        SB  0x40       /* Set Break */
-
-/* Bit masks for UARTx_MCR */
-
-#define                      XOFF  0x1        /* Transmitter Off */
-#define                      MRTS  0x2        /* Manual Request To Send */
-#define                      RFIT  0x4        /* Receive FIFO IRQ Threshold */
-#define                      RFRT  0x8        /* Receive FIFO RTS Threshold */
-#define                  LOOP_ENA  0x10       /* Loopback Mode Enable */
-#define                     FCPOL  0x20       /* Flow Control Pin Polarity */
-#define                      ARTS  0x40       /* Automatic Request To Send */
-#define                      ACTS  0x80       /* Automatic Clear To Send */
-
-/* Bit masks for UARTx_LSR */
-
-#define                        DR  0x1        /* Data Ready */
-#define                        OE  0x2        /* Overrun Error */
-#define                        PE  0x4        /* Parity Error */
-#define                        FE  0x8        /* Framing Error */
-#define                        BI  0x10       /* Break Interrupt */
-#define                      THRE  0x20       /* THR Empty */
-#define                      TEMT  0x40       /* Transmitter Empty */
-#define                       TFI  0x80       /* Transmission Finished Indicator */
-
-/* Bit masks for UARTx_MSR */
-
-#define                      SCTS  0x1        /* Sticky CTS */
-#define                       CTS  0x10       /* Clear To Send */
-#define                      RFCS  0x20       /* Receive FIFO Count Status */
-
-/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
-
-#define                   ERBFI  0x1        /* Enable Receive Buffer Full Interrupt */
-#define                   ETBEI  0x2        /* Enable Transmit Buffer Empty Interrupt */
-#define                    ELSI  0x4        /* Enable Receive Status Interrupt */
-#define                   EDSSI  0x8        /* Enable Modem Status Interrupt */
-#define                  EDTPTI  0x10       /* Enable DMA Transmit PIRQ Interrupt */
-#define                    ETFI  0x20       /* Enable Transmission Finished Interrupt */
-#define                   ERFCI  0x40       /* Enable Receive FIFO Count Interrupt */
-
-/* Bit masks for UARTx_GCTL */
-
-#define                      UCEN  0x1        /* UART Enable */
-#define                      IREN  0x2        /* IrDA Mode Enable */
-#define                     TPOLC  0x4        /* IrDA TX Polarity Change */
-#define                     RPOLC  0x8        /* IrDA RX Polarity Change */
-#define                       FPE  0x10       /* Force Parity Error */
-#define                       FFE  0x20       /* Force Framing Error */
-#define                      EDBO  0x40       /* Enable Divide-by-One */
-#define                     EGLSI  0x80       /* Enable Global LS Interrupt */
-
-
 /* ******************************************* */
 /*     MULTI BIT MACRO ENUMERATIONS            */
 /* ******************************************* */
@@ -2251,13 +2189,6 @@
 #define WDTH_CAP 0x0002
 #define EXT_CLK  0x0003
 
-/* UARTx_LCR bit field options */
-
-#define WLS_5   0x0000    /* 5 data bits */
-#define WLS_6   0x0001    /* 6 data bits */
-#define WLS_7   0x0002    /* 7 data bits */
-#define WLS_8   0x0003    /* 8 data bits */
-
 /* PINTx Register Bit Definitions */
 
 #define PIQ0 0x00000001
@@ -2300,240 +2231,6 @@
 #define PIQ30 0x40000000
 #define PIQ31 0x80000000
 
-/* PORT A Bit Definitions for the registers
-PORTA, PORTA_SET, PORTA_CLEAR,
-PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
-PORTA_FER registers
-*/
-
-#define PA0 0x0001
-#define PA1 0x0002
-#define PA2 0x0004
-#define PA3 0x0008
-#define PA4 0x0010
-#define PA5 0x0020
-#define PA6 0x0040
-#define PA7 0x0080
-#define PA8 0x0100
-#define PA9 0x0200
-#define PA10 0x0400
-#define PA11 0x0800
-#define PA12 0x1000
-#define PA13 0x2000
-#define PA14 0x4000
-#define PA15 0x8000
-
-/* PORT B Bit Definitions for the registers
-PORTB, PORTB_SET, PORTB_CLEAR,
-PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
-PORTB_FER registers
-*/
-
-#define PB0 0x0001
-#define PB1 0x0002
-#define PB2 0x0004
-#define PB3 0x0008
-#define PB4 0x0010
-#define PB5 0x0020
-#define PB6 0x0040
-#define PB7 0x0080
-#define PB8 0x0100
-#define PB9 0x0200
-#define PB10 0x0400
-#define PB11 0x0800
-#define PB12 0x1000
-#define PB13 0x2000
-#define PB14 0x4000
-
-
-/* PORT C Bit Definitions for the registers
-PORTC, PORTC_SET, PORTC_CLEAR,
-PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
-PORTC_FER registers
-*/
-
-
-#define PC0 0x0001
-#define PC1 0x0002
-#define PC2 0x0004
-#define PC3 0x0008
-#define PC4 0x0010
-#define PC5 0x0020
-#define PC6 0x0040
-#define PC7 0x0080
-#define PC8 0x0100
-#define PC9 0x0200
-#define PC10 0x0400
-#define PC11 0x0800
-#define PC12 0x1000
-#define PC13 0x2000
-
-
-/* PORT D Bit Definitions for the registers
-PORTD, PORTD_SET, PORTD_CLEAR,
-PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
-PORTD_FER registers
-*/
-
-#define PD0 0x0001
-#define PD1 0x0002
-#define PD2 0x0004
-#define PD3 0x0008
-#define PD4 0x0010
-#define PD5 0x0020
-#define PD6 0x0040
-#define PD7 0x0080
-#define PD8 0x0100
-#define PD9 0x0200
-#define PD10 0x0400
-#define PD11 0x0800
-#define PD12 0x1000
-#define PD13 0x2000
-#define PD14 0x4000
-#define PD15 0x8000
-
-/* PORT E Bit Definitions for the registers
-PORTE, PORTE_SET, PORTE_CLEAR,
-PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
-PORTE_FER registers
-*/
-
-
-#define PE0 0x0001
-#define PE1 0x0002
-#define PE2 0x0004
-#define PE3 0x0008
-#define PE4 0x0010
-#define PE5 0x0020
-#define PE6 0x0040
-#define PE7 0x0080
-#define PE8 0x0100
-#define PE9 0x0200
-#define PE10 0x0400
-#define PE11 0x0800
-#define PE12 0x1000
-#define PE13 0x2000
-#define PE14 0x4000
-#define PE15 0x8000
-
-/* PORT F Bit Definitions for the registers
-PORTF, PORTF_SET, PORTF_CLEAR,
-PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
-PORTF_FER registers
-*/
-
-
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* PORT G Bit Definitions for the registers
-PORTG, PORTG_SET, PORTG_CLEAR,
-PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
-PORTG_FER registers
-*/
-
-
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* PORT H Bit Definitions for the registers
-PORTH, PORTH_SET, PORTH_CLEAR,
-PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
-PORTH_FER registers
-*/
-
-
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-
-
-/* PORT I Bit Definitions for the registers
-PORTI, PORTI_SET, PORTI_CLEAR,
-PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
-PORTI_FER registers
-*/
-
-
-#define PI0 0x0001
-#define PI1 0x0002
-#define PI2 0x0004
-#define PI3 0x0008
-#define PI4 0x0010
-#define PI5 0x0020
-#define PI6 0x0040
-#define PI7 0x0080
-#define PI8 0x0100
-#define PI9 0x0200
-#define PI10 0x0400
-#define PI11 0x0800
-#define PI12 0x1000
-#define PI13 0x2000
-#define PI14 0x4000
-#define PI15 0x8000
-
-/* PORT J Bit Definitions for the registers
-PORTJ, PORTJ_SET, PORTJ_CLEAR,
-PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
-PORTJ_FER registers
-*/
-
-
-#define PJ0 0x0001
-#define PJ1 0x0002
-#define PJ2 0x0004
-#define PJ3 0x0008
-#define PJ4 0x0010
-#define PJ5 0x0020
-#define PJ6 0x0040
-#define PJ7 0x0080
-#define PJ8 0x0100
-#define PJ9 0x0200
-#define PJ10 0x0400
-#define PJ11 0x0800
-#define PJ12 0x1000
-#define PJ13 0x2000
-
-
 /* Port Muxing Bit Fields for PORTx_MUX Registers */
 
 #define MUX0 0x00000003
@@ -2703,16 +2400,4 @@ PORTJ_FER registers
 #define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
 #define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
 
-
-/* for legacy compatibility */
-
-#define WLS(x)  (((x)-5) & 0x03) /* Word Length Select */
-#define W1LMAX_MAX W1LMAX_MIN
-#define EBIU_AMCBCTL0 EBIU_AMBCTL0
-#define EBIU_AMCBCTL1 EBIU_AMBCTL1
-#define PINT0_IRQ PINT0_REQUEST
-#define PINT1_IRQ PINT1_REQUEST
-#define PINT2_IRQ PINT2_REQUEST
-#define PINT3_IRQ PINT3_REQUEST
-
 #endif /* _DEF_BF54X_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 28037e331964..7db433514e3f 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -200,4 +200,15 @@ struct gpio_port_s {
 
 #endif
 
+#include <mach-common/ports-a.h>
+#include <mach-common/ports-b.h>
+#include <mach-common/ports-c.h>
+#include <mach-common/ports-d.h>
+#include <mach-common/ports-e.h>
+#include <mach-common/ports-f.h>
+#include <mach-common/ports-g.h>
+#include <mach-common/ports-h.h>
+#include <mach-common/ports-i.h>
+#include <mach-common/ports-j.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 1f99b51a3d56..99fd1b2c53d8 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -474,4 +474,26 @@ Events         (highest priority)  EMU         0
 #define IRQ_PINT2_POS           24
 #define IRQ_PINT3_POS           28
 
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
+/*
+ * bfin pint registers layout
+ */
+struct bfin_pint_regs {
+        u32 mask_set;
+        u32 mask_clear;
+        u32 irq;
+        u32 assign;
+        u32 edge_set;
+        u32 edge_clear;
+        u32 invert_set;
+        u32 invert_clear;
+        u32 pinstate;
+        u32 latch;
+        u32 __pad0[2];
+};
+
+#endif
+
 #endif /* _BF548_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
index 7865a090d333..94cca674d835 100644
--- a/arch/blackfin/mach-bf548/include/mach/pll.h
+++ b/arch/blackfin/mach-bf548/include/mach/pll.h
@@ -1,69 +1 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1, iwr2;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        iwr2 = bfin_read32(SIC_IWR2);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-        bfin_write32(SIC_IWR2, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        bfin_write32(SIC_IWR2, iwr2);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1, iwr2;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        iwr2 = bfin_read32(SIC_IWR2);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-        bfin_write32(SIC_IWR2, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        bfin_write32(SIC_IWR2, iwr2);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S
index f99f174b129f..52d6f73fcced 100644
--- a/arch/blackfin/mach-bf561/atomic.S
+++ b/arch/blackfin/mach-bf561/atomic.S
@@ -49,6 +49,7 @@ ENTRY(_get_core_lock)
         jump .Lretry_corelock
 .Ldone_corelock:
         p0 = r1;
+        /* flush core internal write buffer before invalidate dcache */
         CSYNC(r2);
         flushinv[p0];
         SSYNC(r2);
@@ -685,6 +686,8 @@ ENTRY(___raw_atomic_test_asm)
         r1 = -L1_CACHE_BYTES;
         r1 = r0 & r1;
         p0 = r1;
+        /* flush core internal write buffer before invalidate dcache */
+        CSYNC(r2);
         flushinv[p0];
         SSYNC(r2);
         r0 = [p1];
@@ -907,6 +910,8 @@ ENTRY(___raw_uncached_fetch_asm)
         r1 = -L1_CACHE_BYTES;
         r1 = r0 & r1;
         p0 = r1;
+        /* flush core internal write buffer before invalidate dcache */
+        CSYNC(r2);
         flushinv[p0];
         SSYNC(r2);
         r0 = [p1];
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 0b1c20f14fe0..3926cd909b66 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -224,7 +224,7 @@ static struct resource bfin_uart0_resources[] = {
          },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 087b6b05cc73..3b67929d4c0a 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -334,7 +334,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index ab7a487975fd..f667e7704197 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -190,7 +190,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index d3017e53686b..bb056e60f6ed 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -72,7 +72,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
index c938c3c7355d..8ffdd6b4a242 100644
--- a/arch/blackfin/mach-bf561/dma.c
+++ b/arch/blackfin/mach-bf561/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
@@ -36,14 +36,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
         (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
         (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
         (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c
index c95169b612dc..4cd3b28cd046 100644
--- a/arch/blackfin/mach-bf561/hotplug.c
+++ b/arch/blackfin/mach-bf561/hotplug.c
@@ -6,7 +6,9 @@
  */
 
 #include <asm/blackfin.h>
+#include <asm/irq.h>
 #include <asm/smp.h>
+
 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
 
 int hotplug_coreb;
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 4c108c99cb6e..6a3499b02097 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -181,7 +181,11 @@
 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
 #define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
 /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
+/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
+ * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
+ * after the behavior and the root cause are confirmed with hardware team.
+ */
+#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
 /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
 #define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
 /* ICPLB_STATUS MMR Register May Be Corrupted */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..08072c86d5dc
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      1
+
+#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
index e33e158bc16d..3a6947456cf1 100644
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later.
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #ifdef CONFIG_BFIN_UART0_CTSRTS
 # define CONFIG_SERIAL_BFIN_CTSRTS
 # ifndef CONFIG_UART0_CTS_PIN
@@ -44,51 +17,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        int                     status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#else
-# if ANOMALY_05000363
-        unsigned int anomaly_threshold;
-# endif
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int                     cts_pin;
-        int                     rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long   uart_base_addr;
         int             uart_irq;
@@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 6c7dc58c018c..dc470534c085 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -10,11 +10,14 @@
 #define BF561_FAMILY
 
 #include "bf561.h"
-#include "defBF561.h"
 #include "anomaly.h"
 
-#if !defined(__ASSEMBLY__)
-#include "cdefBF561.h"
+#include <asm/def_LPBlackfin.h>
+#include "defBF561.h"
+
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# include "cdefBF561.h"
 #endif
 
 #define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
@@ -35,19 +38,4 @@
 #define bfin_read_SICB_ISR(x)           bfin_read32(__SIC_MUX(SICB_ISR0, x))
 #define bfin_write_SICB_ISR(x, val)     bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
 
-#define BFIN_UART_NR_PORTS      1
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
 #endif                          /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index 2bab99152495..753331597207 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF561_H
 #define _CDEF_BF561_H
 
-#include <asm/blackfin.h>
-
-/* include all Core registers and bit definitions */
-#include "defBF561.h"
-
-/*include core specific register pointer definitions*/
-#include <asm/cdef_LPBlackfin.h>
-
 /*********************************************************************************** */
 /* System MMR Register Map */
 /*********************************************************************************** */
@@ -523,14 +515,14 @@
 #define bfin_read_PPI1_FRAME()               bfin_read16(PPI1_FRAME)
 #define bfin_write_PPI1_FRAME(val)           bfin_write16(PPI1_FRAME,val)
 /*DMA traffic control registers */
-#define bfin_read_DMA1_TC_PER()              bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val)          bfin_write16(DMA1_TC_PER,val)
-#define bfin_read_DMA1_TC_CNT()              bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val)          bfin_write16(DMA1_TC_CNT,val)
-#define bfin_read_DMA2_TC_PER()              bfin_read16(DMA2_TC_PER)
-#define bfin_write_DMA2_TC_PER(val)          bfin_write16(DMA2_TC_PER,val)
-#define bfin_read_DMA2_TC_CNT()              bfin_read16(DMA2_TC_CNT)
-#define bfin_write_DMA2_TC_CNT(val)          bfin_write16(DMA2_TC_CNT,val)
+#define bfin_read_DMAC0_TC_PER()             bfin_read16(DMAC0_TC_PER)
+#define bfin_write_DMAC0_TC_PER(val)         bfin_write16(DMAC0_TC_PER,val)
+#define bfin_read_DMAC0_TC_CNT()             bfin_read16(DMAC0_TC_CNT)
+#define bfin_write_DMAC0_TC_CNT(val)         bfin_write16(DMAC0_TC_CNT,val)
+#define bfin_read_DMAC1_TC_PER()             bfin_read16(DMAC1_TC_PER)
+#define bfin_write_DMAC1_TC_PER(val)         bfin_write16(DMAC1_TC_PER,val)
+#define bfin_read_DMAC1_TC_CNT()             bfin_read16(DMAC1_TC_CNT)
+#define bfin_write_DMAC1_TC_CNT(val)         bfin_write16(DMAC1_TC_CNT,val)
 /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
 #define bfin_read_DMA1_0_CONFIG()            bfin_read16(DMA1_0_CONFIG)
 #define bfin_write_DMA1_0_CONFIG(val)        bfin_write16(DMA1_0_CONFIG,val)
@@ -845,110 +837,110 @@
 #define bfin_read_DMA1_11_PERIPHERAL_MAP()   bfin_read16(DMA1_11_PERIPHERAL_MAP)
 #define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
 /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define bfin_read_MDMA1_D0_CONFIG()          bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val)      bfin_write16(MDMA1_D0_CONFIG,val)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR()   bfin_read32(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_D0_START_ADDR()      bfin_read32(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val)  bfin_write32(MDMA1_D0_START_ADDR,val)
-#define bfin_read_MDMA1_D0_X_COUNT()         bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val)     bfin_write16(MDMA1_D0_X_COUNT,val)
-#define bfin_read_MDMA1_D0_Y_COUNT()         bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val)     bfin_write16(MDMA1_D0_Y_COUNT,val)
-#define bfin_read_MDMA1_D0_X_MODIFY()        bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val)    bfin_write16(MDMA1_D0_X_MODIFY,val)
-#define bfin_read_MDMA1_D0_Y_MODIFY()        bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val)    bfin_write16(MDMA1_D0_Y_MODIFY,val)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR()   bfin_read32(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_D0_CURR_ADDR()       bfin_read32(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val)   bfin_write32(MDMA1_D0_CURR_ADDR,val)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT()    bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT()    bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_D0_IRQ_STATUS()      bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val)  bfin_write16(MDMA1_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP()  bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_S0_CONFIG()          bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val)      bfin_write16(MDMA1_S0_CONFIG,val)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR()   bfin_read32(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_S0_START_ADDR()      bfin_read32(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val)  bfin_write32(MDMA1_S0_START_ADDR,val)
-#define bfin_read_MDMA1_S0_X_COUNT()         bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val)     bfin_write16(MDMA1_S0_X_COUNT,val)
-#define bfin_read_MDMA1_S0_Y_COUNT()         bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val)     bfin_write16(MDMA1_S0_Y_COUNT,val)
-#define bfin_read_MDMA1_S0_X_MODIFY()        bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val)    bfin_write16(MDMA1_S0_X_MODIFY,val)
-#define bfin_read_MDMA1_S0_Y_MODIFY()        bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val)    bfin_write16(MDMA1_S0_Y_MODIFY,val)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR()   bfin_read32(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_S0_CURR_ADDR()       bfin_read32(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val)   bfin_write32(MDMA1_S0_CURR_ADDR,val)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT()    bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT()    bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_S0_IRQ_STATUS()      bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val)  bfin_write16(MDMA1_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP()  bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_D1_CONFIG()          bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val)      bfin_write16(MDMA1_D1_CONFIG,val)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR()   bfin_read32(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_D1_START_ADDR()      bfin_read32(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val)  bfin_write32(MDMA1_D1_START_ADDR,val)
-#define bfin_read_MDMA1_D1_X_COUNT()         bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val)     bfin_write16(MDMA1_D1_X_COUNT,val)
-#define bfin_read_MDMA1_D1_Y_COUNT()         bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val)     bfin_write16(MDMA1_D1_Y_COUNT,val)
-#define bfin_read_MDMA1_D1_X_MODIFY()        bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val)    bfin_write16(MDMA1_D1_X_MODIFY,val)
-#define bfin_read_MDMA1_D1_Y_MODIFY()        bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val)    bfin_write16(MDMA1_D1_Y_MODIFY,val)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR()   bfin_read32(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_D1_CURR_ADDR()       bfin_read32(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val)   bfin_write32(MDMA1_D1_CURR_ADDR,val)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT()    bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT()    bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_D1_IRQ_STATUS()      bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val)  bfin_write16(MDMA1_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP()  bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_S1_CONFIG()          bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val)      bfin_write16(MDMA1_S1_CONFIG,val)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR()   bfin_read32(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_S1_START_ADDR()      bfin_read32(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val)  bfin_write32(MDMA1_S1_START_ADDR,val)
-#define bfin_read_MDMA1_S1_X_COUNT()         bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val)     bfin_write16(MDMA1_S1_X_COUNT,val)
-#define bfin_read_MDMA1_S1_Y_COUNT()         bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val)     bfin_write16(MDMA1_S1_Y_COUNT,val)
-#define bfin_read_MDMA1_S1_X_MODIFY()        bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val)    bfin_write16(MDMA1_S1_X_MODIFY,val)
-#define bfin_read_MDMA1_S1_Y_MODIFY()        bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val)    bfin_write16(MDMA1_S1_Y_MODIFY,val)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR()   bfin_read32(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_S1_CURR_ADDR()       bfin_read32(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val)   bfin_write32(MDMA1_S1_CURR_ADDR,val)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT()    bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT()    bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_S1_IRQ_STATUS()      bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val)  bfin_write16(MDMA1_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP()  bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_D2_CONFIG()          bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val)      bfin_write16(MDMA_D2_CONFIG,val)
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR()   bfin_read32(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D2_START_ADDR()      bfin_read32(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val)  bfin_write32(MDMA_D2_START_ADDR,val)
+#define bfin_read_MDMA_D2_X_COUNT()         bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val)     bfin_write16(MDMA_D2_X_COUNT,val)
+#define bfin_read_MDMA_D2_Y_COUNT()         bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val)     bfin_write16(MDMA_D2_Y_COUNT,val)
+#define bfin_read_MDMA_D2_X_MODIFY()        bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val)    bfin_write16(MDMA_D2_X_MODIFY,val)
+#define bfin_read_MDMA_D2_Y_MODIFY()        bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val)    bfin_write16(MDMA_D2_Y_MODIFY,val)
+#define bfin_read_MDMA_D2_CURR_DESC_PTR()   bfin_read32(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D2_CURR_ADDR()       bfin_read32(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val)   bfin_write32(MDMA_D2_CURR_ADDR,val)
+#define bfin_read_MDMA_D2_CURR_X_COUNT()    bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D2_CURR_Y_COUNT()    bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D2_IRQ_STATUS()      bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val)  bfin_write16(MDMA_D2_IRQ_STATUS,val)
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP()  bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_S2_CONFIG()          bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val)      bfin_write16(MDMA_S2_CONFIG,val)
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR()   bfin_read32(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S2_START_ADDR()      bfin_read32(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val)  bfin_write32(MDMA_S2_START_ADDR,val)
+#define bfin_read_MDMA_S2_X_COUNT()         bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val)     bfin_write16(MDMA_S2_X_COUNT,val)
+#define bfin_read_MDMA_S2_Y_COUNT()         bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val)     bfin_write16(MDMA_S2_Y_COUNT,val)
+#define bfin_read_MDMA_S2_X_MODIFY()        bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val)    bfin_write16(MDMA_S2_X_MODIFY,val)
+#define bfin_read_MDMA_S2_Y_MODIFY()        bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val)    bfin_write16(MDMA_S2_Y_MODIFY,val)
+#define bfin_read_MDMA_S2_CURR_DESC_PTR()   bfin_read32(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S2_CURR_ADDR()       bfin_read32(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val)   bfin_write32(MDMA_S2_CURR_ADDR,val)
+#define bfin_read_MDMA_S2_CURR_X_COUNT()    bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S2_CURR_Y_COUNT()    bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S2_IRQ_STATUS()      bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val)  bfin_write16(MDMA_S2_IRQ_STATUS,val)
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP()  bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_D3_CONFIG()          bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val)      bfin_write16(MDMA_D3_CONFIG,val)
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR()   bfin_read32(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D3_START_ADDR()      bfin_read32(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val)  bfin_write32(MDMA_D3_START_ADDR,val)
+#define bfin_read_MDMA_D3_X_COUNT()         bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val)     bfin_write16(MDMA_D3_X_COUNT,val)
+#define bfin_read_MDMA_D3_Y_COUNT()         bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val)     bfin_write16(MDMA_D3_Y_COUNT,val)
+#define bfin_read_MDMA_D3_X_MODIFY()        bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val)    bfin_write16(MDMA_D3_X_MODIFY,val)
+#define bfin_read_MDMA_D3_Y_MODIFY()        bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val)    bfin_write16(MDMA_D3_Y_MODIFY,val)
+#define bfin_read_MDMA_D3_CURR_DESC_PTR()   bfin_read32(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D3_CURR_ADDR()       bfin_read32(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val)   bfin_write32(MDMA_D3_CURR_ADDR,val)
+#define bfin_read_MDMA_D3_CURR_X_COUNT()    bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D3_CURR_Y_COUNT()    bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D3_IRQ_STATUS()      bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val)  bfin_write16(MDMA_D3_IRQ_STATUS,val)
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP()  bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_S3_CONFIG()          bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val)      bfin_write16(MDMA_S3_CONFIG,val)
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR()   bfin_read32(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S3_START_ADDR()      bfin_read32(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val)  bfin_write32(MDMA_S3_START_ADDR,val)
+#define bfin_read_MDMA_S3_X_COUNT()         bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val)     bfin_write16(MDMA_S3_X_COUNT,val)
+#define bfin_read_MDMA_S3_Y_COUNT()         bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val)     bfin_write16(MDMA_S3_Y_COUNT,val)
+#define bfin_read_MDMA_S3_X_MODIFY()        bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val)    bfin_write16(MDMA_S3_X_MODIFY,val)
+#define bfin_read_MDMA_S3_Y_MODIFY()        bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val)    bfin_write16(MDMA_S3_Y_MODIFY,val)
+#define bfin_read_MDMA_S3_CURR_DESC_PTR()   bfin_read32(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S3_CURR_ADDR()       bfin_read32(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val)   bfin_write32(MDMA_S3_CURR_ADDR,val)
+#define bfin_read_MDMA_S3_CURR_X_COUNT()    bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S3_CURR_Y_COUNT()    bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S3_IRQ_STATUS()      bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val)  bfin_write16(MDMA_S3_IRQ_STATUS,val)
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP()  bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val)
 /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
 #define bfin_read_DMA2_0_CONFIG()            bfin_read16(DMA2_0_CONFIG)
 #define bfin_write_DMA2_0_CONFIG(val)        bfin_write16(DMA2_0_CONFIG,val)
@@ -1263,110 +1255,110 @@
 #define bfin_read_DMA2_11_PERIPHERAL_MAP()   bfin_read16(DMA2_11_PERIPHERAL_MAP)
 #define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
 /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define bfin_read_MDMA2_D0_CONFIG()          bfin_read16(MDMA2_D0_CONFIG)
-#define bfin_write_MDMA2_D0_CONFIG(val)      bfin_write16(MDMA2_D0_CONFIG,val)
-#define bfin_read_MDMA2_D0_NEXT_DESC_PTR()   bfin_read32(MDMA2_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_D0_START_ADDR()      bfin_read32(MDMA2_D0_START_ADDR)
-#define bfin_write_MDMA2_D0_START_ADDR(val)  bfin_write32(MDMA2_D0_START_ADDR,val)
-#define bfin_read_MDMA2_D0_X_COUNT()         bfin_read16(MDMA2_D0_X_COUNT)
-#define bfin_write_MDMA2_D0_X_COUNT(val)     bfin_write16(MDMA2_D0_X_COUNT,val)
-#define bfin_read_MDMA2_D0_Y_COUNT()         bfin_read16(MDMA2_D0_Y_COUNT)
-#define bfin_write_MDMA2_D0_Y_COUNT(val)     bfin_write16(MDMA2_D0_Y_COUNT,val)
-#define bfin_read_MDMA2_D0_X_MODIFY()        bfin_read16(MDMA2_D0_X_MODIFY)
-#define bfin_write_MDMA2_D0_X_MODIFY(val)    bfin_write16(MDMA2_D0_X_MODIFY,val)
-#define bfin_read_MDMA2_D0_Y_MODIFY()        bfin_read16(MDMA2_D0_Y_MODIFY)
-#define bfin_write_MDMA2_D0_Y_MODIFY(val)    bfin_write16(MDMA2_D0_Y_MODIFY,val)
-#define bfin_read_MDMA2_D0_CURR_DESC_PTR()   bfin_read32(MDMA2_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_D0_CURR_ADDR()       bfin_read32(MDMA2_D0_CURR_ADDR)
-#define bfin_write_MDMA2_D0_CURR_ADDR(val)   bfin_write32(MDMA2_D0_CURR_ADDR,val)
-#define bfin_read_MDMA2_D0_CURR_X_COUNT()    bfin_read16(MDMA2_D0_CURR_X_COUNT)
-#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_D0_CURR_Y_COUNT()    bfin_read16(MDMA2_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_D0_IRQ_STATUS()      bfin_read16(MDMA2_D0_IRQ_STATUS)
-#define bfin_write_MDMA2_D0_IRQ_STATUS(val)  bfin_write16(MDMA2_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA2_D0_PERIPHERAL_MAP()  bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_S0_CONFIG()          bfin_read16(MDMA2_S0_CONFIG)
-#define bfin_write_MDMA2_S0_CONFIG(val)      bfin_write16(MDMA2_S0_CONFIG,val)
-#define bfin_read_MDMA2_S0_NEXT_DESC_PTR()   bfin_read32(MDMA2_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_S0_START_ADDR()      bfin_read32(MDMA2_S0_START_ADDR)
-#define bfin_write_MDMA2_S0_START_ADDR(val)  bfin_write32(MDMA2_S0_START_ADDR,val)
-#define bfin_read_MDMA2_S0_X_COUNT()         bfin_read16(MDMA2_S0_X_COUNT)
-#define bfin_write_MDMA2_S0_X_COUNT(val)     bfin_write16(MDMA2_S0_X_COUNT,val)
-#define bfin_read_MDMA2_S0_Y_COUNT()         bfin_read16(MDMA2_S0_Y_COUNT)
-#define bfin_write_MDMA2_S0_Y_COUNT(val)     bfin_write16(MDMA2_S0_Y_COUNT,val)
-#define bfin_read_MDMA2_S0_X_MODIFY()        bfin_read16(MDMA2_S0_X_MODIFY)
-#define bfin_write_MDMA2_S0_X_MODIFY(val)    bfin_write16(MDMA2_S0_X_MODIFY,val)
-#define bfin_read_MDMA2_S0_Y_MODIFY()        bfin_read16(MDMA2_S0_Y_MODIFY)
-#define bfin_write_MDMA2_S0_Y_MODIFY(val)    bfin_write16(MDMA2_S0_Y_MODIFY,val)
-#define bfin_read_MDMA2_S0_CURR_DESC_PTR()   bfin_read32(MDMA2_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_S0_CURR_ADDR()       bfin_read32(MDMA2_S0_CURR_ADDR)
-#define bfin_write_MDMA2_S0_CURR_ADDR(val)   bfin_write32(MDMA2_S0_CURR_ADDR,val)
-#define bfin_read_MDMA2_S0_CURR_X_COUNT()    bfin_read16(MDMA2_S0_CURR_X_COUNT)
-#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_S0_CURR_Y_COUNT()    bfin_read16(MDMA2_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_S0_IRQ_STATUS()      bfin_read16(MDMA2_S0_IRQ_STATUS)
-#define bfin_write_MDMA2_S0_IRQ_STATUS(val)  bfin_write16(MDMA2_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA2_S0_PERIPHERAL_MAP()  bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_D1_CONFIG()          bfin_read16(MDMA2_D1_CONFIG)
-#define bfin_write_MDMA2_D1_CONFIG(val)      bfin_write16(MDMA2_D1_CONFIG,val)
-#define bfin_read_MDMA2_D1_NEXT_DESC_PTR()   bfin_read32(MDMA2_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_D1_START_ADDR()      bfin_read32(MDMA2_D1_START_ADDR)
-#define bfin_write_MDMA2_D1_START_ADDR(val)  bfin_write32(MDMA2_D1_START_ADDR,val)
-#define bfin_read_MDMA2_D1_X_COUNT()         bfin_read16(MDMA2_D1_X_COUNT)
-#define bfin_write_MDMA2_D1_X_COUNT(val)     bfin_write16(MDMA2_D1_X_COUNT,val)
-#define bfin_read_MDMA2_D1_Y_COUNT()         bfin_read16(MDMA2_D1_Y_COUNT)
-#define bfin_write_MDMA2_D1_Y_COUNT(val)     bfin_write16(MDMA2_D1_Y_COUNT,val)
-#define bfin_read_MDMA2_D1_X_MODIFY()        bfin_read16(MDMA2_D1_X_MODIFY)
-#define bfin_write_MDMA2_D1_X_MODIFY(val)    bfin_write16(MDMA2_D1_X_MODIFY,val)
-#define bfin_read_MDMA2_D1_Y_MODIFY()        bfin_read16(MDMA2_D1_Y_MODIFY)
-#define bfin_write_MDMA2_D1_Y_MODIFY(val)    bfin_write16(MDMA2_D1_Y_MODIFY,val)
-#define bfin_read_MDMA2_D1_CURR_DESC_PTR()   bfin_read32(MDMA2_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_D1_CURR_ADDR()       bfin_read32(MDMA2_D1_CURR_ADDR)
-#define bfin_write_MDMA2_D1_CURR_ADDR(val)   bfin_write32(MDMA2_D1_CURR_ADDR,val)
-#define bfin_read_MDMA2_D1_CURR_X_COUNT()    bfin_read16(MDMA2_D1_CURR_X_COUNT)
-#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_D1_CURR_Y_COUNT()    bfin_read16(MDMA2_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_D1_IRQ_STATUS()      bfin_read16(MDMA2_D1_IRQ_STATUS)
-#define bfin_write_MDMA2_D1_IRQ_STATUS(val)  bfin_write16(MDMA2_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA2_D1_PERIPHERAL_MAP()  bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_S1_CONFIG()          bfin_read16(MDMA2_S1_CONFIG)
-#define bfin_write_MDMA2_S1_CONFIG(val)      bfin_write16(MDMA2_S1_CONFIG,val)
-#define bfin_read_MDMA2_S1_NEXT_DESC_PTR()   bfin_read32(MDMA2_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_S1_START_ADDR()      bfin_read32(MDMA2_S1_START_ADDR)
-#define bfin_write_MDMA2_S1_START_ADDR(val)  bfin_write32(MDMA2_S1_START_ADDR,val)
-#define bfin_read_MDMA2_S1_X_COUNT()         bfin_read16(MDMA2_S1_X_COUNT)
-#define bfin_write_MDMA2_S1_X_COUNT(val)     bfin_write16(MDMA2_S1_X_COUNT,val)
-#define bfin_read_MDMA2_S1_Y_COUNT()         bfin_read16(MDMA2_S1_Y_COUNT)
-#define bfin_write_MDMA2_S1_Y_COUNT(val)     bfin_write16(MDMA2_S1_Y_COUNT,val)
-#define bfin_read_MDMA2_S1_X_MODIFY()        bfin_read16(MDMA2_S1_X_MODIFY)
-#define bfin_write_MDMA2_S1_X_MODIFY(val)    bfin_write16(MDMA2_S1_X_MODIFY,val)
-#define bfin_read_MDMA2_S1_Y_MODIFY()        bfin_read16(MDMA2_S1_Y_MODIFY)
-#define bfin_write_MDMA2_S1_Y_MODIFY(val)    bfin_write16(MDMA2_S1_Y_MODIFY,val)
-#define bfin_read_MDMA2_S1_CURR_DESC_PTR()   bfin_read32(MDMA2_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_S1_CURR_ADDR()       bfin_read32(MDMA2_S1_CURR_ADDR)
-#define bfin_write_MDMA2_S1_CURR_ADDR(val)   bfin_write32(MDMA2_S1_CURR_ADDR,val)
-#define bfin_read_MDMA2_S1_CURR_X_COUNT()    bfin_read16(MDMA2_S1_CURR_X_COUNT)
-#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_S1_CURR_Y_COUNT()    bfin_read16(MDMA2_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_S1_IRQ_STATUS()      bfin_read16(MDMA2_S1_IRQ_STATUS)
-#define bfin_write_MDMA2_S1_IRQ_STATUS(val)  bfin_write16(MDMA2_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA2_S1_PERIPHERAL_MAP()  bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_D0_CONFIG()          bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)      bfin_write16(MDMA_D0_CONFIG,val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()   bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D0_START_ADDR()      bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)  bfin_write32(MDMA_D0_START_ADDR,val)
+#define bfin_read_MDMA_D0_X_COUNT()         bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)     bfin_write16(MDMA_D0_X_COUNT,val)
+#define bfin_read_MDMA_D0_Y_COUNT()         bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)     bfin_write16(MDMA_D0_Y_COUNT,val)
+#define bfin_read_MDMA_D0_X_MODIFY()        bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)    bfin_write16(MDMA_D0_X_MODIFY,val)
+#define bfin_read_MDMA_D0_Y_MODIFY()        bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)    bfin_write16(MDMA_D0_Y_MODIFY,val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()   bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D0_CURR_ADDR()       bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)   bfin_write32(MDMA_D0_CURR_ADDR,val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()    bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()    bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()      bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)  bfin_write16(MDMA_D0_IRQ_STATUS,val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()  bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_S0_CONFIG()          bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)      bfin_write16(MDMA_S0_CONFIG,val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()   bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S0_START_ADDR()      bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)  bfin_write32(MDMA_S0_START_ADDR,val)
+#define bfin_read_MDMA_S0_X_COUNT()         bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)     bfin_write16(MDMA_S0_X_COUNT,val)
+#define bfin_read_MDMA_S0_Y_COUNT()         bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)     bfin_write16(MDMA_S0_Y_COUNT,val)
+#define bfin_read_MDMA_S0_X_MODIFY()        bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)    bfin_write16(MDMA_S0_X_MODIFY,val)
+#define bfin_read_MDMA_S0_Y_MODIFY()        bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)    bfin_write16(MDMA_S0_Y_MODIFY,val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()   bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S0_CURR_ADDR()       bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)   bfin_write32(MDMA_S0_CURR_ADDR,val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()    bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()    bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()      bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)  bfin_write16(MDMA_S0_IRQ_STATUS,val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()  bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_D1_CONFIG()          bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)      bfin_write16(MDMA_D1_CONFIG,val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()   bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D1_START_ADDR()      bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)  bfin_write32(MDMA_D1_START_ADDR,val)
+#define bfin_read_MDMA_D1_X_COUNT()         bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)     bfin_write16(MDMA_D1_X_COUNT,val)
+#define bfin_read_MDMA_D1_Y_COUNT()         bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)     bfin_write16(MDMA_D1_Y_COUNT,val)
+#define bfin_read_MDMA_D1_X_MODIFY()        bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)    bfin_write16(MDMA_D1_X_MODIFY,val)
+#define bfin_read_MDMA_D1_Y_MODIFY()        bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)    bfin_write16(MDMA_D1_Y_MODIFY,val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()   bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D1_CURR_ADDR()       bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)   bfin_write32(MDMA_D1_CURR_ADDR,val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()    bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()    bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D1_IRQ_STATUS()      bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)  bfin_write16(MDMA_D1_IRQ_STATUS,val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()  bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_S1_CONFIG()          bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)      bfin_write16(MDMA_S1_CONFIG,val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()   bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S1_START_ADDR()      bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)  bfin_write32(MDMA_S1_START_ADDR,val)
+#define bfin_read_MDMA_S1_X_COUNT()         bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)     bfin_write16(MDMA_S1_X_COUNT,val)
+#define bfin_read_MDMA_S1_Y_COUNT()         bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)     bfin_write16(MDMA_S1_Y_COUNT,val)
+#define bfin_read_MDMA_S1_X_MODIFY()        bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)    bfin_write16(MDMA_S1_X_MODIFY,val)
+#define bfin_read_MDMA_S1_Y_MODIFY()        bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)    bfin_write16(MDMA_S1_Y_MODIFY,val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()   bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S1_CURR_ADDR()       bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)   bfin_write32(MDMA_S1_CURR_ADDR,val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()    bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()    bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S1_IRQ_STATUS()      bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)  bfin_write16(MDMA_S1_IRQ_STATUS,val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()  bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
 /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
 #define bfin_read_IMDMA_D0_CONFIG()          bfin_read16(IMDMA_D0_CONFIG)
 #define bfin_write_IMDMA_D0_CONFIG(val)      bfin_write16(IMDMA_D0_CONFIG,val)
@@ -1465,65 +1457,4 @@
 #define bfin_read_IMDMA_S1_IRQ_STATUS()      bfin_read16(IMDMA_S1_IRQ_STATUS)
 #define bfin_write_IMDMA_S1_IRQ_STATUS(val)  bfin_write16(IMDMA_S1_IRQ_STATUS,val)
 
-#define bfin_read_MDMA_S0_CONFIG()  bfin_read_MDMA1_S0_CONFIG()
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()  bfin_read_MDMA1_S0_IRQ_STATUS()
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
-#define bfin_read_MDMA_S0_X_MODIFY()  bfin_read_MDMA1_S0_X_MODIFY()
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
-#define bfin_read_MDMA_S0_Y_MODIFY()  bfin_read_MDMA1_S0_Y_MODIFY()
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
-#define bfin_read_MDMA_S0_X_COUNT()  bfin_read_MDMA1_S0_X_COUNT()
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
-#define bfin_read_MDMA_S0_Y_COUNT()  bfin_read_MDMA1_S0_Y_COUNT()
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
-#define bfin_read_MDMA_S0_START_ADDR()  bfin_read_MDMA1_S0_START_ADDR()
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
-#define bfin_read_MDMA_D0_CONFIG()  bfin_read_MDMA1_D0_CONFIG()
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()  bfin_read_MDMA1_D0_IRQ_STATUS()
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
-#define bfin_read_MDMA_D0_X_MODIFY()  bfin_read_MDMA1_D0_X_MODIFY()
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
-#define bfin_read_MDMA_D0_Y_MODIFY()  bfin_read_MDMA1_D0_Y_MODIFY()
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
-#define bfin_read_MDMA_D0_X_COUNT()  bfin_read_MDMA1_D0_X_COUNT()
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
-#define bfin_read_MDMA_D0_Y_COUNT()  bfin_read_MDMA1_D0_Y_COUNT()
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
-#define bfin_read_MDMA_D0_START_ADDR()  bfin_read_MDMA1_D0_START_ADDR()
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
-
-#define bfin_read_MDMA_S1_CONFIG()  bfin_read_MDMA1_S1_CONFIG()
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()  bfin_read_MDMA1_S1_IRQ_STATUS()
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val)
-#define bfin_read_MDMA_S1_X_MODIFY()  bfin_read_MDMA1_S1_X_MODIFY()
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val)
-#define bfin_read_MDMA_S1_Y_MODIFY()  bfin_read_MDMA1_S1_Y_MODIFY()
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val)
-#define bfin_read_MDMA_S1_X_COUNT()  bfin_read_MDMA1_S1_X_COUNT()
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val)
-#define bfin_read_MDMA_S1_Y_COUNT()  bfin_read_MDMA1_S1_Y_COUNT()
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val)
-#define bfin_read_MDMA_S1_START_ADDR()  bfin_read_MDMA1_S1_START_ADDR()
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val)
-#define bfin_read_MDMA_D1_CONFIG()  bfin_read_MDMA1_D1_CONFIG()
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()  bfin_read_MDMA1_D1_IRQ_STATUS()
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val)
-#define bfin_read_MDMA_D1_X_MODIFY()  bfin_read_MDMA1_D1_X_MODIFY()
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val)
-#define bfin_read_MDMA_D1_Y_MODIFY()  bfin_read_MDMA1_D1_Y_MODIFY()
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val)
-#define bfin_read_MDMA_D1_X_COUNT()  bfin_read_MDMA1_D1_X_COUNT()
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val)
-#define bfin_read_MDMA_D1_Y_COUNT()  bfin_read_MDMA1_D1_Y_COUNT()
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val)
-#define bfin_read_MDMA_D1_START_ADDR()  bfin_read_MDMA1_D1_START_ADDR()
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val)
-
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
 #endif                          /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 79e048d452e0..71e805ea74e5 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -1,18 +1,11 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
 
 #ifndef _DEF_BF561_H
 #define _DEF_BF561_H
-/*
-#if !defined(__ADSPBF561__)
-#warning defBF561.h should only be included for BF561 chip.
-#endif
-*/
-/* include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
 
 /*********************************************************************************** */
 /* System MMR Register Map */
@@ -311,10 +304,10 @@
 #define PPI1_FRAME                                      0xFFC01310      /* PPI1 Frame Length register */
 
 /*DMA traffic control registers */
-#define DMA1_TC_PER  0xFFC01B0C /* Traffic control periods */
-#define DMA1_TC_CNT  0xFFC01B10 /* Traffic control current counts */
-#define DMA2_TC_PER  0xFFC00B0C /* Traffic control periods */
-#define DMA2_TC_CNT  0xFFC00B10 /* Traffic control current counts        */
+#define DMAC0_TC_PER  0xFFC00B0C        /* Traffic control periods */
+#define DMAC0_TC_CNT  0xFFC00B10        /* Traffic control current counts        */
+#define DMAC1_TC_PER  0xFFC01B0C        /* Traffic control periods */
+#define DMAC1_TC_CNT  0xFFC01B10        /* Traffic control current counts */
 
 /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
 #define DMA1_0_CONFIG 0xFFC01C08        /* DMA1 Channel 0 Configuration register */
@@ -486,61 +479,61 @@
 #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC       /* DMA1 Channel 11 Peripheral Map Register */
 
 /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define MDMA1_D0_CONFIG 0xFFC01F08      /*MemDMA1 Stream 0 Destination Configuration */
-#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00       /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA1_D0_START_ADDR 0xFFC01F04  /*MemDMA1 Stream 0 Destination Start Address */
-#define MDMA1_D0_X_COUNT 0xFFC01F10     /*MemDMA1 Stream 0 Destination Inner-Loop Count */
-#define MDMA1_D0_Y_COUNT 0xFFC01F18     /*MemDMA1 Stream 0 Destination Outer-Loop Count */
-#define MDMA1_D0_X_MODIFY 0xFFC01F14    /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA1_D0_Y_MODIFY 0xFFC01F1C    /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20       /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA1_D0_CURR_ADDR 0xFFC01F24   /*MemDMA1 Stream 0 Destination Current Address */
-#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30        /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
-#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38        /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
-#define MDMA1_D0_IRQ_STATUS 0xFFC01F28  /*MemDMA1 Stream 0 Destination Interrupt/Status */
-#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C      /*MemDMA1 Stream 0 Destination Peripheral Map */
-
-#define MDMA1_S0_CONFIG 0xFFC01F48      /*MemDMA1 Stream 0 Source Configuration */
-#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40       /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA1_S0_START_ADDR 0xFFC01F44  /*MemDMA1 Stream 0 Source Start Address */
-#define MDMA1_S0_X_COUNT 0xFFC01F50     /*MemDMA1 Stream 0 Source Inner-Loop Count */
-#define MDMA1_S0_Y_COUNT 0xFFC01F58     /*MemDMA1 Stream 0 Source Outer-Loop Count */
-#define MDMA1_S0_X_MODIFY 0xFFC01F54    /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
-#define MDMA1_S0_Y_MODIFY 0xFFC01F5C    /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
-#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60       /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA1_S0_CURR_ADDR 0xFFC01F64   /*MemDMA1 Stream 0 Source Current Address */
-#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70        /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
-#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78        /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
-#define MDMA1_S0_IRQ_STATUS 0xFFC01F68  /*MemDMA1 Stream 0 Source Interrupt/Status */
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C      /*MemDMA1 Stream 0 Source Peripheral Map */
-
-#define MDMA1_D1_CONFIG 0xFFC01F88      /*MemDMA1 Stream 1 Destination Configuration */
-#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80       /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA1_D1_START_ADDR 0xFFC01F84  /*MemDMA1 Stream 1 Destination Start Address */
-#define MDMA1_D1_X_COUNT 0xFFC01F90     /*MemDMA1 Stream 1 Destination Inner-Loop Count */
-#define MDMA1_D1_Y_COUNT 0xFFC01F98     /*MemDMA1 Stream 1 Destination Outer-Loop Count */
-#define MDMA1_D1_X_MODIFY 0xFFC01F94    /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA1_D1_Y_MODIFY 0xFFC01F9C    /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0       /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
-#define MDMA1_D1_CURR_ADDR 0xFFC01FA4   /*MemDMA1 Stream 1 Dest Current Address */
-#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0        /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
-#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8        /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
-#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8  /*MemDMA1 Stream 1 Dest Interrupt/Status */
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC      /*MemDMA1 Stream 1 Dest Peripheral Map */
-
-#define MDMA1_S1_CONFIG 0xFFC01FC8      /*MemDMA1 Stream 1 Source Configuration */
-#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0       /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA1_S1_START_ADDR 0xFFC01FC4  /*MemDMA1 Stream 1 Source Start Address */
-#define MDMA1_S1_X_COUNT 0xFFC01FD0     /*MemDMA1 Stream 1 Source Inner-Loop Count */
-#define MDMA1_S1_Y_COUNT 0xFFC01FD8     /*MemDMA1 Stream 1 Source Outer-Loop Count */
-#define MDMA1_S1_X_MODIFY 0xFFC01FD4    /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
-#define MDMA1_S1_Y_MODIFY 0xFFC01FDC    /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0       /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA1_S1_CURR_ADDR 0xFFC01FE4   /*MemDMA1 Stream 1 Source Current Address */
-#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0        /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
-#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8        /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
-#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8  /*MemDMA1 Stream 1 Source Interrupt/Status */
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC      /*MemDMA1 Stream 1 Source Peripheral Map */
+#define MDMA_D2_CONFIG 0xFFC01F08       /*MemDMA1 Stream 0 Destination Configuration */
+#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00        /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA_D2_START_ADDR 0xFFC01F04   /*MemDMA1 Stream 0 Destination Start Address */
+#define MDMA_D2_X_COUNT 0xFFC01F10      /*MemDMA1 Stream 0 Destination Inner-Loop Count */
+#define MDMA_D2_Y_COUNT 0xFFC01F18      /*MemDMA1 Stream 0 Destination Outer-Loop Count */
+#define MDMA_D2_X_MODIFY 0xFFC01F14     /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA_D2_Y_MODIFY 0xFFC01F1C     /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20        /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA_D2_CURR_ADDR 0xFFC01F24    /*MemDMA1 Stream 0 Destination Current Address */
+#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
+#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
+#define MDMA_D2_IRQ_STATUS 0xFFC01F28   /*MemDMA1 Stream 0 Destination Interrupt/Status */
+#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C       /*MemDMA1 Stream 0 Destination Peripheral Map */
+
+#define MDMA_S2_CONFIG 0xFFC01F48       /*MemDMA1 Stream 0 Source Configuration */
+#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40        /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA_S2_START_ADDR 0xFFC01F44   /*MemDMA1 Stream 0 Source Start Address */
+#define MDMA_S2_X_COUNT 0xFFC01F50      /*MemDMA1 Stream 0 Source Inner-Loop Count */
+#define MDMA_S2_Y_COUNT 0xFFC01F58      /*MemDMA1 Stream 0 Source Outer-Loop Count */
+#define MDMA_S2_X_MODIFY 0xFFC01F54     /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
+#define MDMA_S2_Y_MODIFY 0xFFC01F5C     /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
+#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60        /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA_S2_CURR_ADDR 0xFFC01F64    /*MemDMA1 Stream 0 Source Current Address */
+#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
+#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
+#define MDMA_S2_IRQ_STATUS 0xFFC01F68   /*MemDMA1 Stream 0 Source Interrupt/Status */
+#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C       /*MemDMA1 Stream 0 Source Peripheral Map */
+
+#define MDMA_D3_CONFIG 0xFFC01F88       /*MemDMA1 Stream 1 Destination Configuration */
+#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80        /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA_D3_START_ADDR 0xFFC01F84   /*MemDMA1 Stream 1 Destination Start Address */
+#define MDMA_D3_X_COUNT 0xFFC01F90      /*MemDMA1 Stream 1 Destination Inner-Loop Count */
+#define MDMA_D3_Y_COUNT 0xFFC01F98      /*MemDMA1 Stream 1 Destination Outer-Loop Count */
+#define MDMA_D3_X_MODIFY 0xFFC01F94     /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA_D3_Y_MODIFY 0xFFC01F9C     /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0        /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
+#define MDMA_D3_CURR_ADDR 0xFFC01FA4    /*MemDMA1 Stream 1 Dest Current Address */
+#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
+#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
+#define MDMA_D3_IRQ_STATUS 0xFFC01FA8   /*MemDMA1 Stream 1 Dest Interrupt/Status */
+#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC       /*MemDMA1 Stream 1 Dest Peripheral Map */
+
+#define MDMA_S3_CONFIG 0xFFC01FC8       /*MemDMA1 Stream 1 Source Configuration */
+#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0        /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA_S3_START_ADDR 0xFFC01FC4   /*MemDMA1 Stream 1 Source Start Address */
+#define MDMA_S3_X_COUNT 0xFFC01FD0      /*MemDMA1 Stream 1 Source Inner-Loop Count */
+#define MDMA_S3_Y_COUNT 0xFFC01FD8      /*MemDMA1 Stream 1 Source Outer-Loop Count */
+#define MDMA_S3_X_MODIFY 0xFFC01FD4     /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
+#define MDMA_S3_Y_MODIFY 0xFFC01FDC     /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0        /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA_S3_CURR_ADDR 0xFFC01FE4    /*MemDMA1 Stream 1 Source Current Address */
+#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
+#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
+#define MDMA_S3_IRQ_STATUS 0xFFC01FE8   /*MemDMA1 Stream 1 Source Interrupt/Status */
+#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC       /*MemDMA1 Stream 1 Source Peripheral Map */
 
 /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
 #define DMA2_0_CONFIG 0xFFC00C08        /* DMA2 Channel 0 Configuration register */
@@ -712,117 +705,61 @@
 #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC       /* DMA2 Channel 11 Peripheral Map Register */
 
 /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define MDMA2_D0_CONFIG 0xFFC00F08      /*MemDMA2 Stream 0 Destination Configuration register */
-#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00       /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA2_D0_START_ADDR 0xFFC00F04  /*MemDMA2 Stream 0 Destination Start Address */
-#define MDMA2_D0_X_COUNT 0xFFC00F10     /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
-#define MDMA2_D0_Y_COUNT 0xFFC00F18     /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
-#define MDMA2_D0_X_MODIFY 0xFFC00F14    /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA2_D0_Y_MODIFY 0xFFC00F1C    /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20       /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA2_D0_CURR_ADDR 0xFFC00F24   /*MemDMA2 Stream 0 Destination Current Address */
-#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30        /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
-#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38        /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
-#define MDMA2_D0_IRQ_STATUS 0xFFC00F28  /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
-#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C      /*MemDMA2 Stream 0 Destination Peripheral Map register */
-
-#define MDMA2_S0_CONFIG 0xFFC00F48      /*MemDMA2 Stream 0 Source Configuration register */
-#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40       /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA2_S0_START_ADDR 0xFFC00F44  /*MemDMA2 Stream 0 Source Start Address */
-#define MDMA2_S0_X_COUNT 0xFFC00F50     /*MemDMA2 Stream 0 Source Inner-Loop Count register */
-#define MDMA2_S0_Y_COUNT 0xFFC00F58     /*MemDMA2 Stream 0 Source Outer-Loop Count register */
-#define MDMA2_S0_X_MODIFY 0xFFC00F54    /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
-#define MDMA2_S0_Y_MODIFY 0xFFC00F5C    /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
-#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60       /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA2_S0_CURR_ADDR 0xFFC00F64   /*MemDMA2 Stream 0 Source Current Address */
-#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70        /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
-#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78        /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
-#define MDMA2_S0_IRQ_STATUS 0xFFC00F68  /*MemDMA2 Stream 0 Source Interrupt/Status Register */
-#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C      /*MemDMA2 Stream 0 Source Peripheral Map register */
-
-#define MDMA2_D1_CONFIG 0xFFC00F88      /*MemDMA2 Stream 1 Destination Configuration register */
-#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80       /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA2_D1_START_ADDR 0xFFC00F84  /*MemDMA2 Stream 1 Destination Start Address */
-#define MDMA2_D1_X_COUNT 0xFFC00F90     /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
-#define MDMA2_D1_Y_COUNT 0xFFC00F98     /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
-#define MDMA2_D1_X_MODIFY 0xFFC00F94    /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA2_D1_Y_MODIFY 0xFFC00F9C    /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0       /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
-#define MDMA2_D1_CURR_ADDR 0xFFC00FA4   /*MemDMA2 Stream 1 Destination Current Address reg */
-#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0        /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
-#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8        /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
-#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8  /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
-#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC      /*MemDMA2 Stream 1 Destination Peripheral Map register */
-
-#define MDMA2_S1_CONFIG 0xFFC00FC8      /*MemDMA2 Stream 1 Source Configuration register */
-#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0       /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA2_S1_START_ADDR 0xFFC00FC4  /*MemDMA2 Stream 1 Source Start Address */
-#define MDMA2_S1_X_COUNT 0xFFC00FD0     /*MemDMA2 Stream 1 Source Inner-Loop Count register */
-#define MDMA2_S1_Y_COUNT 0xFFC00FD8     /*MemDMA2 Stream 1 Source Outer-Loop Count register */
-#define MDMA2_S1_X_MODIFY 0xFFC00FD4    /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
-#define MDMA2_S1_Y_MODIFY 0xFFC00FDC    /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0       /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA2_S1_CURR_ADDR 0xFFC00FE4   /*MemDMA2 Stream 1 Source Current Address */
-#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0        /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
-#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8        /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
-#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8  /*MemDMA2 Stream 1 Source Interrupt/Status Register */
-#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC      /*MemDMA2 Stream 1 Source Peripheral Map register */
-
-#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
-#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR
-#define MDMA_D0_CONFIG MDMA1_D0_CONFIG
-#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT
-#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY
-#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT
-#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY
-#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR
-#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR
-#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS
-#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP
-#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT
-#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT
-
-#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
-#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR
-#define MDMA_S0_CONFIG MDMA1_S0_CONFIG
-#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT
-#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY
-#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT
-#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY
-#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR
-#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR
-#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS
-#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP
-#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT
-#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT
-
-#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR
-#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR
-#define MDMA_D1_CONFIG MDMA1_D1_CONFIG
-#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT
-#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY
-#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT
-#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY
-#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR
-#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR
-#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS
-#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP
-#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT
-#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT
-
-#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR
-#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR
-#define MDMA_S1_CONFIG MDMA1_S1_CONFIG
-#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT
-#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY
-#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT
-#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY
-#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR
-#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR
-#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS
-#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP
-#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT
-#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT
+#define MDMA_D0_CONFIG 0xFFC00F08       /*MemDMA2 Stream 0 Destination Configuration register */
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00        /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA_D0_START_ADDR 0xFFC00F04   /*MemDMA2 Stream 0 Destination Start Address */
+#define MDMA_D0_X_COUNT 0xFFC00F10      /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
+#define MDMA_D0_Y_COUNT 0xFFC00F18      /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
+#define MDMA_D0_X_MODIFY 0xFFC00F14     /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA_D0_Y_MODIFY 0xFFC00F1C     /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20        /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA_D0_CURR_ADDR 0xFFC00F24    /*MemDMA2 Stream 0 Destination Current Address */
+#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
+#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
+#define MDMA_D0_IRQ_STATUS 0xFFC00F28   /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C       /*MemDMA2 Stream 0 Destination Peripheral Map register */
+
+#define MDMA_S0_CONFIG 0xFFC00F48       /*MemDMA2 Stream 0 Source Configuration register */
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40        /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA_S0_START_ADDR 0xFFC00F44   /*MemDMA2 Stream 0 Source Start Address */
+#define MDMA_S0_X_COUNT 0xFFC00F50      /*MemDMA2 Stream 0 Source Inner-Loop Count register */
+#define MDMA_S0_Y_COUNT 0xFFC00F58      /*MemDMA2 Stream 0 Source Outer-Loop Count register */
+#define MDMA_S0_X_MODIFY 0xFFC00F54     /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
+#define MDMA_S0_Y_MODIFY 0xFFC00F5C     /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
+#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60        /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA_S0_CURR_ADDR 0xFFC00F64    /*MemDMA2 Stream 0 Source Current Address */
+#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
+#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
+#define MDMA_S0_IRQ_STATUS 0xFFC00F68   /*MemDMA2 Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C       /*MemDMA2 Stream 0 Source Peripheral Map register */
+
+#define MDMA_D1_CONFIG 0xFFC00F88       /*MemDMA2 Stream 1 Destination Configuration register */
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80        /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA_D1_START_ADDR 0xFFC00F84   /*MemDMA2 Stream 1 Destination Start Address */
+#define MDMA_D1_X_COUNT 0xFFC00F90      /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
+#define MDMA_D1_Y_COUNT 0xFFC00F98      /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
+#define MDMA_D1_X_MODIFY 0xFFC00F94     /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA_D1_Y_MODIFY 0xFFC00F9C     /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0        /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
+#define MDMA_D1_CURR_ADDR 0xFFC00FA4    /*MemDMA2 Stream 1 Destination Current Address reg */
+#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
+#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
+#define MDMA_D1_IRQ_STATUS 0xFFC00FA8   /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC       /*MemDMA2 Stream 1 Destination Peripheral Map register */
+
+#define MDMA_S1_CONFIG 0xFFC00FC8       /*MemDMA2 Stream 1 Source Configuration register */
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0        /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA_S1_START_ADDR 0xFFC00FC4   /*MemDMA2 Stream 1 Source Start Address */
+#define MDMA_S1_X_COUNT 0xFFC00FD0      /*MemDMA2 Stream 1 Source Inner-Loop Count register */
+#define MDMA_S1_Y_COUNT 0xFFC00FD8      /*MemDMA2 Stream 1 Source Outer-Loop Count register */
+#define MDMA_S1_X_MODIFY 0xFFC00FD4     /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
+#define MDMA_S1_Y_MODIFY 0xFFC00FDC     /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0        /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA_S1_CURR_ADDR 0xFFC00FE4    /*MemDMA2 Stream 1 Source Current Address */
+#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
+#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
+#define MDMA_S1_IRQ_STATUS 0xFFC00FE8   /*MemDMA2 Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC       /*MemDMA2 Stream 1 Source Peripheral Map register */
 
 /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
 #define IMDMA_D0_CONFIG 0xFFC01808      /*IMDMA Stream 0 Destination Configuration */
@@ -927,83 +864,6 @@
 #define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
 
-/* ***************************** UART CONTROLLER MASKS ********************** */
-
-/* UART_LCR Register */
-
-#define DLAB    0x80
-#define SB      0x40
-#define STP      0x20
-#define EPS     0x10
-#define PEN     0x08
-#define STB     0x04
-#define WLS(x)  ((x-5) & 0x03)
-
-#define DLAB_P  0x07
-#define SB_P    0x06
-#define STP_P   0x05
-#define EPS_P   0x04
-#define PEN_P   0x03
-#define STB_P   0x02
-#define WLS_P1  0x01
-#define WLS_P0  0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA        0x10
-#define LOOP_ENA_P      0x04
-
-/* UART_LSR Register */
-#define TEMT    0x40
-#define THRE    0x20
-#define BI      0x10
-#define FE      0x08
-#define PE      0x04
-#define OE      0x02
-#define DR      0x01
-
-#define TEMP_P  0x06
-#define THRE_P  0x05
-#define BI_P    0x04
-#define FE_P    0x03
-#define PE_P    0x02
-#define OE_P    0x01
-#define DR_P    0x00
-
-/* UART_IER Register */
-#define ELSI    0x04
-#define ETBEI   0x02
-#define ERBFI   0x01
-
-#define ELSI_P  0x02
-#define ETBEI_P 0x01
-#define ERBFI_P 0x00
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define NINT            0x01
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-#define NINT_P          0x00
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UART_GCTL Register */
-#define FFE     0x20
-#define FPE     0x10
-#define RPOLC   0x08
-#define TPOLC   0x04
-#define IREN    0x02
-#define UCEN    0x01
-
-#define FFE_P   0x05
-#define FPE_P   0x04
-#define RPOLC_P 0x03
-#define TPOLC_P 0x02
-#define IREN_P  0x01
-#define UCEN_P  0x00
-
 /*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
 
 /*  PPI_CONTROL Masks         */
@@ -1230,44 +1090,6 @@
 #define ERR_TYP_P0              0x0E
 #define ERR_TYP_P1              0x0F
 
-/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-#define PF0         0x0001
-#define PF1         0x0002
-#define PF2         0x0004
-#define PF3         0x0008
-#define PF4         0x0010
-#define PF5         0x0020
-#define PF6         0x0040
-#define PF7         0x0080
-#define PF8         0x0100
-#define PF9         0x0200
-#define PF10        0x0400
-#define PF11        0x0800
-#define PF12        0x1000
-#define PF13        0x2000
-#define PF14        0x4000
-#define PF15        0x8000
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
-#define PF0_P         0
-#define PF1_P         1
-#define PF2_P         2
-#define PF3_P         3
-#define PF4_P         4
-#define PF5_P         5
-#define PF6_P         6
-#define PF7_P         7
-#define PF8_P         8
-#define PF9_P         9
-#define PF10_P        10
-#define PF11_P        11
-#define PF12_P        12
-#define PF13_P        13
-#define PF14_P        14
-#define PF15_P        15
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
 
 /* AMGCTL Masks */
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
index 4f8aa5d08802..57d5eab59faf 100644
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -62,4 +62,6 @@
 #define PORT_FIO1 GPIO_16
 #define PORT_FIO2 GPIO_32
 
+#include <mach-common/ports-f.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index 5b96ea549a04..4cc91995f781 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -106,7 +106,7 @@
 #define COREA_L1_SCRATCH_START  0xFFB00000
 #define COREB_L1_SCRATCH_START  0xFF700000
 
-#ifdef __ASSEMBLY__
+#ifdef CONFIG_SMP
 
 /*
  * The following macros both return the address of the PDA for the
@@ -121,8 +121,7 @@
  * is allowed to use the specified Dreg for determining the PDA
  * address to be returned into Preg.
  */
-#ifdef CONFIG_SMP
-#define GET_PDA_SAFE(preg)              \
+# define GET_PDA_SAFE(preg)             \
         preg.l = lo(DSPID);             \
         preg.h = hi(DSPID);             \
         preg = [preg];                  \
@@ -158,7 +157,7 @@
         preg = [preg];                  \
 4:
 
-#define GET_PDA(preg, dreg)             \
+# define GET_PDA(preg, dreg)            \
         preg.l = lo(DSPID);             \
         preg.h = hi(DSPID);             \
         dreg = [preg];                  \
@@ -169,13 +168,17 @@
         preg = [preg];                  \
 1:                                      \
 
-#define GET_CPUID(preg, dreg)           \
+# define GET_CPUID(preg, dreg)          \
         preg.l = lo(DSPID);             \
         preg.h = hi(DSPID);             \
         dreg = [preg];                  \
         dreg = ROT dreg BY -1;          \
         dreg = CC;
 
+# ifndef __ASSEMBLY__
+
+#  include <asm/processor.h>
+
 static inline unsigned long get_l1_scratch_start_cpu(int cpu)
 {
         return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
@@ -210,8 +213,7 @@ static inline unsigned long get_l1_data_b_start(void)
         return get_l1_data_b_start_cpu(blackfin_core_id());
 }
 
+# endif /* __ASSEMBLY__ */
 #endif /* CONFIG_SMP */
 
-#endif /* __ASSEMBLY__ */
-
 #endif
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
index f2b1fbdb8e72..7977db2f1c12 100644
--- a/arch/blackfin/mach-bf561/include/mach/pll.h
+++ b/arch/blackfin/mach-bf561/include/mach/pll.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,57 +7,48 @@
 #ifndef _MACH_PLL_H
 #define _MACH_PLL_H
 
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_SMP
+
 #include <asm/blackfin.h>
 #include <asm/irqflags.h>
+#include <mach/irq.h>
+
+#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
 
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+static inline void
+bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
 {
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SICA_IWR0);
-        iwr1 = bfin_read32(SICA_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-        bfin_write32(SICA_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SICA_IWR0, iwr0);
-        bfin_write32(SICA_IWR1, iwr1);
-        hard_local_irq_restore(flags);
+        unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
+
+        bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
+        bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
 }
+#define bfin_iwr_restore bfin_iwr_restore
 
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
+static inline void
+bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
+              unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
 {
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SICA_IWR0);
-        iwr1 = bfin_read32(SICA_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-        bfin_write32(SICA_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SICA_IWR0, iwr0);
-        bfin_write32(SICA_IWR1, iwr1);
-        hard_local_irq_restore(flags);
+        unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
+
+        *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
+        *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
+        bfin_iwr_restore(niwr0, niwr1, niwr2);
 }
+#define bfin_iwr_save bfin_iwr_save
+
+static inline void
+bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
+{
+        bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP), 0, iwr0, iwr1, iwr2);
+}
+
+#endif
+
+#endif
+
+#include <mach-common/pll.h>
 
-#endif /* _MACH_PLL_H */
+#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h
index 2c8c514dd386..346c60589be6 100644
--- a/arch/blackfin/mach-bf561/include/mach/smp.h
+++ b/arch/blackfin/mach-bf561/include/mach/smp.h
@@ -7,6 +7,8 @@
 #ifndef _MACH_BF561_SMP
 #define _MACH_BF561_SMP
 
+/* This header has to stand alone to avoid circular deps */
+
 struct task_struct;
 
 void platform_init_cpus(void);
@@ -17,13 +19,13 @@ int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
 
 void platform_secondary_init(unsigned int cpu);
 
-void platform_request_ipi(int (*handler)(int, void *));
+void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler);
 
-void platform_send_ipi(cpumask_t callmap);
+void platform_send_ipi(cpumask_t callmap, int irq);
 
-void platform_send_ipi_cpu(unsigned int cpu);
+void platform_send_ipi_cpu(unsigned int cpu, int irq);
 
-void platform_clear_ipi(unsigned int cpu);
+void platform_clear_ipi(unsigned int cpu, int irq);
 
 void bfin_local_timer_setup(void);
 
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index f540ed1257d6..1074a7ef81c7 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
 
         spin_lock(&boot_lock);
 
-        if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) {
+        if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
                 /* CoreB already running, sending ipi to wakeup it */
                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
         } else {
                 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
-                bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT);
+                bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
                 SSYNC();
         }
 
@@ -111,41 +111,46 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
                 panic("CPU%u: processor failed to boot\n", cpu);
 }
 
-void __init platform_request_ipi(irq_handler_t handler)
+static const char supple0[] = "IRQ_SUPPLE_0";
+static const char supple1[] = "IRQ_SUPPLE_1";
+void __init platform_request_ipi(int irq, void *handler)
 {
         int ret;
+        const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
 
-        ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
-                          "Supplemental Interrupt0", handler);
+        ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_PERCPU, name, handler);
         if (ret)
-                panic("Cannot request supplemental interrupt 0 for IPI service");
+                panic("Cannot request %s for IPI service", name);
 }
 
-void platform_send_ipi(cpumask_t callmap)
+void platform_send_ipi(cpumask_t callmap, int irq)
 {
         unsigned int cpu;
+        int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
 
         for_each_cpu_mask(cpu, callmap) {
                 BUG_ON(cpu >= 2);
                 SSYNC();
-                bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
+                bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
                 SSYNC();
         }
 }
 
-void platform_send_ipi_cpu(unsigned int cpu)
+void platform_send_ipi_cpu(unsigned int cpu, int irq)
 {
+        int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
         BUG_ON(cpu >= 2);
         SSYNC();
-        bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
+        bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
         SSYNC();
 }
 
-void platform_clear_ipi(unsigned int cpu)
+void platform_clear_ipi(unsigned int cpu, int irq)
 {
+        int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
         BUG_ON(cpu >= 2);
         SSYNC();
-        bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));
+        bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
         SSYNC();
 }
 
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 2ca915ee181f..bc08c98d008d 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -615,7 +615,7 @@ ENTRY(_system_call)
 #ifdef CONFIG_IPIPE
         r0 = sp;
         SP += -12;
-        call ___ipipe_syscall_root;
+        pseudo_long_call ___ipipe_syscall_root, p0;
         SP += 12;
         cc = r0 == 1;
         if cc jump .Lsyscall_really_exit;
@@ -692,7 +692,7 @@ ENTRY(_system_call)
         [--sp] = reti;
         SP += 4; /* don't merge with next insn to keep the pattern obvious */
         SP += -12;
-        call ___ipipe_sync_root;
+        pseudo_long_call ___ipipe_sync_root, p4;
         SP += 12;
         jump .Lresume_userspace_1;
 .Lsyscall_no_irqsync:
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index da7e3c63746b..a604f19d8dc3 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -866,7 +866,6 @@ static void bfin_gpio_unmask_irq(unsigned int irq)
         u32 pintbit = PINT_BIT(pint_val);
         u32 bank = PINT_2_BANK(pint_val);
 
-        pint[bank]->request = pintbit;
         pint[bank]->mask_set = pintbit;
 }
 
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 80884b136a0c..42fa87e8375c 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -23,9 +23,6 @@
 
 void bfin_pm_suspend_standby_enter(void)
 {
-        unsigned long flags;
-
-        flags = hard_local_irq_save();
         bfin_pm_standby_setup();
 
 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
@@ -55,8 +52,6 @@ void bfin_pm_suspend_standby_enter(void)
 #else
         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
-
-        hard_local_irq_restore(flags);
 }
 
 int bf53x_suspend_l1_mem(unsigned char *memptr)
@@ -127,7 +122,6 @@ static void flushinv_all_dcache(void)
 
 int bfin_pm_suspend_mem_enter(void)
 {
-        unsigned long flags;
         int wakeup, ret;
 
         unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
@@ -149,12 +143,9 @@ int bfin_pm_suspend_mem_enter(void)
         wakeup |= GPWE;
 #endif
 
-        flags = hard_local_irq_save();
-
         ret = blackfin_dma_suspend();
 
         if (ret) {
-                hard_local_irq_restore(flags);
                 kfree(memptr);
                 return ret;
         }
@@ -178,7 +169,6 @@ int bfin_pm_suspend_mem_enter(void)
         bfin_gpio_pm_hibernate_restore();
         blackfin_dma_resume();
 
-        hard_local_irq_restore(flags);
         kfree(memptr);
 
         return 0;
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index a17107a700d5..9f251406a76a 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -19,6 +19,7 @@
 #include <linux/mm.h>
 #include <linux/cpu.h>
 #include <linux/smp.h>
+#include <linux/cpumask.h>
 #include <linux/seq_file.h>
 #include <linux/irq.h>
 #include <linux/slab.h>
@@ -43,12 +44,6 @@ void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
         *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
         *init_saved_dcplb_fault_addr_coreb;
 
-cpumask_t cpu_possible_map;
-EXPORT_SYMBOL(cpu_possible_map);
-
-cpumask_t cpu_online_map;
-EXPORT_SYMBOL(cpu_online_map);
-
 #define BFIN_IPI_RESCHEDULE   0
 #define BFIN_IPI_CALL_FUNC    1
 #define BFIN_IPI_CPU_STOP     2
@@ -65,8 +60,7 @@ struct smp_call_struct {
         void (*func)(void *info);
         void *info;
         int wait;
-        cpumask_t pending;
-        cpumask_t waitmask;
+        cpumask_t *waitmask;
 };
 
 static struct blackfin_flush_data smp_flush_data;
@@ -74,15 +68,19 @@ static struct blackfin_flush_data smp_flush_data;
 static DEFINE_SPINLOCK(stop_lock);
 
 struct ipi_message {
-        struct list_head list;
         unsigned long type;
         struct smp_call_struct call_struct;
 };
 
+/* A magic number - stress test shows this is safe for common cases */
+#define BFIN_IPI_MSGQ_LEN 5
+
+/* Simple FIFO buffer, overflow leads to panic */
 struct ipi_message_queue {
-        struct list_head head;
         spinlock_t lock;
         unsigned long count;
+        unsigned long head; /* head of the queue */
+        struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
 };
 
 static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
@@ -121,7 +119,6 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
         func = msg->call_struct.func;
         info = msg->call_struct.info;
         wait = msg->call_struct.wait;
-        cpu_clear(cpu, msg->call_struct.pending);
         func(info);
         if (wait) {
 #ifdef __ARCH_SYNC_CORE_DCACHE
@@ -132,51 +129,57 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
                  */
                 resync_core_dcache();
 #endif
-                cpu_clear(cpu, msg->call_struct.waitmask);
-        } else
-                kfree(msg);
+                cpu_clear(cpu, *msg->call_struct.waitmask);
+        }
+}
+
+/* Use IRQ_SUPPLE_0 to request reschedule.
+ * When returning from interrupt to user space,
+ * there is chance to reschedule */
+static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
+{
+        unsigned int cpu = smp_processor_id();
+
+        platform_clear_ipi(cpu, IRQ_SUPPLE_0);
+        return IRQ_HANDLED;
 }
 
-static irqreturn_t ipi_handler(int irq, void *dev_instance)
+static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
 {
         struct ipi_message *msg;
         struct ipi_message_queue *msg_queue;
         unsigned int cpu = smp_processor_id();
+        unsigned long flags;
 
-        platform_clear_ipi(cpu);
+        platform_clear_ipi(cpu, IRQ_SUPPLE_1);
 
         msg_queue = &__get_cpu_var(ipi_msg_queue);
-        msg_queue->count++;
 
-        spin_lock(&msg_queue->lock);
-        while (!list_empty(&msg_queue->head)) {
-                msg = list_entry(msg_queue->head.next, typeof(*msg), list);
-                list_del(&msg->list);
+        spin_lock_irqsave(&msg_queue->lock, flags);
+
+        while (msg_queue->count) {
+                msg = &msg_queue->ipi_message[msg_queue->head];
                 switch (msg->type) {
-                case BFIN_IPI_RESCHEDULE:
-                        /* That's the easiest one; leave it to
-                         * return_from_int. */
-                        kfree(msg);
-                        break;
                 case BFIN_IPI_CALL_FUNC:
-                        spin_unlock(&msg_queue->lock);
+                        spin_unlock_irqrestore(&msg_queue->lock, flags);
                         ipi_call_function(cpu, msg);
-                        spin_lock(&msg_queue->lock);
+                        spin_lock_irqsave(&msg_queue->lock, flags);
                         break;
                 case BFIN_IPI_CPU_STOP:
-                        spin_unlock(&msg_queue->lock);
+                        spin_unlock_irqrestore(&msg_queue->lock, flags);
                         ipi_cpu_stop(cpu);
-                        spin_lock(&msg_queue->lock);
-                        kfree(msg);
+                        spin_lock_irqsave(&msg_queue->lock, flags);
                         break;
                 default:
                         printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
                                cpu, msg->type);
-                        kfree(msg);
                         break;
                 }
+                msg_queue->head++;
+                msg_queue->head %= BFIN_IPI_MSGQ_LEN;
+                msg_queue->count--;
         }
-        spin_unlock(&msg_queue->lock);
+        spin_unlock_irqrestore(&msg_queue->lock, flags);
         return IRQ_HANDLED;
 }
 
@@ -186,48 +189,47 @@ static void ipi_queue_init(void)
         struct ipi_message_queue *msg_queue;
         for_each_possible_cpu(cpu) {
                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
-                INIT_LIST_HEAD(&msg_queue->head);
                 spin_lock_init(&msg_queue->lock);
                 msg_queue->count = 0;
+                msg_queue->head = 0;
         }
 }
 
-int smp_call_function(void (*func)(void *info), void *info, int wait)
+static inline void smp_send_message(cpumask_t callmap, unsigned long type,
+                                        void (*func) (void *info), void *info, int wait)
 {
         unsigned int cpu;
-        cpumask_t callmap;
-        unsigned long flags;
         struct ipi_message_queue *msg_queue;
         struct ipi_message *msg;
-
-        callmap = cpu_online_map;
-        cpu_clear(smp_processor_id(), callmap);
-        if (cpus_empty(callmap))
-                return 0;
-
-        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
-        if (!msg)
-                return -ENOMEM;
-        INIT_LIST_HEAD(&msg->list);
-        msg->call_struct.func = func;
-        msg->call_struct.info = info;
-        msg->call_struct.wait = wait;
-        msg->call_struct.pending = callmap;
-        msg->call_struct.waitmask = callmap;
-        msg->type = BFIN_IPI_CALL_FUNC;
+        unsigned long flags, next_msg;
+        cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
 
         for_each_cpu_mask(cpu, callmap) {
                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
                 spin_lock_irqsave(&msg_queue->lock, flags);
-                list_add_tail(&msg->list, &msg_queue->head);
+                if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
+                        next_msg = (msg_queue->head + msg_queue->count)
+                                        % BFIN_IPI_MSGQ_LEN;
+                        msg = &msg_queue->ipi_message[next_msg];
+                        msg->type = type;
+                        if (type == BFIN_IPI_CALL_FUNC) {
+                                msg->call_struct.func = func;
+                                msg->call_struct.info = info;
+                                msg->call_struct.wait = wait;
+                                msg->call_struct.waitmask = &waitmask;
+                        }
+                        msg_queue->count++;
+                } else
+                        panic("IPI message queue overflow\n");
                 spin_unlock_irqrestore(&msg_queue->lock, flags);
-                platform_send_ipi_cpu(cpu);
+                platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
         }
+
         if (wait) {
-                while (!cpus_empty(msg->call_struct.waitmask))
+                while (!cpus_empty(waitmask))
                         blackfin_dcache_invalidate_range(
-                                (unsigned long)(&msg->call_struct.waitmask),
-                                (unsigned long)(&msg->call_struct.waitmask));
+                                (unsigned long)(&waitmask),
+                                (unsigned long)(&waitmask));
 #ifdef __ARCH_SYNC_CORE_DCACHE
                 /*
                  * Invalidate D cache in case shared data was changed by
@@ -235,8 +237,20 @@ int smp_call_function(void (*func)(void *info), void *info, int wait)
                  */
                 resync_core_dcache();
 #endif
-                kfree(msg);
         }
+}
+
+int smp_call_function(void (*func)(void *info), void *info, int wait)
+{
+        cpumask_t callmap;
+
+        callmap = cpu_online_map;
+        cpu_clear(smp_processor_id(), callmap);
+        if (cpus_empty(callmap))
+                return 0;
+
+        smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
+
         return 0;
 }
 EXPORT_SYMBOL_GPL(smp_call_function);
@@ -246,100 +260,39 @@ int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
 {
         unsigned int cpu = cpuid;
         cpumask_t callmap;
-        unsigned long flags;
-        struct ipi_message_queue *msg_queue;
-        struct ipi_message *msg;
 
         if (cpu_is_offline(cpu))
                 return 0;
         cpus_clear(callmap);
         cpu_set(cpu, callmap);
 
-        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
-        if (!msg)
-                return -ENOMEM;
-        INIT_LIST_HEAD(&msg->list);
-        msg->call_struct.func = func;
-        msg->call_struct.info = info;
-        msg->call_struct.wait = wait;
-        msg->call_struct.pending = callmap;
-        msg->call_struct.waitmask = callmap;
-        msg->type = BFIN_IPI_CALL_FUNC;
-
-        msg_queue = &per_cpu(ipi_msg_queue, cpu);
-        spin_lock_irqsave(&msg_queue->lock, flags);
-        list_add_tail(&msg->list, &msg_queue->head);
-        spin_unlock_irqrestore(&msg_queue->lock, flags);
-        platform_send_ipi_cpu(cpu);
+        smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
 
-        if (wait) {
-                while (!cpus_empty(msg->call_struct.waitmask))
-                        blackfin_dcache_invalidate_range(
-                                (unsigned long)(&msg->call_struct.waitmask),
-                                (unsigned long)(&msg->call_struct.waitmask));
-#ifdef __ARCH_SYNC_CORE_DCACHE
-                /*
-                 * Invalidate D cache in case shared data was changed by
-                 * other processors to ensure cache coherence.
-                 */
-                resync_core_dcache();
-#endif
-                kfree(msg);
-        }
         return 0;
 }
 EXPORT_SYMBOL_GPL(smp_call_function_single);
 
 void smp_send_reschedule(int cpu)
 {
-        unsigned long flags;
-        struct ipi_message_queue *msg_queue;
-        struct ipi_message *msg;
-
+        /* simply trigger an ipi */
         if (cpu_is_offline(cpu))
                 return;
-
-        msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
-        if (!msg)
-                return;
-        INIT_LIST_HEAD(&msg->list);
-        msg->type = BFIN_IPI_RESCHEDULE;
-
-        msg_queue = &per_cpu(ipi_msg_queue, cpu);
-        spin_lock_irqsave(&msg_queue->lock, flags);
-        list_add_tail(&msg->list, &msg_queue->head);
-        spin_unlock_irqrestore(&msg_queue->lock, flags);
-        platform_send_ipi_cpu(cpu);
+        platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
 
         return;
 }
 
 void smp_send_stop(void)
 {
-        unsigned int cpu;
         cpumask_t callmap;
-        unsigned long flags;
-        struct ipi_message_queue *msg_queue;
-        struct ipi_message *msg;
 
         callmap = cpu_online_map;
         cpu_clear(smp_processor_id(), callmap);
         if (cpus_empty(callmap))
                 return;
 
-        msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
-        if (!msg)
-                return;
-        INIT_LIST_HEAD(&msg->list);
-        msg->type = BFIN_IPI_CPU_STOP;
+        smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
 
-        for_each_cpu_mask(cpu, callmap) {
-                msg_queue = &per_cpu(ipi_msg_queue, cpu);
-                spin_lock_irqsave(&msg_queue->lock, flags);
-                list_add_tail(&msg->list, &msg_queue->head);
-                spin_unlock_irqrestore(&msg_queue->lock, flags);
-                platform_send_ipi_cpu(cpu);
-        }
         return;
 }
 
@@ -446,7 +399,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 {
         platform_prepare_cpus(max_cpus);
         ipi_queue_init();
-        platform_request_ipi(&ipi_handler);
+        platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
+        platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
 }
 
 void __init smp_cpus_done(unsigned int max_cpus)
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index 627e04b5ba9a..dfd304a4a3ea 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -704,18 +704,18 @@ int sram_free_with_lsl(const void *addr)
 {
         struct sram_list_struct *lsl, **tmp;
         struct mm_struct *mm = current->mm;
+        int ret = -1;
 
         for (tmp = &mm->context.sram_list; *tmp; tmp = &(*tmp)->next)
-                if ((*tmp)->addr == addr)
-                        goto found;
-        return -1;
-found:
-        lsl = *tmp;
-        sram_free(addr);
-        *tmp = lsl->next;
-        kfree(lsl);
+                if ((*tmp)->addr == addr) {
+                        lsl = *tmp;
+                        ret = sram_free(addr);
+                        *tmp = lsl->next;
+                        kfree(lsl);
+                        break;
+                }
 
-        return 0;
+        return ret;
 }
 EXPORT_SYMBOL(sram_free_with_lsl);
 
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index c6c90f39f4d9..7b897b7b0ae6 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -477,6 +477,12 @@ acpi_numa_processor_affinity_init(struct acpi_srat_cpu_affinity *pa)
         if (!(pa->flags & ACPI_SRAT_CPU_ENABLED))
                 return;
 
+        if (srat_num_cpus >= ARRAY_SIZE(node_cpuid)) {
+                printk_once(KERN_WARNING
+                            "node_cpuid[%d] is too small, may not be able to use all cpus\n",
+                            ARRAY_SIZE(node_cpuid));
+                return;
+        }
         pxm = get_processor_proximity_domain(pa);
 
         /* record this node in proximity bitmap */
diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c
index 9a26015c3e50..38c07b866901 100644
--- a/arch/ia64/kernel/irq_ia64.c
+++ b/arch/ia64/kernel/irq_ia64.c
@@ -633,7 +633,7 @@ ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
         BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
         desc = irq_desc + irq;
         desc->status |= IRQ_PER_CPU;
-        desc->chip = &irq_type_ia64_lsapic;
+        set_irq_chip(irq, &irq_type_ia64_lsapic);
         if (action)
                 setup_irq(irq, action);
         set_irq_handler(irq, handle_percpu_irq);
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 39e534f5a3b0..d92d5b5161fc 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -829,10 +829,9 @@ pfm_rvmalloc(unsigned long size)
         unsigned long addr;
 
         size = PAGE_ALIGN(size);
-        mem  = vmalloc(size);
+        mem  = vzalloc(size);
         if (mem) {
                 //printk("perfmon: CPU%d pfm_rvmalloc(%ld)=%p\n", smp_processor_id(), size, mem);
-                memset(mem, 0, size);
                 addr = (unsigned long)mem;
                 while (size > 0) {
                         pfm_reserve_page(addr);
@@ -1542,7 +1541,7 @@ pfm_exit_smpl_buffer(pfm_buffer_fmt_t *fmt)
  * any operations on the root directory. However, we need a non-trivial
  * d_name - pfm: will go nicely and kill the special-casing in procfs.
  */
-static struct vfsmount *pfmfs_mnt;
+static struct vfsmount *pfmfs_mnt __read_mostly;
 
 static int __init
 init_pfm_fs(void)
@@ -2185,7 +2184,7 @@ static const struct file_operations pfm_file_ops = {
 };
 
 static int
-pfmfs_delete_dentry(struct dentry *dentry)
+pfmfs_delete_dentry(const struct dentry *dentry)
 {
         return 1;
 }
@@ -2233,7 +2232,7 @@ pfm_alloc_file(pfm_context_t *ctx)
         }
         path.mnt = mntget(pfmfs_mnt);
 
-        path.dentry->d_op = &pfmfs_dentry_operations;
+        d_set_d_op(path.dentry, &pfmfs_dentry_operations);
         d_add(path.dentry, inode);
 
         file = alloc_file(&path, FMODE_READ, &pfm_file_ops);
diff --git a/arch/ia64/kernel/smp.c b/arch/ia64/kernel/smp.c
index dabeefe21134..be450a3e9871 100644
--- a/arch/ia64/kernel/smp.c
+++ b/arch/ia64/kernel/smp.c
@@ -293,6 +293,7 @@ smp_flush_tlb_all (void)
 void
 smp_flush_tlb_mm (struct mm_struct *mm)
 {
+        cpumask_var_t cpus;
         preempt_disable();
         /* this happens for the common case of a single-threaded fork():  */
         if (likely(mm == current->active_mm && atomic_read(&mm->mm_users) == 1))
@@ -301,9 +302,15 @@ smp_flush_tlb_mm (struct mm_struct *mm)
                 preempt_enable();
                 return;
         }
-
-        smp_call_function_many(mm_cpumask(mm),
-                (void (*)(void *))local_finish_flush_tlb_mm, mm, 1);
+        if (!alloc_cpumask_var(&cpus, GFP_ATOMIC)) {
+                smp_call_function((void (*)(void *))local_finish_flush_tlb_mm,
+                        mm, 1);
+        } else {
+                cpumask_copy(cpus, mm_cpumask(mm));
+                smp_call_function_many(cpus,
+                        (void (*)(void *))local_finish_flush_tlb_mm, mm, 1);
+                free_cpumask_var(cpus);
+        }
         local_irq_disable();
         local_finish_flush_tlb_mm(mm);
         local_irq_enable();
diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c
index ed6f22eb5b12..9702fa92489e 100644
--- a/arch/ia64/kernel/time.c
+++ b/arch/ia64/kernel/time.c
@@ -168,7 +168,7 @@ timer_interrupt (int irq, void *dev_id)
 {
         unsigned long new_itm;
 
-        if (unlikely(cpu_is_offline(smp_processor_id()))) {
+        if (cpu_is_offline(smp_processor_id())) {
                 return IRQ_HANDLED;
         }
 
diff --git a/arch/m68k/include/asm/sun3_pgtable.h b/arch/m68k/include/asm/sun3_pgtable.h
index cf5fad9b5250..f55aa04161e8 100644
--- a/arch/m68k/include/asm/sun3_pgtable.h
+++ b/arch/m68k/include/asm/sun3_pgtable.h
@@ -217,9 +217,8 @@ static inline pte_t pgoff_to_pte(unsigned off)
 /* Find an entry in the third-level pagetable. */
 #define pte_index(address) ((address >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
 #define pte_offset_kernel(pmd, address) ((pte_t *) __pmd_page(*pmd) + pte_index(address))
-/* FIXME: should we bother with kmap() here? */
-#define pte_offset_map(pmd, address) ((pte_t *)kmap(pmd_page(*pmd)) + pte_index(address))
-#define pte_unmap(pte) kunmap(pte)
+#define pte_offset_map(pmd, address) ((pte_t *)page_address(pmd_page(*pmd)) + pte_index(address))
+#define pte_unmap(pte) do { } while (0)
 
 /* Macros to (de)construct the fake PTEs representing swap pages. */
 #define __swp_type(x)           ((x).val & 0x7F)
diff --git a/arch/m68k/include/asm/thread_info.h b/arch/m68k/include/asm/thread_info.h
index 1da5d53a00eb..790988967ba7 100644
--- a/arch/m68k/include/asm/thread_info.h
+++ b/arch/m68k/include/asm/thread_info.h
@@ -104,5 +104,6 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_SYSCALL_TRACE       15      /* syscall trace active */
 #define TIF_MEMDIE              16      /* is terminating due to OOM killer */
 #define TIF_FREEZE              17      /* thread is freezing for suspend */
+#define TIF_RESTORE_SIGMASK     18      /* restore signal mask in do_signal */
 
 #endif  /* _ASM_M68K_THREAD_INFO_H */
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index b43b36beafe3..26d851d385bb 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -373,6 +373,7 @@
 #define __ARCH_WANT_SYS_SIGPENDING
 #define __ARCH_WANT_SYS_SIGPROCMASK
 #define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
 
 /*
  * "Conditional" syscalls
diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S
index 6360c437dcf5..1559dea36e55 100644
--- a/arch/m68k/kernel/entry.S
+++ b/arch/m68k/kernel/entry.S
@@ -99,7 +99,10 @@ do_trace_exit:
         jra     .Lret_from_exception
 
 ENTRY(ret_from_signal)
-        RESTORE_SWITCH_STACK
+        tstb    %curptr@(TASK_INFO+TINFO_FLAGS+2)
+        jge     1f
+        jbsr    syscall_trace
+1:      RESTORE_SWITCH_STACK
         addql   #4,%sp
 /* on 68040 complete pending writebacks if any */
 #ifdef CONFIG_M68040
@@ -174,16 +177,11 @@ do_signal_return:
         subql   #4,%sp                  | dummy return address
         SAVE_SWITCH_STACK
         pea     %sp@(SWITCH_STACK_SIZE)
-        clrl    %sp@-
         bsrl    do_signal
-        addql   #8,%sp
+        addql   #4,%sp
         RESTORE_SWITCH_STACK
         addql   #4,%sp
-        tstl    %d0
-        jeq     resume_userspace
-        | when single stepping into handler stop at the first insn
-        btst    #6,%curptr@(TASK_INFO+TINFO_FLAGS+2)
-        jeq     resume_userspace
+        jbra    resume_userspace
 
 do_delayed_trace:
         bclr    #7,%sp@(PT_OFF_SR)      | clear trace bit in SR
@@ -290,22 +288,6 @@ ENTRY(sys_vfork)
         RESTORE_SWITCH_STACK
         rts
 
-ENTRY(sys_sigsuspend)
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        jbsr    do_sigsuspend
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(sys_rt_sigsuspend)
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        jbsr    do_rt_sigsuspend
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        rts
-
 ENTRY(sys_sigreturn)
         SAVE_SWITCH_STACK
         jbsr    do_sigreturn
diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c
index 4b387538706f..d12c3b0d9e4f 100644
--- a/arch/m68k/kernel/signal.c
+++ b/arch/m68k/kernel/signal.c
@@ -51,8 +51,6 @@
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 
-asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs);
-
 const int frame_extra_sizes[16] = {
   [1]   = -1, /* sizeof(((struct frame *)0)->un.fmt1), */
   [2]   = sizeof(((struct frame *)0)->un.fmt2),
@@ -74,51 +72,21 @@ const int frame_extra_sizes[16] = {
 /*
  * Atomically swap in the new signal mask, and wait for a signal.
  */
-asmlinkage int do_sigsuspend(struct pt_regs *regs)
+asmlinkage int
+sys_sigsuspend(int unused0, int unused1, old_sigset_t mask)
 {
-        old_sigset_t mask = regs->d3;
-        sigset_t saveset;
-
         mask &= _BLOCKABLE;
-        saveset = current->blocked;
+        spin_lock_irq(&current->sighand->siglock);
+        current->saved_sigmask = current->blocked;
         siginitset(&current->blocked, mask);
         recalc_sigpending();
+        spin_unlock_irq(&current->sighand->siglock);
 
-        regs->d0 = -EINTR;
-        while (1) {
-                current->state = TASK_INTERRUPTIBLE;
-                schedule();
-                if (do_signal(&saveset, regs))
-                        return -EINTR;
-        }
-}
-
-asmlinkage int
-do_rt_sigsuspend(struct pt_regs *regs)
-{
-        sigset_t __user *unewset = (sigset_t __user *)regs->d1;
-        size_t sigsetsize = (size_t)regs->d2;
-        sigset_t saveset, newset;
-
-        /* XXX: Don't preclude handling different sized sigset_t's.  */
-        if (sigsetsize != sizeof(sigset_t))
-                return -EINVAL;
+        current->state = TASK_INTERRUPTIBLE;
+        schedule();
+        set_restore_sigmask();
 
-        if (copy_from_user(&newset, unewset, sizeof(newset)))
-                return -EFAULT;
-        sigdelsetmask(&newset, ~_BLOCKABLE);
-
-        saveset = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-
-        regs->d0 = -EINTR;
-        while (1) {
-                current->state = TASK_INTERRUPTIBLE;
-                schedule();
-                if (do_signal(&saveset, regs))
-                        return -EINTR;
-        }
+        return -ERESTARTNOHAND;
 }
 
 asmlinkage int
@@ -132,10 +100,10 @@ sys_sigaction(int sig, const struct old_sigaction __user *act,
                 old_sigset_t mask;
                 if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
                     __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
-                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
+                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
+                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
+                    __get_user(mask, &act->sa_mask))
                         return -EFAULT;
-                __get_user(new_ka.sa.sa_flags, &act->sa_flags);
-                __get_user(mask, &act->sa_mask);
                 siginitset(&new_ka.sa.sa_mask, mask);
         }
 
@@ -144,10 +112,10 @@ sys_sigaction(int sig, const struct old_sigaction __user *act,
         if (!ret && oact) {
                 if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
                     __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
-                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
+                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
+                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
+                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
                         return -EFAULT;
-                __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
-                __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
         }
 
         return ret;
@@ -318,36 +286,10 @@ out:
         return err;
 }
 
-static inline int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp,
-                   int *pd0)
+static int mangle_kernel_stack(struct pt_regs *regs, int formatvec,
+                               void __user *fp)
 {
-        int fsize, formatvec;
-        struct sigcontext context;
-        int err;
-
-        /* Always make any pending restarted system calls return -EINTR */
-        current_thread_info()->restart_block.fn = do_no_restart_syscall;
-
-        /* get previous context */
-        if (copy_from_user(&context, usc, sizeof(context)))
-                goto badframe;
-
-        /* restore passed registers */
-        regs->d1 = context.sc_d1;
-        regs->a0 = context.sc_a0;
-        regs->a1 = context.sc_a1;
-        regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
-        regs->pc = context.sc_pc;
-        regs->orig_d0 = -1;             /* disable syscall checks */
-        wrusp(context.sc_usp);
-        formatvec = context.sc_formatvec;
-        regs->format = formatvec >> 12;
-        regs->vector = formatvec & 0xfff;
-
-        err = restore_fpu_state(&context);
-
-        fsize = frame_extra_sizes[regs->format];
+        int fsize = frame_extra_sizes[formatvec >> 12];
         if (fsize < 0) {
                 /*
                  * user process trying to return with weird frame format
@@ -355,16 +297,22 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __u
 #ifdef DEBUG
                 printk("user process returning with weird frame format\n");
 #endif
-                goto badframe;
+                return 1;
         }
+        if (!fsize) {
+                regs->format = formatvec >> 12;
+                regs->vector = formatvec & 0xfff;
+        } else {
+                struct switch_stack *sw = (struct switch_stack *)regs - 1;
+                unsigned long buf[fsize / 2]; /* yes, twice as much */
 
-        /* OK.  Make room on the supervisor stack for the extra junk,
-         * if necessary.
-         */
+                /* that'll make sure that expansion won't crap over data */
+                if (copy_from_user(buf + fsize / 4, fp, fsize))
+                        return 1;
 
-        if (fsize) {
-                struct switch_stack *sw = (struct switch_stack *)regs - 1;
-                regs->d0 = context.sc_d0;
+                /* point of no return */
+                regs->format = formatvec >> 12;
+                regs->vector = formatvec & 0xfff;
 #define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
                 __asm__ __volatile__
                         ("   movel %0,%/a0\n\t"
@@ -376,30 +324,50 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __u
                          "   lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */
                          "   lsrl  #2,%1\n\t"
                          "   subql #1,%1\n\t"
-                         "2: movesl %4@+,%2\n\t"
-                         "3: movel %2,%/a0@+\n\t"
+                         /* copy to the gap we'd made */
+                         "2: movel %4@+,%/a0@+\n\t"
                          "   dbra %1,2b\n\t"
                          "   bral ret_from_signal\n"
-                         "4:\n"
-                         ".section __ex_table,\"a\"\n"
-                         "   .align 4\n"
-                         "   .long 2b,4b\n"
-                         "   .long 3b,4b\n"
-                         ".previous"
                          : /* no outputs, it doesn't ever return */
                          : "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
-                           "n" (frame_offset), "a" (fp)
+                           "n" (frame_offset), "a" (buf + fsize/4)
                          : "a0");
 #undef frame_offset
-                /*
-                 * If we ever get here an exception occurred while
-                 * building the above stack-frame.
-                 */
-                goto badframe;
         }
+        return 0;
+}
 
-        *pd0 = context.sc_d0;
-        return err;
+static inline int
+restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp)
+{
+        int formatvec;
+        struct sigcontext context;
+        int err;
+
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+
+        /* get previous context */
+        if (copy_from_user(&context, usc, sizeof(context)))
+                goto badframe;
+
+        /* restore passed registers */
+        regs->d0 = context.sc_d0;
+        regs->d1 = context.sc_d1;
+        regs->a0 = context.sc_a0;
+        regs->a1 = context.sc_a1;
+        regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
+        regs->pc = context.sc_pc;
+        regs->orig_d0 = -1;             /* disable syscall checks */
+        wrusp(context.sc_usp);
+        formatvec = context.sc_formatvec;
+
+        err = restore_fpu_state(&context);
+
+        if (err || mangle_kernel_stack(regs, formatvec, fp))
+                goto badframe;
+
+        return 0;
 
 badframe:
         return 1;
@@ -407,9 +375,9 @@ badframe:
 
 static inline int
 rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
-                    struct ucontext __user *uc, int *pd0)
+                    struct ucontext __user *uc)
 {
-        int fsize, temp;
+        int temp;
         greg_t __user *gregs = uc->uc_mcontext.gregs;
         unsigned long usp;
         int err;
@@ -443,65 +411,16 @@ rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
         regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
         regs->orig_d0 = -1;             /* disable syscall checks */
         err |= __get_user(temp, &uc->uc_formatvec);
-        regs->format = temp >> 12;
-        regs->vector = temp & 0xfff;
 
         err |= rt_restore_fpu_state(uc);
 
-        if (do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
+        if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
                 goto badframe;
 
-        fsize = frame_extra_sizes[regs->format];
-        if (fsize < 0) {
-                /*
-                 * user process trying to return with weird frame format
-                 */
-#ifdef DEBUG
-                printk("user process returning with weird frame format\n");
-#endif
+        if (mangle_kernel_stack(regs, temp, &uc->uc_extra))
                 goto badframe;
-        }
-
-        /* OK.  Make room on the supervisor stack for the extra junk,
-         * if necessary.
-         */
 
-        if (fsize) {
-#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
-                __asm__ __volatile__
-                        ("   movel %0,%/a0\n\t"
-                         "   subl %1,%/a0\n\t"     /* make room on stack */
-                         "   movel %/a0,%/sp\n\t"  /* set stack pointer */
-                         /* move switch_stack and pt_regs */
-                         "1: movel %0@+,%/a0@+\n\t"
-                         "   dbra %2,1b\n\t"
-                         "   lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */
-                         "   lsrl  #2,%1\n\t"
-                         "   subql #1,%1\n\t"
-                         "2: movesl %4@+,%2\n\t"
-                         "3: movel %2,%/a0@+\n\t"
-                         "   dbra %1,2b\n\t"
-                         "   bral ret_from_signal\n"
-                         "4:\n"
-                         ".section __ex_table,\"a\"\n"
-                         "   .align 4\n"
-                         "   .long 2b,4b\n"
-                         "   .long 3b,4b\n"
-                         ".previous"
-                         : /* no outputs, it doesn't ever return */
-                         : "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
-                           "n" (frame_offset), "a" (&uc->uc_extra)
-                         : "a0");
-#undef frame_offset
-                /*
-                 * If we ever get here an exception occurred while
-                 * building the above stack-frame.
-                 */
-                goto badframe;
-        }
-
-        *pd0 = regs->d0;
-        return err;
+        return 0;
 
 badframe:
         return 1;
@@ -514,7 +433,6 @@ asmlinkage int do_sigreturn(unsigned long __unused)
         unsigned long usp = rdusp();
         struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
         sigset_t set;
-        int d0;
 
         if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
                 goto badframe;
@@ -528,9 +446,9 @@ asmlinkage int do_sigreturn(unsigned long __unused)
         current->blocked = set;
         recalc_sigpending();
 
-        if (restore_sigcontext(regs, &frame->sc, frame + 1, &d0))
+        if (restore_sigcontext(regs, &frame->sc, frame + 1))
                 goto badframe;
-        return d0;
+        return regs->d0;
 
 badframe:
         force_sig(SIGSEGV, current);
@@ -544,7 +462,6 @@ asmlinkage int do_rt_sigreturn(unsigned long __unused)
         unsigned long usp = rdusp();
         struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4);
         sigset_t set;
-        int d0;
 
         if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
                 goto badframe;
@@ -555,9 +472,9 @@ asmlinkage int do_rt_sigreturn(unsigned long __unused)
         current->blocked = set;
         recalc_sigpending();
 
-        if (rt_restore_ucontext(regs, sw, &frame->uc, &d0))
+        if (rt_restore_ucontext(regs, sw, &frame->uc))
                 goto badframe;
-        return d0;
+        return regs->d0;
 
 badframe:
         force_sig(SIGSEGV, current);
@@ -775,7 +692,7 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
         return (void __user *)((usp - frame_size) & -8UL);
 }
 
-static void setup_frame (int sig, struct k_sigaction *ka,
+static int setup_frame (int sig, struct k_sigaction *ka,
                          sigset_t *set, struct pt_regs *regs)
 {
         struct sigframe __user *frame;
@@ -793,10 +710,8 @@ static void setup_frame (int sig, struct k_sigaction *ka,
 
         frame = get_sigframe(ka, regs, sizeof(*frame) + fsize);
 
-        if (fsize) {
+        if (fsize)
                 err |= copy_to_user (frame + 1, regs + 1, fsize);
-                regs->stkadj = fsize;
-        }
 
         err |= __put_user((current_thread_info()->exec_domain
                            && current_thread_info()->exec_domain->signal_invmap
@@ -826,11 +741,21 @@ static void setup_frame (int sig, struct k_sigaction *ka,
 
         push_cache ((unsigned long) &frame->retcode);
 
-        /* Set up registers for signal handler */
+        /*
+         * Set up registers for signal handler.  All the state we are about
+         * to destroy is successfully copied to sigframe.
+         */
         wrusp ((unsigned long) frame);
         regs->pc = (unsigned long) ka->sa.sa_handler;
 
-adjust_stack:
+        /*
+         * This is subtle; if we build more than one sigframe, all but the
+         * first one will see frame format 0 and have fsize == 0, so we won't
+         * screw stkadj.
+         */
+        if (fsize)
+                regs->stkadj = fsize;
+
         /* Prepare to skip over the extra stuff in the exception frame.  */
         if (regs->stkadj) {
                 struct pt_regs *tregs =
@@ -845,14 +770,14 @@ adjust_stack:
                 tregs->pc = regs->pc;
                 tregs->sr = regs->sr;
         }
-        return;
+        return 0;
 
 give_sigsegv:
         force_sigsegv(sig, current);
-        goto adjust_stack;
+        return err;
 }
 
-static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
+static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
                             sigset_t *set, struct pt_regs *regs)
 {
         struct rt_sigframe __user *frame;
@@ -869,10 +794,8 @@ static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
 
         frame = get_sigframe(ka, regs, sizeof(*frame));
 
-        if (fsize) {
+        if (fsize)
                 err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize);
-                regs->stkadj = fsize;
-        }
 
         err |= __put_user((current_thread_info()->exec_domain
                            && current_thread_info()->exec_domain->signal_invmap
@@ -914,11 +837,21 @@ static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
 
         push_cache ((unsigned long) &frame->retcode);
 
-        /* Set up registers for signal handler */
+        /*
+         * Set up registers for signal handler.  All the state we are about
+         * to destroy is successfully copied to sigframe.
+         */
         wrusp ((unsigned long) frame);
         regs->pc = (unsigned long) ka->sa.sa_handler;
 
-adjust_stack:
+        /*
+         * This is subtle; if we build more than one sigframe, all but the
+         * first one will see frame format 0 and have fsize == 0, so we won't
+         * screw stkadj.
+         */
+        if (fsize)
+                regs->stkadj = fsize;
+
         /* Prepare to skip over the extra stuff in the exception frame.  */
         if (regs->stkadj) {
                 struct pt_regs *tregs =
@@ -933,11 +866,11 @@ adjust_stack:
                 tregs->pc = regs->pc;
                 tregs->sr = regs->sr;
         }
-        return;
+        return 0;
 
 give_sigsegv:
         force_sigsegv(sig, current);
-        goto adjust_stack;
+        return err;
 }
 
 static inline void
@@ -995,6 +928,7 @@ static void
 handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
               sigset_t *oldset, struct pt_regs *regs)
 {
+        int err;
         /* are we from a system call? */
         if (regs->orig_d0 >= 0)
                 /* If so, check system call restarting.. */
@@ -1002,17 +936,24 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
 
         /* set up the stack frame */
         if (ka->sa.sa_flags & SA_SIGINFO)
-                setup_rt_frame(sig, ka, info, oldset, regs);
+                err = setup_rt_frame(sig, ka, info, oldset, regs);
         else
-                setup_frame(sig, ka, oldset, regs);
+                err = setup_frame(sig, ka, oldset, regs);
 
-        if (ka->sa.sa_flags & SA_ONESHOT)
-                ka->sa.sa_handler = SIG_DFL;
+        if (err)
+                return;
 
         sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
         if (!(ka->sa.sa_flags & SA_NODEFER))
                 sigaddset(&current->blocked,sig);
         recalc_sigpending();
+
+        if (test_thread_flag(TIF_DELAYED_TRACE)) {
+                regs->sr &= ~0x8000;
+                send_sig(SIGTRAP, current, 1);
+        }
+
+        clear_thread_flag(TIF_RESTORE_SIGMASK);
 }
 
 /*
@@ -1020,22 +961,25 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
  * want to handle. Thus you cannot kill init even with a SIGKILL even by
  * mistake.
  */
-asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs)
+asmlinkage void do_signal(struct pt_regs *regs)
 {
         siginfo_t info;
         struct k_sigaction ka;
         int signr;
+        sigset_t *oldset;
 
         current->thread.esp0 = (unsigned long) regs;
 
-        if (!oldset)
+        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                oldset = &current->saved_sigmask;
+        else
                 oldset = &current->blocked;
 
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
         if (signr > 0) {
                 /* Whee!  Actually deliver the signal.  */
                 handle_signal(signr, &ka, &info, oldset, regs);
-                return 1;
+                return;
         }
 
         /* Did we come from a system call? */
@@ -1043,5 +987,9 @@ asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs)
                 /* Restart the system call - no handlers present */
                 handle_restart(regs, NULL, 0);
 
-        return 0;
+        /* If there's no signal to deliver, we just restore the saved mask.  */
+        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+        }
 }
diff --git a/arch/m68knommu/kernel/entry.S b/arch/m68knommu/kernel/entry.S
index aff6f57ef8b5..2783f25e38bd 100644
--- a/arch/m68knommu/kernel/entry.S
+++ b/arch/m68knommu/kernel/entry.S
@@ -112,22 +112,6 @@ ENTRY(sys_clone)
         RESTORE_SWITCH_STACK
         rts
 
-ENTRY(sys_sigsuspend)
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        jbsr    do_sigsuspend
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(sys_rt_sigsuspend)
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        jbsr    do_rt_sigsuspend
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        rts
-
 ENTRY(sys_sigreturn)
         SAVE_SWITCH_STACK
         jbsr    do_sigreturn
diff --git a/arch/m68knommu/kernel/signal.c b/arch/m68knommu/kernel/signal.c
index 5ab6a04af14e..36a81bb6835a 100644
--- a/arch/m68knommu/kernel/signal.c
+++ b/arch/m68knommu/kernel/signal.c
@@ -53,65 +53,30 @@
 
 void ret_from_user_signal(void);
 void ret_from_user_rt_signal(void);
-asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs);
 
 /*
  * Atomically swap in the new signal mask, and wait for a signal.
  */
-asmlinkage int do_sigsuspend(struct pt_regs *regs)
+asmlinkage int
+sys_sigsuspend(int unused0, int unused1, old_sigset_t mask)
 {
-        old_sigset_t mask = regs->d3;
-        sigset_t saveset;
-
         mask &= _BLOCKABLE;
         spin_lock_irq(&current->sighand->siglock);
-        saveset = current->blocked;
+        current->saved_sigmask = current->blocked;
         siginitset(&current->blocked, mask);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
 
-        regs->d0 = -EINTR;
-        while (1) {
-                current->state = TASK_INTERRUPTIBLE;
-                schedule();
-                if (do_signal(&saveset, regs))
-                        return -EINTR;
-        }
-}
-
-asmlinkage int
-do_rt_sigsuspend(struct pt_regs *regs)
-{
-        sigset_t *unewset = (sigset_t *)regs->d1;
-        size_t sigsetsize = (size_t)regs->d2;
-        sigset_t saveset, newset;
-
-        /* XXX: Don't preclude handling different sized sigset_t's.  */
-        if (sigsetsize != sizeof(sigset_t))
-                return -EINVAL;
+        current->state = TASK_INTERRUPTIBLE;
+        schedule();
+        set_restore_sigmask();
 
-        if (copy_from_user(&newset, unewset, sizeof(newset)))
-                return -EFAULT;
-        sigdelsetmask(&newset, ~_BLOCKABLE);
-
-        spin_lock_irq(&current->sighand->siglock);
-        saveset = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-
-        regs->d0 = -EINTR;
-        while (1) {
-                current->state = TASK_INTERRUPTIBLE;
-                schedule();
-                if (do_signal(&saveset, regs))
-                        return -EINTR;
-        }
+        return -ERESTARTNOHAND;
 }
 
-asmlinkage int 
-sys_sigaction(int sig, const struct old_sigaction *act,
-              struct old_sigaction *oact)
+asmlinkage int
+sys_sigaction(int sig, const struct old_sigaction __user *act,
+              struct old_sigaction __user *oact)
 {
         struct k_sigaction new_ka, old_ka;
         int ret;
@@ -120,10 +85,10 @@ sys_sigaction(int sig, const struct old_sigaction *act,
                 old_sigset_t mask;
                 if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
                     __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
-                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
+                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
+                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
+                    __get_user(mask, &act->sa_mask))
                         return -EFAULT;
-                __get_user(new_ka.sa.sa_flags, &act->sa_flags);
-                __get_user(mask, &act->sa_mask);
                 siginitset(&new_ka.sa.sa_mask, mask);
         }
 
@@ -132,17 +97,17 @@ sys_sigaction(int sig, const struct old_sigaction *act,
         if (!ret && oact) {
                 if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
                     __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
-                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
+                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
+                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
+                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
                         return -EFAULT;
-                __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
-                __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
         }
 
         return ret;
 }
 
 asmlinkage int
-sys_sigaltstack(const stack_t *uss, stack_t *uoss)
+sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
 {
         return do_sigaltstack(uss, uoss, rdusp());
 }
@@ -157,10 +122,10 @@ sys_sigaltstack(const stack_t *uss, stack_t *uoss)
 
 struct sigframe
 {
-        char *pretcode;
+        char __user *pretcode;
         int sig;
         int code;
-        struct sigcontext *psc;
+        struct sigcontext __user *psc;
         char retcode[8];
         unsigned long extramask[_NSIG_WORDS-1];
         struct sigcontext sc;
@@ -168,10 +133,10 @@ struct sigframe
 
 struct rt_sigframe
 {
-        char *pretcode;
+        char __user *pretcode;
         int sig;
-        struct siginfo *pinfo;
-        void *puc;
+        struct siginfo __user *pinfo;
+        void __user *puc;
         char retcode[8];
         struct siginfo info;
         struct ucontext uc;
@@ -198,8 +163,8 @@ static inline int restore_fpu_state(struct sigcontext *sc)
                 goto out;
 
             __asm__ volatile (".chip 68k/68881\n\t"
-                              "fmovemx %0,%/fp0-%/fp1\n\t"
-                              "fmoveml %1,%/fpcr/%/fpsr/%/fpiar\n\t"
+                              "fmovemx %0,%%fp0-%%fp1\n\t"
+                              "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
                               ".chip 68k"
                               : /* no outputs */
                               : "m" (*sc->sc_fpregs), "m" (*sc->sc_fpcntl));
@@ -218,7 +183,7 @@ out:
 #define uc_formatvec    uc_filler[FPCONTEXT_SIZE/4]
 #define uc_extra        uc_filler[FPCONTEXT_SIZE/4+1]
 
-static inline int rt_restore_fpu_state(struct ucontext *uc)
+static inline int rt_restore_fpu_state(struct ucontext __user *uc)
 {
         unsigned char fpstate[FPCONTEXT_SIZE];
         int context_size = 0;
@@ -228,7 +193,7 @@ static inline int rt_restore_fpu_state(struct ucontext *uc)
         if (FPU_IS_EMU) {
                 /* restore fpu control register */
                 if (__copy_from_user(current->thread.fpcntl,
-                                &uc->uc_mcontext.fpregs.f_pcr, 12))
+                                uc->uc_mcontext.fpregs.f_fpcntl, 12))
                         goto out;
                 /* restore all other fpu register */
                 if (__copy_from_user(current->thread.fp,
@@ -237,7 +202,7 @@ static inline int rt_restore_fpu_state(struct ucontext *uc)
                 return 0;
         }
 
-        if (__get_user(*(long *)fpstate, (long *)&uc->uc_fpstate))
+        if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
                 goto out;
         if (fpstate[0]) {
                 context_size = fpstate[1];
@@ -249,15 +214,15 @@ static inline int rt_restore_fpu_state(struct ucontext *uc)
                      sizeof(fpregs)))
                         goto out;
                 __asm__ volatile (".chip 68k/68881\n\t"
-                                  "fmovemx %0,%/fp0-%/fp7\n\t"
-                                  "fmoveml %1,%/fpcr/%/fpsr/%/fpiar\n\t"
+                                  "fmovemx %0,%%fp0-%%fp7\n\t"
+                                  "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
                                   ".chip 68k"
                                   : /* no outputs */
                                   : "m" (*fpregs.f_fpregs),
-                                    "m" (fpregs.f_pcr));
+                                    "m" (*fpregs.f_fpcntl));
         }
         if (context_size &&
-            __copy_from_user(fpstate + 4, (long *)&uc->uc_fpstate + 1,
+            __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
                              context_size))
                 goto out;
         __asm__ volatile (".chip 68k/68881\n\t"
@@ -272,7 +237,7 @@ out:
 #endif
 
 static inline int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext *usc, void *fp,
+restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp,
                    int *pd0)
 {
         int formatvec;
@@ -312,10 +277,10 @@ badframe:
 
 static inline int
 rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
-                    struct ucontext *uc, int *pd0)
+                    struct ucontext __user *uc, int *pd0)
 {
         int temp;
-        greg_t *gregs = uc->uc_mcontext.gregs;
+        greg_t __user *gregs = uc->uc_mcontext.gregs;
         unsigned long usp;
         int err;
 
@@ -365,7 +330,7 @@ asmlinkage int do_sigreturn(unsigned long __unused)
         struct switch_stack *sw = (struct switch_stack *) &__unused;
         struct pt_regs *regs = (struct pt_regs *) (sw + 1);
         unsigned long usp = rdusp();
-        struct sigframe *frame = (struct sigframe *)(usp - 4);
+        struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
         sigset_t set;
         int d0;
 
@@ -397,7 +362,7 @@ asmlinkage int do_rt_sigreturn(unsigned long __unused)
         struct switch_stack *sw = (struct switch_stack *) &__unused;
         struct pt_regs *regs = (struct pt_regs *) (sw + 1);
         unsigned long usp = rdusp();
-        struct rt_sigframe *frame = (struct rt_sigframe *)(usp - 4);
+        struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4);
         sigset_t set;
         int d0;
 
@@ -443,17 +408,17 @@ static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
         if (sc->sc_fpstate[0]) {
                 fpu_version = sc->sc_fpstate[0];
                 __asm__ volatile (".chip 68k/68881\n\t"
-                                  "fmovemx %/fp0-%/fp1,%0\n\t"
-                                  "fmoveml %/fpcr/%/fpsr/%/fpiar,%1\n\t"
+                                  "fmovemx %%fp0-%%fp1,%0\n\t"
+                                  "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
                                   ".chip 68k"
-                                  : /* no outputs */
-                                  : "m" (*sc->sc_fpregs),
-                                    "m" (*sc->sc_fpcntl)
+                                  : "=m" (*sc->sc_fpregs),
+                                    "=m" (*sc->sc_fpcntl)
+                                  : /* no inputs */
                                   : "memory");
         }
 }
 
-static inline int rt_save_fpu_state(struct ucontext *uc, struct pt_regs *regs)
+static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
 {
         unsigned char fpstate[FPCONTEXT_SIZE];
         int context_size = 0;
@@ -461,7 +426,7 @@ static inline int rt_save_fpu_state(struct ucontext *uc, struct pt_regs *regs)
 
         if (FPU_IS_EMU) {
                 /* save fpu control register */
-                err |= copy_to_user(&uc->uc_mcontext.fpregs.f_pcr,
+                err |= copy_to_user(uc->uc_mcontext.fpregs.f_pcntl,
                                 current->thread.fpcntl, 12);
                 /* save all other fpu register */
                 err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
@@ -474,24 +439,24 @@ static inline int rt_save_fpu_state(struct ucontext *uc, struct pt_regs *regs)
                           ".chip 68k"
                           : : "m" (*fpstate) : "memory");
 
-        err |= __put_user(*(long *)fpstate, (long *)&uc->uc_fpstate);
+        err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate);
         if (fpstate[0]) {
                 fpregset_t fpregs;
                 context_size = fpstate[1];
                 fpu_version = fpstate[0];
                 __asm__ volatile (".chip 68k/68881\n\t"
-                                  "fmovemx %/fp0-%/fp7,%0\n\t"
-                                  "fmoveml %/fpcr/%/fpsr/%/fpiar,%1\n\t"
+                                  "fmovemx %%fp0-%%fp7,%0\n\t"
+                                  "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
                                   ".chip 68k"
-                                  : /* no outputs */
-                                  : "m" (*fpregs.f_fpregs),
-                                    "m" (fpregs.f_pcr)
+                                  : "=m" (*fpregs.f_fpregs),
+                                    "=m" (*fpregs.f_fpcntl)
+                                  : /* no inputs */
                                   : "memory");
                 err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs,
                                     sizeof(fpregs));
         }
         if (context_size)
-                err |= copy_to_user((long *)&uc->uc_fpstate + 1, fpstate + 4,
+                err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4,
                                     context_size);
         return err;
 }
@@ -516,10 +481,10 @@ static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
 #endif
 }
 
-static inline int rt_setup_ucontext(struct ucontext *uc, struct pt_regs *regs)
+static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs)
 {
         struct switch_stack *sw = (struct switch_stack *)regs - 1;
-        greg_t *gregs = uc->uc_mcontext.gregs;
+        greg_t __user *gregs = uc->uc_mcontext.gregs;
         int err = 0;
 
         err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
@@ -547,7 +512,7 @@ static inline int rt_setup_ucontext(struct ucontext *uc, struct pt_regs *regs)
         return err;
 }
 
-static inline void *
+static inline void __user *
 get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
 {
         unsigned long usp;
@@ -560,13 +525,13 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
                 if (!sas_ss_flags(usp))
                         usp = current->sas_ss_sp + current->sas_ss_size;
         }
-        return (void *)((usp - frame_size) & -8UL);
+        return (void __user *)((usp - frame_size) & -8UL);
 }
 
-static void setup_frame (int sig, struct k_sigaction *ka,
+static int setup_frame (int sig, struct k_sigaction *ka,
                          sigset_t *set, struct pt_regs *regs)
 {
-        struct sigframe *frame;
+        struct sigframe __user *frame;
         struct sigcontext context;
         int err = 0;
 
@@ -617,17 +582,17 @@ adjust_stack:
                 tregs->pc = regs->pc;
                 tregs->sr = regs->sr;
         }
-        return;
+        return err;
 
 give_sigsegv:
         force_sigsegv(sig, current);
         goto adjust_stack;
 }
 
-static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
+static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
                             sigset_t *set, struct pt_regs *regs)
 {
-        struct rt_sigframe *frame;
+        struct rt_sigframe __user *frame;
         int err = 0;
 
         frame = get_sigframe(ka, regs, sizeof(*frame));
@@ -644,8 +609,8 @@ static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
 
         /* Create the ucontext.  */
         err |= __put_user(0, &frame->uc.uc_flags);
-        err |= __put_user(0, &frame->uc.uc_link);
-        err |= __put_user((void *)current->sas_ss_sp,
+        err |= __put_user(NULL, &frame->uc.uc_link);
+        err |= __put_user((void __user *)current->sas_ss_sp,
                           &frame->uc.uc_stack.ss_sp);
         err |= __put_user(sas_ss_flags(rdusp()),
                           &frame->uc.uc_stack.ss_flags);
@@ -681,7 +646,7 @@ adjust_stack:
                 tregs->pc = regs->pc;
                 tregs->sr = regs->sr;
         }
-        return;
+        return err;
 
 give_sigsegv:
         force_sigsegv(sig, current);
@@ -728,6 +693,7 @@ static void
 handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
               sigset_t *oldset, struct pt_regs *regs)
 {
+        int err;
         /* are we from a system call? */
         if (regs->orig_d0 >= 0)
                 /* If so, check system call restarting.. */
@@ -735,12 +701,12 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
 
         /* set up the stack frame */
         if (ka->sa.sa_flags & SA_SIGINFO)
-                setup_rt_frame(sig, ka, info, oldset, regs);
+                err = setup_rt_frame(sig, ka, info, oldset, regs);
         else
-                setup_frame(sig, ka, oldset, regs);
+                err = setup_frame(sig, ka, oldset, regs);
 
-        if (ka->sa.sa_flags & SA_ONESHOT)
-                ka->sa.sa_handler = SIG_DFL;
+        if (err)
+                return;
 
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
@@ -748,6 +714,8 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
                 sigaddset(&current->blocked,sig);
         recalc_sigpending();
         spin_unlock_irq(&current->sighand->siglock);
+
+        clear_thread_flag(TIF_RESTORE_SIGMASK);
 }
 
 /*
@@ -755,11 +723,12 @@ handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
  * want to handle. Thus you cannot kill init even with a SIGKILL even by
  * mistake.
  */
-asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs)
+asmlinkage void do_signal(struct pt_regs *regs)
 {
         struct k_sigaction ka;
         siginfo_t info;
         int signr;
+        sigset_t *oldset;
 
         /*
          * We want the common case to go fast, which
@@ -768,16 +737,18 @@ asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs)
          * if so.
          */
         if (!user_mode(regs))
-                return 1;
+                return;
 
-        if (!oldset)
+        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                oldset = &current->saved_sigmask;
+        else
                 oldset = &current->blocked;
 
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
         if (signr > 0) {
                 /* Whee!  Actually deliver the signal.  */
                 handle_signal(signr, &ka, &info, oldset, regs);
-                return 1;
+                return;
         }
 
         /* Did we come from a system call? */
@@ -785,5 +756,10 @@ asmlinkage int do_signal(sigset_t *oldset, struct pt_regs *regs)
                 /* Restart the system call - no handlers present */
                 handle_restart(regs, NULL, 0);
         }
-        return 0;
+
+        /* If there's no signal to deliver, we just restore the saved mask.  */
+        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+        }
 }
diff --git a/arch/m68knommu/platform/68328/entry.S b/arch/m68knommu/platform/68328/entry.S
index 27241e16a526..240a7a6e25c8 100644
--- a/arch/m68knommu/platform/68328/entry.S
+++ b/arch/m68knommu/platform/68328/entry.S
@@ -106,6 +106,7 @@ Luser_return:
         movel   %sp,%d1                 /* get thread_info pointer */
         andl    #-THREAD_SIZE,%d1
         movel   %d1,%a2
+1:
         move    %a2@(TI_FLAGS),%d1      /* thread_info->flags */
         andl    #_TIF_WORK_MASK,%d1
         jne     Lwork_to_do
@@ -120,13 +121,11 @@ Lsignal_return:
         subql   #4,%sp                  /* dummy return address*/
         SAVE_SWITCH_STACK
         pea     %sp@(SWITCH_STACK_SIZE)
-        clrl    %sp@-
         bsrw    do_signal
-        addql   #8,%sp
+        addql   #4,%sp
         RESTORE_SWITCH_STACK
         addql   #4,%sp
-Lreturn:
-        RESTORE_ALL
+        jra     1b
 
 /*
  * This is the main interrupt handler, responsible for calling process_int()
diff --git a/arch/m68knommu/platform/68360/entry.S b/arch/m68knommu/platform/68360/entry.S
index c131c6e1d92d..8a28788c0eea 100644
--- a/arch/m68knommu/platform/68360/entry.S
+++ b/arch/m68knommu/platform/68360/entry.S
@@ -102,6 +102,7 @@ Luser_return:
         movel   %sp,%d1                 /* get thread_info pointer */
         andl    #-THREAD_SIZE,%d1
         movel   %d1,%a2
+1:
         move    %a2@(TI_FLAGS),%d1      /* thread_info->flags */
         andl    #_TIF_WORK_MASK,%d1
         jne     Lwork_to_do
@@ -116,13 +117,11 @@ Lsignal_return:
         subql   #4,%sp                  /* dummy return address*/
         SAVE_SWITCH_STACK
         pea     %sp@(SWITCH_STACK_SIZE)
-        clrl    %sp@-
         bsrw    do_signal
-        addql   #8,%sp
+        addql   #4,%sp
         RESTORE_SWITCH_STACK
         addql   #4,%sp
-Lreturn:
-        RESTORE_ALL
+        jra     1b
 
 /*
  * This is the main interrupt handler, responsible for calling do_IRQ()
diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68knommu/platform/coldfire/entry.S
index 5e92bed94b7e..e1debc8285ef 100644
--- a/arch/m68knommu/platform/coldfire/entry.S
+++ b/arch/m68knommu/platform/coldfire/entry.S
@@ -167,12 +167,11 @@ Lsignal_return:
         subql   #4,%sp                  /* dummy return address */
         SAVE_SWITCH_STACK
         pea     %sp@(SWITCH_STACK_SIZE)
-        clrl    %sp@-
         jsr     do_signal
-        addql   #8,%sp
+        addql   #4,%sp
         RESTORE_SWITCH_STACK
         addql   #4,%sp
-        jmp     Lreturn
+        jmp     Luser_return
 
 /*
  * This is the generic interrupt handler (for all hardware interrupt
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 387d5ffdfd3a..5f5018a71a3d 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -14,7 +14,7 @@ config MICROBLAZE
         select HAVE_DMA_API_DEBUG
         select TRACING_SUPPORT
         select OF
-        select OF_FLATTREE
+        select OF_EARLY_FLATTREE
 
 config SWAP
         def_bool n
diff --git a/arch/microblaze/Kconfig.debug b/arch/microblaze/Kconfig.debug
index e66e25c4b0b2..012e377330cd 100644
--- a/arch/microblaze/Kconfig.debug
+++ b/arch/microblaze/Kconfig.debug
@@ -23,8 +23,4 @@ config HEART_BEAT
           This option turns on/off heart beat kernel functionality.
           First GPIO node is taken.
 
-config DEBUG_BOOTMEM
-        depends on DEBUG_KERNEL
-        bool "Debug BOOTMEM initialization"
-
 endmenu
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
index 15f1f1d1840d..6f432e6df9af 100644
--- a/arch/microblaze/Makefile
+++ b/arch/microblaze/Makefile
@@ -17,7 +17,7 @@ export CPU_VER CPU_MAJOR CPU_MINOR CPU_REV
 # The various CONFIG_XILINX cpu features options are integers 0/1/2...
 # rather than bools y/n
 
-# Work out HW multipler support.  This is icky.
+# Work out HW multipler support. This is tricky.
 # 1. Spartan2 has no HW multiplers.
 # 2. MicroBlaze v3.x always uses them, except in Spartan 2
 # 3. All other FPGa/CPU ver combos, we can trust the CONFIG_ settings
diff --git a/arch/microblaze/boot/Makefile b/arch/microblaze/boot/Makefile
index be01d78750d9..4c4e58ef0cb6 100644
--- a/arch/microblaze/boot/Makefile
+++ b/arch/microblaze/boot/Makefile
@@ -10,9 +10,6 @@ targets := linux.bin linux.bin.gz simpleImage.%
 
 OBJCOPYFLAGS := -O binary
 
-# Where the DTS files live
-dtstree         := $(srctree)/$(src)/dts
-
 # Ensure system.dtb exists
 $(obj)/linked_dtb.o: $(obj)/system.dtb
 
@@ -51,14 +48,11 @@ $(obj)/simpleImage.%: vmlinux FORCE
         $(call if_changed,strip)
         @echo 'Kernel: $@ is ready' ' (#'`cat .version`')'
 
-# Rule to build device tree blobs
-DTC = $(objtree)/scripts/dtc/dtc
 
 # Rule to build device tree blobs
-quiet_cmd_dtc = DTC     $@
-        cmd_dtc = $(DTC) -O dtb -o $(obj)/$*.dtb -b 0 -p 1024 $(dtstree)/$*.dts
+DTC_FLAGS := -p 1024
 
-$(obj)/%.dtb: $(dtstree)/%.dts FORCE
-        $(call if_changed,dtc)
+$(obj)/%.dtb: $(src)/dts/%.dts FORCE
+        $(call cmd,dtc)
 
 clean-files += *.dtb simpleImage.*.unstrip linux.bin.ub
diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig
index 8b422b12ef78..ab8fbe7ad90b 100644
--- a/arch/microblaze/configs/mmu_defconfig
+++ b/arch/microblaze/configs/mmu_defconfig
@@ -66,5 +66,4 @@ CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_INFO=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_EARLY_PRINTK=y
-CONFIG_DEBUG_BOOTMEM=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h
index bdc38312ae4a..2e72af078b05 100644
--- a/arch/microblaze/include/asm/prom.h
+++ b/arch/microblaze/include/asm/prom.h
@@ -64,9 +64,6 @@ extern void kdump_move_device_tree(void);
 /* CPU OF node matching */
 struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
 
-/* Get the MAC address */
-extern const void *of_get_mac_address(struct device_node *np);
-
 /**
  * of_irq_map_pci - Resolve the interrupt for a PCI device
  * @pdev:       the device whose interrupt is to be resolved
diff --git a/arch/microblaze/include/asm/pvr.h b/arch/microblaze/include/asm/pvr.h
index 37db96a15b45..a10bec62e857 100644
--- a/arch/microblaze/include/asm/pvr.h
+++ b/arch/microblaze/include/asm/pvr.h
@@ -1,9 +1,9 @@
 /*
  * Support for the MicroBlaze PVR (Processor Version Register)
  *
- * Copyright (C) 2009 Michal Simek <monstr@monstr.eu>
+ * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu>
  * Copyright (C) 2007 John Williams <john.williams@petalogix.com>
- * Copyright (C) 2007 - 2009 PetaLogix
+ * Copyright (C) 2007 - 2011 PetaLogix
  *
  * This file is subject to the terms and conditions of the GNU General
  * Public License. See the file COPYING in the main directory of this
@@ -46,11 +46,11 @@ struct pvr_s {
 #define PVR2_I_LMB_MASK                 0x10000000
 #define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
 #define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
-#define PVR2_D_PLB_MASK                 0x02000000      /* new */
-#define PVR2_I_PLB_MASK                 0x01000000      /* new */
-#define PVR2_INTERCONNECT               0x00800000      /* new */
-#define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
-#define PVR2_USE_FSL_EXC                0x00040000      /* new */
+#define PVR2_D_PLB_MASK                 0x02000000 /* new */
+#define PVR2_I_PLB_MASK                 0x01000000 /* new */
+#define PVR2_INTERCONNECT               0x00800000 /* new */
+#define PVR2_USE_EXTEND_FSL             0x00080000 /* new */
+#define PVR2_USE_FSL_EXC                0x00040000 /* new */
 #define PVR2_USE_MSR_INSTR              0x00020000
 #define PVR2_USE_PCMP_INSTR             0x00010000
 #define PVR2_AREA_OPTIMISED             0x00008000
@@ -59,7 +59,7 @@ struct pvr_s {
 #define PVR2_USE_HW_MUL_MASK            0x00001000
 #define PVR2_USE_FPU_MASK               0x00000800
 #define PVR2_USE_MUL64_MASK             0x00000400
-#define PVR2_USE_FPU2_MASK              0x00000200      /* new */
+#define PVR2_USE_FPU2_MASK              0x00000200 /* new */
 #define PVR2_USE_IPLBEXC                0x00000100
 #define PVR2_USE_DPLBEXC                0x00000080
 #define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
@@ -122,96 +122,103 @@ struct pvr_s {
 
 
 /* PVR access macros */
-#define PVR_IS_FULL(pvr)                (pvr.pvr[0] & PVR0_PVR_FULL_MASK)
-#define PVR_USE_BARREL(pvr)             (pvr.pvr[0] & PVR0_USE_BARREL_MASK)
-#define PVR_USE_DIV(pvr)                (pvr.pvr[0] & PVR0_USE_DIV_MASK)
-#define PVR_USE_HW_MUL(pvr)             (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
-#define PVR_USE_FPU(pvr)                (pvr.pvr[0] & PVR0_USE_FPU_MASK)
-#define PVR_USE_FPU2(pvr)               (pvr.pvr[2] & PVR2_USE_FPU2_MASK)
-#define PVR_USE_ICACHE(pvr)             (pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
-#define PVR_USE_DCACHE(pvr)             (pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
-#define PVR_VERSION(pvr)        ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
-#define PVR_USER1(pvr)                  (pvr.pvr[0] & PVR0_USER1_MASK)
-#define PVR_USER2(pvr)                  (pvr.pvr[1] & PVR1_USER2_MASK)
-
-#define PVR_D_OPB(pvr)                  (pvr.pvr[2] & PVR2_D_OPB_MASK)
-#define PVR_D_LMB(pvr)                  (pvr.pvr[2] & PVR2_D_LMB_MASK)
-#define PVR_I_OPB(pvr)                  (pvr.pvr[2] & PVR2_I_OPB_MASK)
-#define PVR_I_LMB(pvr)                  (pvr.pvr[2] & PVR2_I_LMB_MASK)
-#define PVR_INTERRUPT_IS_EDGE(pvr) \
-                        (pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
-#define PVR_EDGE_IS_POSITIVE(pvr) \
-                        (pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
-#define PVR_USE_MSR_INSTR(pvr)          (pvr.pvr[2] & PVR2_USE_MSR_INSTR)
-#define PVR_USE_PCMP_INSTR(pvr)         (pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
-#define PVR_AREA_OPTIMISED(pvr)         (pvr.pvr[2] & PVR2_AREA_OPTIMISED)
-#define PVR_USE_MUL64(pvr)              (pvr.pvr[2] & PVR2_USE_MUL64_MASK)
-#define PVR_OPCODE_0x0_ILLEGAL(pvr) \
-                        (pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
-#define PVR_UNALIGNED_EXCEPTION(pvr) \
-                        (pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
-#define PVR_ILL_OPCODE_EXCEPTION(pvr) \
-                        (pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
-#define PVR_IOPB_BUS_EXCEPTION(pvr) \
-                        (pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
-#define PVR_DOPB_BUS_EXCEPTION(pvr) \
-                        (pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
-#define PVR_DIV_ZERO_EXCEPTION(pvr) \
-                        (pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
-#define PVR_FPU_EXCEPTION(pvr)          (pvr.pvr[2] & PVR2_FPU_EXC_MASK)
-#define PVR_FSL_EXCEPTION(pvr)          (pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
-
-#define PVR_DEBUG_ENABLED(pvr)          (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
-#define PVR_NUMBER_OF_PC_BRK(pvr) \
-                        ((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
-#define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \
-                        ((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
-#define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \
-                        ((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
-#define PVR_FSL_LINKS(pvr)      ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
-
-#define PVR_ICACHE_ADDR_TAG_BITS(pvr) \
-                        ((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
-#define PVR_ICACHE_USE_FSL(pvr)         (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
-#define PVR_ICACHE_ALLOW_WR(pvr)        (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
-#define PVR_ICACHE_LINE_LEN(pvr) \
-                        (1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
-#define PVR_ICACHE_BYTE_SIZE(pvr) \
-                        (1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
-
-#define PVR_DCACHE_ADDR_TAG_BITS(pvr) \
-                        ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
-#define PVR_DCACHE_USE_FSL(pvr)         (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
-#define PVR_DCACHE_ALLOW_WR(pvr)        (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
+#define PVR_IS_FULL(_pvr)       (_pvr.pvr[0] & PVR0_PVR_FULL_MASK)
+#define PVR_USE_BARREL(_pvr)    (_pvr.pvr[0] & PVR0_USE_BARREL_MASK)
+#define PVR_USE_DIV(_pvr)       (_pvr.pvr[0] & PVR0_USE_DIV_MASK)
+#define PVR_USE_HW_MUL(_pvr)    (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
+#define PVR_USE_FPU(_pvr)       (_pvr.pvr[0] & PVR0_USE_FPU_MASK)
+#define PVR_USE_FPU2(_pvr)      (_pvr.pvr[2] & PVR2_USE_FPU2_MASK)
+#define PVR_USE_ICACHE(_pvr)    (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
+#define PVR_USE_DCACHE(_pvr)    (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
+#define PVR_VERSION(_pvr)       ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
+#define PVR_USER1(_pvr)         (_pvr.pvr[0] & PVR0_USER1_MASK)
+#define PVR_USER2(_pvr)         (_pvr.pvr[1] & PVR1_USER2_MASK)
+
+#define PVR_D_OPB(_pvr)         (_pvr.pvr[2] & PVR2_D_OPB_MASK)
+#define PVR_D_LMB(_pvr)         (_pvr.pvr[2] & PVR2_D_LMB_MASK)
+#define PVR_I_OPB(_pvr)         (_pvr.pvr[2] & PVR2_I_OPB_MASK)
+#define PVR_I_LMB(_pvr)         (_pvr.pvr[2] & PVR2_I_LMB_MASK)
+#define PVR_INTERRUPT_IS_EDGE(_pvr) \
+                        (_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
+#define PVR_EDGE_IS_POSITIVE(_pvr) \
+                        (_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
+#define PVR_USE_MSR_INSTR(_pvr)         (_pvr.pvr[2] & PVR2_USE_MSR_INSTR)
+#define PVR_USE_PCMP_INSTR(_pvr)        (_pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
+#define PVR_AREA_OPTIMISED(_pvr)        (_pvr.pvr[2] & PVR2_AREA_OPTIMISED)
+#define PVR_USE_MUL64(_pvr)             (_pvr.pvr[2] & PVR2_USE_MUL64_MASK)
+#define PVR_OPCODE_0x0_ILLEGAL(_pvr) \
+                        (_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
+#define PVR_UNALIGNED_EXCEPTION(_pvr) \
+                        (_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
+#define PVR_ILL_OPCODE_EXCEPTION(_pvr) \
+                        (_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
+#define PVR_IOPB_BUS_EXCEPTION(_pvr) \
+                        (_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
+#define PVR_DOPB_BUS_EXCEPTION(_pvr) \
+                        (_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
+#define PVR_DIV_ZERO_EXCEPTION(_pvr) \
+                        (_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
+#define PVR_FPU_EXCEPTION(_pvr)         (_pvr.pvr[2] & PVR2_FPU_EXC_MASK)
+#define PVR_FSL_EXCEPTION(_pvr)         (_pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
+
+#define PVR_DEBUG_ENABLED(_pvr)         (_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
+#define PVR_NUMBER_OF_PC_BRK(_pvr) \
+                        ((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
+#define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \
+                        ((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
+#define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \
+                        ((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
+#define PVR_FSL_LINKS(_pvr)     ((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
+
+#define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \
+                ((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
+#define PVR_ICACHE_USE_FSL(_pvr) \
+                (_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
+#define PVR_ICACHE_ALLOW_WR(_pvr) \
+                (_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
+#define PVR_ICACHE_LINE_LEN(_pvr) \
+                (1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
+#define PVR_ICACHE_BYTE_SIZE(_pvr) \
+                (1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
+
+#define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \
+                        ((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
+#define PVR_DCACHE_USE_FSL(_pvr)        (_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
+#define PVR_DCACHE_ALLOW_WR(_pvr) \
+                        (_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
 /* FIXME two shifts on one line needs any comment */
-#define PVR_DCACHE_LINE_LEN(pvr) \
-                        (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
-#define PVR_DCACHE_BYTE_SIZE(pvr) \
-                        (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
+#define PVR_DCACHE_LINE_LEN(_pvr) \
+                (1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
+#define PVR_DCACHE_BYTE_SIZE(_pvr) \
+                (1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
 
-#define PVR_DCACHE_USE_WRITEBACK(pvr) \
-                        ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
+#define PVR_DCACHE_USE_WRITEBACK(_pvr) \
+                        ((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
 
-#define PVR_ICACHE_BASEADDR(pvr)        (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
-#define PVR_ICACHE_HIGHADDR(pvr)        (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
+#define PVR_ICACHE_BASEADDR(_pvr) \
+                        (_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
+#define PVR_ICACHE_HIGHADDR(_pvr) \
+                        (_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
+#define PVR_DCACHE_BASEADDR(_pvr) \
+                        (_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
+#define PVR_DCACHE_HIGHADDR(_pvr) \
+                        (_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
 
-#define PVR_DCACHE_BASEADDR(pvr)        (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
-#define PVR_DCACHE_HIGHADDR(pvr)        (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
+#define PVR_TARGET_FAMILY(_pvr) \
+                        ((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
 
-#define PVR_TARGET_FAMILY(pvr)  ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
-
-#define PVR_MSR_RESET_VALUE(pvr) \
-                                (pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
+#define PVR_MSR_RESET_VALUE(_pvr) \
+                        (_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
 
 /* mmu */
-#define PVR_USE_MMU(pvr)        ((pvr.pvr[11] & PVR11_USE_MMU) >> 30)
-#define PVR_MMU_ITLB_SIZE(pvr)  (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
-#define PVR_MMU_DTLB_SIZE(pvr)  (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
-#define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
-#define PVR_MMU_ZONES(pvr)      (pvr.pvr[11] & PVR11_MMU_ZONES)
+#define PVR_USE_MMU(_pvr)               ((_pvr.pvr[11] & PVR11_USE_MMU) >> 30)
+#define PVR_MMU_ITLB_SIZE(_pvr)         (_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
+#define PVR_MMU_DTLB_SIZE(_pvr)         (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
+#define PVR_MMU_TLB_ACCESS(_pvr)        (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
+#define PVR_MMU_ZONES(_pvr)             (_pvr.pvr[11] & PVR11_MMU_ZONES)
 
 /* endian */
-#define PVR_ENDIAN(pvr) (pvr.pvr[0] & PVR0_ENDI)
+#define PVR_ENDIAN(_pvr)        (_pvr.pvr[0] & PVR0_ENDI)
 
 int cpu_has_pvr(void);
 void get_pvr(struct pvr_s *pvr);
diff --git a/arch/microblaze/kernel/cpu/cpuinfo.c b/arch/microblaze/kernel/cpu/cpuinfo.c
index 87c79fa275c3..2c309fccf230 100644
--- a/arch/microblaze/kernel/cpu/cpuinfo.c
+++ b/arch/microblaze/kernel/cpu/cpuinfo.c
@@ -32,6 +32,7 @@ const struct cpu_ver_key cpu_ver_lookup[] = {
         {"7.30.a", 0x10},
         {"7.30.b", 0x11},
         {"8.00.a", 0x12},
+        {"8.00.b", 0x13},
         {NULL, 0},
 };
 
diff --git a/arch/microblaze/kernel/entry.S b/arch/microblaze/kernel/entry.S
index 819238b8a429..41c30cdb2704 100644
--- a/arch/microblaze/kernel/entry.S
+++ b/arch/microblaze/kernel/entry.S
@@ -287,25 +287,44 @@
  * are masked. This is nice, means we don't have to CLI before state save
  */
 C_ENTRY(_user_exception):
-        addi    r14, r14, 4     /* return address is 4 byte after call */
         swi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)) /* save stack */
+        addi    r14, r14, 4     /* return address is 4 byte after call */
+
+        mfs     r1, rmsr
+        nop
+        andi    r1, r1, MSR_UMS
+        bnei    r1, 1f
+
+/* Kernel-mode state save - kernel execve */
+        lwi     r1, r0, TOPHYS(PER_CPU(ENTRY_SP)); /* Reload kernel stack-ptr*/
+        tophys(r1,r1);
+
+        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack. */
+        SAVE_REGS
 
+        swi     r1, r1, PTO + PT_MODE; /* pt_regs -> kernel mode */
+        brid    2f;
+        nop;                            /* Fill delay slot */
+
+/* User-mode state save.  */
+1:
         lwi     r1, r0, TOPHYS(PER_CPU(CURRENT_SAVE)); /* get saved current */
         tophys(r1,r1);
         lwi     r1, r1, TS_THREAD_INFO; /* get stack from task_struct */
-        /* MS these three instructions can be added to one */
-        /* addik        r1, r1, THREAD_SIZE; */
-        /* tophys(r1,r1); */
-        /* addik        r1, r1, -STATE_SAVE_SIZE; */
-        addik r1, r1, THREAD_SIZE + CONFIG_KERNEL_BASE_ADDR - CONFIG_KERNEL_START - STATE_SAVE_SIZE;
+/* calculate kernel stack pointer from task struct 8k */
+        addik   r1, r1, THREAD_SIZE;
+        tophys(r1,r1);
+
+        addik   r1, r1, -STATE_SAVE_SIZE; /* Make room on the stack.  */
         SAVE_REGS
         swi     r0, r1, PTO + PT_R3
         swi     r0, r1, PTO + PT_R4
 
+        swi     r0, r1, PTO + PT_MODE;                  /* Was in user-mode. */
         lwi     r11, r0, TOPHYS(PER_CPU(ENTRY_SP));
         swi     r11, r1, PTO+PT_R1;             /* Store user SP.  */
         clear_ums;
-        lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
+2:      lwi     CURRENT_TASK, r0, TOPHYS(PER_CPU(CURRENT_SAVE));
         /* Save away the syscall number.  */
         swi     r12, r1, PTO+PT_R0;
         tovirt(r1,r1)
@@ -375,6 +394,9 @@ C_ENTRY(ret_from_trap):
         swi     r3, r1, PTO + PT_R3
         swi     r4, r1, PTO + PT_R4
 
+        lwi     r11, r1, PTO + PT_MODE;
+/* See if returning to kernel mode, if so, skip resched &c.  */
+        bnei    r11, 2f;
         /* We're returning to user mode, so check for various conditions that
          * trigger rescheduling. */
         /* FIXME: Restructure all these flag checks. */
@@ -417,6 +439,16 @@ C_ENTRY(ret_from_trap):
         RESTORE_REGS;
         addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
         lwi     r1, r1, PT_R1 - PT_SIZE;/* Restore user stack pointer. */
+        bri     6f;
+
+/* Return to kernel state.  */
+2:      set_bip;                        /*  Ints masked for state restore */
+        VM_OFF;
+        tophys(r1,r1);
+        RESTORE_REGS;
+        addik   r1, r1, STATE_SAVE_SIZE         /* Clean up stack space.  */
+        tovirt(r1,r1);
+6:
 TRAP_return:            /* Make global symbol for debugging */
         rtbd    r14, 0; /* Instructions to return from an IRQ */
         nop;
diff --git a/arch/microblaze/kernel/exceptions.c b/arch/microblaze/kernel/exceptions.c
index 478f2943ede7..a7fa6ae76d89 100644
--- a/arch/microblaze/kernel/exceptions.c
+++ b/arch/microblaze/kernel/exceptions.c
@@ -25,6 +25,7 @@
 #include <linux/errno.h>
 #include <linux/ptrace.h>
 #include <asm/current.h>
+#include <asm/cacheflush.h>
 
 #define MICROBLAZE_ILL_OPCODE_EXCEPTION 0x02
 #define MICROBLAZE_IBUS_EXCEPTION       0x03
@@ -52,6 +53,8 @@ void die(const char *str, struct pt_regs *fp, long err)
 void sw_exception(struct pt_regs *regs)
 {
         _exception(SIGTRAP, regs, TRAP_BRKPT, regs->r16);
+        flush_dcache_range(regs->r16, regs->r16 + 0x4);
+        flush_icache_range(regs->r16, regs->r16 + 0x4);
 }
 
 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index 781195438ee6..25f6e07d8de8 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -945,11 +945,20 @@ store3:	sbi	r3, r4, 2;
 store4: sbi     r3, r4, 3;      /* Delay slot */
 ex_shw_vm:
         /* Store the lower half-word, byte-by-byte into destination address */
+#ifdef __MICROBLAZEEL__
+        lbui    r3, r5, 0;
+store5: sbi     r3, r4, 0;
+        lbui    r3, r5, 1;
+        brid    ret_from_exc;
+store6: sbi     r3, r4, 1;      /* Delay slot */
+#else
         lbui    r3, r5, 2;
 store5: sbi     r3, r4, 0;
         lbui    r3, r5, 3;
         brid    ret_from_exc;
 store6: sbi     r3, r4, 1;      /* Delay slot */
+#endif
+
 ex_sw_end_vm:                   /* Exception handling of store word, ends. */
 
 /* We have to prevent cases that get/put_user macros get unaligned pointer
diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c
index a105301e2b7f..c881393f07fd 100644
--- a/arch/microblaze/kernel/prom.c
+++ b/arch/microblaze/kernel/prom.c
@@ -61,14 +61,12 @@ static int __init early_init_dt_scan_serial(unsigned long node,
         char *p;
         int *addr;
 
-        pr_debug("search \"chosen\", depth: %d, uname: %s\n", depth, uname);
+        pr_debug("search \"serial\", depth: %d, uname: %s\n", depth, uname);
 
 /* find all serial nodes */
         if (strncmp(uname, "serial", 6) != 0)
                 return 0;
 
-        early_init_dt_check_for_initrd(node);
-
 /* find compatible node with uartlite */
         p = of_get_flat_dt_prop(node, "compatible", &l);
         if ((strncmp(p, "xlnx,xps-uartlite", 17) != 0) &&
diff --git a/arch/microblaze/kernel/prom_parse.c b/arch/microblaze/kernel/prom_parse.c
index 99d9b61cccb5..9ae24f4b882b 100644
--- a/arch/microblaze/kernel/prom_parse.c
+++ b/arch/microblaze/kernel/prom_parse.c
@@ -110,41 +110,3 @@ void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
         cells = prop ? *(u32 *)prop : of_n_size_cells(dn);
         *size = of_read_number(dma_window, cells);
 }
-
-/**
- * Search the device tree for the best MAC address to use.  'mac-address' is
- * checked first, because that is supposed to contain to "most recent" MAC
- * address. If that isn't set, then 'local-mac-address' is checked next,
- * because that is the default address.  If that isn't set, then the obsolete
- * 'address' is checked, just in case we're using an old device tree.
- *
- * Note that the 'address' property is supposed to contain a virtual address of
- * the register set, but some DTS files have redefined that property to be the
- * MAC address.
- *
- * All-zero MAC addresses are rejected, because those could be properties that
- * exist in the device tree, but were not set by U-Boot.  For example, the
- * DTS could define 'mac-address' and 'local-mac-address', with zero MAC
- * addresses.  Some older U-Boots only initialized 'local-mac-address'.  In
- * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists
- * but is all zeros.
-*/
-const void *of_get_mac_address(struct device_node *np)
-{
-        struct property *pp;
-
-        pp = of_find_property(np, "mac-address", NULL);
-        if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
-                return pp->value;
-
-        pp = of_find_property(np, "local-mac-address", NULL);
-        if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
-                return pp->value;
-
-        pp = of_find_property(np, "address", NULL);
-        if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
-                return pp->value;
-
-        return NULL;
-}
-EXPORT_SYMBOL(of_get_mac_address);
diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S
index 96a88c31fe48..3451bdec9f05 100644
--- a/arch/microblaze/kernel/vmlinux.lds.S
+++ b/arch/microblaze/kernel/vmlinux.lds.S
@@ -123,20 +123,10 @@ SECTIONS {
 
         __init_end_before_initramfs = .;
 
-        .init.ramfs ALIGN(PAGE_SIZE) : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
-                __initramfs_start = .;
-                *(.init.ramfs)
-                __initramfs_end = .;
-                . = ALIGN(4);
-                LONG(0);
-/*
- * FIXME this can break initramfs for MMU.
- * Pad init.ramfs up to page boundary,
- * so that __init_end == __bss_start. This will make image.elf
- * consistent with the image.bin
- */
-                /* . = ALIGN(PAGE_SIZE); */
+        .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
+                INIT_RAM_FS
         }
+
         __init_end = .;
 
         .bss ALIGN (PAGE_SIZE) : AT(ADDR(.bss) - LOAD_OFFSET) {
diff --git a/arch/microblaze/lib/memmove.c b/arch/microblaze/lib/memmove.c
index 123e3616f2dd..810fd68775e3 100644
--- a/arch/microblaze/lib/memmove.c
+++ b/arch/microblaze/lib/memmove.c
@@ -182,7 +182,7 @@ void *memmove(void *v_dst, const void *v_src, __kernel_size_t c)
                         for (; c >= 4; c -= 4) {
                                 value = *--i_src;
                                 *--i_dst = buf_hold | ((value & 0xFF000000)>> 24);
-                                buf_hold = (value & 0xFFFFFF) << 8;;
+                                buf_hold = (value & 0xFFFFFF) << 8;
                         }
 #endif
                         /* Realign the source */
diff --git a/arch/microblaze/lib/muldi3.S b/arch/microblaze/lib/muldi3.S
deleted file mode 100644
index ceeaa8c407f2..000000000000
--- a/arch/microblaze/lib/muldi3.S
+++ /dev/null
@@ -1,121 +0,0 @@
-#include <linux/linkage.h>
-
-/*
- * Multiply operation for 64 bit integers, for devices with hard multiply
- *      Input : Operand1[H] in Reg r5
- *              Operand1[L] in Reg r6
- *              Operand2[H] in Reg r7
- *              Operand2[L] in Reg r8
- *      Output: Result[H] in Reg r3
- *              Result[L] in Reg r4
- *
- * Explaination:
- *
- *      Both the input numbers are divided into 16 bit number as follows
- *              op1 = A B C D
- *              op2 = E F G H
- *      result = D * H
- *               + (C * H + D * G) << 16
- *               + (B * H + C * G + D * F) << 32
- *               + (A * H + B * G + C * F + D * E) << 48
- *
- *      Only 64 bits of the output are considered
- */
-
-        .text
-        .globl  __muldi3
-        .type __muldi3, @function
-        .ent __muldi3
-
-__muldi3:
-        addi    r1, r1, -40
-
-/* Save the input operands on the caller's stack */
-        swi     r5, r1, 44
-        swi     r6, r1, 48
-        swi     r7, r1, 52
-        swi     r8, r1, 56
-
-/* Store all the callee saved registers */
-        sw      r20, r1, r0
-        swi     r21, r1, 4
-        swi     r22, r1, 8
-        swi     r23, r1, 12
-        swi     r24, r1, 16
-        swi     r25, r1, 20
-        swi     r26, r1, 24
-        swi     r27, r1, 28
-
-/* Load all the 16 bit values for A thru H */
-        lhui    r20, r1, 44 /* A */
-        lhui    r21, r1, 46 /* B */
-        lhui    r22, r1, 48 /* C */
-        lhui    r23, r1, 50 /* D */
-        lhui    r24, r1, 52 /* E */
-        lhui    r25, r1, 54 /* F */
-        lhui    r26, r1, 56 /* G */
-        lhui    r27, r1, 58 /* H */
-
-/* D * H ==> LSB of the result on stack ==> Store1 */
-        mul     r9, r23, r27
-        swi     r9, r1, 36 /* Pos2 and Pos3 */
-
-/* Hi (Store1) + C * H + D * G ==> Store2 ==> Pos1 and Pos2 */
-/* Store the carry generated in position 2 for Pos 3 */
-        lhui    r11, r1, 36 /* Pos2 */
-        mul     r9, r22, r27 /* C * H */
-        mul     r10, r23, r26 /* D * G */
-        add     r9, r9, r10
-        addc    r12, r0, r0
-        add     r9, r9, r11
-        addc    r12, r12, r0 /* Store the Carry */
-        shi     r9, r1, 36 /* Store Pos2 */
-        swi     r9, r1, 32
-        lhui    r11, r1, 32
-        shi     r11, r1, 34 /* Store Pos1 */
-
-/* Hi (Store2) + B * H + C * G + D * F ==> Store3 ==> Pos0 and Pos1 */
-        mul     r9, r21, r27 /* B * H */
-        mul     r10, r22, r26 /* C * G */
-        mul     r7, r23, r25 /* D * F */
-        add     r9, r9, r11
-        add     r9, r9, r10
-        add     r9, r9, r7
-        swi     r9, r1, 32 /* Pos0 and Pos1 */
-
-/* Hi (Store3) + A * H + B * G + C * F + D * E ==> Store3 ==> Pos0 */
-        lhui    r11, r1, 32 /* Pos0 */
-        mul     r9, r20, r27 /* A * H */
-        mul     r10, r21, r26 /* B * G */
-        mul     r7, r22, r25 /* C * F */
-        mul     r8, r23, r24 /* D * E */
-        add     r9, r9, r11
-        add     r9, r9, r10
-        add     r9, r9, r7
-        add     r9, r9, r8
-        sext16  r9, r9 /* Sign extend the MSB */
-        shi     r9, r1, 32
-
-/* Move results to r3 and r4 */
-        lhui    r3, r1, 32
-        add     r3, r3, r12
-        shi     r3, r1, 32
-        lwi     r3, r1, 32 /* Hi Part */
-        lwi     r4, r1, 36 /* Lo Part */
-
-/* Restore Callee saved registers */
-        lw      r20, r1, r0
-        lwi     r21, r1, 4
-        lwi     r22, r1, 8
-        lwi     r23, r1, 12
-        lwi     r24, r1, 16
-        lwi     r25, r1, 20
-        lwi     r26, r1, 24
-        lwi     r27, r1, 28
-
-/* Restore Frame and return */
-        rtsd    r15, 8
-        addi    r1, r1, 40
-
-.size __muldi3, . - __muldi3
-.end __muldi3
diff --git a/arch/microblaze/lib/muldi3.c b/arch/microblaze/lib/muldi3.c
new file mode 100644
index 000000000000..d4860e154d29
--- /dev/null
+++ b/arch/microblaze/lib/muldi3.c
@@ -0,0 +1,60 @@
+#include <linux/module.h>
+
+#include "libgcc.h"
+
+#define DWtype long long
+#define UWtype unsigned long
+#define UHWtype unsigned short
+
+#define W_TYPE_SIZE 32
+
+#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
+#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
+
+/* If we still don't have umul_ppmm, define it using plain C.  */
+#if !defined(umul_ppmm)
+#define umul_ppmm(w1, w0, u, v)                                         \
+        do {                                                            \
+                UWtype __x0, __x1, __x2, __x3;                          \
+                UHWtype __ul, __vl, __uh, __vh;                         \
+                                                                        \
+                __ul = __ll_lowpart(u);                                 \
+                __uh = __ll_highpart(u);                                \
+                __vl = __ll_lowpart(v);                                 \
+                __vh = __ll_highpart(v);                                \
+                                                                        \
+                __x0 = (UWtype) __ul * __vl;                            \
+                __x1 = (UWtype) __ul * __vh;                            \
+                __x2 = (UWtype) __uh * __vl;                            \
+                __x3 = (UWtype) __uh * __vh;                            \
+                                                                        \
+                __x1 += __ll_highpart(__x0); /* this can't give carry */\
+                __x1 += __x2; /* but this indeed can */                 \
+                if (__x1 < __x2) /* did we get it? */                   \
+                __x3 += __ll_B; /* yes, add it in the proper pos */     \
+                                                                        \
+                (w1) = __x3 + __ll_highpart(__x1);                      \
+                (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0);\
+        } while (0)
+#endif
+
+#if !defined(__umulsidi3)
+#define __umulsidi3(u, v) ({                            \
+        DWunion __w;                                    \
+        umul_ppmm(__w.s.high, __w.s.low, u, v);         \
+        __w.ll;                                         \
+        })
+#endif
+
+DWtype __muldi3(DWtype u, DWtype v)
+{
+        const DWunion uu = {.ll = u};
+        const DWunion vv = {.ll = v};
+        DWunion w = {.ll = __umulsidi3(uu.s.low, vv.s.low)};
+
+        w.s.high += ((UWtype) uu.s.low * (UWtype) vv.s.high
+                + (UWtype) uu.s.high * (UWtype) vv.s.low);
+
+        return w.ll;
+}
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0a9b5b8b2a19..f489ec30e071 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2218,7 +2218,7 @@ config SECCOMP
 config USE_OF
         bool "Flattened Device Tree support"
         select OF
-        select OF_FLATTREE
+        select OF_EARLY_FLATTREE
         help
           Include support for flattened device tree machine descriptions.
 
diff --git a/arch/mips/include/asm/ioctls.h b/arch/mips/include/asm/ioctls.h
index d87cb0465693..d967b8997626 100644
--- a/arch/mips/include/asm/ioctls.h
+++ b/arch/mips/include/asm/ioctls.h
@@ -83,6 +83,7 @@
 #define TCSETSF2        _IOW('T', 0x2D, struct termios2)
 #define TIOCGPTN        _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T', 0x31, int)  /* Lock/unlock Pty */
+#define TIOCGDEV        _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */
 #define TIOCSIG         _IOW('T', 0x36, int)  /* Generate signal on Pty slave */
 
 /* I hope the range from 0x5480 on is free ... */
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 5c7c6fc07565..183e0d226669 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1047,6 +1047,6 @@ init_hw_perf_events(void)
 
         return 0;
 }
-arch_initcall(init_hw_perf_events);
+early_initcall(init_hw_perf_events);
 
 #endif /* defined(CONFIG_CPU_MIPS32)... */
diff --git a/arch/parisc/include/asm/ioctls.h b/arch/parisc/include/asm/ioctls.h
index 4e0614456bea..6ba80d03623a 100644
--- a/arch/parisc/include/asm/ioctls.h
+++ b/arch/parisc/include/asm/ioctls.h
@@ -52,6 +52,7 @@
 #define TCSETSF2        _IOW('T',0x2D, struct termios2)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+#define TIOCGDEV        _IOR('T',0x32, int)  /* Get primary device node of /dev/console */
 #define TIOCSIG         _IOW('T',0x36, int)  /* Generate signal on Pty slave */
 
 #define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
diff --git a/arch/parisc/kernel/pdc_cons.c b/arch/parisc/kernel/pdc_cons.c
index 66d1f17fdb94..11bdd68e5762 100644
--- a/arch/parisc/kernel/pdc_cons.c
+++ b/arch/parisc/kernel/pdc_cons.c
@@ -92,8 +92,6 @@ static int pdc_console_setup(struct console *co, char *options)
 
 static struct timer_list pdc_console_timer;
 
-extern struct console * console_drivers;
-
 static int pdc_console_tty_open(struct tty_struct *tty, struct file *filp)
 {
 
@@ -169,11 +167,13 @@ static int __init pdc_console_tty_driver_init(void)
          * It is unregistered if the pdc console was not selected as the
          * primary console. */
 
-        struct console *tmp = console_drivers;
+        struct console *tmp;
 
-        for (tmp = console_drivers; tmp; tmp = tmp->next)
+        acquire_console_sem();
+        for_each_console(tmp)
                 if (tmp == &pdc_cons)
                         break;
+        release_console_sem();
 
         if (!tmp) {
                 printk(KERN_INFO "PDC console driver not registered anymore, not creating %s\n", pdc_cons.name);
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index e625e9e034ae..959f38ccb9a7 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -20,6 +20,9 @@ config WORD_SIZE
 config ARCH_PHYS_ADDR_T_64BIT
        def_bool PPC64 || PHYS_64BIT
 
+config ARCH_DMA_ADDR_T_64BIT
+        def_bool ARCH_PHYS_ADDR_T_64BIT
+
 config MMU
         bool
         default y
@@ -116,7 +119,7 @@ config PPC
         bool
         default y
         select OF
-        select OF_FLATTREE
+        select OF_EARLY_FLATTREE
         select HAVE_FTRACE_MCOUNT_RECORD
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FUNCTION_TRACER
@@ -209,7 +212,7 @@ config ARCH_HIBERNATION_POSSIBLE
 config ARCH_SUSPEND_POSSIBLE
         def_bool y
         depends on ADB_PMU || PPC_EFIKA || PPC_LITE5200 || PPC_83xx || \
-                   PPC_85xx || PPC_86xx || PPC_PSERIES
+                   PPC_85xx || PPC_86xx || PPC_PSERIES || 44x || 40x
 
 config PPC_DCR_NATIVE
         bool
@@ -595,13 +598,11 @@ config EXTRA_TARGETS
 
           If unsure, leave blank
 
-if !44x || BROKEN
 config ARCH_WANTS_FREEZER_CONTROL
         def_bool y
         depends on ADB_PMU
 
 source kernel/power/Kconfig
-endif
 
 config SECCOMP
         bool "Enable seccomp to safely compute untrusted bytecode"
@@ -682,6 +683,15 @@ config FSL_PMC
           Freescale MPC85xx/MPC86xx power management controller support
           (suspend/resume). For MPC83xx see platforms/83xx/suspend.c
 
+config PPC4xx_CPM
+        bool
+        default y
+        depends on SUSPEND && (44x || 40x)
+        help
+          PPC4xx Clock Power Management (CPM) support (suspend/resume).
+          It also enables support for two different idle states (idle-wait
+          and idle-doze).
+
 config 4xx_SOC
         bool
 
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index fae8192c8fcc..96deec63bcf3 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -35,7 +35,7 @@ endif
 
 BOOTCFLAGS      += -I$(obj) -I$(srctree)/$(obj)
 
-DTS_FLAGS       ?= -p 1024
+DTC_FLAGS       ?= -p 1024
 
 $(obj)/4xx.o: BOOTCFLAGS += -mcpu=405
 $(obj)/ebony.o: BOOTCFLAGS += -mcpu=405
@@ -332,10 +332,8 @@ $(obj)/treeImage.%: vmlinux $(obj)/%.dtb $(wrapperbits)
         $(call if_changed,wrap,treeboot-$*,,$(obj)/$*.dtb)
 
 # Rule to build device tree blobs
-DTC = $(objtree)/scripts/dtc/dtc
-
-$(obj)/%.dtb: $(dtstree)/%.dts
-        $(DTC) -O dtb -o $(obj)/$*.dtb -b 0 $(DTS_FLAGS) $(dtstree)/$*.dts
+$(obj)/%.dtb: $(src)/dts/%.dts
+        $(call cmd,dtc)
 
 # If there isn't a platform selected then just strip the vmlinux.
 ifeq (,$(image-y))
diff --git a/arch/powerpc/boot/dts/bluestone.dts b/arch/powerpc/boot/dts/bluestone.dts
index 9bb3d72c0e5a..2a56a0dbd1f7 100644
--- a/arch/powerpc/boot/dts/bluestone.dts
+++ b/arch/powerpc/boot/dts/bluestone.dts
@@ -33,7 +33,7 @@
         aliases {
                 ethernet0 = &EMAC0;
                 serial0 = &UART0;
-                serial1 = &UART1;
+                //serial1 = &UART1; --gcl missing UART1 label
         };
 
         cpus {
@@ -52,7 +52,7 @@
                         d-cache-size = <32768>;
                         dcr-controller;
                         dcr-access-method = "native";
-                        next-level-cache = <&L2C0>;
+                        //next-level-cache = <&L2C0>; --gcl missing L2C0 label
                 };
         };
 
@@ -142,7 +142,7 @@
                                         /*RXEOB*/ 0x7 0x4
                                         /*SERR*/  0x3 0x4
                                         /*TXDE*/  0x4 0x4
-                                        /*RXDE*/  0x5 0x4
+                                        /*RXDE*/  0x5 0x4>;
                 };
 
                 POB0: opb {
@@ -182,7 +182,7 @@
                                                 reg = <0x001a0000 0x00060000>;
                                         };
                                 };
-                        }
+                        };
 
                         UART0: serial@ef600300 {
                                 device_type = "serial";
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index a30370396250..5b27a4b74b79 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -105,6 +105,15 @@
                 dcr-reg = <0x00c 0x002>;
         };
 
+        CPM0: cpm {
+                compatible = "ibm,cpm";
+                dcr-access-method = "native";
+                dcr-reg = <0x160 0x003>;
+                unused-units = <0x00000100>;
+                idle-doze = <0x02000000>;
+                standby = <0xfeff791d>;
+        };
+
         L2C0: l2c {
                 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
                 dcr-reg = <0x020 0x008          /* Internal SRAM DCR's */
@@ -270,28 +279,6 @@
                                 interrupts = <0x1 0x4>;
                         };
 
-                        UART2: serial@ef600500 {
-                                device_type = "serial";
-                                compatible = "ns16550";
-                                reg = <0xef600500 0x00000008>;
-                                virtual-reg = <0xef600500>;
-                                clock-frequency = <0>; /* Filled in by U-Boot */
-                                current-speed = <0>; /* Filled in by U-Boot */
-                                interrupt-parent = <&UIC1>;
-                                interrupts = <28 0x4>;
-                        };
-
-                        UART3: serial@ef600600 {
-                                device_type = "serial";
-                                compatible = "ns16550";
-                                reg = <0xef600600 0x00000008>;
-                                virtual-reg = <0xef600600>;
-                                clock-frequency = <0>; /* Filled in by U-Boot */
-                                current-speed = <0>; /* Filled in by U-Boot */
-                                interrupt-parent = <&UIC1>;
-                                interrupts = <29 0x4>;
-                        };
-
                         IIC0: i2c@ef600700 {
                                 compatible = "ibm,iic-460ex", "ibm,iic";
                                 reg = <0xef600700 0x00000014>;
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index dd3860846f15..ad3a4f4a2b04 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -10,220 +10,74 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
 
 / {
         model = "schindler,cm5200";
         compatible = "schindler,cm5200";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&mpc5200_pic>;
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                PowerPC,5200@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <0x4000>;                // L1, 16K
-                        i-cache-size = <0x4000>;                // L1, 16K
-                        timebase-frequency = <0>;       // from bootloader
-                        bus-frequency = <0>;            // from bootloader
-                        clock-frequency = <0>;          // from bootloader
-                };
-        };
-
-        memory {
-                device_type = "memory";
-                reg = <0x00000000 0x04000000>;  // 64MB
-        };
 
         soc5200@f0000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc5200b-immr";
-                ranges = <0 0xf0000000 0x0000c000>;
-                reg = <0xf0000000 0x00000100>;
-                bus-frequency = <0>;            // from bootloader
-                system-frequency = <0>;         // from bootloader
-
-                cdm@200 {
-                        compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
-                        reg = <0x200 0x38>;
-                };
-
-                mpc5200_pic: interrupt-controller@500 {
-                        // 5200 interrupts are encoded into two levels;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
-                        reg = <0x500 0x80>;
-                };
-
                 timer@600 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x600 0x10>;
-                        interrupts = <1 9 0>;
                         fsl,has-wdt;
                 };
 
-                timer@610 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x610 0x10>;
-                        interrupts = <1 10 0>;
-                };
-
-                timer@620 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x620 0x10>;
-                        interrupts = <1 11 0>;
-                };
-
-                timer@630 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x630 0x10>;
-                        interrupts = <1 12 0>;
-                };
-
-                timer@640 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x640 0x10>;
-                        interrupts = <1 13 0>;
-                };
-
-                timer@650 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x650 0x10>;
-                        interrupts = <1 14 0>;
-                };
-
-                timer@660 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x660 0x10>;
-                        interrupts = <1 15 0>;
-                };
-
-                timer@670 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x670 0x10>;
-                        interrupts = <1 16 0>;
+                can@900 {
+                        status = "disabled";
                 };
 
-                rtc@800 {       // Real time clock
-                        compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
-                        reg = <0x800 0x100>;
-                        interrupts = <1 5 0 1 6 0>;
+                can@980 {
+                        status = "disabled";
                 };
 
-                gpio_simple: gpio@b00 {
-                        compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
-                        reg = <0xb00 0x40>;
-                        interrupts = <1 7 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpio_wkup: gpio@c00 {
-                        compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
-                        reg = <0xc00 0x40>;
-                        interrupts = <1 8 0 0 3 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                spi@f00 {
-                        compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
-                        reg = <0xf00 0x20>;
-                        interrupts = <2 13 0 2 14 0>;
-                };
-
-                usb@1000 {
-                        compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
-                        reg = <0x1000 0xff>;
-                        interrupts = <2 6 0>;
-                };
-
-                dma-controller@1200 {
-                        compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
-                        reg = <0x1200 0x80>;
-                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
-                                      3 4 0  3 5 0  3 6 0  3 7 0
-                                      3 8 0  3 9 0  3 10 0  3 11 0
-                                      3 12 0  3 13 0  3 14 0  3 15 0>;
+                psc@2000 {              // PSC1
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
                 };
 
-                xlb@1f00 {
-                        compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
-                        reg = <0x1f00 0x100>;
+                psc@2200 {              // PSC2
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
                 };
 
-                serial@2000 {           // PSC1
+                psc@2400 {              // PSC3
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2000 0x100>;
-                        interrupts = <2 1 0>;
                 };
 
-                serial@2200 {           // PSC2
-                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2200 0x100>;
-                        interrupts = <2 2 0>;
+                psc@2600 {              // PSC4
+                        status = "disabled";
                 };
 
-                serial@2400 {           // PSC3
-                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2400 0x100>;
-                        interrupts = <2 3 0>;
+                psc@2800 {              // PSC5
+                        status = "disabled";
                 };
 
-                serial@2c00 {           // PSC6
+                psc@2c00 {              // PSC6
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2c00 0x100>;
-                        interrupts = <2 4 0>;
                 };
 
                 ethernet@3000 {
-                        compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <0x3000 0x400>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <2 5 0>;
                         phy-handle = <&phy0>;
                 };
 
                 mdio@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
-                        reg = <0x3000 0x400>;       // fec range, since we need to setup fec interrupts
-                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
-
                         phy0: ethernet-phy@0 {
                                 reg = <0>;
                         };
                 };
 
-                i2c@3d40 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d40 0x40>;
-                        interrupts = <2 16 0>;
+                ata@3a00 {
+                        status = "disabled";
                 };
 
-                sram@8000 {
-                        compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
-                        reg = <0x8000 0x4000>;
+                i2c@3d00 {
+                        status = "disabled";
                 };
+
         };
 
-        localbus {
-                compatible = "fsl,mpc5200b-lpb","simple-bus";
-                #address-cells = <2>;
-                #size-cells = <1>;
-                ranges = <0 0 0xfc000000 0x2000000>;
+        pci@f0000d00 {
+                status = "disabled";
+        };
 
+        localbus {
                 // 16-bit flash device at LocalPlus Bus CS0
                 flash@0,0 {
                         compatible = "cfi-flash";
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
index 8e9be6bfe23e..27bd267d631c 100644
--- a/arch/powerpc/boot/dts/digsy_mtc.dts
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -11,195 +11,68 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
 
 / {
         model = "intercontrol,digsy-mtc";
         compatible = "intercontrol,digsy-mtc";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&mpc5200_pic>;
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                PowerPC,5200@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <0x4000>;                // L1, 16K
-                        i-cache-size = <0x4000>;                // L1, 16K
-                        timebase-frequency = <0>;       // from bootloader
-                        bus-frequency = <0>;            // from bootloader
-                        clock-frequency = <0>;          // from bootloader
-                };
-        };
 
         memory {
-                device_type = "memory";
                 reg = <0x00000000 0x02000000>;  // 32MB
         };
 
         soc5200@f0000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc5200b-immr";
-                ranges = <0 0xf0000000 0x0000c000>;
-                reg = <0xf0000000 0x00000100>;
-                bus-frequency = <0>;            // from bootloader
-                system-frequency = <0>;         // from bootloader
-
-                cdm@200 {
-                        compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
-                        reg = <0x200 0x38>;
-                };
-
-                mpc5200_pic: interrupt-controller@500 {
-                        // 5200 interrupts are encoded into two levels;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
-                        reg = <0x500 0x80>;
-                };
-
                 timer@600 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x600 0x10>;
-                        interrupts = <1 9 0>;
                         fsl,has-wdt;
                 };
 
-                timer@610 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x610 0x10>;
-                        interrupts = <1 10 0>;
-                };
-
-                timer@620 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x620 0x10>;
-                        interrupts = <1 11 0>;
-                };
-
-                timer@630 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x630 0x10>;
-                        interrupts = <1 12 0>;
-                };
-
-                timer@640 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x640 0x10>;
-                        interrupts = <1 13 0>;
-                };
-
-                timer@650 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x650 0x10>;
-                        interrupts = <1 14 0>;
+                rtc@800 {
+                        status = "disabled";
                 };
 
-                timer@660 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x660 0x10>;
-                        interrupts = <1 15 0>;
+                can@900 {
+                        status = "disabled";
                 };
 
-                timer@670 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x670 0x10>;
-                        interrupts = <1 16 0>;
+                can@980 {
+                        status = "disabled";
                 };
 
-                gpio_simple: gpio@b00 {
-                        compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
-                        reg = <0xb00 0x40>;
-                        interrupts = <1 7 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                psc@2000 {              // PSC1
+                        status = "disabled";
                 };
 
-                gpio_wkup: gpio@c00 {
-                        compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
-                        reg = <0xc00 0x40>;
-                        interrupts = <1 8 0 0 3 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                psc@2200 {              // PSC2
+                        status = "disabled";
                 };
 
-                spi@f00 {
-                        compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
-                        reg = <0xf00 0x20>;
-                        interrupts = <2 13 0 2 14 0>;
+                psc@2400 {              // PSC3
+                        status = "disabled";
                 };
 
-                usb@1000 {
-                        compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
-                        reg = <0x1000 0xff>;
-                        interrupts = <2 6 0>;
-                };
-
-                dma-controller@1200 {
-                        compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
-                        reg = <0x1200 0x80>;
-                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
-                                      3 4 0  3 5 0  3 6 0  3 7 0
-                                      3 8 0  3 9 0  3 10 0  3 11 0
-                                      3 12 0  3 13 0  3 14 0  3 15 0>;
-                };
-
-                xlb@1f00 {
-                        compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
-                        reg = <0x1f00 0x100>;
+                psc@2600 {              // PSC4
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
                 };
 
-                serial@2600 {           // PSC4
+                psc@2800 {              // PSC5
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2600 0x100>;
-                        interrupts = <2 11 0>;
                 };
 
-                serial@2800 {           // PSC5
-                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2800 0x100>;
-                        interrupts = <2 12 0>;
+                psc@2c00 {              // PSC6
+                        status = "disabled";
                 };
 
                 ethernet@3000 {
-                        compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <0x3000 0x400>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <2 5 0>;
                         phy-handle = <&phy0>;
                 };
 
                 mdio@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
-                        reg = <0x3000 0x400>;       // fec range, since we need to setup fec interrupts
-                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
-
                         phy0: ethernet-phy@0 {
                                 reg = <0>;
                         };
                 };
 
-                ata@3a00 {
-                        compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
-                        reg = <0x3a00 0x100>;
-                        interrupts = <2 7 0>;
-                };
-
                 i2c@3d00 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d00 0x40>;
-                        interrupts = <2 15 0>;
-
                         rtc@50 {
                                 compatible = "at,24c08";
                                 reg = <0x50>;
@@ -211,16 +84,16 @@
                         };
                 };
 
-                sram@8000 {
-                        compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
-                        reg = <0x8000 0x4000>;
+                i2c@3d40 {
+                        status = "disabled";
                 };
         };
 
-        lpb {
-                compatible = "fsl,mpc5200b-lpb","simple-bus";
-                #address-cells = <2>;
-                #size-cells = <1>;
+        pci@f0000d00 {
+                status = "disabled";
+        };
+
+        localbus {
                 ranges = <0 0 0xff000000 0x1000000>;
 
                 // 16-bit flash device at LocalPlus Bus CS0
diff --git a/arch/powerpc/boot/dts/hotfoot.dts b/arch/powerpc/boot/dts/hotfoot.dts
index cad9c3840afc..71d3bb4931dc 100644
--- a/arch/powerpc/boot/dts/hotfoot.dts
+++ b/arch/powerpc/boot/dts/hotfoot.dts
@@ -117,6 +117,8 @@
                         };
 
                         IIC: i2c@ef600500 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 compatible = "ibm,iic-405ep", "ibm,iic";
                                 reg = <0xef600500 0x00000011>;
                                 interrupt-parent = <&UIC0>;
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 083e68eeaca4..89edb16649c3 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -82,6 +82,15 @@
                 interrupt-parent = <&UIC0>;
         };
 
+        CPM0: cpm {
+                compatible = "ibm,cpm";
+                dcr-access-method = "native";
+                dcr-reg = <0x0b0 0x003>;
+                unused-units = <0x00000000>;
+                idle-doze = <0x02000000>;
+                standby = <0xe3e74800>;
+        };
+
         plb {
                 compatible = "ibm,plb-405ex", "ibm,plb4";
                 #address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 59702ace900f..fb288bb882b6 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -10,256 +10,75 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
 
 / {
         model = "fsl,lite5200b";
         compatible = "fsl,lite5200b";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&mpc5200_pic>;
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                PowerPC,5200@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <0x4000>;        // L1, 16K
-                        i-cache-size = <0x4000>;        // L1, 16K
-                        timebase-frequency = <0>;       // from bootloader
-                        bus-frequency = <0>;            // from bootloader
-                        clock-frequency = <0>;          // from bootloader
-                };
-        };
 
         memory {
-                device_type = "memory";
                 reg = <0x00000000 0x10000000>;  // 256MB
         };
 
         soc5200@f0000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc5200b-immr";
-                ranges = <0 0xf0000000 0x0000c000>;
-                reg = <0xf0000000 0x00000100>;
-                bus-frequency = <0>;            // from bootloader
-                system-frequency = <0>;         // from bootloader
-
-                cdm@200 {
-                        compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
-                        reg = <0x200 0x38>;
-                };
-
-                mpc5200_pic: interrupt-controller@500 {
-                        // 5200 interrupts are encoded into two levels;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
-                        reg = <0x500 0x80>;
-                };
-
                 timer@600 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x600 0x10>;
-                        interrupts = <1 9 0>;
                         fsl,has-wdt;
                 };
 
-                timer@610 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x610 0x10>;
-                        interrupts = <1 10 0>;
-                };
-
-                timer@620 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x620 0x10>;
-                        interrupts = <1 11 0>;
-                };
-
-                timer@630 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x630 0x10>;
-                        interrupts = <1 12 0>;
-                };
-
-                timer@640 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x640 0x10>;
-                        interrupts = <1 13 0>;
-                };
-
-                timer@650 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x650 0x10>;
-                        interrupts = <1 14 0>;
-                };
-
-                timer@660 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x660 0x10>;
-                        interrupts = <1 15 0>;
-                };
-
-                timer@670 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x670 0x10>;
-                        interrupts = <1 16 0>;
-                };
-
-                rtc@800 {       // Real time clock
-                        compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
-                        reg = <0x800 0x100>;
-                        interrupts = <1 5 0 1 6 0>;
-                };
-
-                can@900 {
-                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
-                        interrupts = <2 17 0>;
-                        reg = <0x900 0x80>;
-                };
-
-                can@980 {
-                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
-                        interrupts = <2 18 0>;
-                        reg = <0x980 0x80>;
-                };
-
-                gpio_simple: gpio@b00 {
-                        compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
-                        reg = <0xb00 0x40>;
-                        interrupts = <1 7 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpio_wkup: gpio@c00 {
-                        compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
-                        reg = <0xc00 0x40>;
-                        interrupts = <1 8 0 0 3 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                psc@2000 {              // PSC1
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
+                        cell-index = <0>;
                 };
 
-                spi@f00 {
-                        compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
-                        reg = <0xf00 0x20>;
-                        interrupts = <2 13 0 2 14 0>;
+                psc@2200 {              // PSC2
+                        status = "disabled";
                 };
 
-                usb@1000 {
-                        compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
-                        reg = <0x1000 0xff>;
-                        interrupts = <2 6 0>;
+                psc@2400 {              // PSC3
+                        status = "disabled";
                 };
 
-                dma-controller@1200 {
-                        compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
-                        reg = <0x1200 0x80>;
-                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
-                                      3 4 0  3 5 0  3 6 0  3 7 0
-                                      3 8 0  3 9 0  3 10 0  3 11 0
-                                      3 12 0  3 13 0  3 14 0  3 15 0>;
+                psc@2600 {              // PSC4
+                        status = "disabled";
                 };
 
-                xlb@1f00 {
-                        compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
-                        reg = <0x1f00 0x100>;
+                psc@2800 {              // PSC5
+                        status = "disabled";
                 };
 
-                serial@2000 {           // PSC1
-                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        cell-index = <0>;
-                        reg = <0x2000 0x100>;
-                        interrupts = <2 1 0>;
+                psc@2c00 {              // PSC6
+                        status = "disabled";
                 };
 
                 // PSC2 in ac97 mode example
                 //ac97@2200 {           // PSC2
                 //      compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
                 //      cell-index = <1>;
-                //      reg = <0x2200 0x100>;
-                //      interrupts = <2 2 0>;
                 //};
 
                 // PSC3 in CODEC mode example
                 //i2s@2400 {            // PSC3
                 //      compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
                 //      cell-index = <2>;
-                //      reg = <0x2400 0x100>;
-                //      interrupts = <2 3 0>;
-                //};
-
-                // PSC4 in uart mode example
-                //serial@2600 {         // PSC4
-                //      compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                //      cell-index = <3>;
-                //      reg = <0x2600 0x100>;
-                //      interrupts = <2 11 0>;
-                //};
-
-                // PSC5 in uart mode example
-                //serial@2800 {         // PSC5
-                //      compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                //      cell-index = <4>;
-                //      reg = <0x2800 0x100>;
-                //      interrupts = <2 12 0>;
                 //};
 
                 // PSC6 in spi mode example
                 //spi@2c00 {            // PSC6
                 //      compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
                 //      cell-index = <5>;
-                //      reg = <0x2c00 0x100>;
-                //      interrupts = <2 4 0>;
                 //};
 
                 ethernet@3000 {
-                        compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <0x3000 0x400>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <2 5 0>;
                         phy-handle = <&phy0>;
                 };
 
                 mdio@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
-                        reg = <0x3000 0x400>;   // fec range, since we need to setup fec interrupts
-                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
-
                         phy0: ethernet-phy@0 {
                                 reg = <0>;
                         };
                 };
 
-                ata@3a00 {
-                        compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
-                        reg = <0x3a00 0x100>;
-                        interrupts = <2 7 0>;
-                };
-
-                i2c@3d00 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d00 0x40>;
-                        interrupts = <2 15 0>;
-                };
-
                 i2c@3d40 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d40 0x40>;
-                        interrupts = <2 16 0>;
-
                         eeprom@50 {
                                 compatible = "atmel,24c02";
                                 reg = <0x50>;
@@ -273,12 +92,6 @@
         };
 
         pci@f0000d00 {
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                device_type = "pci";
-                compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
-                reg = <0xf0000d00 0x100>;
                 interrupt-map-mask = <0xf800 0 0 7>;
                 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
                                  0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -298,11 +111,6 @@
         };
 
         localbus {
-                compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
-
-                #address-cells = <2>;
-                #size-cells = <1>;
-
                 ranges = <0 0 0xfe000000 0x02000000>;
 
                 flash@0,0 {
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
index 0c3902bc5b6a..48d72f38e5ed 100644
--- a/arch/powerpc/boot/dts/media5200.dts
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -11,14 +11,11 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
 
 / {
         model = "fsl,media5200";
         compatible = "fsl,media5200";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&mpc5200_pic>;
 
         aliases {
                 console = &console;
@@ -30,16 +27,7 @@
         };
 
         cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
                 PowerPC,5200@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <0x4000>;                // L1, 16K
-                        i-cache-size = <0x4000>;                // L1, 16K
                         timebase-frequency = <33000000>;        // 33 MHz, these were configured by U-Boot
                         bus-frequency = <132000000>;            // 132 MHz
                         clock-frequency = <396000000>;          // 396 MHz
@@ -47,205 +35,57 @@
         };
 
         memory {
-                device_type = "memory";
                 reg = <0x00000000 0x08000000>;  // 128MB RAM
         };
 
-        soc@f0000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc5200b-immr";
-                ranges = <0 0xf0000000 0x0000c000>;
-                reg = <0xf0000000 0x00000100>;
+        soc5200@f0000000 {
                 bus-frequency = <132000000>;// 132 MHz
-                system-frequency = <0>;         // from bootloader
-
-                cdm@200 {
-                        compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
-                        reg = <0x200 0x38>;
-                };
-
-                mpc5200_pic: interrupt-controller@500 {
-                        // 5200 interrupts are encoded into two levels;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
-                        reg = <0x500 0x80>;
-                };
 
                 timer@600 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x600 0x10>;
-                        interrupts = <1 9 0>;
                         fsl,has-wdt;
                 };
 
-                timer@610 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x610 0x10>;
-                        interrupts = <1 10 0>;
-                };
-
-                timer@620 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x620 0x10>;
-                        interrupts = <1 11 0>;
-                };
-
-                timer@630 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x630 0x10>;
-                        interrupts = <1 12 0>;
-                };
-
-                timer@640 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x640 0x10>;
-                        interrupts = <1 13 0>;
-                };
-
-                timer@650 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x650 0x10>;
-                        interrupts = <1 14 0>;
-                };
-
-                timer@660 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x660 0x10>;
-                        interrupts = <1 15 0>;
-                };
-
-                timer@670 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x670 0x10>;
-                        interrupts = <1 16 0>;
-                };
-
-                rtc@800 {       // Real time clock
-                        compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
-                        reg = <0x800 0x100>;
-                        interrupts = <1 5 0 1 6 0>;
-                };
-
-                can@900 {
-                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
-                        interrupts = <2 17 0>;
-                        reg = <0x900 0x80>;
+                psc@2000 {      // PSC1
+                        status = "disabled";
                 };
 
-                can@980 {
-                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
-                        interrupts = <2 18 0>;
-                        reg = <0x980 0x80>;
+                psc@2200 {      // PSC2
+                        status = "disabled";
                 };
 
-                gpio_simple: gpio@b00 {
-                        compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
-                        reg = <0xb00 0x40>;
-                        interrupts = <1 7 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                psc@2400 {      // PSC3
+                        status = "disabled";
                 };
 
-                gpio_wkup: gpio@c00 {
-                        compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
-                        reg = <0xc00 0x40>;
-                        interrupts = <1 8 0 0 3 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                psc@2600 {      // PSC4
+                        status = "disabled";
                 };
 
-                spi@f00 {
-                        compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
-                        reg = <0xf00 0x20>;
-                        interrupts = <2 13 0 2 14 0>;
-                };
-
-                usb@1000 {
-                        compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
-                        reg = <0x1000 0x100>;
-                        interrupts = <2 6 0>;
-                };
-
-                dma-controller@1200 {
-                        compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
-                        reg = <0x1200 0x80>;
-                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
-                                      3 4 0  3 5 0  3 6 0  3 7 0
-                                      3 8 0  3 9 0  3 10 0  3 11 0
-                                      3 12 0  3 13 0  3 14 0  3 15 0>;
-                };
-
-                xlb@1f00 {
-                        compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
-                        reg = <0x1f00 0x100>;
+                psc@2800 {      // PSC5
+                        status = "disabled";
                 };
 
                 // PSC6 in uart mode
-                console: serial@2c00 {          // PSC6
+                console: psc@2c00 {             // PSC6
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        cell-index = <5>;
-                        port-number = <0>;  // Logical port assignment
-                        reg = <0x2c00 0x100>;
-                        interrupts = <2 4 0>;
                 };
 
-                eth0: ethernet@3000 {
-                        compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <0x3000 0x400>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <2 5 0>;
+                ethernet@3000 {
                         phy-handle = <&phy0>;
                 };
 
                 mdio@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
-                        reg = <0x3000 0x400>;   // fec range, since we need to setup fec interrupts
-                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
-
                         phy0: ethernet-phy@0 {
                                 reg = <0>;
                         };
                 };
 
-                ata@3a00 {
-                        compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
-                        reg = <0x3a00 0x100>;
-                        interrupts = <2 7 0>;
-                };
-
-                i2c@3d00 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d00 0x40>;
-                        interrupts = <2 15 0>;
-                };
-
-                i2c@3d40 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d40 0x40>;
-                        interrupts = <2 16 0>;
-                };
-
-                sram@8000 {
-                        compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
-                        reg = <0x8000 0x4000>;
+                usb@1000 {
+                        reg = <0x1000 0x100>;
                 };
         };
 
         pci@f0000d00 {
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                device_type = "pci";
-                compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
-                reg = <0xf0000d00 0x100>;
                 interrupt-map-mask = <0xf800 0 0 7>;
                 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
                                  0xc000 0 0 2 &media5200_fpga 0 3
@@ -262,37 +102,29 @@
 
                                  0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
                                 >;
-                clock-frequency = <0>; // From boot loader
-                interrupts = <2 8 0 2 9 0 2 10 0>;
-                interrupt-parent = <&mpc5200_pic>;
-                bus-range = <0 0>;
                 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
                           0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
                           0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
+                interrupt-parent = <&mpc5200_pic>;
         };
 
         localbus {
-                compatible = "fsl,mpc5200b-lpb","simple-bus";
-                #address-cells = <2>;
-                #size-cells = <1>;
-
                 ranges = < 0 0 0xfc000000 0x02000000
                            1 0 0xfe000000 0x02000000
                            2 0 0xf0010000 0x00010000
                            3 0 0xf0020000 0x00010000 >;
-
                 flash@0,0 {
                         compatible = "amd,am29lv28ml", "cfi-flash";
-                        reg = <0 0x0 0x2000000>;                // 32 MB
-                        bank-width = <4>;                       // Width in bytes of the flash bank
-                        device-width = <2>;                     // Two devices on each bank
+                        reg = <0 0x0 0x2000000>;                // 32 MB
+                        bank-width = <4>;                       // Width in bytes of the flash bank
+                        device-width = <2>;                     // Two devices on each bank
                 };
 
                 flash@1,0 {
                         compatible = "amd,am29lv28ml", "cfi-flash";
-                        reg = <1 0 0x2000000>;                  // 32 MB
-                        bank-width = <4>;                       // Width in bytes of the flash bank
-                        device-width = <2>;                     // Two devices on each bank
+                        reg = <1 0 0x2000000>;                  // 32 MB
+                        bank-width = <4>;                       // Width in bytes of the flash bank
+                        device-width = <2>;                     // Two devices on each bank
                 };
 
                 media5200_fpga: fpga@2,0 {
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 6ca4fc144a33..0b78e89ac69b 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -10,219 +10,73 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
 
 / {
         model = "promess,motionpro";
         compatible = "promess,motionpro";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&mpc5200_pic>;
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                PowerPC,5200@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <0x4000>;        // L1, 16K
-                        i-cache-size = <0x4000>;        // L1, 16K
-                        timebase-frequency = <0>;       // from bootloader
-                        bus-frequency = <0>;            // from bootloader
-                        clock-frequency = <0>;          // from bootloader
-                };
-        };
-
-        memory {
-                device_type = "memory";
-                reg = <0x00000000 0x04000000>;  // 64MB
-        };
 
         soc5200@f0000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc5200b-immr";
-                ranges = <0 0xf0000000 0x0000c000>;
-                reg = <0xf0000000 0x00000100>;
-                bus-frequency = <0>;            // from bootloader
-                system-frequency = <0>;         // from bootloader
-
-                cdm@200 {
-                        compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
-                        reg = <0x200 0x38>;
-                };
-
-                mpc5200_pic: interrupt-controller@500 {
-                        // 5200 interrupts are encoded into two levels;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
-                        reg = <0x500 0x80>;
-                };
-
                 timer@600 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x600 0x10>;
-                        interrupts = <1 9 0>;
                         fsl,has-wdt;
                 };
 
-                timer@610 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x610 0x10>;
-                        interrupts = <1 10 0>;
-                };
-
-                timer@620 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x620 0x10>;
-                        interrupts = <1 11 0>;
-                };
-
-                timer@630 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x630 0x10>;
-                        interrupts = <1 12 0>;
-                };
-
-                timer@640 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x640 0x10>;
-                        interrupts = <1 13 0>;
-                };
-
-                timer@650 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x650 0x10>;
-                        interrupts = <1 14 0>;
-                };
-
-                motionpro-led@660 {     // Motion-PRO status LED
+                timer@660 {     // Motion-PRO status LED
                         compatible = "promess,motionpro-led";
                         label = "motionpro-statusled";
-                        reg = <0x660 0x10>;
-                        interrupts = <1 15 0>;
                         blink-delay = <100>; // 100 msec
                 };
 
-                motionpro-led@670 {     // Motion-PRO ready LED
+                timer@670 {     // Motion-PRO ready LED
                         compatible = "promess,motionpro-led";
                         label = "motionpro-readyled";
-                        reg = <0x670 0x10>;
-                        interrupts = <1 16 0>;
-                };
-
-                rtc@800 {       // Real time clock
-                        compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
-                        reg = <0x800 0x100>;
-                        interrupts = <1 5 0 1 6 0>;
-                };
-
-                can@980 {
-                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
-                        interrupts = <2 18 0>;
-                        reg = <0x980 0x80>;
                 };
 
-                gpio_simple: gpio@b00 {
-                        compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
-                        reg = <0xb00 0x40>;
-                        interrupts = <1 7 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                can@900 {
+                        status = "disabled";
                 };
 
-                gpio_wkup: gpio@c00 {
-                        compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
-                        reg = <0xc00 0x40>;
-                        interrupts = <1 8 0 0 3 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                spi@f00 {
-                        compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
-                        reg = <0xf00 0x20>;
-                        interrupts = <2 13 0 2 14 0>;
+                psc@2000 {              // PSC1
+                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
                 };
 
-                usb@1000 {
-                        compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
-                        reg = <0x1000 0xff>;
-                        interrupts = <2 6 0>;
+                // PSC2 in spi master mode 
+                psc@2200 {              // PSC2
+                        compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
+                        cell-index = <1>;
                 };
 
-                dma-controller@1200 {
-                        compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
-                        reg = <0x1200 0x80>;
-                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
-                                      3 4 0  3 5 0  3 6 0  3 7 0
-                                      3 8 0  3 9 0  3 10 0  3 11 0
-                                      3 12 0  3 13 0  3 14 0  3 15 0>;
+                psc@2400 {              // PSC3
+                        status = "disabled";
                 };
 
-                xlb@1f00 {
-                        compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
-                        reg = <0x1f00 0x100>;
+                psc@2600 {              // PSC4
+                        status = "disabled";
                 };
 
-                serial@2000 {           // PSC1
+                psc@2800 {              // PSC5
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2000 0x100>;
-                        interrupts = <2 1 0>;
-                };
-
-                // PSC2 in spi master mode 
-                spi@2200 {              // PSC2
-                        compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
-                        cell-index = <1>;
-                        reg = <0x2200 0x100>;
-                        interrupts = <2 2 0>;
                 };
 
-                // PSC5 in uart mode
-                serial@2800 {           // PSC5
-                        compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2800 0x100>;
-                        interrupts = <2 12 0>;
+                psc@2c00 {              // PSC6
+                        status = "disabled";
                 };
 
                 ethernet@3000 {
-                        compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <0x3000 0x400>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <2 5 0>;
                         phy-handle = <&phy0>;
                 };
 
                 mdio@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
-                        reg = <0x3000 0x400>;       // fec range, since we need to setup fec interrupts
-                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
-
                         phy0: ethernet-phy@2 {
                                 reg = <2>;
                         };
                 };
 
-                ata@3a00 {
-                        compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
-                        reg = <0x3a00 0x100>;
-                        interrupts = <2 7 0>;
+                i2c@3d00 {
+                        status = "disabled";
                 };
 
                 i2c@3d40 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d40 0x40>;
-                        interrupts = <2 16 0>;
-
                         rtc@68 {
                                 compatible = "dallas,ds1339";
                                 reg = <0x68>;
@@ -235,10 +89,11 @@
                 };
         };
 
+        pci@f0000d00 {
+                status = "disabled";
+        };
+
         localbus {
-                compatible = "fsl,mpc5200b-lpb","simple-bus";
-                #address-cells = <2>;
-                #size-cells = <1>;
                 ranges = <0 0 0xff000000 0x01000000
                           1 0 0x50000000 0x00010000
                           2 0 0x50010000 0x00010000
@@ -280,5 +135,6 @@
                         #size-cells = <1>;
                         #address-cells = <1>;
                 };
+
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc5200b.dtsi b/arch/powerpc/boot/dts/mpc5200b.dtsi
new file mode 100644
index 000000000000..bc27548e895d
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc5200b.dtsi
@@ -0,0 +1,275 @@
+/*
+ * base MPC5200b Device Tree Source
+ *
+ * Copyright (C) 2010 SecretLab
+ * Grant Likely <grant@secretlab.ca>
+ * John Bonesio <bones@secretlab.ca>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "fsl,mpc5200b";
+        compatible = "fsl,mpc5200b";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&mpc5200_pic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                powerpc: PowerPC,5200@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <0x4000>;        // L1, 16K
+                        i-cache-size = <0x4000>;        // L1, 16K
+                        timebase-frequency = <0>;       // from bootloader
+                        bus-frequency = <0>;            // from bootloader
+                        clock-frequency = <0>;          // from bootloader
+                };
+        };
+
+        memory: memory {
+                device_type = "memory";
+                reg = <0x00000000 0x04000000>;  // 64MB
+        };
+
+        soc: soc5200@f0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc5200b-immr";
+                ranges = <0 0xf0000000 0x0000c000>;
+                reg = <0xf0000000 0x00000100>;
+                bus-frequency = <0>;            // from bootloader
+                system-frequency = <0>;         // from bootloader
+
+                cdm@200 {
+                        compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
+                        reg = <0x200 0x38>;
+                };
+
+                mpc5200_pic: interrupt-controller@500 {
+                        // 5200 interrupts are encoded into two levels;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
+                        reg = <0x500 0x80>;
+                };
+
+                timer@600 {     // General Purpose Timer
+                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+                        reg = <0x600 0x10>;
+                        interrupts = <1 9 0>;
+                };
+
+                timer@610 {     // General Purpose Timer
+                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+                        reg = <0x610 0x10>;
+                        interrupts = <1 10 0>;
+                };
+
+                timer@620 {     // General Purpose Timer
+                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+                        reg = <0x620 0x10>;
+                        interrupts = <1 11 0>;
+                };
+
+                timer@630 {     // General Purpose Timer
+                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+                        reg = <0x630 0x10>;
+                        interrupts = <1 12 0>;
+                };
+
+                timer@640 {     // General Purpose Timer
+                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+                        reg = <0x640 0x10>;
+                        interrupts = <1 13 0>;
+                };
+
+                timer@650 {     // General Purpose Timer
+                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+                        reg = <0x650 0x10>;
+                        interrupts = <1 14 0>;
+                };
+
+                timer@660 {     // General Purpose Timer
+                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+                        reg = <0x660 0x10>;
+                        interrupts = <1 15 0>;
+                };
+
+                timer@670 {     // General Purpose Timer
+                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+                        reg = <0x670 0x10>;
+                        interrupts = <1 16 0>;
+                };
+
+                rtc@800 {       // Real time clock
+                        compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
+                        reg = <0x800 0x100>;
+                        interrupts = <1 5 0 1 6 0>;
+                };
+
+                can@900 {
+                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
+                        interrupts = <2 17 0>;
+                        reg = <0x900 0x80>;
+                };
+
+                can@980 {
+                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
+                        interrupts = <2 18 0>;
+                        reg = <0x980 0x80>;
+                };
+
+                gpio_simple: gpio@b00 {
+                        compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
+                        reg = <0xb00 0x40>;
+                        interrupts = <1 7 0>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpio_wkup: gpio@c00 {
+                        compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
+                        reg = <0xc00 0x40>;
+                        interrupts = <1 8 0 0 3 0>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                spi@f00 {
+                        compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
+                        reg = <0xf00 0x20>;
+                        interrupts = <2 13 0 2 14 0>;
+                };
+
+                usb: usb@1000 {
+                        compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
+                        reg = <0x1000 0xff>;
+                        interrupts = <2 6 0>;
+                };
+
+                dma-controller@1200 {
+                        compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
+                        reg = <0x1200 0x80>;
+                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
+                                      3 4 0  3 5 0  3 6 0  3 7 0
+                                      3 8 0  3 9 0  3 10 0  3 11 0
+                                      3 12 0  3 13 0  3 14 0  3 15 0>;
+                };
+
+                xlb@1f00 {
+                        compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
+                        reg = <0x1f00 0x100>;
+                };
+
+                psc1: psc@2000 {                // PSC1
+                        compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+                        reg = <0x2000 0x100>;
+                        interrupts = <2 1 0>;
+                };
+
+                psc2: psc@2200 {                // PSC2
+                        compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+                        reg = <0x2200 0x100>;
+                        interrupts = <2 2 0>;
+                };
+
+                psc3: psc@2400 {                // PSC3
+                        compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+                        reg = <0x2400 0x100>;
+                        interrupts = <2 3 0>;
+                };
+
+                psc4: psc@2600 {                // PSC4
+                        compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+                        reg = <0x2600 0x100>;
+                        interrupts = <2 11 0>;
+                };
+
+                psc5: psc@2800 {                // PSC5
+                        compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+                        reg = <0x2800 0x100>;
+                        interrupts = <2 12 0>;
+                };
+
+                psc6: psc@2c00 {                // PSC6
+                        compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
+                        reg = <0x2c00 0x100>;
+                        interrupts = <2 4 0>;
+                };
+
+                eth0: ethernet@3000 {
+                        compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
+                        reg = <0x3000 0x400>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <2 5 0>;
+                };
+
+                mdio@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
+                        reg = <0x3000 0x400>;   // fec range, since we need to setup fec interrupts
+                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
+                };
+
+                ata@3a00 {
+                        compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
+                        reg = <0x3a00 0x100>;
+                        interrupts = <2 7 0>;
+                };
+
+                i2c@3d00 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+                        reg = <0x3d00 0x40>;
+                        interrupts = <2 15 0>;
+                };
+
+                i2c@3d40 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
+                        reg = <0x3d40 0x40>;
+                        interrupts = <2 16 0>;
+                };
+
+                sram@8000 {
+                        compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
+                        reg = <0x8000 0x4000>;
+                };
+        };
+
+        pci: pci@f0000d00 {
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                device_type = "pci";
+                compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
+                reg = <0xf0000d00 0x100>;
+                // interrupt-map-mask = need to add
+                // interrupt-map = need to add
+                clock-frequency = <0>; // From boot loader
+                interrupts = <2 8 0 2 9 0 2 10 0>;
+                bus-range = <0 0>;
+                // ranges = need to add
+        };
+
+        localbus: localbus {
+                compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0xfc000000 0x2000000>;
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8308_p1m.dts b/arch/powerpc/boot/dts/mpc8308_p1m.dts
index 05a76ccfd499..697b3f6b78bf 100644
--- a/arch/powerpc/boot/dts/mpc8308_p1m.dts
+++ b/arch/powerpc/boot/dts/mpc8308_p1m.dts
@@ -297,6 +297,14 @@
                         interrupt-parent = < &ipic >;
                 };
 
+                dma@2c000 {
+                        compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
+                        reg = <0x2c000 0x1800>;
+                        interrupts = <3 0x8
+                                        94 0x8>;
+                        interrupt-parent = < &ipic >;
+                };
+
         };
 
         pci0: pcie@e0009000 {
diff --git a/arch/powerpc/boot/dts/mpc8308rdb.dts b/arch/powerpc/boot/dts/mpc8308rdb.dts
index a97eb2db5a18..d3db02f98ddd 100644
--- a/arch/powerpc/boot/dts/mpc8308rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8308rdb.dts
@@ -265,6 +265,14 @@
                         interrupt-parent = < &ipic >;
                 };
 
+                dma@2c000 {
+                        compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma";
+                        reg = <0x2c000 0x1800>;
+                        interrupts = <3 0x8
+                                        94 0x8>;
+                        interrupt-parent = < &ipic >;
+                };
+
         };
 
         pci0: pcie@e0009000 {
diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts
index b72a7581d798..21d34720fcc9 100644
--- a/arch/powerpc/boot/dts/mucmc52.dts
+++ b/arch/powerpc/boot/dts/mucmc52.dts
@@ -11,172 +11,109 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
 
 / {
         model = "manroland,mucmc52";
         compatible = "manroland,mucmc52";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&mpc5200_pic>;
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                PowerPC,5200@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <0x4000>;        // L1, 16K
-                        i-cache-size = <0x4000>;        // L1, 16K
-                        timebase-frequency = <0>;       // from bootloader
-                        bus-frequency = <0>;            // from bootloader
-                        clock-frequency = <0>;          // from bootloader
-                };
-        };
-
-        memory {
-                device_type = "memory";
-                reg = <0x00000000 0x04000000>;  // 64MB
-        };
 
         soc5200@f0000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc5200b-immr";
-                ranges = <0 0xf0000000 0x0000c000>;
-                reg = <0xf0000000 0x00000100>;
-                bus-frequency = <0>;            // from bootloader
-                system-frequency = <0>;         // from bootloader
-
-                cdm@200 {
-                        compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
-                        reg = <0x200 0x38>;
-                };
-
-                mpc5200_pic: interrupt-controller@500 {
-                        // 5200 interrupts are encoded into two levels;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
-                        reg = <0x500 0x80>;
-                };
-
                 gpt0: timer@600 {       // GPT 0 in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x600 0x10>;
-                        interrupts = <1 9 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt1: timer@610 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x610 0x10>;
-                        interrupts = <1 10 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt2: timer@620 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x620 0x10>;
-                        interrupts = <1 11 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt3: timer@630 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x630 0x10>;
-                        interrupts = <1 12 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
-                gpio_simple: gpio@b00 {
-                        compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
-                        reg = <0xb00 0x40>;
-                        interrupts = <1 7 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                timer@640 {
+                        status = "disabled";
                 };
 
-                gpio_wkup: gpio@c00 {
-                        compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
-                        reg = <0xc00 0x40>;
-                        interrupts = <1 8 0 0 3 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                timer@650 {
+                        status = "disabled";
+                };
+
+                timer@660 {
+                        status = "disabled";
+                };
+
+                timer@670 {
+                        status = "disabled";
                 };
 
-                dma-controller@1200 {
-                        compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
-                        reg = <0x1200 0x80>;
-                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
-                                      3 4 0  3 5 0  3 6 0  3 7 0
-                                      3 8 0  3 9 0  3 10 0  3 11 0
-                                      3 12 0  3 13 0  3 14 0  3 15 0>;
+                rtc@800 {
+                        status = "disabled";
                 };
 
-                xlb@1f00 {
-                        compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
-                        reg = <0x1f00 0x100>;
+                can@900 {
+                        status = "disabled";
                 };
 
-                serial@2000 { /* PSC1 in UART mode */
+                can@980 {
+                        status = "disabled";
+                };
+
+                spi@f00 {
+                        status = "disabled";
+                };
+
+                usb@1000 {
+                        status = "disabled";
+                };
+
+                psc@2000 {              // PSC1
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2000 0x100>;
-                        interrupts = <2 1 0>;
                 };
 
-                serial@2200 { /* PSC2 in UART mode */
+                psc@2200 {              // PSC2
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2200 0x100>;
-                        interrupts = <2 2 0>;
                 };
 
-                serial@2c00 { /* PSC6 in UART mode */
+                psc@2400 {              // PSC3
+                        status = "disabled";
+                };
+
+                psc@2600 {              // PSC4
+                        status = "disabled";
+                };
+
+                psc@2800 {              // PSC5
+                        status = "disabled";
+                };
+
+                psc@2c00 {              // PSC6
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2c00 0x100>;
-                        interrupts = <2 4 0>;
                 };
 
                 ethernet@3000 {
-                        compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <0x3000 0x400>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <2 5 0>;
                         phy-handle = <&phy0>;
                 };
 
                 mdio@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
-                        reg = <0x3000 0x400>;   // fec range, since we need to setup fec interrupts
-                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
-
                         phy0: ethernet-phy@0 {
                                 compatible = "intel,lxt971";
                                 reg = <0>;
                         };
                 };
 
-                ata@3a00 {
-                        compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
-                        reg = <0x3a00 0x100>;
-                        interrupts = <2 7 0>;
+                i2c@3d00 {
+                        status = "disabled";
                 };
 
                 i2c@3d40 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d40 0x40>;
-                        interrupts = <2 16 0>;
                         hwmon@2c {
                                 compatible = "ad,adm9240";
                                 reg = <0x2c>;
@@ -186,20 +123,9 @@
                                 reg = <0x51>;
                         };
                 };
-
-                sram@8000 {
-                        compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
-                        reg = <0x8000 0x4000>;
-                };
         };
 
         pci@f0000d00 {
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                device_type = "pci";
-                compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
-                reg = <0xf0000d00 0x100>;
                 interrupt-map-mask = <0xf800 0 0 7>;
                 interrupt-map = <
                                 /* IDSEL 0x10 */
@@ -208,20 +134,12 @@
                                 0x8000 0 0 3 &mpc5200_pic 0 2 3
                                 0x8000 0 0 4 &mpc5200_pic 0 1 3
                                 >;
-                clock-frequency = <0>; // From boot loader
-                interrupts = <2 8 0 2 9 0 2 10 0>;
-                bus-range = <0 0>;
                 ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
                           0x02000000 0 0x90000000 0x90000000 0 0x10000000
                           0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
         };
 
         localbus {
-                compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
-
-                #address-cells = <2>;
-                #size-cells = <1>;
-
                 ranges = <0 0 0xff800000 0x00800000
                           1 0 0x80000000 0x00800000
                           3 0 0x80000000 0x00800000>;
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index 8a4ec30b21ae..9e354997eb7e 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -12,246 +12,92 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
 
 / {
         model = "phytec,pcm030";
         compatible = "phytec,pcm030";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&mpc5200_pic>;
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                PowerPC,5200@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <0x4000>;        // L1, 16K
-                        i-cache-size = <0x4000>;        // L1, 16K
-                        timebase-frequency = <0>;       // from bootloader
-                        bus-frequency = <0>;            // from bootloader
-                        clock-frequency = <0>;          // from bootloader
-                };
-        };
-
-        memory {
-                device_type = "memory";
-                reg = <0x00000000 0x04000000>;  // 64MB
-        };
 
         soc5200@f0000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc5200b-immr";
-                ranges = <0 0xf0000000 0x0000c000>;
-                bus-frequency = <0>;            // from bootloader
-                system-frequency = <0>;         // from bootloader
-
-                cdm@200 {
-                        compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
-                        reg = <0x200 0x38>;
-                };
-
-                mpc5200_pic: interrupt-controller@500 {
-                        // 5200 interrupts are encoded into two levels;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
-                        reg = <0x500 0x80>;
-                };
-
-                timer@600 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x600 0x10>;
-                        interrupts = <1 9 0>;
+                timer@600 {             // General Purpose Timer
                         fsl,has-wdt;
                 };
 
-                timer@610 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x610 0x10>;
-                        interrupts = <1 10 0>;
-                };
-
                 gpt2: timer@620 {       // General Purpose Timer in GPIO mode
                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
-                        reg = <0x620 0x10>;
-                        interrupts = <1 11 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt3: timer@630 {       // General Purpose Timer in GPIO mode
                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
-                        reg = <0x630 0x10>;
-                        interrupts = <1 12 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt4: timer@640 {       // General Purpose Timer in GPIO mode
                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
-                        reg = <0x640 0x10>;
-                        interrupts = <1 13 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt5: timer@650 {       // General Purpose Timer in GPIO mode
                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
-                        reg = <0x650 0x10>;
-                        interrupts = <1 14 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt6: timer@660 {       // General Purpose Timer in GPIO mode
                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
-                        reg = <0x660 0x10>;
-                        interrupts = <1 15 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt7: timer@670 {       // General Purpose Timer in GPIO mode
                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
-                        reg = <0x670 0x10>;
-                        interrupts = <1 16 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                rtc@800 {       // Real time clock
-                        compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
-                        reg = <0x800 0x100>;
-                        interrupts = <1 5 0 1 6 0>;
-                };
-
-                can@900 {
-                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
-                        interrupts = <2 17 0>;
-                        reg = <0x900 0x80>;
-                };
-
-                can@980 {
-                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
-                        interrupts = <2 18 0>;
-                        reg = <0x980 0x80>;
-                };
-
-                gpio_simple: gpio@b00 {
-                        compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
-                        reg = <0xb00 0x40>;
-                        interrupts = <1 7 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
-                gpio_wkup: gpio@c00 {
-                        compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
-                        reg = <0xc00 0x40>;
-                        interrupts = <1 8 0 0 3 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                spi@f00 {
-                        compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
-                        reg = <0xf00 0x20>;
-                        interrupts = <2 13 0 2 14 0>;
-                };
-
-                usb@1000 {
-                        compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
-                        reg = <0x1000 0xff>;
-                        interrupts = <2 6 0>;
-                };
-
-                dma-controller@1200 {
-                        compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
-                        reg = <0x1200 0x80>;
-                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
-                                      3 4 0  3 5 0  3 6 0  3 7 0
-                                      3 8 0  3 9 0  3 10 0  3 11 0
-                                      3 12 0  3 13 0  3 14 0  3 15 0>;
-                };
-
-                xlb@1f00 {
-                        compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
-                        reg = <0x1f00 0x100>;
-                };
-
-                ac97@2000 { /* PSC1 in ac97 mode */
+                psc@2000 { /* PSC1 in ac97 mode */
                         compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
                         cell-index = <0>;
-                        reg = <0x2000 0x100>;
-                        interrupts = <2 1 0>;
                 };
 
                 /* PSC2 port is used by CAN1/2 */
+                psc@2200 {
+                        status = "disabled";
+                };
 
-                serial@2400 { /* PSC3 in UART mode */
+                psc@2400 { /* PSC3 in UART mode */
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        cell-index = <2>;
-                        reg = <0x2400 0x100>;
-                        interrupts = <2 3 0>;
                 };
 
                 /* PSC4 is ??? */
+                psc@2600 {
+                        status = "disabled";
+                };
 
                 /* PSC5 is ??? */
+                psc@2800 {
+                        status = "disabled";
+                };
 
-                serial@2c00 { /* PSC6 in UART mode */
+                psc@2c00 { /* PSC6 in UART mode */
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        cell-index = <5>;
-                        reg = <0x2c00 0x100>;
-                        interrupts = <2 4 0>;
                 };
 
                 ethernet@3000 {
-                        compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <0x3000 0x400>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <2 5 0>;
                         phy-handle = <&phy0>;
                 };
 
                 mdio@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
-                        reg = <0x3000 0x400>;   // fec range, since we need to setup fec interrupts
-                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
-
                         phy0: ethernet-phy@0 {
                                 reg = <0>;
                         };
                 };
 
-                ata@3a00 {
-                        compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
-                        reg = <0x3a00 0x100>;
-                        interrupts = <2 7 0>;
-                };
-
-                i2c@3d00 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d00 0x40>;
-                        interrupts = <2 15 0>;
-                };
-
                 i2c@3d40 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d40 0x40>;
-                        interrupts = <2 16 0>;
                         rtc@51 {
                                 compatible = "nxp,pcf8563";
                                 reg = <0x51>;
@@ -259,6 +105,7 @@
                         eeprom@52 {
                                 compatible = "catalyst,24c32";
                                 reg = <0x52>;
+                                pagesize = <32>;
                         };
                 };
 
@@ -269,12 +116,6 @@
         };
 
         pci@f0000d00 {
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                device_type = "pci";
-                compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
-                reg = <0xf0000d00 0x100>;
                 interrupt-map-mask = <0xf800 0 0 7>;
                 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
                                  0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -285,11 +126,12 @@
                                  0xc800 0 0 2 &mpc5200_pic 1 2 3
                                  0xc800 0 0 3 &mpc5200_pic 1 3 3
                                  0xc800 0 0 4 &mpc5200_pic 0 0 3>;
-                clock-frequency = <0>; // From boot loader
-                interrupts = <2 8 0 2 9 0 2 10 0>;
-                bus-range = <0 0>;
                 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
                           0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
                           0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
         };
+
+        localbus {
+                status = "disabled";
+        };
 };
diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
index 85d857a5d46e..1dd478bfff96 100644
--- a/arch/powerpc/boot/dts/pcm032.dts
+++ b/arch/powerpc/boot/dts/pcm032.dts
@@ -12,99 +12,37 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
 
 / {
         model = "phytec,pcm032";
         compatible = "phytec,pcm032";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&mpc5200_pic>;
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                PowerPC,5200@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <0x4000>;        // L1, 16K
-                        i-cache-size = <0x4000>;        // L1, 16K
-                        timebase-frequency = <0>;       // from bootloader
-                        bus-frequency = <0>;            // from bootloader
-                        clock-frequency = <0>;          // from bootloader
-                };
-        };
 
         memory {
-                device_type = "memory";
                 reg = <0x00000000 0x08000000>;  // 128MB
         };
 
         soc5200@f0000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc5200b-immr";
-                ranges = <0 0xf0000000 0x0000c000>;
-                bus-frequency = <0>;            // from bootloader
-                system-frequency = <0>;         // from bootloader
-
-                cdm@200 {
-                        compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
-                        reg = <0x200 0x38>;
-                };
-
-                mpc5200_pic: interrupt-controller@500 {
-                        // 5200 interrupts are encoded into two levels;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
-                        reg = <0x500 0x80>;
-                };
-
-                timer@600 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x600 0x10>;
-                        interrupts = <1 9 0>;
+                timer@600 {             // General Purpose Timer
                         fsl,has-wdt;
                 };
 
-                timer@610 {     // General Purpose Timer
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x610 0x10>;
-                        interrupts = <1 10 0>;
-                };
-
                 gpt2: timer@620 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x620 0x10>;
-                        interrupts = <1 11 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt3: timer@630 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x630 0x10>;
-                        interrupts = <1 12 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt4: timer@640 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x640 0x10>;
-                        interrupts = <1 13 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt5: timer@650 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x650 0x10>;
-                        interrupts = <1 14 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
@@ -118,163 +56,62 @@
                 };
 
                 gpt7: timer@670 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x670 0x10>;
-                        interrupts = <1 16 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
-                rtc@800 {       // Real time clock
-                        compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
-                        reg = <0x800 0x100>;
-                        interrupts = <1 5 0 1 6 0>;
-                };
-
-                can@900 {
-                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
-                        interrupts = <2 17 0>;
-                        reg = <0x900 0x80>;
-                };
-
-                can@980 {
-                        compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
-                        interrupts = <2 18 0>;
-                        reg = <0x980 0x80>;
-                };
-
-                gpio_simple: gpio@b00 {
-                        compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
-                        reg = <0xb00 0x40>;
-                        interrupts = <1 7 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                gpio_wkup: gpio@c00 {
-                        compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
-                        reg = <0xc00 0x40>;
-                        interrupts = <1 8 0 0 3 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
-                };
-
-                spi@f00 {
-                        compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
-                        reg = <0xf00 0x20>;
-                        interrupts = <2 13 0 2 14 0>;
-                };
-
-                usb@1000 {
-                        compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
-                        reg = <0x1000 0xff>;
-                        interrupts = <2 6 0>;
-                };
-
-                dma-controller@1200 {
-                        compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
-                        reg = <0x1200 0x80>;
-                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
-                                      3 4 0  3 5 0  3 6 0  3 7 0
-                                      3 8 0  3 9 0  3 10 0  3 11 0
-                                      3 12 0  3 13 0  3 14 0  3 15 0>;
-                };
-
-                xlb@1f00 {
-                        compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
-                        reg = <0x1f00 0x100>;
-                };
-
-                ac97@2000 {     /* PSC1 is ac97 */
+                psc@2000 {      /* PSC1 is ac97 */
                         compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
                         cell-index = <0>;
-                        reg = <0x2000 0x100>;
-                        interrupts = <2 1 0>;
                 };
 
                 /* PSC2 port is used by CAN1/2 */
+                psc@2200 {
+                        status = "disabled";
+                };
 
-                serial@2400 { /* PSC3 in UART mode */
+                psc@2400 { /* PSC3 in UART mode */
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        cell-index = <2>;
-                        reg = <0x2400 0x100>;
-                        interrupts = <2 3 0>;
                 };
 
                 /* PSC4 is ??? */
+                psc@2600 {
+                        status = "disabled";
+                };
 
                 /* PSC5 is ??? */
+                psc@2800 {
+                        status = "disabled";
+                };
 
-                serial@2c00 { /* PSC6 in UART mode */
+                psc@2c00 { /* PSC6 in UART mode */
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        cell-index = <5>;
-                        reg = <0x2c00 0x100>;
-                        interrupts = <2 4 0>;
                 };
 
                 ethernet@3000 {
-                        compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <0x3000 0x400>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <2 5 0>;
                         phy-handle = <&phy0>;
                 };
 
                 mdio@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
-                        reg = <0x3000 0x400>;   // fec range, since we need to setup fec interrupts
-                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
-
                         phy0: ethernet-phy@0 {
                                 reg = <0>;
                         };
                 };
 
-                ata@3a00 {
-                        compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
-                        reg = <0x3a00 0x100>;
-                        interrupts = <2 7 0>;
-                };
-
-                i2c@3d00 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d00 0x40>;
-                        interrupts = <2 15 0>;
-                };
-
                 i2c@3d40 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d40 0x40>;
-                        interrupts = <2 16 0>;
                         rtc@51 {
                                 compatible = "nxp,pcf8563";
                                 reg = <0x51>;
                         };
                         eeprom@52 {
-                                compatible = "at24,24c32";
+                                compatible = "catalyst,24c32";
                                 reg = <0x52>;
+                                pagesize = <32>;
                         };
                 };
-
-                sram@8000 {
-                        compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
-                        reg = <0x8000 0x4000>;
-                };
         };
 
         pci@f0000d00 {
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                device_type = "pci";
-                compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
-                reg = <0xf0000d00 0x100>;
                 interrupt-map-mask = <0xf800 0 0 7>;
                 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
                                  0xc000 0 0 2 &mpc5200_pic 1 1 3
@@ -285,20 +122,12 @@
                                  0xc800 0 0 2 &mpc5200_pic 1 2 3
                                  0xc800 0 0 3 &mpc5200_pic 1 3 3
                                  0xc800 0 0 4 &mpc5200_pic 0 0 3>;
-                clock-frequency = <0>; // From boot loader
-                interrupts = <2 8 0 2 9 0 2 10 0>;
-                bus-range = <0 0>;
                 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
                           0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
                           0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
         };
 
         localbus {
-                compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
-
-                #address-cells = <2>;
-                #size-cells = <1>;
-
                 ranges = <0 0 0xfe000000 0x02000000
                           1 0 0xfc000000 0x02000000
                           2 0 0xfbe00000 0x00200000
@@ -351,40 +180,39 @@
                         bank-width = <2>;
                 };
 
-                /*
+                /*
                  * example snippets for FPGA
                  *
                  * fpga@3,0 {
-                 *         compatible = "fpga_driver";
-                 *         reg = <3 0 0x02000000>;
-                 *         bank-width = <4>;
+                 *       compatible = "fpga_driver";
+                 *       reg = <3 0 0x02000000>;
+                 *       bank-width = <4>;
                  * };
                  *
                  * fpga@4,0 {
-                 *         compatible = "fpga_driver";
-                 *         reg = <4 0 0x02000000>;
-                 *         bank-width = <4>;
+                 *       compatible = "fpga_driver";
+                 *       reg = <4 0 0x02000000>;
+                 *       bank-width = <4>;
                  * };
-                 */
+                 */
 
-                /*
+                /*
                  * example snippets for free chipselects
-                 *
+                 *
                  * device@5,0 {
-                 *         compatible = "custom_driver";
-                 *         reg = <5 0 0x02000000>;
+                 *       compatible = "custom_driver";
+                 *       reg = <5 0 0x02000000>;
                  * };
-                 *
+                 *
                  * device@6,0 {
-                 *         compatible = "custom_driver";
-                 *         reg = <6 0 0x02000000>;
+                 *       compatible = "custom_driver";
+                 *       reg = <6 0 0x02000000>;
                  * };
-                 *
+                 *
                  * device@7,0 {
-                 *         compatible = "custom_driver";
-                 *         reg = <7 0 0x02000000>;
+                 *       compatible = "custom_driver";
+                 *       reg = <7 0 0x02000000>;
                  * };
-                 */
+                 */
         };
 };
-
diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
index 019264c62904..ba83d5488ec6 100644
--- a/arch/powerpc/boot/dts/uc101.dts
+++ b/arch/powerpc/boot/dts/uc101.dts
@@ -11,79 +11,24 @@
  * option) any later version.
  */
 
-/dts-v1/;
+/include/ "mpc5200b.dtsi"
 
 / {
         model = "manroland,uc101";
         compatible = "manroland,uc101";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&mpc5200_pic>;
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                PowerPC,5200@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <0x4000>;        // L1, 16K
-                        i-cache-size = <0x4000>;        // L1, 16K
-                        timebase-frequency = <0>;       // from bootloader
-                        bus-frequency = <0>;            // from bootloader
-                        clock-frequency = <0>;          // from bootloader
-                };
-        };
-
-        memory {
-                device_type = "memory";
-                reg = <0x00000000 0x04000000>;  // 64MB
-        };
 
         soc5200@f0000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "fsl,mpc5200b-immr";
-                ranges = <0 0xf0000000 0x0000c000>;
-                reg = <0xf0000000 0x00000100>;
-                bus-frequency = <0>;            // from bootloader
-                system-frequency = <0>;         // from bootloader
-
-                cdm@200 {
-                        compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
-                        reg = <0x200 0x38>;
-                };
-
-                mpc5200_pic: interrupt-controller@500 {
-                        // 5200 interrupts are encoded into two levels;
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
-                        reg = <0x500 0x80>;
-                };
-
                 gpt0: timer@600 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x600 0x10>;
-                        interrupts = <1 9 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt1: timer@610 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x610 0x10>;
-                        interrupts = <1 10 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt2: timer@620 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x620 0x10>;
-                        interrupts = <1 11 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
@@ -97,118 +42,85 @@
                 };
 
                 gpt4: timer@640 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x640 0x10>;
-                        interrupts = <1 13 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt5: timer@650 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x650 0x10>;
-                        interrupts = <1 14 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt6: timer@660 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x660 0x10>;
-                        interrupts = <1 15 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
                 gpt7: timer@670 {       // General Purpose Timer in GPIO mode
-                        compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
-                        reg = <0x670 0x10>;
-                        interrupts = <1 16 0>;
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
 
-                gpio_simple: gpio@b00 {
-                        compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
-                        reg = <0xb00 0x40>;
-                        interrupts = <1 7 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                rtc@800 {
+                        status = "disabled";
                 };
 
-                gpio_wkup: gpio@c00 {
-                        compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
-                        reg = <0xc00 0x40>;
-                        interrupts = <1 8 0 0 3 0>;
-                        gpio-controller;
-                        #gpio-cells = <2>;
+                can@900 {
+                        status = "disabled";
+                };
+
+                can@980 {
+                        status = "disabled";
                 };
 
-                dma-controller@1200 {
-                        compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
-                        reg = <0x1200 0x80>;
-                        interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
-                                      3 4 0  3 5 0  3 6 0  3 7 0
-                                      3 8 0  3 9 0  3 10 0  3 11 0
-                                      3 12 0  3 13 0  3 14 0  3 15 0>;
+                spi@f00 {
+                        status = "disabled";
                 };
 
-                xlb@1f00 {
-                        compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
-                        reg = <0x1f00 0x100>;
+                usb@1000 {
+                        status = "disabled";
                 };
 
-                serial@2000 { /* PSC1 in UART mode */
+                psc@2000 {      // PSC1
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2000 0x100>;
-                        interrupts = <2 1 0>;
                 };
 
-                serial@2200 { /* PSC2 in UART mode */
+                psc@2200 {      // PSC2
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2200 0x100>;
-                        interrupts = <2 2 0>;
                 };
 
-                serial@2c00 {           /* PSC6 in UART mode */
+                psc@2400 {      // PSC3
+                        status = "disabled";
+                };
+
+                psc@2600 {      // PSC4
+                        status = "disabled";
+                };
+
+                psc@2800 {      // PSC5
+                        status = "disabled";
+                };
+
+                psc@2c00 {      // PSC6
                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
-                        reg = <0x2c00 0x100>;
-                        interrupts = <2 4 0>;
                 };
 
                 ethernet@3000 {
-                        compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
-                        reg = <0x3000 0x400>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <2 5 0>;
                         phy-handle = <&phy0>;
                 };
 
                 mdio@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
-                        reg = <0x3000 0x400>;   // fec range, since we need to setup fec interrupts
-                        interrupts = <2 5 0>;   // these are for "mii command finished", not link changes & co.
-
                         phy0: ethernet-phy@0 {
                                 compatible = "intel,lxt971";
                                 reg = <0>;
                         };
                 };
 
-                ata@3a00 {
-                        compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
-                        reg = <0x3a00 0x100>;
-                        interrupts = <2 7 0>;
+                i2c@3d00 {
+                        status = "disabled";
                 };
 
                 i2c@3d40 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                        reg = <0x3d40 0x40>;
-                        interrupts = <2 16 0>;
                         fsl,preserve-clocking;
                         clock-frequency = <400000>;
 
@@ -221,19 +133,13 @@
                                 reg = <0x51>;
                         };
                 };
+        };
 
-                sram@8000 {
-                        compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
-                        reg = <0x8000 0x4000>;
-                };
+        pci@f0000d00 {
+                status = "disabled";
         };
 
         localbus {
-                compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
-
-                #address-cells = <2>;
-                #size-cells = <1>;
-
                 ranges = <0 0 0xff800000 0x00800000
                           1 0 0x80000000 0x00800000
                           3 0 0x80000000 0x00800000>;
diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig
index 4e19ee7ce4ee..34b8c1a1e752 100644
--- a/arch/powerpc/configs/40x/kilauea_defconfig
+++ b/arch/powerpc/configs/40x/kilauea_defconfig
@@ -12,6 +12,8 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_KILAUEA=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 # CONFIG_WALNUT is not set
 CONFIG_SPARSE_IRQ=y
 CONFIG_PCI=y
@@ -42,6 +44,9 @@ CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_NDFC=y
 CONFIG_PROC_DEVICETREE=y
+CONFIG_PM=y
+CONFIG_SUSPEND=y
+CONFIG_PPC4xx_CPM=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=35000
 # CONFIG_MISC_DEVICES is not set
diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig
index 45c64d818b2a..17e4dd98eed7 100644
--- a/arch/powerpc/configs/44x/canyonlands_defconfig
+++ b/arch/powerpc/configs/44x/canyonlands_defconfig
@@ -42,6 +42,9 @@ CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_NDFC=y
 CONFIG_PROC_DEVICETREE=y
+CONFIG_PM=y
+CONFIG_SUSPEND=y
+CONFIG_PPC4xx_CPM=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=35000
 # CONFIG_MISC_DEVICES is not set
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 30964ae2d096..8a7e9314c68a 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -267,7 +267,16 @@ static __inline__ int fls64(__u64 x)
 #include <asm-generic/bitops/fls64.h>
 #endif /* __powerpc64__ */
 
+#ifdef CONFIG_PPC64
+unsigned int __arch_hweight8(unsigned int w);
+unsigned int __arch_hweight16(unsigned int w);
+unsigned int __arch_hweight32(unsigned int w);
+unsigned long __arch_hweight64(__u64 w);
+#include <asm-generic/bitops/const_hweight.h>
+#else
 #include <asm-generic/bitops/hweight.h>
+#endif
+
 #include <asm-generic/bitops/find.h>
 
 /* Little-endian versions */
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index f3a1fdd9cf08..f0a211d96923 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -199,6 +199,8 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_UNALIGNED_LD_STD        LONG_ASM_CONST(0x0080000000000000)
 #define CPU_FTR_ASYM_SMT                LONG_ASM_CONST(0x0100000000000000)
 #define CPU_FTR_STCX_CHECKS_ADDRESS     LONG_ASM_CONST(0x0200000000000000)
+#define CPU_FTR_POPCNTB                 LONG_ASM_CONST(0x0400000000000000)
+#define CPU_FTR_POPCNTD                 LONG_ASM_CONST(0x0800000000000000)
 
 #ifndef __ASSEMBLY__
 
@@ -403,21 +405,22 @@ extern const char *powerpc_base_platform;
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
-            CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS)
+            CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \
+            CPU_FTR_POPCNTB)
 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
             CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
-            CPU_FTR_STCX_CHECKS_ADDRESS)
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
             CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
-            CPU_FTR_STCX_CHECKS_ADDRESS)
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
 #define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
diff --git a/arch/powerpc/include/asm/cputhreads.h b/arch/powerpc/include/asm/cputhreads.h
index a8e18447c62b..f71bb4c118b4 100644
--- a/arch/powerpc/include/asm/cputhreads.h
+++ b/arch/powerpc/include/asm/cputhreads.h
@@ -61,22 +61,25 @@ static inline cpumask_t cpu_online_cores_map(void)
         return cpu_thread_mask_to_cores(cpu_online_map);
 }
 
-static inline int cpu_thread_to_core(int cpu)
-{
-        return cpu >> threads_shift;
-}
+#ifdef CONFIG_SMP
+int cpu_core_index_of_thread(int cpu);
+int cpu_first_thread_of_core(int core);
+#else
+static inline int cpu_core_index_of_thread(int cpu) { return cpu; }
+static inline int cpu_first_thread_of_core(int core) { return core; }
+#endif
 
 static inline int cpu_thread_in_core(int cpu)
 {
         return cpu & (threads_per_core - 1);
 }
 
-static inline int cpu_first_thread_in_core(int cpu)
+static inline int cpu_first_thread_sibling(int cpu)
 {
         return cpu & ~(threads_per_core - 1);
 }
 
-static inline int cpu_last_thread_in_core(int cpu)
+static inline int cpu_last_thread_sibling(int cpu)
 {
         return cpu | (threads_per_core - 1);
 }
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index a3954e4fcbe2..16d25c0974be 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -9,6 +9,12 @@
 struct dma_map_ops;
 struct device_node;
 
+/*
+ * Arch extensions to struct device.
+ *
+ * When adding fields, consider macio_add_one_device in
+ * drivers/macintosh/macio_asic.c
+ */
 struct dev_archdata {
         /* DMA operations on that device */
         struct dma_map_ops      *dma_ops;
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 20778a405d7a..4ef662e4a31d 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -46,6 +46,7 @@
 #define FW_FEATURE_PS3_LV1      ASM_CONST(0x0000000000800000)
 #define FW_FEATURE_BEAT         ASM_CONST(0x0000000001000000)
 #define FW_FEATURE_CMO          ASM_CONST(0x0000000002000000)
+#define FW_FEATURE_VPHN         ASM_CONST(0x0000000004000000)
 
 #ifndef __ASSEMBLY__
 
@@ -59,7 +60,7 @@ enum {
                 FW_FEATURE_VIO | FW_FEATURE_RDMA | FW_FEATURE_LLAN |
                 FW_FEATURE_BULK_REMOVE | FW_FEATURE_XDABR |
                 FW_FEATURE_MULTITCE | FW_FEATURE_SPLPAR | FW_FEATURE_LPAR |
-                FW_FEATURE_CMO,
+                FW_FEATURE_CMO | FW_FEATURE_VPHN,
         FW_FEATURE_PSERIES_ALWAYS = 0,
         FW_FEATURE_ISERIES_POSSIBLE = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
         FW_FEATURE_ISERIES_ALWAYS = FW_FEATURE_ISERIES | FW_FEATURE_LPAR,
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index de03ca58db5d..ec089acfa56b 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -232,7 +232,9 @@
 #define H_GET_EM_PARMS          0x2B8
 #define H_SET_MPP               0x2D0
 #define H_GET_MPP               0x2D4
-#define MAX_HCALL_OPCODE        H_GET_MPP
+#define H_HOME_NODE_ASSOCIATIVITY 0x2EC
+#define H_BEST_ENERGY           0x2F4
+#define MAX_HCALL_OPCODE        H_BEST_ENERGY
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/include/asm/ioctls.h b/arch/powerpc/include/asm/ioctls.h
index 851920052e08..c7dc17cf84f1 100644
--- a/arch/powerpc/include/asm/ioctls.h
+++ b/arch/powerpc/include/asm/ioctls.h
@@ -94,6 +94,7 @@
 #define TIOCSRS485      0x542f
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+#define TIOCGDEV        _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
 #define TIOCSIG         _IOW('T',0x36, int)  /* Generate signal on Pty slave */
 
 #define TIOCSERCONFIG   0x5453
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index 7f5e0fefebb0..380d48bacd16 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -62,7 +62,10 @@ struct lppaca {
         volatile u32 dyn_pir;           // Dynamic ProcIdReg value      x20-x23
         u32     dsei_data;              // DSEI data                    x24-x27
         u64     sprg3;                  // SPRG3 value                  x28-x2F
-        u8      reserved3[80];          // Reserved                     x30-x7F
+        u8      reserved3[40];          // Reserved                     x30-x57
+        volatile u8 vphn_assoc_counts[8]; // Virtual processor home node
+                                        // associativity change counters x58-x5F
+        u8      reserved4[32];          // Reserved                     x60-x7F
 
 //=============================================================================
 // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index d045b0145537..8433d36619a1 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -27,9 +27,7 @@ struct iommu_table;
 struct rtc_time;
 struct file;
 struct pci_controller;
-#ifdef CONFIG_KEXEC
 struct kimage;
-#endif
 
 #ifdef CONFIG_SMP
 struct smp_ops_t {
@@ -72,7 +70,7 @@ struct machdep_calls {
                                              int psize, int ssize);
         void            (*flush_hash_range)(unsigned long number, int local);
 
-        /* special for kexec, to be called in real mode, linar mapping is
+        /* special for kexec, to be called in real mode, linear mapping is
          * destroyed as well */
         void            (*hpte_clear_all)(void);
 
@@ -324,8 +322,6 @@ extern sys_ctrler_t sys_ctrler;
 
 #endif /* CONFIG_PPC_PMAC */
 
-extern void setup_pci_ptrs(void);
-
 #ifdef CONFIG_SMP
 /* Poor default implementations */
 extern void __devinit smp_generic_give_timebase(void);
diff --git a/arch/powerpc/include/asm/mmzone.h b/arch/powerpc/include/asm/mmzone.h
index aac87cbceb57..fd3fd58bad84 100644
--- a/arch/powerpc/include/asm/mmzone.h
+++ b/arch/powerpc/include/asm/mmzone.h
@@ -33,6 +33,9 @@ extern int numa_cpu_lookup_table[];
 extern cpumask_var_t node_to_cpumask_map[];
 #ifdef CONFIG_MEMORY_HOTPLUG
 extern unsigned long max_pfn;
+u64 memory_hotplug_max(void);
+#else
+#define memory_hotplug_max() memblock_end_of_DRAM()
 #endif
 
 /*
@@ -42,6 +45,8 @@ extern unsigned long max_pfn;
 #define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
 #define node_end_pfn(nid)       (NODE_DATA(nid)->node_end_pfn)
 
+#else
+#define memory_hotplug_max() memblock_end_of_DRAM()
 #endif /* CONFIG_NEED_MULTIPLE_NODES */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index 850b72f27445..92efe67d1c57 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -10,31 +10,7 @@
 #ifndef _ASM_POWERPC_NVRAM_H
 #define _ASM_POWERPC_NVRAM_H
 
-#include <linux/errno.h>
-
-#define NVRW_CNT 0x20
-#define NVRAM_HEADER_LEN 16 /* sizeof(struct nvram_header) */
-#define NVRAM_BLOCK_LEN 16
-#define NVRAM_MAX_REQ (2080/NVRAM_BLOCK_LEN)
-#define NVRAM_MIN_REQ (1056/NVRAM_BLOCK_LEN)
-
-#define NVRAM_AS0  0x74
-#define NVRAM_AS1  0x75
-#define NVRAM_DATA 0x77
-
-
-/* RTC Offsets */
-
-#define MOTO_RTC_SECONDS        0x1FF9
-#define MOTO_RTC_MINUTES        0x1FFA
-#define MOTO_RTC_HOURS          0x1FFB
-#define MOTO_RTC_DAY_OF_WEEK    0x1FFC
-#define MOTO_RTC_DAY_OF_MONTH   0x1FFD
-#define MOTO_RTC_MONTH          0x1FFE
-#define MOTO_RTC_YEAR           0x1FFF
-#define MOTO_RTC_CONTROLA       0x1FF8
-#define MOTO_RTC_CONTROLB       0x1FF9
-
+/* Signatures for nvram partitions */
 #define NVRAM_SIG_SP    0x02    /* support processor */
 #define NVRAM_SIG_OF    0x50    /* open firmware config */
 #define NVRAM_SIG_FW    0x51    /* general firmware */
@@ -49,32 +25,19 @@
 #define NVRAM_SIG_OS    0xa0    /* OS defined */
 #define NVRAM_SIG_PANIC 0xa1    /* Apple OSX "panic" */
 
-/* If change this size, then change the size of NVNAME_LEN */
-struct nvram_header {
-        unsigned char signature;
-        unsigned char checksum;
-        unsigned short length;
-        char name[12];
-};
-
 #ifdef __KERNEL__
 
+#include <linux/errno.h>
 #include <linux/list.h>
 
-struct nvram_partition {
-        struct list_head partition;
-        struct nvram_header header;
-        unsigned int index;
-};
-
-
+#ifdef CONFIG_PPC_PSERIES
 extern int nvram_write_error_log(char * buff, int length,
                                          unsigned int err_type, unsigned int err_seq);
 extern int nvram_read_error_log(char * buff, int length,
                                          unsigned int * err_type, unsigned int *err_seq);
 extern int nvram_clear_error_log(void);
-
 extern int pSeries_nvram_init(void);
+#endif /* CONFIG_PPC_PSERIES */
 
 #ifdef CONFIG_MMIO_NVRAM
 extern int mmio_nvram_init(void);
@@ -85,6 +48,13 @@ static inline int mmio_nvram_init(void)
 }
 #endif
 
+extern int __init nvram_scan_partitions(void);
+extern loff_t nvram_create_partition(const char *name, int sig,
+                                     int req_size, int min_size);
+extern int nvram_remove_partition(const char *name, int sig);
+extern int nvram_get_partition_size(loff_t data_index);
+extern loff_t nvram_find_partition(const char *name, int sig, int *out_size);
+
 #endif /* __KERNEL__ */
 
 /* PowerMac specific nvram stuffs */
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 43adc8b819ed..1255569387b6 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -36,6 +36,8 @@
 #define PPC_INST_NOP                    0x60000000
 #define PPC_INST_POPCNTB                0x7c0000f4
 #define PPC_INST_POPCNTB_MASK           0xfc0007fe
+#define PPC_INST_POPCNTD                0x7c0003f4
+#define PPC_INST_POPCNTW                0x7c0002f4
 #define PPC_INST_RFCI                   0x4c000066
 #define PPC_INST_RFDI                   0x4c00004e
 #define PPC_INST_RFMCI                  0x4c00004c
@@ -88,6 +90,12 @@
                                         __PPC_RB(b) | __PPC_EH(eh))
 #define PPC_MSGSND(b)           stringify_in_c(.long PPC_INST_MSGSND | \
                                         __PPC_RB(b))
+#define PPC_POPCNTB(a, s)       stringify_in_c(.long PPC_INST_POPCNTB | \
+                                        __PPC_RA(a) | __PPC_RS(s))
+#define PPC_POPCNTD(a, s)       stringify_in_c(.long PPC_INST_POPCNTD | \
+                                        __PPC_RA(a) | __PPC_RS(s))
+#define PPC_POPCNTW(a, s)       stringify_in_c(.long PPC_INST_POPCNTW | \
+                                        __PPC_RA(a) | __PPC_RS(s))
 #define PPC_RFCI                stringify_in_c(.long PPC_INST_RFCI)
 #define PPC_RFDI                stringify_in_c(.long PPC_INST_RFDI)
 #define PPC_RFMCI               stringify_in_c(.long PPC_INST_RFMCI)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 4c14187ba02d..de1967a1ff57 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -122,7 +122,6 @@ extern struct task_struct *last_task_used_spe;
                 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
 #endif
 
-#ifdef __KERNEL__
 #ifdef __powerpc64__
 
 #define STACK_TOP_USER64 TASK_SIZE_USER64
@@ -139,7 +138,6 @@ extern struct task_struct *last_task_used_spe;
 #define STACK_TOP_MAX   STACK_TOP
 
 #endif /* __powerpc64__ */
-#endif /* __KERNEL__ */
 
 typedef struct {
         unsigned long seg;
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index ae26f2efd089..d72757585595 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -42,7 +42,7 @@ extern void pci_create_OF_bus_map(void);
 
 /* Translate a DMA address from device space to CPU space */
 extern u64 of_translate_dma_address(struct device_node *dev,
-                                    const u32 *in_addr);
+                                    const __be32 *in_addr);
 
 #ifdef CONFIG_PCI
 extern unsigned long pci_address_to_pio(phys_addr_t address);
@@ -63,9 +63,6 @@ struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
 /* cache lookup */
 struct device_node *of_find_next_cache_node(struct device_node *np);
 
-/* Get the MAC address */
-extern const void *of_get_mac_address(struct device_node *np);
-
 #ifdef CONFIG_NUMA
 extern int of_node_to_nid(struct device_node *device);
 #else
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index afe4aaa65c3b..7ef0d90defc8 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -106,9 +106,22 @@ static inline void sysfs_remove_device_from_node(struct sys_device *dev,
                                                 int nid)
 {
 }
-
 #endif /* CONFIG_NUMA */
 
+#if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR)
+extern int start_topology_update(void);
+extern int stop_topology_update(void);
+#else
+static inline int start_topology_update(void)
+{
+        return 0;
+}
+static inline int stop_topology_update(void)
+{
+        return 0;
+}
+#endif /* CONFIG_NUMA && CONFIG_PPC_SPLPAR */
+
 #include <asm-generic/topology.h>
 
 #ifdef CONFIG_SMP
diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h
index 08679c5319b8..25e39220e89c 100644
--- a/arch/powerpc/include/asm/vdso_datapage.h
+++ b/arch/powerpc/include/asm/vdso_datapage.h
@@ -116,9 +116,7 @@ struct vdso_data {
 
 #endif /* CONFIG_PPC64 */
 
-#ifdef __KERNEL__
 extern struct vdso_data *vdso_data;
-#endif
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 36c30f31ec93..3bb2a3e6a337 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -29,8 +29,10 @@ endif
 obj-y                           := cputable.o ptrace.o syscalls.o \
                                    irq.o align.o signal_32.o pmc.o vdso.o \
                                    init_task.o process.o systbl.o idle.o \
-                                   signal.o sysfs.o cacheinfo.o
-obj-y                           += vdso32/
+                                   signal.o sysfs.o cacheinfo.o time.o \
+                                   prom.o traps.o setup-common.o \
+                                   udbg.o misc.o io.o dma.o \
+                                   misc_$(CONFIG_WORD_SIZE).o vdso32/
 obj-$(CONFIG_PPC64)             += setup_64.o sys_ppc32.o \
                                    signal_64.o ptrace32.o \
                                    paca.o nvram_64.o firmware.o
@@ -80,9 +82,6 @@ extra-$(CONFIG_FSL_BOOKE)	:= head_fsl_booke.o
 extra-$(CONFIG_8xx)             := head_8xx.o
 extra-y                         += vmlinux.lds
 
-obj-y                           += time.o prom.o traps.o setup-common.o \
-                                   udbg.o misc.o io.o dma.o \
-                                   misc_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_PPC32)             += entry_32.o setup_32.o
 obj-$(CONFIG_PPC64)             += dma-iommu.o iommu.o
 obj-$(CONFIG_KGDB)              += kgdb.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index bd0df2e6aa8f..23e6a93145ab 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -209,7 +209,6 @@ int main(void)
         DEFINE(RTASENTRY, offsetof(struct rtas_t, entry));
 
         /* Interrupt register frame */
-        DEFINE(STACK_FRAME_OVERHEAD, STACK_FRAME_OVERHEAD);
         DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
         DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
 #ifdef CONFIG_PPC64
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 96a908f1cd87..be5ab18b03b5 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -457,16 +457,26 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .dcache_bsize           = 128,
                 .num_pmcs               = 6,
                 .pmc_type               = PPC_PMC_IBM,
-                .cpu_setup              = __setup_cpu_power7,
-                .cpu_restore            = __restore_cpu_power7,
                 .oprofile_cpu_type      = "ppc64/power7",
                 .oprofile_type          = PPC_OPROFILE_POWER4,
-                .oprofile_mmcra_sihv    = POWER6_MMCRA_SIHV,
-                .oprofile_mmcra_sipr    = POWER6_MMCRA_SIPR,
-                .oprofile_mmcra_clear   = POWER6_MMCRA_THRM |
-                        POWER6_MMCRA_OTHER,
                 .platform               = "power7",
         },
+        {       /* Power7+ */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x004A0000,
+                .cpu_name               = "POWER7+ (raw)",
+                .cpu_features           = CPU_FTRS_POWER7,
+                .cpu_user_features      = COMMON_USER_POWER7,
+                .mmu_features           = MMU_FTR_HPTE_TABLE |
+                        MMU_FTR_TLBIE_206,
+                .icache_bsize           = 128,
+                .dcache_bsize           = 128,
+                .num_pmcs               = 6,
+                .pmc_type               = PPC_PMC_IBM,
+                .oprofile_cpu_type      = "ppc64/power7",
+                .oprofile_type          = PPC_OPROFILE_POWER4,
+                .platform               = "power7+",
+        },
         {       /* Cell Broadband Engine */
                 .pvr_mask               = 0xffff0000,
                 .pvr_value              = 0x00700000,
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c
index 8e05c16344e4..0a2af50243cb 100644
--- a/arch/powerpc/kernel/crash_dump.c
+++ b/arch/powerpc/kernel/crash_dump.c
@@ -19,6 +19,7 @@
 #include <asm/prom.h>
 #include <asm/firmware.h>
 #include <asm/uaccess.h>
+#include <asm/rtas.h>
 
 #ifdef DEBUG
 #include <asm/udbg.h>
@@ -141,3 +142,35 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
 
         return csize;
 }
+
+#ifdef CONFIG_PPC_RTAS
+/*
+ * The crashkernel region will almost always overlap the RTAS region, so
+ * we have to be careful when shrinking the crashkernel region.
+ */
+void crash_free_reserved_phys_range(unsigned long begin, unsigned long end)
+{
+        unsigned long addr;
+        const u32 *basep, *sizep;
+        unsigned int rtas_start = 0, rtas_end = 0;
+
+        basep = of_get_property(rtas.dev, "linux,rtas-base", NULL);
+        sizep = of_get_property(rtas.dev, "rtas-size", NULL);
+
+        if (basep && sizep) {
+                rtas_start = *basep;
+                rtas_end = *basep + *sizep;
+        }
+
+        for (addr = begin; addr < end; addr += PAGE_SIZE) {
+                /* Does this page overlap with the RTAS region? */
+                if (addr <= rtas_end && ((addr + PAGE_SIZE) > rtas_start))
+                        continue;
+
+                ClearPageReserved(pfn_to_page(addr >> PAGE_SHIFT));
+                init_page_count(pfn_to_page(addr >> PAGE_SHIFT));
+                free_page((unsigned long)__va(addr));
+                totalram_pages++;
+        }
+}
+#endif
diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index 6e54a0fd31aa..e7554154a6de 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -19,7 +19,7 @@ static void *dma_iommu_alloc_coherent(struct device *dev, size_t size,
                                       dma_addr_t *dma_handle, gfp_t flag)
 {
         return iommu_alloc_coherent(dev, get_iommu_table_base(dev), size,
-                                    dma_handle, device_to_mask(dev), flag,
+                                    dma_handle, dev->coherent_dma_mask, flag,
                                     dev_to_node(dev));
 }
 
diff --git a/arch/powerpc/kernel/e500-pmu.c b/arch/powerpc/kernel/e500-pmu.c
index 7c07de0d8943..b150b510510f 100644
--- a/arch/powerpc/kernel/e500-pmu.c
+++ b/arch/powerpc/kernel/e500-pmu.c
@@ -126,4 +126,4 @@ static int init_e500_pmu(void)
         return register_fsl_emb_pmu(&e500_pmu);
 }
 
-arch_initcall(init_e500_pmu);
+early_initcall(init_e500_pmu);
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index ed4aeb96398b..c22dc1ec1c94 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -31,6 +31,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/unistd.h>
 #include <asm/ftrace.h>
+#include <asm/ptrace.h>
 
 #undef SHOW_SYSCALLS
 #undef SHOW_SYSCALLS_TASK
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 9f8b01d6466f..8a817995b4cd 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -13,6 +13,7 @@
  */
 
 #include <asm/exception-64s.h>
+#include <asm/ptrace.h>
 
 /*
  * We layout physical memory as follows:
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index e86c040ae585..de369558bf0a 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -23,6 +23,7 @@
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/ptrace.h>
 
 #ifdef CONFIG_VSX
 #define REST_32FPVSRS(n,c,base)                                         \
diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index 8278e8bad5a0..9dd21a8c4d52 100644
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -40,6 +40,7 @@
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/ptrace.h>
 
 /* As with the other PowerPC ports, it is expected that when code
  * execution begins here, the following registers contain valid, yet
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 562305b40a8e..cbb3436b592d 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -37,6 +37,7 @@
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/ptrace.h>
 #include <asm/synch.h>
 #include "head_booke.h"
 
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index f0dd577e4a5b..782f23df7c85 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -38,6 +38,7 @@
 #include <asm/page_64.h>
 #include <asm/irqflags.h>
 #include <asm/kvm_book3s_asm.h>
+#include <asm/ptrace.h>
 
 /* The physical memory is layed out such that the secondary processor
  * spin code sits at 0x0000...0x00ff. On server, the vectors follow
@@ -96,7 +97,7 @@ __secondary_hold_acknowledge:
         .llong hvReleaseData-KERNELBASE
 #endif /* CONFIG_PPC_ISERIES */
 
-#ifdef CONFIG_CRASH_DUMP
+#ifdef CONFIG_RELOCATABLE
         /* This flag is set to 1 by a loader if the kernel should run
          * at the loaded address instead of the linked address.  This
          * is used by kexec-tools to keep the the kdump kernel in the
@@ -384,12 +385,10 @@ _STATIC(__after_prom_start)
         /* process relocations for the final address of the kernel */
         lis     r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
         sldi    r25,r25,32
-#ifdef CONFIG_CRASH_DUMP
         lwz     r7,__run_at_load-_stext(r26)
-        cmplwi  cr0,r7,1        /* kdump kernel ? - stay where we are */
+        cmplwi  cr0,r7,1        /* flagged to stay where we are ? */
         bne     1f
         add     r25,r25,r26
-#endif
 1:      mr      r3,r25
         bl      .relocate
 #endif
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1f1a04b5c2a4..1cbf64e6b416 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -29,6 +29,7 @@
 #include <asm/thread_info.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/ptrace.h>
 
 /* Macro to make the code more readable. */
 #ifdef CONFIG_8xx_CPU6
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 529b817f473b..3e02710d9562 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -41,6 +41,7 @@
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
 #include <asm/cache.h>
+#include <asm/ptrace.h>
 #include "head_booke.h"
 
 /* As with the other PowerPC ports, it is expected that when code
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index d5839179ec77..961bb03413f3 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -311,8 +311,9 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
                 /* Handle failure */
                 if (unlikely(entry == DMA_ERROR_CODE)) {
                         if (printk_ratelimit())
-                                printk(KERN_INFO "iommu_alloc failed, tbl %p vaddr %lx"
-                                       " npages %lx\n", tbl, vaddr, npages);
+                                dev_info(dev, "iommu_alloc failed, tbl %p "
+                                         "vaddr %lx npages %lu\n", tbl, vaddr,
+                                         npages);
                         goto failure;
                 }
 
@@ -579,9 +580,9 @@ dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
                                          attrs);
                 if (dma_handle == DMA_ERROR_CODE) {
                         if (printk_ratelimit())  {
-                                printk(KERN_INFO "iommu_alloc failed, "
-                                                "tbl %p vaddr %p npages %d\n",
-                                                tbl, vaddr, npages);
+                                dev_info(dev, "iommu_alloc failed, tbl %p "
+                                         "vaddr %p npages %d\n", tbl, vaddr,
+                                         npages);
                         }
                 } else
                         dma_handle |= (uaddr & ~IOMMU_PAGE_MASK);
@@ -627,7 +628,8 @@ void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
          * the tce tables.
          */
         if (order >= IOMAP_MAX_ORDER) {
-                printk("iommu_alloc_consistent size too large: 0x%lx\n", size);
+                dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
+                         size);
                 return NULL;
         }
 
diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S
index 2d29752cbe16..b69463ec2010 100644
--- a/arch/powerpc/kernel/misc.S
+++ b/arch/powerpc/kernel/misc.S
@@ -122,8 +122,3 @@ _GLOBAL(longjmp)
         mtlr    r0
         mr      r3,r4
         blr
-
-_GLOBAL(__setup_cpu_power7)
-_GLOBAL(__restore_cpu_power7)
-        /* place holder */
-        blr
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index a7a570dcdd57..094bd9821ad4 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -30,6 +30,7 @@
 #include <asm/processor.h>
 #include <asm/kexec.h>
 #include <asm/bug.h>
+#include <asm/ptrace.h>
 
         .text
 
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index e5144906a56d..206a321a71d3 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -25,6 +25,7 @@
 #include <asm/cputable.h>
 #include <asm/thread_info.h>
 #include <asm/kexec.h>
+#include <asm/ptrace.h>
 
         .text
 
diff --git a/arch/powerpc/kernel/mpc7450-pmu.c b/arch/powerpc/kernel/mpc7450-pmu.c
index 09d72028f317..2cc5e0301d0b 100644
--- a/arch/powerpc/kernel/mpc7450-pmu.c
+++ b/arch/powerpc/kernel/mpc7450-pmu.c
@@ -414,4 +414,4 @@ static int init_mpc7450_pmu(void)
         return register_power_pmu(&mpc7450_pmu);
 }
 
-arch_initcall(init_mpc7450_pmu);
+early_initcall(init_mpc7450_pmu);
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index 9cf197f01e94..bb12b3248f13 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -34,15 +34,26 @@
 
 #undef DEBUG_NVRAM
 
-static struct nvram_partition * nvram_part;
-static long nvram_error_log_index = -1;
-static long nvram_error_log_size = 0;
+#define NVRAM_HEADER_LEN        sizeof(struct nvram_header)
+#define NVRAM_BLOCK_LEN         NVRAM_HEADER_LEN
+
+/* If change this size, then change the size of NVNAME_LEN */
+struct nvram_header {
+        unsigned char signature;
+        unsigned char checksum;
+        unsigned short length;
+        /* Terminating null required only for names < 12 chars. */
+        char name[12];
+};
 
-struct err_log_info {
-        int error_type;
-        unsigned int seq_num;
+struct nvram_partition {
+        struct list_head partition;
+        struct nvram_header header;
+        unsigned int index;
 };
 
+static LIST_HEAD(nvram_partitions);
+
 static loff_t dev_nvram_llseek(struct file *file, loff_t offset, int origin)
 {
         int size;
@@ -186,14 +197,12 @@ static struct miscdevice nvram_dev = {
 #ifdef DEBUG_NVRAM
 static void __init nvram_print_partitions(char * label)
 {
-        struct list_head * p;
         struct nvram_partition * tmp_part;
         
         printk(KERN_WARNING "--------%s---------\n", label);
         printk(KERN_WARNING "indx\t\tsig\tchks\tlen\tname\n");
-        list_for_each(p, &nvram_part->partition) {
-                tmp_part = list_entry(p, struct nvram_partition, partition);
-                printk(KERN_WARNING "%4d    \t%02x\t%02x\t%d\t%s\n",
+        list_for_each_entry(tmp_part, &nvram_partitions, partition) {
+                printk(KERN_WARNING "%4d    \t%02x\t%02x\t%d\t%12s\n",
                        tmp_part->index, tmp_part->header.signature,
                        tmp_part->header.checksum, tmp_part->header.length,
                        tmp_part->header.name);
@@ -228,95 +237,113 @@ static unsigned char __init nvram_checksum(struct nvram_header *p)
         return c_sum;
 }
 
-static int __init nvram_remove_os_partition(void)
+/**
+ * nvram_remove_partition - Remove one or more partitions in nvram
+ * @name: name of the partition to remove, or NULL for a
+ *        signature only match
+ * @sig: signature of the partition(s) to remove
+ */
+
+int __init nvram_remove_partition(const char *name, int sig)
 {
-        struct list_head *i;
-        struct list_head *j;
-        struct nvram_partition * part;
-        struct nvram_partition * cur_part;
+        struct nvram_partition *part, *prev, *tmp;
         int rc;
 
-        list_for_each(i, &nvram_part->partition) {
-                part = list_entry(i, struct nvram_partition, partition);
-                if (part->header.signature != NVRAM_SIG_OS)
+        list_for_each_entry(part, &nvram_partitions, partition) {
+                if (part->header.signature != sig)
                         continue;
-                
-                /* Make os partition a free partition */
+                if (name && strncmp(name, part->header.name, 12))
+                        continue;
+
+                /* Make partition a free partition */
                 part->header.signature = NVRAM_SIG_FREE;
-                sprintf(part->header.name, "wwwwwwwwwwww");
+                strncpy(part->header.name, "wwwwwwwwwwww", 12);
                 part->header.checksum = nvram_checksum(&part->header);
-
-                /* Merge contiguous free partitions backwards */
-                list_for_each_prev(j, &part->partition) {
-                        cur_part = list_entry(j, struct nvram_partition, partition);
-                        if (cur_part == nvram_part || cur_part->header.signature != NVRAM_SIG_FREE) {
-                                break;
-                        }
-                        
-                        part->header.length += cur_part->header.length;
-                        part->header.checksum = nvram_checksum(&part->header);
-                        part->index = cur_part->index;
-
-                        list_del(&cur_part->partition);
-                        kfree(cur_part);
-                        j = &part->partition; /* fixup our loop */
-                }
-                
-                /* Merge contiguous free partitions forwards */
-                list_for_each(j, &part->partition) {
-                        cur_part = list_entry(j, struct nvram_partition, partition);
-                        if (cur_part == nvram_part || cur_part->header.signature != NVRAM_SIG_FREE) {
-                                break;
-                        }
-
-                        part->header.length += cur_part->header.length;
-                        part->header.checksum = nvram_checksum(&part->header);
-
-                        list_del(&cur_part->partition);
-                        kfree(cur_part);
-                        j = &part->partition; /* fixup our loop */
-                }
-                
                 rc = nvram_write_header(part);
                 if (rc <= 0) {
-                        printk(KERN_ERR "nvram_remove_os_partition: nvram_write failed (%d)\n", rc);
+                        printk(KERN_ERR "nvram_remove_partition: nvram_write failed (%d)\n", rc);
                         return rc;
                 }
+        }
 
+        /* Merge contiguous ones */
+        prev = NULL;
+        list_for_each_entry_safe(part, tmp, &nvram_partitions, partition) {
+                if (part->header.signature != NVRAM_SIG_FREE) {
+                        prev = NULL;
+                        continue;
+                }
+                if (prev) {
+                        prev->header.length += part->header.length;
+                        prev->header.checksum = nvram_checksum(&part->header);
+                        rc = nvram_write_header(part);
+                        if (rc <= 0) {
+                                printk(KERN_ERR "nvram_remove_partition: nvram_write failed (%d)\n", rc);
+                                return rc;
+                        }
+                        list_del(&part->partition);
+                        kfree(part);
+                } else
+                        prev = part;
         }
         
         return 0;
 }
 
-/* nvram_create_os_partition
+/**
+ * nvram_create_partition - Create a partition in nvram
+ * @name: name of the partition to create
+ * @sig: signature of the partition to create
+ * @req_size: size of data to allocate in bytes
+ * @min_size: minimum acceptable size (0 means req_size)
  *
- * Create a OS linux partition to buffer error logs.
- * Will create a partition starting at the first free
- * space found if space has enough room.
+ * Returns a negative error code or a positive nvram index
+ * of the beginning of the data area of the newly created
+ * partition. If you provided a min_size smaller than req_size
+ * you need to query for the actual size yourself after the
+ * call using nvram_partition_get_size().
  */
-static int __init nvram_create_os_partition(void)
+loff_t __init nvram_create_partition(const char *name, int sig,
+                                     int req_size, int min_size)
 {
         struct nvram_partition *part;
         struct nvram_partition *new_part;
         struct nvram_partition *free_part = NULL;
-        int seq_init[2] = { 0, 0 };
+        static char nv_init_vals[16];
         loff_t tmp_index;
         long size = 0;
         int rc;
-        
+
+        /* Convert sizes from bytes to blocks */
+        req_size = _ALIGN_UP(req_size, NVRAM_BLOCK_LEN) / NVRAM_BLOCK_LEN;
+        min_size = _ALIGN_UP(min_size, NVRAM_BLOCK_LEN) / NVRAM_BLOCK_LEN;
+
+        /* If no minimum size specified, make it the same as the
+         * requested size
+         */
+        if (min_size == 0)
+                min_size = req_size;
+        if (min_size > req_size)
+                return -EINVAL;
+
+        /* Now add one block to each for the header */
+        req_size += 1;
+        min_size += 1;
+
         /* Find a free partition that will give us the maximum needed size 
            If can't find one that will give us the minimum size needed */
-        list_for_each_entry(part, &nvram_part->partition, partition) {
+        list_for_each_entry(part, &nvram_partitions, partition) {
                 if (part->header.signature != NVRAM_SIG_FREE)
                         continue;
 
-                if (part->header.length >= NVRAM_MAX_REQ) {
-                        size = NVRAM_MAX_REQ;
+                if (part->header.length >= req_size) {
+                        size = req_size;
                         free_part = part;
                         break;
                 }
-                if (!size && part->header.length >= NVRAM_MIN_REQ) {
-                        size = NVRAM_MIN_REQ;
+                if (part->header.length > size &&
+                    part->header.length >= min_size) {
+                        size = part->header.length;
                         free_part = part;
                 }
         }
@@ -326,136 +353,95 @@ static int __init nvram_create_os_partition(void)
         /* Create our OS partition */
         new_part = kmalloc(sizeof(*new_part), GFP_KERNEL);
         if (!new_part) {
-                printk(KERN_ERR "nvram_create_os_partition: kmalloc failed\n");
+                pr_err("nvram_create_os_partition: kmalloc failed\n");
                 return -ENOMEM;
         }
 
         new_part->index = free_part->index;
-        new_part->header.signature = NVRAM_SIG_OS;
+        new_part->header.signature = sig;
         new_part->header.length = size;
-        strcpy(new_part->header.name, "ppc64,linux");
+        strncpy(new_part->header.name, name, 12);
         new_part->header.checksum = nvram_checksum(&new_part->header);
 
         rc = nvram_write_header(new_part);
         if (rc <= 0) {
-                printk(KERN_ERR "nvram_create_os_partition: nvram_write_header "
-                                "failed (%d)\n", rc);
-                return rc;
-        }
-
-        /* make sure and initialize to zero the sequence number and the error
-           type logged */
-        tmp_index = new_part->index + NVRAM_HEADER_LEN;
-        rc = ppc_md.nvram_write((char *)&seq_init, sizeof(seq_init), &tmp_index);
-        if (rc <= 0) {
-                printk(KERN_ERR "nvram_create_os_partition: nvram_write "
+                pr_err("nvram_create_os_partition: nvram_write_header "
                        "failed (%d)\n", rc);
                 return rc;
         }
-        
-        nvram_error_log_index = new_part->index + NVRAM_HEADER_LEN;
-        nvram_error_log_size = ((part->header.length - 1) *
-                                NVRAM_BLOCK_LEN) - sizeof(struct err_log_info);
-        
         list_add_tail(&new_part->partition, &free_part->partition);
 
-        if (free_part->header.length <= size) {
+        /* Adjust or remove the partition we stole the space from */
+        if (free_part->header.length > size) {
+                free_part->index += size * NVRAM_BLOCK_LEN;
+                free_part->header.length -= size;
+                free_part->header.checksum = nvram_checksum(&free_part->header);
+                rc = nvram_write_header(free_part);
+                if (rc <= 0) {
+                        pr_err("nvram_create_os_partition: nvram_write_header "
+                               "failed (%d)\n", rc);
+                        return rc;
+                }
+        } else {
                 list_del(&free_part->partition);
                 kfree(free_part);
-                return 0;
         } 
 
-        /* Adjust the partition we stole the space from */
-        free_part->index += size * NVRAM_BLOCK_LEN;
-        free_part->header.length -= size;
-        free_part->header.checksum = nvram_checksum(&free_part->header);
-        
-        rc = nvram_write_header(free_part);
-        if (rc <= 0) {
-                printk(KERN_ERR "nvram_create_os_partition: nvram_write_header "
-                       "failed (%d)\n", rc);
-                return rc;
+        /* Clear the new partition */
+        for (tmp_index = new_part->index + NVRAM_HEADER_LEN;
+             tmp_index <  ((size - 1) * NVRAM_BLOCK_LEN);
+             tmp_index += NVRAM_BLOCK_LEN) {
+                rc = ppc_md.nvram_write(nv_init_vals, NVRAM_BLOCK_LEN, &tmp_index);
+                if (rc <= 0) {
+                        pr_err("nvram_create_partition: nvram_write failed (%d)\n", rc);
+                        return rc;
+                }
         }
-
-        return 0;
+        
+        return new_part->index + NVRAM_HEADER_LEN;
 }
 
-
-/* nvram_setup_partition
- *
- * This will setup the partition we need for buffering the
- * error logs and cleanup partitions if needed.
- *
- * The general strategy is the following:
- * 1.) If there is ppc64,linux partition large enough then use it.
- * 2.) If there is not a ppc64,linux partition large enough, search
- * for a free partition that is large enough.
- * 3.) If there is not a free partition large enough remove 
- * _all_ OS partitions and consolidate the space.
- * 4.) Will first try getting a chunk that will satisfy the maximum
- * error log size (NVRAM_MAX_REQ).
- * 5.) If the max chunk cannot be allocated then try finding a chunk
- * that will satisfy the minum needed (NVRAM_MIN_REQ).
+/**
+ * nvram_get_partition_size - Get the data size of an nvram partition
+ * @data_index: This is the offset of the start of the data of
+ *              the partition. The same value that is returned by
+ *              nvram_create_partition().
  */
-static int __init nvram_setup_partition(void)
+int nvram_get_partition_size(loff_t data_index)
 {
-        struct list_head * p;
-        struct nvram_partition * part;
-        int rc;
-
-        /* For now, we don't do any of this on pmac, until I
-         * have figured out if it's worth killing some unused stuffs
-         * in our nvram, as Apple defined partitions use pretty much
-         * all of the space
-         */
-        if (machine_is(powermac))
-                return -ENOSPC;
-
-        /* see if we have an OS partition that meets our needs.
-           will try getting the max we need.  If not we'll delete
-           partitions and try again. */
-        list_for_each(p, &nvram_part->partition) {
-                part = list_entry(p, struct nvram_partition, partition);
-                if (part->header.signature != NVRAM_SIG_OS)
-                        continue;
+        struct nvram_partition *part;
+        
+        list_for_each_entry(part, &nvram_partitions, partition) {
+                if (part->index + NVRAM_HEADER_LEN == data_index)
+                        return (part->header.length - 1) * NVRAM_BLOCK_LEN;
+        }
+        return -1;
+}
 
-                if (strcmp(part->header.name, "ppc64,linux"))
-                        continue;
 
-                if (part->header.length >= NVRAM_MIN_REQ) {
-                        /* found our partition */
-                        nvram_error_log_index = part->index + NVRAM_HEADER_LEN;
-                        nvram_error_log_size = ((part->header.length - 1) *
-                                                NVRAM_BLOCK_LEN) - sizeof(struct err_log_info);
-                        return 0;
+/**
+ * nvram_find_partition - Find an nvram partition by signature and name
+ * @name: Name of the partition or NULL for any name
+ * @sig: Signature to test against
+ * @out_size: if non-NULL, returns the size of the data part of the partition
+ */
+loff_t nvram_find_partition(const char *name, int sig, int *out_size)
+{
+        struct nvram_partition *p;
+
+        list_for_each_entry(p, &nvram_partitions, partition) {
+                if (p->header.signature == sig &&
+                    (!name || !strncmp(p->header.name, name, 12))) {
+                        if (out_size)
+                                *out_size = (p->header.length - 1) *
+                                        NVRAM_BLOCK_LEN;
+                        return p->index + NVRAM_HEADER_LEN;
                 }
         }
-        
-        /* try creating a partition with the free space we have */
-        rc = nvram_create_os_partition();
-        if (!rc) {
-                return 0;
-        }
-                
-        /* need to free up some space */
-        rc = nvram_remove_os_partition();
-        if (rc) {
-                return rc;
-        }
-        
-        /* create a partition in this new space */
-        rc = nvram_create_os_partition();
-        if (rc) {
-                printk(KERN_ERR "nvram_create_os_partition: Could not find a "
-                       "NVRAM partition large enough\n");
-                return rc;
-        }
-        
         return 0;
 }
 
-
-static int __init nvram_scan_partitions(void)
+int __init nvram_scan_partitions(void)
 {
         loff_t cur_index = 0;
         struct nvram_header phead;
@@ -465,7 +451,7 @@ static int __init nvram_scan_partitions(void)
         int total_size;
         int err;
 
-        if (ppc_md.nvram_size == NULL)
+        if (ppc_md.nvram_size == NULL || ppc_md.nvram_size() <= 0)
                 return -ENODEV;
         total_size = ppc_md.nvram_size();
         
@@ -512,12 +498,16 @@ static int __init nvram_scan_partitions(void)
                 
                 memcpy(&tmp_part->header, &phead, NVRAM_HEADER_LEN);
                 tmp_part->index = cur_index;
-                list_add_tail(&tmp_part->partition, &nvram_part->partition);
+                list_add_tail(&tmp_part->partition, &nvram_partitions);
                 
                 cur_index += phead.length * NVRAM_BLOCK_LEN;
         }
         err = 0;
 
+#ifdef DEBUG_NVRAM
+        nvram_print_partitions("NVRAM Partitions");
+#endif
+
  out:
         kfree(header);
         return err;
@@ -525,9 +515,10 @@ static int __init nvram_scan_partitions(void)
 
 static int __init nvram_init(void)
 {
-        int error;
         int rc;
         
+        BUILD_BUG_ON(NVRAM_BLOCK_LEN != 16);
+
         if (ppc_md.nvram_size == NULL || ppc_md.nvram_size() <= 0)
                 return  -ENODEV;
 
@@ -537,29 +528,6 @@ static int __init nvram_init(void)
                 return rc;
         }
         
-        /* initialize our anchor for the nvram partition list */
-        nvram_part = kmalloc(sizeof(struct nvram_partition), GFP_KERNEL);
-        if (!nvram_part) {
-                printk(KERN_ERR "nvram_init: Failed kmalloc\n");
-                return -ENOMEM;
-        }
-        INIT_LIST_HEAD(&nvram_part->partition);
-  
-        /* Get all the NVRAM partitions */
-        error = nvram_scan_partitions();
-        if (error) {
-                printk(KERN_ERR "nvram_init: Failed nvram_scan_partitions\n");
-                return error;
-        }
-                
-        if(nvram_setup_partition()) 
-                printk(KERN_WARNING "nvram_init: Could not find nvram partition"
-                       " for nvram buffered error logging.\n");
-  
-#ifdef DEBUG_NVRAM
-        nvram_print_partitions("NVRAM Partitions");
-#endif
-
         return rc;
 }
 
@@ -568,135 +536,6 @@ void __exit nvram_cleanup(void)
         misc_deregister( &nvram_dev );
 }
 
-
-#ifdef CONFIG_PPC_PSERIES
-
-/* nvram_write_error_log
- *
- * We need to buffer the error logs into nvram to ensure that we have
- * the failure information to decode.  If we have a severe error there
- * is no way to guarantee that the OS or the machine is in a state to
- * get back to user land and write the error to disk.  For example if
- * the SCSI device driver causes a Machine Check by writing to a bad
- * IO address, there is no way of guaranteeing that the device driver
- * is in any state that is would also be able to write the error data
- * captured to disk, thus we buffer it in NVRAM for analysis on the
- * next boot.
- *
- * In NVRAM the partition containing the error log buffer will looks like:
- * Header (in bytes):
- * +-----------+----------+--------+------------+------------------+
- * | signature | checksum | length | name       | data             |
- * |0          |1         |2      3|4         15|16        length-1|
- * +-----------+----------+--------+------------+------------------+
- *
- * The 'data' section would look like (in bytes):
- * +--------------+------------+-----------------------------------+
- * | event_logged | sequence # | error log                         |
- * |0            3|4          7|8            nvram_error_log_size-1|
- * +--------------+------------+-----------------------------------+
- *
- * event_logged: 0 if event has not been logged to syslog, 1 if it has
- * sequence #: The unique sequence # for each event. (until it wraps)
- * error log: The error log from event_scan
- */
-int nvram_write_error_log(char * buff, int length,
-                          unsigned int err_type, unsigned int error_log_cnt)
-{
-        int rc;
-        loff_t tmp_index;
-        struct err_log_info info;
-        
-        if (nvram_error_log_index == -1) {
-                return -ESPIPE;
-        }
-
-        if (length > nvram_error_log_size) {
-                length = nvram_error_log_size;
-        }
-
-        info.error_type = err_type;
-        info.seq_num = error_log_cnt;
-
-        tmp_index = nvram_error_log_index;
-
-        rc = ppc_md.nvram_write((char *)&info, sizeof(struct err_log_info), &tmp_index);
-        if (rc <= 0) {
-                printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc);
-                return rc;
-        }
-
-        rc = ppc_md.nvram_write(buff, length, &tmp_index);
-        if (rc <= 0) {
-                printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc);
-                return rc;
-        }
-        
-        return 0;
-}
-
-/* nvram_read_error_log
- *
- * Reads nvram for error log for at most 'length'
- */
-int nvram_read_error_log(char * buff, int length,
-                         unsigned int * err_type, unsigned int * error_log_cnt)
-{
-        int rc;
-        loff_t tmp_index;
-        struct err_log_info info;
-        
-        if (nvram_error_log_index == -1)
-                return -1;
-
-        if (length > nvram_error_log_size)
-                length = nvram_error_log_size;
-
-        tmp_index = nvram_error_log_index;
-
-        rc = ppc_md.nvram_read((char *)&info, sizeof(struct err_log_info), &tmp_index);
-        if (rc <= 0) {
-                printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc);
-                return rc;
-        }
-
-        rc = ppc_md.nvram_read(buff, length, &tmp_index);
-        if (rc <= 0) {
-                printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc);
-                return rc;
-        }
-
-        *error_log_cnt = info.seq_num;
-        *err_type = info.error_type;
-
-        return 0;
-}
-
-/* This doesn't actually zero anything, but it sets the event_logged
- * word to tell that this event is safely in syslog.
- */
-int nvram_clear_error_log(void)
-{
-        loff_t tmp_index;
-        int clear_word = ERR_FLAG_ALREADY_LOGGED;
-        int rc;
-
-        if (nvram_error_log_index == -1)
-                return -1;
-
-        tmp_index = nvram_error_log_index;
-        
-        rc = ppc_md.nvram_write((char *)&clear_word, sizeof(int), &tmp_index);
-        if (rc <= 0) {
-                printk(KERN_ERR "nvram_clear_error_log: Failed nvram_write (%d)\n", rc);
-                return rc;
-        }
-
-        return 0;
-}
-
-#endif /* CONFIG_PPC_PSERIES */
-
 module_init(nvram_init);
 module_exit(nvram_cleanup);
 MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index d43fc65749c1..851577608a78 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -193,8 +193,7 @@ int __devinit pcibios_map_io_space(struct pci_bus *bus)
         hose->io_resource.start += io_virt_offset;
         hose->io_resource.end += io_virt_offset;
 
-        pr_debug("  hose->io_resource=0x%016llx...0x%016llx\n",
-                 hose->io_resource.start, hose->io_resource.end);
+        pr_debug("  hose->io_resource=%pR\n", &hose->io_resource);
 
         return 0;
 }
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index 3129c855933c..567480705789 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -1379,7 +1379,7 @@ int register_power_pmu(struct power_pmu *pmu)
                 freeze_events_kernel = MMCR0_FCHV;
 #endif /* CONFIG_PPC64 */
 
-        perf_pmu_register(&power_pmu);
+        perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
         perf_cpu_notifier(power_pmu_notifier);
 
         return 0;
diff --git a/arch/powerpc/kernel/perf_event_fsl_emb.c b/arch/powerpc/kernel/perf_event_fsl_emb.c
index 7ecca59ddf77..4dcf5f831e9d 100644
--- a/arch/powerpc/kernel/perf_event_fsl_emb.c
+++ b/arch/powerpc/kernel/perf_event_fsl_emb.c
@@ -681,7 +681,7 @@ int register_fsl_emb_pmu(struct fsl_emb_pmu *pmu)
         pr_info("%s performance monitor hardware support registered\n",
                 pmu->name);
 
-        perf_pmu_register(&fsl_emb_pmu);
+        perf_pmu_register(&fsl_emb_pmu, "cpu", PERF_TYPE_RAW);
 
         return 0;
 }
diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c
index 2a361cdda635..ead8b3c2649e 100644
--- a/arch/powerpc/kernel/power4-pmu.c
+++ b/arch/powerpc/kernel/power4-pmu.c
@@ -613,4 +613,4 @@ static int init_power4_pmu(void)
         return register_power_pmu(&power4_pmu);
 }
 
-arch_initcall(init_power4_pmu);
+early_initcall(init_power4_pmu);
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
index 199de527d411..eca0ac595cb6 100644
--- a/arch/powerpc/kernel/power5+-pmu.c
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -682,4 +682,4 @@ static int init_power5p_pmu(void)
         return register_power_pmu(&power5p_pmu);
 }
 
-arch_initcall(init_power5p_pmu);
+early_initcall(init_power5p_pmu);
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c
index 98b6a729a9dd..d5ff0f64a5e6 100644
--- a/arch/powerpc/kernel/power5-pmu.c
+++ b/arch/powerpc/kernel/power5-pmu.c
@@ -621,4 +621,4 @@ static int init_power5_pmu(void)
         return register_power_pmu(&power5_pmu);
 }
 
-arch_initcall(init_power5_pmu);
+early_initcall(init_power5_pmu);
diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c
index 84a607bda8fb..31603927e376 100644
--- a/arch/powerpc/kernel/power6-pmu.c
+++ b/arch/powerpc/kernel/power6-pmu.c
@@ -544,4 +544,4 @@ static int init_power6_pmu(void)
         return register_power_pmu(&power6_pmu);
 }
 
-arch_initcall(init_power6_pmu);
+early_initcall(init_power6_pmu);
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c
index 852f7b7f6b40..593740fcb799 100644
--- a/arch/powerpc/kernel/power7-pmu.c
+++ b/arch/powerpc/kernel/power7-pmu.c
@@ -369,4 +369,4 @@ static int init_power7_pmu(void)
         return register_power_pmu(&power7_pmu);
 }
 
-arch_initcall(init_power7_pmu);
+early_initcall(init_power7_pmu);
diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c
index 3fee685de4df..9a6e093858fe 100644
--- a/arch/powerpc/kernel/ppc970-pmu.c
+++ b/arch/powerpc/kernel/ppc970-pmu.c
@@ -494,4 +494,4 @@ static int init_ppc970_pmu(void)
         return register_power_pmu(&ppc970_pmu);
 }
 
-arch_initcall(init_ppc970_pmu);
+early_initcall(init_ppc970_pmu);
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index ab3e392ac63c..ef3ef566235e 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -186,3 +186,10 @@ EXPORT_SYMBOL(__mtdcr);
 EXPORT_SYMBOL(__mfdcr);
 #endif
 EXPORT_SYMBOL(empty_zero_page);
+
+#ifdef CONFIG_PPC64
+EXPORT_SYMBOL(__arch_hweight8);
+EXPORT_SYMBOL(__arch_hweight16);
+EXPORT_SYMBOL(__arch_hweight32);
+EXPORT_SYMBOL(__arch_hweight64);
+#endif
diff --git a/arch/powerpc/kernel/ppc_save_regs.S b/arch/powerpc/kernel/ppc_save_regs.S
index 5113bd2285e1..e83ba3f078e4 100644
--- a/arch/powerpc/kernel/ppc_save_regs.S
+++ b/arch/powerpc/kernel/ppc_save_regs.S
@@ -11,6 +11,7 @@
 #include <asm/processor.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/ptrace.h>
 
 /*
  * Grab the register values as they are now.
diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c
index 88334af038e5..c2b7a07cc3d3 100644
--- a/arch/powerpc/kernel/prom_parse.c
+++ b/arch/powerpc/kernel/prom_parse.c
@@ -117,41 +117,3 @@ void of_parse_dma_window(struct device_node *dn, const void *dma_window_prop,
         cells = prop ? *(u32 *)prop : of_n_size_cells(dn);
         *size = of_read_number(dma_window, cells);
 }
-
-/**
- * Search the device tree for the best MAC address to use.  'mac-address' is
- * checked first, because that is supposed to contain to "most recent" MAC
- * address. If that isn't set, then 'local-mac-address' is checked next,
- * because that is the default address.  If that isn't set, then the obsolete
- * 'address' is checked, just in case we're using an old device tree.
- *
- * Note that the 'address' property is supposed to contain a virtual address of
- * the register set, but some DTS files have redefined that property to be the
- * MAC address.
- *
- * All-zero MAC addresses are rejected, because those could be properties that
- * exist in the device tree, but were not set by U-Boot.  For example, the
- * DTS could define 'mac-address' and 'local-mac-address', with zero MAC
- * addresses.  Some older U-Boots only initialized 'local-mac-address'.  In
- * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists
- * but is all zeros.
-*/
-const void *of_get_mac_address(struct device_node *np)
-{
-        struct property *pp;
-
-        pp = of_find_property(np, "mac-address", NULL);
-        if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
-                return pp->value;
-
-        pp = of_find_property(np, "local-mac-address", NULL);
-        if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
-                return pp->value;
-
-        pp = of_find_property(np, "address", NULL);
-        if (pp && (pp->length == 6) && is_valid_ether_addr(pp->value))
-                return pp->value;
-
-        return NULL;
-}
-EXPORT_SYMBOL(of_get_mac_address);
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index a9b32967cff6..906536998291 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1316,6 +1316,10 @@ static int set_dac_range(struct task_struct *child,
 static long ppc_set_hwdebug(struct task_struct *child,
                      struct ppc_hw_breakpoint *bp_info)
 {
+#ifndef CONFIG_PPC_ADV_DEBUG_REGS
+        unsigned long dabr;
+#endif
+
         if (bp_info->version != 1)
                 return -ENOTSUPP;
 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
@@ -1353,11 +1357,10 @@ static long ppc_set_hwdebug(struct task_struct *child,
         /*
          * We only support one data breakpoint
          */
-        if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) ||
-            ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) ||
-            (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_WRITE) ||
-            (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) ||
-            (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
+        if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
+            (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
+            bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT ||
+            bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
                 return -EINVAL;
 
         if (child->thread.dabr)
@@ -1366,7 +1369,14 @@ static long ppc_set_hwdebug(struct task_struct *child,
         if ((unsigned long)bp_info->addr >= TASK_SIZE)
                 return -EIO;
 
-        child->thread.dabr = (unsigned long)bp_info->addr;
+        dabr = (unsigned long)bp_info->addr & ~7UL;
+        dabr |= DABR_TRANSLATION;
+        if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
+                dabr |= DABR_DATA_READ;
+        if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
+                dabr |= DABR_DATA_WRITE;
+
+        child->thread.dabr = dabr;
 
         return 1;
 #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c
index 8a6daf4129f6..69c4be917d07 100644
--- a/arch/powerpc/kernel/ptrace32.c
+++ b/arch/powerpc/kernel/ptrace32.c
@@ -280,7 +280,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                 /* We only support one DABR and no IABRS at the moment */
                 if (addr > 0)
                         break;
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+                ret = put_user(child->thread.dac1, (u32 __user *)data);
+#else
                 ret = put_user(child->thread.dabr, (u32 __user *)data);
+#endif
                 break;
         }
 
@@ -312,6 +316,9 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
         case PTRACE_SET_DEBUGREG:
         case PTRACE_SYSCALL:
         case PTRACE_CONT:
+        case PPC_PTRACE_GETHWDBGINFO:
+        case PPC_PTRACE_SETHWDEBUG:
+        case PPC_PTRACE_DELHWDEBUG:
                 ret = arch_ptrace(child, request, addr, data);
                 break;
 
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index 8fe8bc61c10a..2097f2b3cba8 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -41,6 +41,7 @@
 #include <asm/atomic.h>
 #include <asm/time.h>
 #include <asm/mmu.h>
+#include <asm/topology.h>
 
 struct rtas_t rtas = {
         .lock = __ARCH_SPIN_LOCK_UNLOCKED
@@ -713,6 +714,7 @@ static int __rtas_suspend_last_cpu(struct rtas_suspend_me_data *data, int wake_w
         int cpu;
 
         slb_set_size(SLB_MIN_SIZE);
+        stop_topology_update();
         printk(KERN_DEBUG "calling ibm,suspend-me on cpu %i\n", smp_processor_id());
 
         while (rc == H_MULTI_THREADS_ACTIVE && !atomic_read(&data->done) &&
@@ -728,6 +730,7 @@ static int __rtas_suspend_last_cpu(struct rtas_suspend_me_data *data, int wake_w
                 rc = atomic_read(&data->error);
 
         atomic_set(&data->error, rc);
+        start_topology_update();
 
         if (wake_when_done) {
                 atomic_set(&data->done, 1);
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index ce6f61c6f871..5a0401fcaebd 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -437,8 +437,8 @@ static void __init irqstack_early_init(void)
         unsigned int i;
 
         /*
-         * interrupt stacks must be under 256MB, we cannot afford to take
-         * SLB misses on them.
+         * Interrupt stacks must be in the first segment since we
+         * cannot afford to take SLB misses on them.
          */
         for_each_possible_cpu(i) {
                 softirq_ctx[i] = (struct thread_info *)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 68034bbf2e4f..981360509172 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -466,7 +466,20 @@ out:
         return id;
 }
 
-/* Must be called when no change can occur to cpu_present_mask,
+/* Helper routines for cpu to core mapping */
+int cpu_core_index_of_thread(int cpu)
+{
+        return cpu >> threads_shift;
+}
+EXPORT_SYMBOL_GPL(cpu_core_index_of_thread);
+
+int cpu_first_thread_of_core(int core)
+{
+        return core << threads_shift;
+}
+EXPORT_SYMBOL_GPL(cpu_first_thread_of_core);
+
+/* Must be called when no change can occur to cpu_present_map,
  * i.e. during cpu online or offline.
  */
 static struct device_node *cpu_to_l2cache(int cpu)
@@ -514,7 +527,7 @@ int __devinit start_secondary(void *unused)
         notify_cpu_starting(cpu);
         set_cpu_online(cpu, true);
         /* Update sibling maps */
-        base = cpu_first_thread_in_core(cpu);
+        base = cpu_first_thread_sibling(cpu);
         for (i = 0; i < threads_per_core; i++) {
                 if (cpu_is_offline(base + i))
                         continue;
@@ -600,7 +613,7 @@ int __cpu_disable(void)
                 return err;
 
         /* Update sibling maps */
-        base = cpu_first_thread_in_core(cpu);
+        base = cpu_first_thread_sibling(cpu);
         for (i = 0; i < threads_per_core; i++) {
                 cpumask_clear_cpu(cpu, cpu_sibling_mask(base + i));
                 cpumask_clear_cpu(base + i, cpu_sibling_mask(cpu));
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 010406958d97..09e4dea4a85a 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -155,7 +155,7 @@ EXPORT_SYMBOL_GPL(rtc_lock);
 
 static u64 tb_to_ns_scale __read_mostly;
 static unsigned tb_to_ns_shift __read_mostly;
-static unsigned long boot_tb __read_mostly;
+static u64 boot_tb __read_mostly;
 
 extern struct timezone sys_tz;
 static long timezone_offset;
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index fe460482fa68..9de6f396cf85 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -5,6 +5,7 @@
 #include <asm/cputable.h>
 #include <asm/thread_info.h>
 #include <asm/page.h>
+#include <asm/ptrace.h>
 
 /*
  * load_up_altivec(unused, unused, tsk)
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index 441d2a722f06..1b695fdc362b 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -600,6 +600,11 @@ static void vio_dma_iommu_unmap_sg(struct device *dev,
         vio_cmo_dealloc(viodev, alloc_size);
 }
 
+static int vio_dma_iommu_dma_supported(struct device *dev, u64 mask)
+{
+        return dma_iommu_ops.dma_supported(dev, mask);
+}
+
 struct dma_map_ops vio_dma_mapping_ops = {
         .alloc_coherent = vio_dma_iommu_alloc_coherent,
         .free_coherent  = vio_dma_iommu_free_coherent,
@@ -607,6 +612,7 @@ struct dma_map_ops vio_dma_mapping_ops = {
         .unmap_sg       = vio_dma_iommu_unmap_sg,
         .map_page       = vio_dma_iommu_map_page,
         .unmap_page     = vio_dma_iommu_unmap_page,
+        .dma_supported  = vio_dma_iommu_dma_supported,
 
 };
 
@@ -858,8 +864,7 @@ static void vio_cmo_bus_remove(struct vio_dev *viodev)
 
 static void vio_cmo_set_dma_ops(struct vio_dev *viodev)
 {
-        vio_dma_mapping_ops.dma_supported = dma_iommu_ops.dma_supported;
-        viodev->dev.archdata.dma_ops = &vio_dma_mapping_ops;
+        set_dma_ops(&viodev->dev, &vio_dma_mapping_ops);
 }
 
 /**
@@ -1244,7 +1249,7 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
         if (firmware_has_feature(FW_FEATURE_CMO))
                 vio_cmo_set_dma_ops(viodev);
         else
-                viodev->dev.archdata.dma_ops = &dma_iommu_ops;
+                set_dma_ops(&viodev->dev, &dma_iommu_ops);
         set_iommu_table_base(&viodev->dev, vio_build_iommu_table(viodev));
         set_dev_node(&viodev->dev, of_node_to_nid(of_node));
 
@@ -1252,6 +1257,10 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
         viodev->dev.parent = &vio_bus_device.dev;
         viodev->dev.bus = &vio_bus_type;
         viodev->dev.release = vio_dev_release;
+        /* needed to ensure proper operation of coherent allocations
+         * later, in case driver doesn't set it explicitly */
+        dma_set_mask(&viodev->dev, DMA_BIT_MASK(64));
+        dma_set_coherent_mask(&viodev->dev, DMA_BIT_MASK(64));
 
         /* register with generic device framework */
         if (device_register(&viodev->dev)) {
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 889f2bc106dd..166a6a0ad544 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_HAS_IOMEM)	+= devres.o
 
 obj-$(CONFIG_PPC64)     += copypage_64.o copyuser_64.o \
                            memcpy_64.o usercopy_64.o mem_64.o string.o \
-                           checksum_wrappers_64.o
+                           checksum_wrappers_64.o hweight_64.o
 obj-$(CONFIG_XMON)      += sstep.o ldstfp.o
 obj-$(CONFIG_KPROBES)   += sstep.o ldstfp.o
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += sstep.o ldstfp.o
diff --git a/arch/powerpc/lib/hweight_64.S b/arch/powerpc/lib/hweight_64.S
new file mode 100644
index 000000000000..fda27868cf8c
--- /dev/null
+++ b/arch/powerpc/lib/hweight_64.S
@@ -0,0 +1,110 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2010
+ *
+ * Author: Anton Blanchard <anton@au.ibm.com>
+ */
+#include <asm/processor.h>
+#include <asm/ppc_asm.h>
+
+/* Note: This code relies on -mminimal-toc */
+
+_GLOBAL(__arch_hweight8)
+BEGIN_FTR_SECTION
+        b .__sw_hweight8
+        nop
+        nop
+FTR_SECTION_ELSE
+        PPC_POPCNTB(r3,r3)
+        clrldi  r3,r3,64-8
+        blr
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
+
+_GLOBAL(__arch_hweight16)
+BEGIN_FTR_SECTION
+        b .__sw_hweight16
+        nop
+        nop
+        nop
+        nop
+FTR_SECTION_ELSE
+  BEGIN_FTR_SECTION_NESTED(50)
+        PPC_POPCNTB(r3,r3)
+        srdi    r4,r3,8
+        add     r3,r4,r3
+        clrldi  r3,r3,64-8
+        blr
+  FTR_SECTION_ELSE_NESTED(50)
+        clrlwi  r3,r3,16
+        PPC_POPCNTW(r3,r3)
+        clrldi  r3,r3,64-8
+        blr
+  ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 50)
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
+
+_GLOBAL(__arch_hweight32)
+BEGIN_FTR_SECTION
+        b .__sw_hweight32
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+FTR_SECTION_ELSE
+  BEGIN_FTR_SECTION_NESTED(51)
+        PPC_POPCNTB(r3,r3)
+        srdi    r4,r3,16
+        add     r3,r4,r3
+        srdi    r4,r3,8
+        add     r3,r4,r3
+        clrldi  r3,r3,64-8
+        blr
+  FTR_SECTION_ELSE_NESTED(51)
+        PPC_POPCNTW(r3,r3)
+        clrldi  r3,r3,64-8
+        blr
+  ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 51)
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
+
+_GLOBAL(__arch_hweight64)
+BEGIN_FTR_SECTION
+        b .__sw_hweight64
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+FTR_SECTION_ELSE
+  BEGIN_FTR_SECTION_NESTED(52)
+        PPC_POPCNTB(r3,r3)
+        srdi    r4,r3,32
+        add     r3,r4,r3
+        srdi    r4,r3,16
+        add     r3,r4,r3
+        srdi    r4,r3,8
+        add     r3,r4,r3
+        clrldi  r3,r3,64-8
+        blr
+  FTR_SECTION_ELSE_NESTED(52)
+        PPC_POPCNTD(r3,r3)
+        clrldi  r3,r3,64-8
+        blr
+  ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 52)
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 5e9584405c45..a5991facddce 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -1070,7 +1070,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
                   unsigned long access, unsigned long trap)
 {
         unsigned long vsid;
-        void *pgdir;
+        pgd_t *pgdir;
         pte_t *ptep;
         unsigned long flags;
         int rc, ssize, local = 0;
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index 5ce99848d91e..c0aab52da3a5 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -111,8 +111,8 @@ static unsigned int steal_context_smp(unsigned int id)
                  * a core map instead but this will do for now.
                  */
                 for_each_cpu(cpu, mm_cpumask(mm)) {
-                        for (i = cpu_first_thread_in_core(cpu);
-                             i <= cpu_last_thread_in_core(cpu); i++)
+                        for (i = cpu_first_thread_sibling(cpu);
+                             i <= cpu_last_thread_sibling(cpu); i++)
                                 __set_bit(id, stale_map[i]);
                         cpu = i - 1;
                 }
@@ -264,14 +264,14 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
          */
         if (test_bit(id, stale_map[cpu])) {
                 pr_hardcont(" | stale flush %d [%d..%d]",
-                            id, cpu_first_thread_in_core(cpu),
-                            cpu_last_thread_in_core(cpu));
+                            id, cpu_first_thread_sibling(cpu),
+                            cpu_last_thread_sibling(cpu));
 
                 local_flush_tlb_mm(next);
 
                 /* XXX This clear should ultimately be part of local_flush_tlb_mm */
-                for (i = cpu_first_thread_in_core(cpu);
-                     i <= cpu_last_thread_in_core(cpu); i++) {
+                for (i = cpu_first_thread_sibling(cpu);
+                     i <= cpu_last_thread_sibling(cpu); i++) {
                         __clear_bit(id, stale_map[i]);
                 }
         }
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 74505b245374..bf5cb91f07de 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -20,10 +20,15 @@
 #include <linux/memblock.h>
 #include <linux/of.h>
 #include <linux/pfn.h>
+#include <linux/cpuset.h>
+#include <linux/node.h>
 #include <asm/sparsemem.h>
 #include <asm/prom.h>
 #include <asm/system.h>
 #include <asm/smp.h>
+#include <asm/firmware.h>
+#include <asm/paca.h>
+#include <asm/hvcall.h>
 
 static int numa_enabled = 1;
 
@@ -163,7 +168,7 @@ static void __init get_node_active_region(unsigned long start_pfn,
         work_with_active_regions(nid, get_active_region_work_fn, node_ar);
 }
 
-static void __cpuinit map_cpu_to_node(int cpu, int node)
+static void map_cpu_to_node(int cpu, int node)
 {
         numa_cpu_lookup_table[cpu] = node;
 
@@ -173,7 +178,7 @@ static void __cpuinit map_cpu_to_node(int cpu, int node)
                 cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
 }
 
-#ifdef CONFIG_HOTPLUG_CPU
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PPC_SPLPAR)
 static void unmap_cpu_from_node(unsigned long cpu)
 {
         int node = numa_cpu_lookup_table[cpu];
@@ -187,7 +192,7 @@ static void unmap_cpu_from_node(unsigned long cpu)
                        cpu, node);
         }
 }
-#endif /* CONFIG_HOTPLUG_CPU */
+#endif /* CONFIG_HOTPLUG_CPU || CONFIG_PPC_SPLPAR */
 
 /* must hold reference to node during call */
 static const int *of_get_associativity(struct device_node *dev)
@@ -246,32 +251,41 @@ static void initialize_distance_lookup_table(int nid,
 /* Returns nid in the range [0..MAX_NUMNODES-1], or -1 if no useful numa
  * info is found.
  */
-static int of_node_to_nid_single(struct device_node *device)
+static int associativity_to_nid(const unsigned int *associativity)
 {
         int nid = -1;
-        const unsigned int *tmp;
 
         if (min_common_depth == -1)
                 goto out;
 
-        tmp = of_get_associativity(device);
-        if (!tmp)
-                goto out;
-
-        if (tmp[0] >= min_common_depth)
-                nid = tmp[min_common_depth];
+        if (associativity[0] >= min_common_depth)
+                nid = associativity[min_common_depth];
 
         /* POWER4 LPAR uses 0xffff as invalid node */
         if (nid == 0xffff || nid >= MAX_NUMNODES)
                 nid = -1;
 
-        if (nid > 0 && tmp[0] >= distance_ref_points_depth)
-                initialize_distance_lookup_table(nid, tmp);
+        if (nid > 0 && associativity[0] >= distance_ref_points_depth)
+                initialize_distance_lookup_table(nid, associativity);
 
 out:
         return nid;
 }
 
+/* Returns the nid associated with the given device tree node,
+ * or -1 if not found.
+ */
+static int of_node_to_nid_single(struct device_node *device)
+{
+        int nid = -1;
+        const unsigned int *tmp;
+
+        tmp = of_get_associativity(device);
+        if (tmp)
+                nid = associativity_to_nid(tmp);
+        return nid;
+}
+
 /* Walk the device tree upwards, looking for an associativity id */
 int of_node_to_nid(struct device_node *device)
 {
@@ -1247,4 +1261,275 @@ int hot_add_scn_to_nid(unsigned long scn_addr)
         return nid;
 }
 
+static u64 hot_add_drconf_memory_max(void)
+{
+        struct device_node *memory = NULL;
+        unsigned int drconf_cell_cnt = 0;
+        u64 lmb_size = 0;
+        const u32 *dm = 0;
+
+        memory = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
+        if (memory) {
+                drconf_cell_cnt = of_get_drconf_memory(memory, &dm);
+                lmb_size = of_get_lmb_size(memory);
+                of_node_put(memory);
+        }
+        return lmb_size * drconf_cell_cnt;
+}
+
+/*
+ * memory_hotplug_max - return max address of memory that may be added
+ *
+ * This is currently only used on systems that support drconfig memory
+ * hotplug.
+ */
+u64 memory_hotplug_max(void)
+{
+        return max(hot_add_drconf_memory_max(), memblock_end_of_DRAM());
+}
 #endif /* CONFIG_MEMORY_HOTPLUG */
+
+/* Vrtual Processor Home Node (VPHN) support */
+#ifdef CONFIG_PPC_SPLPAR
+#define VPHN_NR_CHANGE_CTRS (8)
+static u8 vphn_cpu_change_counts[NR_CPUS][VPHN_NR_CHANGE_CTRS];
+static cpumask_t cpu_associativity_changes_mask;
+static int vphn_enabled;
+static void set_topology_timer(void);
+
+/*
+ * Store the current values of the associativity change counters in the
+ * hypervisor.
+ */
+static void setup_cpu_associativity_change_counters(void)
+{
+        int cpu = 0;
+
+        for_each_possible_cpu(cpu) {
+                int i = 0;
+                u8 *counts = vphn_cpu_change_counts[cpu];
+                volatile u8 *hypervisor_counts = lppaca[cpu].vphn_assoc_counts;
+
+                for (i = 0; i < VPHN_NR_CHANGE_CTRS; i++) {
+                        counts[i] = hypervisor_counts[i];
+                }
+        }
+}
+
+/*
+ * The hypervisor maintains a set of 8 associativity change counters in
+ * the VPA of each cpu that correspond to the associativity levels in the
+ * ibm,associativity-reference-points property. When an associativity
+ * level changes, the corresponding counter is incremented.
+ *
+ * Set a bit in cpu_associativity_changes_mask for each cpu whose home
+ * node associativity levels have changed.
+ *
+ * Returns the number of cpus with unhandled associativity changes.
+ */
+static int update_cpu_associativity_changes_mask(void)
+{
+        int cpu = 0, nr_cpus = 0;
+        cpumask_t *changes = &cpu_associativity_changes_mask;
+
+        cpumask_clear(changes);
+
+        for_each_possible_cpu(cpu) {
+                int i, changed = 0;
+                u8 *counts = vphn_cpu_change_counts[cpu];
+                volatile u8 *hypervisor_counts = lppaca[cpu].vphn_assoc_counts;
+
+                for (i = 0; i < VPHN_NR_CHANGE_CTRS; i++) {
+                        if (hypervisor_counts[i] > counts[i]) {
+                                counts[i] = hypervisor_counts[i];
+                                changed = 1;
+                        }
+                }
+                if (changed) {
+                        cpumask_set_cpu(cpu, changes);
+                        nr_cpus++;
+                }
+        }
+
+        return nr_cpus;
+}
+
+/* 6 64-bit registers unpacked into 12 32-bit associativity values */
+#define VPHN_ASSOC_BUFSIZE (6*sizeof(u64)/sizeof(u32))
+
+/*
+ * Convert the associativity domain numbers returned from the hypervisor
+ * to the sequence they would appear in the ibm,associativity property.
+ */
+static int vphn_unpack_associativity(const long *packed, unsigned int *unpacked)
+{
+        int i = 0;
+        int nr_assoc_doms = 0;
+        const u16 *field = (const u16*) packed;
+
+#define VPHN_FIELD_UNUSED       (0xffff)
+#define VPHN_FIELD_MSB          (0x8000)
+#define VPHN_FIELD_MASK         (~VPHN_FIELD_MSB)
+
+        for (i = 0; i < VPHN_ASSOC_BUFSIZE; i++) {
+                if (*field == VPHN_FIELD_UNUSED) {
+                        /* All significant fields processed, and remaining
+                         * fields contain the reserved value of all 1's.
+                         * Just store them.
+                         */
+                        unpacked[i] = *((u32*)field);
+                        field += 2;
+                }
+                else if (*field & VPHN_FIELD_MSB) {
+                        /* Data is in the lower 15 bits of this field */
+                        unpacked[i] = *field & VPHN_FIELD_MASK;
+                        field++;
+                        nr_assoc_doms++;
+                }
+                else {
+                        /* Data is in the lower 15 bits of this field
+                         * concatenated with the next 16 bit field
+                         */
+                        unpacked[i] = *((u32*)field);
+                        field += 2;
+                        nr_assoc_doms++;
+                }
+        }
+
+        return nr_assoc_doms;
+}
+
+/*
+ * Retrieve the new associativity information for a virtual processor's
+ * home node.
+ */
+static long hcall_vphn(unsigned long cpu, unsigned int *associativity)
+{
+        long rc = 0;
+        long retbuf[PLPAR_HCALL9_BUFSIZE] = {0};
+        u64 flags = 1;
+        int hwcpu = get_hard_smp_processor_id(cpu);
+
+        rc = plpar_hcall9(H_HOME_NODE_ASSOCIATIVITY, retbuf, flags, hwcpu);
+        vphn_unpack_associativity(retbuf, associativity);
+
+        return rc;
+}
+
+static long vphn_get_associativity(unsigned long cpu,
+                                        unsigned int *associativity)
+{
+        long rc = 0;
+
+        rc = hcall_vphn(cpu, associativity);
+
+        switch (rc) {
+        case H_FUNCTION:
+                printk(KERN_INFO
+                        "VPHN is not supported. Disabling polling...\n");
+                stop_topology_update();
+                break;
+        case H_HARDWARE:
+                printk(KERN_ERR
+                        "hcall_vphn() experienced a hardware fault "
+                        "preventing VPHN. Disabling polling...\n");
+                stop_topology_update();
+        }
+
+        return rc;
+}
+
+/*
+ * Update the node maps and sysfs entries for each cpu whose home node
+ * has changed.
+ */
+int arch_update_cpu_topology(void)
+{
+        int cpu = 0, nid = 0, old_nid = 0;
+        unsigned int associativity[VPHN_ASSOC_BUFSIZE] = {0};
+        struct sys_device *sysdev = NULL;
+
+        for_each_cpu_mask(cpu, cpu_associativity_changes_mask) {
+                vphn_get_associativity(cpu, associativity);
+                nid = associativity_to_nid(associativity);
+
+                if (nid < 0 || !node_online(nid))
+                        nid = first_online_node;
+
+                old_nid = numa_cpu_lookup_table[cpu];
+
+                /* Disable hotplug while we update the cpu
+                 * masks and sysfs.
+                 */
+                get_online_cpus();
+                unregister_cpu_under_node(cpu, old_nid);
+                unmap_cpu_from_node(cpu);
+                map_cpu_to_node(cpu, nid);
+                register_cpu_under_node(cpu, nid);
+                put_online_cpus();
+
+                sysdev = get_cpu_sysdev(cpu);
+                if (sysdev)
+                        kobject_uevent(&sysdev->kobj, KOBJ_CHANGE);
+        }
+
+        return 1;
+}
+
+static void topology_work_fn(struct work_struct *work)
+{
+        rebuild_sched_domains();
+}
+static DECLARE_WORK(topology_work, topology_work_fn);
+
+void topology_schedule_update(void)
+{
+        schedule_work(&topology_work);
+}
+
+static void topology_timer_fn(unsigned long ignored)
+{
+        if (!vphn_enabled)
+                return;
+        if (update_cpu_associativity_changes_mask() > 0)
+                topology_schedule_update();
+        set_topology_timer();
+}
+static struct timer_list topology_timer =
+        TIMER_INITIALIZER(topology_timer_fn, 0, 0);
+
+static void set_topology_timer(void)
+{
+        topology_timer.data = 0;
+        topology_timer.expires = jiffies + 60 * HZ;
+        add_timer(&topology_timer);
+}
+
+/*
+ * Start polling for VPHN associativity changes.
+ */
+int start_topology_update(void)
+{
+        int rc = 0;
+
+        if (firmware_has_feature(FW_FEATURE_VPHN)) {
+                vphn_enabled = 1;
+                setup_cpu_associativity_change_counters();
+                init_timer_deferrable(&topology_timer);
+                set_topology_timer();
+                rc = 1;
+        }
+
+        return rc;
+}
+__initcall(start_topology_update);
+
+/*
+ * Disable polling for VPHN associativity changes.
+ */
+int stop_topology_update(void)
+{
+        vphn_enabled = 0;
+        return del_timer_sync(&topology_timer);
+}
+#endif /* CONFIG_PPC_SPLPAR */
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index a87ead0138b4..8dc41c0157fe 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -78,7 +78,7 @@ pgd_t *pgd_alloc(struct mm_struct *mm)
 
         /* pgdir take page or two with 4K pages and a page fraction otherwise */
 #ifndef CONFIG_PPC_4K_PAGES
-        ret = (pgd_t *)kzalloc(1 << PGDIR_ORDER, GFP_KERNEL);
+        ret = kzalloc(1 << PGDIR_ORDER, GFP_KERNEL);
 #else
         ret = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO,
                         PGDIR_ORDER - PAGE_SHIFT);
@@ -230,6 +230,7 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags,
                 area = get_vm_area_caller(size, VM_IOREMAP, caller);
                 if (area == 0)
                         return NULL;
+                area->phys_addr = p;
                 v = (unsigned long) area->addr;
         } else {
                 v = (ioremap_bot -= size);
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 21d6dfab7942..88927a05cdc2 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -223,6 +223,8 @@ void __iomem * __ioremap_caller(phys_addr_t addr, unsigned long size,
                                             caller);
                 if (area == NULL)
                         return NULL;
+
+                area->phys_addr = paligned;
                 ret = __ioremap_at(paligned, area->addr, size, flags);
                 if (!ret)
                         vunmap(area->addr);
diff --git a/arch/powerpc/platforms/40x/ppc40x_simple.c b/arch/powerpc/platforms/40x/ppc40x_simple.c
index 546bbc229d19..2521d93ef136 100644
--- a/arch/powerpc/platforms/40x/ppc40x_simple.c
+++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
@@ -50,7 +50,7 @@ machine_device_initcall(ppc40x_simple, ppc40x_device_probe);
  * Again, if your board needs to do things differently then create a
  * board.c file for it rather than adding it to this list.
  */
-static char *board[] __initdata = {
+static const char *board[] __initdata = {
         "amcc,acadia",
         "amcc,haleakala",
         "amcc,kilauea",
@@ -60,14 +60,9 @@ static char *board[] __initdata = {
 
 static int __init ppc40x_probe(void)
 {
-        unsigned long root = of_get_flat_dt_root();
-        int i = 0;
-
-        for (i = 0; i < ARRAY_SIZE(board); i++) {
-                if (of_flat_dt_is_compatible(root, board[i])) {
-                        ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);
-                        return 1;
-                }
+        if (of_flat_dt_match(of_get_flat_dt_root(), board)) {
+                ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);
+                return 1;
         }
 
         return 0;
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 82ff326e0795..c04d16df8488 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -1,4 +1,7 @@
-obj-$(CONFIG_44x)       := misc_44x.o idle.o
+obj-$(CONFIG_44x)       += misc_44x.o
+ifneq ($(CONFIG_PPC4xx_CPM),y)
+obj-$(CONFIG_44x)       += idle.o
+endif
 obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
 obj-$(CONFIG_EBONY)     += ebony.o
 obj-$(CONFIG_SAM440EP)  += sam440ep.o
diff --git a/arch/powerpc/platforms/512x/mpc5121_generic.c b/arch/powerpc/platforms/512x/mpc5121_generic.c
index e487eb06ec6b..926731f1ff01 100644
--- a/arch/powerpc/platforms/512x/mpc5121_generic.c
+++ b/arch/powerpc/platforms/512x/mpc5121_generic.c
@@ -26,7 +26,7 @@
 /*
  * list of supported boards
  */
-static char *board[] __initdata = {
+static const char *board[] __initdata = {
         "prt,prtlvt",
         NULL
 };
@@ -36,16 +36,7 @@ static char *board[] __initdata = {
  */
 static int __init mpc5121_generic_probe(void)
 {
-        unsigned long node = of_get_flat_dt_root();
-        int i = 0;
-
-        while (board[i]) {
-                if (of_flat_dt_is_compatible(node, board[i]))
-                        break;
-                i++;
-        }
-
-        return board[i] != NULL;
+        return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
 
 define_machine(mpc5121_generic) {
diff --git a/arch/powerpc/platforms/52xx/lite5200.c b/arch/powerpc/platforms/52xx/lite5200.c
index de55bc0584b5..01ffa64d2aa7 100644
--- a/arch/powerpc/platforms/52xx/lite5200.c
+++ b/arch/powerpc/platforms/52xx/lite5200.c
@@ -172,20 +172,18 @@ static void __init lite5200_setup_arch(void)
         mpc52xx_setup_pci();
 }
 
+static const char *board[] __initdata = {
+        "fsl,lite5200",
+        "fsl,lite5200b",
+        NULL,
+};
+
 /*
  * Called very early, MMU is off, device-tree isn't unflattened
  */
 static int __init lite5200_probe(void)
 {
-        unsigned long node = of_get_flat_dt_root();
-        const char *model = of_get_flat_dt_prop(node, "model", NULL);
-
-        if (!of_flat_dt_is_compatible(node, "fsl,lite5200") &&
-            !of_flat_dt_is_compatible(node, "fsl,lite5200b"))
-                return 0;
-        pr_debug("%s board found\n", model ? model : "unknown");
-
-        return 1;
+        return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
 
 define_machine(lite5200) {
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c
index 0bac3a3dbecf..2c7780cb68e5 100644
--- a/arch/powerpc/platforms/52xx/media5200.c
+++ b/arch/powerpc/platforms/52xx/media5200.c
@@ -239,7 +239,7 @@ static void __init media5200_setup_arch(void)
 }
 
 /* list of the supported boards */
-static char *board[] __initdata = {
+static const char *board[] __initdata = {
         "fsl,media5200",
         NULL
 };
@@ -249,16 +249,7 @@ static char *board[] __initdata = {
  */
 static int __init media5200_probe(void)
 {
-        unsigned long node = of_get_flat_dt_root();
-        int i = 0;
-
-        while (board[i]) {
-                if (of_flat_dt_is_compatible(node, board[i]))
-                        break;
-                i++;
-        }
-
-        return (board[i] != NULL);
+        return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
 
 define_machine(media5200_platform) {
diff --git a/arch/powerpc/platforms/52xx/mpc5200_simple.c b/arch/powerpc/platforms/52xx/mpc5200_simple.c
index d45be5b5ad49..e36d6e232ae6 100644
--- a/arch/powerpc/platforms/52xx/mpc5200_simple.c
+++ b/arch/powerpc/platforms/52xx/mpc5200_simple.c
@@ -49,7 +49,7 @@ static void __init mpc5200_simple_setup_arch(void)
 }
 
 /* list of the supported boards */
-static char *board[] __initdata = {
+static const char *board[] __initdata = {
         "intercontrol,digsy-mtc",
         "manroland,mucmc52",
         "manroland,uc101",
@@ -66,16 +66,7 @@ static char *board[] __initdata = {
  */
 static int __init mpc5200_simple_probe(void)
 {
-        unsigned long node = of_get_flat_dt_root();
-        int i = 0;
-
-        while (board[i]) {
-                if (of_flat_dt_is_compatible(node, board[i]))
-                        break;
-                i++;
-        }
-        
-        return (board[i] != NULL);
+        return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
 
 define_machine(mpc5200_simple_platform) {
diff --git a/arch/powerpc/platforms/83xx/mpc830x_rdb.c b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
index 846831d495b5..661d354e4ff2 100644
--- a/arch/powerpc/platforms/83xx/mpc830x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc830x_rdb.c
@@ -57,16 +57,19 @@ static void __init mpc830x_rdb_init_IRQ(void)
         ipic_set_default_priority();
 }
 
+struct const char *board[] __initdata = {
+        "MPC8308RDB",
+        "fsl,mpc8308rdb",
+        "denx,mpc8308_p1m",
+        NULL
+}
+
 /*
  * Called very early, MMU is off, device-tree isn't unflattened
  */
 static int __init mpc830x_rdb_probe(void)
 {
-        unsigned long root = of_get_flat_dt_root();
-
-        return of_flat_dt_is_compatible(root, "MPC8308RDB") ||
-               of_flat_dt_is_compatible(root, "fsl,mpc8308rdb") ||
-               of_flat_dt_is_compatible(root, "denx,mpc8308_p1m");
+        return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
 
 static struct of_device_id __initdata of_bus_ids[] = {
diff --git a/arch/powerpc/platforms/83xx/mpc831x_rdb.c b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
index ae525e4745d2..b54cd736a895 100644
--- a/arch/powerpc/platforms/83xx/mpc831x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
@@ -60,15 +60,18 @@ static void __init mpc831x_rdb_init_IRQ(void)
         ipic_set_default_priority();
 }
 
+struct const char *board[] __initdata = {
+        "MPC8313ERDB",
+        "fsl,mpc8315erdb",
+        NULL
+}
+
 /*
  * Called very early, MMU is off, device-tree isn't unflattened
  */
 static int __init mpc831x_rdb_probe(void)
 {
-        unsigned long root = of_get_flat_dt_root();
-
-        return of_flat_dt_is_compatible(root, "MPC8313ERDB") ||
-               of_flat_dt_is_compatible(root, "fsl,mpc8315erdb");
+        return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
 
 static struct of_device_id __initdata of_bus_ids[] = {
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index 910caa6b5810..7bafbf2ec0f9 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -101,17 +101,20 @@ static void __init mpc837x_rdb_init_IRQ(void)
         ipic_set_default_priority();
 }
 
+static const char *board[] __initdata = {
+        "fsl,mpc8377rdb",
+        "fsl,mpc8378rdb",
+        "fsl,mpc8379rdb",
+        "fsl,mpc8377wlan",
+        NULL
+};
+
 /*
  * Called very early, MMU is off, device-tree isn't unflattened
  */
 static int __init mpc837x_rdb_probe(void)
 {
-        unsigned long root = of_get_flat_dt_root();
-
-        return of_flat_dt_is_compatible(root, "fsl,mpc8377rdb") ||
-               of_flat_dt_is_compatible(root, "fsl,mpc8378rdb") ||
-               of_flat_dt_is_compatible(root, "fsl,mpc8379rdb") ||
-               of_flat_dt_is_compatible(root, "fsl,mpc8377wlan");
+        return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
 
 define_machine(mpc837x_rdb) {
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 8f29bbce5360..5e847d0b47c8 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -186,21 +186,21 @@ static int __init declare_of_platform_devices(void)
 }
 machine_device_initcall(tqm85xx, declare_of_platform_devices);
 
+static const char *board[] __initdata = {
+        "tqc,tqm8540",
+        "tqc,tqm8541",
+        "tqc,tqm8548",
+        "tqc,tqm8555",
+        "tqc,tqm8560",
+        NULL
+};
+
 /*
  * Called very early, device-tree isn't unflattened
  */
 static int __init tqm85xx_probe(void)
 {
-        unsigned long root = of_get_flat_dt_root();
-
-        if ((of_flat_dt_is_compatible(root, "tqc,tqm8540")) ||
-            (of_flat_dt_is_compatible(root, "tqc,tqm8541")) ||
-            (of_flat_dt_is_compatible(root, "tqc,tqm8548")) ||
-            (of_flat_dt_is_compatible(root, "tqc,tqm8555")) ||
-            (of_flat_dt_is_compatible(root, "tqc,tqm8560")))
-                return 1;
-
-        return 0;
+        return of_flat_dt_match(of_get_flat_dt_root(), board);
 }
 
 define_machine(tqm85xx) {
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 956154f32cfe..20576829eca5 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -313,13 +313,14 @@ config OF_RTC
 source "arch/powerpc/sysdev/bestcomm/Kconfig"
 
 config MPC8xxx_GPIO
-        bool "MPC8xxx GPIO support"
-        depends on PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || FSL_SOC_BOOKE || PPC_86xx
+        bool "MPC512x/MPC8xxx GPIO support"
+        depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \
+                   FSL_SOC_BOOKE || PPC_86xx
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
         help
           Say Y here if you're going to use hardware that connects to the
-          MPC831x/834x/837x/8572/8610 GPIOs.
+          MPC512x/831x/834x/837x/8572/8610 GPIOs.
 
 config SIMPLE_GPIO
         bool "Support for simple, memory-mapped GPIO controllers"
diff --git a/arch/powerpc/platforms/cell/beat_iommu.c b/arch/powerpc/platforms/cell/beat_iommu.c
index beec405eb6f8..3ce685568935 100644
--- a/arch/powerpc/platforms/cell/beat_iommu.c
+++ b/arch/powerpc/platforms/cell/beat_iommu.c
@@ -76,7 +76,7 @@ static void __init celleb_init_direct_mapping(void)
 
 static void celleb_dma_dev_setup(struct device *dev)
 {
-        dev->archdata.dma_ops = get_pci_dma_ops();
+        set_dma_ops(dev, &dma_direct_ops);
         set_dma_offset(dev, celleb_dma_direct_offset);
 }
 
@@ -106,7 +106,6 @@ static struct notifier_block celleb_of_bus_notifier = {
 static int __init celleb_init_iommu(void)
 {
         celleb_init_direct_mapping();
-        set_pci_dma_ops(&dma_direct_ops);
         ppc_md.pci_dma_dev_setup = celleb_pci_dma_dev_setup;
         bus_register_notifier(&platform_bus_type, &celleb_of_bus_notifier);
 
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index 3532b92de983..856e9c398068 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -71,12 +71,18 @@ spufs_alloc_inode(struct super_block *sb)
         return &ei->vfs_inode;
 }
 
-static void
-spufs_destroy_inode(struct inode *inode)
+static void spufs_i_callback(struct rcu_head *head)
 {
+        struct inode *inode = container_of(head, struct inode, i_rcu);
+        INIT_LIST_HEAD(&inode->i_dentry);
         kmem_cache_free(spufs_inode_cache, SPUFS_I(inode));
 }
 
+static void spufs_destroy_inode(struct inode *inode)
+{
+        call_rcu(&inode->i_rcu, spufs_i_callback);
+}
+
 static void
 spufs_init_once(void *p)
 {
@@ -159,18 +165,18 @@ static void spufs_prune_dir(struct dentry *dir)
 
         mutex_lock(&dir->d_inode->i_mutex);
         list_for_each_entry_safe(dentry, tmp, &dir->d_subdirs, d_u.d_child) {
-                spin_lock(&dcache_lock);
                 spin_lock(&dentry->d_lock);
                 if (!(d_unhashed(dentry)) && dentry->d_inode) {
-                        dget_locked(dentry);
+                        dget_dlock(dentry);
                         __d_drop(dentry);
                         spin_unlock(&dentry->d_lock);
                         simple_unlink(dir->d_inode, dentry);
-                        spin_unlock(&dcache_lock);
+                        /* XXX: what was dcache_lock protecting here? Other
+                         * filesystems (IB, configfs) release dcache_lock
+                         * before unlink */
                         dput(dentry);
                 } else {
                         spin_unlock(&dentry->d_lock);
-                        spin_unlock(&dcache_lock);
                 }
         }
         shrink_dcache_parent(dir);
diff --git a/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c b/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c
index a101abf17504..3b894f585280 100644
--- a/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c
+++ b/arch/powerpc/platforms/cell/spufs/lscsa_alloc.c
@@ -36,10 +36,9 @@ static int spu_alloc_lscsa_std(struct spu_state *csa)
         struct spu_lscsa *lscsa;
         unsigned char *p;
 
-        lscsa = vmalloc(sizeof(struct spu_lscsa));
+        lscsa = vzalloc(sizeof(struct spu_lscsa));
         if (!lscsa)
                 return -ENOMEM;
-        memset(lscsa, 0, sizeof(struct spu_lscsa));
         csa->lscsa = lscsa;
 
         /* Set LS pages reserved to allow for user-space mapping. */
diff --git a/arch/powerpc/platforms/chrp/time.c b/arch/powerpc/platforms/chrp/time.c
index 054dfe5b8e77..f803f4b8ab6f 100644
--- a/arch/powerpc/platforms/chrp/time.c
+++ b/arch/powerpc/platforms/chrp/time.c
@@ -29,6 +29,10 @@
 
 extern spinlock_t rtc_lock;
 
+#define NVRAM_AS0  0x74
+#define NVRAM_AS1  0x75
+#define NVRAM_DATA 0x77
+
 static int nvram_as1 = NVRAM_AS1;
 static int nvram_as0 = NVRAM_AS0;
 static int nvram_data = NVRAM_DATA;
diff --git a/arch/powerpc/platforms/iseries/mf.c b/arch/powerpc/platforms/iseries/mf.c
index 42d0a886de05..b5e026bdca21 100644
--- a/arch/powerpc/platforms/iseries/mf.c
+++ b/arch/powerpc/platforms/iseries/mf.c
@@ -1045,71 +1045,9 @@ static const struct file_operations mf_side_proc_fops = {
         .write          = mf_side_proc_write,
 };
 
-#if 0
-static void mf_getSrcHistory(char *buffer, int size)
-{
-        struct IplTypeReturnStuff return_stuff;
-        struct pending_event *ev = new_pending_event();
-        int rc = 0;
-        char *pages[4];
-
-        pages[0] = kmalloc(4096, GFP_ATOMIC);
-        pages[1] = kmalloc(4096, GFP_ATOMIC);
-        pages[2] = kmalloc(4096, GFP_ATOMIC);
-        pages[3] = kmalloc(4096, GFP_ATOMIC);
-        if ((ev == NULL) || (pages[0] == NULL) || (pages[1] == NULL)
-                         || (pages[2] == NULL) || (pages[3] == NULL))
-                return -ENOMEM;
-
-        return_stuff.xType = 0;
-        return_stuff.xRc = 0;
-        return_stuff.xDone = 0;
-        ev->event.hp_lp_event.xSubtype = 6;
-        ev->event.hp_lp_event.x.xSubtypeData =
-                subtype_data('M', 'F', 'V', 'I');
-        ev->event.data.vsp_cmd.xEvent = &return_stuff;
-        ev->event.data.vsp_cmd.cmd = 4;
-        ev->event.data.vsp_cmd.lp_index = HvLpConfig_getLpIndex();
-        ev->event.data.vsp_cmd.result_code = 0xFF;
-        ev->event.data.vsp_cmd.reserved = 0;
-        ev->event.data.vsp_cmd.sub_data.page[0] = iseries_hv_addr(pages[0]);
-        ev->event.data.vsp_cmd.sub_data.page[1] = iseries_hv_addr(pages[1]);
-        ev->event.data.vsp_cmd.sub_data.page[2] = iseries_hv_addr(pages[2]);
-        ev->event.data.vsp_cmd.sub_data.page[3] = iseries_hv_addr(pages[3]);
-        mb();
-        if (signal_event(ev) != 0)
-                return;
-
-        while (return_stuff.xDone != 1)
-                udelay(10);
-        if (return_stuff.xRc == 0)
-                memcpy(buffer, pages[0], size);
-        kfree(pages[0]);
-        kfree(pages[1]);
-        kfree(pages[2]);
-        kfree(pages[3]);
-}
-#endif
-
 static int mf_src_proc_show(struct seq_file *m, void *v)
 {
-#if 0
-        int len;
-
-        mf_getSrcHistory(page, count);
-        len = count;
-        len -= off;
-        if (len < count) {
-                *eof = 1;
-                if (len <= 0)
-                        return 0;
-        } else
-                len = count;
-        *start = page + off;
-        return len;
-#else
         return 0;
-#endif
 }
 
 static int mf_src_proc_open(struct inode *inode, struct file *file)
diff --git a/arch/powerpc/platforms/pasemi/iommu.c b/arch/powerpc/platforms/pasemi/iommu.c
index 1f9fb2c57761..14943ef01918 100644
--- a/arch/powerpc/platforms/pasemi/iommu.c
+++ b/arch/powerpc/platforms/pasemi/iommu.c
@@ -156,20 +156,12 @@ static void iommu_table_iobmap_setup(void)
 
 static void pci_dma_bus_setup_pasemi(struct pci_bus *bus)
 {
-        struct device_node *dn;
-
         pr_debug("pci_dma_bus_setup, bus %p, bus->self %p\n", bus, bus->self);
 
         if (!iommu_table_iobmap_inited) {
                 iommu_table_iobmap_inited = 1;
                 iommu_table_iobmap_setup();
         }
-
-        dn = pci_bus_to_OF_node(bus);
-
-        if (dn)
-                PCI_DN(dn)->iommu_table = &iommu_table_iobmap;
-
 }
 
 
@@ -192,9 +184,6 @@ static void pci_dma_dev_setup_pasemi(struct pci_dev *dev)
         set_iommu_table_base(&dev->dev, &iommu_table_iobmap);
 }
 
-static void pci_dma_bus_setup_null(struct pci_bus *b) { }
-static void pci_dma_dev_setup_null(struct pci_dev *d) { }
-
 int __init iob_init(struct device_node *dn)
 {
         unsigned long tmp;
@@ -251,14 +240,8 @@ void __init iommu_init_early_pasemi(void)
         iommu_off = of_chosen &&
                         of_get_property(of_chosen, "linux,iommu-off", NULL);
 #endif
-        if (iommu_off) {
-                /* Direct I/O, IOMMU off */
-                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_null;
-                ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_null;
-                set_pci_dma_ops(&dma_direct_ops);
-
+        if (iommu_off)
                 return;
-        }
 
         iob_init(NULL);
 
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index 9deb274841f1..d5aceb7fb125 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -506,6 +506,15 @@ static int __init pmac_declare_of_platform_devices(void)
                 of_platform_device_create(np, "smu", NULL);
                 of_node_put(np);
         }
+        np = of_find_node_by_type(NULL, "fcu");
+        if (np == NULL) {
+                /* Some machines have strangely broken device-tree */
+                np = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/fan@15e");
+        }
+        if (np) {
+                of_platform_device_create(np, "temperature", NULL);
+                of_node_put(np);
+        }
 
         return 0;
 }
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 3139814f6439..5d1b743dbe7e 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -33,6 +33,16 @@ config PSERIES_MSI
        depends on PCI_MSI && EEH
        default y
 
+config PSERIES_ENERGY
+        tristate "pSeries energy management capabilities driver"
+        depends on PPC_PSERIES
+        default y
+        help
+          Provides interface to platform energy management capabilities
+          on supported PSERIES platforms.
+          Provides: /sys/devices/system/cpu/pseries_(de)activation_hint_list
+          and /sys/devices/system/cpu/cpuN/pseries_(de)activation_hint
+
 config SCANLOG
         tristate "Scanlog dump interface"
         depends on RTAS_PROC && PPC_PSERIES
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index 59eb8bdaa79d..fc5237810ece 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_EEH)	+= eeh.o eeh_cache.o eeh_driver.o eeh_event.o eeh_sysfs.o
 obj-$(CONFIG_KEXEC)     += kexec.o
 obj-$(CONFIG_PCI)       += pci.o pci_dlpar.o
 obj-$(CONFIG_PSERIES_MSI)       += msi.o
+obj-$(CONFIG_PSERIES_ENERGY)    += pseries_energy.o
 
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug-cpu.o
 obj-$(CONFIG_MEMORY_HOTPLUG)    += hotplug-memory.o
diff --git a/arch/powerpc/platforms/pseries/eeh_sysfs.c b/arch/powerpc/platforms/pseries/eeh_sysfs.c
index 15e13b568904..23982c7892d2 100644
--- a/arch/powerpc/platforms/pseries/eeh_sysfs.c
+++ b/arch/powerpc/platforms/pseries/eeh_sysfs.c
@@ -25,7 +25,6 @@
 #include <linux/pci.h>
 #include <asm/ppc-pci.h>
 #include <asm/pci-bridge.h>
-#include <linux/kobject.h>
 
 /**
  * EEH_SHOW_ATTR -- create sysfs entry for eeh statistic
diff --git a/arch/powerpc/platforms/pseries/firmware.c b/arch/powerpc/platforms/pseries/firmware.c
index 0a14d8cd314f..0b0eff0cce35 100644
--- a/arch/powerpc/platforms/pseries/firmware.c
+++ b/arch/powerpc/platforms/pseries/firmware.c
@@ -55,6 +55,7 @@ firmware_features_table[FIRMWARE_MAX_FEATURES] = {
         {FW_FEATURE_XDABR,              "hcall-xdabr"},
         {FW_FEATURE_MULTITCE,           "hcall-multi-tce"},
         {FW_FEATURE_SPLPAR,             "hcall-splpar"},
+        {FW_FEATURE_VPHN,               "hcall-vphn"},
 };
 
 /* Build up the firmware features bitmask using the contents of
diff --git a/arch/powerpc/platforms/pseries/hvCall.S b/arch/powerpc/platforms/pseries/hvCall.S
index 48d20573e4de..fd05fdee576a 100644
--- a/arch/powerpc/platforms/pseries/hvCall.S
+++ b/arch/powerpc/platforms/pseries/hvCall.S
@@ -11,6 +11,7 @@
 #include <asm/processor.h>
 #include <asm/ppc_asm.h>
 #include <asm/asm-offsets.h>
+#include <asm/ptrace.h>
         
 #define STK_PARM(i)     (48 + ((i)-3)*8)
 
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index a77bcaed80af..edea60b7ee90 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -140,7 +140,7 @@ static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
         return ret;
 }
 
-static DEFINE_PER_CPU(u64 *, tce_page) = NULL;
+static DEFINE_PER_CPU(u64 *, tce_page);
 
 static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
                                      long npages, unsigned long uaddr,
@@ -323,14 +323,13 @@ static void iommu_table_setparms(struct pci_controller *phb,
 static void iommu_table_setparms_lpar(struct pci_controller *phb,
                                       struct device_node *dn,
                                       struct iommu_table *tbl,
-                                      const void *dma_window,
-                                      int bussubno)
+                                      const void *dma_window)
 {
         unsigned long offset, size;
 
-        tbl->it_busno  = bussubno;
         of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
 
+        tbl->it_busno = phb->bus->number;
         tbl->it_base   = 0;
         tbl->it_blocksize  = 16;
         tbl->it_type = TCE_PCI;
@@ -450,14 +449,10 @@ static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
         if (!ppci->iommu_table) {
                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
                                    ppci->phb->node);
-                iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window,
-                        bus->number);
+                iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
                 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
                 pr_debug("  created table: %p\n", ppci->iommu_table);
         }
-
-        if (pdn != dn)
-                PCI_DN(dn)->iommu_table = ppci->iommu_table;
 }
 
 
@@ -533,21 +528,11 @@ static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
         }
         pr_debug("  parent is %s\n", pdn->full_name);
 
-        /* Check for parent == NULL so we don't try to setup the empty EADS
-         * slots on POWER4 machines.
-         */
-        if (dma_window == NULL || pdn->parent == NULL) {
-                pr_debug("  no dma window for device, linking to parent\n");
-                set_iommu_table_base(&dev->dev, PCI_DN(pdn)->iommu_table);
-                return;
-        }
-
         pci = PCI_DN(pdn);
         if (!pci->iommu_table) {
                 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
                                    pci->phb->node);
-                iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window,
-                        pci->phb->bus->number);
+                iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
                 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
                 pr_debug("  created table: %p\n", pci->iommu_table);
         } else {
@@ -571,8 +556,7 @@ static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long acti
 
         switch (action) {
         case PSERIES_RECONFIG_REMOVE:
-                if (pci && pci->iommu_table &&
-                    of_get_property(np, "ibm,dma-window", NULL))
+                if (pci && pci->iommu_table)
                         iommu_free_table(pci->iommu_table, np->full_name);
                 break;
         default:
@@ -589,13 +573,8 @@ static struct notifier_block iommu_reconfig_nb = {
 /* These are called very early. */
 void iommu_init_early_pSeries(void)
 {
-        if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) {
-                /* Direct I/O, IOMMU off */
-                ppc_md.pci_dma_dev_setup = NULL;
-                ppc_md.pci_dma_bus_setup = NULL;
-                set_pci_dma_ops(&dma_direct_ops);
+        if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
                 return;
-        }
 
         if (firmware_has_feature(FW_FEATURE_LPAR)) {
                 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
@@ -622,3 +601,17 @@ void iommu_init_early_pSeries(void)
         set_pci_dma_ops(&dma_iommu_ops);
 }
 
+static int __init disable_multitce(char *str)
+{
+        if (strcmp(str, "off") == 0 &&
+            firmware_has_feature(FW_FEATURE_LPAR) &&
+            firmware_has_feature(FW_FEATURE_MULTITCE)) {
+                printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
+                ppc_md.tce_build = tce_build_pSeriesLP;
+                ppc_md.tce_free  = tce_free_pSeriesLP;
+                powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
+        }
+        return 1;
+}
+
+__setup("multitce=", disable_multitce);
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index f129040d974c..5d3ea9f60dd7 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -627,6 +627,18 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
                 spin_unlock_irqrestore(&pSeries_lpar_tlbie_lock, flags);
 }
 
+static int __init disable_bulk_remove(char *str)
+{
+        if (strcmp(str, "off") == 0 &&
+            firmware_has_feature(FW_FEATURE_BULK_REMOVE)) {
+                        printk(KERN_INFO "Disabling BULK_REMOVE firmware feature");
+                        powerpc_firmware_features &= ~FW_FEATURE_BULK_REMOVE;
+        }
+        return 1;
+}
+
+__setup("bulk_remove=", disable_bulk_remove);
+
 void __init hpte_init_lpar(void)
 {
         ppc_md.hpte_invalidate  = pSeries_lpar_hpte_invalidate;
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c
index bc3c7f2abd79..7e828ba29bc3 100644
--- a/arch/powerpc/platforms/pseries/nvram.c
+++ b/arch/powerpc/platforms/pseries/nvram.c
@@ -22,11 +22,25 @@
 #include <asm/prom.h>
 #include <asm/machdep.h>
 
+/* Max bytes to read/write in one go */
+#define NVRW_CNT 0x20
+
 static unsigned int nvram_size;
 static int nvram_fetch, nvram_store;
 static char nvram_buf[NVRW_CNT];        /* assume this is in the first 4GB */
 static DEFINE_SPINLOCK(nvram_lock);
 
+static long nvram_error_log_index = -1;
+static long nvram_error_log_size = 0;
+
+struct err_log_info {
+        int error_type;
+        unsigned int seq_num;
+};
+#define NVRAM_MAX_REQ           2079
+#define NVRAM_MIN_REQ           1055
+
+#define NVRAM_LOG_PART_NAME     "ibm,rtas-log"
 
 static ssize_t pSeries_nvram_read(char *buf, size_t count, loff_t *index)
 {
@@ -119,6 +133,197 @@ static ssize_t pSeries_nvram_get_size(void)
         return nvram_size ? nvram_size : -ENODEV;
 }
 
+
+/* nvram_write_error_log
+ *
+ * We need to buffer the error logs into nvram to ensure that we have
+ * the failure information to decode.  If we have a severe error there
+ * is no way to guarantee that the OS or the machine is in a state to
+ * get back to user land and write the error to disk.  For example if
+ * the SCSI device driver causes a Machine Check by writing to a bad
+ * IO address, there is no way of guaranteeing that the device driver
+ * is in any state that is would also be able to write the error data
+ * captured to disk, thus we buffer it in NVRAM for analysis on the
+ * next boot.
+ *
+ * In NVRAM the partition containing the error log buffer will looks like:
+ * Header (in bytes):
+ * +-----------+----------+--------+------------+------------------+
+ * | signature | checksum | length | name       | data             |
+ * |0          |1         |2      3|4         15|16        length-1|
+ * +-----------+----------+--------+------------+------------------+
+ *
+ * The 'data' section would look like (in bytes):
+ * +--------------+------------+-----------------------------------+
+ * | event_logged | sequence # | error log                         |
+ * |0            3|4          7|8            nvram_error_log_size-1|
+ * +--------------+------------+-----------------------------------+
+ *
+ * event_logged: 0 if event has not been logged to syslog, 1 if it has
+ * sequence #: The unique sequence # for each event. (until it wraps)
+ * error log: The error log from event_scan
+ */
+int nvram_write_error_log(char * buff, int length,
+                          unsigned int err_type, unsigned int error_log_cnt)
+{
+        int rc;
+        loff_t tmp_index;
+        struct err_log_info info;
+        
+        if (nvram_error_log_index == -1) {
+                return -ESPIPE;
+        }
+
+        if (length > nvram_error_log_size) {
+                length = nvram_error_log_size;
+        }
+
+        info.error_type = err_type;
+        info.seq_num = error_log_cnt;
+
+        tmp_index = nvram_error_log_index;
+
+        rc = ppc_md.nvram_write((char *)&info, sizeof(struct err_log_info), &tmp_index);
+        if (rc <= 0) {
+                printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc);
+                return rc;
+        }
+
+        rc = ppc_md.nvram_write(buff, length, &tmp_index);
+        if (rc <= 0) {
+                printk(KERN_ERR "nvram_write_error_log: Failed nvram_write (%d)\n", rc);
+                return rc;
+        }
+        
+        return 0;
+}
+
+/* nvram_read_error_log
+ *
+ * Reads nvram for error log for at most 'length'
+ */
+int nvram_read_error_log(char * buff, int length,
+                         unsigned int * err_type, unsigned int * error_log_cnt)
+{
+        int rc;
+        loff_t tmp_index;
+        struct err_log_info info;
+        
+        if (nvram_error_log_index == -1)
+                return -1;
+
+        if (length > nvram_error_log_size)
+                length = nvram_error_log_size;
+
+        tmp_index = nvram_error_log_index;
+
+        rc = ppc_md.nvram_read((char *)&info, sizeof(struct err_log_info), &tmp_index);
+        if (rc <= 0) {
+                printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc);
+                return rc;
+        }
+
+        rc = ppc_md.nvram_read(buff, length, &tmp_index);
+        if (rc <= 0) {
+                printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc);
+                return rc;
+        }
+
+        *error_log_cnt = info.seq_num;
+        *err_type = info.error_type;
+
+        return 0;
+}
+
+/* This doesn't actually zero anything, but it sets the event_logged
+ * word to tell that this event is safely in syslog.
+ */
+int nvram_clear_error_log(void)
+{
+        loff_t tmp_index;
+        int clear_word = ERR_FLAG_ALREADY_LOGGED;
+        int rc;
+
+        if (nvram_error_log_index == -1)
+                return -1;
+
+        tmp_index = nvram_error_log_index;
+        
+        rc = ppc_md.nvram_write((char *)&clear_word, sizeof(int), &tmp_index);
+        if (rc <= 0) {
+                printk(KERN_ERR "nvram_clear_error_log: Failed nvram_write (%d)\n", rc);
+                return rc;
+        }
+
+        return 0;
+}
+
+/* pseries_nvram_init_log_partition
+ *
+ * This will setup the partition we need for buffering the
+ * error logs and cleanup partitions if needed.
+ *
+ * The general strategy is the following:
+ * 1.) If there is log partition large enough then use it.
+ * 2.) If there is none large enough, search
+ * for a free partition that is large enough.
+ * 3.) If there is not a free partition large enough remove 
+ * _all_ OS partitions and consolidate the space.
+ * 4.) Will first try getting a chunk that will satisfy the maximum
+ * error log size (NVRAM_MAX_REQ).
+ * 5.) If the max chunk cannot be allocated then try finding a chunk
+ * that will satisfy the minum needed (NVRAM_MIN_REQ).
+ */
+static int __init pseries_nvram_init_log_partition(void)
+{
+        loff_t p;
+        int size;
+
+        /* Scan nvram for partitions */
+        nvram_scan_partitions();
+
+        /* Lookg for ours */
+        p = nvram_find_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS, &size);
+
+        /* Found one but too small, remove it */
+        if (p && size < NVRAM_MIN_REQ) {
+                pr_info("nvram: Found too small "NVRAM_LOG_PART_NAME" partition"
+                        ",removing it...");
+                nvram_remove_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS);
+                p = 0;
+        }
+
+        /* Create one if we didn't find */
+        if (!p) {
+                p = nvram_create_partition(NVRAM_LOG_PART_NAME, NVRAM_SIG_OS,
+                                           NVRAM_MAX_REQ, NVRAM_MIN_REQ);
+                /* No room for it, try to get rid of any OS partition
+                 * and try again
+                 */
+                if (p == -ENOSPC) {
+                        pr_info("nvram: No room to create "NVRAM_LOG_PART_NAME
+                                " partition, deleting all OS partitions...");
+                        nvram_remove_partition(NULL, NVRAM_SIG_OS);
+                        p = nvram_create_partition(NVRAM_LOG_PART_NAME,
+                                                   NVRAM_SIG_OS, NVRAM_MAX_REQ,
+                                                   NVRAM_MIN_REQ);
+                }
+        }
+
+        if (p <= 0) {
+                pr_err("nvram: Failed to find or create "NVRAM_LOG_PART_NAME
+                       " partition, err %d\n", (int)p);
+                return 0;
+        }
+
+        nvram_error_log_index = p;
+        nvram_error_log_size = nvram_get_partition_size(p) -
+                sizeof(struct err_log_info);
+        
+        return 0;
+}
+machine_arch_initcall(pseries, pseries_nvram_init_log_partition);
+
 int __init pSeries_nvram_init(void)
 {
         struct device_node *nvram;
diff --git a/arch/powerpc/platforms/pseries/pseries_energy.c b/arch/powerpc/platforms/pseries/pseries_energy.c
new file mode 100644
index 000000000000..c8b3c69fe891
--- /dev/null
+++ b/arch/powerpc/platforms/pseries/pseries_energy.c
@@ -0,0 +1,326 @@
+/*
+ * POWER platform energy management driver
+ * Copyright (C) 2010 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This pseries platform device driver provides access to
+ * platform energy management capabilities.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/seq_file.h>
+#include <linux/sysdev.h>
+#include <linux/cpu.h>
+#include <linux/of.h>
+#include <asm/cputhreads.h>
+#include <asm/page.h>
+#include <asm/hvcall.h>
+
+
+#define MODULE_VERS "1.0"
+#define MODULE_NAME "pseries_energy"
+
+/* Driver flags */
+
+static int sysfs_entries;
+
+/* Helper routines */
+
+/*
+ * Routine to detect firmware support for hcall
+ * return 1 if H_BEST_ENERGY is supported
+ * else return 0
+ */
+
+static int check_for_h_best_energy(void)
+{
+        struct device_node *rtas = NULL;
+        const char *hypertas, *s;
+        int length;
+        int rc = 0;
+
+        rtas = of_find_node_by_path("/rtas");
+        if (!rtas)
+                return 0;
+
+        hypertas = of_get_property(rtas, "ibm,hypertas-functions", &length);
+        if (!hypertas) {
+                of_node_put(rtas);
+                return 0;
+        }
+
+        /* hypertas will have list of strings with hcall names */
+        for (s = hypertas; s < hypertas + length; s += strlen(s) + 1) {
+                if (!strncmp("hcall-best-energy-1", s, 19)) {
+                        rc = 1; /* Found the string */
+                        break;
+                }
+        }
+        of_node_put(rtas);
+        return rc;
+}
+
+/* Helper Routines to convert between drc_index to cpu numbers */
+
+static u32 cpu_to_drc_index(int cpu)
+{
+        struct device_node *dn = NULL;
+        const int *indexes;
+        int i;
+        int rc = 1;
+        u32 ret = 0;
+
+        dn = of_find_node_by_path("/cpus");
+        if (dn == NULL)
+                goto err;
+        indexes = of_get_property(dn, "ibm,drc-indexes", NULL);
+        if (indexes == NULL)
+                goto err_of_node_put;
+        /* Convert logical cpu number to core number */
+        i = cpu_core_index_of_thread(cpu);
+        /*
+         * The first element indexes[0] is the number of drc_indexes
+         * returned in the list.  Hence i+1 will get the drc_index
+         * corresponding to core number i.
+         */
+        WARN_ON(i > indexes[0]);
+        ret = indexes[i + 1];
+        rc = 0;
+
+err_of_node_put:
+        of_node_put(dn);
+err:
+        if (rc)
+                printk(KERN_WARNING "cpu_to_drc_index(%d) failed", cpu);
+        return ret;
+}
+
+static int drc_index_to_cpu(u32 drc_index)
+{
+        struct device_node *dn = NULL;
+        const int *indexes;
+        int i, cpu = 0;
+        int rc = 1;
+
+        dn = of_find_node_by_path("/cpus");
+        if (dn == NULL)
+                goto err;
+        indexes = of_get_property(dn, "ibm,drc-indexes", NULL);
+        if (indexes == NULL)
+                goto err_of_node_put;
+        /*
+         * First element in the array is the number of drc_indexes
+         * returned.  Search through the list to find the matching
+         * drc_index and get the core number
+         */
+        for (i = 0; i < indexes[0]; i++) {
+                if (indexes[i + 1] == drc_index)
+                        break;
+        }
+        /* Convert core number to logical cpu number */
+        cpu = cpu_first_thread_of_core(i);
+        rc = 0;
+
+err_of_node_put:
+        of_node_put(dn);
+err:
+        if (rc)
+                printk(KERN_WARNING "drc_index_to_cpu(%d) failed", drc_index);
+        return cpu;
+}
+
+/*
+ * pseries hypervisor call H_BEST_ENERGY provides hints to OS on
+ * preferred logical cpus to activate or deactivate for optimized
+ * energy consumption.
+ */
+
+#define FLAGS_MODE1     0x004E200000080E01
+#define FLAGS_MODE2     0x004E200000080401
+#define FLAGS_ACTIVATE  0x100
+
+static ssize_t get_best_energy_list(char *page, int activate)
+{
+        int rc, cnt, i, cpu;
+        unsigned long retbuf[PLPAR_HCALL9_BUFSIZE];
+        unsigned long flags = 0;
+        u32 *buf_page;
+        char *s = page;
+
+        buf_page = (u32 *) get_zeroed_page(GFP_KERNEL);
+        if (!buf_page)
+                return -ENOMEM;
+
+        flags = FLAGS_MODE1;
+        if (activate)
+                flags |= FLAGS_ACTIVATE;
+
+        rc = plpar_hcall9(H_BEST_ENERGY, retbuf, flags, 0, __pa(buf_page),
+                                0, 0, 0, 0, 0, 0);
+        if (rc != H_SUCCESS) {
+                free_page((unsigned long) buf_page);
+                return -EINVAL;
+        }
+
+        cnt = retbuf[0];
+        for (i = 0; i < cnt; i++) {
+                cpu = drc_index_to_cpu(buf_page[2*i+1]);
+                if ((cpu_online(cpu) && !activate) ||
+                    (!cpu_online(cpu) && activate))
+                        s += sprintf(s, "%d,", cpu);
+        }
+        if (s > page) { /* Something to show */
+                s--; /* Suppress last comma */
+                s += sprintf(s, "\n");
+        }
+
+        free_page((unsigned long) buf_page);
+        return s-page;
+}
+
+static ssize_t get_best_energy_data(struct sys_device *dev,
+                                        char *page, int activate)
+{
+        int rc;
+        unsigned long retbuf[PLPAR_HCALL9_BUFSIZE];
+        unsigned long flags = 0;
+
+        flags = FLAGS_MODE2;
+        if (activate)
+                flags |= FLAGS_ACTIVATE;
+
+        rc = plpar_hcall9(H_BEST_ENERGY, retbuf, flags,
+                                cpu_to_drc_index(dev->id),
+                                0, 0, 0, 0, 0, 0, 0);
+
+        if (rc != H_SUCCESS)
+                return -EINVAL;
+
+        return sprintf(page, "%lu\n", retbuf[1] >> 32);
+}
+
+/* Wrapper functions */
+
+static ssize_t cpu_activate_hint_list_show(struct sysdev_class *class,
+                        struct sysdev_class_attribute *attr, char *page)
+{
+        return get_best_energy_list(page, 1);
+}
+
+static ssize_t cpu_deactivate_hint_list_show(struct sysdev_class *class,
+                        struct sysdev_class_attribute *attr, char *page)
+{
+        return get_best_energy_list(page, 0);
+}
+
+static ssize_t percpu_activate_hint_show(struct sys_device *dev,
+                        struct sysdev_attribute *attr, char *page)
+{
+        return get_best_energy_data(dev, page, 1);
+}
+
+static ssize_t percpu_deactivate_hint_show(struct sys_device *dev,
+                        struct sysdev_attribute *attr, char *page)
+{
+        return get_best_energy_data(dev, page, 0);
+}
+
+/*
+ * Create sysfs interface:
+ * /sys/devices/system/cpu/pseries_activate_hint_list
+ * /sys/devices/system/cpu/pseries_deactivate_hint_list
+ *      Comma separated list of cpus to activate or deactivate
+ * /sys/devices/system/cpu/cpuN/pseries_activate_hint
+ * /sys/devices/system/cpu/cpuN/pseries_deactivate_hint
+ *      Per-cpu value of the hint
+ */
+
+struct sysdev_class_attribute attr_cpu_activate_hint_list =
+                _SYSDEV_CLASS_ATTR(pseries_activate_hint_list, 0444,
+                cpu_activate_hint_list_show, NULL);
+
+struct sysdev_class_attribute attr_cpu_deactivate_hint_list =
+                _SYSDEV_CLASS_ATTR(pseries_deactivate_hint_list, 0444,
+                cpu_deactivate_hint_list_show, NULL);
+
+struct sysdev_attribute attr_percpu_activate_hint =
+                _SYSDEV_ATTR(pseries_activate_hint, 0444,
+                percpu_activate_hint_show, NULL);
+
+struct sysdev_attribute attr_percpu_deactivate_hint =
+                _SYSDEV_ATTR(pseries_deactivate_hint, 0444,
+                percpu_deactivate_hint_show, NULL);
+
+static int __init pseries_energy_init(void)
+{
+        int cpu, err;
+        struct sys_device *cpu_sys_dev;
+
+        if (!check_for_h_best_energy()) {
+                printk(KERN_INFO "Hypercall H_BEST_ENERGY not supported\n");
+                return 0;
+        }
+        /* Create the sysfs files */
+        err = sysfs_create_file(&cpu_sysdev_class.kset.kobj,
+                                &attr_cpu_activate_hint_list.attr);
+        if (!err)
+                err = sysfs_create_file(&cpu_sysdev_class.kset.kobj,
+                                &attr_cpu_deactivate_hint_list.attr);
+
+        if (err)
+                return err;
+        for_each_possible_cpu(cpu) {
+                cpu_sys_dev = get_cpu_sysdev(cpu);
+                err = sysfs_create_file(&cpu_sys_dev->kobj,
+                                &attr_percpu_activate_hint.attr);
+                if (err)
+                        break;
+                err = sysfs_create_file(&cpu_sys_dev->kobj,
+                                &attr_percpu_deactivate_hint.attr);
+                if (err)
+                        break;
+        }
+
+        if (err)
+                return err;
+
+        sysfs_entries = 1; /* Removed entries on cleanup */
+        return 0;
+
+}
+
+static void __exit pseries_energy_cleanup(void)
+{
+        int cpu;
+        struct sys_device *cpu_sys_dev;
+
+        if (!sysfs_entries)
+                return;
+
+        /* Remove the sysfs files */
+        sysfs_remove_file(&cpu_sysdev_class.kset.kobj,
+                                &attr_cpu_activate_hint_list.attr);
+
+        sysfs_remove_file(&cpu_sysdev_class.kset.kobj,
+                                &attr_cpu_deactivate_hint_list.attr);
+
+        for_each_possible_cpu(cpu) {
+                cpu_sys_dev = get_cpu_sysdev(cpu);
+                sysfs_remove_file(&cpu_sys_dev->kobj,
+                                &attr_percpu_activate_hint.attr);
+                sysfs_remove_file(&cpu_sys_dev->kobj,
+                                &attr_percpu_deactivate_hint.attr);
+        }
+}
+
+module_init(pseries_energy_init);
+module_exit(pseries_energy_cleanup);
+MODULE_DESCRIPTION("Driver for pSeries platform energy management");
+MODULE_AUTHOR("Vaidyanathan Srinivasan");
+MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 0bef9dacb64e..9c2973479142 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_OF_RTC)		+= of_rtc.o
 ifeq ($(CONFIG_PCI),y)
 obj-$(CONFIG_4xx)               += ppc4xx_pci.o
 endif
+obj-$(CONFIG_PPC4xx_CPM)        += ppc4xx_cpm.o
 obj-$(CONFIG_PPC4xx_GPIO)       += ppc4xx_gpio.o
 
 obj-$(CONFIG_CPM)               += cpm_common.o
diff --git a/arch/powerpc/sysdev/dart_iommu.c b/arch/powerpc/sysdev/dart_iommu.c
index 17cf15ec38be..8e9e06a7ca59 100644
--- a/arch/powerpc/sysdev/dart_iommu.c
+++ b/arch/powerpc/sysdev/dart_iommu.c
@@ -312,17 +312,10 @@ static void pci_dma_dev_setup_dart(struct pci_dev *dev)
 
 static void pci_dma_bus_setup_dart(struct pci_bus *bus)
 {
-        struct device_node *dn;
-
         if (!iommu_table_dart_inited) {
                 iommu_table_dart_inited = 1;
                 iommu_table_dart_setup();
         }
-
-        dn = pci_bus_to_OF_node(bus);
-
-        if (dn)
-                PCI_DN(dn)->iommu_table = &iommu_table_dart;
 }
 
 static bool dart_device_on_pcie(struct device *dev)
@@ -373,7 +366,7 @@ void __init iommu_init_early_dart(void)
         if (dn == NULL) {
                 dn = of_find_compatible_node(NULL, "dart", "u4-dart");
                 if (dn == NULL)
-                        goto bail;
+                        return; /* use default direct_dma_ops */
                 dart_is_u4 = 1;
         }
 
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
index c0ea05e87f1d..c48cd8178079 100644
--- a/arch/powerpc/sysdev/mpc8xxx_gpio.c
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -1,5 +1,5 @@
 /*
- * GPIOs on MPC8349/8572/8610 and compatible
+ * GPIOs on MPC512x/8349/8572/8610 and compatible
  *
  * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
  *
@@ -26,6 +26,7 @@
 #define GPIO_IER                0x0c
 #define GPIO_IMR                0x10
 #define GPIO_ICR                0x14
+#define GPIO_ICR2               0x18
 
 struct mpc8xxx_gpio_chip {
         struct of_mm_gpio_chip mm_gc;
@@ -37,6 +38,7 @@ struct mpc8xxx_gpio_chip {
          */
         u32 data;
         struct irq_host *irq;
+        void *of_dev_id_data;
 };
 
 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
@@ -215,6 +217,51 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
         return 0;
 }
 
+static int mpc512x_irq_set_type(unsigned int virq, unsigned int flow_type)
+{
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
+        struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+        unsigned long gpio = virq_to_hw(virq);
+        void __iomem *reg;
+        unsigned int shift;
+        unsigned long flags;
+
+        if (gpio < 16) {
+                reg = mm->regs + GPIO_ICR;
+                shift = (15 - gpio) * 2;
+        } else {
+                reg = mm->regs + GPIO_ICR2;
+                shift = (15 - (gpio % 16)) * 2;
+        }
+
+        switch (flow_type) {
+        case IRQ_TYPE_EDGE_FALLING:
+        case IRQ_TYPE_LEVEL_LOW:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                clrsetbits_be32(reg, 3 << shift, 2 << shift);
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        case IRQ_TYPE_EDGE_RISING:
+        case IRQ_TYPE_LEVEL_HIGH:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                clrsetbits_be32(reg, 3 << shift, 1 << shift);
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        case IRQ_TYPE_EDGE_BOTH:
+                spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+                clrbits32(reg, 3 << shift);
+                spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
 static struct irq_chip mpc8xxx_irq_chip = {
         .name           = "mpc8xxx-gpio",
         .unmask         = mpc8xxx_irq_unmask,
@@ -226,6 +273,11 @@ static struct irq_chip mpc8xxx_irq_chip = {
 static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
                                 irq_hw_number_t hw)
 {
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
+
+        if (mpc8xxx_gc->of_dev_id_data)
+                mpc8xxx_irq_chip.set_type = mpc8xxx_gc->of_dev_id_data;
+
         set_irq_chip_data(virq, h->host_data);
         set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
         set_irq_type(virq, IRQ_TYPE_NONE);
@@ -253,11 +305,20 @@ static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
         .xlate  = mpc8xxx_gpio_irq_xlate,
 };
 
+static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
+        { .compatible = "fsl,mpc8349-gpio", },
+        { .compatible = "fsl,mpc8572-gpio", },
+        { .compatible = "fsl,mpc8610-gpio", },
+        { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
+        {}
+};
+
 static void __init mpc8xxx_add_controller(struct device_node *np)
 {
         struct mpc8xxx_gpio_chip *mpc8xxx_gc;
         struct of_mm_gpio_chip *mm_gc;
         struct gpio_chip *gc;
+        const struct of_device_id *id;
         unsigned hwirq;
         int ret;
 
@@ -297,6 +358,10 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
         if (!mpc8xxx_gc->irq)
                 goto skip_irq;
 
+        id = of_match_node(mpc8xxx_gpio_ids, np);
+        if (id)
+                mpc8xxx_gc->of_dev_id_data = id->data;
+
         mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
 
         /* ack and mask all irqs */
@@ -321,13 +386,7 @@ static int __init mpc8xxx_add_gpiochips(void)
 {
         struct device_node *np;
 
-        for_each_compatible_node(np, NULL, "fsl,mpc8349-gpio")
-                mpc8xxx_add_controller(np);
-
-        for_each_compatible_node(np, NULL, "fsl,mpc8572-gpio")
-                mpc8xxx_add_controller(np);
-
-        for_each_compatible_node(np, NULL, "fsl,mpc8610-gpio")
+        for_each_matching_node(np, mpc8xxx_gpio_ids)
                 mpc8xxx_add_controller(np);
 
         for_each_compatible_node(np, NULL, "fsl,qoriq-gpio")
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index 1398bc454999..feaee402e2d6 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -16,6 +16,7 @@
 #include <linux/mv643xx.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
+#include <linux/of_net.h>
 #include <linux/dma-mapping.h>
 
 #include <asm/prom.h>
diff --git a/arch/powerpc/sysdev/ppc4xx_cpm.c b/arch/powerpc/sysdev/ppc4xx_cpm.c
new file mode 100644
index 000000000000..73b86cc5ea74
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_cpm.c
@@ -0,0 +1,346 @@
+/*
+ * PowerPC 4xx Clock and Power Management
+ *
+ * Copyright (C) 2010, Applied Micro Circuits Corporation
+ * Victor Gallardo (vgallardo@apm.com)
+ *
+ * Based on arch/powerpc/platforms/44x/idle.c:
+ * Jerone Young <jyoung5@us.ibm.com>
+ * Copyright 2008 IBM Corp.
+ *
+ * Based on arch/powerpc/sysdev/fsl_pmc.c:
+ * Anton Vorontsov <avorontsov@ru.mvista.com>
+ * Copyright 2009  MontaVista Software, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+#include <linux/sysfs.h>
+#include <linux/cpu.h>
+#include <linux/suspend.h>
+#include <asm/dcr.h>
+#include <asm/dcr-native.h>
+#include <asm/machdep.h>
+
+#define CPM_ER  0
+#define CPM_FR  1
+#define CPM_SR  2
+
+#define CPM_IDLE_WAIT   0
+#define CPM_IDLE_DOZE   1
+
+struct cpm {
+        dcr_host_t      dcr_host;
+        unsigned int    dcr_offset[3];
+        unsigned int    powersave_off;
+        unsigned int    unused;
+        unsigned int    idle_doze;
+        unsigned int    standby;
+        unsigned int    suspend;
+};
+
+static struct cpm cpm;
+
+struct cpm_idle_mode {
+        unsigned int enabled;
+        const char  *name;
+};
+
+static struct cpm_idle_mode idle_mode[] = {
+        [CPM_IDLE_WAIT] = { 1, "wait" }, /* default */
+        [CPM_IDLE_DOZE] = { 0, "doze" },
+};
+
+static unsigned int cpm_set(unsigned int cpm_reg, unsigned int mask)
+{
+        unsigned int value;
+
+        /* CPM controller supports 3 different types of sleep interface
+         * known as class 1, 2 and 3. For class 1 units, they are
+         * unconditionally put to sleep when the corresponding CPM bit is
+         * set. For class 2 and 3 units this is not case; if they can be
+         * put to to sleep, they will. Here we do not verify, we just
+         * set them and expect them to eventually go off when they can.
+         */
+        value = dcr_read(cpm.dcr_host, cpm.dcr_offset[cpm_reg]);
+        dcr_write(cpm.dcr_host, cpm.dcr_offset[cpm_reg], value | mask);
+
+        /* return old state, to restore later if needed */
+        return value;
+}
+
+static void cpm_idle_wait(void)
+{
+        unsigned long msr_save;
+
+        /* save off initial state */
+        msr_save = mfmsr();
+        /* sync required when CPM0_ER[CPU] is set */
+        mb();
+        /* set wait state MSR */
+        mtmsr(msr_save|MSR_WE|MSR_EE|MSR_CE|MSR_DE);
+        isync();
+        /* return to initial state */
+        mtmsr(msr_save);
+        isync();
+}
+
+static void cpm_idle_sleep(unsigned int mask)
+{
+        unsigned int er_save;
+
+        /* update CPM_ER state */
+        er_save = cpm_set(CPM_ER, mask);
+
+        /* go to wait state so that CPM0_ER[CPU] can take effect */
+        cpm_idle_wait();
+
+        /* restore CPM_ER state */
+        dcr_write(cpm.dcr_host, cpm.dcr_offset[CPM_ER], er_save);
+}
+
+static void cpm_idle_doze(void)
+{
+        cpm_idle_sleep(cpm.idle_doze);
+}
+
+static void cpm_idle_config(int mode)
+{
+        int i;
+
+        if (idle_mode[mode].enabled)
+                return;
+
+        for (i = 0; i < ARRAY_SIZE(idle_mode); i++)
+                idle_mode[i].enabled = 0;
+
+        idle_mode[mode].enabled = 1;
+}
+
+static ssize_t cpm_idle_show(struct kobject *kobj,
+                             struct kobj_attribute *attr, char *buf)
+{
+        char *s = buf;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(idle_mode); i++) {
+                if (idle_mode[i].enabled)
+                        s += sprintf(s, "[%s] ", idle_mode[i].name);
+                else
+                        s += sprintf(s, "%s ", idle_mode[i].name);
+        }
+
+        *(s-1) = '\n'; /* convert the last space to a newline */
+
+        return s - buf;
+}
+
+static ssize_t cpm_idle_store(struct kobject *kobj,
+                              struct kobj_attribute *attr,
+                              const char *buf, size_t n)
+{
+        int i;
+        char *p;
+        int len;
+
+        p = memchr(buf, '\n', n);
+        len = p ? p - buf : n;
+
+        for (i = 0; i < ARRAY_SIZE(idle_mode); i++) {
+                if (strncmp(buf, idle_mode[i].name, len) == 0) {
+                        cpm_idle_config(i);
+                        return n;
+                }
+        }
+
+        return -EINVAL;
+}
+
+static struct kobj_attribute cpm_idle_attr =
+        __ATTR(idle, 0644, cpm_idle_show, cpm_idle_store);
+
+static void cpm_idle_config_sysfs(void)
+{
+        struct sys_device *sys_dev;
+        unsigned long ret;
+
+        sys_dev = get_cpu_sysdev(0);
+
+        ret = sysfs_create_file(&sys_dev->kobj,
+                                &cpm_idle_attr.attr);
+        if (ret)
+                printk(KERN_WARNING
+                       "cpm: failed to create idle sysfs entry\n");
+}
+
+static void cpm_idle(void)
+{
+        if (idle_mode[CPM_IDLE_DOZE].enabled)
+                cpm_idle_doze();
+        else
+                cpm_idle_wait();
+}
+
+static int cpm_suspend_valid(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_STANDBY:
+                return !!cpm.standby;
+        case PM_SUSPEND_MEM:
+                return !!cpm.suspend;
+        default:
+                return 0;
+        }
+}
+
+static void cpm_suspend_standby(unsigned int mask)
+{
+        unsigned long tcr_save;
+
+        /* disable decrement interrupt */
+        tcr_save = mfspr(SPRN_TCR);
+        mtspr(SPRN_TCR, tcr_save & ~TCR_DIE);
+
+        /* go to sleep state */
+        cpm_idle_sleep(mask);
+
+        /* restore decrement interrupt */
+        mtspr(SPRN_TCR, tcr_save);
+}
+
+static int cpm_suspend_enter(suspend_state_t state)
+{
+        switch (state) {
+        case PM_SUSPEND_STANDBY:
+                cpm_suspend_standby(cpm.standby);
+                break;
+        case PM_SUSPEND_MEM:
+                cpm_suspend_standby(cpm.suspend);
+                break;
+        }
+
+        return 0;
+}
+
+static struct platform_suspend_ops cpm_suspend_ops = {
+        .valid          = cpm_suspend_valid,
+        .enter          = cpm_suspend_enter,
+};
+
+static int cpm_get_uint_property(struct device_node *np,
+                                 const char *name)
+{
+        int len;
+        const unsigned int *prop = of_get_property(np, name, &len);
+
+        if (prop == NULL || len < sizeof(u32))
+                return 0;
+
+        return *prop;
+}
+
+static int __init cpm_init(void)
+{
+        struct device_node *np;
+        int dcr_base, dcr_len;
+        int ret = 0;
+
+        if (!cpm.powersave_off) {
+                cpm_idle_config(CPM_IDLE_WAIT);
+                ppc_md.power_save = &cpm_idle;
+        }
+
+        np = of_find_compatible_node(NULL, NULL, "ibm,cpm");
+        if (!np) {
+                ret = -EINVAL;
+                goto out;
+        }
+
+        dcr_base = dcr_resource_start(np, 0);
+        dcr_len = dcr_resource_len(np, 0);
+
+        if (dcr_base == 0 || dcr_len == 0) {
+                printk(KERN_ERR "cpm: could not parse dcr property for %s\n",
+                       np->full_name);
+                ret = -EINVAL;
+                goto out;
+        }
+
+        cpm.dcr_host = dcr_map(np, dcr_base, dcr_len);
+
+        if (!DCR_MAP_OK(cpm.dcr_host)) {
+                printk(KERN_ERR "cpm: failed to map dcr property for %s\n",
+                       np->full_name);
+                ret = -EINVAL;
+                goto out;
+        }
+
+        /* All 4xx SoCs with a CPM controller have one of two
+         * different order for the CPM registers. Some have the
+         * CPM registers in the following order (ER,FR,SR). The
+         * others have them in the following order (SR,ER,FR).
+         */
+
+        if (cpm_get_uint_property(np, "er-offset") == 0) {
+                cpm.dcr_offset[CPM_ER] = 0;
+                cpm.dcr_offset[CPM_FR] = 1;
+                cpm.dcr_offset[CPM_SR] = 2;
+        } else {
+                cpm.dcr_offset[CPM_ER] = 1;
+                cpm.dcr_offset[CPM_FR] = 2;
+                cpm.dcr_offset[CPM_SR] = 0;
+        }
+
+        /* Now let's see what IPs to turn off for the following modes */
+
+        cpm.unused = cpm_get_uint_property(np, "unused-units");
+        cpm.idle_doze = cpm_get_uint_property(np, "idle-doze");
+        cpm.standby = cpm_get_uint_property(np, "standby");
+        cpm.suspend = cpm_get_uint_property(np, "suspend");
+
+        /* If some IPs are unused let's turn them off now */
+
+        if (cpm.unused) {
+                cpm_set(CPM_ER, cpm.unused);
+                cpm_set(CPM_FR, cpm.unused);
+        }
+
+        /* Now let's export interfaces */
+
+        if (!cpm.powersave_off && cpm.idle_doze)
+                cpm_idle_config_sysfs();
+
+        if (cpm.standby || cpm.suspend)
+                suspend_set_ops(&cpm_suspend_ops);
+out:
+        if (np)
+                of_node_put(np);
+        return ret;
+}
+
+late_initcall(cpm_init);
+
+static int __init cpm_powersave_off(char *arg)
+{
+        cpm.powersave_off = 1;
+        return 0;
+}
+__setup("powersave=off", cpm_powersave_off);
diff --git a/arch/powerpc/sysdev/tsi108_dev.c b/arch/powerpc/sysdev/tsi108_dev.c
index d4d15aaf18fa..ee056807b52c 100644
--- a/arch/powerpc/sysdev/tsi108_dev.c
+++ b/arch/powerpc/sysdev/tsi108_dev.c
@@ -19,6 +19,7 @@
 #include <linux/module.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
+#include <linux/of_net.h>
 #include <asm/tsi108.h>
 
 #include <asm/system.h>
@@ -83,8 +84,8 @@ static int __init tsi108_eth_of_init(void)
                 memset(&tsi_eth_data, 0, sizeof(tsi_eth_data));
 
                 ret = of_address_to_resource(np, 0, &r[0]);
-                DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
-                        __func__,r[0].name, r[0].start, r[0].end);
+                DBG("%s: name:start->end = %s:%pR\n",
+                    __func__, r[0].name, &r[0]);
                 if (ret)
                         goto err;
 
@@ -92,8 +93,8 @@ static int __init tsi108_eth_of_init(void)
                 r[1].start = irq_of_parse_and_map(np, 0);
                 r[1].end = irq_of_parse_and_map(np, 0);
                 r[1].flags = IORESOURCE_IRQ;
-                DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
-                        __func__,r[1].name, r[1].start, r[1].end);
+                DBG("%s: name:start->end = %s:%pR\n",
+                        __func__, r[1].name, &r[1]);
 
                 tsi_eth_dev =
                     platform_device_register_simple("tsi-ethernet", i++, &r[0],
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index e0b98e71ff47..ff19efdf6fef 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -1,13 +1,8 @@
-config SCHED_MC
-        def_bool y
-        depends on SMP
-
 config MMU
         def_bool y
 
 config ZONE_DMA
-        def_bool y
-        depends on 64BIT
+        def_bool y if 64BIT
 
 config LOCKDEP_SUPPORT
         def_bool y
@@ -25,12 +20,10 @@ config RWSEM_XCHGADD_ALGORITHM
         def_bool y
 
 config ARCH_HAS_ILOG2_U32
-        bool
-        default n
+        def_bool n
 
 config ARCH_HAS_ILOG2_U64
-        bool
-        default n
+        def_bool n
 
 config GENERIC_HWEIGHT
         def_bool y
@@ -42,9 +35,7 @@ config GENERIC_CLOCKEVENTS
         def_bool y
 
 config GENERIC_BUG
-        bool
-        depends on BUG
-        default y
+        def_bool y if BUG
 
 config GENERIC_BUG_RELATIVE_POINTERS
         def_bool y
@@ -59,13 +50,10 @@ config ARCH_DMA_ADDR_T_64BIT
         def_bool 64BIT
 
 config GENERIC_LOCKBREAK
-        bool
-        default y
-        depends on SMP && PREEMPT
+        def_bool y if SMP && PREEMPT
 
 config PGSTE
-        bool
-        default y if KVM
+        def_bool y if KVM
 
 config VIRT_CPU_ACCOUNTING
         def_bool y
@@ -85,7 +73,6 @@ config S390
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FUNCTION_GRAPH_TRACER
         select HAVE_REGS_AND_STACK_ACCESS_API
-        select HAVE_DEFAULT_NO_SPIN_MUTEXES
         select HAVE_OPROFILE
         select HAVE_KPROBES
         select HAVE_KRETPROBES
@@ -99,6 +86,7 @@ config S390
         select HAVE_KERNEL_LZMA
         select HAVE_KERNEL_LZO
         select HAVE_GET_USER_PAGES_FAST
+        select HAVE_ARCH_MUTEX_CPU_RELAX
         select ARCH_INLINE_SPIN_TRYLOCK
         select ARCH_INLINE_SPIN_TRYLOCK_BH
         select ARCH_INLINE_SPIN_LOCK
@@ -129,8 +117,7 @@ config S390
         select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE
 
 config SCHED_OMIT_FRAME_POINTER
-        bool
-        default y
+        def_bool y
 
 source "init/Kconfig"
 
@@ -143,20 +130,21 @@ comment "Processor type and features"
 source "kernel/time/Kconfig"
 
 config 64BIT
-        bool "64 bit kernel"
+        def_bool y
+        prompt "64 bit kernel"
         help
           Select this option if you have an IBM z/Architecture machine
           and want to use the 64 bit addressing mode.
 
 config 32BIT
-        bool
-        default y if !64BIT
+        def_bool y if !64BIT
 
 config KTIME_SCALAR
         def_bool 32BIT
 
 config SMP
-        bool "Symmetric multi-processing support"
+        def_bool y
+        prompt "Symmetric multi-processing support"
         ---help---
           This enables support for systems with more than one CPU. If you have
           a system with only one CPU, like most personal computers, say N. If
@@ -188,10 +176,10 @@ config NR_CPUS
           approximately sixteen kilobytes to the kernel image.
 
 config HOTPLUG_CPU
-        bool "Support for hot-pluggable CPUs"
+        def_bool y
+        prompt "Support for hot-pluggable CPUs"
         depends on SMP
         select HOTPLUG
-        default n
         help
           Say Y here to be able to turn CPUs off and on. CPUs
           can be controlled through /sys/devices/system/cpu/cpu#.
@@ -207,14 +195,16 @@ config SCHED_MC
           increased overhead in some places.
 
 config SCHED_BOOK
-        bool "Book scheduler support"
+        def_bool y
+        prompt "Book scheduler support"
         depends on SMP && SCHED_MC
         help
           Book scheduler support improves the CPU scheduler's decision making
           when dealing with machines that have several books.
 
 config MATHEMU
-        bool "IEEE FPU emulation"
+        def_bool y
+        prompt "IEEE FPU emulation"
         depends on MARCH_G5
         help
           This option is required for IEEE compliant floating point arithmetic
@@ -222,7 +212,8 @@ config MATHEMU
           need this.
 
 config COMPAT
-        bool "Kernel support for 31 bit emulation"
+        def_bool y
+        prompt "Kernel support for 31 bit emulation"
         depends on 64BIT
         select COMPAT_BINFMT_ELF
         help
@@ -232,16 +223,14 @@ config COMPAT
           executing 31 bit applications.  It is safe to say "Y".
 
 config SYSVIPC_COMPAT
-        bool
-        depends on COMPAT && SYSVIPC
-        default y
+        def_bool y if COMPAT && SYSVIPC
 
 config AUDIT_ARCH
-        bool
-        default y
+        def_bool y
 
 config S390_EXEC_PROTECT
-        bool "Data execute protection"
+        def_bool y
+        prompt "Data execute protection"
         help
           This option allows to enable a buffer overflow protection for user
           space programs and it also selects the addressing mode option above.
@@ -301,7 +290,8 @@ config MARCH_Z196
 endchoice
 
 config PACK_STACK
-        bool "Pack kernel stack"
+        def_bool y
+        prompt "Pack kernel stack"
         help
           This option enables the compiler option -mkernel-backchain if it
           is available. If the option is available the compiler supports
@@ -314,7 +304,8 @@ config PACK_STACK
           Say Y if you are unsure.
 
 config SMALL_STACK
-        bool "Use 8kb for kernel stack instead of 16kb"
+        def_bool n
+        prompt "Use 8kb for kernel stack instead of 16kb"
         depends on PACK_STACK && 64BIT && !LOCKDEP
         help
           If you say Y here and the compiler supports the -mkernel-backchain
@@ -326,7 +317,8 @@ config SMALL_STACK
           Say N if you are unsure.
 
 config CHECK_STACK
-        bool "Detect kernel stack overflow"
+        def_bool y
+        prompt "Detect kernel stack overflow"
         help
           This option enables the compiler option -mstack-guard and
           -mstack-size if they are available. If the compiler supports them
@@ -350,7 +342,8 @@ config STACK_GUARD
           512 for 64 bit.
 
 config WARN_STACK
-        bool "Emit compiler warnings for function with broken stack usage"
+        def_bool n
+        prompt "Emit compiler warnings for function with broken stack usage"
         help
           This option enables the compiler options -mwarn-framesize and
           -mwarn-dynamicstack. If the compiler supports these options it
@@ -385,24 +378,24 @@ config ARCH_SPARSEMEM_DEFAULT
         def_bool y
 
 config ARCH_SELECT_MEMORY_MODEL
-       def_bool y
+        def_bool y
 
 config ARCH_ENABLE_MEMORY_HOTPLUG
-        def_bool y
-        depends on SPARSEMEM
+        def_bool y if SPARSEMEM
 
 config ARCH_ENABLE_MEMORY_HOTREMOVE
         def_bool y
 
 config ARCH_HIBERNATION_POSSIBLE
-       def_bool y if 64BIT
+        def_bool y if 64BIT
 
 source "mm/Kconfig"
 
 comment "I/O subsystem configuration"
 
 config QDIO
-        tristate "QDIO support"
+        def_tristate y
+        prompt "QDIO support"
         ---help---
           This driver provides the Queued Direct I/O base support for
           IBM System z.
@@ -413,7 +406,8 @@ config QDIO
           If unsure, say Y.
 
 config CHSC_SCH
-        tristate "Support for CHSC subchannels"
+        def_tristate y
+        prompt "Support for CHSC subchannels"
         help
           This driver allows usage of CHSC subchannels. A CHSC subchannel
           is usually present on LPAR only.
@@ -431,7 +425,8 @@ config CHSC_SCH
 comment "Misc"
 
 config IPL
-        bool "Builtin IPL record support"
+        def_bool y
+        prompt "Builtin IPL record support"
         help
           If you want to use the produced kernel to IPL directly from a
           device, you have to merge a bootsector specific to the device
@@ -463,7 +458,8 @@ config FORCE_MAX_ZONEORDER
         default "9"
 
 config PFAULT
-        bool "Pseudo page fault support"
+        def_bool y
+        prompt "Pseudo page fault support"
         help
           Select this option, if you want to use PFAULT pseudo page fault
           handling under VM. If running native or in LPAR, this option
@@ -475,7 +471,8 @@ config PFAULT
           this option.
 
 config SHARED_KERNEL
-        bool "VM shared kernel support"
+        def_bool y
+        prompt "VM shared kernel support"
         help
           Select this option, if you want to share the text segment of the
           Linux kernel between different VM guests. This reduces memory
@@ -486,7 +483,8 @@ config SHARED_KERNEL
           doing and want to exploit this feature.
 
 config CMM
-        tristate "Cooperative memory management"
+        def_tristate n
+        prompt "Cooperative memory management"
         help
           Select this option, if you want to enable the kernel interface
           to reduce the memory size of the system. This is accomplished
@@ -498,14 +496,16 @@ config CMM
           option.
 
 config CMM_IUCV
-        bool "IUCV special message interface to cooperative memory management"
+        def_bool y
+        prompt "IUCV special message interface to cooperative memory management"
         depends on CMM && (SMSGIUCV=y || CMM=SMSGIUCV)
         help
           Select this option to enable the special message interface to
           the cooperative memory management.
 
 config APPLDATA_BASE
-        bool "Linux - VM Monitor Stream, base infrastructure"
+        def_bool n
+        prompt "Linux - VM Monitor Stream, base infrastructure"
         depends on PROC_FS
         help
           This provides a kernel interface for creating and updating z/VM APPLDATA
@@ -520,7 +520,8 @@ config APPLDATA_BASE
           The /proc entries can also be read from, showing the current settings.
 
 config APPLDATA_MEM
-        tristate "Monitor memory management statistics"
+        def_tristate m
+        prompt "Monitor memory management statistics"
         depends on APPLDATA_BASE && VM_EVENT_COUNTERS
         help
           This provides memory management related data to the Linux - VM Monitor
@@ -536,7 +537,8 @@ config APPLDATA_MEM
           appldata_mem.o.
 
 config APPLDATA_OS
-        tristate "Monitor OS statistics"
+        def_tristate m
+        prompt "Monitor OS statistics"
         depends on APPLDATA_BASE
         help
           This provides OS related data to the Linux - VM Monitor Stream, like
@@ -550,7 +552,8 @@ config APPLDATA_OS
           appldata_os.o.
 
 config APPLDATA_NET_SUM
-        tristate "Monitor overall network statistics"
+        def_tristate m
+        prompt "Monitor overall network statistics"
         depends on APPLDATA_BASE && NET
         help
           This provides network related data to the Linux - VM Monitor Stream,
@@ -567,30 +570,32 @@ config APPLDATA_NET_SUM
 source kernel/Kconfig.hz
 
 config S390_HYPFS_FS
-        bool "s390 hypervisor file system support"
+        def_bool y
+        prompt "s390 hypervisor file system support"
         select SYS_HYPERVISOR
-        default y
         help
           This is a virtual file system intended to provide accounting
           information in an s390 hypervisor environment.
 
 config KEXEC
-        bool "kexec system call"
+        def_bool n
+        prompt "kexec system call"
         help
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
           but is independent of hardware/microcode support.
 
 config ZFCPDUMP
-        bool "zfcpdump support"
+        def_bool n
+        prompt "zfcpdump support"
         select SMP
-        default n
         help
           Select this option if you want to build an zfcpdump enabled kernel.
           Refer to <file:Documentation/s390/zfcpdump.txt> for more details on this.
 
 config S390_GUEST
-bool "s390 guest support for KVM (EXPERIMENTAL)"
+        def_bool y
+        prompt "s390 guest support for KVM (EXPERIMENTAL)"
         depends on 64BIT && EXPERIMENTAL
         select VIRTIO
         select VIRTIO_RING
@@ -602,9 +607,9 @@ bool "s390 guest support for KVM (EXPERIMENTAL)"
           the default console.
 
 config SECCOMP
-        bool "Enable seccomp to safely compute untrusted bytecode"
+        def_bool y
+        prompt "Enable seccomp to safely compute untrusted bytecode"
         depends on PROC_FS
-        default y
         help
           This kernel feature is useful for number crunching applications
           that may need to compute untrusted bytecode during their
diff --git a/arch/s390/Kconfig.debug b/arch/s390/Kconfig.debug
index 05221b13ffb1..2b380df95606 100644
--- a/arch/s390/Kconfig.debug
+++ b/arch/s390/Kconfig.debug
@@ -1,8 +1,7 @@
 menu "Kernel hacking"
 
 config TRACE_IRQFLAGS_SUPPORT
-        bool
-        default y
+        def_bool y
 
 source "lib/Kconfig.debug"
 
@@ -19,7 +18,8 @@ config STRICT_DEVMEM
           If you are unsure, say Y.
 
 config DEBUG_STRICT_USER_COPY_CHECKS
-        bool "Strict user copy size checks"
+        def_bool n
+        prompt "Strict user copy size checks"
         ---help---
           Enabling this option turns a certain set of sanity checks for user
           copy operations into compile time warnings.
diff --git a/arch/s390/defconfig b/arch/s390/defconfig
index e40ac6ee6526..d79697157ac0 100644
--- a/arch/s390/defconfig
+++ b/arch/s390/defconfig
@@ -2,16 +2,12 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_AUDIT=y
+CONFIG_RCU_TRACE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_NS=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_UTS_NS=y
-CONFIG_IPC_NS=y
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-# CONFIG_COMPAT_BRK is not set
+CONFIG_PERF_EVENTS=y
 CONFIG_SLAB=y
 CONFIG_KPROBES=y
 CONFIG_MODULES=y
@@ -20,24 +16,12 @@ CONFIG_MODVERSIONS=y
 CONFIG_DEFAULT_DEADLINE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
-CONFIG_64BIT=y
-CONFIG_SMP=y
-CONFIG_NR_CPUS=32
-CONFIG_COMPAT=y
-CONFIG_S390_EXEC_PROTECT=y
-CONFIG_PACK_STACK=y
-CONFIG_CHECK_STACK=y
 CONFIG_PREEMPT=y
 CONFIG_MEMORY_HOTPLUG=y
 CONFIG_MEMORY_HOTREMOVE=y
-CONFIG_QDIO=y
-CONFIG_CHSC_SCH=m
-CONFIG_IPL=y
 CONFIG_BINFMT_MISC=m
-CONFIG_PFAULT=y
 CONFIG_HZ_100=y
 CONFIG_KEXEC=y
-CONFIG_S390_GUEST=y
 CONFIG_PM=y
 CONFIG_HIBERNATION=y
 CONFIG_PACKET=y
@@ -46,16 +30,15 @@ CONFIG_NET_KEY=y
 CONFIG_AFIUCV=m
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
+# CONFIG_INET_LRO is not set
 CONFIG_IPV6=y
-CONFIG_NETFILTER=y
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK=m
-# CONFIG_NF_CT_PROTO_SCTP is not set
+CONFIG_NET_SCTPPROBE=m
+CONFIG_L2TP=m
+CONFIG_L2TP_DEBUGFS=m
+CONFIG_VLAN_8021Q=y
 CONFIG_NET_SCHED=y
 CONFIG_NET_SCH_CBQ=m
 CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_MULTIQ=y
 CONFIG_NET_SCH_RED=m
 CONFIG_NET_SCH_SFQ=m
 CONFIG_NET_SCH_TEQL=m
@@ -69,28 +52,14 @@ CONFIG_NET_CLS_U32=m
 CONFIG_CLS_U32_MARK=y
 CONFIG_NET_CLS_RSVP=m
 CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_CLS_FLOW=m
 CONFIG_NET_CLS_ACT=y
 CONFIG_NET_ACT_POLICE=y
-CONFIG_NET_ACT_NAT=m
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_VCAN=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_NBD=m
 CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_XIP=y
-CONFIG_BLK_DEV_XPRAM=m
-CONFIG_DASD=y
-CONFIG_DASD_PROFILE=y
-CONFIG_DASD_ECKD=y
-CONFIG_DASD_FBA=y
-CONFIG_DASD_DIAG=y
-CONFIG_DASD_EER=y
-CONFIG_VIRTIO_BLK=m
+CONFIG_VIRTIO_BLK=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=y
@@ -102,101 +71,92 @@ CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_ZFCP=y
-CONFIG_SCSI_DH=m
-CONFIG_SCSI_DH_RDAC=m
-CONFIG_SCSI_DH_HP_SW=m
-CONFIG_SCSI_DH_EMC=m
-CONFIG_SCSI_DH_ALUA=m
-CONFIG_SCSI_OSD_INITIATOR=m
-CONFIG_SCSI_OSD_ULD=m
-CONFIG_MD=y
-CONFIG_BLK_DEV_MD=y
-CONFIG_MD_LINEAR=m
-CONFIG_MD_RAID0=m
-CONFIG_MD_RAID1=m
-CONFIG_MD_MULTIPATH=m
-CONFIG_BLK_DEV_DM=y
-CONFIG_DM_CRYPT=y
-CONFIG_DM_SNAPSHOT=y
-CONFIG_DM_MIRROR=y
-CONFIG_DM_ZERO=y
-CONFIG_DM_MULTIPATH=m
+CONFIG_ZFCP_DIF=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=m
 CONFIG_BONDING=m
 CONFIG_EQUALIZER=m
 CONFIG_TUN=m
-CONFIG_VETH=m
 CONFIG_NET_ETHERNET=y
-CONFIG_LCS=m
-CONFIG_CTCM=m
-CONFIG_QETH=y
-CONFIG_QETH_L2=y
-CONFIG_QETH_L3=y
-CONFIG_VIRTIO_NET=m
-CONFIG_HW_RANDOM_VIRTIO=m
+CONFIG_VIRTIO_NET=y
 CONFIG_RAW_DRIVER=m
-CONFIG_TN3270=y
-CONFIG_TN3270_TTY=y
-CONFIG_TN3270_FS=m
-CONFIG_TN3270_CONSOLE=y
-CONFIG_TN3215=y
-CONFIG_TN3215_CONSOLE=y
-CONFIG_SCLP_TTY=y
-CONFIG_SCLP_CONSOLE=y
-CONFIG_SCLP_VT220_TTY=y
-CONFIG_SCLP_VT220_CONSOLE=y
-CONFIG_SCLP_CPI=m
-CONFIG_SCLP_ASYNC=m
-CONFIG_S390_TAPE=m
-CONFIG_S390_TAPE_BLOCK=y
-CONFIG_S390_TAPE_34XX=m
-CONFIG_ACCESSIBILITY=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFSD=y
-CONFIG_NFSD_V3=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_IBM_PARTITION=y
 CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
+CONFIG_TIMER_STATS=y
+CONFIG_PROVE_LOCKING=y
+CONFIG_PROVE_RCU=y
+CONFIG_LOCK_STAT=y
+CONFIG_DEBUG_LOCKDEP=y
 CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_DEBUG_LIST=y
+CONFIG_DEBUG_NOTIFIERS=y
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
+CONFIG_KPROBES_SANITY_TEST=y
+CONFIG_CPU_NOTIFIER_ERROR_INJECT=m
+CONFIG_LATENCYTOP=y
 CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_SAMPLES=y
-CONFIG_CRYPTO_FIPS=y
+CONFIG_DEBUG_PAGEALLOC=y
+# CONFIG_FTRACE is not set
+# CONFIG_STRICT_DEVMEM is not set
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
 CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_CCM=m
 CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CBC=y
 CONFIG_CRYPTO_CTS=m
 CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_LRW=m
 CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_XCBC=m
 CONFIG_CRYPTO_VMAC=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_RMD128=m
 CONFIG_CRYPTO_RMD160=m
 CONFIG_CRYPTO_RMD256=m
 CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=m
 CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_SALSA20=m
 CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_DEFLATE=m
 CONFIG_CRYPTO_ZLIB=m
 CONFIG_CRYPTO_LZO=m
 CONFIG_ZCRYPT=m
+CONFIG_CRYPTO_SHA1_S390=m
+CONFIG_CRYPTO_SHA256_S390=m
 CONFIG_CRYPTO_SHA512_S390=m
-CONFIG_CRC_T10DIF=y
-CONFIG_CRC32=m
+CONFIG_CRYPTO_DES_S390=m
+CONFIG_CRYPTO_AES_S390=m
 CONFIG_CRC7=m
-CONFIG_KVM=m
-CONFIG_VIRTIO_BALLOON=m
+CONFIG_VIRTIO_BALLOON=y
diff --git a/arch/s390/hypfs/Makefile b/arch/s390/hypfs/Makefile
index b08d2abf6178..2e671d5004ca 100644
--- a/arch/s390/hypfs/Makefile
+++ b/arch/s390/hypfs/Makefile
@@ -4,4 +4,4 @@
 
 obj-$(CONFIG_S390_HYPFS_FS) += s390_hypfs.o
 
-s390_hypfs-objs := inode.o hypfs_diag.o hypfs_vm.o
+s390_hypfs-objs := inode.o hypfs_diag.o hypfs_vm.o hypfs_dbfs.o
diff --git a/arch/s390/hypfs/hypfs.h b/arch/s390/hypfs/hypfs.h
index fa487d4cc08b..80c1526f2af3 100644
--- a/arch/s390/hypfs/hypfs.h
+++ b/arch/s390/hypfs/hypfs.h
@@ -12,6 +12,8 @@
 #include <linux/fs.h>
 #include <linux/types.h>
 #include <linux/debugfs.h>
+#include <linux/workqueue.h>
+#include <linux/kref.h>
 
 #define REG_FILE_MODE    0440
 #define UPDATE_FILE_MODE 0220
@@ -38,6 +40,33 @@ extern int hypfs_vm_init(void);
 extern void hypfs_vm_exit(void);
 extern int hypfs_vm_create_files(struct super_block *sb, struct dentry *root);
 
-/* Directory for debugfs files */
-extern struct dentry *hypfs_dbfs_dir;
+/* debugfs interface */
+struct hypfs_dbfs_file;
+
+struct hypfs_dbfs_data {
+        void                    *buf;
+        void                    *buf_free_ptr;
+        size_t                  size;
+        struct hypfs_dbfs_file  *dbfs_file;;
+        struct kref             kref;
+};
+
+struct hypfs_dbfs_file {
+        const char      *name;
+        int             (*data_create)(void **data, void **data_free_ptr,
+                                       size_t *size);
+        void            (*data_free)(const void *buf_free_ptr);
+
+        /* Private data for hypfs_dbfs.c */
+        struct hypfs_dbfs_data  *data;
+        struct delayed_work     data_free_work;
+        struct mutex            lock;
+        struct dentry           *dentry;
+};
+
+extern int hypfs_dbfs_init(void);
+extern void hypfs_dbfs_exit(void);
+extern int hypfs_dbfs_create_file(struct hypfs_dbfs_file *df);
+extern void hypfs_dbfs_remove_file(struct hypfs_dbfs_file *df);
+
 #endif /* _HYPFS_H_ */
diff --git a/arch/s390/hypfs/hypfs_dbfs.c b/arch/s390/hypfs/hypfs_dbfs.c
new file mode 100644
index 000000000000..b478013b7fec
--- /dev/null
+++ b/arch/s390/hypfs/hypfs_dbfs.c
@@ -0,0 +1,116 @@
+/*
+ * Hypervisor filesystem for Linux on s390 - debugfs interface
+ *
+ * Copyright (C) IBM Corp. 2010
+ * Author(s): Michael Holzheu <holzheu@linux.vnet.ibm.com>
+ */
+
+#include <linux/slab.h>
+#include "hypfs.h"
+
+static struct dentry *dbfs_dir;
+
+static struct hypfs_dbfs_data *hypfs_dbfs_data_alloc(struct hypfs_dbfs_file *f)
+{
+        struct hypfs_dbfs_data *data;
+
+        data = kmalloc(sizeof(*data), GFP_KERNEL);
+        if (!data)
+                return NULL;
+        kref_init(&data->kref);
+        data->dbfs_file = f;
+        return data;
+}
+
+static void hypfs_dbfs_data_free(struct kref *kref)
+{
+        struct hypfs_dbfs_data *data;
+
+        data = container_of(kref, struct hypfs_dbfs_data, kref);
+        data->dbfs_file->data_free(data->buf_free_ptr);
+        kfree(data);
+}
+
+static void data_free_delayed(struct work_struct *work)
+{
+        struct hypfs_dbfs_data *data;
+        struct hypfs_dbfs_file *df;
+
+        df = container_of(work, struct hypfs_dbfs_file, data_free_work.work);
+        mutex_lock(&df->lock);
+        data = df->data;
+        df->data = NULL;
+        mutex_unlock(&df->lock);
+        kref_put(&data->kref, hypfs_dbfs_data_free);
+}
+
+static ssize_t dbfs_read(struct file *file, char __user *buf,
+                         size_t size, loff_t *ppos)
+{
+        struct hypfs_dbfs_data *data;
+        struct hypfs_dbfs_file *df;
+        ssize_t rc;
+
+        if (*ppos != 0)
+                return 0;
+
+        df = file->f_path.dentry->d_inode->i_private;
+        mutex_lock(&df->lock);
+        if (!df->data) {
+                data = hypfs_dbfs_data_alloc(df);
+                if (!data) {
+                        mutex_unlock(&df->lock);
+                        return -ENOMEM;
+                }
+                rc = df->data_create(&data->buf, &data->buf_free_ptr,
+                                     &data->size);
+                if (rc) {
+                        mutex_unlock(&df->lock);
+                        kfree(data);
+                        return rc;
+                }
+                df->data = data;
+                schedule_delayed_work(&df->data_free_work, HZ);
+        }
+        data = df->data;
+        kref_get(&data->kref);
+        mutex_unlock(&df->lock);
+
+        rc = simple_read_from_buffer(buf, size, ppos, data->buf, data->size);
+        kref_put(&data->kref, hypfs_dbfs_data_free);
+        return rc;
+}
+
+static const struct file_operations dbfs_ops = {
+        .read           = dbfs_read,
+        .llseek         = no_llseek,
+};
+
+int hypfs_dbfs_create_file(struct hypfs_dbfs_file *df)
+{
+        df->dentry = debugfs_create_file(df->name, 0400, dbfs_dir, df,
+                                         &dbfs_ops);
+        if (IS_ERR(df->dentry))
+                return PTR_ERR(df->dentry);
+        mutex_init(&df->lock);
+        INIT_DELAYED_WORK(&df->data_free_work, data_free_delayed);
+        return 0;
+}
+
+void hypfs_dbfs_remove_file(struct hypfs_dbfs_file *df)
+{
+        debugfs_remove(df->dentry);
+}
+
+int hypfs_dbfs_init(void)
+{
+        dbfs_dir = debugfs_create_dir("s390_hypfs", NULL);
+        if (IS_ERR(dbfs_dir))
+                return PTR_ERR(dbfs_dir);
+        return 0;
+}
+
+void hypfs_dbfs_exit(void)
+{
+        debugfs_remove(dbfs_dir);
+}
diff --git a/arch/s390/hypfs/hypfs_diag.c b/arch/s390/hypfs/hypfs_diag.c
index cd4a81be9cf8..6023c6dc1fb7 100644
--- a/arch/s390/hypfs/hypfs_diag.c
+++ b/arch/s390/hypfs/hypfs_diag.c
@@ -555,81 +555,38 @@ struct dbfs_d204 {
         char                    buf[];  /* d204 buffer */
 } __attribute__ ((packed));
 
-struct dbfs_d204_private {
-        struct dbfs_d204        *d204;  /* Aligned d204 data with header */
-        void                    *base;  /* Base pointer (needed for vfree) */
-};
-
-static int dbfs_d204_open(struct inode *inode, struct file *file)
+static int dbfs_d204_create(void **data, void **data_free_ptr, size_t *size)
 {
-        struct dbfs_d204_private *data;
         struct dbfs_d204 *d204;
         int rc, buf_size;
+        void *base;
 
-        data = kzalloc(sizeof(*data), GFP_KERNEL);
-        if (!data)
-                return -ENOMEM;
         buf_size = PAGE_SIZE * (diag204_buf_pages + 1) + sizeof(d204->hdr);
-        data->base = vmalloc(buf_size);
-        if (!data->base) {
-                rc = -ENOMEM;
-                goto fail_kfree_data;
+        base = vmalloc(buf_size);
+        if (!base)
+                return -ENOMEM;
+        memset(base, 0, buf_size);
+        d204 = page_align_ptr(base + sizeof(d204->hdr)) - sizeof(d204->hdr);
+        rc = diag204_do_store(d204->buf, diag204_buf_pages);
+        if (rc) {
+                vfree(base);
+                return rc;
         }
-        memset(data->base, 0, buf_size);
-        d204 = page_align_ptr(data->base + sizeof(d204->hdr))
-                - sizeof(d204->hdr);
-        rc = diag204_do_store(&d204->buf, diag204_buf_pages);
-        if (rc)
-                goto fail_vfree_base;
         d204->hdr.version = DBFS_D204_HDR_VERSION;
         d204->hdr.len = PAGE_SIZE * diag204_buf_pages;
         d204->hdr.sc = diag204_store_sc;
-        data->d204 = d204;
-        file->private_data = data;
-        return nonseekable_open(inode, file);
-
-fail_vfree_base:
-        vfree(data->base);
-fail_kfree_data:
-        kfree(data);
-        return rc;
-}
-
-static int dbfs_d204_release(struct inode *inode, struct file *file)
-{
-        struct dbfs_d204_private *data = file->private_data;
-
-        vfree(data->base);
-        kfree(data);
+        *data = d204;
+        *data_free_ptr = base;
+        *size = d204->hdr.len + sizeof(struct dbfs_d204_hdr);
         return 0;
 }
 
-static ssize_t dbfs_d204_read(struct file *file, char __user *buf,
-                              size_t size, loff_t *ppos)
-{
-        struct dbfs_d204_private *data = file->private_data;
-
-        return simple_read_from_buffer(buf, size, ppos, data->d204,
-                                       data->d204->hdr.len +
-                                       sizeof(data->d204->hdr));
-}
-
-static const struct file_operations dbfs_d204_ops = {
-        .open           = dbfs_d204_open,
-        .read           = dbfs_d204_read,
-        .release        = dbfs_d204_release,
-        .llseek         = no_llseek,
+static struct hypfs_dbfs_file dbfs_file_d204 = {
+        .name           = "diag_204",
+        .data_create    = dbfs_d204_create,
+        .data_free      = vfree,
 };
 
-static int hypfs_dbfs_init(void)
-{
-        dbfs_d204_file = debugfs_create_file("diag_204", 0400, hypfs_dbfs_dir,
-                                             NULL, &dbfs_d204_ops);
-        if (IS_ERR(dbfs_d204_file))
-                return PTR_ERR(dbfs_d204_file);
-        return 0;
-}
-
 __init int hypfs_diag_init(void)
 {
         int rc;
@@ -639,7 +596,7 @@ __init int hypfs_diag_init(void)
                 return -ENODATA;
         }
         if (diag204_info_type == INFO_EXT) {
-                rc = hypfs_dbfs_init();
+                rc = hypfs_dbfs_create_file(&dbfs_file_d204);
                 if (rc)
                         return rc;
         }
@@ -660,6 +617,7 @@ void hypfs_diag_exit(void)
         debugfs_remove(dbfs_d204_file);
         diag224_delete_name_table();
         diag204_free_buffer();
+        hypfs_dbfs_remove_file(&dbfs_file_d204);
 }
 
 /*
diff --git a/arch/s390/hypfs/hypfs_vm.c b/arch/s390/hypfs/hypfs_vm.c
index 26cf177f6a3a..e54796002f61 100644
--- a/arch/s390/hypfs/hypfs_vm.c
+++ b/arch/s390/hypfs/hypfs_vm.c
@@ -20,8 +20,6 @@ static char local_guest[] = "        ";
 static char all_guests[] = "*       ";
 static char *guest_query;
 
-static struct dentry *dbfs_d2fc_file;
-
 struct diag2fc_data {
         __u32 version;
         __u32 flags;
@@ -104,7 +102,7 @@ static void *diag2fc_store(char *query, unsigned int *count, int offset)
         return data;
 }
 
-static void diag2fc_free(void *data)
+static void diag2fc_free(const void *data)
 {
         vfree(data);
 }
@@ -239,43 +237,29 @@ struct dbfs_d2fc {
         char                    buf[];  /* d2fc buffer */
 } __attribute__ ((packed));
 
-static int dbfs_d2fc_open(struct inode *inode, struct file *file)
+static int dbfs_diag2fc_create(void **data, void **data_free_ptr, size_t *size)
 {
-        struct dbfs_d2fc *data;
+        struct dbfs_d2fc *d2fc;
         unsigned int count;
 
-        data = diag2fc_store(guest_query, &count, sizeof(data->hdr));
-        if (IS_ERR(data))
-                return PTR_ERR(data);
-        get_clock_ext(data->hdr.tod_ext);
-        data->hdr.len = count * sizeof(struct diag2fc_data);
-        data->hdr.version = DBFS_D2FC_HDR_VERSION;
-        data->hdr.count = count;
-        memset(&data->hdr.reserved, 0, sizeof(data->hdr.reserved));
-        file->private_data = data;
-        return nonseekable_open(inode, file);
-}
-
-static int dbfs_d2fc_release(struct inode *inode, struct file *file)
-{
-        diag2fc_free(file->private_data);
+        d2fc = diag2fc_store(guest_query, &count, sizeof(d2fc->hdr));
+        if (IS_ERR(d2fc))
+                return PTR_ERR(d2fc);
+        get_clock_ext(d2fc->hdr.tod_ext);
+        d2fc->hdr.len = count * sizeof(struct diag2fc_data);
+        d2fc->hdr.version = DBFS_D2FC_HDR_VERSION;
+        d2fc->hdr.count = count;
+        memset(&d2fc->hdr.reserved, 0, sizeof(d2fc->hdr.reserved));
+        *data = d2fc;
+        *data_free_ptr = d2fc;
+        *size = d2fc->hdr.len + sizeof(struct dbfs_d2fc_hdr);
         return 0;
 }
 
-static ssize_t dbfs_d2fc_read(struct file *file, char __user *buf,
-                                    size_t size, loff_t *ppos)
-{
-        struct dbfs_d2fc *data = file->private_data;
-
-        return simple_read_from_buffer(buf, size, ppos, data, data->hdr.len +
-                                       sizeof(struct dbfs_d2fc_hdr));
-}
-
-static const struct file_operations dbfs_d2fc_ops = {
-        .open           = dbfs_d2fc_open,
-        .read           = dbfs_d2fc_read,
-        .release        = dbfs_d2fc_release,
-        .llseek         = no_llseek,
+static struct hypfs_dbfs_file dbfs_file_2fc = {
+        .name           = "diag_2fc",
+        .data_create    = dbfs_diag2fc_create,
+        .data_free      = diag2fc_free,
 };
 
 int hypfs_vm_init(void)
@@ -288,18 +272,12 @@ int hypfs_vm_init(void)
                 guest_query = local_guest;
         else
                 return -EACCES;
-
-        dbfs_d2fc_file = debugfs_create_file("diag_2fc", 0400, hypfs_dbfs_dir,
-                                             NULL, &dbfs_d2fc_ops);
-        if (IS_ERR(dbfs_d2fc_file))
-                return PTR_ERR(dbfs_d2fc_file);
-
-        return 0;
+        return hypfs_dbfs_create_file(&dbfs_file_2fc);
 }
 
 void hypfs_vm_exit(void)
 {
         if (!MACHINE_IS_VM)
                 return;
-        debugfs_remove(dbfs_d2fc_file);
+        hypfs_dbfs_remove_file(&dbfs_file_2fc);
 }
diff --git a/arch/s390/hypfs/inode.c b/arch/s390/hypfs/inode.c
index 47cc446dab8f..6fe874fc5f8e 100644
--- a/arch/s390/hypfs/inode.c
+++ b/arch/s390/hypfs/inode.c
@@ -46,8 +46,6 @@ static const struct super_operations hypfs_s_ops;
 /* start of list of all dentries, which have to be deleted on update */
 static struct dentry *hypfs_last_dentry;
 
-struct dentry *hypfs_dbfs_dir;
-
 static void hypfs_update_update(struct super_block *sb)
 {
         struct hypfs_sb_info *sb_info = sb->s_fs_info;
@@ -471,13 +469,12 @@ static int __init hypfs_init(void)
 {
         int rc;
 
-        hypfs_dbfs_dir = debugfs_create_dir("s390_hypfs", NULL);
-        if (IS_ERR(hypfs_dbfs_dir))
-                return PTR_ERR(hypfs_dbfs_dir);
-
+        rc = hypfs_dbfs_init();
+        if (rc)
+                return rc;
         if (hypfs_diag_init()) {
                 rc = -ENODATA;
-                goto fail_debugfs_remove;
+                goto fail_dbfs_exit;
         }
         if (hypfs_vm_init()) {
                 rc = -ENODATA;
@@ -499,9 +496,8 @@ fail_hypfs_vm_exit:
         hypfs_vm_exit();
 fail_hypfs_diag_exit:
         hypfs_diag_exit();
-fail_debugfs_remove:
-        debugfs_remove(hypfs_dbfs_dir);
-
+fail_dbfs_exit:
+        hypfs_dbfs_exit();
         pr_err("Initialization of hypfs failed with rc=%i\n", rc);
         return rc;
 }
@@ -510,7 +506,7 @@ static void __exit hypfs_exit(void)
 {
         hypfs_diag_exit();
         hypfs_vm_exit();
-        debugfs_remove(hypfs_dbfs_dir);
+        hypfs_dbfs_exit();
         unregister_filesystem(&hypfs_type);
         kobject_put(s390_kobj);
 }
diff --git a/arch/s390/include/asm/ccwdev.h b/arch/s390/include/asm/ccwdev.h
index e8501115eca8..ff6f62e0ec3e 100644
--- a/arch/s390/include/asm/ccwdev.h
+++ b/arch/s390/include/asm/ccwdev.h
@@ -204,6 +204,8 @@ int ccw_device_tm_start_timeout(struct ccw_device *, struct tcw *,
                             unsigned long, u8, int);
 int ccw_device_tm_intrg(struct ccw_device *cdev);
 
+int ccw_device_get_mdc(struct ccw_device *cdev, u8 mask);
+
 extern int ccw_device_set_online(struct ccw_device *cdev);
 extern int ccw_device_set_offline(struct ccw_device *cdev);
 
diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h
index 40e2ab0fa3f0..081434878296 100644
--- a/arch/s390/include/asm/cputime.h
+++ b/arch/s390/include/asm/cputime.h
@@ -202,7 +202,7 @@ static inline void s390_idle_check(struct pt_regs *regs, __u64 int_clock,
 
 static inline int s390_nohz_delay(int cpu)
 {
-        return per_cpu(s390_idle, cpu).nohz_delay != 0;
+        return __get_cpu_var(s390_idle).nohz_delay != 0;
 }
 
 #define arch_needs_cpu(cpu) s390_nohz_delay(cpu)
diff --git a/arch/s390/include/asm/dasd.h b/arch/s390/include/asm/dasd.h
index b604a9186f8e..0be28efe5b66 100644
--- a/arch/s390/include/asm/dasd.h
+++ b/arch/s390/include/asm/dasd.h
@@ -73,6 +73,7 @@ typedef struct dasd_information2_t {
  * 0x02: use diag discipline (diag)
  * 0x04: set the device initially online (internal use only)
  * 0x08: enable ERP related logging
+ * 0x20: give access to raw eckd data
  */
 #define DASD_FEATURE_DEFAULT         0x00
 #define DASD_FEATURE_READONLY        0x01
@@ -80,6 +81,8 @@ typedef struct dasd_information2_t {
 #define DASD_FEATURE_INITIAL_ONLINE  0x04
 #define DASD_FEATURE_ERPLOG          0x08
 #define DASD_FEATURE_FAILFAST        0x10
+#define DASD_FEATURE_FAILONSLCK      0x20
+#define DASD_FEATURE_USERAW          0x40
 
 #define DASD_PARTN_BITS 2
 
diff --git a/arch/s390/include/asm/ftrace.h b/arch/s390/include/asm/ftrace.h
index 96c14a9102b8..3c29be4836ed 100644
--- a/arch/s390/include/asm/ftrace.h
+++ b/arch/s390/include/asm/ftrace.h
@@ -4,20 +4,17 @@
 #ifndef __ASSEMBLY__
 
 extern void _mcount(void);
-extern unsigned long ftrace_dyn_func;
 
 struct dyn_arch_ftrace { };
 
 #define MCOUNT_ADDR ((long)_mcount)
 
 #ifdef CONFIG_64BIT
-#define MCOUNT_OFFSET_RET 18
-#define MCOUNT_INSN_SIZE  24
-#define MCOUNT_OFFSET     14
-#else
-#define MCOUNT_OFFSET_RET 26
-#define MCOUNT_INSN_SIZE  30
+#define MCOUNT_INSN_SIZE  12
 #define MCOUNT_OFFSET      8
+#else
+#define MCOUNT_INSN_SIZE  20
+#define MCOUNT_OFFSET      4
 #endif
 
 static inline unsigned long ftrace_call_adjust(unsigned long addr)
diff --git a/arch/s390/include/asm/hardirq.h b/arch/s390/include/asm/hardirq.h
index 881d94590aeb..e4155d3eb2cb 100644
--- a/arch/s390/include/asm/hardirq.h
+++ b/arch/s390/include/asm/hardirq.h
@@ -21,20 +21,4 @@
 
 #define HARDIRQ_BITS    8
 
-void clock_comparator_work(void);
-
-static inline unsigned long long local_tick_disable(void)
-{
-        unsigned long long old;
-
-        old = S390_lowcore.clock_comparator;
-        S390_lowcore.clock_comparator = -1ULL;
-        return old;
-}
-
-static inline void local_tick_enable(unsigned long long comp)
-{
-        S390_lowcore.clock_comparator = comp;
-}
-
 #endif /* __ASM_HARDIRQ_H */
diff --git a/arch/s390/include/asm/irq.h b/arch/s390/include/asm/irq.h
index 7da991a858f8..db14a311f1d2 100644
--- a/arch/s390/include/asm/irq.h
+++ b/arch/s390/include/asm/irq.h
@@ -1,23 +1,33 @@
 #ifndef _ASM_IRQ_H
 #define _ASM_IRQ_H
 
-#ifdef __KERNEL__
 #include <linux/hardirq.h>
 
-/*
- * the definition of irqs has changed in 2.5.46:
- * NR_IRQS is no longer the number of i/o
- * interrupts (65536), but rather the number
- * of interrupt classes (2).
- * Only external and i/o interrupts make much sense here (CH).
- */
-
 enum interruption_class {
         EXTERNAL_INTERRUPT,
         IO_INTERRUPT,
-
+        EXTINT_CLK,
+        EXTINT_IPI,
+        EXTINT_TMR,
+        EXTINT_TLA,
+        EXTINT_PFL,
+        EXTINT_DSD,
+        EXTINT_VRT,
+        EXTINT_SCP,
+        EXTINT_IUC,
+        IOINT_QAI,
+        IOINT_QDI,
+        IOINT_DAS,
+        IOINT_C15,
+        IOINT_C70,
+        IOINT_TAP,
+        IOINT_VMR,
+        IOINT_LCS,
+        IOINT_CLW,
+        IOINT_CTC,
+        IOINT_APB,
+        NMI_NMI,
         NR_IRQS,
 };
 
-#endif /* __KERNEL__ */
-#endif
+#endif /* _ASM_IRQ_H */
diff --git a/arch/s390/include/asm/kprobes.h b/arch/s390/include/asm/kprobes.h
index 330f68caffe4..a231a9439c4b 100644
--- a/arch/s390/include/asm/kprobes.h
+++ b/arch/s390/include/asm/kprobes.h
@@ -31,7 +31,6 @@
 #include <linux/ptrace.h>
 #include <linux/percpu.h>
 
-#define  __ARCH_WANT_KPROBES_INSN_SLOT
 struct pt_regs;
 struct kprobe;
 
@@ -58,23 +57,12 @@ typedef u16 kprobe_opcode_t;
 /* Architecture specific copy of original instruction */
 struct arch_specific_insn {
         /* copy of original instruction */
-        kprobe_opcode_t *insn;
-        int fixup;
-        int ilen;
-        int reg;
+        kprobe_opcode_t insn[MAX_INSN_SIZE];
 };
 
-struct ins_replace_args {
-        kprobe_opcode_t *ptr;
-        kprobe_opcode_t old;
-        kprobe_opcode_t new;
-};
 struct prev_kprobe {
         struct kprobe *kp;
         unsigned long status;
-        unsigned long saved_psw;
-        unsigned long kprobe_saved_imask;
-        unsigned long kprobe_saved_ctl[3];
 };
 
 /* per-cpu kprobe control block */
@@ -82,17 +70,13 @@ struct kprobe_ctlblk {
         unsigned long kprobe_status;
         unsigned long kprobe_saved_imask;
         unsigned long kprobe_saved_ctl[3];
-        struct pt_regs jprobe_saved_regs;
-        unsigned long jprobe_saved_r14;
-        unsigned long jprobe_saved_r15;
         struct prev_kprobe prev_kprobe;
+        struct pt_regs jprobe_saved_regs;
         kprobe_opcode_t jprobes_stack[MAX_STACK_SIZE];
 };
 
 void arch_remove_kprobe(struct kprobe *p);
 void kretprobe_trampoline(void);
-int  is_prohibited_opcode(kprobe_opcode_t *instruction);
-void get_instruction_type(struct arch_specific_insn *ainsn);
 
 int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
 int kprobe_exceptions_notify(struct notifier_block *self,
diff --git a/arch/s390/include/asm/mutex.h b/arch/s390/include/asm/mutex.h
index 458c1f7fbc18..688271f5f2e4 100644
--- a/arch/s390/include/asm/mutex.h
+++ b/arch/s390/include/asm/mutex.h
@@ -7,3 +7,5 @@
  */
 
 #include <asm-generic/mutex-dec.h>
+
+#define arch_mutex_cpu_relax()  barrier()
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
index 8d6f87169577..bf3de04170a7 100644
--- a/arch/s390/include/asm/processor.h
+++ b/arch/s390/include/asm/processor.h
@@ -32,7 +32,6 @@ static inline void get_cpu_id(struct cpuid *ptr)
 }
 
 extern void s390_adjust_jiffies(void);
-extern void print_cpu_info(void);
 extern int get_cpu_capability(unsigned int *);
 
 /*
@@ -81,7 +80,8 @@ struct thread_struct {
         mm_segment_t mm_segment;
         unsigned long prot_addr;        /* address of protection-excep.     */
         unsigned int trap_no;
-        per_struct per_info;
+        struct per_regs per_user;       /* User specified PER registers */
+        struct per_event per_event;     /* Cause of the last PER trap */
         /* pfault_wait is used to block the process on a pfault event */
         unsigned long pfault_wait;
 };
diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h
index d9d42b1e46fa..9ad628a8574a 100644
--- a/arch/s390/include/asm/ptrace.h
+++ b/arch/s390/include/asm/ptrace.h
@@ -331,10 +331,60 @@ struct pt_regs
         unsigned short ilc;
         unsigned short svcnr;
 };
+
+/*
+ * Program event recording (PER) register set.
+ */
+struct per_regs {
+        unsigned long control;          /* PER control bits */
+        unsigned long start;            /* PER starting address */
+        unsigned long end;              /* PER ending address */
+};
+
+/*
+ * PER event contains information about the cause of the last PER exception.
+ */
+struct per_event {
+        unsigned short cause;           /* PER code, ATMID and AI */
+        unsigned long address;          /* PER address */
+        unsigned char paid;             /* PER access identification */
+};
+
+/*
+ * Simplified per_info structure used to decode the ptrace user space ABI.
+ */
+struct per_struct_kernel {
+        unsigned long cr9;              /* PER control bits */
+        unsigned long cr10;             /* PER starting address */
+        unsigned long cr11;             /* PER ending address */
+        unsigned long bits;             /* Obsolete software bits */
+        unsigned long starting_addr;    /* User specified start address */
+        unsigned long ending_addr;      /* User specified end address */
+        unsigned short perc_atmid;      /* PER trap ATMID */
+        unsigned long address;          /* PER trap instruction address */
+        unsigned char access_id;        /* PER trap access identification */
+};
+
+#define PER_EVENT_MASK                  0xE9000000UL
+
+#define PER_EVENT_BRANCH                0x80000000UL
+#define PER_EVENT_IFETCH                0x40000000UL
+#define PER_EVENT_STORE                 0x20000000UL
+#define PER_EVENT_STORE_REAL            0x08000000UL
+#define PER_EVENT_NULLIFICATION         0x01000000UL
+
+#define PER_CONTROL_MASK                0x00a00000UL
+
+#define PER_CONTROL_BRANCH_ADDRESS      0x00800000UL
+#define PER_CONTROL_ALTERATION          0x00200000UL
+
 #endif
 
 /*
- * Now for the program event recording (trace) definitions.
+ * Now for the user space program event recording (trace) definitions.
+ * The following structures are used only for the ptrace interface, don't
+ * touch or even look at it if you don't want to modify the user-space
+ * ptrace interface. In particular stay away from it for in-kernel PER.
  */
 typedef struct
 {
diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h
index 46e96bc1f5a1..350e7ee5952d 100644
--- a/arch/s390/include/asm/qdio.h
+++ b/arch/s390/include/asm/qdio.h
@@ -361,6 +361,7 @@ struct qdio_initialize {
         qdio_handler_t *input_handler;
         qdio_handler_t *output_handler;
         void (*queue_start_poll) (struct ccw_device *, int, unsigned long);
+        int scan_threshold;
         unsigned long int_parm;
         void **input_sbal_addr_array;
         void **output_sbal_addr_array;
diff --git a/arch/s390/include/asm/qeth.h b/arch/s390/include/asm/qeth.h
index 06cbd1e8c943..90efda0b137d 100644
--- a/arch/s390/include/asm/qeth.h
+++ b/arch/s390/include/asm/qeth.h
@@ -28,39 +28,70 @@ struct qeth_arp_cache_entry {
         __u8  reserved2[32];
 } __attribute__ ((packed));
 
+enum qeth_arp_ipaddrtype {
+        QETHARP_IP_ADDR_V4 = 1,
+        QETHARP_IP_ADDR_V6 = 2,
+};
+struct qeth_arp_entrytype {
+        __u8 mac;
+        __u8 ip;
+} __attribute__((packed));
+
+#define QETH_QARP_MEDIASPECIFIC_BYTES 32
+#define QETH_QARP_MACADDRTYPE_BYTES 1
 struct qeth_arp_qi_entry7 {
-        __u8 media_specific[32];
-        __u8 macaddr_type;
-        __u8 ipaddr_type;
+        __u8 media_specific[QETH_QARP_MEDIASPECIFIC_BYTES];
+        struct qeth_arp_entrytype type;
         __u8 macaddr[6];
         __u8 ipaddr[4];
 } __attribute__((packed));
 
+struct qeth_arp_qi_entry7_ipv6 {
+        __u8 media_specific[QETH_QARP_MEDIASPECIFIC_BYTES];
+        struct qeth_arp_entrytype type;
+        __u8 macaddr[6];
+        __u8 ipaddr[16];
+} __attribute__((packed));
+
 struct qeth_arp_qi_entry7_short {
-        __u8 macaddr_type;
-        __u8 ipaddr_type;
+        struct qeth_arp_entrytype type;
         __u8 macaddr[6];
         __u8 ipaddr[4];
 } __attribute__((packed));
 
+struct qeth_arp_qi_entry7_short_ipv6 {
+        struct qeth_arp_entrytype type;
+        __u8 macaddr[6];
+        __u8 ipaddr[16];
+} __attribute__((packed));
+
 struct qeth_arp_qi_entry5 {
-        __u8 media_specific[32];
-        __u8 macaddr_type;
-        __u8 ipaddr_type;
+        __u8 media_specific[QETH_QARP_MEDIASPECIFIC_BYTES];
+        struct qeth_arp_entrytype type;
         __u8 ipaddr[4];
 } __attribute__((packed));
 
+struct qeth_arp_qi_entry5_ipv6 {
+        __u8 media_specific[QETH_QARP_MEDIASPECIFIC_BYTES];
+        struct qeth_arp_entrytype type;
+        __u8 ipaddr[16];
+} __attribute__((packed));
+
 struct qeth_arp_qi_entry5_short {
-        __u8 macaddr_type;
-        __u8 ipaddr_type;
+        struct qeth_arp_entrytype type;
         __u8 ipaddr[4];
 } __attribute__((packed));
 
+struct qeth_arp_qi_entry5_short_ipv6 {
+        struct qeth_arp_entrytype type;
+        __u8 ipaddr[16];
+} __attribute__((packed));
 /*
  * can be set by user if no "media specific information" is wanted
  * -> saves a lot of space in user space buffer
  */
 #define QETH_QARP_STRIP_ENTRIES  0x8000
+#define QETH_QARP_WITH_IPV6      0x4000
 #define QETH_QARP_REQUEST_MASK   0x00ff
 
 /* data sent to user space as result of query arp ioctl */
diff --git a/arch/s390/include/asm/s390_ext.h b/arch/s390/include/asm/s390_ext.h
index 1a9307e70842..080876d5f196 100644
--- a/arch/s390/include/asm/s390_ext.h
+++ b/arch/s390/include/asm/s390_ext.h
@@ -1,32 +1,17 @@
-#ifndef _S390_EXTINT_H
-#define _S390_EXTINT_H
-
 /*
- *  include/asm-s390/s390_ext.h
- *
- *  S390 version
- *    Copyright IBM Corp. 1999,2007
- *    Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com),
- *               Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *    Copyright IBM Corp. 1999,2010
+ *    Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
+ *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  */
 
+#ifndef _S390_EXTINT_H
+#define _S390_EXTINT_H
+
 #include <linux/types.h>
 
 typedef void (*ext_int_handler_t)(unsigned int, unsigned int, unsigned long);
 
-typedef struct ext_int_info_t {
-        struct ext_int_info_t *next;
-        ext_int_handler_t handler;
-        __u16 code;
-} ext_int_info_t;
-
-extern ext_int_info_t *ext_int_hash[];
-
 int register_external_interrupt(__u16 code, ext_int_handler_t handler);
-int register_early_external_interrupt(__u16 code, ext_int_handler_t handler,
-                                      ext_int_info_t *info);
 int unregister_external_interrupt(__u16 code, ext_int_handler_t handler);
-int unregister_early_external_interrupt(__u16 code, ext_int_handler_t handler,
-                                        ext_int_info_t *info);
 
-#endif
+#endif /* _S390_EXTINT_H */
diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h
index edc03cb9cd79..045e009fc164 100644
--- a/arch/s390/include/asm/smp.h
+++ b/arch/s390/include/asm/smp.h
@@ -20,7 +20,6 @@ extern void machine_power_off_smp(void);
 
 extern int __cpu_disable (void);
 extern void __cpu_die (unsigned int cpu);
-extern void cpu_die (void) __attribute__ ((noreturn));
 extern int __cpu_up (unsigned int cpu);
 
 extern struct mutex smp_cpu_state_mutex;
@@ -71,8 +70,10 @@ static inline void smp_switch_to_ipl_cpu(void (*func)(void *), void *data)
 
 #ifdef CONFIG_HOTPLUG_CPU
 extern int smp_rescan_cpus(void);
+extern void __noreturn cpu_die(void);
 #else
 static inline int smp_rescan_cpus(void) { return 0; }
+static inline void cpu_die(void) { }
 #endif
 
 #endif /* __ASM_SMP_H */
diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h
index 3ad16dbf622e..6710b0eac165 100644
--- a/arch/s390/include/asm/system.h
+++ b/arch/s390/include/asm/system.h
@@ -20,6 +20,7 @@
 struct task_struct;
 
 extern struct task_struct *__switch_to(void *, void *);
+extern void update_per_regs(struct task_struct *task);
 
 static inline void save_fp_regs(s390_fp_regs *fpregs)
 {
@@ -93,6 +94,7 @@ static inline void restore_access_regs(unsigned int *acrs)
         if (next->mm) {                                                 \
                 restore_fp_regs(&next->thread.fp_regs);                 \
                 restore_access_regs(&next->thread.acrs[0]);             \
+                update_per_regs(next);                                  \
         }                                                               \
         prev = __switch_to(prev,next);                                  \
 } while (0)
@@ -101,11 +103,9 @@ extern void account_vtime(struct task_struct *, struct task_struct *);
 extern void account_tick_vtime(struct task_struct *);
 
 #ifdef CONFIG_PFAULT
-extern void pfault_irq_init(void);
 extern int pfault_init(void);
 extern void pfault_fini(void);
 #else /* CONFIG_PFAULT */
-#define pfault_irq_init()       do { } while (0)
 #define pfault_init()           ({-1;})
 #define pfault_fini()           do { } while (0)
 #endif /* CONFIG_PFAULT */
diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
index 5baf0230b29b..ebc77091466f 100644
--- a/arch/s390/include/asm/thread_info.h
+++ b/arch/s390/include/asm/thread_info.h
@@ -74,7 +74,7 @@ struct thread_info {
 /* how to get the thread information struct from C */
 static inline struct thread_info *current_thread_info(void)
 {
-        return (struct thread_info *)(S390_lowcore.kernel_stack - THREAD_SIZE);
+        return (struct thread_info *) S390_lowcore.thread_info;
 }
 
 #define THREAD_SIZE_ORDER THREAD_ORDER
@@ -88,7 +88,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_SIGPENDING          2       /* signal pending */
 #define TIF_NEED_RESCHED        3       /* rescheduling necessary */
 #define TIF_RESTART_SVC         4       /* restart svc with new svc number */
-#define TIF_SINGLE_STEP         6       /* deliver sigtrap on return to user */
+#define TIF_PER_TRAP            6       /* deliver sigtrap on return to user */
 #define TIF_MCCK_PENDING        7       /* machine check handling is pending */
 #define TIF_SYSCALL_TRACE       8       /* syscall trace active */
 #define TIF_SYSCALL_AUDIT       9       /* syscall auditing active */
@@ -99,14 +99,15 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_31BIT               17      /* 32bit process */
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK     19      /* restore signal mask in do_signal() */
-#define TIF_FREEZE              20      /* thread is freezing for suspend */
+#define TIF_SINGLE_STEP         20      /* This task is single stepped */
+#define TIF_FREEZE              21      /* thread is freezing for suspend */
 
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_RESTART_SVC        (1<<TIF_RESTART_SVC)
-#define _TIF_SINGLE_STEP        (1<<TIF_SINGLE_STEP)
+#define _TIF_PER_TRAP           (1<<TIF_PER_TRAP)
 #define _TIF_MCCK_PENDING       (1<<TIF_MCCK_PENDING)
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
@@ -114,6 +115,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_31BIT              (1<<TIF_31BIT)
+#define _TIF_SINGLE_STEP        (1<<TIF_FREEZE)
 #define _TIF_FREEZE             (1<<TIF_FREEZE)
 
 #endif /* __KERNEL__ */
diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h
index 09d345a701dc..88829a40af6f 100644
--- a/arch/s390/include/asm/timex.h
+++ b/arch/s390/include/asm/timex.h
@@ -11,6 +11,8 @@
 #ifndef _ASM_S390_TIMEX_H
 #define _ASM_S390_TIMEX_H
 
+#include <asm/lowcore.h>
+
 /* The value of the TOD clock for 1.1.1970. */
 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 
@@ -49,6 +51,24 @@ static inline void store_clock_comparator(__u64 *time)
         asm volatile("stckc %0" : "=Q" (*time));
 }
 
+void clock_comparator_work(void);
+
+static inline unsigned long long local_tick_disable(void)
+{
+        unsigned long long old;
+
+        old = S390_lowcore.clock_comparator;
+        S390_lowcore.clock_comparator = -1ULL;
+        set_clock_comparator(S390_lowcore.clock_comparator);
+        return old;
+}
+
+static inline void local_tick_enable(unsigned long long comp)
+{
+        S390_lowcore.clock_comparator = comp;
+        set_clock_comparator(S390_lowcore.clock_comparator);
+}
+
 #define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
 
 typedef unsigned long long cycles_t;
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index 33982e7ce04d..fe03c140002a 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -23,14 +23,16 @@ int main(void)
 {
         DEFINE(__THREAD_info, offsetof(struct task_struct, stack));
         DEFINE(__THREAD_ksp, offsetof(struct task_struct, thread.ksp));
-        DEFINE(__THREAD_per, offsetof(struct task_struct, thread.per_info));
         DEFINE(__THREAD_mm_segment, offsetof(struct task_struct, thread.mm_segment));
         BLANK();
         DEFINE(__TASK_pid, offsetof(struct task_struct, pid));
         BLANK();
-        DEFINE(__PER_atmid, offsetof(per_struct, lowcore.words.perc_atmid));
-        DEFINE(__PER_address, offsetof(per_struct, lowcore.words.address));
-        DEFINE(__PER_access_id, offsetof(per_struct, lowcore.words.access_id));
+        DEFINE(__THREAD_per_cause,
+               offsetof(struct task_struct, thread.per_event.cause));
+        DEFINE(__THREAD_per_address,
+               offsetof(struct task_struct, thread.per_event.address));
+        DEFINE(__THREAD_per_paid,
+               offsetof(struct task_struct, thread.per_event.paid));
         BLANK();
         DEFINE(__TI_task, offsetof(struct thread_info, task));
         DEFINE(__TI_domain, offsetof(struct thread_info, exec_domain));
@@ -85,9 +87,9 @@ int main(void)
         DEFINE(__LC_PGM_ILC, offsetof(struct _lowcore, pgm_ilc));
         DEFINE(__LC_PGM_INT_CODE, offsetof(struct _lowcore, pgm_code));
         DEFINE(__LC_TRANS_EXC_CODE, offsetof(struct _lowcore, trans_exc_code));
-        DEFINE(__LC_PER_ATMID, offsetof(struct _lowcore, per_perc_atmid));
+        DEFINE(__LC_PER_CAUSE, offsetof(struct _lowcore, per_perc_atmid));
         DEFINE(__LC_PER_ADDRESS, offsetof(struct _lowcore, per_address));
-        DEFINE(__LC_PER_ACCESS_ID, offsetof(struct _lowcore, per_access_id));
+        DEFINE(__LC_PER_PAID, offsetof(struct _lowcore, per_access_id));
         DEFINE(__LC_AR_MODE_ID, offsetof(struct _lowcore, ar_access_id));
         DEFINE(__LC_SUBCHANNEL_ID, offsetof(struct _lowcore, subchannel_id));
         DEFINE(__LC_SUBCHANNEL_NR, offsetof(struct _lowcore, subchannel_nr));
diff --git a/arch/s390/kernel/compat_ptrace.h b/arch/s390/kernel/compat_ptrace.h
index 3141025724f4..12b823833510 100644
--- a/arch/s390/kernel/compat_ptrace.h
+++ b/arch/s390/kernel/compat_ptrace.h
@@ -4,40 +4,19 @@
 #include <asm/ptrace.h>    /* needed for NUM_CR_WORDS */
 #include "compat_linux.h"  /* needed for psw_compat_t */
 
-typedef struct {
-        __u32 cr[NUM_CR_WORDS];
-} per_cr_words32;
-
-typedef struct {
-        __u16          perc_atmid;          /* 0x096 */
-        __u32          address;             /* 0x098 */
-        __u8           access_id;           /* 0x0a1 */
-} per_lowcore_words32;
-
-typedef struct {
-        union {
-                per_cr_words32   words;
-        } control_regs;
-        /*
-         * Use these flags instead of setting em_instruction_fetch
-         * directly they are used so that single stepping can be
-         * switched on & off while not affecting other tracing
-         */
-        unsigned  single_step       : 1;
-        unsigned  instruction_fetch : 1;
-        unsigned                    : 30;
-        /*
-         * These addresses are copied into cr10 & cr11 if single
-         * stepping is switched off
-         */
-        __u32     starting_addr;
-        __u32     ending_addr;
-        union {
-                per_lowcore_words32 words;
-        } lowcore; 
-} per_struct32;
+struct compat_per_struct_kernel {
+        __u32 cr9;              /* PER control bits */
+        __u32 cr10;             /* PER starting address */
+        __u32 cr11;             /* PER ending address */
+        __u32 bits;             /* Obsolete software bits */
+        __u32 starting_addr;    /* User specified start address */
+        __u32 ending_addr;      /* User specified end address */
+        __u16 perc_atmid;       /* PER trap ATMID */
+        __u32 address;          /* PER trap instruction address */
+        __u8  access_id;        /* PER trap access identification */
+};
 
-struct user_regs_struct32
+struct compat_user_regs_struct
 {
         psw_compat_t psw;
         u32 gprs[NUM_GPRS];
@@ -50,14 +29,14 @@ struct user_regs_struct32
          * itself as there is no "official" ptrace interface for hardware
          * watchpoints. This is the way intel does it.
          */
-        per_struct32 per_info;
+        struct compat_per_struct_kernel per_info;
         u32  ieee_instruction_pointer;  /* obsolete, always 0 */
 };
 
-struct user32 {
+struct compat_user {
         /* We start with the registers, to mimic the way that "memory"
            is returned from the ptrace(3,...) function.  */
-        struct user_regs_struct32 regs; /* Where the registers are actually stored */
+        struct compat_user_regs_struct regs;
         /* The rest of this junk is to help gdb figure out what goes where */
         u32 u_tsize;            /* Text segment size (pages). */
         u32 u_dsize;            /* Data segment size (pages). */
@@ -79,6 +58,6 @@ typedef struct
         __u32   len;
         __u32   kernel_addr;
         __u32   process_addr;
-} ptrace_area_emu31;
+} compat_ptrace_area;
 
 #endif /* _PTRACE32_H */
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 1ecc337fb679..648f64239a9d 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -9,7 +9,6 @@
  *               Heiko Carstens <heiko.carstens@de.ibm.com>
  */
 
-#include <linux/sys.h>
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/cache.h>
@@ -49,7 +48,7 @@ SP_SVCNR     =	STACK_FRAME_OVERHEAD + __PT_SVCNR
 SP_SIZE      =  STACK_FRAME_OVERHEAD + __PT_SIZE
 
 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
-                 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
+                 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_PER_TRAP )
 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
                  _TIF_MCCK_PENDING)
 _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \
@@ -110,31 +109,36 @@ STACK_SIZE  = 1 << STACK_SHIFT
 1:      stm     %r10,%r11,\lc_sum
         .endm
 
-        .macro  SAVE_ALL_BASE savearea
+        .macro  SAVE_ALL_SVC psworg,savearea
         stm     %r12,%r15,\savearea
         l       %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13
+        l       %r15,__LC_KERNEL_STACK  # problem state -> load ksp
+        s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
         .endm
 
-        .macro  SAVE_ALL_SVC psworg,savearea
-        la      %r12,\psworg
-        l       %r15,__LC_KERNEL_STACK  # problem state -> load ksp
+        .macro  SAVE_ALL_BASE savearea
+        stm     %r12,%r15,\savearea
+        l       %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13
         .endm
 
-        .macro  SAVE_ALL_SYNC psworg,savearea
-        la      %r12,\psworg
+        .macro  SAVE_ALL_PGM psworg,savearea
         tm      \psworg+1,0x01          # test problem state bit
-        bz      BASED(2f)               # skip stack setup save
-        l       %r15,__LC_KERNEL_STACK  # problem state -> load ksp
 #ifdef CONFIG_CHECK_STACK
-        b       BASED(3f)
-2:      tml     %r15,STACK_SIZE - CONFIG_STACK_GUARD
-        bz      BASED(stack_overflow)
-3:
+        bnz     BASED(1f)
+        tml     %r15,STACK_SIZE - CONFIG_STACK_GUARD
+        bnz     BASED(2f)
+        la      %r12,\psworg
+        b       BASED(stack_overflow)
+#else
+        bz      BASED(2f)
 #endif
-2:
+1:      l       %r15,__LC_KERNEL_STACK  # problem state -> load ksp
+2:      s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
         .endm
 
         .macro  SAVE_ALL_ASYNC psworg,savearea
+        stm     %r12,%r15,\savearea
+        l       %r13,__LC_SVC_NEW_PSW+4 # load &system_call to %r13
         la      %r12,\psworg
         tm      \psworg+1,0x01          # test problem state bit
         bnz     BASED(1f)               # from user -> load async stack
@@ -149,27 +153,23 @@ STACK_SIZE  = 1 << STACK_SHIFT
 0:      l       %r14,__LC_ASYNC_STACK   # are we already on the async stack ?
         slr     %r14,%r15
         sra     %r14,STACK_SHIFT
-        be      BASED(2f)
-1:      l       %r15,__LC_ASYNC_STACK
 #ifdef CONFIG_CHECK_STACK
-        b       BASED(3f)
-2:      tml     %r15,STACK_SIZE - CONFIG_STACK_GUARD
-        bz      BASED(stack_overflow)
-3:
+        bnz     BASED(1f)
+        tml     %r15,STACK_SIZE - CONFIG_STACK_GUARD
+        bnz     BASED(2f)
+        b       BASED(stack_overflow)
+#else
+        bz      BASED(2f)
 #endif
-2:
+1:      l       %r15,__LC_ASYNC_STACK
+2:      s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
         .endm
 
-        .macro  CREATE_STACK_FRAME psworg,savearea
-        s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
-        mvc     SP_PSW(8,%r15),0(%r12)  # move user PSW to stack
+        .macro  CREATE_STACK_FRAME savearea
+        xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
         st      %r2,SP_ORIG_R2(%r15)    # store original content of gpr 2
-        icm     %r12,12,__LC_SVC_ILC
-        stm     %r0,%r11,SP_R0(%r15)    # store gprs %r0-%r11 to kernel stack
-        st      %r12,SP_ILC(%r15)
         mvc     SP_R12(16,%r15),\savearea # move %r12-%r15 to stack
-        la      %r12,0
-        st      %r12,__SF_BACKCHAIN(%r15)       # clear back chain
+        stm     %r0,%r11,SP_R0(%r15)    # store gprs %r0-%r11 to kernel stack
         .endm
 
         .macro  RESTORE_ALL psworg,sync
@@ -188,6 +188,8 @@ STACK_SIZE  = 1 << STACK_SHIFT
         ssm     __SF_EMPTY(%r15)
         .endm
 
+        .section .kprobes.text, "ax"
+
 /*
  * Scheduler resume function, called by switch_to
  *  gpr2 = (task_struct *) prev
@@ -198,31 +200,21 @@ STACK_SIZE  = 1 << STACK_SHIFT
         .globl  __switch_to
 __switch_to:
         basr    %r1,0
-__switch_to_base:
-        tm      __THREAD_per(%r3),0xe8          # new process is using per ?
-        bz      __switch_to_noper-__switch_to_base(%r1) # if not we're fine
-        stctl   %c9,%c11,__SF_EMPTY(%r15)       # We are using per stuff
-        clc     __THREAD_per(12,%r3),__SF_EMPTY(%r15)
-        be      __switch_to_noper-__switch_to_base(%r1) # we got away w/o bashing TLB's
-        lctl    %c9,%c11,__THREAD_per(%r3)      # Nope we didn't
-__switch_to_noper:
-        l       %r4,__THREAD_info(%r2)          # get thread_info of prev
+0:      l       %r4,__THREAD_info(%r2)          # get thread_info of prev
+        l       %r5,__THREAD_info(%r3)          # get thread_info of next
         tm      __TI_flags+3(%r4),_TIF_MCCK_PENDING # machine check pending?
-        bz      __switch_to_no_mcck-__switch_to_base(%r1)
-        ni      __TI_flags+3(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
-        l       %r4,__THREAD_info(%r3)          # get thread_info of next
-        oi      __TI_flags+3(%r4),_TIF_MCCK_PENDING # set it in next
-__switch_to_no_mcck:
-        stm     %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
-        st      %r15,__THREAD_ksp(%r2)  # store kernel stack to prev->tss.ksp
-        l       %r15,__THREAD_ksp(%r3)  # load kernel stack from next->tss.ksp
-        lm      %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
-        st      %r3,__LC_CURRENT        # __LC_CURRENT = current task struct
-        lctl    %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
-        l       %r3,__THREAD_info(%r3)  # load thread_info from task struct
-        st      %r3,__LC_THREAD_INFO
-        ahi     %r3,STACK_SIZE
-        st      %r3,__LC_KERNEL_STACK   # __LC_KERNEL_STACK = new kernel stack
+        bz      1f-0b(%r1)
+        ni      __TI_flags+3(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
+        oi      __TI_flags+3(%r5),_TIF_MCCK_PENDING     # set it in next
+1:      stm     %r6,%r15,__SF_GPRS(%r15)        # store gprs of prev task
+        st      %r15,__THREAD_ksp(%r2)          # store kernel stack of prev
+        l       %r15,__THREAD_ksp(%r3)          # load kernel stack of next
+        lctl    %c4,%c4,__TASK_pid(%r3)         # load pid to control reg. 4
+        lm      %r6,%r15,__SF_GPRS(%r15)        # load gprs of next task
+        st      %r3,__LC_CURRENT                # store task struct of next
+        st      %r5,__LC_THREAD_INFO            # store thread info of next
+        ahi     %r5,STACK_SIZE                  # end of kernel stack of next
+        st      %r5,__LC_KERNEL_STACK           # store end of kernel stack
         br      %r14
 
 __critical_start:
@@ -235,10 +227,11 @@ __critical_start:
 system_call:
         stpt    __LC_SYNC_ENTER_TIMER
 sysc_saveall:
-        SAVE_ALL_BASE __LC_SAVE_AREA
         SAVE_ALL_SVC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
-        lh      %r7,0x8a          # get svc number from lowcore
+        CREATE_STACK_FRAME __LC_SAVE_AREA
+        mvc     SP_PSW(8,%r15),__LC_SVC_OLD_PSW
+        mvc     SP_ILC(4,%r15),__LC_SVC_ILC
+        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
 sysc_vtime:
         UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
 sysc_stime:
@@ -246,20 +239,20 @@ sysc_stime:
 sysc_update:
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
 sysc_do_svc:
-        l       %r9,__LC_THREAD_INFO    # load pointer to thread_info struct
-        ltr     %r7,%r7                 # test for svc 0
+        xr      %r7,%r7
+        icm     %r7,3,SP_SVCNR(%r15)    # load svc number and test for svc 0
         bnz     BASED(sysc_nr_ok)       # svc number > 0
         # svc 0: system call number in %r1
         cl      %r1,BASED(.Lnr_syscalls)
         bnl     BASED(sysc_nr_ok)
+        sth     %r1,SP_SVCNR(%r15)
         lr      %r7,%r1           # copy svc number to %r7
 sysc_nr_ok:
-        sth     %r7,SP_SVCNR(%r15)
         sll     %r7,2             # svc number *4
-        l       %r8,BASED(.Lsysc_table)
-        tm      __TI_flags+2(%r9),_TIF_SYSCALL
+        l       %r10,BASED(.Lsysc_table)
+        tm      __TI_flags+2(%r12),_TIF_SYSCALL
         mvc     SP_ARGS(4,%r15),SP_R7(%r15)
-        l       %r8,0(%r7,%r8)    # get system call addr.
+        l       %r8,0(%r7,%r10)   # get system call addr.
         bnz     BASED(sysc_tracesys)
         basr    %r14,%r8          # call sys_xxxx
         st      %r2,SP_R2(%r15)   # store return value (change R2 on stack)
@@ -267,7 +260,7 @@ sysc_nr_ok:
 sysc_return:
         LOCKDEP_SYS_EXIT
 sysc_tif:
-        tm      __TI_flags+3(%r9),_TIF_WORK_SVC
+        tm      __TI_flags+3(%r12),_TIF_WORK_SVC
         bnz     BASED(sysc_work)  # there is work to do (signals etc.)
 sysc_restore:
         RESTORE_ALL __LC_RETURN_PSW,1
@@ -284,17 +277,17 @@ sysc_work:
 # One of the work bits is on. Find out which one.
 #
 sysc_work_tif:
-        tm      __TI_flags+3(%r9),_TIF_MCCK_PENDING
+        tm      __TI_flags+3(%r12),_TIF_MCCK_PENDING
         bo      BASED(sysc_mcck_pending)
-        tm      __TI_flags+3(%r9),_TIF_NEED_RESCHED
+        tm      __TI_flags+3(%r12),_TIF_NEED_RESCHED
         bo      BASED(sysc_reschedule)
-        tm      __TI_flags+3(%r9),_TIF_SIGPENDING
+        tm      __TI_flags+3(%r12),_TIF_SIGPENDING
         bo      BASED(sysc_sigpending)
-        tm      __TI_flags+3(%r9),_TIF_NOTIFY_RESUME
+        tm      __TI_flags+3(%r12),_TIF_NOTIFY_RESUME
         bo      BASED(sysc_notify_resume)
-        tm      __TI_flags+3(%r9),_TIF_RESTART_SVC
+        tm      __TI_flags+3(%r12),_TIF_RESTART_SVC
         bo      BASED(sysc_restart)
-        tm      __TI_flags+3(%r9),_TIF_SINGLE_STEP
+        tm      __TI_flags+3(%r12),_TIF_PER_TRAP
         bo      BASED(sysc_singlestep)
         b       BASED(sysc_return)      # beware of critical section cleanup
 
@@ -318,13 +311,13 @@ sysc_mcck_pending:
 # _TIF_SIGPENDING is set, call do_signal
 #
 sysc_sigpending:
-        ni      __TI_flags+3(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
+        ni      __TI_flags+3(%r12),255-_TIF_PER_TRAP # clear TIF_PER_TRAP
         la      %r2,SP_PTREGS(%r15)     # load pt_regs
         l       %r1,BASED(.Ldo_signal)
         basr    %r14,%r1                # call do_signal
-        tm      __TI_flags+3(%r9),_TIF_RESTART_SVC
+        tm      __TI_flags+3(%r12),_TIF_RESTART_SVC
         bo      BASED(sysc_restart)
-        tm      __TI_flags+3(%r9),_TIF_SINGLE_STEP
+        tm      __TI_flags+3(%r12),_TIF_PER_TRAP
         bo      BASED(sysc_singlestep)
         b       BASED(sysc_return)
 
@@ -342,23 +335,23 @@ sysc_notify_resume:
 # _TIF_RESTART_SVC is set, set up registers and restart svc
 #
 sysc_restart:
-        ni      __TI_flags+3(%r9),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
+        ni      __TI_flags+3(%r12),255-_TIF_RESTART_SVC # clear TIF_RESTART_SVC
         l       %r7,SP_R2(%r15)         # load new svc number
         mvc     SP_R2(4,%r15),SP_ORIG_R2(%r15) # restore first argument
         lm      %r2,%r6,SP_R2(%r15)     # load svc arguments
+        sth     %r7,SP_SVCNR(%r15)
         b       BASED(sysc_nr_ok)       # restart svc
 
 #
-# _TIF_SINGLE_STEP is set, call do_single_step
+# _TIF_PER_TRAP is set, call do_per_trap
 #
 sysc_singlestep:
-        ni      __TI_flags+3(%r9),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
-        mvi     SP_SVCNR(%r15),0xff     # set trap indication to pgm check
-        mvi     SP_SVCNR+1(%r15),0xff
+        ni      __TI_flags+3(%r12),255-_TIF_PER_TRAP # clear TIF_PER_TRAP
+        xc      SP_SVCNR(2,%r15),SP_SVCNR(%r15)         # clear svc number
         la      %r2,SP_PTREGS(%r15)     # address of register-save area
         l       %r1,BASED(.Lhandle_per) # load adr. of per handler
         la      %r14,BASED(sysc_return) # load adr. of system return
-        br      %r1                     # branch to do_single_step
+        br      %r1                     # branch to do_per_trap
 
 #
 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
@@ -368,15 +361,15 @@ sysc_tracesys:
         l       %r1,BASED(.Ltrace_entry)
         la      %r2,SP_PTREGS(%r15)     # load pt_regs
         la      %r3,0
-        srl     %r7,2
-        st      %r7,SP_R2(%r15)
+        xr      %r0,%r0
+        icm     %r0,3,SP_SVCNR(%r15)
+        st      %r0,SP_R2(%r15)
         basr    %r14,%r1
         cl      %r2,BASED(.Lnr_syscalls)
         bnl     BASED(sysc_tracenogo)
-        l       %r8,BASED(.Lsysc_table)
         lr      %r7,%r2
         sll     %r7,2                   # svc number *4
-        l       %r8,0(%r7,%r8)
+        l       %r8,0(%r7,%r10)
 sysc_tracego:
         lm      %r3,%r6,SP_R3(%r15)
         mvc     SP_ARGS(4,%r15),SP_R7(%r15)
@@ -384,7 +377,7 @@ sysc_tracego:
         basr    %r14,%r8                # call sys_xxx
         st      %r2,SP_R2(%r15)         # store return value
 sysc_tracenogo:
-        tm      __TI_flags+2(%r9),_TIF_SYSCALL
+        tm      __TI_flags+2(%r12),_TIF_SYSCALL
         bz      BASED(sysc_return)
         l       %r1,BASED(.Ltrace_exit)
         la      %r2,SP_PTREGS(%r15)     # load pt_regs
@@ -397,7 +390,7 @@ sysc_tracenogo:
         .globl  ret_from_fork
 ret_from_fork:
         l       %r13,__LC_SVC_NEW_PSW+4
-        l       %r9,__LC_THREAD_INFO    # load pointer to thread_info struct
+        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
         tm      SP_PSW+1(%r15),0x01     # forking a kernel thread ?
         bo      BASED(0f)
         st      %r15,SP_R15(%r15)       # store stack pointer for new kthread
@@ -432,8 +425,8 @@ kernel_execve:
 0:      stnsm   __SF_EMPTY(%r15),0xfc   # disable interrupts
         l       %r15,__LC_KERNEL_STACK  # load ksp
         s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
-        l       %r9,__LC_THREAD_INFO
         mvc     SP_PTREGS(__PT_SIZE,%r15),0(%r12)       # copy pt_regs
+        l       %r12,__LC_THREAD_INFO
         xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
         stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
         l       %r1,BASED(.Lexecve_tail)
@@ -463,26 +456,27 @@ pgm_check_handler:
         SAVE_ALL_BASE __LC_SAVE_AREA
         tm      __LC_PGM_INT_CODE+1,0x80 # check whether we got a per exception
         bnz     BASED(pgm_per)          # got per exception -> special case
-        SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
+        SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA
+        CREATE_STACK_FRAME __LC_SAVE_AREA
+        xc      SP_ILC(4,%r15),SP_ILC(%r15)
+        mvc     SP_PSW(8,%r15),__LC_PGM_OLD_PSW
+        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
         tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
         bz      BASED(pgm_no_vtime)
         UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
         UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
 pgm_no_vtime:
-        l       %r9,__LC_THREAD_INFO    # load pointer to thread_info struct
         l       %r3,__LC_PGM_ILC        # load program interruption code
         l       %r4,__LC_TRANS_EXC_CODE
         REENABLE_IRQS
         la      %r8,0x7f
         nr      %r8,%r3
-pgm_do_call:
-        l       %r7,BASED(.Ljump_table)
         sll     %r8,2
-        l       %r7,0(%r8,%r7)          # load address of handler routine
+        l       %r1,BASED(.Ljump_table)
+        l       %r1,0(%r8,%r1)          # load address of handler routine
         la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        basr    %r14,%r7                # branch to interrupt-handler
+        basr    %r14,%r1                # branch to interrupt-handler
 pgm_exit:
         b       BASED(sysc_return)
 
@@ -503,33 +497,34 @@ pgm_per:
 # Normal per exception
 #
 pgm_per_std:
-        SAVE_ALL_SYNC __LC_PGM_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_PGM_OLD_PSW,__LC_SAVE_AREA
+        SAVE_ALL_PGM __LC_PGM_OLD_PSW,__LC_SAVE_AREA
+        CREATE_STACK_FRAME __LC_SAVE_AREA
+        mvc     SP_PSW(8,%r15),__LC_PGM_OLD_PSW
+        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
         tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
         bz      BASED(pgm_no_vtime2)
         UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
         UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
 pgm_no_vtime2:
-        l       %r9,__LC_THREAD_INFO    # load pointer to thread_info struct
-        l       %r1,__TI_task(%r9)
+        l       %r1,__TI_task(%r12)
         tm      SP_PSW+1(%r15),0x01     # kernel per event ?
         bz      BASED(kernel_per)
-        mvc     __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
-        mvc     __THREAD_per+__PER_address(4,%r1),__LC_PER_ADDRESS
-        mvc     __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
-        oi      __TI_flags+3(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
+        mvc     __THREAD_per_cause(2,%r1),__LC_PER_CAUSE
+        mvc     __THREAD_per_address(4,%r1),__LC_PER_ADDRESS
+        mvc     __THREAD_per_paid(1,%r1),__LC_PER_PAID
+        oi      __TI_flags+3(%r12),_TIF_PER_TRAP # set TIF_PER_TRAP
         l       %r3,__LC_PGM_ILC        # load program interruption code
         l       %r4,__LC_TRANS_EXC_CODE
         REENABLE_IRQS
         la      %r8,0x7f
         nr      %r8,%r3                 # clear per-event-bit and ilc
         be      BASED(pgm_exit2)        # only per or per+check ?
-        l       %r7,BASED(.Ljump_table)
         sll     %r8,2
-        l       %r7,0(%r8,%r7)          # load address of handler routine
+        l       %r1,BASED(.Ljump_table)
+        l       %r1,0(%r8,%r1)          # load address of handler routine
         la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        basr    %r14,%r7                # branch to interrupt-handler
+        basr    %r14,%r1                # branch to interrupt-handler
 pgm_exit2:
         b       BASED(sysc_return)
 
@@ -537,18 +532,19 @@ pgm_exit2:
 # it was a single stepped SVC that is causing all the trouble
 #
 pgm_svcper:
-        SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
+        SAVE_ALL_PGM __LC_SVC_OLD_PSW,__LC_SAVE_AREA
+        CREATE_STACK_FRAME __LC_SAVE_AREA
+        mvc     SP_PSW(8,%r15),__LC_SVC_OLD_PSW
+        mvc     SP_ILC(4,%r15),__LC_SVC_ILC
+        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
         UPDATE_VTIME __LC_EXIT_TIMER,__LC_SYNC_ENTER_TIMER,__LC_USER_TIMER
         UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
-        lh      %r7,0x8a                # get svc number from lowcore
-        l       %r9,__LC_THREAD_INFO    # load pointer to thread_info struct
-        l       %r8,__TI_task(%r9)
-        mvc     __THREAD_per+__PER_atmid(2,%r8),__LC_PER_ATMID
-        mvc     __THREAD_per+__PER_address(4,%r8),__LC_PER_ADDRESS
-        mvc     __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID
-        oi      __TI_flags+3(%r9),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
+        l       %r8,__TI_task(%r12)
+        mvc     __THREAD_per_cause(2,%r8),__LC_PER_CAUSE
+        mvc     __THREAD_per_address(4,%r8),__LC_PER_ADDRESS
+        mvc     __THREAD_per_paid(1,%r8),__LC_PER_PAID
+        oi      __TI_flags+3(%r12),_TIF_PER_TRAP # set TIF_PER_TRAP
         stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
         lm      %r2,%r6,SP_R2(%r15)     # load svc arguments
         b       BASED(sysc_do_svc)
@@ -558,8 +554,7 @@ pgm_svcper:
 #
 kernel_per:
         REENABLE_IRQS
-        mvi     SP_SVCNR(%r15),0xff     # set trap indication to pgm check
-        mvi     SP_SVCNR+1(%r15),0xff
+        xc      SP_SVCNR(2,%r15),SP_SVCNR(%r15)
         la      %r2,SP_PTREGS(%r15)     # address of register-save area
         l       %r1,BASED(.Lhandle_per) # load adr. of per handler
         basr    %r14,%r1                # branch to do_single_step
@@ -573,9 +568,10 @@ kernel_per:
 io_int_handler:
         stck    __LC_INT_CLOCK
         stpt    __LC_ASYNC_ENTER_TIMER
-        SAVE_ALL_BASE __LC_SAVE_AREA+16
         SAVE_ALL_ASYNC __LC_IO_OLD_PSW,__LC_SAVE_AREA+16
-        CREATE_STACK_FRAME __LC_IO_OLD_PSW,__LC_SAVE_AREA+16
+        CREATE_STACK_FRAME __LC_SAVE_AREA+16
+        mvc     SP_PSW(8,%r15),0(%r12)  # move user PSW to stack
+        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
         tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
         bz      BASED(io_no_vtime)
         UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
@@ -583,7 +579,6 @@ io_int_handler:
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
 io_no_vtime:
         TRACE_IRQS_OFF
-        l       %r9,__LC_THREAD_INFO    # load pointer to thread_info struct
         l       %r1,BASED(.Ldo_IRQ)     # load address of do_IRQ
         la      %r2,SP_PTREGS(%r15)     # address of register-save area
         basr    %r14,%r1                # branch to standard irq handler
@@ -591,7 +586,7 @@ io_return:
         LOCKDEP_SYS_EXIT
         TRACE_IRQS_ON
 io_tif:
-        tm      __TI_flags+3(%r9),_TIF_WORK_INT
+        tm      __TI_flags+3(%r12),_TIF_WORK_INT
         bnz     BASED(io_work)          # there is work to do (signals etc.)
 io_restore:
         RESTORE_ALL __LC_RETURN_PSW,0
@@ -609,9 +604,9 @@ io_work:
         bo      BASED(io_work_user)     # yes -> do resched & signal
 #ifdef CONFIG_PREEMPT
         # check for preemptive scheduling
-        icm     %r0,15,__TI_precount(%r9)
+        icm     %r0,15,__TI_precount(%r12)
         bnz     BASED(io_restore)       # preemption disabled
-        tm      __TI_flags+3(%r9),_TIF_NEED_RESCHED
+        tm      __TI_flags+3(%r12),_TIF_NEED_RESCHED
         bno     BASED(io_restore)
         # switch to kernel stack
         l       %r1,SP_R15(%r15)
@@ -645,13 +640,13 @@ io_work_user:
 #               and _TIF_MCCK_PENDING
 #
 io_work_tif:
-        tm      __TI_flags+3(%r9),_TIF_MCCK_PENDING
+        tm      __TI_flags+3(%r12),_TIF_MCCK_PENDING
         bo      BASED(io_mcck_pending)
-        tm      __TI_flags+3(%r9),_TIF_NEED_RESCHED
+        tm      __TI_flags+3(%r12),_TIF_NEED_RESCHED
         bo      BASED(io_reschedule)
-        tm      __TI_flags+3(%r9),_TIF_SIGPENDING
+        tm      __TI_flags+3(%r12),_TIF_SIGPENDING
         bo      BASED(io_sigpending)
-        tm      __TI_flags+3(%r9),_TIF_NOTIFY_RESUME
+        tm      __TI_flags+3(%r12),_TIF_NOTIFY_RESUME
         bo      BASED(io_notify_resume)
         b       BASED(io_return)        # beware of critical section cleanup
 
@@ -711,16 +706,16 @@ io_notify_resume:
 ext_int_handler:
         stck    __LC_INT_CLOCK
         stpt    __LC_ASYNC_ENTER_TIMER
-        SAVE_ALL_BASE __LC_SAVE_AREA+16
         SAVE_ALL_ASYNC __LC_EXT_OLD_PSW,__LC_SAVE_AREA+16
-        CREATE_STACK_FRAME __LC_EXT_OLD_PSW,__LC_SAVE_AREA+16
+        CREATE_STACK_FRAME __LC_SAVE_AREA+16
+        mvc     SP_PSW(8,%r15),0(%r12)  # move user PSW to stack
+        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
         tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
         bz      BASED(ext_no_vtime)
         UPDATE_VTIME __LC_EXIT_TIMER,__LC_ASYNC_ENTER_TIMER,__LC_USER_TIMER
         UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_ASYNC_ENTER_TIMER
 ext_no_vtime:
-        l       %r9,__LC_THREAD_INFO    # load pointer to thread_info struct
         TRACE_IRQS_OFF
         la      %r2,SP_PTREGS(%r15)     # address of register-save area
         l       %r3,__LC_CPU_ADDRESS    # get cpu address + interruption code
@@ -775,7 +770,10 @@ mcck_int_main:
         sra     %r14,PAGE_SHIFT
         be      BASED(0f)
         l       %r15,__LC_PANIC_STACK   # load panic stack
-0:      CREATE_STACK_FRAME __LC_MCK_OLD_PSW,__LC_SAVE_AREA+32
+0:      s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
+        CREATE_STACK_FRAME __LC_SAVE_AREA+32
+        mvc     SP_PSW(8,%r15),0(%r12)
+        l       %r12,__LC_THREAD_INFO   # load pointer to thread_info struct
         tm      __LC_MCCK_CODE+2,0x08   # mwp of old psw valid?
         bno     BASED(mcck_no_vtime)    # no -> skip cleanup critical
         tm      SP_PSW+1(%r15),0x01     # interrupting from user ?
@@ -784,7 +782,6 @@ mcck_int_main:
         UPDATE_VTIME __LC_LAST_UPDATE_TIMER,__LC_EXIT_TIMER,__LC_SYSTEM_TIMER
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_MCCK_ENTER_TIMER
 mcck_no_vtime:
-        l       %r9,__LC_THREAD_INFO    # load pointer to thread_info struct
         la      %r2,SP_PTREGS(%r15)     # load pt_regs
         l       %r1,BASED(.Ls390_mcck)
         basr    %r14,%r1                # call machine check handler
@@ -796,7 +793,7 @@ mcck_no_vtime:
         xc      __SF_BACKCHAIN(4,%r1),__SF_BACKCHAIN(%r1) # clear back chain
         lr      %r15,%r1
         stosm   __SF_EMPTY(%r15),0x04   # turn dat on
-        tm      __TI_flags+3(%r9),_TIF_MCCK_PENDING
+        tm      __TI_flags+3(%r12),_TIF_MCCK_PENDING
         bno     BASED(mcck_return)
         TRACE_IRQS_OFF
         l       %r1,BASED(.Ls390_handle_mcck)
@@ -861,6 +858,8 @@ restart_crash:
 restart_go:
 #endif
 
+        .section .kprobes.text, "ax"
+
 #ifdef CONFIG_CHECK_STACK
 /*
  * The synchronous or the asynchronous stack overflowed. We are dead.
@@ -943,12 +942,13 @@ cleanup_system_call:
         bh      BASED(0f)
         mvc     __LC_SAVE_AREA(16),0(%r12)
 0:      st      %r13,4(%r12)
-        st      %r12,__LC_SAVE_AREA+48  # argh
-        SAVE_ALL_SYNC __LC_SVC_OLD_PSW,__LC_SAVE_AREA
-        CREATE_STACK_FRAME __LC_SVC_OLD_PSW,__LC_SAVE_AREA
-        l       %r12,__LC_SAVE_AREA+48  # argh
+        l       %r15,__LC_KERNEL_STACK  # problem state -> load ksp
+        s       %r15,BASED(.Lc_spsize)  # make room for registers & psw
         st      %r15,12(%r12)
-        lh      %r7,0x8a
+        CREATE_STACK_FRAME __LC_SAVE_AREA
+        mvc     SP_PSW(8,%r15),__LC_SVC_OLD_PSW
+        mvc     SP_ILC(4,%r15),__LC_SVC_ILC
+        mvc     0(4,%r12),__LC_THREAD_INFO
 cleanup_vtime:
         clc     __LC_RETURN_PSW+4(4),BASED(cleanup_system_call_insn+12)
         bhe     BASED(cleanup_stime)
@@ -1046,7 +1046,7 @@ cleanup_io_restore_insn:
 .Ldo_signal:    .long   do_signal
 .Ldo_notify_resume:
                 .long   do_notify_resume
-.Lhandle_per:   .long   do_single_step
+.Lhandle_per:   .long   do_per_trap
 .Ldo_execve:    .long   do_execve
 .Lexecve_tail:  .long   execve_tail
 .Ljump_table:   .long   pgm_check_table
diff --git a/arch/s390/kernel/entry.h b/arch/s390/kernel/entry.h
index 95c1dfc4ef31..17a6f83a2d67 100644
--- a/arch/s390/kernel/entry.h
+++ b/arch/s390/kernel/entry.h
@@ -12,7 +12,7 @@ pgm_check_handler_t do_dat_exception;
 
 extern int sysctl_userprocess_debug;
 
-void do_single_step(struct pt_regs *regs);
+void do_per_trap(struct pt_regs *regs);
 void syscall_trace(struct pt_regs *regs, int entryexit);
 void kernel_stack_overflow(struct pt_regs * regs);
 void do_signal(struct pt_regs *regs);
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 8f3e802174db..9d3603d6c511 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -51,7 +51,7 @@ STACK_SHIFT = PAGE_SHIFT + THREAD_ORDER
 STACK_SIZE  = 1 << STACK_SHIFT
 
 _TIF_WORK_SVC = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
-                 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_SINGLE_STEP )
+                 _TIF_MCCK_PENDING | _TIF_RESTART_SVC | _TIF_PER_TRAP )
 _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
                  _TIF_MCCK_PENDING)
 _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \
@@ -197,6 +197,8 @@ _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \
         ssm     __SF_EMPTY(%r15)
         .endm
 
+        .section .kprobes.text, "ax"
+
 /*
  * Scheduler resume function, called by switch_to
  *  gpr2 = (task_struct *) prev
@@ -206,30 +208,21 @@ _TIF_SYSCALL = (_TIF_SYSCALL_TRACE>>8 | _TIF_SYSCALL_AUDIT>>8 | \
  */
         .globl  __switch_to
 __switch_to:
-        tm      __THREAD_per+4(%r3),0xe8 # is the new process using per ?
-        jz      __switch_to_noper               # if not we're fine
-        stctg   %c9,%c11,__SF_EMPTY(%r15)# We are using per stuff
-        clc     __THREAD_per(24,%r3),__SF_EMPTY(%r15)
-        je      __switch_to_noper            # we got away without bashing TLB's
-        lctlg   %c9,%c11,__THREAD_per(%r3)      # Nope we didn't
-__switch_to_noper:
-        lg      %r4,__THREAD_info(%r2)              # get thread_info of prev
+        lg      %r4,__THREAD_info(%r2)          # get thread_info of prev
+        lg      %r5,__THREAD_info(%r3)          # get thread_info of next
         tm      __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
-        jz      __switch_to_no_mcck
-        ni      __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
-        lg      %r4,__THREAD_info(%r3)              # get thread_info of next
-        oi      __TI_flags+7(%r4),_TIF_MCCK_PENDING # set it in next
-__switch_to_no_mcck:
-        stmg    %r6,%r15,__SF_GPRS(%r15)# store __switch_to registers of prev task
-        stg     %r15,__THREAD_ksp(%r2)  # store kernel stack to prev->tss.ksp
-        lg      %r15,__THREAD_ksp(%r3)  # load kernel stack from next->tss.ksp
-        lmg     %r6,%r15,__SF_GPRS(%r15)# load __switch_to registers of next task
-        stg     %r3,__LC_CURRENT        # __LC_CURRENT = current task struct
-        lctl    %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
-        lg      %r3,__THREAD_info(%r3)  # load thread_info from task struct
-        stg     %r3,__LC_THREAD_INFO
-        aghi    %r3,STACK_SIZE
-        stg     %r3,__LC_KERNEL_STACK   # __LC_KERNEL_STACK = new kernel stack
+        jz      0f
+        ni      __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
+        oi      __TI_flags+7(%r5),_TIF_MCCK_PENDING     # set it in next
+0:      stmg    %r6,%r15,__SF_GPRS(%r15)        # store gprs of prev task
+        stg     %r15,__THREAD_ksp(%r2)          # store kernel stack of prev
+        lg      %r15,__THREAD_ksp(%r3)          # load kernel stack of next
+        lctl    %c4,%c4,__TASK_pid(%r3)         # load pid to control reg. 4
+        lmg     %r6,%r15,__SF_GPRS(%r15)        # load gprs of next task
+        stg     %r3,__LC_CURRENT                # store task struct of next
+        stg     %r5,__LC_THREAD_INFO            # store thread info of next
+        aghi    %r5,STACK_SIZE                  # end of kernel stack of next
+        stg     %r5,__LC_KERNEL_STACK           # store end of kernel stack
         br      %r14
 
 __critical_start:
@@ -309,7 +302,7 @@ sysc_work_tif:
         jo      sysc_notify_resume
         tm      __TI_flags+7(%r12),_TIF_RESTART_SVC
         jo      sysc_restart
-        tm      __TI_flags+7(%r12),_TIF_SINGLE_STEP
+        tm      __TI_flags+7(%r12),_TIF_PER_TRAP
         jo      sysc_singlestep
         j       sysc_return             # beware of critical section cleanup
 
@@ -331,12 +324,12 @@ sysc_mcck_pending:
 # _TIF_SIGPENDING is set, call do_signal
 #
 sysc_sigpending:
-        ni      __TI_flags+7(%r12),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
+        ni      __TI_flags+7(%r12),255-_TIF_PER_TRAP # clear TIF_PER_TRAP
         la      %r2,SP_PTREGS(%r15)     # load pt_regs
         brasl   %r14,do_signal          # call do_signal
         tm      __TI_flags+7(%r12),_TIF_RESTART_SVC
         jo      sysc_restart
-        tm      __TI_flags+7(%r12),_TIF_SINGLE_STEP
+        tm      __TI_flags+7(%r12),_TIF_PER_TRAP
         jo      sysc_singlestep
         j       sysc_return
 
@@ -361,14 +354,14 @@ sysc_restart:
         j       sysc_nr_ok              # restart svc
 
 #
-# _TIF_SINGLE_STEP is set, call do_single_step
+# _TIF_PER_TRAP is set, call do_per_trap
 #
 sysc_singlestep:
-        ni      __TI_flags+7(%r12),255-_TIF_SINGLE_STEP # clear TIF_SINGLE_STEP
+        ni      __TI_flags+7(%r12),255-_TIF_PER_TRAP    # clear TIF_PER_TRAP
         xc      SP_SVCNR(2,%r15),SP_SVCNR(%r15)         # clear svc number
         la      %r2,SP_PTREGS(%r15)     # address of register-save area
         larl    %r14,sysc_return        # load adr. of system return
-        jg      do_single_step          # branch to do_sigtrap
+        jg      do_per_trap
 
 #
 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
@@ -524,10 +517,10 @@ pgm_no_vtime2:
         lg      %r1,__TI_task(%r12)
         tm      SP_PSW+1(%r15),0x01     # kernel per event ?
         jz      kernel_per
-        mvc     __THREAD_per+__PER_atmid(2,%r1),__LC_PER_ATMID
-        mvc     __THREAD_per+__PER_address(8,%r1),__LC_PER_ADDRESS
-        mvc     __THREAD_per+__PER_access_id(1,%r1),__LC_PER_ACCESS_ID
-        oi      __TI_flags+7(%r12),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
+        mvc     __THREAD_per_cause(2,%r1),__LC_PER_CAUSE
+        mvc     __THREAD_per_address(8,%r1),__LC_PER_ADDRESS
+        mvc     __THREAD_per_paid(1,%r1),__LC_PER_PAID
+        oi      __TI_flags+7(%r12),_TIF_PER_TRAP # set TIF_PER_TRAP
         lgf     %r3,__LC_PGM_ILC        # load program interruption code
         lg      %r4,__LC_TRANS_EXC_CODE
         REENABLE_IRQS
@@ -556,10 +549,10 @@ pgm_svcper:
         mvc     __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
         LAST_BREAK
         lg      %r8,__TI_task(%r12)
-        mvc     __THREAD_per+__PER_atmid(2,%r8),__LC_PER_ATMID
-        mvc     __THREAD_per+__PER_address(8,%r8),__LC_PER_ADDRESS
-        mvc     __THREAD_per+__PER_access_id(1,%r8),__LC_PER_ACCESS_ID
-        oi      __TI_flags+7(%r12),_TIF_SINGLE_STEP # set TIF_SINGLE_STEP
+        mvc     __THREAD_per_cause(2,%r8),__LC_PER_CAUSE
+        mvc     __THREAD_per_address(8,%r8),__LC_PER_ADDRESS
+        mvc     __THREAD_per_paid(1,%r8),__LC_PER_PAID
+        oi      __TI_flags+7(%r12),_TIF_PER_TRAP # set TIF_PER_TRAP
         stosm   __SF_EMPTY(%r15),0x03   # reenable interrupts
         lmg     %r2,%r6,SP_R2(%r15)     # load svc arguments
         j       sysc_do_svc
@@ -571,7 +564,7 @@ kernel_per:
         REENABLE_IRQS
         xc      SP_SVCNR(2,%r15),SP_SVCNR(%r15) # clear svc number
         la      %r2,SP_PTREGS(%r15)     # address of register-save area
-        brasl   %r14,do_single_step
+        brasl   %r14,do_per_trap
         j       pgm_exit
 
 /*
@@ -868,6 +861,8 @@ restart_crash:
 restart_go:
 #endif
 
+        .section .kprobes.text, "ax"
+
 #ifdef CONFIG_CHECK_STACK
 /*
  * The synchronous or the asynchronous stack overflowed. We are dead.
diff --git a/arch/s390/kernel/ftrace.c b/arch/s390/kernel/ftrace.c
index 6a83d0581317..78bdf0e5dff7 100644
--- a/arch/s390/kernel/ftrace.c
+++ b/arch/s390/kernel/ftrace.c
@@ -4,7 +4,7 @@
  * Copyright IBM Corp. 2009
  *
  *   Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>,
- *
+ *              Martin Schwidefsky <schwidefsky@de.ibm.com>
  */
 
 #include <linux/hardirq.h>
@@ -12,176 +12,144 @@
 #include <linux/ftrace.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
+#include <linux/kprobes.h>
 #include <trace/syscall.h>
 #include <asm/asm-offsets.h>
 
+#ifdef CONFIG_64BIT
+#define MCOUNT_OFFSET_RET 12
+#else
+#define MCOUNT_OFFSET_RET 22
+#endif
+
 #ifdef CONFIG_DYNAMIC_FTRACE
 
 void ftrace_disable_code(void);
-void ftrace_disable_return(void);
-void ftrace_call_code(void);
-void ftrace_nop_code(void);
-
-#define FTRACE_INSN_SIZE 4
+void ftrace_enable_insn(void);
 
 #ifdef CONFIG_64BIT
-
+/*
+ * The 64-bit mcount code looks like this:
+ *      stg     %r14,8(%r15)            # offset 0
+ * >    larl    %r1,<&counter>          # offset 6
+ * >    brasl   %r14,_mcount            # offset 12
+ *      lg      %r14,8(%r15)            # offset 18
+ * Total length is 24 bytes. The middle two instructions of the mcount
+ * block get overwritten by ftrace_make_nop / ftrace_make_call.
+ * The 64-bit enabled ftrace code block looks like this:
+ *      stg     %r14,8(%r15)            # offset 0
+ * >    lg      %r1,__LC_FTRACE_FUNC    # offset 6
+ * >    lgr     %r0,%r0                 # offset 12
+ * >    basr    %r14,%r1                # offset 16
+ *      lg      %r14,8(%15)             # offset 18
+ * The return points of the mcount/ftrace function have the same offset 18.
+ * The 64-bit disable ftrace code block looks like this:
+ *      stg     %r14,8(%r15)            # offset 0
+ * >    jg      .+18                    # offset 6
+ * >    lgr     %r0,%r0                 # offset 12
+ * >    basr    %r14,%r1                # offset 16
+ *      lg      %r14,8(%15)             # offset 18
+ * The jg instruction branches to offset 24 to skip as many instructions
+ * as possible.
+ */
 asm(
         "       .align  4\n"
         "ftrace_disable_code:\n"
-        "       j       0f\n"
-        "       .word   0x0024\n"
-        "       lg      %r1,"__stringify(__LC_FTRACE_FUNC)"\n"
-        "       basr    %r14,%r1\n"
-        "ftrace_disable_return:\n"
-        "       lg      %r14,8(15)\n"
+        "       jg      0f\n"
         "       lgr     %r0,%r0\n"
-        "0:\n");
-
-asm(
+        "       basr    %r14,%r1\n"
+        "0:\n"
         "       .align  4\n"
-        "ftrace_nop_code:\n"
-        "       j       .+"__stringify(MCOUNT_INSN_SIZE)"\n");
+        "ftrace_enable_insn:\n"
+        "       lg      %r1,"__stringify(__LC_FTRACE_FUNC)"\n");
 
-asm(
-        "       .align  4\n"
-        "ftrace_call_code:\n"
-        "       stg     %r14,8(%r15)\n");
+#define FTRACE_INSN_SIZE        6
 
 #else /* CONFIG_64BIT */
-
+/*
+ * The 31-bit mcount code looks like this:
+ *      st      %r14,4(%r15)            # offset 0
+ * >    bras    %r1,0f                  # offset 4
+ * >    .long   _mcount                 # offset 8
+ * >    .long   <&counter>              # offset 12
+ * > 0: l       %r14,0(%r1)             # offset 16
+ * >    l       %r1,4(%r1)              # offset 20
+ *      basr    %r14,%r14               # offset 24
+ *      l       %r14,4(%r15)            # offset 26
+ * Total length is 30 bytes. The twenty bytes starting from offset 4
+ * to offset 24 get overwritten by ftrace_make_nop / ftrace_make_call.
+ * The 31-bit enabled ftrace code block looks like this:
+ *      st      %r14,4(%r15)            # offset 0
+ * >    l       %r14,__LC_FTRACE_FUNC   # offset 4
+ * >    j       0f                      # offset 8
+ * >    .fill   12,1,0x07               # offset 12
+ *   0: basr    %r14,%r14               # offset 24
+ *      l       %r14,4(%r14)            # offset 26
+ * The return points of the mcount/ftrace function have the same offset 26.
+ * The 31-bit disabled ftrace code block looks like this:
+ *      st      %r14,4(%r15)            # offset 0
+ * >    j       .+26                    # offset 4
+ * >    j       0f                      # offset 8
+ * >    .fill   12,1,0x07               # offset 12
+ *   0: basr    %r14,%r14               # offset 24
+ *      l       %r14,4(%r14)            # offset 26
+ * The j instruction branches to offset 30 to skip as many instructions
+ * as possible.
+ */
 asm(
         "       .align  4\n"
         "ftrace_disable_code:\n"
+        "       j       1f\n"
         "       j       0f\n"
-        "       l       %r1,"__stringify(__LC_FTRACE_FUNC)"\n"
-        "       basr    %r14,%r1\n"
-        "ftrace_disable_return:\n"
-        "       l       %r14,4(%r15)\n"
-        "       j       0f\n"
-        "       bcr     0,%r7\n"
-        "       bcr     0,%r7\n"
-        "       bcr     0,%r7\n"
-        "       bcr     0,%r7\n"
-        "       bcr     0,%r7\n"
-        "       bcr     0,%r7\n"
-        "0:\n");
-
-asm(
+        "       .fill   12,1,0x07\n"
+        "0:     basr    %r14,%r14\n"
+        "1:\n"
         "       .align  4\n"
-        "ftrace_nop_code:\n"
-        "       j       .+"__stringify(MCOUNT_INSN_SIZE)"\n");
+        "ftrace_enable_insn:\n"
+        "       l       %r14,"__stringify(__LC_FTRACE_FUNC)"\n");
 
-asm(
-        "       .align  4\n"
-        "ftrace_call_code:\n"
-        "       st      %r14,4(%r15)\n");
+#define FTRACE_INSN_SIZE        4
 
 #endif /* CONFIG_64BIT */
 
-static int ftrace_modify_code(unsigned long ip,
-                              void *old_code, int old_size,
-                              void *new_code, int new_size)
-{
-        unsigned char replaced[MCOUNT_INSN_SIZE];
-
-        /*
-         * Note: Due to modules code can disappear and change.
-         *  We need to protect against faulting as well as code
-         *  changing. We do this by using the probe_kernel_*
-         *  functions.
-         *  This however is just a simple sanity check.
-         */
-        if (probe_kernel_read(replaced, (void *)ip, old_size))
-                return -EFAULT;
-        if (memcmp(replaced, old_code, old_size) != 0)
-                return -EINVAL;
-        if (probe_kernel_write((void *)ip, new_code, new_size))
-                return -EPERM;
-        return 0;
-}
-
-static int ftrace_make_initial_nop(struct module *mod, struct dyn_ftrace *rec,
-                                   unsigned long addr)
-{
-        return ftrace_modify_code(rec->ip,
-                                  ftrace_call_code, FTRACE_INSN_SIZE,
-                                  ftrace_disable_code, MCOUNT_INSN_SIZE);
-}
 
 int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec,
                     unsigned long addr)
 {
-        if (addr == MCOUNT_ADDR)
-                return ftrace_make_initial_nop(mod, rec, addr);
-        return ftrace_modify_code(rec->ip,
-                                  ftrace_call_code, FTRACE_INSN_SIZE,
-                                  ftrace_nop_code, FTRACE_INSN_SIZE);
+        if (probe_kernel_write((void *) rec->ip, ftrace_disable_code,
+                               MCOUNT_INSN_SIZE))
+                return -EPERM;
+        return 0;
 }
 
 int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
 {
-        return ftrace_modify_code(rec->ip,
-                                  ftrace_nop_code, FTRACE_INSN_SIZE,
-                                  ftrace_call_code, FTRACE_INSN_SIZE);
+        if (probe_kernel_write((void *) rec->ip, ftrace_enable_insn,
+                               FTRACE_INSN_SIZE))
+                return -EPERM;
+        return 0;
 }
 
 int ftrace_update_ftrace_func(ftrace_func_t func)
 {
-        ftrace_dyn_func = (unsigned long)func;
         return 0;
 }
 
 int __init ftrace_dyn_arch_init(void *data)
 {
-        *(unsigned long *)data = 0;
+        *(unsigned long *) data = 0;
         return 0;
 }
 
 #endif /* CONFIG_DYNAMIC_FTRACE */
 
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
-#ifdef CONFIG_DYNAMIC_FTRACE
-/*
- * Patch the kernel code at ftrace_graph_caller location:
- * The instruction there is branch relative on condition. The condition mask
- * is either all ones (always branch aka disable ftrace_graph_caller) or all
- * zeroes (nop aka enable ftrace_graph_caller).
- * Instruction format for brc is a7m4xxxx where m is the condition mask.
- */
-int ftrace_enable_ftrace_graph_caller(void)
-{
-        unsigned short opcode = 0xa704;
-
-        return probe_kernel_write(ftrace_graph_caller, &opcode, sizeof(opcode));
-}
-
-int ftrace_disable_ftrace_graph_caller(void)
-{
-        unsigned short opcode = 0xa7f4;
-
-        return probe_kernel_write(ftrace_graph_caller, &opcode, sizeof(opcode));
-}
-
-static inline unsigned long ftrace_mcount_call_adjust(unsigned long addr)
-{
-        return addr - (ftrace_disable_return - ftrace_disable_code);
-}
-
-#else /* CONFIG_DYNAMIC_FTRACE */
-
-static inline unsigned long ftrace_mcount_call_adjust(unsigned long addr)
-{
-        return addr - MCOUNT_OFFSET_RET;
-}
-
-#endif /* CONFIG_DYNAMIC_FTRACE */
-
 /*
  * Hook the return address and push it in the stack of return addresses
  * in current thread info.
  */
-unsigned long prepare_ftrace_return(unsigned long ip, unsigned long parent)
+unsigned long __kprobes prepare_ftrace_return(unsigned long parent,
+                                              unsigned long ip)
 {
         struct ftrace_graph_ent trace;
 
@@ -189,14 +157,42 @@ unsigned long prepare_ftrace_return(unsigned long ip, unsigned long parent)
                 goto out;
         if (ftrace_push_return_trace(parent, ip, &trace.depth, 0) == -EBUSY)
                 goto out;
-        trace.func = ftrace_mcount_call_adjust(ip) & PSW_ADDR_INSN;
+        trace.func = (ip & PSW_ADDR_INSN) - MCOUNT_OFFSET_RET;
         /* Only trace if the calling function expects to. */
         if (!ftrace_graph_entry(&trace)) {
                 current->curr_ret_stack--;
                 goto out;
         }
-        parent = (unsigned long)return_to_handler;
+        parent = (unsigned long) return_to_handler;
 out:
         return parent;
 }
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+/*
+ * Patch the kernel code at ftrace_graph_caller location. The instruction
+ * there is branch relative and save to prepare_ftrace_return. To disable
+ * the call to prepare_ftrace_return we patch the bras offset to point
+ * directly after the instructions. To enable the call we calculate
+ * the original offset to prepare_ftrace_return and put it back.
+ */
+int ftrace_enable_ftrace_graph_caller(void)
+{
+        unsigned short offset;
+
+        offset = ((void *) prepare_ftrace_return -
+                  (void *) ftrace_graph_caller) / 2;
+        return probe_kernel_write(ftrace_graph_caller + 2,
+                                  &offset, sizeof(offset));
+}
+
+int ftrace_disable_ftrace_graph_caller(void)
+{
+        static unsigned short offset = 0x0002;
+
+        return probe_kernel_write(ftrace_graph_caller + 2,
+                                  &offset, sizeof(offset));
+}
+
+#endif /* CONFIG_DYNAMIC_FTRACE */
 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index 026a37a94fc9..ea5099c9709c 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -1,7 +1,5 @@
 /*
- *  arch/s390/kernel/irq.c
- *
- *    Copyright IBM Corp. 2004,2007
+ *    Copyright IBM Corp. 2004,2010
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Thomas Spatzier (tspat@de.ibm.com)
  *
@@ -17,12 +15,42 @@
 #include <linux/proc_fs.h>
 #include <linux/profile.h>
 
+struct irq_class {
+        char *name;
+        char *desc;
+};
+
+static const struct irq_class intrclass_names[] = {
+        {.name = "EXT" },
+        {.name = "I/O" },
+        {.name = "CLK", .desc = "[EXT] Clock Comparator" },
+        {.name = "IPI", .desc = "[EXT] Signal Processor" },
+        {.name = "TMR", .desc = "[EXT] CPU Timer" },
+        {.name = "TAL", .desc = "[EXT] Timing Alert" },
+        {.name = "PFL", .desc = "[EXT] Pseudo Page Fault" },
+        {.name = "DSD", .desc = "[EXT] DASD Diag" },
+        {.name = "VRT", .desc = "[EXT] Virtio" },
+        {.name = "SCP", .desc = "[EXT] Service Call" },
+        {.name = "IUC", .desc = "[EXT] IUCV" },
+        {.name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt" },
+        {.name = "QDI", .desc = "[I/O] QDIO Interrupt" },
+        {.name = "DAS", .desc = "[I/O] DASD" },
+        {.name = "C15", .desc = "[I/O] 3215" },
+        {.name = "C70", .desc = "[I/O] 3270" },
+        {.name = "TAP", .desc = "[I/O] Tape" },
+        {.name = "VMR", .desc = "[I/O] Unit Record Devices" },
+        {.name = "LCS", .desc = "[I/O] LCS" },
+        {.name = "CLW", .desc = "[I/O] CLAW" },
+        {.name = "CTC", .desc = "[I/O] CTC" },
+        {.name = "APB", .desc = "[I/O] AP Bus" },
+        {.name = "NMI", .desc = "[NMI] Machine Check" },
+};
+
 /*
  * show_interrupts is needed by /proc/interrupts.
  */
 int show_interrupts(struct seq_file *p, void *v)
 {
-        static const char *intrclass_names[] = { "EXT", "I/O", };
         int i = *(loff_t *) v, j;
 
         get_online_cpus();
@@ -34,15 +62,16 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
-                seq_printf(p, "%s: ", intrclass_names[i]);
+                seq_printf(p, "%s: ", intrclass_names[i].name);
 #ifndef CONFIG_SMP
                 seq_printf(p, "%10u ", kstat_irqs(i));
 #else
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
 #endif
+                if (intrclass_names[i].desc)
+                        seq_printf(p, "  %s", intrclass_names[i].desc);
                 seq_putc(p, '\n');
-
         }
         put_online_cpus();
         return 0;
diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c
index 2564793ec2b6..1d05d669107c 100644
--- a/arch/s390/kernel/kprobes.c
+++ b/arch/s390/kernel/kprobes.c
@@ -32,34 +32,14 @@
 #include <linux/slab.h>
 #include <linux/hardirq.h>
 
-DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL;
+DEFINE_PER_CPU(struct kprobe *, current_kprobe);
 DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
 
-struct kretprobe_blackpoint kretprobe_blacklist[] = {{NULL, NULL}};
+struct kretprobe_blackpoint kretprobe_blacklist[] = { };
 
-int __kprobes arch_prepare_kprobe(struct kprobe *p)
-{
-        /* Make sure the probe isn't going on a difficult instruction */
-        if (is_prohibited_opcode((kprobe_opcode_t *) p->addr))
-                return -EINVAL;
-
-        if ((unsigned long)p->addr & 0x01)
-                return -EINVAL;
-
-        /* Use the get_insn_slot() facility for correctness */
-        if (!(p->ainsn.insn = get_insn_slot()))
-                return -ENOMEM;
-
-        memcpy(p->ainsn.insn, p->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
-
-        get_instruction_type(&p->ainsn);
-        p->opcode = *p->addr;
-        return 0;
-}
-
-int __kprobes is_prohibited_opcode(kprobe_opcode_t *instruction)
+static int __kprobes is_prohibited_opcode(kprobe_opcode_t *insn)
 {
-        switch (*(__u8 *) instruction) {
+        switch (insn[0] >> 8) {
         case 0x0c:      /* bassm */
         case 0x0b:      /* bsm   */
         case 0x83:      /* diag  */
@@ -68,7 +48,7 @@ int __kprobes is_prohibited_opcode(kprobe_opcode_t *instruction)
         case 0xad:      /* stosm */
                 return -EINVAL;
         }
-        switch (*(__u16 *) instruction) {
+        switch (insn[0]) {
         case 0x0101:    /* pr    */
         case 0xb25a:    /* bsa   */
         case 0xb240:    /* bakr  */
@@ -81,93 +61,92 @@ int __kprobes is_prohibited_opcode(kprobe_opcode_t *instruction)
         return 0;
 }
 
-void __kprobes get_instruction_type(struct arch_specific_insn *ainsn)
+static int __kprobes get_fixup_type(kprobe_opcode_t *insn)
 {
         /* default fixup method */
-        ainsn->fixup = FIXUP_PSW_NORMAL;
-
-        /* save r1 operand */
-        ainsn->reg = (*ainsn->insn & 0xf0) >> 4;
+        int fixup = FIXUP_PSW_NORMAL;
 
-        /* save the instruction length (pop 5-5) in bytes */
-        switch (*(__u8 *) (ainsn->insn) >> 6) {
-        case 0:
-                ainsn->ilen = 2;
-                break;
-        case 1:
-        case 2:
-                ainsn->ilen = 4;
-                break;
-        case 3:
-                ainsn->ilen = 6;
-                break;
-        }
-
-        switch (*(__u8 *) ainsn->insn) {
+        switch (insn[0] >> 8) {
         case 0x05:      /* balr */
         case 0x0d:      /* basr */
-                ainsn->fixup = FIXUP_RETURN_REGISTER;
+                fixup = FIXUP_RETURN_REGISTER;
                 /* if r2 = 0, no branch will be taken */
-                if ((*ainsn->insn & 0x0f) == 0)
-                        ainsn->fixup |= FIXUP_BRANCH_NOT_TAKEN;
+                if ((insn[0] & 0x0f) == 0)
+                        fixup |= FIXUP_BRANCH_NOT_TAKEN;
                 break;
         case 0x06:      /* bctr */
         case 0x07:      /* bcr  */
-                ainsn->fixup = FIXUP_BRANCH_NOT_TAKEN;
+                fixup = FIXUP_BRANCH_NOT_TAKEN;
                 break;
         case 0x45:      /* bal  */
         case 0x4d:      /* bas  */
-                ainsn->fixup = FIXUP_RETURN_REGISTER;
+                fixup = FIXUP_RETURN_REGISTER;
                 break;
         case 0x47:      /* bc   */
         case 0x46:      /* bct  */
         case 0x86:      /* bxh  */
         case 0x87:      /* bxle */
-                ainsn->fixup = FIXUP_BRANCH_NOT_TAKEN;
+                fixup = FIXUP_BRANCH_NOT_TAKEN;
                 break;
         case 0x82:      /* lpsw */
-                ainsn->fixup = FIXUP_NOT_REQUIRED;
+                fixup = FIXUP_NOT_REQUIRED;
                 break;
         case 0xb2:      /* lpswe */
-                if (*(((__u8 *) ainsn->insn) + 1) == 0xb2) {
-                        ainsn->fixup = FIXUP_NOT_REQUIRED;
-                }
+                if ((insn[0] & 0xff) == 0xb2)
+                        fixup = FIXUP_NOT_REQUIRED;
                 break;
         case 0xa7:      /* bras */
-                if ((*ainsn->insn & 0x0f) == 0x05) {
-                        ainsn->fixup |= FIXUP_RETURN_REGISTER;
-                }
+                if ((insn[0] & 0x0f) == 0x05)
+                        fixup |= FIXUP_RETURN_REGISTER;
                 break;
         case 0xc0:
-                if ((*ainsn->insn & 0x0f) == 0x00  /* larl  */
-                        || (*ainsn->insn & 0x0f) == 0x05) /* brasl */
-                ainsn->fixup |= FIXUP_RETURN_REGISTER;
+                if ((insn[0] & 0x0f) == 0x00 || /* larl  */
+                    (insn[0] & 0x0f) == 0x05)   /* brasl */
+                fixup |= FIXUP_RETURN_REGISTER;
                 break;
         case 0xeb:
-                if (*(((__u8 *) ainsn->insn) + 5 ) == 0x44 ||   /* bxhg  */
-                        *(((__u8 *) ainsn->insn) + 5) == 0x45) {/* bxleg */
-                        ainsn->fixup = FIXUP_BRANCH_NOT_TAKEN;
-                }
+                if ((insn[2] & 0xff) == 0x44 || /* bxhg  */
+                    (insn[2] & 0xff) == 0x45)   /* bxleg */
+                        fixup = FIXUP_BRANCH_NOT_TAKEN;
                 break;
         case 0xe3:      /* bctg */
-                if (*(((__u8 *) ainsn->insn) + 5) == 0x46) {
-                        ainsn->fixup = FIXUP_BRANCH_NOT_TAKEN;
-                }
+                if ((insn[2] & 0xff) == 0x46)
+                        fixup = FIXUP_BRANCH_NOT_TAKEN;
                 break;
         }
+        return fixup;
+}
+
+int __kprobes arch_prepare_kprobe(struct kprobe *p)
+{
+        if ((unsigned long) p->addr & 0x01)
+                return -EINVAL;
+
+        /* Make sure the probe isn't going on a difficult instruction */
+        if (is_prohibited_opcode(p->addr))
+                return -EINVAL;
+
+        p->opcode = *p->addr;
+        memcpy(p->ainsn.insn, p->addr, ((p->opcode >> 14) + 3) & -2);
+
+        return 0;
 }
 
+struct ins_replace_args {
+        kprobe_opcode_t *ptr;
+        kprobe_opcode_t opcode;
+};
+
 static int __kprobes swap_instruction(void *aref)
 {
         struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
         unsigned long status = kcb->kprobe_status;
         struct ins_replace_args *args = aref;
-        int rc;
 
         kcb->kprobe_status = KPROBE_SWAP_INST;
-        rc = probe_kernel_write(args->ptr, &args->new, sizeof(args->new));
+        probe_kernel_write(args->ptr, &args->opcode, sizeof(args->opcode));
         kcb->kprobe_status = status;
-        return rc;
+        return 0;
 }
 
 void __kprobes arch_arm_kprobe(struct kprobe *p)
@@ -175,8 +154,7 @@ void __kprobes arch_arm_kprobe(struct kprobe *p)
         struct ins_replace_args args;
 
         args.ptr = p->addr;
-        args.old = p->opcode;
-        args.new = BREAKPOINT_INSTRUCTION;
+        args.opcode = BREAKPOINT_INSTRUCTION;
         stop_machine(swap_instruction, &args, NULL);
 }
 
@@ -185,64 +163,69 @@ void __kprobes arch_disarm_kprobe(struct kprobe *p)
         struct ins_replace_args args;
 
         args.ptr = p->addr;
-        args.old = BREAKPOINT_INSTRUCTION;
-        args.new = p->opcode;
+        args.opcode = p->opcode;
         stop_machine(swap_instruction, &args, NULL);
 }
 
 void __kprobes arch_remove_kprobe(struct kprobe *p)
 {
-        if (p->ainsn.insn) {
-                free_insn_slot(p->ainsn.insn, 0);
-                p->ainsn.insn = NULL;
-        }
 }
 
-static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
+static void __kprobes enable_singlestep(struct kprobe_ctlblk *kcb,
+                                        struct pt_regs *regs,
+                                        unsigned long ip)
 {
-        per_cr_bits kprobe_per_regs[1];
+        struct per_regs per_kprobe;
 
-        memset(kprobe_per_regs, 0, sizeof(per_cr_bits));
-        regs->psw.addr = (unsigned long)p->ainsn.insn | PSW_ADDR_AMODE;
+        /* Set up the PER control registers %cr9-%cr11 */
+        per_kprobe.control = PER_EVENT_IFETCH;
+        per_kprobe.start = ip;
+        per_kprobe.end = ip;
 
-        /* Set up the per control reg info, will pass to lctl */
-        kprobe_per_regs[0].em_instruction_fetch = 1;
-        kprobe_per_regs[0].starting_addr = (unsigned long)p->ainsn.insn;
-        kprobe_per_regs[0].ending_addr = (unsigned long)p->ainsn.insn + 1;
+        /* Save control regs and psw mask */
+        __ctl_store(kcb->kprobe_saved_ctl, 9, 11);
+        kcb->kprobe_saved_imask = regs->psw.mask &
+                (PSW_MASK_PER | PSW_MASK_IO | PSW_MASK_EXT);
 
-        /* Set the PER control regs, turns on single step for this address */
-        __ctl_load(kprobe_per_regs, 9, 11);
+        /* Set PER control regs, turns on single step for the given address */
+        __ctl_load(per_kprobe, 9, 11);
         regs->psw.mask |= PSW_MASK_PER;
         regs->psw.mask &= ~(PSW_MASK_IO | PSW_MASK_EXT);
+        regs->psw.addr = ip | PSW_ADDR_AMODE;
 }
 
-static void __kprobes save_previous_kprobe(struct kprobe_ctlblk *kcb)
+static void __kprobes disable_singlestep(struct kprobe_ctlblk *kcb,
+                                         struct pt_regs *regs,
+                                         unsigned long ip)
 {
-        kcb->prev_kprobe.kp = kprobe_running();
-        kcb->prev_kprobe.status = kcb->kprobe_status;
-        kcb->prev_kprobe.kprobe_saved_imask = kcb->kprobe_saved_imask;
-        memcpy(kcb->prev_kprobe.kprobe_saved_ctl, kcb->kprobe_saved_ctl,
-                                        sizeof(kcb->kprobe_saved_ctl));
+        /* Restore control regs and psw mask, set new psw address */
+        __ctl_load(kcb->kprobe_saved_ctl, 9, 11);
+        regs->psw.mask &= ~PSW_MASK_PER;
+        regs->psw.mask |= kcb->kprobe_saved_imask;
+        regs->psw.addr = ip | PSW_ADDR_AMODE;
 }
 
-static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb)
+/*
+ * Activate a kprobe by storing its pointer to current_kprobe. The
+ * previous kprobe is stored in kcb->prev_kprobe. A stack of up to
+ * two kprobes can be active, see KPROBE_REENTER.
+ */
+static void __kprobes push_kprobe(struct kprobe_ctlblk *kcb, struct kprobe *p)
 {
-        __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp;
-        kcb->kprobe_status = kcb->prev_kprobe.status;
-        kcb->kprobe_saved_imask = kcb->prev_kprobe.kprobe_saved_imask;
-        memcpy(kcb->kprobe_saved_ctl, kcb->prev_kprobe.kprobe_saved_ctl,
-                                        sizeof(kcb->kprobe_saved_ctl));
+        kcb->prev_kprobe.kp = __get_cpu_var(current_kprobe);
+        kcb->prev_kprobe.status = kcb->kprobe_status;
+        __get_cpu_var(current_kprobe) = p;
 }
 
-static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
-                                                struct kprobe_ctlblk *kcb)
+/*
+ * Deactivate a kprobe by backing up to the previous state. If the
+ * current state is KPROBE_REENTER prev_kprobe.kp will be non-NULL,
+ * for any other state prev_kprobe.kp will be NULL.
+ */
+static void __kprobes pop_kprobe(struct kprobe_ctlblk *kcb)
 {
-        __get_cpu_var(current_kprobe) = p;
-        /* Save the interrupt and per flags */
-        kcb->kprobe_saved_imask = regs->psw.mask &
-                (PSW_MASK_PER | PSW_MASK_IO | PSW_MASK_EXT);
-        /* Save the control regs that govern PER */
-        __ctl_store(kcb->kprobe_saved_ctl, 9, 11);
+        __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp;
+        kcb->kprobe_status = kcb->prev_kprobe.status;
 }
 
 void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
@@ -251,79 +234,104 @@ void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
         ri->ret_addr = (kprobe_opcode_t *) regs->gprs[14];
 
         /* Replace the return addr with trampoline addr */
-        regs->gprs[14] = (unsigned long)&kretprobe_trampoline;
+        regs->gprs[14] = (unsigned long) &kretprobe_trampoline;
+}
+
+static void __kprobes kprobe_reenter_check(struct kprobe_ctlblk *kcb,
+                                           struct kprobe *p)
+{
+        switch (kcb->kprobe_status) {
+        case KPROBE_HIT_SSDONE:
+        case KPROBE_HIT_ACTIVE:
+                kprobes_inc_nmissed_count(p);
+                break;
+        case KPROBE_HIT_SS:
+        case KPROBE_REENTER:
+        default:
+                /*
+                 * A kprobe on the code path to single step an instruction
+                 * is a BUG. The code path resides in the .kprobes.text
+                 * section and is executed with interrupts disabled.
+                 */
+                printk(KERN_EMERG "Invalid kprobe detected at %p.\n", p->addr);
+                dump_kprobe(p);
+                BUG();
+        }
 }
 
 static int __kprobes kprobe_handler(struct pt_regs *regs)
 {
-        struct kprobe *p;
-        int ret = 0;
-        unsigned long *addr = (unsigned long *)
-                ((regs->psw.addr & PSW_ADDR_INSN) - 2);
         struct kprobe_ctlblk *kcb;
+        struct kprobe *p;
 
         /*
-         * We don't want to be preempted for the entire
-         * duration of kprobe processing
+         * We want to disable preemption for the entire duration of kprobe
+         * processing. That includes the calls to the pre/post handlers
+         * and single stepping the kprobe instruction.
          */
         preempt_disable();
         kcb = get_kprobe_ctlblk();
+        p = get_kprobe((void *)((regs->psw.addr & PSW_ADDR_INSN) - 2));
 
-        /* Check we're not actually recursing */
-        if (kprobe_running()) {
-                p = get_kprobe(addr);
-                if (p) {
-                        if (kcb->kprobe_status == KPROBE_HIT_SS &&
-                            *p->ainsn.insn == BREAKPOINT_INSTRUCTION) {
-                                regs->psw.mask &= ~PSW_MASK_PER;
-                                regs->psw.mask |= kcb->kprobe_saved_imask;
-                                goto no_kprobe;
-                        }
-                        /* We have reentered the kprobe_handler(), since
-                         * another probe was hit while within the handler.
-                         * We here save the original kprobes variables and
-                         * just single step on the instruction of the new probe
-                         * without calling any user handlers.
+        if (p) {
+                if (kprobe_running()) {
+                        /*
+                         * We have hit a kprobe while another is still
+                         * active. This can happen in the pre and post
+                         * handler. Single step the instruction of the
+                         * new probe but do not call any handler function
+                         * of this secondary kprobe.
+                         * push_kprobe and pop_kprobe saves and restores
+                         * the currently active kprobe.
                          */
-                        save_previous_kprobe(kcb);
-                        set_current_kprobe(p, regs, kcb);
-                        kprobes_inc_nmissed_count(p);
-                        prepare_singlestep(p, regs);
+                        kprobe_reenter_check(kcb, p);
+                        push_kprobe(kcb, p);
                         kcb->kprobe_status = KPROBE_REENTER;
-                        return 1;
                 } else {
-                        p = __get_cpu_var(current_kprobe);
-                        if (p->break_handler && p->break_handler(p, regs)) {
-                                goto ss_probe;
-                        }
+                        /*
+                         * If we have no pre-handler or it returned 0, we
+                         * continue with single stepping. If we have a
+                         * pre-handler and it returned non-zero, it prepped
+                         * for calling the break_handler below on re-entry
+                         * for jprobe processing, so get out doing nothing
+                         * more here.
+                         */
+                        push_kprobe(kcb, p);
+                        kcb->kprobe_status = KPROBE_HIT_ACTIVE;
+                        if (p->pre_handler && p->pre_handler(p, regs))
+                                return 1;
+                        kcb->kprobe_status = KPROBE_HIT_SS;
                 }
-                goto no_kprobe;
-        }
-
-        p = get_kprobe(addr);
-        if (!p)
-                /*
-                 * No kprobe at this address. The fault has not been
-                 * caused by a kprobe breakpoint. The race of breakpoint
-                 * vs. kprobe remove does not exist because on s390 we
-                 * use stop_machine to arm/disarm the breakpoints.
-                 */
-                goto no_kprobe;
-
-        kcb->kprobe_status = KPROBE_HIT_ACTIVE;
-        set_current_kprobe(p, regs, kcb);
-        if (p->pre_handler && p->pre_handler(p, regs))
-                /* handler has already set things up, so skip ss setup */
+                enable_singlestep(kcb, regs, (unsigned long) p->ainsn.insn);
                 return 1;
-
-ss_probe:
-        prepare_singlestep(p, regs);
-        kcb->kprobe_status = KPROBE_HIT_SS;
-        return 1;
-
-no_kprobe:
+        } else if (kprobe_running()) {
+                p = __get_cpu_var(current_kprobe);
+                if (p->break_handler && p->break_handler(p, regs)) {
+                        /*
+                         * Continuation after the jprobe completed and
+                         * caused the jprobe_return trap. The jprobe
+                         * break_handler "returns" to the original
+                         * function that still has the kprobe breakpoint
+                         * installed. We continue with single stepping.
+                         */
+                        kcb->kprobe_status = KPROBE_HIT_SS;
+                        enable_singlestep(kcb, regs,
+                                          (unsigned long) p->ainsn.insn);
+                        return 1;
+                } /* else:
+                   * No kprobe at this address and the current kprobe
+                   * has no break handler (no jprobe!). The kernel just
+                   * exploded, let the standard trap handler pick up the
+                   * pieces.
+                   */
+        } /* else:
+           * No kprobe at this address and no active kprobe. The trap has
+           * not been caused by a kprobe breakpoint. The race of breakpoint
+           * vs. kprobe remove does not exist because on s390 as we use
+           * stop_machine to arm/disarm the breakpoints.
+           */
         preempt_enable_no_resched();
-        return ret;
+        return 0;
 }
 
 /*
@@ -344,12 +352,12 @@ static void __used kretprobe_trampoline_holder(void)
 static int __kprobes trampoline_probe_handler(struct kprobe *p,
                                               struct pt_regs *regs)
 {
-        struct kretprobe_instance *ri = NULL;
+        struct kretprobe_instance *ri;
         struct hlist_head *head, empty_rp;
         struct hlist_node *node, *tmp;
-        unsigned long flags, orig_ret_address = 0;
-        unsigned long trampoline_address = (unsigned long)&kretprobe_trampoline;
-        kprobe_opcode_t *correct_ret_addr = NULL;
+        unsigned long flags, orig_ret_address;
+        unsigned long trampoline_address;
+        kprobe_opcode_t *correct_ret_addr;
 
         INIT_HLIST_HEAD(&empty_rp);
         kretprobe_hash_lock(current, &head, &flags);
@@ -367,12 +375,16 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p,
          *       real return address, and all the rest will point to
          *       kretprobe_trampoline
          */
+        ri = NULL;
+        orig_ret_address = 0;
+        correct_ret_addr = NULL;
+        trampoline_address = (unsigned long) &kretprobe_trampoline;
         hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
                 if (ri->task != current)
                         /* another task is sharing our hash bucket */
                         continue;
 
-                orig_ret_address = (unsigned long)ri->ret_addr;
+                orig_ret_address = (unsigned long) ri->ret_addr;
 
                 if (orig_ret_address != trampoline_address)
                         /*
@@ -391,7 +403,7 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p,
                         /* another task is sharing our hash bucket */
                         continue;
 
-                orig_ret_address = (unsigned long)ri->ret_addr;
+                orig_ret_address = (unsigned long) ri->ret_addr;
 
                 if (ri->rp && ri->rp->handler) {
                         ri->ret_addr = correct_ret_addr;
@@ -400,19 +412,18 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p,
 
                 recycle_rp_inst(ri, &empty_rp);
 
-                if (orig_ret_address != trampoline_address) {
+                if (orig_ret_address != trampoline_address)
                         /*
                          * This is the real return address. Any other
                          * instances associated with this task are for
                          * other calls deeper on the call stack
                          */
                         break;
-                }
         }
 
         regs->psw.addr = orig_ret_address | PSW_ADDR_AMODE;
 
-        reset_current_kprobe();
+        pop_kprobe(get_kprobe_ctlblk());
         kretprobe_hash_unlock(current, &flags);
         preempt_enable_no_resched();
 
@@ -439,55 +450,42 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p,
 static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs)
 {
         struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+        unsigned long ip = regs->psw.addr & PSW_ADDR_INSN;
+        int fixup = get_fixup_type(p->ainsn.insn);
 
-        regs->psw.addr &= PSW_ADDR_INSN;
-
-        if (p->ainsn.fixup & FIXUP_PSW_NORMAL)
-                regs->psw.addr = (unsigned long)p->addr +
-                                ((unsigned long)regs->psw.addr -
-                                 (unsigned long)p->ainsn.insn);
+        if (fixup & FIXUP_PSW_NORMAL)
+                ip += (unsigned long) p->addr - (unsigned long) p->ainsn.insn;
 
-        if (p->ainsn.fixup & FIXUP_BRANCH_NOT_TAKEN)
-                if ((unsigned long)regs->psw.addr -
-                    (unsigned long)p->ainsn.insn == p->ainsn.ilen)
-                        regs->psw.addr = (unsigned long)p->addr + p->ainsn.ilen;
+        if (fixup & FIXUP_BRANCH_NOT_TAKEN) {
+                int ilen = ((p->ainsn.insn[0] >> 14) + 3) & -2;
+                if (ip - (unsigned long) p->ainsn.insn == ilen)
+                        ip = (unsigned long) p->addr + ilen;
+        }
 
-        if (p->ainsn.fixup & FIXUP_RETURN_REGISTER)
-                regs->gprs[p->ainsn.reg] = ((unsigned long)p->addr +
-                                                (regs->gprs[p->ainsn.reg] -
-                                                (unsigned long)p->ainsn.insn))
-                                                | PSW_ADDR_AMODE;
+        if (fixup & FIXUP_RETURN_REGISTER) {
+                int reg = (p->ainsn.insn[0] & 0xf0) >> 4;
+                regs->gprs[reg] += (unsigned long) p->addr -
+                                   (unsigned long) p->ainsn.insn;
+        }
 
-        regs->psw.addr |= PSW_ADDR_AMODE;
-        /* turn off PER mode */
-        regs->psw.mask &= ~PSW_MASK_PER;
-        /* Restore the original per control regs */
-        __ctl_load(kcb->kprobe_saved_ctl, 9, 11);
-        regs->psw.mask |= kcb->kprobe_saved_imask;
+        disable_singlestep(kcb, regs, ip);
 }
 
 static int __kprobes post_kprobe_handler(struct pt_regs *regs)
 {
-        struct kprobe *cur = kprobe_running();
         struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+        struct kprobe *p = kprobe_running();
 
-        if (!cur)
+        if (!p)
                 return 0;
 
-        if ((kcb->kprobe_status != KPROBE_REENTER) && cur->post_handler) {
+        if (kcb->kprobe_status != KPROBE_REENTER && p->post_handler) {
                 kcb->kprobe_status = KPROBE_HIT_SSDONE;
-                cur->post_handler(cur, regs, 0);
+                p->post_handler(p, regs, 0);
         }
 
-        resume_execution(cur, regs);
-
-        /*Restore back the original saved kprobes variables and continue. */
-        if (kcb->kprobe_status == KPROBE_REENTER) {
-                restore_previous_kprobe(kcb);
-                goto out;
-        }
-        reset_current_kprobe();
-out:
+        resume_execution(p, regs);
+        pop_kprobe(kcb);
         preempt_enable_no_resched();
 
         /*
@@ -495,17 +493,16 @@ out:
          * will have PER set, in which case, continue the remaining processing
          * of do_single_step, as if this is not a probe hit.
          */
-        if (regs->psw.mask & PSW_MASK_PER) {
+        if (regs->psw.mask & PSW_MASK_PER)
                 return 0;
-        }
 
         return 1;
 }
 
 static int __kprobes kprobe_trap_handler(struct pt_regs *regs, int trapnr)
 {
-        struct kprobe *cur = kprobe_running();
         struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+        struct kprobe *p = kprobe_running();
         const struct exception_table_entry *entry;
 
         switch(kcb->kprobe_status) {
@@ -521,14 +518,8 @@ static int __kprobes kprobe_trap_handler(struct pt_regs *regs, int trapnr)
                  * and allow the page fault handler to continue as a
                  * normal page fault.
                  */
-                regs->psw.addr = (unsigned long)cur->addr | PSW_ADDR_AMODE;
-                regs->psw.mask &= ~PSW_MASK_PER;
-                regs->psw.mask |= kcb->kprobe_saved_imask;
-                if (kcb->kprobe_status == KPROBE_REENTER)
-                        restore_previous_kprobe(kcb);
-                else {
-                        reset_current_kprobe();
-                }
+                disable_singlestep(kcb, regs, (unsigned long) p->addr);
+                pop_kprobe(kcb);
                 preempt_enable_no_resched();
                 break;
         case KPROBE_HIT_ACTIVE:
@@ -538,7 +529,7 @@ static int __kprobes kprobe_trap_handler(struct pt_regs *regs, int trapnr)
                  * we can also use npre/npostfault count for accouting
                  * these specific fault cases.
                  */
-                kprobes_inc_nmissed_count(cur);
+                kprobes_inc_nmissed_count(p);
 
                 /*
                  * We come here because instructions in the pre/post
@@ -547,7 +538,7 @@ static int __kprobes kprobe_trap_handler(struct pt_regs *regs, int trapnr)
                  * copy_from_user(), get_user() etc. Let the
                  * user-specified handler try to fix it first.
                  */
-                if (cur->fault_handler && cur->fault_handler(cur, regs, trapnr))
+                if (p->fault_handler && p->fault_handler(p, regs, trapnr))
                         return 1;
 
                 /*
@@ -589,7 +580,7 @@ int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr)
 int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
                                        unsigned long val, void *data)
 {
-        struct die_args *args = (struct die_args *)data;
+        struct die_args *args = (struct die_args *) data;
         struct pt_regs *regs = args->regs;
         int ret = NOTIFY_DONE;
 
@@ -598,16 +589,16 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
 
         switch (val) {
         case DIE_BPT:
-                if (kprobe_handler(args->regs))
+                if (kprobe_handler(regs))
                         ret = NOTIFY_STOP;
                 break;
         case DIE_SSTEP:
-                if (post_kprobe_handler(args->regs))
+                if (post_kprobe_handler(regs))
                         ret = NOTIFY_STOP;
                 break;
         case DIE_TRAP:
                 if (!preemptible() && kprobe_running() &&
-                    kprobe_trap_handler(args->regs, args->trapnr))
+                    kprobe_trap_handler(regs, args->trapnr))
                         ret = NOTIFY_STOP;
                 break;
         default:
@@ -623,23 +614,19 @@ int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
 int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
 {
         struct jprobe *jp = container_of(p, struct jprobe, kp);
-        unsigned long addr;
         struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
+        unsigned long stack;
 
         memcpy(&kcb->jprobe_saved_regs, regs, sizeof(struct pt_regs));
 
         /* setup return addr to the jprobe handler routine */
-        regs->psw.addr = (unsigned long)(jp->entry) | PSW_ADDR_AMODE;
+        regs->psw.addr = (unsigned long) jp->entry | PSW_ADDR_AMODE;
         regs->psw.mask &= ~(PSW_MASK_IO | PSW_MASK_EXT);
 
-        /* r14 is the function return address */
-        kcb->jprobe_saved_r14 = (unsigned long)regs->gprs[14];
         /* r15 is the stack pointer */
-        kcb->jprobe_saved_r15 = (unsigned long)regs->gprs[15];
-        addr = (unsigned long)kcb->jprobe_saved_r15;
+        stack = (unsigned long) regs->gprs[15];
 
-        memcpy(kcb->jprobes_stack, (kprobe_opcode_t *) addr,
-               MIN_STACK_SIZE(addr));
+        memcpy(kcb->jprobes_stack, (void *) stack, MIN_STACK_SIZE(stack));
         return 1;
 }
 
@@ -656,30 +643,29 @@ void __kprobes jprobe_return_end(void)
 int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
 {
         struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
-        unsigned long stack_addr = (unsigned long)(kcb->jprobe_saved_r15);
+        unsigned long stack;
+
+        stack = (unsigned long) kcb->jprobe_saved_regs.gprs[15];
 
         /* Put the regs back */
         memcpy(regs, &kcb->jprobe_saved_regs, sizeof(struct pt_regs));
         /* put the stack back */
-        memcpy((kprobe_opcode_t *) stack_addr, kcb->jprobes_stack,
-               MIN_STACK_SIZE(stack_addr));
+        memcpy((void *) stack, kcb->jprobes_stack, MIN_STACK_SIZE(stack));
         preempt_enable_no_resched();
         return 1;
 }
 
-static struct kprobe trampoline_p = {
-        .addr = (kprobe_opcode_t *) & kretprobe_trampoline,
+static struct kprobe trampoline = {
+        .addr = (kprobe_opcode_t *) &kretprobe_trampoline,
         .pre_handler = trampoline_probe_handler
 };
 
 int __init arch_init_kprobes(void)
 {
-        return register_kprobe(&trampoline_p);
+        return register_kprobe(&trampoline);
 }
 
 int __kprobes arch_trampoline_kprobe(struct kprobe *p)
 {
-        if (p->addr == (kprobe_opcode_t *) & kretprobe_trampoline)
-                return 1;
-        return 0;
+        return p->addr == (kprobe_opcode_t *) &kretprobe_trampoline;
 }
diff --git a/arch/s390/kernel/mcount.S b/arch/s390/kernel/mcount.S
index dfe015d7398c..1e6a55795628 100644
--- a/arch/s390/kernel/mcount.S
+++ b/arch/s390/kernel/mcount.S
@@ -7,6 +7,8 @@
 
 #include <asm/asm-offsets.h>
 
+        .section .kprobes.text, "ax"
+
         .globl ftrace_stub
 ftrace_stub:
         br      %r14
@@ -16,22 +18,12 @@ _mcount:
 #ifdef CONFIG_DYNAMIC_FTRACE
         br      %r14
 
-        .data
-        .globl  ftrace_dyn_func
-ftrace_dyn_func:
-        .long   ftrace_stub
-        .previous
-
         .globl ftrace_caller
 ftrace_caller:
 #endif
         stm     %r2,%r5,16(%r15)
         bras    %r1,2f
-#ifdef CONFIG_DYNAMIC_FTRACE
-0:      .long   ftrace_dyn_func
-#else
 0:      .long   ftrace_trace_function
-#endif
 1:      .long   function_trace_stop
 2:      l       %r2,1b-0b(%r1)
         icm     %r2,0xf,0(%r2)
@@ -47,21 +39,15 @@ ftrace_caller:
         l       %r14,0(%r14)
         basr    %r14,%r14
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
-#ifdef CONFIG_DYNAMIC_FTRACE
+        l       %r2,100(%r15)
+        l       %r3,152(%r15)
         .globl  ftrace_graph_caller
 ftrace_graph_caller:
-        # This unconditional branch gets runtime patched. Change only if
-        # you know what you are doing. See ftrace_enable_graph_caller().
-        j       1f
-#endif
-        bras    %r1,0f
-        .long   prepare_ftrace_return
-0:      l       %r2,152(%r15)
-        l       %r4,0(%r1)
-        l       %r3,100(%r15)
-        basr    %r14,%r4
-        st      %r2,100(%r15)
-1:
+# The bras instruction gets runtime patched to call prepare_ftrace_return.
+# See ftrace_enable_ftrace_graph_caller. The patched instruction is:
+#       bras    %r14,prepare_ftrace_return
+        bras    %r14,0f
+0:      st      %r2,100(%r15)
 #endif
         ahi     %r15,96
         l       %r14,56(%r15)
diff --git a/arch/s390/kernel/mcount64.S b/arch/s390/kernel/mcount64.S
index c37211c6092b..e73667286ac0 100644
--- a/arch/s390/kernel/mcount64.S
+++ b/arch/s390/kernel/mcount64.S
@@ -7,6 +7,8 @@
 
 #include <asm/asm-offsets.h>
 
+        .section .kprobes.text, "ax"
+
         .globl ftrace_stub
 ftrace_stub:
         br      %r14
@@ -16,12 +18,6 @@ _mcount:
 #ifdef CONFIG_DYNAMIC_FTRACE
         br      %r14
 
-        .data
-        .globl  ftrace_dyn_func
-ftrace_dyn_func:
-        .quad   ftrace_stub
-        .previous
-
         .globl ftrace_caller
 ftrace_caller:
 #endif
@@ -35,26 +31,19 @@ ftrace_caller:
         stg     %r1,__SF_BACKCHAIN(%r15)
         lgr     %r2,%r14
         lg      %r3,168(%r15)
-#ifdef CONFIG_DYNAMIC_FTRACE
-        larl    %r14,ftrace_dyn_func
-#else
         larl    %r14,ftrace_trace_function
-#endif
         lg      %r14,0(%r14)
         basr    %r14,%r14
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
-#ifdef CONFIG_DYNAMIC_FTRACE
+        lg      %r2,168(%r15)
+        lg      %r3,272(%r15)
         .globl  ftrace_graph_caller
 ftrace_graph_caller:
-        # This unconditional branch gets runtime patched. Change only if
-        # you know what you are doing. See ftrace_enable_graph_caller().
-        j       0f
-#endif
-        lg      %r2,272(%r15)
-        lg      %r3,168(%r15)
-        brasl   %r14,prepare_ftrace_return
-        stg     %r2,168(%r15)
-0:
+# The bras instruction gets runtime patched to call prepare_ftrace_return.
+# See ftrace_enable_ftrace_graph_caller. The patched instruction is:
+#       bras    %r14,prepare_ftrace_return
+        bras    %r14,0f
+0:      stg     %r2,168(%r15)
 #endif
         aghi    %r15,160
         lmg     %r2,%r5,32(%r15)
diff --git a/arch/s390/kernel/nmi.c b/arch/s390/kernel/nmi.c
index 1995c1712fc8..fab88431a06f 100644
--- a/arch/s390/kernel/nmi.c
+++ b/arch/s390/kernel/nmi.c
@@ -8,6 +8,7 @@
  *               Heiko Carstens <heiko.carstens@de.ibm.com>,
  */
 
+#include <linux/kernel_stat.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/hardirq.h>
@@ -255,7 +256,7 @@ void notrace s390_do_machine_check(struct pt_regs *regs)
         nmi_enter();
         s390_idle_check(regs, S390_lowcore.mcck_clock,
                         S390_lowcore.mcck_enter_timer);
-
+        kstat_cpu(smp_processor_id()).irqs[NMI_NMI]++;
         mci = (struct mci *) &S390_lowcore.mcck_interruption_code;
         mcck = &__get_cpu_var(cpu_mcck);
         umode = user_mode(regs);
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index ec2e03b22ead..6ba42222b542 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -32,6 +32,7 @@
 #include <linux/kernel_stat.h>
 #include <linux/syscalls.h>
 #include <linux/compat.h>
+#include <linux/kprobes.h>
 #include <asm/compat.h>
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
@@ -41,6 +42,7 @@
 #include <asm/irq.h>
 #include <asm/timer.h>
 #include <asm/nmi.h>
+#include <asm/smp.h>
 #include "entry.h"
 
 asmlinkage void ret_from_fork(void) asm ("ret_from_fork");
@@ -75,13 +77,8 @@ unsigned long thread_saved_pc(struct task_struct *tsk)
  */
 static void default_idle(void)
 {
-        /* CPU is going idle. */
-#ifdef CONFIG_HOTPLUG_CPU
-        if (cpu_is_offline(smp_processor_id())) {
-                preempt_enable_no_resched();
+        if (cpu_is_offline(smp_processor_id()))
                 cpu_die();
-        }
-#endif
         local_irq_disable();
         if (need_resched()) {
                 local_irq_enable();
@@ -116,15 +113,17 @@ void cpu_idle(void)
         }
 }
 
-extern void kernel_thread_starter(void);
+extern void __kprobes kernel_thread_starter(void);
 
 asm(
-        ".align 4\n"
+        ".section .kprobes.text, \"ax\"\n"
+        ".global kernel_thread_starter\n"
         "kernel_thread_starter:\n"
         "    la    2,0(10)\n"
         "    basr  14,9\n"
         "    la    2,0\n"
-        "    br    11\n");
+        "    br    11\n"
+        ".previous\n");
 
 int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
 {
@@ -214,8 +213,10 @@ int copy_thread(unsigned long clone_flags, unsigned long new_stackp,
         /* start new process with ar4 pointing to the correct address space */
         p->thread.mm_segment = get_fs();
         /* Don't copy debug registers */
-        memset(&p->thread.per_info, 0, sizeof(p->thread.per_info));
+        memset(&p->thread.per_user, 0, sizeof(p->thread.per_user));
+        memset(&p->thread.per_event, 0, sizeof(p->thread.per_event));
         clear_tsk_thread_flag(p, TIF_SINGLE_STEP);
+        clear_tsk_thread_flag(p, TIF_PER_TRAP);
         /* Initialize per thread user and system timer values */
         ti = task_thread_info(p);
         ti->user_timer = 0;
diff --git a/arch/s390/kernel/processor.c b/arch/s390/kernel/processor.c
index 644548e615c6..311e9d712888 100644
--- a/arch/s390/kernel/processor.c
+++ b/arch/s390/kernel/processor.c
@@ -13,7 +13,7 @@
 #include <linux/smp.h>
 #include <linux/seq_file.h>
 #include <linux/delay.h>
-
+#include <linux/cpu.h>
 #include <asm/elf.h>
 #include <asm/lowcore.h>
 #include <asm/param.h>
@@ -35,17 +35,6 @@ void __cpuinit cpu_init(void)
 }
 
 /*
- * print_cpu_info - print basic information about a cpu
- */
-void __cpuinit print_cpu_info(void)
-{
-        struct cpuid *id = &per_cpu(cpu_id, smp_processor_id());
-
-        pr_info("Processor %d started, address %d, identification %06X\n",
-                S390_lowcore.cpu_nr, stap(), id->ident);
-}
-
-/*
  * show_cpuinfo - Get information on one CPU for use by procfs.
  */
 static int show_cpuinfo(struct seq_file *m, void *v)
@@ -57,9 +46,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         unsigned long n = (unsigned long) v - 1;
         int i;
 
-        s390_adjust_jiffies();
-        preempt_disable();
         if (!n) {
+                s390_adjust_jiffies();
                 seq_printf(m, "vendor_id       : IBM/S390\n"
                            "# processors    : %i\n"
                            "bogomips per cpu: %lu.%02lu\n",
@@ -71,7 +59,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                                 seq_printf(m, "%s ", hwcap_str[i]);
                 seq_puts(m, "\n");
         }
-
+        get_online_cpus();
         if (cpu_online(n)) {
                 struct cpuid *id = &per_cpu(cpu_id, n);
                 seq_printf(m, "processor %li: "
@@ -80,7 +68,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                            "machine = %04X\n",
                            n, id->version, id->ident, id->machine);
         }
-        preempt_enable();
+        put_online_cpus();
         return 0;
 }
 
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index 019bb714db49..ef86ad243986 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -1,25 +1,9 @@
 /*
- *  arch/s390/kernel/ptrace.c
+ *  Ptrace user space interface.
  *
- *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
- *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
+ *    Copyright IBM Corp. 1999,2010
+ *    Author(s): Denis Joseph Barrow
  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
- *
- *  Based on PowerPC version 
- *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
- *
- *  Derived from "arch/m68k/kernel/ptrace.c"
- *  Copyright (C) 1994 by Hamish Macdonald
- *  Taken from linux/kernel/ptrace.c and modified for M680x0.
- *  linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
- *
- * Modified by Cort Dougan (cort@cs.nmt.edu) 
- *
- *
- * This file is subject to the terms and conditions of the GNU General
- * Public License.  See the file README.legal in the main directory of
- * this archive for more details.
  */
 
 #include <linux/kernel.h>
@@ -61,76 +45,58 @@ enum s390_regset {
         REGSET_GENERAL_EXTENDED,
 };
 
-static void
-FixPerRegisters(struct task_struct *task)
+void update_per_regs(struct task_struct *task)
 {
-        struct pt_regs *regs;
-        per_struct *per_info;
-        per_cr_words cr_words;
-
-        regs = task_pt_regs(task);
-        per_info = (per_struct *) &task->thread.per_info;
-        per_info->control_regs.bits.em_instruction_fetch =
-                per_info->single_step | per_info->instruction_fetch;
-        
-        if (per_info->single_step) {
-                per_info->control_regs.bits.starting_addr = 0;
-#ifdef CONFIG_COMPAT
-                if (is_compat_task())
-                        per_info->control_regs.bits.ending_addr = 0x7fffffffUL;
-                else
-#endif
-                        per_info->control_regs.bits.ending_addr = PSW_ADDR_INSN;
-        } else {
-                per_info->control_regs.bits.starting_addr =
-                        per_info->starting_addr;
-                per_info->control_regs.bits.ending_addr =
-                        per_info->ending_addr;
-        }
-        /*
-         * if any of the control reg tracing bits are on 
-         * we switch on per in the psw
-         */
-        if (per_info->control_regs.words.cr[0] & PER_EM_MASK)
-                regs->psw.mask |= PSW_MASK_PER;
-        else
+        static const struct per_regs per_single_step = {
+                .control = PER_EVENT_IFETCH,
+                .start = 0,
+                .end = PSW_ADDR_INSN,
+        };
+        struct pt_regs *regs = task_pt_regs(task);
+        struct thread_struct *thread = &task->thread;
+        const struct per_regs *new;
+        struct per_regs old;
+
+        /* TIF_SINGLE_STEP overrides the user specified PER registers. */
+        new = test_tsk_thread_flag(task, TIF_SINGLE_STEP) ?
+                &per_single_step : &thread->per_user;
+
+        /* Take care of the PER enablement bit in the PSW. */
+        if (!(new->control & PER_EVENT_MASK)) {
                 regs->psw.mask &= ~PSW_MASK_PER;
-
-        if (per_info->control_regs.bits.em_storage_alteration)
-                per_info->control_regs.bits.storage_alt_space_ctl = 1;
-        else
-                per_info->control_regs.bits.storage_alt_space_ctl = 0;
-
-        if (task == current) {
-                __ctl_store(cr_words, 9, 11);
-                if (memcmp(&cr_words, &per_info->control_regs.words,
-                           sizeof(cr_words)) != 0)
-                        __ctl_load(per_info->control_regs.words, 9, 11);
+                return;
         }
+        regs->psw.mask |= PSW_MASK_PER;
+        __ctl_store(old, 9, 11);
+        if (memcmp(new, &old, sizeof(struct per_regs)) != 0)
+                __ctl_load(*new, 9, 11);
 }
 
 void user_enable_single_step(struct task_struct *task)
 {
-        task->thread.per_info.single_step = 1;
-        FixPerRegisters(task);
+        set_tsk_thread_flag(task, TIF_SINGLE_STEP);
+        if (task == current)
+                update_per_regs(task);
 }
 
 void user_disable_single_step(struct task_struct *task)
 {
-        task->thread.per_info.single_step = 0;
-        FixPerRegisters(task);
+        clear_tsk_thread_flag(task, TIF_SINGLE_STEP);
+        if (task == current)
+                update_per_regs(task);
 }
 
 /*
  * Called by kernel/ptrace.c when detaching..
  *
- * Make sure single step bits etc are not set.
+ * Clear all debugging related fields.
  */
-void
-ptrace_disable(struct task_struct *child)
+void ptrace_disable(struct task_struct *task)
 {
-        /* make sure the single step bit is not set. */
-        user_disable_single_step(child);
+        memset(&task->thread.per_user, 0, sizeof(task->thread.per_user));
+        memset(&task->thread.per_event, 0, sizeof(task->thread.per_event));
+        clear_tsk_thread_flag(task, TIF_SINGLE_STEP);
+        clear_tsk_thread_flag(task, TIF_PER_TRAP);
 }
 
 #ifndef CONFIG_64BIT
@@ -139,6 +105,47 @@ ptrace_disable(struct task_struct *child)
 # define __ADDR_MASK 7
 #endif
 
+static inline unsigned long __peek_user_per(struct task_struct *child,
+                                            addr_t addr)
+{
+        struct per_struct_kernel *dummy = NULL;
+
+        if (addr == (addr_t) &dummy->cr9)
+                /* Control bits of the active per set. */
+                return test_thread_flag(TIF_SINGLE_STEP) ?
+                        PER_EVENT_IFETCH : child->thread.per_user.control;
+        else if (addr == (addr_t) &dummy->cr10)
+                /* Start address of the active per set. */
+                return test_thread_flag(TIF_SINGLE_STEP) ?
+                        0 : child->thread.per_user.start;
+        else if (addr == (addr_t) &dummy->cr11)
+                /* End address of the active per set. */
+                return test_thread_flag(TIF_SINGLE_STEP) ?
+                        PSW_ADDR_INSN : child->thread.per_user.end;
+        else if (addr == (addr_t) &dummy->bits)
+                /* Single-step bit. */
+                return test_thread_flag(TIF_SINGLE_STEP) ?
+                        (1UL << (BITS_PER_LONG - 1)) : 0;
+        else if (addr == (addr_t) &dummy->starting_addr)
+                /* Start address of the user specified per set. */
+                return child->thread.per_user.start;
+        else if (addr == (addr_t) &dummy->ending_addr)
+                /* End address of the user specified per set. */
+                return child->thread.per_user.end;
+        else if (addr == (addr_t) &dummy->perc_atmid)
+                /* PER code, ATMID and AI of the last PER trap */
+                return (unsigned long)
+                        child->thread.per_event.cause << (BITS_PER_LONG - 16);
+        else if (addr == (addr_t) &dummy->address)
+                /* Address of the last PER trap */
+                return child->thread.per_event.address;
+        else if (addr == (addr_t) &dummy->access_id)
+                /* Access id of the last PER trap */
+                return (unsigned long)
+                        child->thread.per_event.paid << (BITS_PER_LONG - 8);
+        return 0;
+}
+
 /*
  * Read the word at offset addr from the user area of a process. The
  * trouble here is that the information is littered over different
@@ -204,10 +211,10 @@ static unsigned long __peek_user(struct task_struct *child, addr_t addr)
 
         } else if (addr < (addr_t) (&dummy->regs.per_info + 1)) {
                 /*
-                 * per_info is found in the thread structure
+                 * Handle access to the per_info structure.
                  */
-                offset = addr - (addr_t) &dummy->regs.per_info;
-                tmp = *(addr_t *)((addr_t) &child->thread.per_info + offset);
+                addr -= (addr_t) &dummy->regs.per_info;
+                tmp = __peek_user_per(child, addr);
 
         } else
                 tmp = 0;
@@ -237,6 +244,35 @@ peek_user(struct task_struct *child, addr_t addr, addr_t data)
         return put_user(tmp, (addr_t __user *) data);
 }
 
+static inline void __poke_user_per(struct task_struct *child,
+                                   addr_t addr, addr_t data)
+{
+        struct per_struct_kernel *dummy = NULL;
+
+        /*
+         * There are only three fields in the per_info struct that the
+         * debugger user can write to.
+         * 1) cr9: the debugger wants to set a new PER event mask
+         * 2) starting_addr: the debugger wants to set a new starting
+         *    address to use with the PER event mask.
+         * 3) ending_addr: the debugger wants to set a new ending
+         *    address to use with the PER event mask.
+         * The user specified PER event mask and the start and end
+         * addresses are used only if single stepping is not in effect.
+         * Writes to any other field in per_info are ignored.
+         */
+        if (addr == (addr_t) &dummy->cr9)
+                /* PER event mask of the user specified per set. */
+                child->thread.per_user.control =
+                        data & (PER_EVENT_MASK | PER_CONTROL_MASK);
+        else if (addr == (addr_t) &dummy->starting_addr)
+                /* Starting address of the user specified per set. */
+                child->thread.per_user.start = data;
+        else if (addr == (addr_t) &dummy->ending_addr)
+                /* Ending address of the user specified per set. */
+                child->thread.per_user.end = data;
+}
+
 /*
  * Write a word to the user area of a process at location addr. This
  * operation does have an additional problem compared to peek_user.
@@ -311,19 +347,17 @@ static int __poke_user(struct task_struct *child, addr_t addr, addr_t data)
 
         } else if (addr < (addr_t) (&dummy->regs.per_info + 1)) {
                 /*
-                 * per_info is found in the thread structure 
+                 * Handle access to the per_info structure.
                  */
-                offset = addr - (addr_t) &dummy->regs.per_info;
-                *(addr_t *)((addr_t) &child->thread.per_info + offset) = data;
+                addr -= (addr_t) &dummy->regs.per_info;
+                __poke_user_per(child, addr, data);
 
         }
 
-        FixPerRegisters(child);
         return 0;
 }
 
-static int
-poke_user(struct task_struct *child, addr_t addr, addr_t data)
+static int poke_user(struct task_struct *child, addr_t addr, addr_t data)
 {
         addr_t mask;
 
@@ -410,12 +444,53 @@ long arch_ptrace(struct task_struct *child, long request,
  */
 
 /*
+ * Same as peek_user_per but for a 31 bit program.
+ */
+static inline __u32 __peek_user_per_compat(struct task_struct *child,
+                                           addr_t addr)
+{
+        struct compat_per_struct_kernel *dummy32 = NULL;
+
+        if (addr == (addr_t) &dummy32->cr9)
+                /* Control bits of the active per set. */
+                return (__u32) test_thread_flag(TIF_SINGLE_STEP) ?
+                        PER_EVENT_IFETCH : child->thread.per_user.control;
+        else if (addr == (addr_t) &dummy32->cr10)
+                /* Start address of the active per set. */
+                return (__u32) test_thread_flag(TIF_SINGLE_STEP) ?
+                        0 : child->thread.per_user.start;
+        else if (addr == (addr_t) &dummy32->cr11)
+                /* End address of the active per set. */
+                return test_thread_flag(TIF_SINGLE_STEP) ?
+                        PSW32_ADDR_INSN : child->thread.per_user.end;
+        else if (addr == (addr_t) &dummy32->bits)
+                /* Single-step bit. */
+                return (__u32) test_thread_flag(TIF_SINGLE_STEP) ?
+                        0x80000000 : 0;
+        else if (addr == (addr_t) &dummy32->starting_addr)
+                /* Start address of the user specified per set. */
+                return (__u32) child->thread.per_user.start;
+        else if (addr == (addr_t) &dummy32->ending_addr)
+                /* End address of the user specified per set. */
+                return (__u32) child->thread.per_user.end;
+        else if (addr == (addr_t) &dummy32->perc_atmid)
+                /* PER code, ATMID and AI of the last PER trap */
+                return (__u32) child->thread.per_event.cause << 16;
+        else if (addr == (addr_t) &dummy32->address)
+                /* Address of the last PER trap */
+                return (__u32) child->thread.per_event.address;
+        else if (addr == (addr_t) &dummy32->access_id)
+                /* Access id of the last PER trap */
+                return (__u32) child->thread.per_event.paid << 24;
+        return 0;
+}
+
+/*
  * Same as peek_user but for a 31 bit program.
  */
 static u32 __peek_user_compat(struct task_struct *child, addr_t addr)
 {
-        struct user32 *dummy32 = NULL;
-        per_struct32 *dummy_per32 = NULL;
+        struct compat_user *dummy32 = NULL;
         addr_t offset;
         __u32 tmp;
 
@@ -465,19 +540,10 @@ static u32 __peek_user_compat(struct task_struct *child, addr_t addr)
 
         } else if (addr < (addr_t) (&dummy32->regs.per_info + 1)) {
                 /*
-                 * per_info is found in the thread structure
+                 * Handle access to the per_info structure.
                  */
-                offset = addr - (addr_t) &dummy32->regs.per_info;
-                /* This is magic. See per_struct and per_struct32. */
-                if ((offset >= (addr_t) &dummy_per32->control_regs &&
-                     offset < (addr_t) (&dummy_per32->control_regs + 1)) ||
-                    (offset >= (addr_t) &dummy_per32->starting_addr &&
-                     offset <= (addr_t) &dummy_per32->ending_addr) ||
-                    offset == (addr_t) &dummy_per32->lowcore.words.address)
-                        offset = offset*2 + 4;
-                else
-                        offset = offset*2;
-                tmp = *(__u32 *)((addr_t) &child->thread.per_info + offset);
+                addr -= (addr_t) &dummy32->regs.per_info;
+                tmp = __peek_user_per_compat(child, addr);
 
         } else
                 tmp = 0;
@@ -498,13 +564,32 @@ static int peek_user_compat(struct task_struct *child,
 }
 
 /*
+ * Same as poke_user_per but for a 31 bit program.
+ */
+static inline void __poke_user_per_compat(struct task_struct *child,
+                                          addr_t addr, __u32 data)
+{
+        struct compat_per_struct_kernel *dummy32 = NULL;
+
+        if (addr == (addr_t) &dummy32->cr9)
+                /* PER event mask of the user specified per set. */
+                child->thread.per_user.control =
+                        data & (PER_EVENT_MASK | PER_CONTROL_MASK);
+        else if (addr == (addr_t) &dummy32->starting_addr)
+                /* Starting address of the user specified per set. */
+                child->thread.per_user.start = data;
+        else if (addr == (addr_t) &dummy32->ending_addr)
+                /* Ending address of the user specified per set. */
+                child->thread.per_user.end = data;
+}
+
+/*
  * Same as poke_user but for a 31 bit program.
  */
 static int __poke_user_compat(struct task_struct *child,
                               addr_t addr, addr_t data)
 {
-        struct user32 *dummy32 = NULL;
-        per_struct32 *dummy_per32 = NULL;
+        struct compat_user *dummy32 = NULL;
         __u32 tmp = (__u32) data;
         addr_t offset;
 
@@ -561,37 +646,20 @@ static int __poke_user_compat(struct task_struct *child,
 
         } else if (addr < (addr_t) (&dummy32->regs.per_info + 1)) {
                 /*
-                 * per_info is found in the thread structure.
-                 */
-                offset = addr - (addr_t) &dummy32->regs.per_info;
-                /*
-                 * This is magic. See per_struct and per_struct32.
-                 * By incident the offsets in per_struct are exactly
-                 * twice the offsets in per_struct32 for all fields.
-                 * The 8 byte fields need special handling though,
-                 * because the second half (bytes 4-7) is needed and
-                 * not the first half.
+                 * Handle access to the per_info structure.
                  */
-                if ((offset >= (addr_t) &dummy_per32->control_regs &&
-                     offset < (addr_t) (&dummy_per32->control_regs + 1)) ||
-                    (offset >= (addr_t) &dummy_per32->starting_addr &&
-                     offset <= (addr_t) &dummy_per32->ending_addr) ||
-                    offset == (addr_t) &dummy_per32->lowcore.words.address)
-                        offset = offset*2 + 4;
-                else
-                        offset = offset*2;
-                *(__u32 *)((addr_t) &child->thread.per_info + offset) = tmp;
-
+                addr -= (addr_t) &dummy32->regs.per_info;
+                __poke_user_per_compat(child, addr, data);
         }
 
-        FixPerRegisters(child);
         return 0;
 }
 
 static int poke_user_compat(struct task_struct *child,
                             addr_t addr, addr_t data)
 {
-        if (!is_compat_task() || (addr & 3) || addr > sizeof(struct user32) - 3)
+        if (!is_compat_task() || (addr & 3) ||
+            addr > sizeof(struct compat_user) - 3)
                 return -EIO;
 
         return __poke_user_compat(child, addr, data);
@@ -602,7 +670,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
 {
         unsigned long addr = caddr;
         unsigned long data = cdata;
-        ptrace_area_emu31 parea; 
+        compat_ptrace_area parea;
         int copied, ret;
 
         switch (request) {
diff --git a/arch/s390/kernel/s390_ext.c b/arch/s390/kernel/s390_ext.c
index bd1db508e8af..185029919c4d 100644
--- a/arch/s390/kernel/s390_ext.c
+++ b/arch/s390/kernel/s390_ext.c
@@ -1,33 +1,36 @@
 /*
- *  arch/s390/kernel/s390_ext.c
- *
- *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
- *    Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com),
- *               Martin Schwidefsky (schwidefsky@de.ibm.com)
+ *    Copyright IBM Corp. 1999,2010
+ *    Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
+ *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  */
 
+#include <linux/kernel_stat.h>
+#include <linux/interrupt.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/slab.h>
 #include <linux/ftrace.h>
 #include <linux/errno.h>
-#include <linux/kernel_stat.h>
-#include <linux/interrupt.h>
-#include <asm/cputime.h>
-#include <asm/lowcore.h>
+#include <linux/slab.h>
 #include <asm/s390_ext.h>
 #include <asm/irq_regs.h>
+#include <asm/cputime.h>
+#include <asm/lowcore.h>
 #include <asm/irq.h>
 #include "entry.h"
 
+struct ext_int_info {
+        struct ext_int_info *next;
+        ext_int_handler_t handler;
+        __u16 code;
+};
+
 /*
  * ext_int_hash[index] is the start of the list for all external interrupts
  * that hash to this index. With the current set of external interrupts 
  * (0x1202 external call, 0x1004 cpu timer, 0x2401 hwc console, 0x4000
  * iucv and 0x2603 pfault) this is always the first element. 
  */
-ext_int_info_t *ext_int_hash[256] = { NULL, };
+static struct ext_int_info *ext_int_hash[256];
 
 static inline int ext_hash(__u16 code)
 {
@@ -36,90 +39,53 @@ static inline int ext_hash(__u16 code)
 
 int register_external_interrupt(__u16 code, ext_int_handler_t handler)
 {
-        ext_int_info_t *p;
-        int index;
-
-        p = kmalloc(sizeof(ext_int_info_t), GFP_ATOMIC);
-        if (p == NULL)
-                return -ENOMEM;
-        p->code = code;
-        p->handler = handler;
-        index = ext_hash(code);
-        p->next = ext_int_hash[index];
-        ext_int_hash[index] = p;
-        return 0;
-}
-
-int register_early_external_interrupt(__u16 code, ext_int_handler_t handler,
-                                      ext_int_info_t *p)
-{
-        int index;
+        struct ext_int_info *p;
+        int index;
 
-        if (p == NULL)
-                return -EINVAL;
-        p->code = code;
-        p->handler = handler;
+        p = kmalloc(sizeof(*p), GFP_ATOMIC);
+        if (!p)
+                return -ENOMEM;
+        p->code = code;
+        p->handler = handler;
         index = ext_hash(code);
-        p->next = ext_int_hash[index];
-        ext_int_hash[index] = p;
-        return 0;
+        p->next = ext_int_hash[index];
+        ext_int_hash[index] = p;
+        return 0;
 }
+EXPORT_SYMBOL(register_external_interrupt);
 
 int unregister_external_interrupt(__u16 code, ext_int_handler_t handler)
 {
-        ext_int_info_t *p, *q;
-        int index;
-
-        index = ext_hash(code);
-        q = NULL;
-        p = ext_int_hash[index];
-        while (p != NULL) {
-                if (p->code == code && p->handler == handler)
-                        break;
-                q = p;
-                p = p->next;
-        }
-        if (p == NULL)
-                return -ENOENT;
-        if (q != NULL)
-                q->next = p->next;
-        else
-                ext_int_hash[index] = p->next;
-        kfree(p);
-        return 0;
-}
-
-int unregister_early_external_interrupt(__u16 code, ext_int_handler_t handler,
-                                        ext_int_info_t *p)
-{
-        ext_int_info_t *q;
+        struct ext_int_info *p, *q;
         int index;
 
-        if (p == NULL || p->code != code || p->handler != handler)
-                return -EINVAL;
         index = ext_hash(code);
-        q = ext_int_hash[index];
-        if (p != q) {
-                while (q != NULL) {
-                        if (q->next == p)
-                                break;
-                        q = q->next;
-                }
-                if (q == NULL)
-                        return -ENOENT;
+        q = NULL;
+        p = ext_int_hash[index];
+        while (p) {
+                if (p->code == code && p->handler == handler)
+                        break;
+                q = p;
+                p = p->next;
+        }
+        if (!p)
+                return -ENOENT;
+        if (q)
                 q->next = p->next;
-        } else
+        else
                 ext_int_hash[index] = p->next;
+        kfree(p);
         return 0;
 }
+EXPORT_SYMBOL(unregister_external_interrupt);
 
 void __irq_entry do_extint(struct pt_regs *regs, unsigned int ext_int_code,
                            unsigned int param32, unsigned long param64)
 {
         struct pt_regs *old_regs;
         unsigned short code;
-        ext_int_info_t *p;
-        int index;
+        struct ext_int_info *p;
+        int index;
 
         code = (unsigned short) ext_int_code;
         old_regs = set_irq_regs(regs);
@@ -132,7 +98,7 @@ void __irq_entry do_extint(struct pt_regs *regs, unsigned int ext_int_code,
         kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++;
         if (code != 0x1004)
                 __get_cpu_var(s390_idle).nohz_delay = 1;
-        index = ext_hash(code);
+        index = ext_hash(code);
         for (p = ext_int_hash[index]; p; p = p->next) {
                 if (likely(p->code == code))
                         p->handler(ext_int_code, param32, param64);
@@ -140,6 +106,3 @@ void __irq_entry do_extint(struct pt_regs *regs, unsigned int ext_int_code,
         irq_exit();
         set_irq_regs(old_regs);
 }
-
-EXPORT_SYMBOL(register_external_interrupt);
-EXPORT_SYMBOL(unregister_external_interrupt);
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index ee7ac8b11782..abbb3c3c7aab 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -505,7 +505,7 @@ void do_signal(struct pt_regs *regs)
                          * Let tracing know that we've done the handler setup.
                          */
                         tracehook_signal_handler(signr, &info, &ka, regs,
-                                        current->thread.per_info.single_step);
+                                        test_thread_flag(TIF_SINGLE_STEP));
                 }
                 return;
         }
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 94cf510b8fe1..63a97db83f96 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -23,6 +23,7 @@
 #define KMSG_COMPONENT "cpu"
 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
 
+#include <linux/workqueue.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/mm.h>
@@ -161,6 +162,7 @@ static void do_ext_call_interrupt(unsigned int ext_int_code,
 {
         unsigned long bits;
 
+        kstat_cpu(smp_processor_id()).irqs[EXTINT_IPI]++;
         /*
          * handle bit signal external calls
          *
@@ -469,25 +471,25 @@ int __cpuinit start_secondary(void *cpuvoid)
         ipi_call_unlock();
         /* Switch on interrupts */
         local_irq_enable();
-        /* Print info about this processor */
-        print_cpu_info();
         /* cpu_idle will call schedule for us */
         cpu_idle();
         return 0;
 }
 
-static void __init smp_create_idle(unsigned int cpu)
+struct create_idle {
+        struct work_struct work;
+        struct task_struct *idle;
+        struct completion done;
+        int cpu;
+};
+
+static void __cpuinit smp_fork_idle(struct work_struct *work)
 {
-        struct task_struct *p;
+        struct create_idle *c_idle;
 
-        /*
-         *  don't care about the psw and regs settings since we'll never
-         *  reschedule the forked task.
-         */
-        p = fork_idle(cpu);
-        if (IS_ERR(p))
-                panic("failed fork for CPU %u: %li", cpu, PTR_ERR(p));
-        current_set[cpu] = p;
+        c_idle = container_of(work, struct create_idle, work);
+        c_idle->idle = fork_idle(c_idle->cpu);
+        complete(&c_idle->done);
 }
 
 static int __cpuinit smp_alloc_lowcore(int cpu)
@@ -551,6 +553,7 @@ static void smp_free_lowcore(int cpu)
 int __cpuinit __cpu_up(unsigned int cpu)
 {
         struct _lowcore *cpu_lowcore;
+        struct create_idle c_idle;
         struct task_struct *idle;
         struct stack_frame *sf;
         u32 lowcore;
@@ -558,6 +561,19 @@ int __cpuinit __cpu_up(unsigned int cpu)
 
         if (smp_cpu_state[cpu] != CPU_STATE_CONFIGURED)
                 return -EIO;
+        idle = current_set[cpu];
+        if (!idle) {
+                c_idle.done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done);
+                INIT_WORK_ONSTACK(&c_idle.work, smp_fork_idle);
+                c_idle.cpu = cpu;
+                schedule_work(&c_idle.work);
+                wait_for_completion(&c_idle.done);
+                if (IS_ERR(c_idle.idle))
+                        return PTR_ERR(c_idle.idle);
+                idle = c_idle.idle;
+                current_set[cpu] = c_idle.idle;
+        }
+        init_idle(idle, cpu);
         if (smp_alloc_lowcore(cpu))
                 return -ENOMEM;
         do {
@@ -572,7 +588,6 @@ int __cpuinit __cpu_up(unsigned int cpu)
         while (sigp_p(lowcore, cpu, sigp_set_prefix) == sigp_busy)
                 udelay(10);
 
-        idle = current_set[cpu];
         cpu_lowcore = lowcore_ptr[cpu];
         cpu_lowcore->kernel_stack = (unsigned long)
                 task_stack_page(idle) + THREAD_SIZE;
@@ -664,7 +679,6 @@ void __cpu_die(unsigned int cpu)
                 udelay(10);
         smp_free_lowcore(cpu);
         atomic_dec(&init_mm.context.attach_count);
-        pr_info("Processor %d stopped\n", cpu);
 }
 
 void cpu_die(void)
@@ -684,14 +698,12 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 #endif
         unsigned long async_stack, panic_stack;
         struct _lowcore *lowcore;
-        unsigned int cpu;
 
         smp_detect_cpus();
 
         /* request the 0x1201 emergency signal external interrupt */
         if (register_external_interrupt(0x1201, do_ext_call_interrupt) != 0)
                 panic("Couldn't request external interrupt 0x1201");
-        print_cpu_info();
 
         /* Reallocate current lowcore, but keep its contents. */
         lowcore = (void *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
@@ -719,9 +731,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         if (vdso_alloc_per_cpu(smp_processor_id(), &S390_lowcore))
                 BUG();
 #endif
-        for_each_possible_cpu(cpu)
-                if (cpu != smp_processor_id())
-                        smp_create_idle(cpu);
 }
 
 void __init smp_prepare_boot_cpu(void)
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index f754a6dc4f94..9e7b039458da 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -15,6 +15,7 @@
 #define KMSG_COMPONENT "time"
 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
 
+#include <linux/kernel_stat.h>
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/sched.h>
@@ -37,6 +38,7 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/gfp.h>
+#include <linux/kprobes.h>
 #include <asm/uaccess.h>
 #include <asm/delay.h>
 #include <asm/s390_ext.h>
@@ -60,7 +62,7 @@ static DEFINE_PER_CPU(struct clock_event_device, comparators);
 /*
  * Scheduler clock - returns current time in nanosec units.
  */
-unsigned long long notrace sched_clock(void)
+unsigned long long notrace __kprobes sched_clock(void)
 {
         return (get_clock_monotonic() * 125) >> 9;
 }
@@ -159,6 +161,7 @@ static void clock_comparator_interrupt(unsigned int ext_int_code,
                                        unsigned int param32,
                                        unsigned long param64)
 {
+        kstat_cpu(smp_processor_id()).irqs[EXTINT_CLK]++;
         if (S390_lowcore.clock_comparator == -1ULL)
                 set_clock_comparator(S390_lowcore.clock_comparator);
 }
@@ -169,6 +172,7 @@ static void stp_timing_alert(struct stp_irq_parm *);
 static void timing_alert_interrupt(unsigned int ext_int_code,
                                    unsigned int param32, unsigned long param64)
 {
+        kstat_cpu(smp_processor_id()).irqs[EXTINT_TLA]++;
         if (param32 & 0x00c40000)
                 etr_timing_alert((struct etr_irq_parm *) &param32);
         if (param32 & 0x00038000)
diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c
index 70640822621a..5eb78dd584ce 100644
--- a/arch/s390/kernel/traps.c
+++ b/arch/s390/kernel/traps.c
@@ -365,12 +365,10 @@ static inline void __user *get_psw_address(struct pt_regs *regs,
                 ((regs->psw.addr - (pgm_int_code >> 16)) & PSW_ADDR_INSN);
 }
 
-void __kprobes do_single_step(struct pt_regs *regs)
+void __kprobes do_per_trap(struct pt_regs *regs)
 {
-        if (notify_die(DIE_SSTEP, "sstep", regs, 0, 0,
-                                        SIGTRAP) == NOTIFY_STOP){
+        if (notify_die(DIE_SSTEP, "sstep", regs, 0, 0, SIGTRAP) == NOTIFY_STOP)
                 return;
-        }
         if (tracehook_consider_fatal_signal(current, SIGTRAP))
                 force_sig(SIGTRAP, current);
 }
@@ -451,8 +449,8 @@ static inline void do_fp_trap(struct pt_regs *regs, void __user *location,
                 "floating point exception", regs, &si);
 }
 
-static void illegal_op(struct pt_regs *regs, long pgm_int_code,
-                       unsigned long trans_exc_code)
+static void __kprobes illegal_op(struct pt_regs *regs, long pgm_int_code,
+                                 unsigned long trans_exc_code)
 {
         siginfo_t info;
         __u8 opcode[6];
@@ -688,7 +686,7 @@ static void space_switch_exception(struct pt_regs *regs, long pgm_int_code,
         do_trap(pgm_int_code, SIGILL, "space switch event", regs, &info);
 }
 
-asmlinkage void kernel_stack_overflow(struct pt_regs * regs)
+asmlinkage void __kprobes kernel_stack_overflow(struct pt_regs * regs)
 {
         bust_spinlocks(1);
         printk("Kernel stack overflow.\n");
@@ -733,5 +731,6 @@ void __init trap_init(void)
         pgm_check_table[0x15] = &operand_exception;
         pgm_check_table[0x1C] = &space_switch_exception;
         pgm_check_table[0x1D] = &hfp_sqrt_exception;
-        pfault_irq_init();
+        /* Enable machine checks early. */
+        local_mcck_enable();
 }
diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c
index 7eff9b7347c0..1ccdf4d8aa85 100644
--- a/arch/s390/kernel/vtime.c
+++ b/arch/s390/kernel/vtime.c
@@ -20,6 +20,7 @@
 #include <linux/rcupdate.h>
 #include <linux/posix-timers.h>
 #include <linux/cpu.h>
+#include <linux/kprobes.h>
 
 #include <asm/s390_ext.h>
 #include <asm/timer.h>
@@ -122,7 +123,7 @@ void account_system_vtime(struct task_struct *tsk)
 }
 EXPORT_SYMBOL_GPL(account_system_vtime);
 
-void vtime_start_cpu(__u64 int_clock, __u64 enter_timer)
+void __kprobes vtime_start_cpu(__u64 int_clock, __u64 enter_timer)
 {
         struct s390_idle_data *idle = &__get_cpu_var(s390_idle);
         struct vtimer_queue *vq = &__get_cpu_var(virt_cpu_timer);
@@ -162,7 +163,7 @@ void vtime_start_cpu(__u64 int_clock, __u64 enter_timer)
         idle->sequence++;
 }
 
-void vtime_stop_cpu(void)
+void __kprobes vtime_stop_cpu(void)
 {
         struct s390_idle_data *idle = &__get_cpu_var(s390_idle);
         struct vtimer_queue *vq = &__get_cpu_var(virt_cpu_timer);
@@ -323,6 +324,7 @@ static void do_cpu_timer_interrupt(unsigned int ext_int_code,
         struct list_head cb_list;       /* the callback queue */
         __u64 elapsed, next;
 
+        kstat_cpu(smp_processor_id()).irqs[EXTINT_TMR]++;
         INIT_LIST_HEAD(&cb_list);
         vq = &__get_cpu_var(virt_cpu_timer);
 
diff --git a/arch/s390/kvm/Kconfig b/arch/s390/kvm/Kconfig
index a7251580891c..f66a1bdbb61d 100644
--- a/arch/s390/kvm/Kconfig
+++ b/arch/s390/kvm/Kconfig
@@ -4,8 +4,8 @@
 source "virt/kvm/Kconfig"
 
 menuconfig VIRTUALIZATION
-        bool "Virtualization"
-        default y
+        def_bool y
+        prompt "Virtualization"
         ---help---
           Say Y here to get to see options for using your Linux host to run other
           operating systems inside virtual machines (guests).
@@ -16,7 +16,8 @@ menuconfig VIRTUALIZATION
 if VIRTUALIZATION
 
 config KVM
-        tristate "Kernel-based Virtual Machine (KVM) support"
+        def_tristate y
+        prompt "Kernel-based Virtual Machine (KVM) support"
         depends on HAVE_KVM && EXPERIMENTAL
         select PREEMPT_NOTIFIERS
         select ANON_INODES
diff --git a/arch/s390/lib/delay.c b/arch/s390/lib/delay.c
index 7c37ec359ec2..0f53110e1d09 100644
--- a/arch/s390/lib/delay.c
+++ b/arch/s390/lib/delay.c
@@ -47,7 +47,6 @@ static void __udelay_disabled(unsigned long long usecs)
         lockdep_on();
         __ctl_load(cr0_saved, 0, 0);
         local_tick_enable(clock_saved);
-        set_clock_comparator(S390_lowcore.clock_comparator);
 }
 
 static void __udelay_enabled(unsigned long long usecs)
@@ -70,7 +69,6 @@ static void __udelay_enabled(unsigned long long usecs)
                 if (clock_saved)
                         local_tick_enable(clock_saved);
         } while (get_clock() < end);
-        set_clock_comparator(S390_lowcore.clock_comparator);
 }
 
 /*
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index fe5701e9efbf..2c57806c0858 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -10,6 +10,7 @@
  *    Copyright (C) 1995  Linus Torvalds
  */
 
+#include <linux/kernel_stat.h>
 #include <linux/perf_event.h>
 #include <linux/signal.h>
 #include <linux/sched.h>
@@ -234,13 +235,13 @@ static noinline int signal_return(struct pt_regs *regs, long int_code,
         rc = __get_user(instruction, (u16 __user *) regs->psw.addr);
 
         if (!rc && instruction == 0x0a77) {
-                clear_tsk_thread_flag(current, TIF_SINGLE_STEP);
+                clear_tsk_thread_flag(current, TIF_PER_TRAP);
                 if (is_compat_task())
                         sys32_sigreturn();
                 else
                         sys_sigreturn();
         } else if (!rc && instruction == 0x0aad) {
-                clear_tsk_thread_flag(current, TIF_SINGLE_STEP);
+                clear_tsk_thread_flag(current, TIF_PER_TRAP);
                 if (is_compat_task())
                         sys32_rt_sigreturn();
                 else
@@ -378,7 +379,7 @@ static inline int do_exception(struct pt_regs *regs, int access,
          * The instruction that caused the program check will
          * be repeated. Don't signal single step via SIGTRAP.
          */
-        clear_tsk_thread_flag(tsk, TIF_SINGLE_STEP);
+        clear_tsk_thread_flag(tsk, TIF_PER_TRAP);
         fault = 0;
 out_up:
         up_read(&mm->mmap_sem);
@@ -480,8 +481,7 @@ int __handle_fault(unsigned long uaddr, unsigned long pgm_int_code, int write)
 /*
  * 'pfault' pseudo page faults routines.
  */
-static ext_int_info_t ext_int_pfault;
-static int pfault_disable = 0;
+static int pfault_disable;
 
 static int __init nopfault(char *str)
 {
@@ -543,6 +543,7 @@ static void pfault_interrupt(unsigned int ext_int_code,
         struct task_struct *tsk;
         __u16 subcode;
 
+        kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++;
         /*
          * Get the external interruption subcode & pfault
          * initial/completion signal bit. VM stores this 
@@ -592,24 +593,28 @@ static void pfault_interrupt(unsigned int ext_int_code,
         }
 }
 
-void __init pfault_irq_init(void)
+static int __init pfault_irq_init(void)
 {
-        if (!MACHINE_IS_VM)
-                return;
+        int rc;
 
+        if (!MACHINE_IS_VM)
+                return 0;
         /*
          * Try to get pfault pseudo page faults going.
          */
-        if (register_early_external_interrupt(0x2603, pfault_interrupt,
-                                              &ext_int_pfault) != 0)
-                panic("Couldn't request external interrupt 0x2603");
-
+        rc = register_external_interrupt(0x2603, pfault_interrupt);
+        if (rc) {
+                pfault_disable = 1;
+                return rc;
+        }
         if (pfault_init() == 0)
-                return;
+                return 0;
 
         /* Tough luck, no pfault. */
         pfault_disable = 1;
-        unregister_early_external_interrupt(0x2603, pfault_interrupt,
-                                            &ext_int_pfault);
+        unregister_external_interrupt(0x2603, pfault_interrupt);
+        return 0;
 }
+early_initcall(pfault_irq_init);
+
 #endif
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 2e9d78d21fd3..fff252209f63 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -1,7 +1,7 @@
 config SUPERH
         def_bool y
         select EMBEDDED
-        select HAVE_CLK
+        select CLKDEV_LOOKUP
         select HAVE_IDE if HAS_IOPORT
         select HAVE_MEMBLOCK
         select HAVE_OPROFILE
@@ -162,7 +162,8 @@ config ARCH_HAS_CPU_IDLE_WAIT
         def_bool y
 
 config NO_IOPORT
-        bool
+        def_bool !PCI
+        depends on !SH_CAYMAN && !SH_SH4202_MICRODEV
 
 config IO_TRAPPED
         bool
@@ -275,6 +276,7 @@ config CPU_SUBTYPE_SH7203
         select CPU_HAS_FPU
         select SYS_SUPPORTS_CMT
         select SYS_SUPPORTS_MTU2
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config CPU_SUBTYPE_SH7206
         bool "Support SH7206 processor"
@@ -346,6 +348,8 @@ config CPU_SUBTYPE_SH7720
         select CPU_SH3
         select CPU_HAS_DSP
         select SYS_SUPPORTS_CMT
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select USB_ARCH_HAS_OHCI
         help
           Select SH7720 if you have a SH3-DSP SH7720 CPU.
 
@@ -354,6 +358,7 @@ config CPU_SUBTYPE_SH7721
         select CPU_SH3
         select CPU_HAS_DSP
         select SYS_SUPPORTS_CMT
+        select USB_ARCH_HAS_OHCI
         help
           Select SH7721 if you have a SH3-DSP SH7721 CPU.
 
@@ -408,6 +413,7 @@ config CPU_SUBTYPE_SH7723
         select ARCH_SHMOBILE
         select ARCH_SPARSEMEM_ENABLE
         select SYS_SUPPORTS_CMT
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         help
           Select SH7723 if you have an SH-MobileR2 CPU.
 
@@ -418,6 +424,7 @@ config CPU_SUBTYPE_SH7724
         select ARCH_SHMOBILE
         select ARCH_SPARSEMEM_ENABLE
         select SYS_SUPPORTS_CMT
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         help
           Select SH7724 if you have an SH-MobileR2R CPU.
 
@@ -425,12 +432,14 @@ config CPU_SUBTYPE_SH7757
         bool "Support SH7757 processor"
         select CPU_SH4A
         select CPU_SHX2
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         help
           Select SH7757 if you have a SH4A SH7757 CPU.
 
 config CPU_SUBTYPE_SH7763
         bool "Support SH7763 processor"
         select CPU_SH4A
+        select USB_ARCH_HAS_OHCI
         help
           Select SH7763 if you have a SH4A SH7763(R5S77631) CPU.
 
@@ -448,6 +457,7 @@ config CPU_SUBTYPE_SH7785
         select CPU_SHX2
         select ARCH_SPARSEMEM_ENABLE
         select SYS_SUPPORTS_NUMA
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config CPU_SUBTYPE_SH7786
         bool "Support SH7786 processor"
@@ -455,6 +465,9 @@ config CPU_SUBTYPE_SH7786
         select CPU_SHX3
         select CPU_HAS_PTEAEX
         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select USB_ARCH_HAS_OHCI
+        select USB_ARCH_HAS_EHCI
 
 config CPU_SUBTYPE_SHX3
         bool "Support SH-X3 processor"
@@ -479,6 +492,7 @@ config CPU_SUBTYPE_SH7722
         select ARCH_SPARSEMEM_ENABLE
         select SYS_SUPPORTS_NUMA
         select SYS_SUPPORTS_CMT
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config CPU_SUBTYPE_SH7366
         bool "Support SH7366 processor"
@@ -568,15 +582,6 @@ config SH_CLK_CPG_LEGACY
         def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
                       !CPU_SHX3 && !CPU_SUBTYPE_SH7757
 
-config SH_CLK_MD
-        int "CPU Mode Pin Setting"
-        depends on CPU_SH2
-        default 6 if CPU_SUBTYPE_SH7206
-        default 5 if CPU_SUBTYPE_SH7619
-        default 0
-        help
-          MD2 - MD0 pin setting.
-
 source "kernel/time/Kconfig"
 
 endmenu
diff --git a/arch/sh/boards/board-secureedge5410.c b/arch/sh/boards/board-secureedge5410.c
index 32f875e8493d..f968f17891a4 100644
--- a/arch/sh/boards/board-secureedge5410.c
+++ b/arch/sh/boards/board-secureedge5410.c
@@ -29,8 +29,6 @@ unsigned short secureedge5410_ioport;
  */
 static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
 {
-        ctrl_delay();   /* dummy read */
-
         printk("SnapGear: erase switch interrupt!\n");
 
         return IRQ_HANDLED;
diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c
index a5ecfbacaf36..87618c91d178 100644
--- a/arch/sh/boards/mach-highlander/setup.c
+++ b/arch/sh/boards/mach-highlander/setup.c
@@ -24,10 +24,10 @@
 #include <linux/interrupt.h>
 #include <linux/usb/r8a66597.h>
 #include <linux/usb/m66592.h>
+#include <linux/clkdev.h>
 #include <net/ax88796.h>
 #include <asm/machvec.h>
 #include <mach/highlander.h>
-#include <asm/clkdev.h>
 #include <asm/clock.h>
 #include <asm/heartbeat.h>
 #include <asm/io.h>
diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c
index 4fa08ba10253..a8089f79d058 100644
--- a/arch/sh/boards/mach-rsk/devices-rsk7203.c
+++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c
@@ -1,7 +1,7 @@
 /*
  * Renesas Technology Europe RSK+ 7203 Support.
  *
- * Copyright (C) 2008 Paul Mundt
+ * Copyright (C) 2008 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -12,7 +12,9 @@
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
+#include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/gpio_keys.h>
 #include <linux/leds.h>
 #include <asm/machvec.h>
 #include <asm/io.h>
@@ -84,9 +86,42 @@ static struct platform_device led_device = {
         },
 };
 
+static struct gpio_keys_button rsk7203_gpio_keys_table[] = {
+        {
+                .code           = BTN_0,
+                .gpio           = GPIO_PB0,
+                .active_low     = 1,
+                .desc           = "SW1",
+        }, {
+                .code           = BTN_1,
+                .gpio           = GPIO_PB1,
+                .active_low     = 1,
+                .desc           = "SW2",
+        }, {
+                .code           = BTN_2,
+                .gpio           = GPIO_PB2,
+                .active_low     = 1,
+                .desc           = "SW3",
+        },
+};
+
+static struct gpio_keys_platform_data rsk7203_gpio_keys_info = {
+        .buttons        = rsk7203_gpio_keys_table,
+        .nbuttons       = ARRAY_SIZE(rsk7203_gpio_keys_table),
+        .poll_interval  = 50, /* default to 50ms */
+};
+
+static struct platform_device keys_device = {
+        .name           = "gpio-keys-polled",
+        .dev            = {
+                .platform_data  = &rsk7203_gpio_keys_info,
+        },
+};
+
 static struct platform_device *rsk7203_devices[] __initdata = {
         &smsc911x_device,
         &led_device,
+        &keys_device,
 };
 
 static int __init rsk7203_devices_setup(void)
diff --git a/arch/sh/boards/mach-sdk7786/Makefile b/arch/sh/boards/mach-sdk7786/Makefile
index 23ff7d4ac491..8ae56e9560ac 100644
--- a/arch/sh/boards/mach-sdk7786/Makefile
+++ b/arch/sh/boards/mach-sdk7786/Makefile
@@ -1,4 +1,4 @@
-obj-y   := fpga.o irq.o setup.o
+obj-y   := fpga.o irq.o nmi.o setup.o
 
 obj-$(CONFIG_GENERIC_GPIO)      += gpio.o
 obj-$(CONFIG_HAVE_SRAM_POOL)    += sram.o
diff --git a/arch/sh/boards/mach-sdk7786/nmi.c b/arch/sh/boards/mach-sdk7786/nmi.c
new file mode 100644
index 000000000000..edcfa1f568ba
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/nmi.c
@@ -0,0 +1,83 @@
+/*
+ * SDK7786 FPGA NMI Support.
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <mach/fpga.h>
+
+enum {
+        NMI_MODE_MANUAL,
+        NMI_MODE_AUX,
+        NMI_MODE_MASKED,
+        NMI_MODE_ANY,
+        NMI_MODE_UNKNOWN,
+};
+
+/*
+ * Default to the manual NMI switch.
+ */
+static unsigned int __initdata nmi_mode = NMI_MODE_ANY;
+
+static int __init nmi_mode_setup(char *str)
+{
+        if (!str)
+                return 0;
+
+        if (strcmp(str, "manual") == 0)
+                nmi_mode = NMI_MODE_MANUAL;
+        else if (strcmp(str, "aux") == 0)
+                nmi_mode = NMI_MODE_AUX;
+        else if (strcmp(str, "masked") == 0)
+                nmi_mode = NMI_MODE_MASKED;
+        else if (strcmp(str, "any") == 0)
+                nmi_mode = NMI_MODE_ANY;
+        else {
+                nmi_mode = NMI_MODE_UNKNOWN;
+                pr_warning("Unknown NMI mode %s\n", str);
+        }
+
+        printk("Set NMI mode to %d\n", nmi_mode);
+        return 0;
+}
+early_param("nmi_mode", nmi_mode_setup);
+
+void __init sdk7786_nmi_init(void)
+{
+        unsigned int source, mask, tmp;
+
+        switch (nmi_mode) {
+        case NMI_MODE_MANUAL:
+                source = NMISR_MAN_NMI;
+                mask = NMIMR_MAN_NMIM;
+                break;
+        case NMI_MODE_AUX:
+                source = NMISR_AUX_NMI;
+                mask = NMIMR_AUX_NMIM;
+                break;
+        case NMI_MODE_ANY:
+                source = NMISR_MAN_NMI | NMISR_AUX_NMI;
+                mask = NMIMR_MAN_NMIM | NMIMR_AUX_NMIM;
+                break;
+        case NMI_MODE_MASKED:
+        case NMI_MODE_UNKNOWN:
+        default:
+                source = mask = 0;
+                break;
+        }
+
+        /* Set the NMI source */
+        tmp = fpga_read_reg(NMISR);
+        tmp &= ~NMISR_MASK;
+        tmp |= source;
+        fpga_write_reg(tmp, NMISR);
+
+        /* And the IRQ masking */
+        fpga_write_reg(NMIMR_MASK ^ mask, NMIMR);
+}
diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c
index 7e0c4e3878e0..75e4ddbbec3e 100644
--- a/arch/sh/boards/mach-sdk7786/setup.c
+++ b/arch/sh/boards/mach-sdk7786/setup.c
@@ -237,6 +237,7 @@ static void __init sdk7786_setup(char **cmdline_p)
         pr_info("Renesas Technology Europe SDK7786 support:\n");
 
         sdk7786_fpga_init();
+        sdk7786_nmi_init();
 
         pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
 
diff --git a/arch/sh/boards/mach-se/7206/setup.c b/arch/sh/boards/mach-se/7206/setup.c
index 7f4871c71a01..33039e0dc568 100644
--- a/arch/sh/boards/mach-se/7206/setup.c
+++ b/arch/sh/boards/mach-se/7206/setup.c
@@ -79,6 +79,11 @@ static int __init se7206_devices_setup(void)
 }
 __initcall(se7206_devices_setup);
 
+static int se7206_mode_pins(void)
+{
+        return MODE_PIN1 | MODE_PIN2;
+}
+
 /*
  * The Machine Vector
  */
@@ -87,4 +92,5 @@ static struct sh_machine_vector mv_se __initmv = {
         .mv_name                = "SolutionEngine",
         .mv_nr_irqs             = 256,
         .mv_init_irq            = init_se7206_IRQ,
+        .mv_mode_pins           = se7206_mode_pins,
 };
diff --git a/arch/sh/boards/mach-se/board-se7619.c b/arch/sh/boards/mach-se/board-se7619.c
index 1d0ef7faa10d..82b6d4a5dc02 100644
--- a/arch/sh/boards/mach-se/board-se7619.c
+++ b/arch/sh/boards/mach-se/board-se7619.c
@@ -11,6 +11,11 @@
 #include <asm/io.h>
 #include <asm/machvec.h>
 
+static int se7619_mode_pins(void)
+{
+        return MODE_PIN2 | MODE_PIN0;
+}
+
 /*
  * The Machine Vector
  */
@@ -18,4 +23,5 @@
 static struct sh_machine_vector mv_se __initmv = {
         .mv_name                = "SolutionEngine",
         .mv_nr_irqs             = 108,
+        .mv_mode_pins           = se7619_mode_pins,
 };
diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig
index 9ad904a110de..cc61eda44922 100644
--- a/arch/sh/configs/migor_defconfig
+++ b/arch/sh/configs/migor_defconfig
@@ -54,6 +54,8 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_SH_KEYSC=y
 # CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_MIGOR=y
 # CONFIG_SERIO is not set
 CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_SERIAL_SH_SCI=y
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 60ee09a4e121..a09c77dd09db 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -382,14 +382,13 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
         struct pci_channel *chan = dev->sysdata;
 
         if (unlikely(!chan->io_map_base)) {
-                chan->io_map_base = generic_io_base;
+                chan->io_map_base = sh_io_port_base;
 
                 if (pci_domains_supported)
                         panic("To avoid data corruption io_map_base MUST be "
                               "set with multiple PCI domains.");
         }
 
-
         return (void __iomem *)(chan->io_map_base + port);
 }
 
diff --git a/arch/sh/drivers/push-switch.c b/arch/sh/drivers/push-switch.c
index 7b42c247316c..afc24556572b 100644
--- a/arch/sh/drivers/push-switch.c
+++ b/arch/sh/drivers/push-switch.c
@@ -107,7 +107,7 @@ static int switch_drv_remove(struct platform_device *pdev)
                 device_remove_file(&pdev->dev, &dev_attr_switch);
 
         platform_set_drvdata(pdev, NULL);
-        flush_scheduled_work();
+        flush_work_sync(&psw->work);
         del_timer_sync(&psw->debounce);
         free_irq(irq, pdev);
 
diff --git a/arch/sh/include/asm/clkdev.h b/arch/sh/include/asm/clkdev.h
index 5645f358128b..6ba91868201c 100644
--- a/arch/sh/include/asm/clkdev.h
+++ b/arch/sh/include/asm/clkdev.h
@@ -1,9 +1,5 @@
 /*
- *  arch/sh/include/asm/clkdev.h
- *
- * Cloned from arch/arm/include/asm/clkdev.h:
- *
- *  Copyright (C) 2008 Russell King.
+ *  Copyright (C) 2010 Paul Mundt <lethal@linux-sh.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -11,25 +7,25 @@
  *
  * Helper for the clk API to assist looking up a struct clk.
  */
-#ifndef __ASM_CLKDEV_H
-#define __ASM_CLKDEV_H
 
-struct clk;
+#ifndef __CLKDEV__H_
+#define __CLKDEV__H_
 
-struct clk_lookup {
-        struct list_head        node;
-        const char              *dev_id;
-        const char              *con_id;
-        struct clk              *clk;
-};
+#include <linux/bootmem.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
 
-struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
-        const char *dev_fmt, ...);
+#include <asm/clock.h>
 
-void clkdev_add(struct clk_lookup *cl);
-void clkdev_drop(struct clk_lookup *cl);
+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
+{
+        if (!slab_is_available())
+                return alloc_bootmem_low_pages(size);
+        else
+                return kzalloc(size, GFP_KERNEL);
+}
 
-void clkdev_add_table(struct clk_lookup *, size_t);
-int clk_add_alias(const char *, const char *, char *, struct device *);
+#define __clk_put(clk)
+#define __clk_get(clk) ({ 1; })
 
-#endif
+#endif /* __CLKDEV_H__ */
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index b237d525d592..89ab2c57a4c2 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -1,5 +1,6 @@
 #ifndef __ASM_SH_IO_H
 #define __ASM_SH_IO_H
+
 /*
  * Convention:
  *    read{b,w,l,q}/write{b,w,l,q} are for PCI,
@@ -15,12 +16,6 @@
  * SuperH specific I/O (raw I/O to on-chip CPU peripherals). In practice
  * these have the same semantics as the __raw variants, and as such, all
  * new code should be using the __raw versions.
- *
- * All ISA I/O routines are wrapped through the machine vector. If a
- * board does not provide overrides, a generic set that are copied in
- * from the default machine vector are used instead. These are largely
- * for old compat code for I/O offseting to SuperIOs, all of which are
- * better handled through the machvec ioport mapping routines these days.
  */
 #include <linux/errno.h>
 #include <asm/cache.h>
@@ -31,39 +26,10 @@
 #include <asm-generic/iomap.h>
 
 #ifdef __KERNEL__
-/*
- * Depending on which platform we are running on, we need different
- * I/O functions.
- */
-#define __IO_PREFIX     generic
+#define __IO_PREFIX     generic
 #include <asm/io_generic.h>
 #include <asm/io_trapped.h>
 
-#ifdef CONFIG_HAS_IOPORT
-
-#define inb(p)                  sh_mv.mv_inb((p))
-#define inw(p)                  sh_mv.mv_inw((p))
-#define inl(p)                  sh_mv.mv_inl((p))
-#define outb(x,p)               sh_mv.mv_outb((x),(p))
-#define outw(x,p)               sh_mv.mv_outw((x),(p))
-#define outl(x,p)               sh_mv.mv_outl((x),(p))
-
-#define inb_p(p)                sh_mv.mv_inb_p((p))
-#define inw_p(p)                sh_mv.mv_inw_p((p))
-#define inl_p(p)                sh_mv.mv_inl_p((p))
-#define outb_p(x,p)             sh_mv.mv_outb_p((x),(p))
-#define outw_p(x,p)             sh_mv.mv_outw_p((x),(p))
-#define outl_p(x,p)             sh_mv.mv_outl_p((x),(p))
-
-#define insb(p,b,c)             sh_mv.mv_insb((p), (b), (c))
-#define insw(p,b,c)             sh_mv.mv_insw((p), (b), (c))
-#define insl(p,b,c)             sh_mv.mv_insl((p), (b), (c))
-#define outsb(p,b,c)            sh_mv.mv_outsb((p), (b), (c))
-#define outsw(p,b,c)            sh_mv.mv_outsw((p), (b), (c))
-#define outsl(p,b,c)            sh_mv.mv_outsl((p), (b), (c))
-
-#endif
-
 #define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile u8  __force *)(a) = (v))
 #define __raw_writew(v,a)       (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
 #define __raw_writel(v,a)       (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
@@ -74,68 +40,39 @@
 #define __raw_readl(a)          (__chk_io_ptr(a), *(volatile u32 __force *)(a))
 #define __raw_readq(a)          (__chk_io_ptr(a), *(volatile u64 __force *)(a))
 
-#define readb(a)                ({ u8  r_ = __raw_readb(a); mb(); r_; })
-#define readw(a)                ({ u16 r_ = __raw_readw(a); mb(); r_; })
-#define readl(a)                ({ u32 r_ = __raw_readl(a); mb(); r_; })
-#define readq(a)                ({ u64 r_ = __raw_readq(a); mb(); r_; })
-
-#define writeb(v,a)             ({ __raw_writeb((v),(a)); mb(); })
-#define writew(v,a)             ({ __raw_writew((v),(a)); mb(); })
-#define writel(v,a)             ({ __raw_writel((v),(a)); mb(); })
-#define writeq(v,a)             ({ __raw_writeq((v),(a)); mb(); })
-
-/*
- * Legacy SuperH on-chip I/O functions
- *
- * These are all deprecated, all new (and especially cross-platform) code
- * should be using the __raw_xxx() routines directly.
- */
-static inline u8 __deprecated ctrl_inb(unsigned long addr)
-{
-        return __raw_readb(addr);
-}
-
-static inline u16 __deprecated ctrl_inw(unsigned long addr)
-{
-        return __raw_readw(addr);
-}
-
-static inline u32 __deprecated ctrl_inl(unsigned long addr)
-{
-        return __raw_readl(addr);
-}
-
-static inline u64 __deprecated ctrl_inq(unsigned long addr)
-{
-        return __raw_readq(addr);
-}
-
-static inline void __deprecated ctrl_outb(u8 v, unsigned long addr)
-{
-        __raw_writeb(v, addr);
-}
-
-static inline void __deprecated ctrl_outw(u16 v, unsigned long addr)
-{
-        __raw_writew(v, addr);
-}
-
-static inline void __deprecated ctrl_outl(u32 v, unsigned long addr)
-{
-        __raw_writel(v, addr);
-}
-
-static inline void __deprecated ctrl_outq(u64 v, unsigned long addr)
-{
-        __raw_writeq(v, addr);
-}
-
-extern unsigned long generic_io_base;
-
-static inline void ctrl_delay(void)
-{
-        __raw_readw(generic_io_base);
-}
+#define readb_relaxed(c)        ({ u8  __v = __raw_readb(c); __v; })
+#define readw_relaxed(c)        ({ u16 __v = le16_to_cpu((__force __le16) \
+                                        __raw_readw(c)); __v; })
+#define readl_relaxed(c)        ({ u32 __v = le32_to_cpu((__force __le32) \
+                                        __raw_readl(c)); __v; })
+#define readq_relaxed(c)        ({ u64 __v = le64_to_cpu((__force __le64) \
+                                        __raw_readq(c)); __v; })
+
+#define writeb_relaxed(v,c)     ((void)__raw_writeb(v,c))
+#define writew_relaxed(v,c)     ((void)__raw_writew((__force u16) \
+                                        cpu_to_le16(v),c))
+#define writel_relaxed(v,c)     ((void)__raw_writel((__force u32) \
+                                        cpu_to_le32(v),c))
+#define writeq_relaxed(v,c)     ((void)__raw_writeq((__force u64) \
+                                        cpu_to_le64(v),c))
+
+#define readb(a)                ({ u8  r_ = readb_relaxed(a); rmb(); r_; })
+#define readw(a)                ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
+#define readl(a)                ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
+#define readq(a)                ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
+
+#define writeb(v,a)             ({ wmb(); writeb_relaxed((v),(a)); })
+#define writew(v,a)             ({ wmb(); writew_relaxed((v),(a)); })
+#define writel(v,a)             ({ wmb(); writel_relaxed((v),(a)); })
+#define writeq(v,a)             ({ wmb(); writeq_relaxed((v),(a)); })
+
+#define readsb(p,d,l)           __raw_readsb(p,d,l)
+#define readsw(p,d,l)           __raw_readsw(p,d,l)
+#define readsl(p,d,l)           __raw_readsl(p,d,l)
+
+#define writesb(p,d,l)          __raw_writesb(p,d,l)
+#define writesw(p,d,l)          __raw_writesw(p,d,l)
+#define writesl(p,d,l)          __raw_writesl(p,d,l)
 
 #define __BUILD_UNCACHED_IO(bwlq, type)                                 \
 static inline type read##bwlq##_uncached(unsigned long addr)            \
@@ -159,10 +96,11 @@ __BUILD_UNCACHED_IO(w, u16)
 __BUILD_UNCACHED_IO(l, u32)
 __BUILD_UNCACHED_IO(q, u64)
 
-#define __BUILD_MEMORY_STRING(bwlq, type)                               \
+#define __BUILD_MEMORY_STRING(pfx, bwlq, type)                          \
                                                                         \
-static inline void __raw_writes##bwlq(volatile void __iomem *mem,       \
-                                const void *addr, unsigned int count)   \
+static inline void                                                      \
+pfx##writes##bwlq(volatile void __iomem *mem, const void *addr,         \
+                  unsigned int count)                                   \
 {                                                                       \
         const volatile type *__addr = addr;                             \
                                                                         \
@@ -172,8 +110,8 @@ static inline void __raw_writes##bwlq(volatile void __iomem *mem,	\
         }                                                               \
 }                                                                       \
                                                                         \
-static inline void __raw_reads##bwlq(volatile void __iomem *mem,        \
-                               void *addr, unsigned int count)          \
+static inline void pfx##reads##bwlq(volatile void __iomem *mem,         \
+                                    void *addr, unsigned int count)     \
 {                                                                       \
         volatile type *__addr = addr;                                   \
                                                                         \
@@ -183,85 +121,166 @@ static inline void __raw_reads##bwlq(volatile void __iomem *mem,	\
         }                                                               \
 }
 
-__BUILD_MEMORY_STRING(b, u8)
-__BUILD_MEMORY_STRING(w, u16)
+__BUILD_MEMORY_STRING(__raw_, b, u8)
+__BUILD_MEMORY_STRING(__raw_, w, u16)
 
 #ifdef CONFIG_SUPERH32
 void __raw_writesl(void __iomem *addr, const void *data, int longlen);
 void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 #else
-__BUILD_MEMORY_STRING(l, u32)
+__BUILD_MEMORY_STRING(__raw_, l, u32)
 #endif
 
-__BUILD_MEMORY_STRING(q, u64)
-
-#define writesb                 __raw_writesb
-#define writesw                 __raw_writesw
-#define writesl                 __raw_writesl
-
-#define readsb                  __raw_readsb
-#define readsw                  __raw_readsw
-#define readsl                  __raw_readsl
-
-#define readb_relaxed(a)        readb(a)
-#define readw_relaxed(a)        readw(a)
-#define readl_relaxed(a)        readl(a)
-#define readq_relaxed(a)        readq(a)
-
-#ifndef CONFIG_GENERIC_IOMAP
-/* Simple MMIO */
-#define ioread8(a)              __raw_readb(a)
-#define ioread16(a)             __raw_readw(a)
-#define ioread16be(a)           be16_to_cpu(__raw_readw((a)))
-#define ioread32(a)             __raw_readl(a)
-#define ioread32be(a)           be32_to_cpu(__raw_readl((a)))
-
-#define iowrite8(v,a)           __raw_writeb((v),(a))
-#define iowrite16(v,a)          __raw_writew((v),(a))
-#define iowrite16be(v,a)        __raw_writew(cpu_to_be16((v)),(a))
-#define iowrite32(v,a)          __raw_writel((v),(a))
-#define iowrite32be(v,a)        __raw_writel(cpu_to_be32((v)),(a))
-
-#define ioread8_rep(a, d, c)    __raw_readsb((a), (d), (c))
-#define ioread16_rep(a, d, c)   __raw_readsw((a), (d), (c))
-#define ioread32_rep(a, d, c)   __raw_readsl((a), (d), (c))
-
-#define iowrite8_rep(a, s, c)   __raw_writesb((a), (s), (c))
-#define iowrite16_rep(a, s, c)  __raw_writesw((a), (s), (c))
-#define iowrite32_rep(a, s, c)  __raw_writesl((a), (s), (c))
+__BUILD_MEMORY_STRING(__raw_, q, u64)
+
+#ifdef CONFIG_HAS_IOPORT
+
+/*
+ * Slowdown I/O port space accesses for antique hardware.
+ */
+#undef CONF_SLOWDOWN_IO
+
+/*
+ * On SuperH I/O ports are memory mapped, so we access them using normal
+ * load/store instructions. sh_io_port_base is the virtual address to
+ * which all ports are being mapped.
+ */
+extern const unsigned long sh_io_port_base;
+
+static inline void __set_io_port_base(unsigned long pbase)
+{
+        *(unsigned long *)&sh_io_port_base = pbase;
+        barrier();
+}
+
+#ifdef CONFIG_GENERIC_IOMAP
+#define __ioport_map ioport_map
+#else
+extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
 #endif
 
-#define mmio_insb(p,d,c)        __raw_readsb(p,d,c)
-#define mmio_insw(p,d,c)        __raw_readsw(p,d,c)
-#define mmio_insl(p,d,c)        __raw_readsl(p,d,c)
+#ifdef CONF_SLOWDOWN_IO
+#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
+#else
+#define SLOW_DOWN_IO
+#endif
 
-#define mmio_outsb(p,s,c)       __raw_writesb(p,s,c)
-#define mmio_outsw(p,s,c)       __raw_writesw(p,s,c)
-#define mmio_outsl(p,s,c)       __raw_writesl(p,s,c)
+#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
+                                                                        \
+static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
+{                                                                       \
+        volatile type *__addr;                                          \
+                                                                        \
+        __addr = __ioport_map(port, sizeof(type));                      \
+        *__addr = val;                                                  \
+        slow;                                                           \
+}                                                                       \
+                                                                        \
+static inline type pfx##in##bwlq##p(unsigned long port)                 \
+{                                                                       \
+        volatile type *__addr;                                          \
+        type __val;                                                     \
+                                                                        \
+        __addr = __ioport_map(port, sizeof(type));                      \
+        __val = *__addr;                                                \
+        slow;                                                           \
+                                                                        \
+        return __val;                                                   \
+}
 
-/* synco on SH-4A, otherwise a nop */
-#define mmiowb()                wmb()
+#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
+        __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
 
-#define IO_SPACE_LIMIT 0xffffffff
+#define BUILDIO_IOPORT(bwlq, type)                                      \
+        __BUILD_IOPORT_PFX(, bwlq, type)
 
-#ifdef CONFIG_HAS_IOPORT
+BUILDIO_IOPORT(b, u8)
+BUILDIO_IOPORT(w, u16)
+BUILDIO_IOPORT(l, u32)
+BUILDIO_IOPORT(q, u64)
+
+#define __BUILD_IOPORT_STRING(bwlq, type)                               \
+                                                                        \
+static inline void outs##bwlq(unsigned long port, const void *addr,     \
+                              unsigned int count)                       \
+{                                                                       \
+        const volatile type *__addr = addr;                             \
+                                                                        \
+        while (count--) {                                               \
+                out##bwlq(*__addr, port);                               \
+                __addr++;                                               \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void ins##bwlq(unsigned long port, void *addr,            \
+                             unsigned int count)                        \
+{                                                                       \
+        volatile type *__addr = addr;                                   \
+                                                                        \
+        while (count--) {                                               \
+                *__addr = in##bwlq(port);                               \
+                __addr++;                                               \
+        }                                                               \
+}
+
+__BUILD_IOPORT_STRING(b, u8)
+__BUILD_IOPORT_STRING(w, u16)
+__BUILD_IOPORT_STRING(l, u32)
+__BUILD_IOPORT_STRING(q, u64)
+
+#endif
 
 /*
- * This function provides a method for the generic case where a
- * board-specific ioport_map simply needs to return the port + some
- * arbitrary port base.
+ * Legacy SuperH on-chip I/O functions
  *
- * We use this at board setup time to implicitly set the port base, and
- * as a result, we can use the generic ioport_map.
+ * These are all deprecated, all new (and especially cross-platform) code
+ * should be using the __raw_xxx() routines directly.
  */
-static inline void __set_io_port_base(unsigned long pbase)
+static inline u8 __deprecated ctrl_inb(unsigned long addr)
 {
-        generic_io_base = pbase;
+        return __raw_readb(addr);
 }
 
-#define __ioport_map(p, n) sh_mv.mv_ioport_map((p), (n))
+static inline u16 __deprecated ctrl_inw(unsigned long addr)
+{
+        return __raw_readw(addr);
+}
 
-#endif
+static inline u32 __deprecated ctrl_inl(unsigned long addr)
+{
+        return __raw_readl(addr);
+}
+
+static inline u64 __deprecated ctrl_inq(unsigned long addr)
+{
+        return __raw_readq(addr);
+}
+
+static inline void __deprecated ctrl_outb(u8 v, unsigned long addr)
+{
+        __raw_writeb(v, addr);
+}
+
+static inline void __deprecated ctrl_outw(u16 v, unsigned long addr)
+{
+        __raw_writew(v, addr);
+}
+
+static inline void __deprecated ctrl_outl(u32 v, unsigned long addr)
+{
+        __raw_writel(v, addr);
+}
+
+static inline void __deprecated ctrl_outq(u64 v, unsigned long addr)
+{
+        __raw_writeq(v, addr);
+}
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* synco on SH-4A, otherwise a nop */
+#define mmiowb()                wmb()
 
 /* We really want to try and get these to memcpy etc */
 void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
@@ -395,10 +414,6 @@ static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
 #define ioremap_nocache ioremap
 #define iounmap         __iounmap
 
-#define maybebadio(port) \
-        printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
-               __func__, __LINE__, (port), (u32)__builtin_return_address(0))
-
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  * access
diff --git a/arch/sh/include/asm/io_generic.h b/arch/sh/include/asm/io_generic.h
index 491df93cbf8e..b5f6956f19c8 100644
--- a/arch/sh/include/asm/io_generic.h
+++ b/arch/sh/include/asm/io_generic.h
@@ -11,31 +11,6 @@
 #error "Don't include this header without a valid system prefix"
 #endif
 
-u8 IO_CONCAT(__IO_PREFIX,inb)(unsigned long);
-u16 IO_CONCAT(__IO_PREFIX,inw)(unsigned long);
-u32 IO_CONCAT(__IO_PREFIX,inl)(unsigned long);
-
-void IO_CONCAT(__IO_PREFIX,outb)(u8, unsigned long);
-void IO_CONCAT(__IO_PREFIX,outw)(u16, unsigned long);
-void IO_CONCAT(__IO_PREFIX,outl)(u32, unsigned long);
-
-u8 IO_CONCAT(__IO_PREFIX,inb_p)(unsigned long);
-u16 IO_CONCAT(__IO_PREFIX,inw_p)(unsigned long);
-u32 IO_CONCAT(__IO_PREFIX,inl_p)(unsigned long);
-void IO_CONCAT(__IO_PREFIX,outb_p)(u8, unsigned long);
-void IO_CONCAT(__IO_PREFIX,outw_p)(u16, unsigned long);
-void IO_CONCAT(__IO_PREFIX,outl_p)(u32, unsigned long);
-
-void IO_CONCAT(__IO_PREFIX,insb)(unsigned long, void *dst, unsigned long count);
-void IO_CONCAT(__IO_PREFIX,insw)(unsigned long, void *dst, unsigned long count);
-void IO_CONCAT(__IO_PREFIX,insl)(unsigned long, void *dst, unsigned long count);
-void IO_CONCAT(__IO_PREFIX,outsb)(unsigned long, const void *src, unsigned long count);
-void IO_CONCAT(__IO_PREFIX,outsw)(unsigned long, const void *src, unsigned long count);
-void IO_CONCAT(__IO_PREFIX,outsl)(unsigned long, const void *src, unsigned long count);
-
-void *IO_CONCAT(__IO_PREFIX,ioremap)(unsigned long offset, unsigned long size);
-void IO_CONCAT(__IO_PREFIX,iounmap)(void *addr);
-
 void __iomem *IO_CONCAT(__IO_PREFIX,ioport_map)(unsigned long addr, unsigned int size);
 void IO_CONCAT(__IO_PREFIX,ioport_unmap)(void __iomem *addr);
 void IO_CONCAT(__IO_PREFIX,mem_init)(void);
diff --git a/arch/sh/include/asm/ioctls.h b/arch/sh/include/asm/ioctls.h
index eb6c4c687972..84e85a792638 100644
--- a/arch/sh/include/asm/ioctls.h
+++ b/arch/sh/include/asm/ioctls.h
@@ -85,6 +85,7 @@
 #define TCSETSF2        _IOW('T', 45, struct termios2)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+#define TIOCGDEV        _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
 #define TIOCSIG         _IOW('T',0x36, int)  /* Generate signal on Pty slave */
 
 #define TIOCSERCONFIG   _IO('T', 83) /* 0x5453 */
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index a0b0cf79cf8a..dd5d6e5bf204 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -23,27 +23,6 @@ struct sh_machine_vector {
         void (*mv_init_irq)(void);
 
 #ifdef CONFIG_HAS_IOPORT
-        u8 (*mv_inb)(unsigned long);
-        u16 (*mv_inw)(unsigned long);
-        u32 (*mv_inl)(unsigned long);
-        void (*mv_outb)(u8, unsigned long);
-        void (*mv_outw)(u16, unsigned long);
-        void (*mv_outl)(u32, unsigned long);
-
-        u8 (*mv_inb_p)(unsigned long);
-        u16 (*mv_inw_p)(unsigned long);
-        u32 (*mv_inl_p)(unsigned long);
-        void (*mv_outb_p)(u8, unsigned long);
-        void (*mv_outw_p)(u16, unsigned long);
-        void (*mv_outl_p)(u32, unsigned long);
-
-        void (*mv_insb)(unsigned long, void *dst, unsigned long count);
-        void (*mv_insw)(unsigned long, void *dst, unsigned long count);
-        void (*mv_insl)(unsigned long, void *dst, unsigned long count);
-        void (*mv_outsb)(unsigned long, const void *src, unsigned long count);
-        void (*mv_outsw)(unsigned long, const void *src, unsigned long count);
-        void (*mv_outsl)(unsigned long, const void *src, unsigned long count);
-
         void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
         void (*mv_ioport_unmap)(void __iomem *);
 #endif
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index f6edc10aa0d3..de167d3a1a80 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -40,8 +40,8 @@
 #include <asm/system.h>
 
 #define user_mode(regs)                 (((regs)->sr & 0x40000000)==0)
-#define user_stack_pointer(regs)        ((unsigned long)(regs)->regs[15])
-#define kernel_stack_pointer(regs)      ((unsigned long)(regs)->regs[15])
+#define user_stack_pointer(_regs)       ((unsigned long)(_regs)->regs[15])
+#define kernel_stack_pointer(_regs)     ((unsigned long)(_regs)->regs[15])
 #define instruction_pointer(regs)       ((unsigned long)(regs)->pc)
 
 extern void show_regs(struct pt_regs *);
diff --git a/arch/sh/include/asm/ptrace_32.h b/arch/sh/include/asm/ptrace_32.h
index 35d9e257558c..6c2239cca1a2 100644
--- a/arch/sh/include/asm/ptrace_32.h
+++ b/arch/sh/include/asm/ptrace_32.h
@@ -76,7 +76,7 @@ struct pt_dspregs {
 #ifdef __KERNEL__
 
 #define MAX_REG_OFFSET          offsetof(struct pt_regs, tra)
-#define regs_return_value(regs) ((regs)->regs[0])
+#define regs_return_value(_regs)        ((_regs)->regs[0])
 
 #endif /* __KERNEL__ */
 
diff --git a/arch/sh/include/asm/ptrace_64.h b/arch/sh/include/asm/ptrace_64.h
index d43c1cb0bbe7..bf9be7764d69 100644
--- a/arch/sh/include/asm/ptrace_64.h
+++ b/arch/sh/include/asm/ptrace_64.h
@@ -13,7 +13,7 @@ struct pt_regs {
 #ifdef __KERNEL__
 
 #define MAX_REG_OFFSET          offsetof(struct pt_regs, tregs[7])
-#define regs_return_value(regs) ((regs)->regs[3])
+#define regs_return_value(_regs)        ((_regs)->regs[3])
 
 #endif /* __KERNEL__ */
 
diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h
index 9f4dd252c981..c48a9c3420da 100644
--- a/arch/sh/include/asm/unaligned-sh4a.h
+++ b/arch/sh/include/asm/unaligned-sh4a.h
@@ -18,10 +18,20 @@
  * of spill registers and blowing up when building at low optimization
  * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777.
  */
+#include <linux/unaligned/packed_struct.h>
 #include <linux/types.h>
 #include <asm/byteorder.h>
 
-static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
+static inline u16 sh4a_get_unaligned_cpu16(const u8 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        return p[0] | p[1] << 8;
+#else
+        return p[0] << 8 | p[1];
+#endif
+}
+
+static __always_inline u32 sh4a_get_unaligned_cpu32(const u8 *p)
 {
         unsigned long unaligned;
 
@@ -34,218 +44,148 @@ static __always_inline u32 __get_unaligned_cpu32(const u8 *p)
         return unaligned;
 }
 
-struct __una_u16 { u16 x __attribute__((packed)); };
-struct __una_u32 { u32 x __attribute__((packed)); };
-struct __una_u64 { u64 x __attribute__((packed)); };
-
-static inline u16 __get_unaligned_cpu16(const u8 *p)
-{
-#ifdef __LITTLE_ENDIAN
-        return p[0] | p[1] << 8;
-#else
-        return p[0] << 8 | p[1];
-#endif
-}
-
 /*
  * Even though movua.l supports auto-increment on the read side, it can
  * only store to r0 due to instruction encoding constraints, so just let
  * the compiler sort it out on its own.
  */
-static inline u64 __get_unaligned_cpu64(const u8 *p)
+static inline u64 sh4a_get_unaligned_cpu64(const u8 *p)
 {
 #ifdef __LITTLE_ENDIAN
-        return (u64)__get_unaligned_cpu32(p + 4) << 32 |
-                    __get_unaligned_cpu32(p);
+        return (u64)sh4a_get_unaligned_cpu32(p + 4) << 32 |
+                    sh4a_get_unaligned_cpu32(p);
 #else
-        return (u64)__get_unaligned_cpu32(p) << 32 |
-                    __get_unaligned_cpu32(p + 4);
+        return (u64)sh4a_get_unaligned_cpu32(p) << 32 |
+                    sh4a_get_unaligned_cpu32(p + 4);
 #endif
 }
 
 static inline u16 get_unaligned_le16(const void *p)
 {
-        return le16_to_cpu(__get_unaligned_cpu16(p));
+        return le16_to_cpu(sh4a_get_unaligned_cpu16(p));
 }
 
 static inline u32 get_unaligned_le32(const void *p)
 {
-        return le32_to_cpu(__get_unaligned_cpu32(p));
+        return le32_to_cpu(sh4a_get_unaligned_cpu32(p));
 }
 
 static inline u64 get_unaligned_le64(const void *p)
 {
-        return le64_to_cpu(__get_unaligned_cpu64(p));
+        return le64_to_cpu(sh4a_get_unaligned_cpu64(p));
 }
 
 static inline u16 get_unaligned_be16(const void *p)
 {
-        return be16_to_cpu(__get_unaligned_cpu16(p));
+        return be16_to_cpu(sh4a_get_unaligned_cpu16(p));
 }
 
 static inline u32 get_unaligned_be32(const void *p)
 {
-        return be32_to_cpu(__get_unaligned_cpu32(p));
+        return be32_to_cpu(sh4a_get_unaligned_cpu32(p));
 }
 
 static inline u64 get_unaligned_be64(const void *p)
 {
-        return be64_to_cpu(__get_unaligned_cpu64(p));
+        return be64_to_cpu(sh4a_get_unaligned_cpu64(p));
 }
 
-static inline void __put_le16_noalign(u8 *p, u16 val)
+static inline void nonnative_put_le16(u16 val, u8 *p)
 {
         *p++ = val;
         *p++ = val >> 8;
 }
 
-static inline void __put_le32_noalign(u8 *p, u32 val)
+static inline void nonnative_put_le32(u32 val, u8 *p)
 {
-        __put_le16_noalign(p, val);
-        __put_le16_noalign(p + 2, val >> 16);
+        nonnative_put_le16(val, p);
+        nonnative_put_le16(val >> 16, p + 2);
 }
 
-static inline void __put_le64_noalign(u8 *p, u64 val)
+static inline void nonnative_put_le64(u64 val, u8 *p)
 {
-        __put_le32_noalign(p, val);
-        __put_le32_noalign(p + 4, val >> 32);
+        nonnative_put_le32(val, p);
+        nonnative_put_le32(val >> 32, p + 4);
 }
 
-static inline void __put_be16_noalign(u8 *p, u16 val)
+static inline void nonnative_put_be16(u16 val, u8 *p)
 {
         *p++ = val >> 8;
         *p++ = val;
 }
 
-static inline void __put_be32_noalign(u8 *p, u32 val)
+static inline void nonnative_put_be32(u32 val, u8 *p)
 {
-        __put_be16_noalign(p, val >> 16);
-        __put_be16_noalign(p + 2, val);
+        nonnative_put_be16(val >> 16, p);
+        nonnative_put_be16(val, p + 2);
 }
 
-static inline void __put_be64_noalign(u8 *p, u64 val)
+static inline void nonnative_put_be64(u64 val, u8 *p)
 {
-        __put_be32_noalign(p, val >> 32);
-        __put_be32_noalign(p + 4, val);
+        nonnative_put_be32(val >> 32, p);
+        nonnative_put_be32(val, p + 4);
 }
 
 static inline void put_unaligned_le16(u16 val, void *p)
 {
 #ifdef __LITTLE_ENDIAN
-        ((struct __una_u16 *)p)->x = val;
+        __put_unaligned_cpu16(val, p);
 #else
-        __put_le16_noalign(p, val);
+        nonnative_put_le16(val, p);
 #endif
 }
 
 static inline void put_unaligned_le32(u32 val, void *p)
 {
 #ifdef __LITTLE_ENDIAN
-        ((struct __una_u32 *)p)->x = val;
+        __put_unaligned_cpu32(val, p);
 #else
-        __put_le32_noalign(p, val);
+        nonnative_put_le32(val, p);
 #endif
 }
 
 static inline void put_unaligned_le64(u64 val, void *p)
 {
 #ifdef __LITTLE_ENDIAN
-        ((struct __una_u64 *)p)->x = val;
+        __put_unaligned_cpu64(val, p);
 #else
-        __put_le64_noalign(p, val);
+        nonnative_put_le64(val, p);
 #endif
 }
 
 static inline void put_unaligned_be16(u16 val, void *p)
 {
 #ifdef __BIG_ENDIAN
-        ((struct __una_u16 *)p)->x = val;
+        __put_unaligned_cpu16(val, p);
 #else
-        __put_be16_noalign(p, val);
+        nonnative_put_be16(val, p);
 #endif
 }
 
 static inline void put_unaligned_be32(u32 val, void *p)
 {
 #ifdef __BIG_ENDIAN
-        ((struct __una_u32 *)p)->x = val;
+        __put_unaligned_cpu32(val, p);
 #else
-        __put_be32_noalign(p, val);
+        nonnative_put_be32(val, p);
 #endif
 }
 
 static inline void put_unaligned_be64(u64 val, void *p)
 {
 #ifdef __BIG_ENDIAN
-        ((struct __una_u64 *)p)->x = val;
+        __put_unaligned_cpu64(val, p);
 #else
-        __put_be64_noalign(p, val);
+        nonnative_put_be64(val, p);
 #endif
 }
 
 /*
- * Cause a link-time error if we try an unaligned access other than
- * 1,2,4 or 8 bytes long
+ * While it's a bit non-obvious, even though the generic le/be wrappers
+ * use the __get/put_xxx prefixing, they actually wrap in to the
+ * non-prefixed get/put_xxx variants as provided above.
  */
-extern void __bad_unaligned_access_size(void);
-
-#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({                     \
-        __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),                      \
-        __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)),   \
-        __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)),   \
-        __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)),   \
-        __bad_unaligned_access_size()))));                                      \
-        }))
-
-#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({                     \
-        __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),                      \
-        __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)),   \
-        __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)),   \
-        __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)),   \
-        __bad_unaligned_access_size()))));                                      \
-        }))
-
-#define __put_unaligned_le(val, ptr) ({                                 \
-        void *__gu_p = (ptr);                                           \
-        switch (sizeof(*(ptr))) {                                       \
-        case 1:                                                         \
-                *(u8 *)__gu_p = (__force u8)(val);                      \
-                break;                                                  \
-        case 2:                                                         \
-                put_unaligned_le16((__force u16)(val), __gu_p);         \
-                break;                                                  \
-        case 4:                                                         \
-                put_unaligned_le32((__force u32)(val), __gu_p);         \
-                break;                                                  \
-        case 8:                                                         \
-                put_unaligned_le64((__force u64)(val), __gu_p);         \
-                break;                                                  \
-        default:                                                        \
-                __bad_unaligned_access_size();                          \
-                break;                                                  \
-        }                                                               \
-        (void)0; })
-
-#define __put_unaligned_be(val, ptr) ({                                 \
-        void *__gu_p = (ptr);                                           \
-        switch (sizeof(*(ptr))) {                                       \
-        case 1:                                                         \
-                *(u8 *)__gu_p = (__force u8)(val);                      \
-                break;                                                  \
-        case 2:                                                         \
-                put_unaligned_be16((__force u16)(val), __gu_p);         \
-                break;                                                  \
-        case 4:                                                         \
-                put_unaligned_be32((__force u32)(val), __gu_p);         \
-                break;                                                  \
-        case 8:                                                         \
-                put_unaligned_be64((__force u64)(val), __gu_p);         \
-                break;                                                  \
-        default:                                                        \
-                __bad_unaligned_access_size();                          \
-                break;                                                  \
-        }                                                               \
-        (void)0; })
+#include <linux/unaligned/generic.h>
 
 #ifdef __LITTLE_ENDIAN
 # define get_unaligned __get_unaligned_le
diff --git a/arch/sh/include/mach-common/mach/romimage.h b/arch/sh/include/mach-common/mach/romimage.h
index 08fb42269ecd..3670455faaac 100644
--- a/arch/sh/include/mach-common/mach/romimage.h
+++ b/arch/sh/include/mach-common/mach/romimage.h
@@ -4,7 +4,7 @@
 
 #else /* __ASSEMBLY__ */
 
-extern inline void mmcif_update_progress(int nr)
+static inline void mmcif_update_progress(int nr)
 {
 }
 
diff --git a/arch/sh/include/mach-ecovec24/mach/romimage.h b/arch/sh/include/mach-ecovec24/mach/romimage.h
index 1dcf5e6c8d83..d63ef51ec186 100644
--- a/arch/sh/include/mach-ecovec24/mach/romimage.h
+++ b/arch/sh/include/mach-ecovec24/mach/romimage.h
@@ -35,7 +35,7 @@
 #define HIZCRA          0xa4050158
 #define PGDR            0xa405012c
 
-extern inline void mmcif_update_progress(int nr)
+static inline void mmcif_update_progress(int nr)
 {
         /* disable Hi-Z for LED pins */
         __raw_writew(__raw_readw(HIZCRA) & ~(1 << 1), HIZCRA);
diff --git a/arch/sh/include/mach-kfr2r09/mach/romimage.h b/arch/sh/include/mach-kfr2r09/mach/romimage.h
index 976256a323f2..7a883167c846 100644
--- a/arch/sh/include/mach-kfr2r09/mach/romimage.h
+++ b/arch/sh/include/mach-kfr2r09/mach/romimage.h
@@ -23,7 +23,7 @@
 
 #else /* __ASSEMBLY__ */
 
-extern inline void mmcif_update_progress(int nr)
+static inline void mmcif_update_progress(int nr)
 {
 }
 
diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h
index 40f0c2d3690c..a9cdac469927 100644
--- a/arch/sh/include/mach-sdk7786/mach/fpga.h
+++ b/arch/sh/include/mach-sdk7786/mach/fpga.h
@@ -14,11 +14,16 @@
 #define INTTESTR        0x040
 #define SYSSR           0x050
 #define NRGPR           0x060
+
 #define NMISR           0x070
+#define  NMISR_MAN_NMI  BIT(0)
+#define  NMISR_AUX_NMI  BIT(1)
+#define  NMISR_MASK     (NMISR_MAN_NMI | NMISR_AUX_NMI)
 
 #define NMIMR           0x080
 #define  NMIMR_MAN_NMIM BIT(0)  /* Manual NMI mask */
 #define  NMIMR_AUX_NMIM BIT(1)  /* Auxiliary NMI mask */
+#define  NMIMR_MASK     (NMIMR_MAN_NMIM | NMIMR_AUX_NMIM)
 
 #define INTBSR          0x090
 #define INTBMR          0x0a0
@@ -126,6 +131,9 @@
 extern void __iomem *sdk7786_fpga_base;
 extern void sdk7786_fpga_init(void);
 
+/* arch/sh/boards/mach-sdk7786/nmi.c */
+extern void sdk7786_nmi_init(void);
+
 #define SDK7786_FPGA_REGADDR(reg)       (sdk7786_fpga_base + (reg))
 
 /*
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index 8eed6a485446..77f7ae1d4647 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -11,7 +11,7 @@ endif
 
 CFLAGS_REMOVE_return_address.o = -pg
 
-obj-y   := clkdev.o debugtraps.o dma-nommu.o dumpstack.o                \
+obj-y   := debugtraps.o dma-nommu.o dumpstack.o                 \
            idle.o io.o irq.o irq_$(BITS).o kdebugfs.o                   \
            machvec.o nmi_debug.o process.o                              \
            process_$(BITS).o ptrace.o ptrace_$(BITS).o                  \
@@ -20,6 +20,11 @@ obj-y	:= clkdev.o debugtraps.o dma-nommu.o dumpstack.o 		\
            syscalls_$(BITS).o time.o topology.o traps.o                 \
            traps_$(BITS).o unwinder.o
 
+ifndef CONFIG_GENERIC_IOMAP
+obj-y                           += iomap.o
+obj-$(CONFIG_HAS_IOPORT)        += ioport.o
+endif
+
 obj-y                           += cpu/
 obj-$(CONFIG_VSYSCALL)          += vsyscall/
 obj-$(CONFIG_SMP)               += smp.o
@@ -39,7 +44,6 @@ obj-$(CONFIG_DUMP_CODE)		+= disassemble.o
 obj-$(CONFIG_HIBERNATION)       += swsusp.o
 obj-$(CONFIG_DWARF_UNWINDER)    += dwarf.o
 obj-$(CONFIG_PERF_EVENTS)       += perf_event.o perf_callchain.o
-obj-$(CONFIG_HAS_IOPORT)        += io_generic.o
 
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)                += hw_breakpoint.o
 obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)     += localtimer.o
diff --git a/arch/sh/kernel/clkdev.c b/arch/sh/kernel/clkdev.c
deleted file mode 100644
index 1f800ef4a735..000000000000
--- a/arch/sh/kernel/clkdev.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * arch/sh/kernel/clkdev.c
- *
- * Cloned from arch/arm/common/clkdev.c:
- *
- *  Copyright (C) 2008 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Helper for the clk API to assist looking up a struct clk.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/mutex.h>
-#include <linux/clk.h>
-#include <linux/slab.h>
-#include <linux/bootmem.h>
-#include <linux/mm.h>
-#include <asm/clock.h>
-#include <asm/clkdev.h>
-
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-/*
- * Find the correct struct clk for the device and connection ID.
- * We do slightly fuzzy matching here:
- *  An entry with a NULL ID is assumed to be a wildcard.
- *  If an entry has a device ID, it must match
- *  If an entry has a connection ID, it must match
- * Then we take the most specific entry - with the following
- * order of precedence: dev+con > dev only > con only.
- */
-static struct clk *clk_find(const char *dev_id, const char *con_id)
-{
-        struct clk_lookup *p;
-        struct clk *clk = NULL;
-        int match, best = 0;
-
-        list_for_each_entry(p, &clocks, node) {
-                match = 0;
-                if (p->dev_id) {
-                        if (!dev_id || strcmp(p->dev_id, dev_id))
-                                continue;
-                        match += 2;
-                }
-                if (p->con_id) {
-                        if (!con_id || strcmp(p->con_id, con_id))
-                                continue;
-                        match += 1;
-                }
-                if (match == 0)
-                        continue;
-
-                if (match > best) {
-                        clk = p->clk;
-                        best = match;
-                }
-        }
-        return clk;
-}
-
-struct clk *clk_get_sys(const char *dev_id, const char *con_id)
-{
-        struct clk *clk;
-
-        mutex_lock(&clocks_mutex);
-        clk = clk_find(dev_id, con_id);
-        mutex_unlock(&clocks_mutex);
-
-        return clk ? clk : ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get_sys);
-
-void clkdev_add(struct clk_lookup *cl)
-{
-        mutex_lock(&clocks_mutex);
-        list_add_tail(&cl->node, &clocks);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clkdev_add);
-
-void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
-{
-        mutex_lock(&clocks_mutex);
-        while (num--) {
-                list_add_tail(&cl->node, &clocks);
-                cl++;
-        }
-        mutex_unlock(&clocks_mutex);
-}
-
-#define MAX_DEV_ID      20
-#define MAX_CON_ID      16
-
-struct clk_lookup_alloc {
-        struct clk_lookup cl;
-        char    dev_id[MAX_DEV_ID];
-        char    con_id[MAX_CON_ID];
-};
-
-struct clk_lookup * __init_refok
-clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
-{
-        struct clk_lookup_alloc *cla;
-
-        if (!slab_is_available())
-                cla = alloc_bootmem_low_pages(sizeof(*cla));
-        else
-                cla = kzalloc(sizeof(*cla), GFP_KERNEL);
-
-        if (!cla)
-                return NULL;
-
-        cla->cl.clk = clk;
-        if (con_id) {
-                strlcpy(cla->con_id, con_id, sizeof(cla->con_id));
-                cla->cl.con_id = cla->con_id;
-        }
-
-        if (dev_fmt) {
-                va_list ap;
-
-                va_start(ap, dev_fmt);
-                vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
-                cla->cl.dev_id = cla->dev_id;
-                va_end(ap);
-        }
-
-        return &cla->cl;
-}
-EXPORT_SYMBOL(clkdev_alloc);
-
-int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
-        struct device *dev)
-{
-        struct clk *r = clk_get(dev, id);
-        struct clk_lookup *l;
-
-        if (IS_ERR(r))
-                return PTR_ERR(r);
-
-        l = clkdev_alloc(r, alias, alias_dev_name);
-        clk_put(r);
-        if (!l)
-                return -ENODEV;
-        clkdev_add(l);
-        return 0;
-}
-EXPORT_SYMBOL(clk_add_alias);
-
-/*
- * clkdev_drop - remove a clock dynamically allocated
- */
-void clkdev_drop(struct clk_lookup *cl)
-{
-        struct clk_lookup_alloc *cla = container_of(cl, struct clk_lookup_alloc, cl);
-
-        mutex_lock(&clocks_mutex);
-        list_del(&cl->node);
-        mutex_unlock(&clocks_mutex);
-        kfree(cla);
-}
-EXPORT_SYMBOL(clkdev_drop);
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 4edcb60a1355..d49c2135fd48 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -20,4 +20,4 @@ obj-$(CONFIG_SH_CLK_CPG_LEGACY)	+= clock-cpg.o
 obj-$(CONFIG_SH_FPU)            += fpu.o
 obj-$(CONFIG_SH_FPU_EMU)        += fpu.o
 
-obj-y   += irq/ init.o clock.o hwblk.o
+obj-y   += irq/ init.o clock.o hwblk.o proc.o
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index e2f63d68da51..dd0e0f211359 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -2,7 +2,7 @@
 #include <linux/compiler.h>
 #include <linux/slab.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 
 static struct clk master_clk = {
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 50f887dda565..4187cf4fe185 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -48,20 +48,4 @@ int __init clk_init(void)
         return ret;
 }
 
-/*
- * Returns a clock. Note that we first try to use device id on the bus
- * and clock name. If this fails, we try to use clock name only.
- */
-struct clk *clk_get(struct device *dev, const char *con_id)
-{
-        const char *dev_id = dev ? dev_name(dev) : NULL;
-
-        return clk_get_sys(dev_id, con_id);
-}
-EXPORT_SYMBOL_GPL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL_GPL(clk_put);
 
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
new file mode 100644
index 000000000000..e80a936f409a
--- /dev/null
+++ b/arch/sh/kernel/cpu/proc.c
@@ -0,0 +1,148 @@
+#include <linux/seq_file.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/machvec.h>
+#include <asm/processor.h>
+
+static const char *cpu_name[] = {
+        [CPU_SH7201]    = "SH7201",
+        [CPU_SH7203]    = "SH7203",     [CPU_SH7263]    = "SH7263",
+        [CPU_SH7206]    = "SH7206",     [CPU_SH7619]    = "SH7619",
+        [CPU_SH7705]    = "SH7705",     [CPU_SH7706]    = "SH7706",
+        [CPU_SH7707]    = "SH7707",     [CPU_SH7708]    = "SH7708",
+        [CPU_SH7709]    = "SH7709",     [CPU_SH7710]    = "SH7710",
+        [CPU_SH7712]    = "SH7712",     [CPU_SH7720]    = "SH7720",
+        [CPU_SH7721]    = "SH7721",     [CPU_SH7729]    = "SH7729",
+        [CPU_SH7750]    = "SH7750",     [CPU_SH7750S]   = "SH7750S",
+        [CPU_SH7750R]   = "SH7750R",    [CPU_SH7751]    = "SH7751",
+        [CPU_SH7751R]   = "SH7751R",    [CPU_SH7760]    = "SH7760",
+        [CPU_SH4_202]   = "SH4-202",    [CPU_SH4_501]   = "SH4-501",
+        [CPU_SH7763]    = "SH7763",     [CPU_SH7770]    = "SH7770",
+        [CPU_SH7780]    = "SH7780",     [CPU_SH7781]    = "SH7781",
+        [CPU_SH7343]    = "SH7343",     [CPU_SH7785]    = "SH7785",
+        [CPU_SH7786]    = "SH7786",     [CPU_SH7757]    = "SH7757",
+        [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
+        [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
+        [CPU_MXG]       = "MX-G",       [CPU_SH7723]    = "SH7723",
+        [CPU_SH7366]    = "SH7366",     [CPU_SH7724]    = "SH7724",
+        [CPU_SH_NONE]   = "Unknown"
+};
+
+const char *get_cpu_subtype(struct sh_cpuinfo *c)
+{
+        return cpu_name[c->type];
+}
+EXPORT_SYMBOL(get_cpu_subtype);
+
+#ifdef CONFIG_PROC_FS
+/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
+static const char *cpu_flags[] = {
+        "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
+        "ptea", "llsc", "l2", "op32", "pteaex", NULL
+};
+
+static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
+{
+        unsigned long i;
+
+        seq_printf(m, "cpu flags\t:");
+
+        if (!c->flags) {
+                seq_printf(m, " %s\n", cpu_flags[0]);
+                return;
+        }
+
+        for (i = 0; cpu_flags[i]; i++)
+                if ((c->flags & (1 << i)))
+                        seq_printf(m, " %s", cpu_flags[i+1]);
+
+        seq_printf(m, "\n");
+}
+
+static void show_cacheinfo(struct seq_file *m, const char *type,
+                           struct cache_info info)
+{
+        unsigned int cache_size;
+
+        cache_size = info.ways * info.sets * info.linesz;
+
+        seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
+                   type, cache_size >> 10, info.ways);
+}
+
+/*
+ *      Get CPU information for use by the procfs.
+ */
+static int show_cpuinfo(struct seq_file *m, void *v)
+{
+        struct sh_cpuinfo *c = v;
+        unsigned int cpu = c - cpu_data;
+
+        if (!cpu_online(cpu))
+                return 0;
+
+        if (cpu == 0)
+                seq_printf(m, "machine\t\t: %s\n", get_system_type());
+        else
+                seq_printf(m, "\n");
+
+        seq_printf(m, "processor\t: %d\n", cpu);
+        seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
+        seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
+        if (c->cut_major == -1)
+                seq_printf(m, "cut\t\t: unknown\n");
+        else if (c->cut_minor == -1)
+                seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
+        else
+                seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
+
+        show_cpuflags(m, c);
+
+        seq_printf(m, "cache type\t: ");
+
+        /*
+         * Check for what type of cache we have, we support both the
+         * unified cache on the SH-2 and SH-3, as well as the harvard
+         * style cache on the SH-4.
+         */
+        if (c->icache.flags & SH_CACHE_COMBINED) {
+                seq_printf(m, "unified\n");
+                show_cacheinfo(m, "cache", c->icache);
+        } else {
+                seq_printf(m, "split (harvard)\n");
+                show_cacheinfo(m, "icache", c->icache);
+                show_cacheinfo(m, "dcache", c->dcache);
+        }
+
+        /* Optional secondary cache */
+        if (c->flags & CPU_HAS_L2_CACHE)
+                show_cacheinfo(m, "scache", c->scache);
+
+        seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
+
+        seq_printf(m, "bogomips\t: %lu.%02lu\n",
+                     c->loops_per_jiffy/(500000/HZ),
+                     (c->loops_per_jiffy/(5000/HZ)) % 100);
+
+        return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+        return *pos < NR_CPUS ? cpu_data + *pos : NULL;
+}
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
+{
+        ++*pos;
+        return c_start(m, pos);
+}
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+const struct seq_operations cpuinfo_op = {
+        .start  = c_start,
+        .next   = c_next,
+        .stop   = c_stop,
+        .show   = show_cpuinfo,
+};
+#endif /* CONFIG_PROC_FS */
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 0c9f24d7a02f..5b7f12e58a8d 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -14,24 +14,18 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/io.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
-#include <asm/io.h>
+#include <asm/processor.h>
 
 static const int pll1rate[] = {1,2};
 static const int pfc_divisors[] = {1,2,0,4};
-
-#if (CONFIG_SH_CLK_MD == 1) || (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 5) || (CONFIG_SH_CLK_MD == 6)
-#define PLL2 (2)
-#else
-#error "Illigal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
+        clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
 static struct clk_ops sh7619_master_clk_ops = {
@@ -70,6 +64,14 @@ static struct clk_ops *sh7619_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
+            test_mode_pin(MODE_PIN2 | MODE_PIN1))
+                pll2_mult = 2;
+        else if (test_mode_pin(MODE_PIN0) || test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+
+        BUG_ON(!pll2_mult);
+
         if (idx < ARRAY_SIZE(sh7619_clk_ops))
                 *ops = sh7619_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index c509c40cba4b..1174e2d96c03 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -22,19 +22,12 @@ static const int pll1rate[]={1,2,3,4,6,8};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 0)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 3)
-#define PLL2 (1)
-#else
-#error "Illegal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate = 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
+        clk->rate = 10000000 * pll2_mult *
+               pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7201_master_clk_ops = {
@@ -80,6 +73,13 @@ static struct clk_ops *sh7201_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
+                pll2_mult = 1;
+        else if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 2;
+        else
+                pll2_mult = 4;
+
         if (idx < ARRAY_SIZE(sh7201_clk_ops))
                 *ops = sh7201_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 7e75d8f79502..95a008e8b735 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -25,21 +25,11 @@ static const int pll1rate[]={8,12,16,0};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 0)
-#define PLL2 (1)
-#elif (CONFIG_SH_CLK_MD == 1)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 3)
-#define PLL2 (4)
-#else
-#error "Illegal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * PLL2 ;
+        clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult;
 }
 
 static struct clk_ops sh7203_master_clk_ops = {
@@ -79,6 +69,13 @@ static struct clk_ops *sh7203_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+        else if (test_mode_pin(MODE_PIN0))
+                pll2_mult = 2;
+        else
+                pll2_mult = 1;
+
         if (idx < ARRAY_SIZE(sh7203_clk_ops))
                 *ops = sh7203_clk_ops[idx];
 }
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index b27a5e2687ab..3c314d7cd6e6 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -22,19 +22,11 @@ static const int pll1rate[]={1,2,3,4,6,8};
 static const int pfc_divisors[]={1,2,3,4,6,8,12};
 #define ifc_divisors pfc_divisors
 
-#if (CONFIG_SH_CLK_MD == 2)
-#define PLL2 (4)
-#elif (CONFIG_SH_CLK_MD == 6)
-#define PLL2 (2)
-#elif (CONFIG_SH_CLK_MD == 7)
-#define PLL2 (1)
-#else
-#error "Illigal Clock Mode!"
-#endif
+static unsigned int pll2_mult;
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
+        clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7206_master_clk_ops = {
@@ -79,7 +71,13 @@ static struct clk_ops *sh7206_clk_ops[] = {
 
 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 {
+        if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0))
+                pll2_mult = 1;
+        else if (test_mode_pin(MODE_PIN2 | MODE_PIN1))
+                pll2_mult = 2;
+        else if (test_mode_pin(MODE_PIN1))
+                pll2_mult = 4;
+
         if (idx < ARRAY_SIZE(sh7206_clk_ops))
                 *ops = sh7206_clk_ops[idx];
 }
-
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 6282a839e08e..3f6f8e98635c 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -13,7 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/err.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 
diff --git a/arch/sh/kernel/cpu/sh4/perf_event.c b/arch/sh/kernel/cpu/sh4/perf_event.c
index dbf3b4bb71fe..748955df018d 100644
--- a/arch/sh/kernel/cpu/sh4/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4/perf_event.c
@@ -250,4 +250,4 @@ static int __init sh7750_pmu_init(void)
 
         return register_sh_pmu(&sh7750_pmu);
 }
-arch_initcall(sh7750_pmu_init);
+early_initcall(sh7750_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 71291ae201b9..93c646072c1b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 
 /* SH7343 registers */
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 7ce5bbcd4084..049dc0628ccc 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 
 /* SH7366 registers */
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 2030f3d9fac7..9d23a36f0647 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/hwblk.h>
 #include <cpu/sh7722.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index d3938f0d3702..55493cd5bd8f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/clk.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/hwblk.h>
 #include <cpu/sh7723.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 271c0b325a9a..d08fa953c88b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -22,7 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/clk.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/hwblk.h>
 #include <cpu/sh7724.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index ce39a2ae8c6c..e073e3eb4c3d 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 1f1df48008cd..599630fc4d3b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -13,7 +13,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 #include <asm/io.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 62d706350060..8894926479a6 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -12,7 +12,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 #include <asm/io.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index c3e458aaa2b7..2d960247f3eb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -14,7 +14,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/cpufreq.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 #include <cpu/sh7785.h>
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index 597c9fbe49c6..42e403be9076 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -13,7 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 4f70df6b6169..1afdb93b8ccb 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -14,7 +14,7 @@
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <asm/clkdev.h>
+#include <linux/clkdev.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
 
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c
index 580276525731..17e6bebfede0 100644
--- a/arch/sh/kernel/cpu/sh4a/perf_event.c
+++ b/arch/sh/kernel/cpu/sh4a/perf_event.c
@@ -284,4 +284,4 @@ static int __init sh4a_pmu_init(void)
 
         return register_sh_pmu(&sh4a_pmu);
 }
-arch_initcall(sh4a_pmu_init);
+early_initcall(sh4a_pmu_init);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index c016c0004714..0170dbda1d00 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -522,10 +522,37 @@ static struct platform_device dma0_device = {
         },
 };
 
+#define USB_EHCI_START 0xffe70000
+#define USB_OHCI_START 0xffe70400
+
+static struct resource usb_ehci_resources[] = {
+        [0] = {
+                .start  = USB_EHCI_START,
+                .end    = USB_EHCI_START + 0x3ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 77,
+                .end    = 77,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb_ehci_device = {
+        .name           = "sh_ehci",
+        .id             = -1,
+        .dev = {
+                .dma_mask               = &usb_ehci_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(usb_ehci_resources),
+        .resource       = usb_ehci_resources,
+};
+
 static struct resource usb_ohci_resources[] = {
         [0] = {
-                .start  = 0xffe70400,
-                .end    = 0xffe704ff,
+                .start  = USB_OHCI_START,
+                .end    = USB_OHCI_START + 0x3ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -535,12 +562,11 @@ static struct resource usb_ohci_resources[] = {
         },
 };
 
-static u64 usb_ohci_dma_mask = DMA_BIT_MASK(32);
 static struct platform_device usb_ohci_device = {
         .name           = "sh_ohci",
         .id             = -1,
         .dev = {
-                .dma_mask               = &usb_ohci_dma_mask,
+                .dma_mask               = &usb_ohci_device.dev.coherent_dma_mask,
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
@@ -570,6 +596,7 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
 
 static struct platform_device *sh7786_devices[] __initdata = {
         &dma0_device,
+        &usb_ehci_device,
         &usb_ohci_device,
 };
 
diff --git a/arch/sh/kernel/io_generic.c b/arch/sh/kernel/io_generic.c
deleted file mode 100644
index 447d78f666f9..000000000000
--- a/arch/sh/kernel/io_generic.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * arch/sh/kernel/io_generic.c
- *
- * Copyright (C) 2000  Niibe Yutaka
- * Copyright (C) 2005 - 2007 Paul Mundt
- *
- * Generic I/O routine. These can be used where a machine specific version
- * is not required.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/module.h>
-#include <linux/io.h>
-#include <asm/machvec.h>
-
-#ifdef CONFIG_CPU_SH3
-/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
- * workaround. */
-/* I'm not sure SH7709 has this kind of bug */
-#define dummy_read()    __raw_readb(0xba000000)
-#else
-#define dummy_read()
-#endif
-
-unsigned long generic_io_base = 0;
-
-u8 generic_inb(unsigned long port)
-{
-        return __raw_readb(__ioport_map(port, 1));
-}
-
-u16 generic_inw(unsigned long port)
-{
-        return __raw_readw(__ioport_map(port, 2));
-}
-
-u32 generic_inl(unsigned long port)
-{
-        return __raw_readl(__ioport_map(port, 4));
-}
-
-u8 generic_inb_p(unsigned long port)
-{
-        unsigned long v = generic_inb(port);
-
-        ctrl_delay();
-        return v;
-}
-
-u16 generic_inw_p(unsigned long port)
-{
-        unsigned long v = generic_inw(port);
-
-        ctrl_delay();
-        return v;
-}
-
-u32 generic_inl_p(unsigned long port)
-{
-        unsigned long v = generic_inl(port);
-
-        ctrl_delay();
-        return v;
-}
-
-/*
- * insb/w/l all read a series of bytes/words/longs from a fixed port
- * address. However as the port address doesn't change we only need to
- * convert the port address to real address once.
- */
-
-void generic_insb(unsigned long port, void *dst, unsigned long count)
-{
-        __raw_readsb(__ioport_map(port, 1), dst, count);
-        dummy_read();
-}
-
-void generic_insw(unsigned long port, void *dst, unsigned long count)
-{
-        __raw_readsw(__ioport_map(port, 2), dst, count);
-        dummy_read();
-}
-
-void generic_insl(unsigned long port, void *dst, unsigned long count)
-{
-        __raw_readsl(__ioport_map(port, 4), dst, count);
-        dummy_read();
-}
-
-void generic_outb(u8 b, unsigned long port)
-{
-        __raw_writeb(b, __ioport_map(port, 1));
-}
-
-void generic_outw(u16 b, unsigned long port)
-{
-        __raw_writew(b, __ioport_map(port, 2));
-}
-
-void generic_outl(u32 b, unsigned long port)
-{
-        __raw_writel(b, __ioport_map(port, 4));
-}
-
-void generic_outb_p(u8 b, unsigned long port)
-{
-        generic_outb(b, port);
-        ctrl_delay();
-}
-
-void generic_outw_p(u16 b, unsigned long port)
-{
-        generic_outw(b, port);
-        ctrl_delay();
-}
-
-void generic_outl_p(u32 b, unsigned long port)
-{
-        generic_outl(b, port);
-        ctrl_delay();
-}
-
-/*
- * outsb/w/l all write a series of bytes/words/longs to a fixed port
- * address. However as the port address doesn't change we only need to
- * convert the port address to real address once.
- */
-void generic_outsb(unsigned long port, const void *src, unsigned long count)
-{
-        __raw_writesb(__ioport_map(port, 1), src, count);
-        dummy_read();
-}
-
-void generic_outsw(unsigned long port, const void *src, unsigned long count)
-{
-        __raw_writesw(__ioport_map(port, 2), src, count);
-        dummy_read();
-}
-
-void generic_outsl(unsigned long port, const void *src, unsigned long count)
-{
-        __raw_writesl(__ioport_map(port, 4), src, count);
-        dummy_read();
-}
-
-void __iomem *generic_ioport_map(unsigned long addr, unsigned int size)
-{
-#ifdef P1SEG
-        if (PXSEG(addr) >= P1SEG)
-                return (void __iomem *)addr;
-#endif
-
-        return (void __iomem *)(addr + generic_io_base);
-}
-
-void generic_ioport_unmap(void __iomem *addr)
-{
-}
-
-#ifndef CONFIG_GENERIC_IOMAP
-void __iomem *ioport_map(unsigned long port, unsigned int nr)
-{
-        void __iomem *ret;
-
-        ret = __ioport_map_trapped(port, nr);
-        if (ret)
-                return ret;
-
-        return __ioport_map(port, nr);
-}
-EXPORT_SYMBOL(ioport_map);
-
-void ioport_unmap(void __iomem *addr)
-{
-        sh_mv.mv_ioport_unmap(addr);
-}
-EXPORT_SYMBOL(ioport_unmap);
-#endif /* CONFIG_GENERIC_IOMAP */
diff --git a/arch/sh/kernel/iomap.c b/arch/sh/kernel/iomap.c
new file mode 100644
index 000000000000..2e8e8b9b9cef
--- /dev/null
+++ b/arch/sh/kernel/iomap.c
@@ -0,0 +1,165 @@
+/*
+ * arch/sh/kernel/iomap.c
+ *
+ * Copyright (C) 2000  Niibe Yutaka
+ * Copyright (C) 2005 - 2007 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+
+unsigned int ioread8(void __iomem *addr)
+{
+        return readb(addr);
+}
+EXPORT_SYMBOL(ioread8);
+
+unsigned int ioread16(void __iomem *addr)
+{
+        return readw(addr);
+}
+EXPORT_SYMBOL(ioread16);
+
+unsigned int ioread16be(void __iomem *addr)
+{
+        return be16_to_cpu(__raw_readw(addr));
+}
+EXPORT_SYMBOL(ioread16be);
+
+unsigned int ioread32(void __iomem *addr)
+{
+        return readl(addr);
+}
+EXPORT_SYMBOL(ioread32);
+
+unsigned int ioread32be(void __iomem *addr)
+{
+        return be32_to_cpu(__raw_readl(addr));
+}
+EXPORT_SYMBOL(ioread32be);
+
+void iowrite8(u8 val, void __iomem *addr)
+{
+        writeb(val, addr);
+}
+EXPORT_SYMBOL(iowrite8);
+
+void iowrite16(u16 val, void __iomem *addr)
+{
+        writew(val, addr);
+}
+EXPORT_SYMBOL(iowrite16);
+
+void iowrite16be(u16 val, void __iomem *addr)
+{
+        __raw_writew(cpu_to_be16(val), addr);
+}
+EXPORT_SYMBOL(iowrite16be);
+
+void iowrite32(u32 val, void __iomem *addr)
+{
+        writel(val, addr);
+}
+EXPORT_SYMBOL(iowrite32);
+
+void iowrite32be(u32 val, void __iomem *addr)
+{
+        __raw_writel(cpu_to_be32(val), addr);
+}
+EXPORT_SYMBOL(iowrite32be);
+
+/*
+ * These are the "repeat MMIO read/write" functions.
+ * Note the "__raw" accesses, since we don't want to
+ * convert to CPU byte order. We write in "IO byte
+ * order" (we also don't have IO barriers).
+ */
+static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
+{
+        while (--count >= 0) {
+                u8 data = __raw_readb(addr);
+                *dst = data;
+                dst++;
+        }
+}
+
+static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
+{
+        while (--count >= 0) {
+                u16 data = __raw_readw(addr);
+                *dst = data;
+                dst++;
+        }
+}
+
+static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
+{
+        while (--count >= 0) {
+                u32 data = __raw_readl(addr);
+                *dst = data;
+                dst++;
+        }
+}
+
+static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
+{
+        while (--count >= 0) {
+                __raw_writeb(*src, addr);
+                src++;
+        }
+}
+
+static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
+{
+        while (--count >= 0) {
+                __raw_writew(*src, addr);
+                src++;
+        }
+}
+
+static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
+{
+        while (--count >= 0) {
+                __raw_writel(*src, addr);
+                src++;
+        }
+}
+
+void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+        mmio_insb(addr, dst, count);
+}
+EXPORT_SYMBOL(ioread8_rep);
+
+void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+        mmio_insw(addr, dst, count);
+}
+EXPORT_SYMBOL(ioread16_rep);
+
+void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
+{
+        mmio_insl(addr, dst, count);
+}
+EXPORT_SYMBOL(ioread32_rep);
+
+void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+        mmio_outsb(addr, src, count);
+}
+EXPORT_SYMBOL(iowrite8_rep);
+
+void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+        mmio_outsw(addr, src, count);
+}
+EXPORT_SYMBOL(iowrite16_rep);
+
+void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
+{
+        mmio_outsl(addr, src, count);
+}
+EXPORT_SYMBOL(iowrite32_rep);
diff --git a/arch/sh/kernel/ioport.c b/arch/sh/kernel/ioport.c
new file mode 100644
index 000000000000..e3ad6103e7c1
--- /dev/null
+++ b/arch/sh/kernel/ioport.c
@@ -0,0 +1,43 @@
+/*
+ * arch/sh/kernel/ioport.c
+ *
+ * Copyright (C) 2000  Niibe Yutaka
+ * Copyright (C) 2005 - 2007 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+
+const unsigned long sh_io_port_base __read_mostly = -1;
+EXPORT_SYMBOL(sh_io_port_base);
+
+void __iomem *__ioport_map(unsigned long addr, unsigned int size)
+{
+        if (sh_mv.mv_ioport_map)
+                return sh_mv.mv_ioport_map(addr, size);
+
+        return (void __iomem *)(addr + sh_io_port_base);
+}
+EXPORT_SYMBOL(__ioport_map);
+
+void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+        void __iomem *ret;
+
+        ret = __ioport_map_trapped(port, nr);
+        if (ret)
+                return ret;
+
+        return __ioport_map(port, nr);
+}
+EXPORT_SYMBOL(ioport_map);
+
+void ioport_unmap(void __iomem *addr)
+{
+        if (sh_mv.mv_ioport_unmap)
+                sh_mv.mv_ioport_unmap(addr);
+}
+EXPORT_SYMBOL(ioport_unmap);
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index 9f9bb63616ad..3d722e49db08 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -118,28 +118,6 @@ void __init sh_mv_setup(void)
                 sh_mv.mv_##elem = generic_##elem; \
 } while (0)
 
-#ifdef CONFIG_HAS_IOPORT
-
-#ifdef P2SEG
-        __set_io_port_base(P2SEG);
-#else
-        __set_io_port_base(0);
-#endif
-
-        mv_set(inb);    mv_set(inw);    mv_set(inl);
-        mv_set(outb);   mv_set(outw);   mv_set(outl);
-
-        mv_set(inb_p);  mv_set(inw_p);  mv_set(inl_p);
-        mv_set(outb_p); mv_set(outw_p); mv_set(outl_p);
-
-        mv_set(insb);   mv_set(insw);   mv_set(insl);
-        mv_set(outsb);  mv_set(outsw);  mv_set(outsl);
-
-        mv_set(ioport_map);
-        mv_set(ioport_unmap);
-
-#endif
-
         mv_set(irq_demux);
         mv_set(mode_pins);
         mv_set(mem_init);
diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index 5a4b33435650..2ee21a47b5af 100644
--- a/arch/sh/kernel/perf_event.c
+++ b/arch/sh/kernel/perf_event.c
@@ -389,7 +389,7 @@ int __cpuinit register_sh_pmu(struct sh_pmu *_pmu)
 
         WARN_ON(_pmu->num_events > MAX_HWEVENTS);
 
-        perf_pmu_register(&pmu);
+        perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
         perf_cpu_notifier(sh_pmu_notifier);
         return 0;
 }
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index d6b018c7ebdc..4f267160c515 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -12,7 +12,6 @@
 #include <linux/initrd.h>
 #include <linux/bootmem.h>
 #include <linux/console.h>
-#include <linux/seq_file.h>
 #include <linux/root_dev.h>
 #include <linux/utsname.h>
 #include <linux/nodemask.h>
@@ -319,146 +318,3 @@ int test_mode_pin(int pin)
 {
         return sh_mv.mv_mode_pins() & pin;
 }
-
-static const char *cpu_name[] = {
-        [CPU_SH7201]    = "SH7201",
-        [CPU_SH7203]    = "SH7203",     [CPU_SH7263]    = "SH7263",
-        [CPU_SH7206]    = "SH7206",     [CPU_SH7619]    = "SH7619",
-        [CPU_SH7705]    = "SH7705",     [CPU_SH7706]    = "SH7706",
-        [CPU_SH7707]    = "SH7707",     [CPU_SH7708]    = "SH7708",
-        [CPU_SH7709]    = "SH7709",     [CPU_SH7710]    = "SH7710",
-        [CPU_SH7712]    = "SH7712",     [CPU_SH7720]    = "SH7720",
-        [CPU_SH7721]    = "SH7721",     [CPU_SH7729]    = "SH7729",
-        [CPU_SH7750]    = "SH7750",     [CPU_SH7750S]   = "SH7750S",
-        [CPU_SH7750R]   = "SH7750R",    [CPU_SH7751]    = "SH7751",
-        [CPU_SH7751R]   = "SH7751R",    [CPU_SH7760]    = "SH7760",
-        [CPU_SH4_202]   = "SH4-202",    [CPU_SH4_501]   = "SH4-501",
-        [CPU_SH7763]    = "SH7763",     [CPU_SH7770]    = "SH7770",
-        [CPU_SH7780]    = "SH7780",     [CPU_SH7781]    = "SH7781",
-        [CPU_SH7343]    = "SH7343",     [CPU_SH7785]    = "SH7785",
-        [CPU_SH7786]    = "SH7786",     [CPU_SH7757]    = "SH7757",
-        [CPU_SH7722]    = "SH7722",     [CPU_SHX3]      = "SH-X3",
-        [CPU_SH5_101]   = "SH5-101",    [CPU_SH5_103]   = "SH5-103",
-        [CPU_MXG]       = "MX-G",       [CPU_SH7723]    = "SH7723",
-        [CPU_SH7366]    = "SH7366",     [CPU_SH7724]    = "SH7724",
-        [CPU_SH_NONE]   = "Unknown"
-};
-
-const char *get_cpu_subtype(struct sh_cpuinfo *c)
-{
-        return cpu_name[c->type];
-}
-EXPORT_SYMBOL(get_cpu_subtype);
-
-#ifdef CONFIG_PROC_FS
-/* Symbolic CPU flags, keep in sync with asm/cpu-features.h */
-static const char *cpu_flags[] = {
-        "none", "fpu", "p2flush", "mmuassoc", "dsp", "perfctr",
-        "ptea", "llsc", "l2", "op32", "pteaex", NULL
-};
-
-static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
-{
-        unsigned long i;
-
-        seq_printf(m, "cpu flags\t:");
-
-        if (!c->flags) {
-                seq_printf(m, " %s\n", cpu_flags[0]);
-                return;
-        }
-
-        for (i = 0; cpu_flags[i]; i++)
-                if ((c->flags & (1 << i)))
-                        seq_printf(m, " %s", cpu_flags[i+1]);
-
-        seq_printf(m, "\n");
-}
-
-static void show_cacheinfo(struct seq_file *m, const char *type,
-                           struct cache_info info)
-{
-        unsigned int cache_size;
-
-        cache_size = info.ways * info.sets * info.linesz;
-
-        seq_printf(m, "%s size\t: %2dKiB (%d-way)\n",
-                   type, cache_size >> 10, info.ways);
-}
-
-/*
- *      Get CPU information for use by the procfs.
- */
-static int show_cpuinfo(struct seq_file *m, void *v)
-{
-        struct sh_cpuinfo *c = v;
-        unsigned int cpu = c - cpu_data;
-
-        if (!cpu_online(cpu))
-                return 0;
-
-        if (cpu == 0)
-                seq_printf(m, "machine\t\t: %s\n", get_system_type());
-        else
-                seq_printf(m, "\n");
-
-        seq_printf(m, "processor\t: %d\n", cpu);
-        seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
-        seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
-        if (c->cut_major == -1)
-                seq_printf(m, "cut\t\t: unknown\n");
-        else if (c->cut_minor == -1)
-                seq_printf(m, "cut\t\t: %d.x\n", c->cut_major);
-        else
-                seq_printf(m, "cut\t\t: %d.%d\n", c->cut_major, c->cut_minor);
-
-        show_cpuflags(m, c);
-
-        seq_printf(m, "cache type\t: ");
-
-        /*
-         * Check for what type of cache we have, we support both the
-         * unified cache on the SH-2 and SH-3, as well as the harvard
-         * style cache on the SH-4.
-         */
-        if (c->icache.flags & SH_CACHE_COMBINED) {
-                seq_printf(m, "unified\n");
-                show_cacheinfo(m, "cache", c->icache);
-        } else {
-                seq_printf(m, "split (harvard)\n");
-                show_cacheinfo(m, "icache", c->icache);
-                show_cacheinfo(m, "dcache", c->dcache);
-        }
-
-        /* Optional secondary cache */
-        if (c->flags & CPU_HAS_L2_CACHE)
-                show_cacheinfo(m, "scache", c->scache);
-
-        seq_printf(m, "address sizes\t: %u bits physical\n", c->phys_bits);
-
-        seq_printf(m, "bogomips\t: %lu.%02lu\n",
-                     c->loops_per_jiffy/(500000/HZ),
-                     (c->loops_per_jiffy/(5000/HZ)) % 100);
-
-        return 0;
-}
-
-static void *c_start(struct seq_file *m, loff_t *pos)
-{
-        return *pos < NR_CPUS ? cpu_data + *pos : NULL;
-}
-static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-{
-        ++*pos;
-        return c_start(m, pos);
-}
-static void c_stop(struct seq_file *m, void *v)
-{
-}
-const struct seq_operations cpuinfo_op = {
-        .start  = c_start,
-        .next   = c_next,
-        .stop   = c_stop,
-        .show   = show_cpuinfo,
-};
-#endif /* CONFIG_PROC_FS */
diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile
index 97e3feb9ff1b..a2c5898c1ab1 100644
--- a/arch/sparc/boot/Makefile
+++ b/arch/sparc/boot/Makefile
@@ -6,25 +6,24 @@
 ROOT_IMG        := /usr/src/root.img
 ELFTOAOUT       := elftoaout
 
-hostprogs-y     := piggyback_32 piggyback_64 btfixupprep
+hostprogs-y     := piggyback btfixupprep
 targets         := tftpboot.img btfix.o btfix.S image zImage vmlinux.aout
 clean-files     := System.map
 
 quiet_cmd_elftoaout     = ELFTOAOUT $@
       cmd_elftoaout     = $(ELFTOAOUT) $(obj)/image -o $@
+quiet_cmd_piggy         = PIGGY   $@
+      cmd_piggy         = $(obj)/piggyback $(BITS) $@ System.map $(ROOT_IMG)
+quiet_cmd_strip         = STRIP   $@
+      cmd_strip         = $(STRIP) -R .comment -R .note -K sun4u_init -K _end -K _start $< -o $@
 
 ifeq ($(CONFIG_SPARC32),y)
-quiet_cmd_piggy         = PIGGY   $@
-      cmd_piggy         = $(obj)/piggyback_32 $@ System.map $(ROOT_IMG)
 quiet_cmd_btfix         = BTFIX   $@
       cmd_btfix         = $(OBJDUMP) -x vmlinux | $(obj)/btfixupprep > $@
 quiet_cmd_sysmap        = SYSMAP  $(obj)/System.map
       cmd_sysmap        = $(CONFIG_SHELL) $(srctree)/scripts/mksysmap
 quiet_cmd_image = LD      $@
       cmd_image = $(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) $(LDFLAGS_$(@F)) -o $@
-quiet_cmd_strip = STRIP   $@
-      cmd_strip = $(STRIP) -R .comment -R .note -K sun4u_init -K _end -K _start $(obj)/image -o $@
-
 
 define rule_image
         $(if $($(quiet)cmd_image),               \
@@ -57,10 +56,7 @@ $(obj)/image: $(obj)/btfix.o FORCE
 
 $(obj)/zImage: $(obj)/image
         $(call if_changed,strip)
-
-$(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback_32 System.map $(ROOT_IMG) FORCE
-        $(call if_changed,elftoaout)
-        $(call if_changed,piggy)
+        @echo '  kernel: $@ is ready'
 
 $(obj)/btfix.S: $(obj)/btfixupprep vmlinux FORCE
         $(call if_changed,btfix)
@@ -68,11 +64,6 @@ $(obj)/btfix.S: $(obj)/btfixupprep vmlinux FORCE
 endif
 
 ifeq ($(CONFIG_SPARC64),y)
-quiet_cmd_piggy     = PIGGY   $@
-      cmd_piggy     = $(obj)/piggyback_64 $@ System.map $(ROOT_IMG)
-quiet_cmd_strip     = STRIP   $@
-      cmd_strip     = $(STRIP) -R .comment -R .note -K sun4u_init -K _end -K _start vmlinux -o $@
-
 
 # Actual linking
 $(obj)/image: vmlinux FORCE
@@ -81,10 +72,6 @@ $(obj)/image: vmlinux FORCE
 
 $(obj)/zImage: $(obj)/image
         $(call if_changed,gzip)
-
-$(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback_64 System.map $(ROOT_IMG) FORCE
-        $(call if_changed,elftoaout)
-        $(call if_changed,piggy)
         @echo '  kernel: $@ is ready'
 
 $(obj)/vmlinux.aout: vmlinux FORCE
@@ -92,3 +79,6 @@ $(obj)/vmlinux.aout: vmlinux FORCE
         @echo '  kernel: $@ is ready'
 endif
 
+$(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback System.map $(ROOT_IMG) FORCE
+        $(call if_changed,elftoaout)
+        $(call if_changed,piggy)
diff --git a/arch/sparc/boot/piggyback.c b/arch/sparc/boot/piggyback.c
new file mode 100644
index 000000000000..c0a798fcf030
--- /dev/null
+++ b/arch/sparc/boot/piggyback.c
@@ -0,0 +1,272 @@
+/*
+   Simple utility to make a single-image install kernel with initial ramdisk
+   for Sparc tftpbooting without need to set up nfs.
+
+   Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+   Pete Zaitcev <zaitcev@yahoo.com> endian fixes for cross-compiles, 2000.
+   Copyright (C) 2011 Sam Ravnborg <sam@ravnborg.org>
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#include <dirent.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <ctype.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <stdio.h>
+
+#include <sys/types.h>
+#include <sys/stat.h>
+
+/*
+ * Note: run this on an a.out kernel (use elftoaout for it),
+ * as PROM looks for a.out image only.
+ */
+
+#define AOUT_TEXT_OFFSET   32
+
+static int is64bit = 0;
+
+/* align to power-of-two size */
+static int align(int n)
+{
+        if (is64bit)
+                return (n + 0x1fff) & ~0x1fff;
+        else
+                return (n + 0xfff) & ~0xfff;
+}
+
+/* read two bytes as big endian */
+static unsigned short ld2(char *p)
+{
+        return (p[0] << 8) | p[1];
+}
+
+/* save 4 bytes as big endian */
+static void st4(char *p, unsigned int x)
+{
+        p[0] = x >> 24;
+        p[1] = x >> 16;
+        p[2] = x >> 8;
+        p[3] = x;
+}
+
+static void die(const char *str)
+{
+        perror(str);
+        exit(1);
+}
+
+static void usage(void)
+{
+        /* fs_img.gz is an image of initial ramdisk. */
+        fprintf(stderr, "Usage: piggyback bits vmlinux.aout System.map fs_img.gz\n");
+        fprintf(stderr, "\tKernel image will be modified in place.\n");
+        exit(1);
+}
+
+static int start_line(const char *line)
+{
+        if (strcmp(line + 8, " T _start\n") == 0)
+                return 1;
+        else if (strcmp(line + 16, " T _start\n") == 0)
+                return 1;
+        return 0;
+}
+
+static int end_line(const char *line)
+{
+        if (strcmp(line + 8, " A _end\n") == 0)
+                return 1;
+        else if (strcmp (line + 16, " A _end\n") == 0)
+                return 1;
+        return 0;
+}
+
+/*
+ * Find address for start and end in System.map.
+ * The file looks like this:
+ * f0004000 T _start
+ * f0379f79 A _end
+ * 1234567890123456
+ * ^coloumn 1
+ * There is support for 64 bit addresses too.
+ *
+ * Return 0 if either start or end is not found
+ */
+static int get_start_end(const char *filename, unsigned int *start,
+                                               unsigned int *end)
+{
+        FILE *map;
+        char buffer[1024];
+
+        *start = 0;
+        *end = 0;
+        map = fopen(filename, "r");
+        if (!map)
+                die(filename);
+        while (fgets(buffer, 1024, map)) {
+                if (start_line(buffer))
+                        *start = strtoul(buffer, NULL, 16);
+                else if (end_line(buffer))
+                        *end = strtoul(buffer, NULL, 16);
+        }
+        fclose (map);
+
+        if (*start == 0 || *end == 0)
+                return 0;
+
+        return 1;
+}
+
+#define LOOKBACK (128 * 4)
+#define BUFSIZE 1024
+/*
+ * Find the HdrS entry from head_32/head_64.
+ * We check if it is at the beginning of the file (sparc64 case)
+ * and if not we search for it.
+ * When we search do so in steps of 4 as HdrS is on a 4-byte aligned
+ * address (it is on same alignment as sparc instructions)
+ * Return the offset to the HdrS entry (as off_t)
+ */
+static off_t get_hdrs_offset(int kernelfd, const char *filename)
+{
+        char buffer[BUFSIZE];
+        off_t offset;
+        int i;
+
+        if (lseek(kernelfd, 0, SEEK_SET) < 0)
+                die("lseek");
+        if (read(kernelfd, buffer, BUFSIZE) != BUFSIZE)
+                die(filename);
+
+        if (buffer[40] == 'H' && buffer[41] == 'd' &&
+            buffer[42] == 'r' && buffer[43] == 'S') {
+                return 40;
+        } else {
+                /*  Find the gokernel label */
+                /* Decode offset from branch instruction */
+                offset = ld2(buffer + AOUT_TEXT_OFFSET + 2) << 2;
+                /* Go back 512 bytes so we do not miss HdrS */
+                offset -= LOOKBACK;
+                /* skip a.out header */
+                offset += AOUT_TEXT_OFFSET;
+                if (lseek(kernelfd, offset, SEEK_SET) < 0)
+                        die("lseek");
+                if (read(kernelfd, buffer, BUFSIZE) != BUFSIZE)
+                        die(filename);
+
+                for (i = 0; i < LOOKBACK; i += 4) {
+                        if (buffer[i + 0] == 'H' && buffer[i + 1] == 'd' &&
+                            buffer[i + 2] == 'r' && buffer[i + 3] == 'S') {
+                                return offset + i;
+                        }
+                }
+        }
+        fprintf (stderr, "Couldn't find headers signature in %s\n", filename);
+        exit(1);
+}
+
+int main(int argc,char **argv)
+{
+        static char aout_magic[] = { 0x01, 0x03, 0x01, 0x07 };
+        char buffer[1024];
+        unsigned int i, start, end;
+        off_t offset;
+        struct stat s;
+        int image, tail;
+
+        if (argc != 5)
+                usage();
+        if (strcmp(argv[1], "64") == 0)
+                is64bit = 1;
+        if (stat (argv[4], &s) < 0)
+                die(argv[4]);
+
+        if (!get_start_end(argv[3], &start, &end)) {
+                fprintf(stderr, "Could not determine start and end from %s\n",
+                        argv[3]);
+                exit(1);
+        }
+        if ((image = open(argv[2], O_RDWR)) < 0)
+                die(argv[2]);
+        if (read(image, buffer, 512) != 512)
+                die(argv[2]);
+        if (memcmp(buffer, aout_magic, 4) != 0) {
+                fprintf (stderr, "Not a.out. Don't blame me.\n");
+                exit(1);
+        }
+        /*
+         * We need to fill in values for
+         * sparc_ramdisk_image + sparc_ramdisk_size
+         * To locate these symbols search for the "HdrS" text which appear
+         * in the image a little before the gokernel symbol.
+         * See definition of these in init_32.S
+         */
+
+        offset = get_hdrs_offset(image, argv[2]);
+        /* skip HdrS + LINUX_VERSION_CODE + HdrS version */
+        offset += 10;
+
+        if (lseek(image, offset, 0) < 0)
+                die("lseek");
+
+        /*
+         * root_flags = 0
+         * root_dev = 1 (RAMDISK_MAJOR)
+         * ram_flags = 0
+         * sparc_ramdisk_image = "PAGE aligned address after _end")
+         * sparc_ramdisk_size = size of image
+         */
+        st4(buffer, 0);
+        st4(buffer + 4, 0x01000000);
+        st4(buffer + 8, align(end + 32));
+        st4(buffer + 12, s.st_size);
+
+        if (write(image, buffer + 2, 14) != 14)
+                die(argv[2]);
+
+        /* For sparc64 update a_text and clear a_data + a_bss */
+        if (is64bit)
+        {
+                if (lseek(image, 4, 0) < 0)
+                        die("lseek");
+                /* a_text */
+                st4(buffer, align(end + 32 + 8191) - (start & ~0x3fffffUL) +
+                            s.st_size);
+                /* a_data */
+                st4(buffer + 4, 0);
+                /* a_bss */
+                st4(buffer + 8, 0);
+                if (write(image, buffer, 12) != 12)
+                        die(argv[2]);
+        }
+
+        /* seek page aligned boundary in the image file and add boot image */
+        if (lseek(image, AOUT_TEXT_OFFSET - start + align(end + 32), 0) < 0)
+                die("lseek");
+        if ((tail = open(argv[4], O_RDONLY)) < 0)
+                die(argv[4]);
+        while ((i = read(tail, buffer, 1024)) > 0)
+                if (write(image, buffer, i) != i)
+                        die(argv[2]);
+        if (close(image) < 0)
+                die("close");
+        if (close(tail) < 0)
+                die("close");
+        return 0;
+}
diff --git a/arch/sparc/boot/piggyback_32.c b/arch/sparc/boot/piggyback_32.c
deleted file mode 100644
index ac944aec7301..000000000000
--- a/arch/sparc/boot/piggyback_32.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
-   Simple utility to make a single-image install kernel with initial ramdisk
-   for Sparc tftpbooting without need to set up nfs.
-
-   Copyright (C) 1996 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
-   Pete Zaitcev <zaitcev@yahoo.com> endian fixes for cross-compiles, 2000.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License, or
-   (at your option) any later version.
-   
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
-   
-#include <stdio.h>
-#include <string.h>
-#include <ctype.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <dirent.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-/*
- * Note: run this on an a.out kernel (use elftoaout for it),
- * as PROM looks for a.out image only.
- */
-
-static unsigned short ld2(char *p)
-{
-        return (p[0] << 8) | p[1];
-}
-
-static unsigned int ld4(char *p)
-{
-        return (p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3];
-}
-
-static void st4(char *p, unsigned int x)
-{
-        p[0] = x >> 24;
-        p[1] = x >> 16;
-        p[2] = x >> 8;
-        p[3] = x;
-}
-
-static void usage(void)
-{
-        /* fs_img.gz is an image of initial ramdisk. */
-        fprintf(stderr, "Usage: piggyback vmlinux.aout System.map fs_img.gz\n");
-        fprintf(stderr, "\tKernel image will be modified in place.\n");
-        exit(1);
-}
-
-static void die(char *str)
-{
-        perror (str);
-        exit(1);
-}
-
-int main(int argc,char **argv)
-{
-        static char aout_magic[] = { 0x01, 0x03, 0x01, 0x07 };
-        char buffer[1024], *q, *r;
-        unsigned int i, j, k, start, end, offset;
-        FILE *map;
-        struct stat s;
-        int image, tail;
-
-        if (argc != 4) usage();
-        start = end = 0;
-        if (stat (argv[3], &s) < 0) die (argv[3]);
-        map = fopen (argv[2], "r");
-        if (!map) die(argv[2]);
-        while (fgets (buffer, 1024, map)) {
-                if (!strcmp (buffer + 8, " T start\n") || !strcmp (buffer + 16, " T start\n"))
-                        start = strtoul (buffer, NULL, 16);
-                else if (!strcmp (buffer + 8, " A _end\n") || !strcmp (buffer + 16, " A _end\n"))
-                        end = strtoul (buffer, NULL, 16);
-        }
-        fclose (map);
-        if (!start || !end) {
-                fprintf (stderr, "Could not determine start and end from System.map\n");
-                exit(1);
-        }
-        if ((image = open(argv[1],O_RDWR)) < 0) die(argv[1]);
-        if (read(image,buffer,512) != 512) die(argv[1]);
-        if (memcmp (buffer, "\177ELF", 4) == 0) {
-                q = buffer + ld4(buffer + 28);
-                i = ld4(q + 4) + ld4(buffer + 24) - ld4(q + 8);
-                if (lseek(image,i,0) < 0) die("lseek");
-                if (read(image,buffer,512) != 512) die(argv[1]);
-                j = 0;
-        } else if (memcmp(buffer, aout_magic, 4) == 0) {
-                i = j = 32;
-        } else {
-                fprintf (stderr, "Not ELF nor a.out. Don't blame me.\n");
-                exit(1);
-        }
-        k = i;
-        i += (ld2(buffer + j + 2)<<2) - 512;
-        if (lseek(image,i,0) < 0) die("lseek");
-        if (read(image,buffer,1024) != 1024) die(argv[1]);
-        for (q = buffer, r = q + 512; q < r; q += 4) {
-                if (*q == 'H' && q[1] == 'd' && q[2] == 'r' && q[3] == 'S')
-                        break;
-        }
-        if (q == r) {
-                fprintf (stderr, "Couldn't find headers signature in the kernel.\n");
-                exit(1);
-        }
-        offset = i + (q - buffer) + 10;
-        if (lseek(image, offset, 0) < 0) die ("lseek");
-
-        st4(buffer, 0);
-        st4(buffer + 4, 0x01000000);
-        st4(buffer + 8, (end + 32 + 4095) & ~4095);
-        st4(buffer + 12, s.st_size);
-
-        if (write(image,buffer+2,14) != 14) die (argv[1]);
-        if (lseek(image, k - start + ((end + 32 + 4095) & ~4095), 0) < 0) die ("lseek");
-        if ((tail = open(argv[3],O_RDONLY)) < 0) die(argv[3]);
-        while ((i = read (tail,buffer,1024)) > 0)
-                if (write(image,buffer,i) != i) die (argv[1]);
-        if (close(image) < 0) die("close");
-        if (close(tail) < 0) die("close");
-        return 0;
-}
diff --git a/arch/sparc/boot/piggyback_64.c b/arch/sparc/boot/piggyback_64.c
deleted file mode 100644
index a26a686cb5aa..000000000000
--- a/arch/sparc/boot/piggyback_64.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
-   Simple utility to make a single-image install kernel with initial ramdisk
-   for Sparc64 tftpbooting without need to set up nfs.
-   
-   Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
-   
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License, or
-   (at your option) any later version.
-   
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
-   
-#include <stdio.h>
-#include <string.h>
-#include <ctype.h>
-#include <errno.h>
-#include <fcntl.h>
-#include <dirent.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-
-/* Note: run this on an a.out kernel (use elftoaout for it), as PROM looks for a.out image onlly
-   usage: piggyback vmlinux System.map tail, where tail is gzipped fs of the initial ramdisk */
-
-static void die(char *str)
-{
-        perror (str);
-        exit(1);
-}
-
-int main(int argc,char **argv)
-{
-        char buffer [1024], *q, *r;
-        unsigned int i, j, k, start, end, offset;
-        FILE *map;
-        struct stat s;
-        int image, tail;
-        
-        start = end = 0;
-        if (stat (argv[3], &s) < 0) die (argv[3]);
-        map = fopen (argv[2], "r");
-        if (!map) die(argv[2]);
-        while (fgets (buffer, 1024, map)) {
-                if (!strcmp (buffer + 19, "_start\n"))
-                start = strtoul (buffer + 8, NULL, 16);
-                else if (!strcmp (buffer + 19, "_end\n"))
-                end = strtoul (buffer + 8, NULL, 16);
-        }
-        fclose (map);
-        if ((image = open(argv[1],O_RDWR)) < 0) die(argv[1]);
-        if (read(image,buffer,512) != 512) die(argv[1]);
-        if (!memcmp (buffer, "\177ELF", 4)) {
-                unsigned int *p = (unsigned int *)(buffer + *(unsigned int *)(buffer + 28));
-                
-                i = p[1] + *(unsigned int *)(buffer + 24) - p[2];
-                if (lseek(image,i,0) < 0) die("lseek");
-                if (read(image,buffer,512) != 512) die(argv[1]);
-                j = 0;
-        } else if (*(unsigned int *)buffer == 0x01030107) {
-                i = j = 32;
-        } else {
-                fprintf (stderr, "Not ELF nor a.out. Don't blame me.\n");
-                exit(1);
-        }
-        k = i;
-        if (j == 32 && buffer[40] == 'H' && buffer[41] == 'd' && buffer[42] == 'r' && buffer[43] == 'S') {
-                offset = 40 + 10;
-        } else {
-                i += ((*(unsigned short *)(buffer + j + 2))<<2) - 512;
-                if (lseek(image,i,0) < 0) die("lseek");
-                if (read(image,buffer,1024) != 1024) die(argv[1]);
-                for (q = buffer, r = q + 512; q < r; q += 4) {
-                        if (*q == 'H' && q[1] == 'd' && q[2] == 'r' && q[3] == 'S')
-                                break;
-                }
-                if (q == r) {
-                        fprintf (stderr, "Couldn't find headers signature in the kernel.\n");
-                        exit(1);
-                }
-                offset = i + (q - buffer) + 10;
-        }
-        if (lseek(image, offset, 0) < 0) die ("lseek");
-        *(unsigned *)buffer = 0;
-        *(unsigned *)(buffer + 4) = 0x01000000;
-        *(unsigned *)(buffer + 8) = ((end + 32 + 8191) & ~8191);
-        *(unsigned *)(buffer + 12) = s.st_size;
-        if (write(image,buffer+2,14) != 14) die (argv[1]);
-        if (lseek(image, 4, 0) < 0) die ("lseek");
-        *(unsigned *)buffer = ((end + 32 + 8191) & ~8191) - (start & ~0x3fffffUL) + s.st_size;
-        *(unsigned *)(buffer + 4) = 0;
-        *(unsigned *)(buffer + 8) = 0;
-        if (write(image,buffer,12) != 12) die (argv[1]);
-        if (lseek(image, k - start + ((end + 32 + 8191) & ~8191), 0) < 0) die ("lseek");
-        if ((tail = open(argv[3],O_RDONLY)) < 0) die(argv[3]);
-        while ((i = read (tail,buffer,1024)) > 0)
-                if (write(image,buffer,i) != i) die (argv[1]);
-        if (close(image) < 0) die("close");
-        if (close(tail) < 0) die("close");
-        return 0;
-}
diff --git a/arch/sparc/include/asm/ioctls.h b/arch/sparc/include/asm/ioctls.h
index 53f4ee009bdd..ed3807b96bb5 100644
--- a/arch/sparc/include/asm/ioctls.h
+++ b/arch/sparc/include/asm/ioctls.h
@@ -19,6 +19,7 @@
 #define TCSETS2         _IOW('T', 13, struct termios2)
 #define TCSETSW2        _IOW('T', 14, struct termios2)
 #define TCSETSF2        _IOW('T', 15, struct termios2)
+#define TIOCGDEV        _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
 
 /* Note that all the ioctls that are not available in Linux have a 
  * double underscore on the front to: a) avoid some programs to
diff --git a/arch/sparc/include/asm/leon.h b/arch/sparc/include/asm/leon.h
index 3ea5964c43b4..8580d1764f90 100644
--- a/arch/sparc/include/asm/leon.h
+++ b/arch/sparc/include/asm/leon.h
@@ -224,6 +224,18 @@ static inline void sparc_leon3_disable_cache(void)
                           "sta %%l2, [%%g0] 2\n\t" : : : "l1", "l2");
 };
 
+static inline unsigned long sparc_leon3_asr17(void)
+{
+        u32 asr17;
+        __asm__ __volatile__ ("rd %%asr17, %0\n\t" : "=r"(asr17));
+        return asr17;
+};
+
+static inline int sparc_leon3_cpuid(void)
+{
+        return sparc_leon3_asr17() >> 28;
+}
+
 #endif /*!__ASSEMBLY__*/
 
 #ifdef CONFIG_SMP
diff --git a/arch/sparc/include/asm/leon_amba.h b/arch/sparc/include/asm/leon_amba.h
index 618e88821795..263c719e96f5 100644
--- a/arch/sparc/include/asm/leon_amba.h
+++ b/arch/sparc/include/asm/leon_amba.h
@@ -100,9 +100,8 @@ struct leon3_irqctrl_regs_map {
         u32 mpbroadcast;
         u32 notused02;
         u32 notused03;
-        u32 notused10;
-        u32 notused11;
-        u32 notused12;
+        u32 ampctrl;
+        u32 icsel[2];
         u32 notused13;
         u32 notused20;
         u32 notused21;
@@ -112,6 +111,7 @@ struct leon3_irqctrl_regs_map {
         u32 force[16];
         /* Extended IRQ registers */
         u32 intid[16];  /* 0xc0 */
+        u32 unused[(0x1000-0x100)/4];
 };
 
 struct leon3_apbuart_regs_map {
diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h
index 9e5c64084b86..71e5e9aeb67e 100644
--- a/arch/sparc/include/asm/oplib_32.h
+++ b/arch/sparc/include/asm/oplib_32.h
@@ -48,18 +48,6 @@ extern void prom_init(struct linux_romvec *rom_ptr);
 /* Boot argument acquisition, returns the boot command line string. */
 extern char *prom_getbootargs(void);
 
-/* Device utilities. */
-
-/* Map and unmap devices in IO space at virtual addresses. Note that the
- * virtual address you pass is a request and the prom may put your mappings
- * somewhere else, so check your return value as that is where your new
- * mappings really are!
- *
- * Another note, these are only available on V2 or higher proms!
- */
-extern char *prom_mapio(char *virt_hint, int io_space, unsigned int phys_addr, unsigned int num_bytes);
-extern void prom_unmapio(char *virt_addr, unsigned int num_bytes);
-
 /* Miscellaneous routines, don't really fit in any category per se. */
 
 /* Reboot the machine with the command line passed. */
@@ -76,7 +64,7 @@ extern void prom_cmdline(void);
 /* Enter the prom, with no chance of continuation for the stand-alone
  * which calls this.
  */
-extern void prom_halt(void) __attribute__ ((noreturn));
+extern void __noreturn prom_halt(void);
 
 /* Set the PROM 'sync' callback function to the passed function pointer.
  * When the user gives the 'sync' command at the prom prompt while the
@@ -117,25 +105,6 @@ extern void prom_write(const char *buf, unsigned int len);
 extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table,
                          int context, char *program_counter);
 
-/* Stop the CPU with the passed device tree node. */
-extern int prom_stopcpu(int cpunode);
-
-/* Idle the CPU with the passed device tree node. */
-extern int prom_idlecpu(int cpunode);
-
-/* Re-Start the CPU with the passed device tree node. */
-extern int prom_restartcpu(int cpunode);
-
-/* PROM memory allocation facilities... */
-
-/* Allocated at possibly the given virtual address a chunk of the
- * indicated size.
- */
-extern char *prom_alloc(char *virt_hint, unsigned int size);
-
-/* Free a previously allocated chunk. */
-extern void prom_free(char *virt_addr, unsigned int size);
-
 /* Sun4/sun4c specific memory-management startup hook. */
 
 /* Map the passed segment in the given context at the passed
@@ -144,6 +113,8 @@ extern void prom_free(char *virt_addr, unsigned int size);
 extern void prom_putsegment(int context, unsigned long virt_addr,
                             int physical_segment);
 
+/* Initialize the memory lists based upon the prom version. */
+void prom_meminit(void);
 
 /* PROM device tree traversal functions... */
 
@@ -178,19 +149,11 @@ extern int prom_getbool(phandle node, char *prop);
 /* Acquire a string property, null string on error. */
 extern void prom_getstring(phandle node, char *prop, char *buf, int bufsize);
 
-/* Does the passed node have the given "name"? YES=1 NO=0 */
-extern int prom_nodematch(phandle thisnode, char *name);
-
 /* Search all siblings starting at the passed node for "name" matching
  * the given string.  Returns the node on success, zero on failure.
  */
 extern phandle prom_searchsiblings(phandle node_start, char *name);
 
-/* Return the first property type, as a string, for the given node.
- * Returns a null string on error.
- */
-extern char *prom_firstprop(phandle node, char *buffer);
-
 /* Returns the next property after the passed property for the given
  * node.  Returns null string on failure.
  */
@@ -199,9 +162,6 @@ extern char *prom_nextprop(phandle node, char *prev_property, char *buffer);
 /* Returns phandle of the path specified */
 extern phandle prom_finddevice(char *name);
 
-/* Returns 1 if the specified node has given property. */
-extern int prom_node_has_property(phandle node, char *property);
-
 /* Set the indicated property at the given node with the passed value.
  * Returns the number of bytes of your value that the prom took.
  */
@@ -219,6 +179,8 @@ extern void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nr
 extern void prom_apply_generic_ranges(phandle node, phandle parent,
                                       struct linux_prom_registers *sbusregs, int nregs);
 
+void prom_ranges_init(void);
+
 /* CPU probing helpers.  */
 int cpu_find_by_instance(int instance, phandle *prom_node, int *mid);
 int cpu_find_by_mid(int mid, phandle *prom_node);
diff --git a/arch/sparc/include/asm/oplib_64.h b/arch/sparc/include/asm/oplib_64.h
index 8cd0df34e82b..97a90475c314 100644
--- a/arch/sparc/include/asm/oplib_64.h
+++ b/arch/sparc/include/asm/oplib_64.h
@@ -18,8 +18,8 @@ extern char prom_version[];
  */
 extern phandle prom_root_node;
 
-/* PROM stdin and stdout */
-extern int prom_stdin, prom_stdout;
+/* PROM stdout */
+extern int prom_stdout;
 
 /* /chosen node of the prom device tree, this stays constant after
  * initialization is complete.
diff --git a/arch/sparc/include/asm/perf_event.h b/arch/sparc/include/asm/perf_event.h
index 6e8bfa1786da..4d3dbe3703e9 100644
--- a/arch/sparc/include/asm/perf_event.h
+++ b/arch/sparc/include/asm/perf_event.h
@@ -4,8 +4,6 @@
 #ifdef CONFIG_PERF_EVENTS
 #include <asm/ptrace.h>
 
-extern void init_hw_perf_events(void);
-
 #define perf_arch_fetch_caller_regs(regs, ip)           \
 do {                                                    \
         unsigned long _pstate, _asi, _pil, _i7, _fp;    \
@@ -26,8 +24,6 @@ do {							\
         (regs)->u_regs[UREG_I6] = _fp;                  \
         (regs)->u_regs[UREG_I7] = _i7;                  \
 } while (0)
-#else
-static inline void init_hw_perf_events(void)    { }
 #endif
 
 #endif
diff --git a/arch/sparc/kernel/auxio_32.c b/arch/sparc/kernel/auxio_32.c
index 35f48837871a..8505e0ac78ba 100644
--- a/arch/sparc/kernel/auxio_32.c
+++ b/arch/sparc/kernel/auxio_32.c
@@ -121,7 +121,7 @@ void __init auxio_power_probe(void)
         node = prom_searchsiblings(node, "obio");
         node = prom_getchild(node);
         node = prom_searchsiblings(node, "power");
-        if (node == 0 || node == -1)
+        if (node == 0 || (s32)node == -1)
                 return;
 
         /* Map the power control register. */
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index e447938d39cf..0dc714fa23d8 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -375,5 +375,5 @@ static int __init cpu_type_probe(void)
         return 0;
 }
 
-arch_initcall(cpu_type_probe);
+early_initcall(cpu_type_probe);
 #endif
diff --git a/arch/sparc/kernel/head_32.S b/arch/sparc/kernel/head_32.S
index 21bb2590d4ae..59423491cef8 100644
--- a/arch/sparc/kernel/head_32.S
+++ b/arch/sparc/kernel/head_32.S
@@ -73,12 +73,11 @@ sun4e_notsup:
 
         /* The Sparc trap table, bootloader gives us control at _start. */
         __HEAD
-        .globl  start, _stext, _start, __stext
+        .globl  _stext, _start, __stext
         .globl  trapbase
 _start:   /* danger danger */
 __stext:
 _stext:
-start:
 trapbase:
 #ifdef CONFIG_SMP
 trapbase_cpu0:
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index f01c42661ee5..fdab7f854f80 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -23,15 +23,16 @@
 #include "prom.h"
 #include "irq.h"
 
-struct leon3_irqctrl_regs_map *leon3_irqctrl_regs; /* interrupt controller base address, initialized by amba_init() */
-struct leon3_gptimer_regs_map *leon3_gptimer_regs; /* timer controller base address, initialized by amba_init() */
+struct leon3_irqctrl_regs_map *leon3_irqctrl_regs; /* interrupt controller base address */
+struct leon3_gptimer_regs_map *leon3_gptimer_regs; /* timer controller base address */
 struct amba_apb_device leon_percpu_timer_dev[16];
 
 int leondebug_irq_disable;
 int leon_debug_irqout;
 static int dummy_master_l10_counter;
 
-unsigned long leon3_gptimer_irq; /* interrupt controller irq number, initialized by amba_init() */
+unsigned long leon3_gptimer_irq; /* interrupt controller irq number */
+unsigned long leon3_gptimer_idx; /* Timer Index (0..6) within Timer Core */
 unsigned int sparc_leon_eirq;
 #define LEON_IMASK ((&leon3_irqctrl_regs->mask[0]))
 
@@ -105,21 +106,79 @@ static void leon_disable_irq(unsigned int irq_nr)
 void __init leon_init_timers(irq_handler_t counter_fn)
 {
         int irq;
+        struct device_node *rootnp, *np, *nnp;
+        struct property *pp;
+        int len;
+        int cpu, icsel;
+        int ampopts;
 
         leondebug_irq_disable = 0;
         leon_debug_irqout = 0;
         master_l10_counter = (unsigned int *)&dummy_master_l10_counter;
         dummy_master_l10_counter = 0;
 
-        if (leon3_gptimer_regs && leon3_irqctrl_regs) {
-                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].val, 0);
-                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].rld,
-                                      (((1000000 / HZ) - 1)));
-                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].ctrl, 0);
+        /*Find IRQMP IRQ Controller Registers base address otherwise bail out.*/
+        rootnp = of_find_node_by_path("/ambapp0");
+        if (!rootnp)
+                goto bad;
+        np = of_find_node_by_name(rootnp, "GAISLER_IRQMP");
+        if (!np) {
+                np = of_find_node_by_name(rootnp, "01_00d");
+                if (!np)
+                        goto bad;
+        }
+        pp = of_find_property(np, "reg", &len);
+        if (!pp)
+                goto bad;
+        leon3_irqctrl_regs = *(struct leon3_irqctrl_regs_map **)pp->value;
+
+        /* Find GPTIMER Timer Registers base address otherwise bail out. */
+        nnp = rootnp;
+        do {
+                np = of_find_node_by_name(nnp, "GAISLER_GPTIMER");
+                if (!np) {
+                        np = of_find_node_by_name(nnp, "01_011");
+                        if (!np)
+                                goto bad;
+                }
+
+                ampopts = 0;
+                pp = of_find_property(np, "ampopts", &len);
+                if (pp) {
+                        ampopts = *(int *)pp->value;
+                        if (ampopts == 0) {
+                                /* Skip this instance, resource already
+                                 * allocated by other OS */
+                                nnp = np;
+                                continue;
+                        }
+                }
+
+                /* Select Timer-Instance on Timer Core. Default is zero */
+                leon3_gptimer_idx = ampopts & 0x7;
+
+                pp = of_find_property(np, "reg", &len);
+                if (pp)
+                        leon3_gptimer_regs = *(struct leon3_gptimer_regs_map **)
+                                                pp->value;
+                pp = of_find_property(np, "interrupts", &len);
+                if (pp)
+                        leon3_gptimer_irq = *(unsigned int *)pp->value;
+        } while (0);
+
+        if (leon3_gptimer_regs && leon3_irqctrl_regs && leon3_gptimer_irq) {
+                LEON3_BYPASS_STORE_PA(
+                        &leon3_gptimer_regs->e[leon3_gptimer_idx].val, 0);
+                LEON3_BYPASS_STORE_PA(
+                        &leon3_gptimer_regs->e[leon3_gptimer_idx].rld,
+                        (((1000000 / HZ) - 1)));
+                LEON3_BYPASS_STORE_PA(
+                        &leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, 0);
 
 #ifdef CONFIG_SMP
                 leon_percpu_timer_dev[0].start = (int)leon3_gptimer_regs;
-                leon_percpu_timer_dev[0].irq = leon3_gptimer_irq+1;
+                leon_percpu_timer_dev[0].irq = leon3_gptimer_irq + 1 +
+                                               leon3_gptimer_idx;
 
                 if (!(LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->config) &
                       (1<<LEON3_GPTIMER_SEPIRQ))) {
@@ -127,17 +186,33 @@ void __init leon_init_timers(irq_handler_t counter_fn)
                         BUG();
                 }
 
-                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[1].val, 0);
-                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[1].rld, (((1000000/HZ) - 1)));
-                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[1].ctrl, 0);
+                LEON3_BYPASS_STORE_PA(
+                        &leon3_gptimer_regs->e[leon3_gptimer_idx+1].val, 0);
+                LEON3_BYPASS_STORE_PA(
+                        &leon3_gptimer_regs->e[leon3_gptimer_idx+1].rld,
+                        (((1000000/HZ) - 1)));
+                LEON3_BYPASS_STORE_PA(
+                        &leon3_gptimer_regs->e[leon3_gptimer_idx+1].ctrl, 0);
 # endif
 
+                /*
+                 * The IRQ controller may (if implemented) consist of multiple
+                 * IRQ controllers, each mapped on a 4Kb boundary.
+                 * Each CPU may be routed to different IRQCTRLs, however
+                 * we assume that all CPUs (in SMP system) is routed to the
+                 * same IRQ Controller, and for non-SMP only one IRQCTRL is
+                 * accessed anyway.
+                 * In AMP systems, Linux must run on CPU0 for the time being.
+                 */
+                cpu = sparc_leon3_cpuid();
+                icsel = LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->icsel[cpu/8]);
+                icsel = (icsel >> ((7 - (cpu&0x7)) * 4)) & 0xf;
+                leon3_irqctrl_regs += icsel;
         } else {
-                printk(KERN_ERR "No Timer/irqctrl found\n");
-                BUG();
+                goto bad;
         }
 
-        irq = request_irq(leon3_gptimer_irq,
+        irq = request_irq(leon3_gptimer_irq+leon3_gptimer_idx,
                           counter_fn,
                           (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL);
 
@@ -169,13 +244,13 @@ void __init leon_init_timers(irq_handler_t counter_fn)
 # endif
 
         if (leon3_gptimer_regs) {
-                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].ctrl,
+                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl,
                                       LEON3_GPTIMER_EN |
                                       LEON3_GPTIMER_RL |
                                       LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN);
 
 #ifdef CONFIG_SMP
-                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[1].ctrl,
+                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx+1].ctrl,
                                       LEON3_GPTIMER_EN |
                                       LEON3_GPTIMER_RL |
                                       LEON3_GPTIMER_LD |
@@ -183,6 +258,11 @@ void __init leon_init_timers(irq_handler_t counter_fn)
 #endif
 
         }
+        return;
+bad:
+        printk(KERN_ERR "No Timer/irqctrl found\n");
+        BUG();
+        return;
 }
 
 void leon_clear_clock_irq(void)
diff --git a/arch/sparc/kernel/nmi.c b/arch/sparc/kernel/nmi.c
index a4bd7ba74c89..300f810142f5 100644
--- a/arch/sparc/kernel/nmi.c
+++ b/arch/sparc/kernel/nmi.c
@@ -270,8 +270,6 @@ int __init nmi_init(void)
                         atomic_set(&nmi_active, -1);
                 }
         }
-        if (!err)
-                init_hw_perf_events();
 
         return err;
 }
diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c
index b87873c0e8ea..ae96cf52a955 100644
--- a/arch/sparc/kernel/pcr.c
+++ b/arch/sparc/kernel/pcr.c
@@ -168,4 +168,4 @@ out_unregister:
         return err;
 }
 
-arch_initcall(pcr_arch_init);
+early_initcall(pcr_arch_init);
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 0d6deb55a2ae..760578687e7c 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1307,20 +1307,23 @@ static bool __init supported_pmu(void)
         return false;
 }
 
-void __init init_hw_perf_events(void)
+int __init init_hw_perf_events(void)
 {
         pr_info("Performance events: ");
 
         if (!supported_pmu()) {
                 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
-                return;
+                return 0;
         }
 
         pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
 
-        perf_pmu_register(&pmu);
+        perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
         register_die_notifier(&perf_event_nmi_notifier);
+
+        return 0;
 }
+early_initcall(init_hw_perf_events);
 
 void perf_callchain_kernel(struct perf_callchain_entry *entry,
                            struct pt_regs *regs)
diff --git a/arch/sparc/kernel/prom_32.c b/arch/sparc/kernel/prom_32.c
index 0a37e8cfd160..05fb25330583 100644
--- a/arch/sparc/kernel/prom_32.c
+++ b/arch/sparc/kernel/prom_32.c
@@ -136,18 +136,29 @@ static void __init ebus_path_component(struct device_node *dp, char *tmp_buf)
 /* "name:vendor:device@irq,addrlo" */
 static void __init ambapp_path_component(struct device_node *dp, char *tmp_buf)
 {
-        struct amba_prom_registers *regs; unsigned int *intr;
-        unsigned int *device, *vendor;
+        struct amba_prom_registers *regs;
+        unsigned int *intr, *device, *vendor, reg0;
         struct property *prop;
+        int interrupt = 0;
 
+        /* In order to get a unique ID in the device tree (multiple AMBA devices
+         * may have the same name) the node number is printed
+         */
         prop = of_find_property(dp, "reg", NULL);
-        if (!prop)
-                return;
-        regs = prop->value;
+        if (!prop) {
+                reg0 = (unsigned int)dp->phandle;
+        } else {
+                regs = prop->value;
+                reg0 = regs->phys_addr;
+        }
+
+        /* Not all cores have Interrupt */
         prop = of_find_property(dp, "interrupts", NULL);
         if (!prop)
-                return;
-        intr = prop->value;
+                intr = &interrupt; /* IRQ0 does not exist */
+        else
+                intr = prop->value;
+
         prop = of_find_property(dp, "vendor", NULL);
         if (!prop)
                 return;
@@ -159,7 +170,7 @@ static void __init ambapp_path_component(struct device_node *dp, char *tmp_buf)
 
         sprintf(tmp_buf, "%s:%d:%d@%x,%x",
                 dp->name, *vendor, *device,
-                *intr, regs->phys_addr);
+                *intr, reg0);
 }
 
 static void __init __build_path_component(struct device_node *dp, char *tmp_buf)
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index b22ce6100403..648f2161b851 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -185,7 +185,6 @@ static void __init boot_flags_init(char *commands)
 
 extern void sun4c_probe_vac(void);
 extern char cputypval;
-extern unsigned long start, end;
 
 extern unsigned short root_flags;
 extern unsigned short root_dev;
@@ -210,7 +209,7 @@ void __init setup_arch(char **cmdline_p)
         int i;
         unsigned long highest_paddr;
 
-        sparc_ttable = (struct tt_entry *) &start;
+        sparc_ttable = (struct tt_entry *) &trapbase;
 
         /* Initialize PROM console and command line. */
         *cmdline_p = prom_getbootargs();
diff --git a/arch/sparc/kernel/starfire.c b/arch/sparc/kernel/starfire.c
index a4446c0fb7a1..82281a566bb8 100644
--- a/arch/sparc/kernel/starfire.c
+++ b/arch/sparc/kernel/starfire.c
@@ -24,7 +24,7 @@ int this_is_starfire = 0;
 void check_if_starfire(void)
 {
         phandle ssnode = prom_finddevice("/ssp-serial");
-        if (ssnode != 0 && ssnode != -1)
+        if (ssnode != 0 && (s32)ssnode != -1)
                 this_is_starfire = 1;
 }
 
diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c
index ddd0d86e508e..b5137cc2aba3 100644
--- a/arch/sparc/mm/sun4c.c
+++ b/arch/sparc/mm/sun4c.c
@@ -435,16 +435,14 @@ void __init sun4c_probe_memerr_reg(void)
 
 static inline void sun4c_init_ss2_cache_bug(void)
 {
-        extern unsigned long start;
-
         if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS2)) ||
             (idprom->id_machtype == (SM_SUN4C | SM_4C_IPX)) ||
             (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC))) {
                 /* Whee.. */
                 printk("SS2 cache bug detected, uncaching trap table page\n");
-                sun4c_flush_page((unsigned int) &start);
-                sun4c_put_pte(((unsigned long) &start),
-                        (sun4c_get_pte((unsigned long) &start) | _SUN4C_PAGE_NOCACHE));
+                sun4c_flush_page((unsigned int) &_start);
+                sun4c_put_pte(((unsigned long) &_start),
+                        (sun4c_get_pte((unsigned long) &_start) | _SUN4C_PAGE_NOCACHE));
         }
 }
 
diff --git a/arch/sparc/prom/Makefile b/arch/sparc/prom/Makefile
index 816c0fa12dc0..8287bbe88768 100644
--- a/arch/sparc/prom/Makefile
+++ b/arch/sparc/prom/Makefile
@@ -5,12 +5,10 @@ asflags := -ansi
 ccflags := -Werror
 
 lib-y                 := bootstr_$(BITS).o
-lib-$(CONFIG_SPARC32) += devmap.o
 lib-y                 += init_$(BITS).o
 lib-$(CONFIG_SPARC32) += memory.o
 lib-y                 += misc_$(BITS).o
 lib-$(CONFIG_SPARC32) += mp.o
-lib-$(CONFIG_SPARC32) += palloc.o
 lib-$(CONFIG_SPARC32) += ranges.o
 lib-$(CONFIG_SPARC32) += segment.o
 lib-y                 += console_$(BITS).o
diff --git a/arch/sparc/prom/bootstr_32.c b/arch/sparc/prom/bootstr_32.c
index 916831da7e67..f5ec32e0d419 100644
--- a/arch/sparc/prom/bootstr_32.c
+++ b/arch/sparc/prom/bootstr_32.c
@@ -29,7 +29,8 @@ prom_getbootargs(void)
                 /* Start from 1 and go over fd(0,0,0)kernel */
                 for(iter = 1; iter < 8; iter++) {
                         arg = (*(romvec->pv_v0bootargs))->argv[iter];
-                        if(arg == 0) break;
+                        if (arg == NULL)
+                                break;
                         while(*arg != 0) {
                                 /* Leave place for space and null. */
                                 if(cp >= barg_buf + BARG_LEN-2){
diff --git a/arch/sparc/prom/console_32.c b/arch/sparc/prom/console_32.c
index 48863108a44c..b05e3db5fa63 100644
--- a/arch/sparc/prom/console_32.c
+++ b/arch/sparc/prom/console_32.c
@@ -27,13 +27,14 @@ static int prom_nbputchar(const char *buf)
         spin_lock_irqsave(&prom_lock, flags);
         switch(prom_vers) {
         case PROM_V0:
-                i = (*(romvec->pv_nbputchar))(*buf);
+                if ((*(romvec->pv_nbputchar))(*buf))
+                        i = 1;
                 break;
         case PROM_V2:
         case PROM_V3:
                 if ((*(romvec->pv_v2devops).v2_dev_write)(*romvec->pv_v2bootargs.fd_stdout,
                                                           buf, 0x1) == 1)
-                        i = 0;
+                        i = 1;
                 break;
         default:
                 break;
@@ -47,7 +48,7 @@ void prom_console_write_buf(const char *buf, int len)
 {
         while (len) {
                 int n = prom_nbputchar(buf);
-                if (n)
+                if (n < 0)
                         continue;
                 len--;
                 buf++;
diff --git a/arch/sparc/prom/console_64.c b/arch/sparc/prom/console_64.c
index ed39e75828bd..9de6c8cfe04a 100644
--- a/arch/sparc/prom/console_64.c
+++ b/arch/sparc/prom/console_64.c
@@ -13,8 +13,6 @@
 #include <asm/system.h>
 #include <linux/string.h>
 
-extern int prom_stdin, prom_stdout;
-
 static int __prom_console_write_buf(const char *buf, int len)
 {
         unsigned long args[7];
diff --git a/arch/sparc/prom/devmap.c b/arch/sparc/prom/devmap.c
deleted file mode 100644
index 46157d2aba0d..000000000000
--- a/arch/sparc/prom/devmap.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * promdevmap.c:  Map device/IO areas to virtual addresses.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-
-#include <asm/openprom.h>
-#include <asm/oplib.h>
-
-extern void restore_current(void);
-
-/* Just like the routines in palloc.c, these should not be used
- * by the kernel at all.  Bootloader facility mainly.  And again,
- * this is only available on V2 proms and above.
- */
-
-/* Map physical device address 'paddr' in IO space 'ios' of size
- * 'num_bytes' to a virtual address, with 'vhint' being a hint to
- * the prom as to where you would prefer the mapping.  We return
- * where the prom actually mapped it.
- */
-char *
-prom_mapio(char *vhint, int ios, unsigned int paddr, unsigned int num_bytes)
-{
-        unsigned long flags;
-        char *ret;
-
-        spin_lock_irqsave(&prom_lock, flags);
-        if((num_bytes == 0) || (paddr == 0)) ret = (char *) 0x0;
-        else
-        ret = (*(romvec->pv_v2devops.v2_dumb_mmap))(vhint, ios, paddr,
-                                                    num_bytes);
-        restore_current();
-        spin_unlock_irqrestore(&prom_lock, flags);
-        return ret;
-}
-
-/* Unmap an IO/device area that was mapped using the above routine. */
-void
-prom_unmapio(char *vaddr, unsigned int num_bytes)
-{
-        unsigned long flags;
-
-        if(num_bytes == 0x0) return;
-        spin_lock_irqsave(&prom_lock, flags);
-        (*(romvec->pv_v2devops.v2_dumb_munmap))(vaddr, num_bytes);
-        restore_current();
-        spin_unlock_irqrestore(&prom_lock, flags);
-}
diff --git a/arch/sparc/prom/init_32.c b/arch/sparc/prom/init_32.c
index d342dba4dd54..0a601b300639 100644
--- a/arch/sparc/prom/init_32.c
+++ b/arch/sparc/prom/init_32.c
@@ -60,7 +60,7 @@ void __init prom_init(struct linux_romvec *rp)
         prom_nodeops = romvec->pv_nodeops;
 
         prom_root_node = prom_getsibling(0);
-        if((prom_root_node == 0) || (prom_root_node == -1))
+        if ((prom_root_node == 0) || ((s32)prom_root_node == -1))
                 prom_halt();
 
         if((((unsigned long) prom_nodeops) == 0) || 
diff --git a/arch/sparc/prom/init_64.c b/arch/sparc/prom/init_64.c
index 3ff911e7d25b..5016c5e20575 100644
--- a/arch/sparc/prom/init_64.c
+++ b/arch/sparc/prom/init_64.c
@@ -18,7 +18,7 @@
 char prom_version[80];
 
 /* The root node of the prom device tree. */
-int prom_stdin, prom_stdout;
+int prom_stdout;
 phandle prom_chosen_node;
 
 /* You must call prom_init() before you attempt to use any of the
@@ -35,14 +35,13 @@ void __init prom_init(void *cif_handler, void *cif_stack)
         prom_cif_init(cif_handler, cif_stack);
 
         prom_chosen_node = prom_finddevice(prom_chosen_path);
-        if (!prom_chosen_node || prom_chosen_node == -1)
+        if (!prom_chosen_node || (s32)prom_chosen_node == -1)
                 prom_halt();
 
-        prom_stdin = prom_getint(prom_chosen_node, "stdin");
         prom_stdout = prom_getint(prom_chosen_node, "stdout");
 
         node = prom_finddevice("/openprom");
-        if (!node || node == -1)
+        if (!node || (s32)node == -1)
                 prom_halt();
 
         prom_getstring(node, "version", prom_version, sizeof(prom_version));
diff --git a/arch/sparc/prom/misc_32.c b/arch/sparc/prom/misc_32.c
index 4d61c540bb3d..8c278c311ba4 100644
--- a/arch/sparc/prom/misc_32.c
+++ b/arch/sparc/prom/misc_32.c
@@ -70,7 +70,7 @@ prom_cmdline(void)
 /* Drop into the prom, but completely terminate the program.
  * No chance of continuing.
  */
-void
+void __noreturn
 prom_halt(void)
 {
         unsigned long flags;
diff --git a/arch/sparc/prom/mp.c b/arch/sparc/prom/mp.c
index 4c4dc79f65af..97c44c9ddbc8 100644
--- a/arch/sparc/prom/mp.c
+++ b/arch/sparc/prom/mp.c
@@ -41,81 +41,3 @@ prom_startcpu(int cpunode, struct linux_prom_registers *ctable_reg, int ctx, cha
 
         return ret;
 }
-
-/* Stop CPU with device prom-tree node 'cpunode'.
- * XXX Again, what does the return value really mean? XXX
- */
-int
-prom_stopcpu(int cpunode)
-{
-        int ret;
-        unsigned long flags;
-
-        spin_lock_irqsave(&prom_lock, flags);
-        switch(prom_vers) {
-        case PROM_V0:
-        case PROM_V2:
-        default:
-                ret = -1;
-                break;
-        case PROM_V3:
-                ret = (*(romvec->v3_cpustop))(cpunode);
-                break;
-        };
-        restore_current();
-        spin_unlock_irqrestore(&prom_lock, flags);
-
-        return ret;
-}
-
-/* Make CPU with device prom-tree node 'cpunode' idle.
- * XXX Return value, anyone? XXX
- */
-int
-prom_idlecpu(int cpunode)
-{
-        int ret;
-        unsigned long flags;
-
-        spin_lock_irqsave(&prom_lock, flags);
-        switch(prom_vers) {
-        case PROM_V0:
-        case PROM_V2:
-        default:
-                ret = -1;
-                break;
-        case PROM_V3:
-                ret = (*(romvec->v3_cpuidle))(cpunode);
-                break;
-        };
-        restore_current();
-        spin_unlock_irqrestore(&prom_lock, flags);
-
-        return ret;
-}
-
-/* Resume the execution of CPU with nodeid 'cpunode'.
- * XXX Come on, somebody has to know... XXX
- */
-int
-prom_restartcpu(int cpunode)
-{
-        int ret;
-        unsigned long flags;
-
-        spin_lock_irqsave(&prom_lock, flags);
-        switch(prom_vers) {
-        case PROM_V0:
-        case PROM_V2:
-        default:
-                ret = -1;
-                break;
-        case PROM_V3:
-                ret = (*(romvec->v3_cpuresume))(cpunode);
-                break;
-        };
-        restore_current();
-        spin_unlock_irqrestore(&prom_lock, flags);
-
-        return ret;
-}
diff --git a/arch/sparc/prom/palloc.c b/arch/sparc/prom/palloc.c
deleted file mode 100644
index 2e2a88b211fb..000000000000
--- a/arch/sparc/prom/palloc.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * palloc.c:  Memory allocation from the Sun PROM.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-
-#include <asm/openprom.h>
-#include <asm/oplib.h>
-
-/* You should not call these routines after memory management
- * has been initialized in the kernel, if fact you should not
- * use these if at all possible in the kernel.  They are mainly
- * to be used for a bootloader for temporary allocations which
- * it will free before jumping into the kernel it has loaded.
- *
- * Also, these routines don't work on V0 proms, only V2 and later.
- */
-
-/* Allocate a chunk of memory of size 'num_bytes' giving a suggestion
- * of virtual_hint as the preferred virtual base address of this chunk.
- * There are no guarantees that you will get the allocation, or that
- * the prom will abide by your "hint".  So check your return value.
- */
-char *
-prom_alloc(char *virtual_hint, unsigned int num_bytes)
-{
-        if(prom_vers == PROM_V0) return (char *) 0x0;
-        if(num_bytes == 0x0) return (char *) 0x0;
-        return (*(romvec->pv_v2devops.v2_dumb_mem_alloc))(virtual_hint, num_bytes);
-}
-
-/* Free a previously allocated chunk back to the prom at virtual address
- * 'vaddr' of size 'num_bytes'.  NOTE: This vaddr is not the hint you
- * used for the allocation, but the virtual address the prom actually
- * returned to you.  They may be have been the same, they may have not,
- * doesn't matter.
- */
-void
-prom_free(char *vaddr, unsigned int num_bytes)
-{
-        if((prom_vers == PROM_V0) || (num_bytes == 0x0)) return;
-        (*(romvec->pv_v2devops.v2_dumb_mem_free))(vaddr, num_bytes);
-}
diff --git a/arch/sparc/prom/ranges.c b/arch/sparc/prom/ranges.c
index 541fc829c207..0857aa9e839d 100644
--- a/arch/sparc/prom/ranges.c
+++ b/arch/sparc/prom/ranges.c
@@ -13,8 +13,8 @@
 #include <asm/types.h>
 #include <asm/system.h>
 
-struct linux_prom_ranges promlib_obio_ranges[PROMREG_MAX];
-int num_obio_ranges;
+static struct linux_prom_ranges promlib_obio_ranges[PROMREG_MAX];
+static int num_obio_ranges;
 
 /* Adjust register values based upon the ranges parameters. */
 static void
@@ -35,7 +35,7 @@ prom_adjust_regs(struct linux_prom_registers *regp, int nregs,
         }
 }
 
-void
+static void
 prom_adjust_ranges(struct linux_prom_ranges *ranges1, int nranges1,
                    struct linux_prom_ranges *ranges2, int nranges2)
 {
diff --git a/arch/sparc/prom/tree_32.c b/arch/sparc/prom/tree_32.c
index 535e2e69ac1d..f30e8d038f01 100644
--- a/arch/sparc/prom/tree_32.c
+++ b/arch/sparc/prom/tree_32.c
@@ -20,7 +20,7 @@ extern void restore_current(void);
 static char promlib_buf[128];
 
 /* Internal version of prom_getchild that does not alter return values. */
-phandle __prom_getchild(phandle node)
+static phandle __prom_getchild(phandle node)
 {
         unsigned long flags;
         phandle cnode;
@@ -40,11 +40,11 @@ phandle prom_getchild(phandle node)
 {
         phandle cnode;
 
-        if (node == -1)
+        if ((s32)node == -1)
                 return 0;
 
         cnode = __prom_getchild(node);
-        if (cnode == 0 || cnode == -1)
+        if (cnode == 0 || (s32)cnode == -1)
                 return 0;
 
         return cnode;
@@ -52,7 +52,7 @@ phandle prom_getchild(phandle node)
 EXPORT_SYMBOL(prom_getchild);
 
 /* Internal version of prom_getsibling that does not alter return values. */
-phandle __prom_getsibling(phandle node)
+static phandle __prom_getsibling(phandle node)
 {
         unsigned long flags;
         phandle cnode;
@@ -72,11 +72,11 @@ phandle prom_getsibling(phandle node)
 {
         phandle sibnode;
 
-        if (node == -1)
+        if ((s32)node == -1)
                 return 0;
 
         sibnode = __prom_getsibling(node);
-        if (sibnode == 0 || sibnode == -1)
+        if (sibnode == 0 || (s32)sibnode == -1)
                 return 0;
 
         return sibnode;
@@ -177,20 +177,6 @@ void prom_getstring(phandle node, char *prop, char *user_buf, int ubuf_size)
 EXPORT_SYMBOL(prom_getstring);
 
 
-/* Does the device at node 'node' have name 'name'?
- * YES = 1   NO = 0
- */
-int prom_nodematch(phandle node, char *name)
-{
-        int error;
-
-        static char namebuf[128];
-        error = prom_getproperty(node, "name", namebuf, sizeof(namebuf));
-        if (error == -1) return 0;
-        if(strcmp(namebuf, name) == 0) return 1;
-        return 0;
-}
-
 /* Search siblings at 'node_start' for a node with name
  * 'nodename'.  Return node if successful, zero if not.
  */
@@ -214,7 +200,7 @@ phandle prom_searchsiblings(phandle node_start, char *nodename)
 EXPORT_SYMBOL(prom_searchsiblings);
 
 /* Interal version of nextprop that does not alter return values. */
-char *__prom_nextprop(phandle node, char * oprop)
+static char *__prom_nextprop(phandle node, char * oprop)
 {
         unsigned long flags;
         char *prop;
@@ -227,24 +213,13 @@ char *__prom_nextprop(phandle node, char * oprop)
         return prop;
 }
 
-/* Return the first property name for node 'node'. */
-/* buffer is unused argument, but as v9 uses it, we need to have the same interface */
-char *prom_firstprop(phandle node, char *bufer)
-{
-        if (node == 0 || node == -1)
-                return "";
-
-        return __prom_nextprop(node, "");
-}
-EXPORT_SYMBOL(prom_firstprop);
-
 /* Return the property type string after property type 'oprop'
  * at node 'node' .  Returns empty string if no more
  * property types for this node.
  */
 char *prom_nextprop(phandle node, char *oprop, char *buffer)
 {
-        if (node == 0 || node == -1)
+        if (node == 0 || (s32)node == -1)
                 return "";
 
         return __prom_nextprop(node, oprop);
@@ -278,7 +253,7 @@ phandle prom_finddevice(char *name)
                                 if (d != s + 3 && (!*d || *d == '/')
                                     && d <= s + 3 + 8) {
                                         node2 = node;
-                                        while (node2 && node2 != -1) {
+                                        while (node2 && (s32)node2 != -1) {
                                                 if (prom_getproperty (node2, "reg", (char *)reg, sizeof (reg)) > 0) {
                                                         if (which_io == reg[0].which_io && phys_addr == reg[0].phys_addr) {
                                                                 node = node2;
@@ -286,7 +261,7 @@ phandle prom_finddevice(char *name)
                                                         }
                                                 }
                                                 node2 = prom_getsibling(node2);
-                                                if (!node2 || node2 == -1)
+                                                if (!node2 || (s32)node2 == -1)
                                                         break;
                                                 node2 = prom_searchsiblings(prom_getsibling(node2), nbuf);
                                         }
@@ -299,19 +274,6 @@ phandle prom_finddevice(char *name)
 }
 EXPORT_SYMBOL(prom_finddevice);
 
-int prom_node_has_property(phandle node, char *prop)
-{
-        char *current_property = "";
-
-        do {
-                current_property = prom_nextprop(node, current_property, NULL);
-                if(!strcmp(current_property, prop))
-                   return 1;
-        } while (*current_property);
-        return 0;
-}
-EXPORT_SYMBOL(prom_node_has_property);
-
 /* Set property 'pname' at node 'node' to value 'value' which has a length
  * of 'size' bytes.  Return the number of bytes the prom accepted.
  */
@@ -320,8 +282,10 @@ int prom_setprop(phandle node, const char *pname, char *value, int size)
         unsigned long flags;
         int ret;
 
-        if(size == 0) return 0;
-        if((pname == 0) || (value == 0)) return 0;
+        if (size == 0)
+                return 0;
+        if ((pname == NULL) || (value == NULL))
+                return 0;
         spin_lock_irqsave(&prom_lock, flags);
         ret = prom_nodeops->no_setprop(node, pname, value, size);
         restore_current();
@@ -339,6 +303,7 @@ phandle prom_inst2pkg(int inst)
         node = (*romvec->pv_v2devops.v2_inst2pkg)(inst);
         restore_current();
         spin_unlock_irqrestore(&prom_lock, flags);
-        if (node == -1) return 0;
+        if ((s32)node == -1)
+                return 0;
         return node;
 }
diff --git a/arch/sparc/prom/tree_64.c b/arch/sparc/prom/tree_64.c
index d93660048376..92204c3800b5 100644
--- a/arch/sparc/prom/tree_64.c
+++ b/arch/sparc/prom/tree_64.c
@@ -43,10 +43,10 @@ inline phandle prom_getchild(phandle node)
 {
         phandle cnode;
 
-        if (node == -1)
+        if ((s32)node == -1)
                 return 0;
         cnode = __prom_getchild(node);
-        if (cnode == -1)
+        if ((s32)cnode == -1)
                 return 0;
         return cnode;
 }
@@ -56,10 +56,10 @@ inline phandle prom_getparent(phandle node)
 {
         phandle cnode;
 
-        if (node == -1)
+        if ((s32)node == -1)
                 return 0;
         cnode = prom_node_to_node("parent", node);
-        if (cnode == -1)
+        if ((s32)cnode == -1)
                 return 0;
         return cnode;
 }
@@ -76,10 +76,10 @@ inline phandle prom_getsibling(phandle node)
 {
         phandle sibnode;
 
-        if (node == -1)
+        if ((s32)node == -1)
                 return 0;
         sibnode = __prom_getsibling(node);
-        if (sibnode == -1)
+        if ((s32)sibnode == -1)
                 return 0;
 
         return sibnode;
@@ -240,7 +240,7 @@ inline char *prom_firstprop(phandle node, char *buffer)
         unsigned long args[7];
 
         *buffer = 0;
-        if (node == -1)
+        if ((s32)node == -1)
                 return buffer;
 
         args[0] = (unsigned long) prom_nextprop_name;
@@ -266,7 +266,7 @@ inline char *prom_nextprop(phandle node, const char *oprop, char *buffer)
         unsigned long args[7];
         char buf[32];
 
-        if (node == -1) {
+        if ((s32)node == -1) {
                 *buffer = 0;
                 return buffer;
         }
@@ -369,7 +369,7 @@ inline phandle prom_inst2pkg(int inst)
         p1275_cmd_direct(args);
 
         node = (int) args[4];
-        if (node == -1)
+        if ((s32)node == -1)
                 return 0;
         return node;
 }
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e330da21b84f..b6fccb07123e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -377,6 +377,18 @@ config X86_ELAN
 
           If unsure, choose "PC-compatible" instead.
 
+config X86_INTEL_CE
+        bool "CE4100 TV platform"
+        depends on PCI
+        depends on PCI_GODIRECT
+        depends on X86_32
+        depends on X86_EXTENDED_PLATFORM
+        select X86_REBOOTFIXUPS
+        ---help---
+          Select for the Intel CE media processor (CE4100) SOC.
+          This option compiles in support for the CE4100 SOC for settop
+          boxes and media devices.
+
 config X86_MRST
        bool "Moorestown MID platform"
         depends on PCI
@@ -385,6 +397,10 @@ config X86_MRST
         depends on X86_EXTENDED_PLATFORM
         depends on X86_IO_APIC
         select APB_TIMER
+        select I2C
+        select SPI
+        select INTEL_SCU_IPC
+        select X86_PLATFORM_DEVICES
         ---help---
           Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin
           Internet Device(MID) platform. Moorestown consists of two chips:
@@ -466,6 +482,19 @@ config X86_ES7000
           Support for Unisys ES7000 systems.  Say 'Y' here if this kernel is
           supposed to run on an IA32-based Unisys ES7000 system.
 
+config X86_32_IRIS
+        tristate "Eurobraille/Iris poweroff module"
+        depends on X86_32
+        ---help---
+          The Iris machines from EuroBraille do not have APM or ACPI support
+          to shut themselves down properly.  A special I/O sequence is
+          needed to do so, which is what this module does at
+          kernel shutdown.
+
+          This is only for Iris machines from EuroBraille.
+
+          If unused, say N.
+
 config SCHED_OMIT_FRAME_POINTER
         def_bool y
         prompt "Single-depth WCHAN output"
@@ -1141,16 +1170,16 @@ config NUMA
 comment "NUMA (Summit) requires SMP, 64GB highmem support, ACPI"
         depends on X86_32 && X86_SUMMIT && (!HIGHMEM64G || !ACPI)
 
-config K8_NUMA
+config AMD_NUMA
         def_bool y
         prompt "Old style AMD Opteron NUMA detection"
         depends on X86_64 && NUMA && PCI
         ---help---
-          Enable K8 NUMA node topology detection.  You should say Y here if
-          you have a multi processor AMD K8 system. This uses an old
-          method to read the NUMA configuration directly from the builtin
-          Northbridge of Opteron. It is recommended to use X86_64_ACPI_NUMA
-          instead, which also takes priority if both are compiled in.
+          Enable AMD NUMA node topology detection.  You should say Y here if
+          you have a multi processor AMD system. This uses an old method to
+          read the NUMA configuration directly from the builtin Northbridge
+          of Opteron. It is recommended to use X86_64_ACPI_NUMA instead,
+          which also takes priority if both are compiled in.
 
 config X86_64_ACPI_NUMA
         def_bool y
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 2ac9069890cd..15588a0ef466 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -310,6 +310,9 @@ config X86_INTERNODE_CACHE_SHIFT
 config X86_CMPXCHG
         def_bool X86_64 || (X86_32 && !M386)
 
+config CMPXCHG_LOCAL
+        def_bool X86_64 || (X86_32 && !M386)
+
 config X86_L1_CACHE_SHIFT
         int
         default "7" if MPENTIUM4 || MPSC
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index b59ee765414e..45143bbcfe5e 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -117,6 +117,17 @@ config DEBUG_RODATA_TEST
           feature as well as for the change_page_attr() infrastructure.
           If in doubt, say "N"
 
+config DEBUG_SET_MODULE_RONX
+        bool "Set loadable kernel module data as NX and text as RO"
+        depends on MODULES
+        ---help---
+          This option helps catch unintended modifications to loadable
+          kernel module's text and read-only data. It also prevents execution
+          of module data. Such protection may interfere with run-time code
+          patching and dynamic kernel tracing - and they might also protect
+          against certain classes of kernel exploits.
+          If in doubt, say "N".
+
 config DEBUG_NX_TEST
         tristate "Testcase for the NX non-executable stack feature"
         depends on DEBUG_KERNEL && m
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 52f85a196fa0..35af09d13dc1 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -182,7 +182,7 @@ no_longmode:
         hlt
         jmp     1b
 
-#include "../../kernel/verify_cpu_64.S"
+#include "../../kernel/verify_cpu.S"
 
         /*
          * Be careful here startup_64 needs to be at a predictable
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 55d106b5e31b..211ca3f7fd16 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -185,17 +185,16 @@ struct bootnode;
 
 #ifdef CONFIG_ACPI_NUMA
 extern int acpi_numa;
-extern int acpi_get_nodes(struct bootnode *physnodes);
+extern void acpi_get_nodes(struct bootnode *physnodes, unsigned long start,
+                                unsigned long end);
 extern int acpi_scan_nodes(unsigned long start, unsigned long end);
 #define NR_NODE_MEMBLKS (MAX_NUMNODES*2)
+
+#ifdef CONFIG_NUMA_EMU
 extern void acpi_fake_nodes(const struct bootnode *fake_nodes,
                                    int num_nodes);
-#else
-static inline void acpi_fake_nodes(const struct bootnode *fake_nodes,
-                                   int num_nodes)
-{
-}
 #endif
+#endif /* CONFIG_ACPI_NUMA */
 
 #define acpi_unlazy_tlb(x)      leave_mm(x)
 
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index 76561d20ea2f..13009d1af99a 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -66,6 +66,7 @@ extern void alternatives_smp_module_add(struct module *mod, char *name,
 extern void alternatives_smp_module_del(struct module *mod);
 extern void alternatives_smp_switch(int smp);
 extern int alternatives_text_reserved(void *start, void *end);
+extern bool skip_smp_alternatives;
 #else
 static inline void alternatives_smp_module_add(struct module *mod, char *name,
                                                void *locks, void *locks_end,
@@ -180,8 +181,15 @@ extern void *text_poke_early(void *addr, const void *opcode, size_t len);
  * On the local CPU you need to be protected again NMI or MCE handlers seeing an
  * inconsistent instruction while you patch.
  */
+struct text_poke_param {
+        void *addr;
+        const void *opcode;
+        size_t len;
+};
+
 extern void *text_poke(void *addr, const void *opcode, size_t len);
 extern void *text_poke_smp(void *addr, const void *opcode, size_t len);
+extern void text_poke_smp_batch(struct text_poke_param *params, int n);
 
 #if defined(CONFIG_DYNAMIC_FTRACE) || defined(HAVE_JUMP_LABEL)
 #define IDEAL_NOP_SIZE_5 5
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index c8517f81b21e..64dc82ee19f0 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -3,36 +3,64 @@
 
 #include <linux/pci.h>
 
-extern struct pci_device_id k8_nb_ids[];
+struct amd_nb_bus_dev_range {
+        u8 bus;
+        u8 dev_base;
+        u8 dev_limit;
+};
+
+extern struct pci_device_id amd_nb_misc_ids[];
+extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
 struct bootnode;
 
-extern int early_is_k8_nb(u32 value);
-extern int cache_k8_northbridges(void);
-extern void k8_flush_garts(void);
-extern int k8_get_nodes(struct bootnode *nodes);
-extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
-extern int k8_scan_nodes(void);
+extern int early_is_amd_nb(u32 value);
+extern int amd_cache_northbridges(void);
+extern void amd_flush_garts(void);
+extern int amd_numa_init(unsigned long start_pfn, unsigned long end_pfn);
+extern int amd_scan_nodes(void);
+
+#ifdef CONFIG_NUMA_EMU
+extern void amd_fake_nodes(const struct bootnode *nodes, int nr_nodes);
+extern void amd_get_nodes(struct bootnode *nodes);
+#endif
 
-struct k8_northbridge_info {
+struct amd_northbridge {
+        struct pci_dev *misc;
+};
+
+struct amd_northbridge_info {
         u16 num;
-        u8 gart_supported;
-        struct pci_dev **nb_misc;
+        u64 flags;
+        struct amd_northbridge *nb;
 };
-extern struct k8_northbridge_info k8_northbridges;
+extern struct amd_northbridge_info amd_northbridges;
+
+#define AMD_NB_GART                     0x1
+#define AMD_NB_L3_INDEX_DISABLE         0x2
 
 #ifdef CONFIG_AMD_NB
 
-static inline struct pci_dev *node_to_k8_nb_misc(int node)
+static inline int amd_nb_num(void)
 {
-        return (node < k8_northbridges.num) ? k8_northbridges.nb_misc[node] : NULL;
+        return amd_northbridges.num;
 }
 
-#else
+static inline int amd_nb_has_feature(int feature)
+{
+        return ((amd_northbridges.flags & feature) == feature);
+}
 
-static inline struct pci_dev *node_to_k8_nb_misc(int node)
+static inline struct amd_northbridge *node_to_amd_nb(int node)
 {
-        return NULL;
+        return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
 }
+
+#else
+
+#define amd_nb_num(x)           0
+#define amd_nb_has_feature(x)   false
+#define node_to_amd_nb(x)       NULL
+
 #endif
 
 
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index f6ce0bda3b98..5e3969c36d7f 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -234,16 +234,17 @@ extern void init_bsp_APIC(void);
 extern void setup_local_APIC(void);
 extern void end_local_APIC_setup(void);
 extern void init_apic_mappings(void);
+void register_lapic_address(unsigned long address);
 extern void setup_boot_APIC_clock(void);
 extern void setup_secondary_APIC_clock(void);
 extern int APIC_init_uniprocessor(void);
 extern void enable_NMI_through_LVT0(void);
+extern int apic_force_enable(void);
 
 /*
  * On 32bit this is mach-xxx local
  */
 #ifdef CONFIG_X86_64
-extern void early_init_lapic_mapping(void);
 extern int apic_is_clustered_box(void);
 #else
 static inline int apic_is_clustered_box(void)
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index a859ca461fb0..47a30ff8e517 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -145,6 +145,7 @@
 
 #ifdef CONFIG_X86_32
 # define MAX_IO_APICS 64
+# define MAX_LOCAL_APIC 256
 #else
 # define MAX_IO_APICS 128
 # define MAX_LOCAL_APIC 32768
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index 8e6218550e77..c8bfe63a06de 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -124,6 +124,7 @@ enum {
         X86_SUBARCH_LGUEST,
         X86_SUBARCH_XEN,
         X86_SUBARCH_MRST,
+        X86_SUBARCH_CE4100,
         X86_NR_SUBARCHS,
 };
 
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index b81002f23614..078ad0caefc6 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -94,7 +94,7 @@ static inline void hw_breakpoint_disable(void)
 
 static inline int hw_breakpoint_active(void)
 {
-        return __get_cpu_var(cpu_dr7) & DR_GLOBAL_ENABLE_MASK;
+        return __this_cpu_read(cpu_dr7) & DR_GLOBAL_ENABLE_MASK;
 }
 
 extern void aout_dump_debugregs(struct user *dump);
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 9479a037419f..4729b2b63117 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -116,7 +116,11 @@ enum fixed_addresses {
 #endif
         FIX_TEXT_POKE1, /* reserve 2 pages for text_poke() */
         FIX_TEXT_POKE0, /* first page is last, because allocation is backward */
+#ifdef  CONFIG_X86_MRST
+        FIX_LNW_VRTC,
+#endif
         __end_of_permanent_fixed_addresses,
+
         /*
          * 256 temporary boot-time mappings, used by early_ioremap(),
          * before ioremap() is functional.
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 49dbfdfa50f9..91d915a65259 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -38,12 +38,9 @@ static inline int gpio_cansleep(unsigned int gpio)
         return __gpio_cansleep(gpio);
 }
 
-/*
- * Not implemented, yet.
- */
 static inline int gpio_to_irq(unsigned int gpio)
 {
-        return -ENOSYS;
+        return __gpio_to_irq(gpio);
 }
 
 static inline int irq_to_gpio(unsigned int irq)
diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h
index ff2546ce7178..7a15153c675d 100644
--- a/arch/x86/include/asm/hypervisor.h
+++ b/arch/x86/include/asm/hypervisor.h
@@ -20,6 +20,9 @@
 #ifndef _ASM_X86_HYPERVISOR_H
 #define _ASM_X86_HYPERVISOR_H
 
+#include <asm/kvm_para.h>
+#include <asm/xen/hypervisor.h>
+
 extern void init_hypervisor(struct cpuinfo_x86 *c);
 extern void init_hypervisor_platform(void);
 
@@ -47,4 +50,13 @@ extern const struct hypervisor_x86 x86_hyper_vmware;
 extern const struct hypervisor_x86 x86_hyper_ms_hyperv;
 extern const struct hypervisor_x86 x86_hyper_xen_hvm;
 
+static inline bool hypervisor_x2apic_available(void)
+{
+        if (kvm_para_available())
+                return true;
+        if (xen_x2apic_para_available())
+                return true;
+        return false;
+}
+
 #endif
diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h
index 4aa2bb3b242a..ef328901c802 100644
--- a/arch/x86/include/asm/i387.h
+++ b/arch/x86/include/asm/i387.h
@@ -93,6 +93,17 @@ static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
         int err;
 
         /* See comment in fxsave() below. */
+#ifdef CONFIG_AS_FXSAVEQ
+        asm volatile("1:  fxrstorq %[fx]\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err)
+                     : [fx] "m" (*fx), "0" (0));
+#else
         asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
                      "2:\n"
                      ".section .fixup,\"ax\"\n"
@@ -102,6 +113,7 @@ static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
                      _ASM_EXTABLE(1b, 3b)
                      : [err] "=r" (err)
                      : [fx] "R" (fx), "m" (*fx), "0" (0));
+#endif
         return err;
 }
 
@@ -119,6 +131,17 @@ static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
                 return -EFAULT;
 
         /* See comment in fxsave() below. */
+#ifdef CONFIG_AS_FXSAVEQ
+        asm volatile("1:  fxsaveq %[fx]\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err), [fx] "=m" (*fx)
+                     : "0" (0));
+#else
         asm volatile("1:  rex64/fxsave (%[fx])\n\t"
                      "2:\n"
                      ".section .fixup,\"ax\"\n"
@@ -128,6 +151,7 @@ static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
                      _ASM_EXTABLE(1b, 3b)
                      : [err] "=r" (err), "=m" (*fx)
                      : [fx] "R" (fx), "0" (0));
+#endif
         if (unlikely(err) &&
             __clear_user(fx, sizeof(struct i387_fxsave_struct)))
                 err = -EFAULT;
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index a6b28d017c2f..f327d386d6cc 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -159,7 +159,7 @@ struct io_apic_irq_attr;
 extern int io_apic_set_pci_routing(struct device *dev, int irq,
                  struct io_apic_irq_attr *irq_attr);
 void setup_IO_APIC_irq_extra(u32 gsi);
-extern void ioapic_init_mappings(void);
+extern void ioapic_and_gsi_init(void);
 extern void ioapic_insert_resources(void);
 
 extern struct IO_APIC_route_entry **alloc_ioapic_entries(void);
@@ -168,10 +168,10 @@ extern int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
 extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
 extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
 
-extern void probe_nr_irqs_gsi(void);
 extern int get_nr_irqs_gsi(void);
 
 extern void setup_ioapic_ids_from_mpc(void);
+extern void setup_ioapic_ids_from_mpc_nocheck(void);
 
 struct mp_ioapic_gsi{
         u32 gsi_base;
@@ -184,14 +184,15 @@ int mp_find_ioapic_pin(int ioapic, u32 gsi);
 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base);
 extern void __init pre_init_apic_IRQ0(void);
 
+extern void mp_save_irq(struct mpc_intsrc *m);
+
 #else  /* !CONFIG_X86_IO_APIC */
 
 #define io_apic_assign_pci_irqs 0
 #define setup_ioapic_ids_from_mpc x86_init_noop
 static const int timer_through_8259 = 0;
-static inline void ioapic_init_mappings(void)   { }
+static inline void ioapic_and_gsi_init(void) { }
 static inline void ioapic_insert_resources(void) { }
-static inline void probe_nr_irqs_gsi(void)      { }
 #define gsi_top (NR_IRQS_LEGACY)
 static inline int mp_find_ioapic(u32 gsi) { return 0; }
 
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 13b0ebaa512f..ba870bb6dd8e 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -15,10 +15,6 @@ static inline int irq_canonicalize(int irq)
         return ((irq == 2) ? 9 : irq);
 }
 
-#ifdef CONFIG_X86_LOCAL_APIC
-# define ARCH_HAS_NMI_WATCHDOG
-#endif
-
 #ifdef CONFIG_X86_32
 extern void irq_ctx_init(int cpu);
 #else
diff --git a/arch/x86/include/asm/kdebug.h b/arch/x86/include/asm/kdebug.h
index 5bdfca86581b..ca242d35e873 100644
--- a/arch/x86/include/asm/kdebug.h
+++ b/arch/x86/include/asm/kdebug.h
@@ -18,7 +18,6 @@ enum die_val {
         DIE_TRAP,
         DIE_GPF,
         DIE_CALL,
-        DIE_NMI_IPI,
         DIE_PAGE_FAULT,
         DIE_NMIUNKNOWN,
 };
@@ -28,7 +27,7 @@ extern void die(const char *, struct pt_regs *,long);
 extern int __must_check __die(const char *, struct pt_regs *, long);
 extern void show_registers(struct pt_regs *regs);
 extern void show_trace(struct task_struct *t, struct pt_regs *regs,
-                       unsigned long *sp, unsigned long bp);
+                       unsigned long *sp);
 extern void __show_regs(struct pt_regs *regs, int all);
 extern void show_regs(struct pt_regs *regs);
 extern unsigned long oops_begin(void);
diff --git a/arch/x86/include/asm/mach_traps.h b/arch/x86/include/asm/mach_traps.h
index f7920601e472..72a8b52e7dfd 100644
--- a/arch/x86/include/asm/mach_traps.h
+++ b/arch/x86/include/asm/mach_traps.h
@@ -7,9 +7,19 @@
 
 #include <asm/mc146818rtc.h>
 
+#define NMI_REASON_PORT         0x61
+
+#define NMI_REASON_SERR         0x80
+#define NMI_REASON_IOCHK        0x40
+#define NMI_REASON_MASK         (NMI_REASON_SERR | NMI_REASON_IOCHK)
+
+#define NMI_REASON_CLEAR_SERR   0x04
+#define NMI_REASON_CLEAR_IOCHK  0x08
+#define NMI_REASON_CLEAR_MASK   0x0f
+
 static inline unsigned char get_nmi_reason(void)
 {
-        return inb(0x61);
+        return inb(NMI_REASON_PORT);
 }
 
 static inline void reassert_nmi(void)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index c62c13cb9788..eb16e94ae04f 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -223,6 +223,9 @@ void intel_init_thermal(struct cpuinfo_x86 *c);
 
 void mce_log_therm_throt_event(__u64 status);
 
+/* Interrupt Handler for core thermal thresholds */
+extern int (*platform_thermal_notify)(__u64 msr_val);
+
 #ifdef CONFIG_X86_THERMAL_VECTOR
 extern void mcheck_intel_therm_init(void);
 #else
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index ef51b501e22a..24215072d0e1 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -48,6 +48,12 @@ static inline struct microcode_ops * __init init_intel_microcode(void)
 
 #ifdef CONFIG_MICROCODE_AMD
 extern struct microcode_ops * __init init_amd_microcode(void);
+
+static inline void get_ucode_data(void *to, const u8 *from, size_t n)
+{
+        memcpy(to, from, n);
+}
+
 #else
 static inline struct microcode_ops * __init init_amd_microcode(void)
 {
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
index c82868e9f905..0c90dd9f0505 100644
--- a/arch/x86/include/asm/mpspec.h
+++ b/arch/x86/include/asm/mpspec.h
@@ -5,8 +5,9 @@
 
 #include <asm/mpspec_def.h>
 #include <asm/x86_init.h>
+#include <asm/apicdef.h>
 
-extern int apic_version[MAX_APICS];
+extern int apic_version[];
 extern int pic_mode;
 
 #ifdef CONFIG_X86_32
@@ -107,7 +108,7 @@ extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level,
                                  int active_high_low);
 #endif /* CONFIG_ACPI */
 
-#define PHYSID_ARRAY_SIZE       BITS_TO_LONGS(MAX_APICS)
+#define PHYSID_ARRAY_SIZE       BITS_TO_LONGS(MAX_LOCAL_APIC)
 
 struct physid_mask {
         unsigned long mask[PHYSID_ARRAY_SIZE];
@@ -122,31 +123,31 @@ typedef struct physid_mask physid_mask_t;
         test_and_set_bit(physid, (map).mask)
 
 #define physids_and(dst, src1, src2)                                    \
-        bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
+        bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
 
 #define physids_or(dst, src1, src2)                                     \
-        bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
+        bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
 
 #define physids_clear(map)                                      \
-        bitmap_zero((map).mask, MAX_APICS)
+        bitmap_zero((map).mask, MAX_LOCAL_APIC)
 
 #define physids_complement(dst, src)                            \
-        bitmap_complement((dst).mask, (src).mask, MAX_APICS)
+        bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC)
 
 #define physids_empty(map)                                      \
-        bitmap_empty((map).mask, MAX_APICS)
+        bitmap_empty((map).mask, MAX_LOCAL_APIC)
 
 #define physids_equal(map1, map2)                               \
-        bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
+        bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC)
 
 #define physids_weight(map)                                     \
-        bitmap_weight((map).mask, MAX_APICS)
+        bitmap_weight((map).mask, MAX_LOCAL_APIC)
 
 #define physids_shift_right(d, s, n)                            \
-        bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
+        bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC)
 
 #define physids_shift_left(d, s, n)                             \
-        bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
+        bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC)
 
 static inline unsigned long physids_coerce(physid_mask_t *map)
 {
@@ -159,14 +160,6 @@ static inline void physids_promote(unsigned long physids, physid_mask_t *map)
         map->mask[0] = physids;
 }
 
-/* Note: will create very large stack frames if physid_mask_t is big */
-#define physid_mask_of_physid(physid)                                   \
-        ({                                                              \
-                physid_mask_t __physid_mask = PHYSID_MASK_NONE;         \
-                physid_set(physid, __physid_mask);                      \
-                __physid_mask;                                          \
-        })
-
 static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
 {
         physids_clear(*map);
diff --git a/arch/x86/include/asm/mpspec_def.h b/arch/x86/include/asm/mpspec_def.h
index 4a7f96d7c188..c0a955a9a087 100644
--- a/arch/x86/include/asm/mpspec_def.h
+++ b/arch/x86/include/asm/mpspec_def.h
@@ -15,13 +15,6 @@
 
 #ifdef CONFIG_X86_32
 # define MAX_MPC_ENTRY 1024
-# define MAX_APICS      256
-#else
-# if NR_CPUS <= 255
-#  define MAX_APICS     255
-# else
-#  define MAX_APICS   32768
-# endif
 #endif
 
 /* Intel MP Floating Pointer Structure */
diff --git a/arch/x86/include/asm/mrst-vrtc.h b/arch/x86/include/asm/mrst-vrtc.h
new file mode 100644
index 000000000000..73668abdbedf
--- /dev/null
+++ b/arch/x86/include/asm/mrst-vrtc.h
@@ -0,0 +1,9 @@
+#ifndef _MRST_VRTC_H
+#define _MRST_VRTC_H
+
+extern unsigned char vrtc_cmos_read(unsigned char reg);
+extern void vrtc_cmos_write(unsigned char val, unsigned char reg);
+extern unsigned long vrtc_get_time(void);
+extern int vrtc_set_mmss(unsigned long nowtime);
+
+#endif
diff --git a/arch/x86/include/asm/mrst.h b/arch/x86/include/asm/mrst.h
index 4a711a684b17..719f00b28ff5 100644
--- a/arch/x86/include/asm/mrst.h
+++ b/arch/x86/include/asm/mrst.h
@@ -14,7 +14,9 @@
 #include <linux/sfi.h>
 
 extern int pci_mrst_init(void);
-int __init sfi_parse_mrtc(struct sfi_table_header *table);
+extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
+extern int sfi_mrtc_num;
+extern struct sfi_rtc_table_entry sfi_mrtc_array[];
 
 /*
  * Medfield is the follow-up of Moorestown, it combines two chip solution into
@@ -50,4 +52,14 @@ extern void mrst_early_console_init(void);
 
 extern struct console early_hsu_console;
 extern void hsu_early_console_init(void);
+
+extern void intel_scu_devices_create(void);
+extern void intel_scu_devices_destroy(void);
+
+/* VRTC timer */
+#define MRST_VRTC_MAP_SZ        (1024)
+/*#define MRST_VRTC_PGOFFSET    (0xc00) */
+
+extern void mrst_rtc_init(void);
+
 #endif /* _ASM_X86_MRST_H */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6b89f5e86021..4d0dfa0d998e 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -123,6 +123,10 @@
 #define MSR_AMD64_IBSCTL                0xc001103a
 #define MSR_AMD64_IBSBRTARGET           0xc001103b
 
+/* Fam 15h MSRs */
+#define MSR_F15H_PERF_CTL               0xc0010200
+#define MSR_F15H_PERF_CTR               0xc0010201
+
 /* Fam 10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE       0xc0010058
 #define FAM10H_MMIO_CONF_ENABLE         (1<<0)
@@ -253,6 +257,18 @@
 #define PACKAGE_THERM_INT_LOW_ENABLE            (1 << 1)
 #define PACKAGE_THERM_INT_PLN_ENABLE            (1 << 24)
 
+/* Thermal Thresholds Support */
+#define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
+#define THERM_SHIFT_THRESHOLD0        8
+#define THERM_MASK_THRESHOLD0          (0x7f << THERM_SHIFT_THRESHOLD0)
+#define THERM_INT_THRESHOLD1_ENABLE    (1 << 23)
+#define THERM_SHIFT_THRESHOLD1        16
+#define THERM_MASK_THRESHOLD1          (0x7f << THERM_SHIFT_THRESHOLD1)
+#define THERM_STATUS_THRESHOLD0        (1 << 6)
+#define THERM_LOG_THRESHOLD0           (1 << 7)
+#define THERM_STATUS_THRESHOLD1        (1 << 8)
+#define THERM_LOG_THRESHOLD1           (1 << 9)
+
 /* MISC_ENABLE bits: architectural */
 #define MSR_IA32_MISC_ENABLE_FAST_STRING        (1ULL << 0)
 #define MSR_IA32_MISC_ENABLE_TCC                (1ULL << 1)
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index 932f0f86b4b7..c76f5b92b840 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -5,41 +5,15 @@
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#ifdef ARCH_HAS_NMI_WATCHDOG
-
-/**
- * do_nmi_callback
- *
- * Check to see if a callback exists and execute it.  Return 1
- * if the handler exists and was handled successfully.
- */
-int do_nmi_callback(struct pt_regs *regs, int cpu);
+#ifdef CONFIG_X86_LOCAL_APIC
 
 extern void die_nmi(char *str, struct pt_regs *regs, int do_panic);
-extern int check_nmi_watchdog(void);
-#if !defined(CONFIG_LOCKUP_DETECTOR)
-extern int nmi_watchdog_enabled;
-#endif
 extern int avail_to_resrv_perfctr_nmi_bit(unsigned int);
 extern int reserve_perfctr_nmi(unsigned int);
 extern void release_perfctr_nmi(unsigned int);
 extern int reserve_evntsel_nmi(unsigned int);
 extern void release_evntsel_nmi(unsigned int);
 
-extern void setup_apic_nmi_watchdog(void *);
-extern void stop_apic_nmi_watchdog(void *);
-extern void disable_timer_nmi_watchdog(void);
-extern void enable_timer_nmi_watchdog(void);
-extern int nmi_watchdog_tick(struct pt_regs *regs, unsigned reason);
-extern void cpu_nmi_set_wd_enabled(void);
-
-extern atomic_t nmi_active;
-extern unsigned int nmi_watchdog;
-#define NMI_NONE        0
-#define NMI_IO_APIC     1
-#define NMI_LOCAL_APIC  2
-#define NMI_INVALID     3
-
 struct ctl_table;
 extern int proc_nmi_enabled(struct ctl_table *, int ,
                         void __user *, size_t *, loff_t *);
@@ -47,33 +21,28 @@ extern int unknown_nmi_panic;
 
 void arch_trigger_all_cpu_backtrace(void);
 #define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
+#endif
 
-static inline void localise_nmi_watchdog(void)
-{
-        if (nmi_watchdog == NMI_IO_APIC)
-                nmi_watchdog = NMI_LOCAL_APIC;
-}
+/*
+ * Define some priorities for the nmi notifier call chain.
+ *
+ * Create a local nmi bit that has a higher priority than
+ * external nmis, because the local ones are more frequent.
+ *
+ * Also setup some default high/normal/low settings for
+ * subsystems to registers with.  Using 4 bits to seperate
+ * the priorities.  This can go alot higher if needed be.
+ */
 
-/* check if nmi_watchdog is active (ie was specified at boot) */
-static inline int nmi_watchdog_active(void)
-{
-        /*
-         * actually it should be:
-         *      return (nmi_watchdog == NMI_LOCAL_APIC ||
-         *              nmi_watchdog == NMI_IO_APIC)
-         * but since they are power of two we could use a
-         * cheaper way --cvg
-         */
-        return nmi_watchdog & (NMI_LOCAL_APIC | NMI_IO_APIC);
-}
-#endif
+#define NMI_LOCAL_SHIFT         16      /* randomly picked */
+#define NMI_LOCAL_BIT           (1ULL << NMI_LOCAL_SHIFT)
+#define NMI_HIGH_PRIOR          (1ULL << 8)
+#define NMI_NORMAL_PRIOR        (1ULL << 4)
+#define NMI_LOW_PRIOR           (1ULL << 0)
+#define NMI_LOCAL_HIGH_PRIOR    (NMI_LOCAL_BIT | NMI_HIGH_PRIOR)
+#define NMI_LOCAL_NORMAL_PRIOR  (NMI_LOCAL_BIT | NMI_NORMAL_PRIOR)
+#define NMI_LOCAL_LOW_PRIOR     (NMI_LOCAL_BIT | NMI_LOW_PRIOR)
 
-void lapic_watchdog_stop(void);
-int lapic_watchdog_init(unsigned nmi_hz);
-int lapic_wd_event(unsigned nmi_hz);
-unsigned lapic_adjust_nmi_hz(unsigned hz);
-void disable_lapic_nmi_watchdog(void);
-void enable_lapic_nmi_watchdog(void);
 void stop_nmi(void);
 void restart_nmi(void);
 
diff --git a/arch/x86/include/asm/numa_64.h b/arch/x86/include/asm/numa_64.h
index 823e070e7c26..5ae87285a502 100644
--- a/arch/x86/include/asm/numa_64.h
+++ b/arch/x86/include/asm/numa_64.h
@@ -38,7 +38,7 @@ extern void __cpuinit numa_add_cpu(int cpu);
 extern void __cpuinit numa_remove_cpu(int cpu);
 
 #ifdef CONFIG_NUMA_EMU
-#define FAKE_NODE_MIN_SIZE      ((u64)64 << 20)
+#define FAKE_NODE_MIN_SIZE      ((u64)32 << 20)
 #define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL))
 #endif /* CONFIG_NUMA_EMU */
 #else
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index ef9975812c77..7709c12431b8 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -112,7 +112,7 @@ static inline void arch_safe_halt(void)
 
 static inline void halt(void)
 {
-        PVOP_VCALL0(pv_irq_ops.safe_halt);
+        PVOP_VCALL0(pv_irq_ops.halt);
 }
 
 static inline void wbinvd(void)
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index ca0437c714b2..676129229630 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -65,6 +65,7 @@ extern unsigned long pci_mem_start;
 
 #define PCIBIOS_MIN_CARDBUS_IO  0x4000
 
+extern int pcibios_enabled;
 void pcibios_config_init(void);
 struct pci_bus *pcibios_scan_root(int bus);
 
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index f899e01a8ac9..8ee45167e817 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -230,6 +230,125 @@ do {									\
 })
 
 /*
+ * Add return operation
+ */
+#define percpu_add_return_op(var, val)                                  \
+({                                                                      \
+        typeof(var) paro_ret__ = val;                                   \
+        switch (sizeof(var)) {                                          \
+        case 1:                                                         \
+                asm("xaddb %0, "__percpu_arg(1)                         \
+                            : "+q" (paro_ret__), "+m" (var)             \
+                            : : "memory");                              \
+                break;                                                  \
+        case 2:                                                         \
+                asm("xaddw %0, "__percpu_arg(1)                         \
+                            : "+r" (paro_ret__), "+m" (var)             \
+                            : : "memory");                              \
+                break;                                                  \
+        case 4:                                                         \
+                asm("xaddl %0, "__percpu_arg(1)                         \
+                            : "+r" (paro_ret__), "+m" (var)             \
+                            : : "memory");                              \
+                break;                                                  \
+        case 8:                                                         \
+                asm("xaddq %0, "__percpu_arg(1)                         \
+                            : "+re" (paro_ret__), "+m" (var)            \
+                            : : "memory");                              \
+                break;                                                  \
+        default: __bad_percpu_size();                                   \
+        }                                                               \
+        paro_ret__ += val;                                              \
+        paro_ret__;                                                     \
+})
+
+/*
+ * xchg is implemented using cmpxchg without a lock prefix. xchg is
+ * expensive due to the implied lock prefix.  The processor cannot prefetch
+ * cachelines if xchg is used.
+ */
+#define percpu_xchg_op(var, nval)                                       \
+({                                                                      \
+        typeof(var) pxo_ret__;                                          \
+        typeof(var) pxo_new__ = (nval);                                 \
+        switch (sizeof(var)) {                                          \
+        case 1:                                                         \
+                asm("\n1:mov "__percpu_arg(1)",%%al"                    \
+                    "\n\tcmpxchgb %2, "__percpu_arg(1)                  \
+                    "\n\tjnz 1b"                                        \
+                            : "=a" (pxo_ret__), "+m" (var)              \
+                            : "q" (pxo_new__)                           \
+                            : "memory");                                \
+                break;                                                  \
+        case 2:                                                         \
+                asm("\n1:mov "__percpu_arg(1)",%%ax"                    \
+                    "\n\tcmpxchgw %2, "__percpu_arg(1)                  \
+                    "\n\tjnz 1b"                                        \
+                            : "=a" (pxo_ret__), "+m" (var)              \
+                            : "r" (pxo_new__)                           \
+                            : "memory");                                \
+                break;                                                  \
+        case 4:                                                         \
+                asm("\n1:mov "__percpu_arg(1)",%%eax"                   \
+                    "\n\tcmpxchgl %2, "__percpu_arg(1)                  \
+                    "\n\tjnz 1b"                                        \
+                            : "=a" (pxo_ret__), "+m" (var)              \
+                            : "r" (pxo_new__)                           \
+                            : "memory");                                \
+                break;                                                  \
+        case 8:                                                         \
+                asm("\n1:mov "__percpu_arg(1)",%%rax"                   \
+                    "\n\tcmpxchgq %2, "__percpu_arg(1)                  \
+                    "\n\tjnz 1b"                                        \
+                            : "=a" (pxo_ret__), "+m" (var)              \
+                            : "r" (pxo_new__)                           \
+                            : "memory");                                \
+                break;                                                  \
+        default: __bad_percpu_size();                                   \
+        }                                                               \
+        pxo_ret__;                                                      \
+})
+
+/*
+ * cmpxchg has no such implied lock semantics as a result it is much
+ * more efficient for cpu local operations.
+ */
+#define percpu_cmpxchg_op(var, oval, nval)                              \
+({                                                                      \
+        typeof(var) pco_ret__;                                          \
+        typeof(var) pco_old__ = (oval);                                 \
+        typeof(var) pco_new__ = (nval);                                 \
+        switch (sizeof(var)) {                                          \
+        case 1:                                                         \
+                asm("cmpxchgb %2, "__percpu_arg(1)                      \
+                            : "=a" (pco_ret__), "+m" (var)              \
+                            : "q" (pco_new__), "0" (pco_old__)          \
+                            : "memory");                                \
+                break;                                                  \
+        case 2:                                                         \
+                asm("cmpxchgw %2, "__percpu_arg(1)                      \
+                            : "=a" (pco_ret__), "+m" (var)              \
+                            : "r" (pco_new__), "0" (pco_old__)          \
+                            : "memory");                                \
+                break;                                                  \
+        case 4:                                                         \
+                asm("cmpxchgl %2, "__percpu_arg(1)                      \
+                            : "=a" (pco_ret__), "+m" (var)              \
+                            : "r" (pco_new__), "0" (pco_old__)          \
+                            : "memory");                                \
+                break;                                                  \
+        case 8:                                                         \
+                asm("cmpxchgq %2, "__percpu_arg(1)                      \
+                            : "=a" (pco_ret__), "+m" (var)              \
+                            : "r" (pco_new__), "0" (pco_old__)          \
+                            : "memory");                                \
+                break;                                                  \
+        default: __bad_percpu_size();                                   \
+        }                                                               \
+        pco_ret__;                                                      \
+})
+
+/*
  * percpu_read() makes gcc load the percpu variable every time it is
  * accessed while percpu_read_stable() allows the value to be cached.
  * percpu_read_stable() is more efficient and can be used if its value
@@ -267,6 +386,12 @@ do {									\
 #define __this_cpu_xor_1(pcp, val)      percpu_to_op("xor", (pcp), val)
 #define __this_cpu_xor_2(pcp, val)      percpu_to_op("xor", (pcp), val)
 #define __this_cpu_xor_4(pcp, val)      percpu_to_op("xor", (pcp), val)
+/*
+ * Generic fallback operations for __this_cpu_xchg_[1-4] are okay and much
+ * faster than an xchg with forced lock semantics.
+ */
+#define __this_cpu_xchg_8(pcp, nval)    percpu_xchg_op(pcp, nval)
+#define __this_cpu_cmpxchg_8(pcp, oval, nval)   percpu_cmpxchg_op(pcp, oval, nval)
 
 #define this_cpu_read_1(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
 #define this_cpu_read_2(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
@@ -286,6 +411,11 @@ do {									\
 #define this_cpu_xor_1(pcp, val)        percpu_to_op("xor", (pcp), val)
 #define this_cpu_xor_2(pcp, val)        percpu_to_op("xor", (pcp), val)
 #define this_cpu_xor_4(pcp, val)        percpu_to_op("xor", (pcp), val)
+#define this_cpu_xchg_1(pcp, nval)      percpu_xchg_op(pcp, nval)
+#define this_cpu_xchg_2(pcp, nval)      percpu_xchg_op(pcp, nval)
+#define this_cpu_xchg_4(pcp, nval)      percpu_xchg_op(pcp, nval)
+#define this_cpu_xchg_8(pcp, nval)      percpu_xchg_op(pcp, nval)
+#define this_cpu_cmpxchg_8(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
 
 #define irqsafe_cpu_add_1(pcp, val)     percpu_add_op((pcp), val)
 #define irqsafe_cpu_add_2(pcp, val)     percpu_add_op((pcp), val)
@@ -299,6 +429,31 @@ do {									\
 #define irqsafe_cpu_xor_1(pcp, val)     percpu_to_op("xor", (pcp), val)
 #define irqsafe_cpu_xor_2(pcp, val)     percpu_to_op("xor", (pcp), val)
 #define irqsafe_cpu_xor_4(pcp, val)     percpu_to_op("xor", (pcp), val)
+#define irqsafe_cpu_xchg_1(pcp, nval)   percpu_xchg_op(pcp, nval)
+#define irqsafe_cpu_xchg_2(pcp, nval)   percpu_xchg_op(pcp, nval)
+#define irqsafe_cpu_xchg_4(pcp, nval)   percpu_xchg_op(pcp, nval)
+#define irqsafe_cpu_xchg_8(pcp, nval)   percpu_xchg_op(pcp, nval)
+#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
+
+#ifndef CONFIG_M386
+#define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
+#define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
+#define __this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
+#define __this_cpu_cmpxchg_1(pcp, oval, nval)   percpu_cmpxchg_op(pcp, oval, nval)
+#define __this_cpu_cmpxchg_2(pcp, oval, nval)   percpu_cmpxchg_op(pcp, oval, nval)
+#define __this_cpu_cmpxchg_4(pcp, oval, nval)   percpu_cmpxchg_op(pcp, oval, nval)
+
+#define this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
+#define this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
+#define this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)
+#define this_cpu_cmpxchg_1(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
+#define this_cpu_cmpxchg_2(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
+#define this_cpu_cmpxchg_4(pcp, oval, nval)     percpu_cmpxchg_op(pcp, oval, nval)
+
+#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
+#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
+#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval)  percpu_cmpxchg_op(pcp, oval, nval)
+#endif /* !CONFIG_M386 */
 
 /*
  * Per cpu atomic 64 bit operations are only available under 64 bit.
@@ -311,6 +466,7 @@ do {									\
 #define __this_cpu_and_8(pcp, val)      percpu_to_op("and", (pcp), val)
 #define __this_cpu_or_8(pcp, val)       percpu_to_op("or", (pcp), val)
 #define __this_cpu_xor_8(pcp, val)      percpu_to_op("xor", (pcp), val)
+#define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
 
 #define this_cpu_read_8(pcp)            percpu_from_op("mov", (pcp), "m"(pcp))
 #define this_cpu_write_8(pcp, val)      percpu_to_op("mov", (pcp), val)
@@ -318,12 +474,12 @@ do {									\
 #define this_cpu_and_8(pcp, val)        percpu_to_op("and", (pcp), val)
 #define this_cpu_or_8(pcp, val)         percpu_to_op("or", (pcp), val)
 #define this_cpu_xor_8(pcp, val)        percpu_to_op("xor", (pcp), val)
+#define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val)
 
 #define irqsafe_cpu_add_8(pcp, val)     percpu_add_op((pcp), val)
 #define irqsafe_cpu_and_8(pcp, val)     percpu_to_op("and", (pcp), val)
 #define irqsafe_cpu_or_8(pcp, val)      percpu_to_op("or", (pcp), val)
 #define irqsafe_cpu_xor_8(pcp, val)     percpu_to_op("xor", (pcp), val)
-
 #endif
 
 /* This is not atomic against other CPUs -- CPU preemption needs to be off */
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 550e26b1dbb3..d9d4dae305f6 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -125,7 +125,6 @@ union cpuid10_edx {
 #define IBS_OP_MAX_CNT_EXT      0x007FFFFFULL   /* not a register bit mask */
 
 #ifdef CONFIG_PERF_EVENTS
-extern void init_hw_perf_events(void);
 extern void perf_events_lapic_init(void);
 
 #define PERF_EVENT_INDEX_OFFSET                 0
@@ -156,7 +155,6 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs);
 }
 
 #else
-static inline void init_hw_perf_events(void)            { }
 static inline void perf_events_lapic_init(void) { }
 #endif
 
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index a70cd216be5d..e2f6a99f14ab 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -20,6 +20,9 @@
 #define ARCH_P4_MAX_ESCR        (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
 #define ARCH_P4_MAX_CCCR        (18)
 
+#define ARCH_P4_CNTRVAL_BITS    (40)
+#define ARCH_P4_CNTRVAL_MASK    ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
+
 #define P4_ESCR_EVENT_MASK      0x7e000000U
 #define P4_ESCR_EVENT_SHIFT     25
 #define P4_ESCR_EVENTMASK_MASK  0x01fffe00U
@@ -744,14 +747,6 @@ enum P4_ESCR_EMASKS {
 };
 
 /*
- * P4 PEBS specifics (Replay Event only)
- *
- * Format (bits):
- *   0-6: metric from P4_PEBS_METRIC enum
- *    7 : reserved
- *    8 : reserved
- * 9-11 : reserved
- *
  * Note we have UOP and PEBS bits reserved for now
  * just in case if we will need them once
  */
@@ -788,5 +783,60 @@ enum P4_PEBS_METRIC {
         P4_PEBS_METRIC__max
 };
 
+/*
+ * Notes on internal configuration of ESCR+CCCR tuples
+ *
+ * Since P4 has quite the different architecture of
+ * performance registers in compare with "architectural"
+ * once and we have on 64 bits to keep configuration
+ * of performance event, the following trick is used.
+ *
+ * 1) Since both ESCR and CCCR registers have only low
+ *    32 bits valuable, we pack them into a single 64 bit
+ *    configuration. Low 32 bits of such config correspond
+ *    to low 32 bits of CCCR register and high 32 bits
+ *    correspond to low 32 bits of ESCR register.
+ *
+ * 2) The meaning of every bit of such config field can
+ *    be found in Intel SDM but it should be noted that
+ *    we "borrow" some reserved bits for own usage and
+ *    clean them or set to a proper value when we do
+ *    a real write to hardware registers.
+ *
+ * 3) The format of bits of config is the following
+ *    and should be either 0 or set to some predefined
+ *    values:
+ *
+ *    Low 32 bits
+ *    -----------
+ *      0-6: P4_PEBS_METRIC enum
+ *     7-11:                    reserved
+ *       12:                    reserved (Enable)
+ *    13-15:                    reserved (ESCR select)
+ *    16-17: Active Thread
+ *       18: Compare
+ *       19: Complement
+ *    20-23: Threshold
+ *       24: Edge
+ *       25:                    reserved (FORCE_OVF)
+ *       26:                    reserved (OVF_PMI_T0)
+ *       27:                    reserved (OVF_PMI_T1)
+ *    28-29:                    reserved
+ *       30:                    reserved (Cascade)
+ *       31:                    reserved (OVF)
+ *
+ *    High 32 bits
+ *    ------------
+ *        0:                    reserved (T1_USR)
+ *        1:                    reserved (T1_OS)
+ *        2:                    reserved (T0_USR)
+ *        3:                    reserved (T0_OS)
+ *        4: Tag Enable
+ *      5-8: Tag Value
+ *     9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
+ *    25-30: enum P4_EVENTS
+ *       31:                    reserved (HT thread)
+ */
+
 #endif /* PERF_EVENT_P4_H */
 
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index b79bd980461c..521acfc47e7d 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -141,10 +141,9 @@ extern __u32			cpu_caps_set[NCAPINTS];
 #ifdef CONFIG_SMP
 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
-#define current_cpu_data        __get_cpu_var(cpu_info)
 #else
+#define cpu_info                boot_cpu_data
 #define cpu_data(cpu)           boot_cpu_data
-#define current_cpu_data        boot_cpu_data
 #endif
 
 extern const struct seq_operations cpuinfo_op;
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index d6763b139a84..db8aa19a08a2 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -53,6 +53,12 @@ extern void x86_mrst_early_setup(void);
 static inline void x86_mrst_early_setup(void) { }
 #endif
 
+#ifdef CONFIG_X86_INTEL_CE
+extern void x86_ce4100_early_setup(void);
+#else
+static inline void x86_ce4100_early_setup(void) { }
+#endif
+
 #ifndef _SETUP
 
 /*
diff --git a/arch/x86/include/asm/smpboot_hooks.h b/arch/x86/include/asm/smpboot_hooks.h
index 1def60114906..6c22bf353f26 100644
--- a/arch/x86/include/asm/smpboot_hooks.h
+++ b/arch/x86/include/asm/smpboot_hooks.h
@@ -48,7 +48,6 @@ static inline void __init smpboot_setup_io_apic(void)
                 setup_IO_APIC();
         else {
                 nr_ioapics = 0;
-                localise_nmi_watchdog();
         }
 #endif
 }
diff --git a/arch/x86/include/asm/stacktrace.h b/arch/x86/include/asm/stacktrace.h
index 2b16a2ad23dc..52b5c7ed3608 100644
--- a/arch/x86/include/asm/stacktrace.h
+++ b/arch/x86/include/asm/stacktrace.h
@@ -7,6 +7,7 @@
 #define _ASM_X86_STACKTRACE_H
 
 #include <linux/uaccess.h>
+#include <linux/ptrace.h>
 
 extern int kstack_depth_to_print;
 
@@ -46,7 +47,7 @@ struct stacktrace_ops {
 };
 
 void dump_trace(struct task_struct *tsk, struct pt_regs *regs,
-                unsigned long *stack, unsigned long bp,
+                unsigned long *stack,
                 const struct stacktrace_ops *ops, void *data);
 
 #ifdef CONFIG_X86_32
@@ -57,13 +58,39 @@ void dump_trace(struct task_struct *tsk, struct pt_regs *regs,
 #define get_bp(bp) asm("movq %%rbp, %0" : "=r" (bp) :)
 #endif
 
+#ifdef CONFIG_FRAME_POINTER
+static inline unsigned long
+stack_frame(struct task_struct *task, struct pt_regs *regs)
+{
+        unsigned long bp;
+
+        if (regs)
+                return regs->bp;
+
+        if (task == current) {
+                /* Grab bp right from our regs */
+                get_bp(bp);
+                return bp;
+        }
+
+        /* bp is the last reg pushed by switch_to */
+        return *(unsigned long *)task->thread.sp;
+}
+#else
+static inline unsigned long
+stack_frame(struct task_struct *task, struct pt_regs *regs)
+{
+        return 0;
+}
+#endif
+
 extern void
 show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
-                unsigned long *stack, unsigned long bp, char *log_lvl);
+                   unsigned long *stack, char *log_lvl);
 
 extern void
 show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
-                unsigned long *sp, unsigned long bp, char *log_lvl);
+                   unsigned long *sp, char *log_lvl);
 
 extern unsigned int code_bytes;
 
diff --git a/arch/x86/include/asm/timer.h b/arch/x86/include/asm/timer.h
index 5469630b27f5..fa7b9176b76c 100644
--- a/arch/x86/include/asm/timer.h
+++ b/arch/x86/include/asm/timer.h
@@ -10,12 +10,6 @@
 unsigned long long native_sched_clock(void);
 extern int recalibrate_cpu_khz(void);
 
-#if defined(CONFIG_X86_32) && defined(CONFIG_X86_IO_APIC)
-extern int timer_ack;
-#else
-# define timer_ack (0)
-#endif
-
 extern int no_timer_check;
 
 /* Accelerators for sched_clock()
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index 42d412fd8b02..ce1d54c8a433 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -26,20 +26,22 @@
  * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
  * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
  *
- * We will use 31 sets, one for sending BAU messages from each of the 32
+ * We will use one set for sending BAU messages from each of the
  * cpu's on the uvhub.
  *
  * TLB shootdown will use the first of the 8 descriptors of each set.
  * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
  */
 
+#define MAX_CPUS_PER_UVHUB              64
+#define MAX_CPUS_PER_SOCKET             32
+#define UV_ADP_SIZE                     64 /* hardware-provided max. */
+#define UV_CPUS_PER_ACT_STATUS          32 /* hardware-provided max. */
 #define UV_ITEMS_PER_DESCRIPTOR         8
 /* the 'throttle' to prevent the hardware stay-busy bug */
 #define MAX_BAU_CONCURRENT              3
-#define UV_CPUS_PER_ACT_STATUS          32
 #define UV_ACT_STATUS_MASK              0x3
 #define UV_ACT_STATUS_SIZE              2
-#define UV_ADP_SIZE                     32
 #define UV_DISTRIBUTION_SIZE            256
 #define UV_SW_ACK_NPENDING              8
 #define UV_NET_ENDPOINT_INTD            0x38
@@ -100,7 +102,6 @@
  * number of destination side software ack resources
  */
 #define DEST_NUM_RESOURCES              8
-#define MAX_CPUS_PER_NODE               32
 /*
  * completion statuses for sending a TLB flush message
  */
diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/xen/hypervisor.h
index 396ff4cc8ed4..66d0fff1ee84 100644
--- a/arch/x86/include/asm/xen/hypervisor.h
+++ b/arch/x86/include/asm/xen/hypervisor.h
@@ -37,4 +37,39 @@
 extern struct shared_info *HYPERVISOR_shared_info;
 extern struct start_info *xen_start_info;
 
+#include <asm/processor.h>
+
+static inline uint32_t xen_cpuid_base(void)
+{
+        uint32_t base, eax, ebx, ecx, edx;
+        char signature[13];
+
+        for (base = 0x40000000; base < 0x40010000; base += 0x100) {
+                cpuid(base, &eax, &ebx, &ecx, &edx);
+                *(uint32_t *)(signature + 0) = ebx;
+                *(uint32_t *)(signature + 4) = ecx;
+                *(uint32_t *)(signature + 8) = edx;
+                signature[12] = 0;
+
+                if (!strcmp("XenVMMXenVMM", signature) && ((eax - base) >= 2))
+                        return base;
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_XEN
+extern bool xen_hvm_need_lapic(void);
+
+static inline bool xen_x2apic_para_available(void)
+{
+        return xen_hvm_need_lapic();
+}
+#else
+static inline bool xen_x2apic_para_available(void)
+{
+        return (xen_cpuid_base() != 0);
+}
+#endif
+
 #endif /* _ASM_X86_XEN_HYPERVISOR_H */
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 1e994754d323..34244b2cd880 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -85,7 +85,6 @@ obj-$(CONFIG_DOUBLEFAULT) 	+= doublefault_32.o
 obj-$(CONFIG_KGDB)              += kgdb.o
 obj-$(CONFIG_VM86)              += vm86_32.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
-obj-$(CONFIG_EARLY_PRINTK_MRST) += early_printk_mrst.o
 
 obj-$(CONFIG_HPET_TIMER)        += hpet.o
 obj-$(CONFIG_APB_TIMER)         += apb_timer.o
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 71232b941b6c..ec881c6bfee0 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -198,6 +198,11 @@ static void __cpuinit acpi_register_lapic(int id, u8 enabled)
 {
         unsigned int ver = 0;
 
+        if (id >= (MAX_LOCAL_APIC-1)) {
+                printk(KERN_INFO PREFIX "skipped apicid that is too big\n");
+                return;
+        }
+
         if (!enabled) {
                 ++disabled_cpus;
                 return;
@@ -847,18 +852,6 @@ static int __init acpi_parse_fadt(struct acpi_table_header *table)
  * returns 0 on success, < 0 on error
  */
 
-static void __init acpi_register_lapic_address(unsigned long address)
-{
-        mp_lapic_addr = address;
-
-        set_fixmap_nocache(FIX_APIC_BASE, address);
-        if (boot_cpu_physical_apicid == -1U) {
-                boot_cpu_physical_apicid  = read_apic_id();
-                apic_version[boot_cpu_physical_apicid] =
-                         GET_APIC_VERSION(apic_read(APIC_LVR));
-        }
-}
-
 static int __init early_acpi_parse_madt_lapic_addr_ovr(void)
 {
         int count;
@@ -880,7 +873,7 @@ static int __init early_acpi_parse_madt_lapic_addr_ovr(void)
                 return count;
         }
 
-        acpi_register_lapic_address(acpi_lapic_addr);
+        register_lapic_address(acpi_lapic_addr);
 
         return count;
 }
@@ -907,16 +900,16 @@ static int __init acpi_parse_madt_lapic_entries(void)
                 return count;
         }
 
-        acpi_register_lapic_address(acpi_lapic_addr);
+        register_lapic_address(acpi_lapic_addr);
 
         count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_SAPIC,
-                                      acpi_parse_sapic, MAX_APICS);
+                                      acpi_parse_sapic, MAX_LOCAL_APIC);
 
         if (!count) {
                 x2count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_X2APIC,
-                                                acpi_parse_x2apic, MAX_APICS);
+                                        acpi_parse_x2apic, MAX_LOCAL_APIC);
                 count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC,
-                                              acpi_parse_lapic, MAX_APICS);
+                                        acpi_parse_lapic, MAX_LOCAL_APIC);
         }
         if (!count && !x2count) {
                 printk(KERN_ERR PREFIX "No LAPIC entries present\n");
@@ -949,32 +942,6 @@ static int __init acpi_parse_madt_lapic_entries(void)
 extern int es7000_plat;
 #endif
 
-static void assign_to_mp_irq(struct mpc_intsrc *m,
-                                    struct mpc_intsrc *mp_irq)
-{
-        memcpy(mp_irq, m, sizeof(struct mpc_intsrc));
-}
-
-static int mp_irq_cmp(struct mpc_intsrc *mp_irq,
-                                struct mpc_intsrc *m)
-{
-        return memcmp(mp_irq, m, sizeof(struct mpc_intsrc));
-}
-
-static void save_mp_irq(struct mpc_intsrc *m)
-{
-        int i;
-
-        for (i = 0; i < mp_irq_entries; i++) {
-                if (!mp_irq_cmp(&mp_irqs[i], m))
-                        return;
-        }
-
-        assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
-        if (++mp_irq_entries == MAX_IRQ_SOURCES)
-                panic("Max # of irq sources exceeded!!\n");
-}
-
 void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
 {
         int ioapic;
@@ -1005,7 +972,7 @@ void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
         mp_irq.dstapic = mp_ioapics[ioapic].apicid; /* APIC ID */
         mp_irq.dstirq = pin;    /* INTIN# */
 
-        save_mp_irq(&mp_irq);
+        mp_save_irq(&mp_irq);
 
         isa_irq_to_gsi[bus_irq] = gsi;
 }
@@ -1080,7 +1047,7 @@ void __init mp_config_acpi_legacy_irqs(void)
                 mp_irq.srcbusirq = i; /* Identity mapped */
                 mp_irq.dstirq = pin;
 
-                save_mp_irq(&mp_irq);
+                mp_save_irq(&mp_irq);
         }
 }
 
@@ -1117,7 +1084,7 @@ static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
         mp_irq.dstapic = mp_ioapics[ioapic].apicid;
         mp_irq.dstirq = mp_find_ioapic_pin(ioapic, gsi);
 
-        save_mp_irq(&mp_irq);
+        mp_save_irq(&mp_irq);
 #endif
         return 0;
 }
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 5079f24c955a..123608531c8f 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -353,6 +353,7 @@ void __init_or_module alternatives_smp_module_del(struct module *mod)
         mutex_unlock(&smp_alt);
 }
 
+bool skip_smp_alternatives;
 void alternatives_smp_switch(int smp)
 {
         struct smp_alt_module *mod;
@@ -368,7 +369,7 @@ void alternatives_smp_switch(int smp)
         printk("lockdep: fixing up alternatives.\n");
 #endif
 
-        if (noreplace_smp || smp_alt_once)
+        if (noreplace_smp || smp_alt_once || skip_smp_alternatives)
                 return;
         BUG_ON(!smp && (num_online_cpus() > 1));
 
@@ -591,17 +592,21 @@ static atomic_t stop_machine_first;
 static int wrote_text;
 
 struct text_poke_params {
-        void *addr;
-        const void *opcode;
-        size_t len;
+        struct text_poke_param *params;
+        int nparams;
 };
 
 static int __kprobes stop_machine_text_poke(void *data)
 {
         struct text_poke_params *tpp = data;
+        struct text_poke_param *p;
+        int i;
 
         if (atomic_dec_and_test(&stop_machine_first)) {
-                text_poke(tpp->addr, tpp->opcode, tpp->len);
+                for (i = 0; i < tpp->nparams; i++) {
+                        p = &tpp->params[i];
+                        text_poke(p->addr, p->opcode, p->len);
+                }
                 smp_wmb();      /* Make sure other cpus see that this has run */
                 wrote_text = 1;
         } else {
@@ -610,8 +615,12 @@ static int __kprobes stop_machine_text_poke(void *data)
                 smp_mb();       /* Load wrote_text before following execution */
         }
 
-        flush_icache_range((unsigned long)tpp->addr,
-                           (unsigned long)tpp->addr + tpp->len);
+        for (i = 0; i < tpp->nparams; i++) {
+                p = &tpp->params[i];
+                flush_icache_range((unsigned long)p->addr,
+                                   (unsigned long)p->addr + p->len);
+        }
+
         return 0;
 }
 
@@ -631,10 +640,13 @@ static int __kprobes stop_machine_text_poke(void *data)
 void *__kprobes text_poke_smp(void *addr, const void *opcode, size_t len)
 {
         struct text_poke_params tpp;
+        struct text_poke_param p;
 
-        tpp.addr = addr;
-        tpp.opcode = opcode;
-        tpp.len = len;
+        p.addr = addr;
+        p.opcode = opcode;
+        p.len = len;
+        tpp.params = &p;
+        tpp.nparams = 1;
         atomic_set(&stop_machine_first, 1);
         wrote_text = 0;
         /* Use __stop_machine() because the caller already got online_cpus. */
@@ -642,6 +654,26 @@ void *__kprobes text_poke_smp(void *addr, const void *opcode, size_t len)
         return addr;
 }
 
+/**
+ * text_poke_smp_batch - Update instructions on a live kernel on SMP
+ * @params: an array of text_poke parameters
+ * @n: the number of elements in params.
+ *
+ * Modify multi-byte instruction by using stop_machine() on SMP. Since the
+ * stop_machine() is heavy task, it is better to aggregate text_poke requests
+ * and do it once if possible.
+ *
+ * Note: Must be called under get_online_cpus() and text_mutex.
+ */
+void __kprobes text_poke_smp_batch(struct text_poke_param *params, int n)
+{
+        struct text_poke_params tpp = {.params = params, .nparams = n};
+
+        atomic_set(&stop_machine_first, 1);
+        wrote_text = 0;
+        stop_machine(stop_machine_text_poke, (void *)&tpp, NULL);
+}
+
 #if defined(CONFIG_DYNAMIC_FTRACE) || defined(HAVE_JUMP_LABEL)
 
 #ifdef CONFIG_X86_64
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 8f6463d8ed0d..0a99f7198bc3 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -12,95 +12,123 @@
 
 static u32 *flush_words;
 
-struct pci_device_id k8_nb_ids[] = {
+struct pci_device_id amd_nb_misc_ids[] = {
         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) },
         {}
 };
-EXPORT_SYMBOL(k8_nb_ids);
+EXPORT_SYMBOL(amd_nb_misc_ids);
 
-struct k8_northbridge_info k8_northbridges;
-EXPORT_SYMBOL(k8_northbridges);
+const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
+        { 0x00, 0x18, 0x20 },
+        { 0xff, 0x00, 0x20 },
+        { 0xfe, 0x00, 0x20 },
+        { }
+};
+
+struct amd_northbridge_info amd_northbridges;
+EXPORT_SYMBOL(amd_northbridges);
 
-static struct pci_dev *next_k8_northbridge(struct pci_dev *dev)
+static struct pci_dev *next_northbridge(struct pci_dev *dev,
+                                        struct pci_device_id *ids)
 {
         do {
                 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
                 if (!dev)
                         break;
-        } while (!pci_match_id(&k8_nb_ids[0], dev));
+        } while (!pci_match_id(ids, dev));
         return dev;
 }
 
-int cache_k8_northbridges(void)
+int amd_cache_northbridges(void)
 {
-        int i;
-        struct pci_dev *dev;
+        int i = 0;
+        struct amd_northbridge *nb;
+        struct pci_dev *misc;
 
-        if (k8_northbridges.num)
+        if (amd_nb_num())
                 return 0;
 
-        dev = NULL;
-        while ((dev = next_k8_northbridge(dev)) != NULL)
-                k8_northbridges.num++;
+        misc = NULL;
+        while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
+                i++;
 
-        /* some CPU families (e.g. family 0x11) do not support GART */
-        if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
-            boot_cpu_data.x86 == 0x15)
-                k8_northbridges.gart_supported = 1;
+        if (i == 0)
+                return 0;
 
-        k8_northbridges.nb_misc = kmalloc((k8_northbridges.num + 1) *
-                                          sizeof(void *), GFP_KERNEL);
-        if (!k8_northbridges.nb_misc)
+        nb = kzalloc(i * sizeof(struct amd_northbridge), GFP_KERNEL);
+        if (!nb)
                 return -ENOMEM;
 
-        if (!k8_northbridges.num) {
-                k8_northbridges.nb_misc[0] = NULL;
-                return 0;
-        }
+        amd_northbridges.nb = nb;
+        amd_northbridges.num = i;
 
-        if (k8_northbridges.gart_supported) {
-                flush_words = kmalloc(k8_northbridges.num * sizeof(u32),
-                                      GFP_KERNEL);
-                if (!flush_words) {
-                        kfree(k8_northbridges.nb_misc);
-                        return -ENOMEM;
-                }
-        }
+        misc = NULL;
+        for (i = 0; i != amd_nb_num(); i++) {
+                node_to_amd_nb(i)->misc = misc =
+                        next_northbridge(misc, amd_nb_misc_ids);
+        }
+
+        /* some CPU families (e.g. family 0x11) do not support GART */
+        if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
+            boot_cpu_data.x86 == 0x15)
+                amd_northbridges.flags |= AMD_NB_GART;
+
+        /*
+         * Some CPU families support L3 Cache Index Disable. There are some
+         * limitations because of E382 and E388 on family 0x10.
+         */
+        if (boot_cpu_data.x86 == 0x10 &&
+            boot_cpu_data.x86_model >= 0x8 &&
+            (boot_cpu_data.x86_model > 0x9 ||
+             boot_cpu_data.x86_mask >= 0x1))
+                amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 
-        dev = NULL;
-        i = 0;
-        while ((dev = next_k8_northbridge(dev)) != NULL) {
-                k8_northbridges.nb_misc[i] = dev;
-                if (k8_northbridges.gart_supported)
-                        pci_read_config_dword(dev, 0x9c, &flush_words[i++]);
-        }
-        k8_northbridges.nb_misc[i] = NULL;
         return 0;
 }
-EXPORT_SYMBOL_GPL(cache_k8_northbridges);
+EXPORT_SYMBOL_GPL(amd_cache_northbridges);
 
 /* Ignores subdevice/subvendor but as far as I can figure out
    they're useless anyways */
-int __init early_is_k8_nb(u32 device)
+int __init early_is_amd_nb(u32 device)
 {
         struct pci_device_id *id;
         u32 vendor = device & 0xffff;
         device >>= 16;
-        for (id = k8_nb_ids; id->vendor; id++)
+        for (id = amd_nb_misc_ids; id->vendor; id++)
                 if (vendor == id->vendor && device == id->device)
                         return 1;
         return 0;
 }
 
-void k8_flush_garts(void)
+int amd_cache_gart(void)
+{
+       int i;
+
+       if (!amd_nb_has_feature(AMD_NB_GART))
+               return 0;
+
+       flush_words = kmalloc(amd_nb_num() * sizeof(u32), GFP_KERNEL);
+       if (!flush_words) {
+               amd_northbridges.flags &= ~AMD_NB_GART;
+               return -ENOMEM;
+       }
+
+       for (i = 0; i != amd_nb_num(); i++)
+               pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c,
+                                     &flush_words[i]);
+
+       return 0;
+}
+
+void amd_flush_garts(void)
 {
         int flushed, i;
         unsigned long flags;
         static DEFINE_SPINLOCK(gart_lock);
 
-        if (!k8_northbridges.gart_supported)
+        if (!amd_nb_has_feature(AMD_NB_GART))
                 return;
 
         /* Avoid races between AGP and IOMMU. In theory it's not needed
@@ -109,16 +137,16 @@ void k8_flush_garts(void)
            that it doesn't matter to serialize more. -AK */
         spin_lock_irqsave(&gart_lock, flags);
         flushed = 0;
-        for (i = 0; i < k8_northbridges.num; i++) {
-                pci_write_config_dword(k8_northbridges.nb_misc[i], 0x9c,
-                                       flush_words[i]|1);
+        for (i = 0; i < amd_nb_num(); i++) {
+                pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
+                                       flush_words[i] | 1);
                 flushed++;
         }
-        for (i = 0; i < k8_northbridges.num; i++) {
+        for (i = 0; i < amd_nb_num(); i++) {
                 u32 w;
                 /* Make sure the hardware actually executed the flush*/
                 for (;;) {
-                        pci_read_config_dword(k8_northbridges.nb_misc[i],
+                        pci_read_config_dword(node_to_amd_nb(i)->misc,
                                               0x9c, &w);
                         if (!(w & 1))
                                 break;
@@ -129,19 +157,23 @@ void k8_flush_garts(void)
         if (!flushed)
                 printk("nothing to flush?\n");
 }
-EXPORT_SYMBOL_GPL(k8_flush_garts);
+EXPORT_SYMBOL_GPL(amd_flush_garts);
 
-static __init int init_k8_nbs(void)
+static __init int init_amd_nbs(void)
 {
         int err = 0;
 
-        err = cache_k8_northbridges();
+        err = amd_cache_northbridges();
 
         if (err < 0)
-                printk(KERN_NOTICE "K8 NB: Cannot enumerate AMD northbridges.\n");
+                printk(KERN_NOTICE "AMD NB: Cannot enumerate AMD northbridges.\n");
+
+        if (amd_cache_gart() < 0)
+                printk(KERN_NOTICE "AMD NB: Cannot initialize GART flush words, "
+                       "GART support disabled.\n");
 
         return err;
 }
 
 /* This has to go after the PCI subsystem */
-fs_initcall(init_k8_nbs);
+fs_initcall(init_amd_nbs);
diff --git a/arch/x86/kernel/apb_timer.c b/arch/x86/kernel/apb_timer.c
index 92543c73cf8e..7c9ab59653e8 100644
--- a/arch/x86/kernel/apb_timer.c
+++ b/arch/x86/kernel/apb_timer.c
@@ -315,6 +315,7 @@ static void apbt_setup_irq(struct apbt_dev *adev)
 
         if (system_state == SYSTEM_BOOTING) {
                 irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
+                irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
                 /* APB timer irqs are set up as mp_irqs, timer is edge type */
                 __set_irq_handler(adev->irq, handle_edge_irq, 0, "edge");
                 if (request_irq(adev->irq, apbt_interrupt_handler,
diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index b3a16e8f0703..5955a7800a96 100644
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -39,18 +39,6 @@ int fallback_aper_force __initdata;
 
 int fix_aperture __initdata = 1;
 
-struct bus_dev_range {
-        int bus;
-        int dev_base;
-        int dev_limit;
-};
-
-static struct bus_dev_range bus_dev_ranges[] __initdata = {
-        { 0x00, 0x18, 0x20},
-        { 0xff, 0x00, 0x20},
-        { 0xfe, 0x00, 0x20}
-};
-
 static struct resource gart_resource = {
         .name   = "GART",
         .flags  = IORESOURCE_MEM,
@@ -206,7 +194,7 @@ static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
  * Do an PCI bus scan by hand because we're running before the PCI
  * subsystem.
  *
- * All K8 AGP bridges are AGPv3 compliant, so we can do this scan
+ * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
  * generically. It's probably overkill to always scan all slots because
  * the AGP bridges should be always an own bus on the HT hierarchy,
  * but do it here for future safety.
@@ -294,16 +282,16 @@ void __init early_gart_iommu_check(void)
         search_agp_bridge(&agp_aper_order, &valid_agp);
 
         fix = 0;
-        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+        for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
                 int bus;
                 int dev_base, dev_limit;
 
-                bus = bus_dev_ranges[i].bus;
-                dev_base = bus_dev_ranges[i].dev_base;
-                dev_limit = bus_dev_ranges[i].dev_limit;
+                bus = amd_nb_bus_dev_ranges[i].bus;
+                dev_base = amd_nb_bus_dev_ranges[i].dev_base;
+                dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
 
                 for (slot = dev_base; slot < dev_limit; slot++) {
-                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                        if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
                                 continue;
 
                         ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
@@ -349,16 +337,16 @@ void __init early_gart_iommu_check(void)
                 return;
 
         /* disable them all at first */
-        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+        for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
                 int bus;
                 int dev_base, dev_limit;
 
-                bus = bus_dev_ranges[i].bus;
-                dev_base = bus_dev_ranges[i].dev_base;
-                dev_limit = bus_dev_ranges[i].dev_limit;
+                bus = amd_nb_bus_dev_ranges[i].bus;
+                dev_base = amd_nb_bus_dev_ranges[i].dev_base;
+                dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
 
                 for (slot = dev_base; slot < dev_limit; slot++) {
-                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                        if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
                                 continue;
 
                         ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
@@ -390,17 +378,17 @@ int __init gart_iommu_hole_init(void)
 
         fix = 0;
         node = 0;
-        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+        for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
                 int bus;
                 int dev_base, dev_limit;
                 u32 ctl;
 
-                bus = bus_dev_ranges[i].bus;
-                dev_base = bus_dev_ranges[i].dev_base;
-                dev_limit = bus_dev_ranges[i].dev_limit;
+                bus = amd_nb_bus_dev_ranges[i].bus;
+                dev_base = amd_nb_bus_dev_ranges[i].dev_base;
+                dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
 
                 for (slot = dev_base; slot < dev_limit; slot++) {
-                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                        if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
                                 continue;
 
                         iommu_detected = 1;
@@ -505,7 +493,7 @@ out:
         }
 
         /* Fix up the north bridges */
-        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
+        for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
                 int bus, dev_base, dev_limit;
 
                 /*
@@ -514,11 +502,11 @@ out:
                  */
                 u32 ctl = DISTLBWALKPRB | aper_order << 1;
 
-                bus = bus_dev_ranges[i].bus;
-                dev_base = bus_dev_ranges[i].dev_base;
-                dev_limit = bus_dev_ranges[i].dev_limit;
+                bus = amd_nb_bus_dev_ranges[i].bus;
+                dev_base = amd_nb_bus_dev_ranges[i].dev_base;
+                dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
                 for (slot = dev_base; slot < dev_limit; slot++) {
-                        if (!early_is_k8_nb(read_pci_config(bus, slot, 3, 0x00)))
+                        if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
                                 continue;
 
                         write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
diff --git a/arch/x86/kernel/apic/Makefile b/arch/x86/kernel/apic/Makefile
index 910f20b457c4..3966b564ea47 100644
--- a/arch/x86/kernel/apic/Makefile
+++ b/arch/x86/kernel/apic/Makefile
@@ -3,10 +3,7 @@
 #
 
 obj-$(CONFIG_X86_LOCAL_APIC)    += apic.o apic_noop.o probe_$(BITS).o ipi.o
-ifneq ($(CONFIG_HARDLOCKUP_DETECTOR),y)
-obj-$(CONFIG_X86_LOCAL_APIC)    += nmi.o
-endif
-obj-$(CONFIG_HARDLOCKUP_DETECTOR)       += hw_nmi.o
+obj-y                           += hw_nmi.o
 
 obj-$(CONFIG_X86_IO_APIC)       += io_apic.o
 obj-$(CONFIG_SMP)               += ipi.o
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 78218135b48e..06c196d7e59c 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -31,7 +31,6 @@
 #include <linux/init.h>
 #include <linux/cpu.h>
 #include <linux/dmi.h>
-#include <linux/nmi.h>
 #include <linux/smp.h>
 #include <linux/mm.h>
 
@@ -50,8 +49,8 @@
 #include <asm/mtrr.h>
 #include <asm/smp.h>
 #include <asm/mce.h>
-#include <asm/kvm_para.h>
 #include <asm/tsc.h>
+#include <asm/hypervisor.h>
 
 unsigned int num_processors;
 
@@ -432,17 +431,18 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
         reserved = reserve_eilvt_offset(offset, new);
 
         if (reserved != new) {
-                pr_err(FW_BUG "cpu %d, try to setup vector 0x%x, but "
-                       "vector 0x%x was already reserved by another core, "
-                       "APIC%lX=0x%x\n",
-                       smp_processor_id(), new, reserved, reg, old);
+                pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
+                       "vector 0x%x, but the register is already in use for "
+                       "vector 0x%x on another cpu\n",
+                       smp_processor_id(), reg, offset, new, reserved);
                 return -EINVAL;
         }
 
         if (!eilvt_entry_is_changeable(old, new)) {
-                pr_err(FW_BUG "cpu %d, try to setup vector 0x%x but "
-                       "register already in use, APIC%lX=0x%x\n",
-                       smp_processor_id(), new, reg, old);
+                pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
+                       "vector 0x%x, but the register is already in use for "
+                       "vector 0x%x on this cpu\n",
+                       smp_processor_id(), reg, offset, new, old);
                 return -EBUSY;
         }
 
@@ -516,7 +516,7 @@ static void __cpuinit setup_APIC_timer(void)
 {
         struct clock_event_device *levt = &__get_cpu_var(lapic_events);
 
-        if (cpu_has(&current_cpu_data, X86_FEATURE_ARAT)) {
+        if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_ARAT)) {
                 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
                 /* Make LAPIC timer preferrable over percpu HPET */
                 lapic_clockevent.rating = 150;
@@ -684,7 +684,7 @@ static int __init calibrate_APIC_clock(void)
         lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
                                        lapic_clockevent.shift);
         lapic_clockevent.max_delta_ns =
-                clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
+                clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
         lapic_clockevent.min_delta_ns =
                 clockevent_delta2ns(0xF, &lapic_clockevent);
 
@@ -799,11 +799,7 @@ void __init setup_boot_APIC_clock(void)
          * PIT/HPET going.  Otherwise register lapic as a dummy
          * device.
          */
-        if (nmi_watchdog != NMI_IO_APIC)
-                lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
-        else
-                pr_warning("APIC timer registered as dummy,"
-                        " due to nmi_watchdog=%d!\n", nmi_watchdog);
+        lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
 
         /* Setup the lapic or request the broadcast */
         setup_APIC_timer();
@@ -1195,12 +1191,15 @@ static void __cpuinit lapic_setup_esr(void)
                         oldvalue, value);
 }
 
-
 /**
  * setup_local_APIC - setup the local APIC
+ *
+ * Used to setup local APIC while initializing BSP or bringin up APs.
+ * Always called with preemption disabled.
  */
 void __cpuinit setup_local_APIC(void)
 {
+        int cpu = smp_processor_id();
         unsigned int value, queued;
         int i, j, acked = 0;
         unsigned long long tsc = 0, ntsc;
@@ -1225,8 +1224,6 @@ void __cpuinit setup_local_APIC(void)
 #endif
         perf_events_lapic_init();
 
-        preempt_disable();
-
         /*
          * Double-check whether this APIC is really registered.
          * This is meaningless in clustered apic mode, so we skip it.
@@ -1342,21 +1339,19 @@ void __cpuinit setup_local_APIC(void)
          * TODO: set up through-local-APIC from through-I/O-APIC? --macro
          */
         value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
-        if (!smp_processor_id() && (pic_mode || !value)) {
+        if (!cpu && (pic_mode || !value)) {
                 value = APIC_DM_EXTINT;
-                apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
-                                smp_processor_id());
+                apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
         } else {
                 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
-                apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
-                                smp_processor_id());
+                apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
         }
         apic_write(APIC_LVT0, value);
 
         /*
          * only the BP should see the LINT1 NMI signal, obviously.
          */
-        if (!smp_processor_id())
+        if (!cpu)
                 value = APIC_DM_NMI;
         else
                 value = APIC_DM_NMI | APIC_LVT_MASKED;
@@ -1364,11 +1359,9 @@ void __cpuinit setup_local_APIC(void)
                 value |= APIC_LVT_LEVEL_TRIGGER;
         apic_write(APIC_LVT1, value);
 
-        preempt_enable();
-
 #ifdef CONFIG_X86_MCE_INTEL
         /* Recheck CMCI information after local APIC is up on CPU #0 */
-        if (smp_processor_id() == 0)
+        if (!cpu)
                 cmci_recheck();
 #endif
 }
@@ -1387,7 +1380,6 @@ void __cpuinit end_local_APIC_setup(void)
         }
 #endif
 
-        setup_apic_nmi_watchdog(NULL);
         apic_pm_activate();
 
         /*
@@ -1484,7 +1476,8 @@ void __init enable_IR_x2apic(void)
                 /* IR is required if there is APIC ID > 255 even when running
                  * under KVM
                  */
-                if (max_physical_apicid > 255 || !kvm_para_available())
+                if (max_physical_apicid > 255 ||
+                    !hypervisor_x2apic_available())
                         goto nox2apic;
                 /*
                  * without IR all CPUs can be addressed by IOAPIC/MSI
@@ -1538,13 +1531,60 @@ static int __init detect_init_APIC(void)
         return 0;
 }
 #else
+
+static int apic_verify(void)
+{
+        u32 features, h, l;
+
+        /*
+         * The APIC feature bit should now be enabled
+         * in `cpuid'
+         */
+        features = cpuid_edx(1);
+        if (!(features & (1 << X86_FEATURE_APIC))) {
+                pr_warning("Could not enable APIC!\n");
+                return -1;
+        }
+        set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
+        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
+
+        /* The BIOS may have set up the APIC at some other address */
+        rdmsr(MSR_IA32_APICBASE, l, h);
+        if (l & MSR_IA32_APICBASE_ENABLE)
+                mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+
+        pr_info("Found and enabled local APIC!\n");
+        return 0;
+}
+
+int apic_force_enable(void)
+{
+        u32 h, l;
+
+        if (disable_apic)
+                return -1;
+
+        /*
+         * Some BIOSes disable the local APIC in the APIC_BASE
+         * MSR. This can only be done in software for Intel P6 or later
+         * and AMD K7 (Model > 1) or later.
+         */
+        rdmsr(MSR_IA32_APICBASE, l, h);
+        if (!(l & MSR_IA32_APICBASE_ENABLE)) {
+                pr_info("Local APIC disabled by BIOS -- reenabling.\n");
+                l &= ~MSR_IA32_APICBASE_BASE;
+                l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
+                wrmsr(MSR_IA32_APICBASE, l, h);
+                enabled_via_apicbase = 1;
+        }
+        return apic_verify();
+}
+
 /*
  * Detect and initialize APIC
  */
 static int __init detect_init_APIC(void)
 {
-        u32 h, l, features;
-
         /* Disabled by kernel option? */
         if (disable_apic)
                 return -1;
@@ -1574,38 +1614,12 @@ static int __init detect_init_APIC(void)
                                 "you can enable it with \"lapic\"\n");
                         return -1;
                 }
-                /*
-                 * Some BIOSes disable the local APIC in the APIC_BASE
-                 * MSR. This can only be done in software for Intel P6 or later
-                 * and AMD K7 (Model > 1) or later.
-                 */
-                rdmsr(MSR_IA32_APICBASE, l, h);
-                if (!(l & MSR_IA32_APICBASE_ENABLE)) {
-                        pr_info("Local APIC disabled by BIOS -- reenabling.\n");
-                        l &= ~MSR_IA32_APICBASE_BASE;
-                        l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
-                        wrmsr(MSR_IA32_APICBASE, l, h);
-                        enabled_via_apicbase = 1;
-                }
-        }
-        /*
-         * The APIC feature bit should now be enabled
-         * in `cpuid'
-         */
-        features = cpuid_edx(1);
-        if (!(features & (1 << X86_FEATURE_APIC))) {
-                pr_warning("Could not enable APIC!\n");
-                return -1;
+                if (apic_force_enable())
+                        return -1;
+        } else {
+                if (apic_verify())
+                        return -1;
         }
-        set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
-        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
-
-        /* The BIOS may have set up the APIC at some other address */
-        rdmsr(MSR_IA32_APICBASE, l, h);
-        if (l & MSR_IA32_APICBASE_ENABLE)
-                mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
-
-        pr_info("Found and enabled local APIC!\n");
 
         apic_pm_activate();
 
@@ -1617,28 +1631,6 @@ no_apic:
 }
 #endif
 
-#ifdef CONFIG_X86_64
-void __init early_init_lapic_mapping(void)
-{
-        /*
-         * If no local APIC can be found then go out
-         * : it means there is no mpatable and MADT
-         */
-        if (!smp_found_config)
-                return;
-
-        set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
-        apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
-                    APIC_BASE, mp_lapic_addr);
-
-        /*
-         * Fetch the APIC ID of the BSP in case we have a
-         * default configuration (or the MP table is broken).
-         */
-        boot_cpu_physical_apicid = read_apic_id();
-}
-#endif
-
 /**
  * init_apic_mappings - initialize APIC mappings
  */
@@ -1664,10 +1656,7 @@ void __init init_apic_mappings(void)
                  * acpi_register_lapic_address()
                  */
                 if (!acpi_lapic && !smp_found_config)
-                        set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
-
-                apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
-                                        APIC_BASE, apic_phys);
+                        register_lapic_address(apic_phys);
         }
 
         /*
@@ -1689,11 +1678,27 @@ void __init init_apic_mappings(void)
         }
 }
 
+void __init register_lapic_address(unsigned long address)
+{
+        mp_lapic_addr = address;
+
+        if (!x2apic_mode) {
+                set_fixmap_nocache(FIX_APIC_BASE, address);
+                apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
+                            APIC_BASE, mp_lapic_addr);
+        }
+        if (boot_cpu_physical_apicid == -1U) {
+                boot_cpu_physical_apicid  = read_apic_id();
+                apic_version[boot_cpu_physical_apicid] =
+                         GET_APIC_VERSION(apic_read(APIC_LVR));
+        }
+}
+
 /*
  * This initializes the IO-APIC and APIC hardware if this is
  * a UP kernel.
  */
-int apic_version[MAX_APICS];
+int apic_version[MAX_LOCAL_APIC];
 
 int __init APIC_init_uniprocessor(void)
 {
@@ -1758,17 +1763,10 @@ int __init APIC_init_uniprocessor(void)
                 setup_IO_APIC();
         else {
                 nr_ioapics = 0;
-                localise_nmi_watchdog();
         }
-#else
-        localise_nmi_watchdog();
 #endif
 
         x86_init.timers.setup_percpu_clockev();
-#ifdef CONFIG_X86_64
-        check_nmi_watchdog();
-#endif
-
         return 0;
 }
 
diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c
index 62f6e1e55b90..79fd43ca6f96 100644
--- a/arch/x86/kernel/apic/hw_nmi.c
+++ b/arch/x86/kernel/apic/hw_nmi.c
@@ -17,20 +17,31 @@
 #include <linux/nmi.h>
 #include <linux/module.h>
 
+#ifdef CONFIG_HARDLOCKUP_DETECTOR
 u64 hw_nmi_get_sample_period(void)
 {
         return (u64)(cpu_khz) * 1000 * 60;
 }
+#endif
 
-#ifdef ARCH_HAS_NMI_WATCHDOG
-
+#ifdef arch_trigger_all_cpu_backtrace
 /* For reliability, we're prepared to waste bits here. */
 static DECLARE_BITMAP(backtrace_mask, NR_CPUS) __read_mostly;
 
+/* "in progress" flag of arch_trigger_all_cpu_backtrace */
+static unsigned long backtrace_flag;
+
 void arch_trigger_all_cpu_backtrace(void)
 {
         int i;
 
+        if (test_and_set_bit(0, &backtrace_flag))
+                /*
+                 * If there is already a trigger_all_cpu_backtrace() in progress
+                 * (backtrace_flag == 1), don't output double cpu dump infos.
+                 */
+                return;
+
         cpumask_copy(to_cpumask(backtrace_mask), cpu_online_mask);
 
         printk(KERN_INFO "sending NMI to all CPUs:\n");
@@ -42,6 +53,9 @@ void arch_trigger_all_cpu_backtrace(void)
                         break;
                 mdelay(1);
         }
+
+        clear_bit(0, &backtrace_flag);
+        smp_mb__after_clear_bit();
 }
 
 static int __kprobes
@@ -50,11 +64,10 @@ arch_trigger_all_cpu_backtrace_handler(struct notifier_block *self,
 {
         struct die_args *args = __args;
         struct pt_regs *regs;
-        int cpu = smp_processor_id();
+        int cpu;
 
         switch (cmd) {
         case DIE_NMI:
-        case DIE_NMI_IPI:
                 break;
 
         default:
@@ -62,6 +75,7 @@ arch_trigger_all_cpu_backtrace_handler(struct notifier_block *self,
         }
 
         regs = args->regs;
+        cpu = smp_processor_id();
 
         if (cpumask_test_cpu(cpu, to_cpumask(backtrace_mask))) {
                 static arch_spinlock_t lock = __ARCH_SPIN_LOCK_UNLOCKED;
@@ -81,7 +95,7 @@ arch_trigger_all_cpu_backtrace_handler(struct notifier_block *self,
 static __read_mostly struct notifier_block backtrace_notifier = {
         .notifier_call          = arch_trigger_all_cpu_backtrace_handler,
         .next                   = NULL,
-        .priority               = 1
+        .priority               = NMI_LOCAL_LOW_PRIOR,
 };
 
 static int __init register_trigger_all_cpu_backtrace(void)
@@ -91,18 +105,3 @@ static int __init register_trigger_all_cpu_backtrace(void)
 }
 early_initcall(register_trigger_all_cpu_backtrace);
 #endif
-
-/* STUB calls to mimic old nmi_watchdog behaviour */
-#if defined(CONFIG_X86_LOCAL_APIC)
-unsigned int nmi_watchdog = NMI_NONE;
-EXPORT_SYMBOL(nmi_watchdog);
-void acpi_nmi_enable(void) { return; }
-void acpi_nmi_disable(void) { return; }
-#endif
-atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
-EXPORT_SYMBOL(nmi_active);
-int unknown_nmi_panic;
-void cpu_nmi_set_wd_enabled(void) { return; }
-void stop_apic_nmi_watchdog(void *unused) { return; }
-void setup_apic_nmi_watchdog(void *unused) { return; }
-int __init check_nmi_watchdog(void) { return 0; }
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index fadcd743a74f..697dc34b7b87 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -54,7 +54,6 @@
 #include <asm/dma.h>
 #include <asm/timer.h>
 #include <asm/i8259.h>
-#include <asm/nmi.h>
 #include <asm/msidef.h>
 #include <asm/hypertransport.h>
 #include <asm/setup.h>
@@ -126,6 +125,26 @@ static int __init parse_noapic(char *str)
 }
 early_param("noapic", parse_noapic);
 
+/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
+void mp_save_irq(struct mpc_intsrc *m)
+{
+        int i;
+
+        apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
+                " IRQ %02x, APIC ID %x, APIC INT %02x\n",
+                m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
+                m->srcbusirq, m->dstapic, m->dstirq);
+
+        for (i = 0; i < mp_irq_entries; i++) {
+                if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
+                        return;
+        }
+
+        memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
+        if (++mp_irq_entries == MAX_IRQ_SOURCES)
+                panic("Max # of irq sources exceeded!!\n");
+}
+
 struct irq_pin_list {
         int apic, pin;
         struct irq_pin_list *next;
@@ -136,6 +155,7 @@ static struct irq_pin_list *alloc_irq_pin_list(int node)
         return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
 }
 
+
 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 #ifdef CONFIG_SPARSE_IRQ
 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
@@ -1934,8 +1954,7 @@ void disable_IO_APIC(void)
  *
  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
  */
-
-void __init setup_ioapic_ids_from_mpc(void)
+void __init setup_ioapic_ids_from_mpc_nocheck(void)
 {
         union IO_APIC_reg_00 reg_00;
         physid_mask_t phys_id_present_map;
@@ -1944,15 +1963,6 @@ void __init setup_ioapic_ids_from_mpc(void)
         unsigned char old_id;
         unsigned long flags;
 
-        if (acpi_ioapic)
-                return;
-        /*
-         * Don't check I/O APIC IDs for xAPIC systems.  They have
-         * no meaning without the serial APIC bus.
-         */
-        if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
-                || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
-                return;
         /*
          * This is broken; anything with a real cpu count has to
          * circumvent this idiocy regardless.
@@ -2006,7 +2016,6 @@ void __init setup_ioapic_ids_from_mpc(void)
                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
                 }
 
-
                 /*
                  * We need to adjust the IRQ routing table
                  * if the ID changed.
@@ -2018,9 +2027,12 @@ void __init setup_ioapic_ids_from_mpc(void)
                                                 = mp_ioapics[apic_id].apicid;
 
                 /*
-                 * Read the right value from the MPC table and
-                 * write it into the ID register.
+                 * Update the ID register according to the right value
+                 * from the MPC table if they are different.
                  */
+                if (mp_ioapics[apic_id].apicid == reg_00.bits.ID)
+                        continue;
+
                 apic_printk(APIC_VERBOSE, KERN_INFO
                         "...changing IO-APIC physical APIC ID to %d ...",
                         mp_ioapics[apic_id].apicid);
@@ -2042,6 +2054,21 @@ void __init setup_ioapic_ids_from_mpc(void)
                         apic_printk(APIC_VERBOSE, " ok.\n");
         }
 }
+
+void __init setup_ioapic_ids_from_mpc(void)
+{
+
+        if (acpi_ioapic)
+                return;
+        /*
+         * Don't check I/O APIC IDs for xAPIC systems.  They have
+         * no meaning without the serial APIC bus.
+         */
+        if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
+                || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
+                return;
+        setup_ioapic_ids_from_mpc_nocheck();
+}
 #endif
 
 int no_timer_check __initdata;
@@ -2302,7 +2329,7 @@ asmlinkage void smp_irq_move_cleanup_interrupt(void)
                 unsigned int irr;
                 struct irq_desc *desc;
                 struct irq_cfg *cfg;
-                irq = __get_cpu_var(vector_irq)[vector];
+                irq = __this_cpu_read(vector_irq[vector]);
 
                 if (irq == -1)
                         continue;
@@ -2336,7 +2363,7 @@ asmlinkage void smp_irq_move_cleanup_interrupt(void)
                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
                         goto unlock;
                 }
-                __get_cpu_var(vector_irq)[vector] = -1;
+                __this_cpu_write(vector_irq[vector], -1);
 unlock:
                 raw_spin_unlock(&desc->lock);
         }
@@ -2642,24 +2669,6 @@ static void lapic_register_intr(int irq)
                                       "edge");
 }
 
-static void __init setup_nmi(void)
-{
-        /*
-         * Dirty trick to enable the NMI watchdog ...
-         * We put the 8259A master into AEOI mode and
-         * unmask on all local APICs LVT0 as NMI.
-         *
-         * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
-         * is from Maciej W. Rozycki - so we do not have to EOI from
-         * the NMI handler or the timer interrupt.
-         */
-        apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
-
-        enable_NMI_through_LVT0();
-
-        apic_printk(APIC_VERBOSE, " done.\n");
-}
-
 /*
  * This looks a bit hackish but it's about the only one way of sending
  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
@@ -2765,15 +2774,6 @@ static inline void __init check_timer(void)
          */
         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
         legacy_pic->init(1);
-#ifdef CONFIG_X86_32
-        {
-                unsigned int ver;
-
-                ver = apic_read(APIC_LVR);
-                ver = GET_APIC_VERSION(ver);
-                timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
-        }
-#endif
 
         pin1  = find_isa_irq_pin(0, mp_INT);
         apic1 = find_isa_irq_apic(0, mp_INT);
@@ -2821,10 +2821,6 @@ static inline void __init check_timer(void)
                                 unmask_ioapic(cfg);
                 }
                 if (timer_irq_works()) {
-                        if (nmi_watchdog == NMI_IO_APIC) {
-                                setup_nmi();
-                                legacy_pic->unmask(0);
-                        }
                         if (disable_timer_pin_1 > 0)
                                 clear_IO_APIC_pin(0, pin1);
                         goto out;
@@ -2850,11 +2846,6 @@ static inline void __init check_timer(void)
                 if (timer_irq_works()) {
                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
                         timer_through_8259 = 1;
-                        if (nmi_watchdog == NMI_IO_APIC) {
-                                legacy_pic->mask(0);
-                                setup_nmi();
-                                legacy_pic->unmask(0);
-                        }
                         goto out;
                 }
                 /*
@@ -2866,15 +2857,6 @@ static inline void __init check_timer(void)
                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
         }
 
-        if (nmi_watchdog == NMI_IO_APIC) {
-                apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
-                            "through the IO-APIC - disabling NMI Watchdog!\n");
-                nmi_watchdog = NMI_NONE;
-        }
-#ifdef CONFIG_X86_32
-        timer_ack = 0;
-#endif
-
         apic_printk(APIC_QUIET, KERN_INFO
                     "...trying to set up timer as Virtual Wire IRQ...\n");
 
@@ -3639,7 +3621,7 @@ int __init io_apic_get_redir_entries (int ioapic)
         return reg_01.bits.entries + 1;
 }
 
-void __init probe_nr_irqs_gsi(void)
+static void __init probe_nr_irqs_gsi(void)
 {
         int nr;
 
@@ -3956,7 +3938,7 @@ static struct resource * __init ioapic_setup_resources(int nr_ioapics)
         return res;
 }
 
-void __init ioapic_init_mappings(void)
+void __init ioapic_and_gsi_init(void)
 {
         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
         struct resource *ioapic_res;
@@ -3994,6 +3976,8 @@ fake_ioapic_page:
                 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
                 ioapic_res++;
         }
+
+        probe_nr_irqs_gsi();
 }
 
 void __init ioapic_insert_resources(void)
@@ -4103,7 +4087,8 @@ void __init pre_init_apic_IRQ0(void)
 
         printk(KERN_INFO "Early APIC setup for system timer0\n");
 #ifndef CONFIG_SMP
-        phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
+        physid_set_mask_of_physid(boot_cpu_physical_apicid,
+                                         &phys_cpu_present_map);
 #endif
         /* Make sure the irq descriptor is set up */
         cfg = alloc_irq_and_cfg_at(0, 0);
diff --git a/arch/x86/kernel/apic/nmi.c b/arch/x86/kernel/apic/nmi.c
deleted file mode 100644
index c90041ccb742..000000000000
--- a/arch/x86/kernel/apic/nmi.c
+++ /dev/null
@@ -1,567 +0,0 @@
-/*
- *  NMI watchdog support on APIC systems
- *
- *  Started by Ingo Molnar <mingo@redhat.com>
- *
- *  Fixes:
- *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
- *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
- *  Mikael Pettersson   : Pentium 4 support for local APIC NMI watchdog.
- *  Pavel Machek and
- *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
- */
-
-#include <asm/apic.h>
-
-#include <linux/nmi.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/sysdev.h>
-#include <linux/sysctl.h>
-#include <linux/percpu.h>
-#include <linux/kprobes.h>
-#include <linux/cpumask.h>
-#include <linux/kernel_stat.h>
-#include <linux/kdebug.h>
-#include <linux/smp.h>
-
-#include <asm/i8259.h>
-#include <asm/io_apic.h>
-#include <asm/proto.h>
-#include <asm/timer.h>
-
-#include <asm/mce.h>
-
-#include <asm/mach_traps.h>
-
-int unknown_nmi_panic;
-int nmi_watchdog_enabled;
-
-/* For reliability, we're prepared to waste bits here. */
-static DECLARE_BITMAP(backtrace_mask, NR_CPUS) __read_mostly;
-
-/* nmi_active:
- * >0: the lapic NMI watchdog is active, but can be disabled
- * <0: the lapic NMI watchdog has not been set up, and cannot
- *     be enabled
- *  0: the lapic NMI watchdog is disabled, but can be enabled
- */
-atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
-EXPORT_SYMBOL(nmi_active);
-
-unsigned int nmi_watchdog = NMI_NONE;
-EXPORT_SYMBOL(nmi_watchdog);
-
-static int panic_on_timeout;
-
-static unsigned int nmi_hz = HZ;
-static DEFINE_PER_CPU(short, wd_enabled);
-static int endflag __initdata;
-
-static inline unsigned int get_nmi_count(int cpu)
-{
-        return per_cpu(irq_stat, cpu).__nmi_count;
-}
-
-static inline int mce_in_progress(void)
-{
-#if defined(CONFIG_X86_MCE)
-        return atomic_read(&mce_entry) > 0;
-#endif
-        return 0;
-}
-
-/*
- * Take the local apic timer and PIT/HPET into account. We don't
- * know which one is active, when we have highres/dyntick on
- */
-static inline unsigned int get_timer_irqs(int cpu)
-{
-        return per_cpu(irq_stat, cpu).apic_timer_irqs +
-                per_cpu(irq_stat, cpu).irq0_irqs;
-}
-
-#ifdef CONFIG_SMP
-/*
- * The performance counters used by NMI_LOCAL_APIC don't trigger when
- * the CPU is idle. To make sure the NMI watchdog really ticks on all
- * CPUs during the test make them busy.
- */
-static __init void nmi_cpu_busy(void *data)
-{
-        local_irq_enable_in_hardirq();
-        /*
-         * Intentionally don't use cpu_relax here. This is
-         * to make sure that the performance counter really ticks,
-         * even if there is a simulator or similar that catches the
-         * pause instruction. On a real HT machine this is fine because
-         * all other CPUs are busy with "useless" delay loops and don't
-         * care if they get somewhat less cycles.
-         */
-        while (endflag == 0)
-                mb();
-}
-#endif
-
-static void report_broken_nmi(int cpu, unsigned int *prev_nmi_count)
-{
-        printk(KERN_CONT "\n");
-
-        printk(KERN_WARNING
-                "WARNING: CPU#%d: NMI appears to be stuck (%d->%d)!\n",
-                        cpu, prev_nmi_count[cpu], get_nmi_count(cpu));
-
-        printk(KERN_WARNING
-                "Please report this to bugzilla.kernel.org,\n");
-        printk(KERN_WARNING
-                "and attach the output of the 'dmesg' command.\n");
-
-        per_cpu(wd_enabled, cpu) = 0;
-        atomic_dec(&nmi_active);
-}
-
-static void __acpi_nmi_disable(void *__unused)
-{
-        apic_write(APIC_LVT0, APIC_DM_NMI | APIC_LVT_MASKED);
-}
-
-int __init check_nmi_watchdog(void)
-{
-        unsigned int *prev_nmi_count;
-        int cpu;
-
-        if (!nmi_watchdog_active() || !atomic_read(&nmi_active))
-                return 0;
-
-        prev_nmi_count = kmalloc(nr_cpu_ids * sizeof(int), GFP_KERNEL);
-        if (!prev_nmi_count)
-                goto error;
-
-        printk(KERN_INFO "Testing NMI watchdog ... ");
-
-#ifdef CONFIG_SMP
-        if (nmi_watchdog == NMI_LOCAL_APIC)
-                smp_call_function(nmi_cpu_busy, (void *)&endflag, 0);
-#endif
-
-        for_each_possible_cpu(cpu)
-                prev_nmi_count[cpu] = get_nmi_count(cpu);
-        local_irq_enable();
-        mdelay((20 * 1000) / nmi_hz); /* wait 20 ticks */
-
-        for_each_online_cpu(cpu) {
-                if (!per_cpu(wd_enabled, cpu))
-                        continue;
-                if (get_nmi_count(cpu) - prev_nmi_count[cpu] <= 5)
-                        report_broken_nmi(cpu, prev_nmi_count);
-        }
-        endflag = 1;
-        if (!atomic_read(&nmi_active)) {
-                kfree(prev_nmi_count);
-                atomic_set(&nmi_active, -1);
-                goto error;
-        }
-        printk("OK.\n");
-
-        /*
-         * now that we know it works we can reduce NMI frequency to
-         * something more reasonable; makes a difference in some configs
-         */
-        if (nmi_watchdog == NMI_LOCAL_APIC)
-                nmi_hz = lapic_adjust_nmi_hz(1);
-
-        kfree(prev_nmi_count);
-        return 0;
-error:
-        if (nmi_watchdog == NMI_IO_APIC) {
-                if (!timer_through_8259)
-                        legacy_pic->mask(0);
-                on_each_cpu(__acpi_nmi_disable, NULL, 1);
-        }
-
-#ifdef CONFIG_X86_32
-        timer_ack = 0;
-#endif
-        return -1;
-}
-
-static int __init setup_nmi_watchdog(char *str)
-{
-        unsigned int nmi;
-
-        if (!strncmp(str, "panic", 5)) {
-                panic_on_timeout = 1;
-                str = strchr(str, ',');
-                if (!str)
-                        return 1;
-                ++str;
-        }
-
-        if (!strncmp(str, "lapic", 5))
-                nmi_watchdog = NMI_LOCAL_APIC;
-        else if (!strncmp(str, "ioapic", 6))
-                nmi_watchdog = NMI_IO_APIC;
-        else {
-                get_option(&str, &nmi);
-                if (nmi >= NMI_INVALID)
-                        return 0;
-                nmi_watchdog = nmi;
-        }
-
-        return 1;
-}
-__setup("nmi_watchdog=", setup_nmi_watchdog);
-
-/*
- * Suspend/resume support
- */
-#ifdef CONFIG_PM
-
-static int nmi_pm_active; /* nmi_active before suspend */
-
-static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
-{
-        /* only CPU0 goes here, other CPUs should be offline */
-        nmi_pm_active = atomic_read(&nmi_active);
-        stop_apic_nmi_watchdog(NULL);
-        BUG_ON(atomic_read(&nmi_active) != 0);
-        return 0;
-}
-
-static int lapic_nmi_resume(struct sys_device *dev)
-{
-        /* only CPU0 goes here, other CPUs should be offline */
-        if (nmi_pm_active > 0) {
-                setup_apic_nmi_watchdog(NULL);
-                touch_nmi_watchdog();
-        }
-        return 0;
-}
-
-static struct sysdev_class nmi_sysclass = {
-        .name           = "lapic_nmi",
-        .resume         = lapic_nmi_resume,
-        .suspend        = lapic_nmi_suspend,
-};
-
-static struct sys_device device_lapic_nmi = {
-        .id     = 0,
-        .cls    = &nmi_sysclass,
-};
-
-static int __init init_lapic_nmi_sysfs(void)
-{
-        int error;
-
-        /*
-         * should really be a BUG_ON but b/c this is an
-         * init call, it just doesn't work.  -dcz
-         */
-        if (nmi_watchdog != NMI_LOCAL_APIC)
-                return 0;
-
-        if (atomic_read(&nmi_active) < 0)
-                return 0;
-
-        error = sysdev_class_register(&nmi_sysclass);
-        if (!error)
-                error = sysdev_register(&device_lapic_nmi);
-        return error;
-}
-
-/* must come after the local APIC's device_initcall() */
-late_initcall(init_lapic_nmi_sysfs);
-
-#endif  /* CONFIG_PM */
-
-static void __acpi_nmi_enable(void *__unused)
-{
-        apic_write(APIC_LVT0, APIC_DM_NMI);
-}
-
-/*
- * Enable timer based NMIs on all CPUs:
- */
-void acpi_nmi_enable(void)
-{
-        if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
-                on_each_cpu(__acpi_nmi_enable, NULL, 1);
-}
-
-/*
- * Disable timer based NMIs on all CPUs:
- */
-void acpi_nmi_disable(void)
-{
-        if (atomic_read(&nmi_active) && nmi_watchdog == NMI_IO_APIC)
-                on_each_cpu(__acpi_nmi_disable, NULL, 1);
-}
-
-/*
- * This function is called as soon the LAPIC NMI watchdog driver has everything
- * in place and it's ready to check if the NMIs belong to the NMI watchdog
- */
-void cpu_nmi_set_wd_enabled(void)
-{
-        __get_cpu_var(wd_enabled) = 1;
-}
-
-void setup_apic_nmi_watchdog(void *unused)
-{
-        if (__get_cpu_var(wd_enabled))
-                return;
-
-        /* cheap hack to support suspend/resume */
-        /* if cpu0 is not active neither should the other cpus */
-        if (smp_processor_id() != 0 && atomic_read(&nmi_active) <= 0)
-                return;
-
-        switch (nmi_watchdog) {
-        case NMI_LOCAL_APIC:
-                if (lapic_watchdog_init(nmi_hz) < 0) {
-                        __get_cpu_var(wd_enabled) = 0;
-                        return;
-                }
-                /* FALL THROUGH */
-        case NMI_IO_APIC:
-                __get_cpu_var(wd_enabled) = 1;
-                atomic_inc(&nmi_active);
-        }
-}
-
-void stop_apic_nmi_watchdog(void *unused)
-{
-        /* only support LOCAL and IO APICs for now */
-        if (!nmi_watchdog_active())
-                return;
-        if (__get_cpu_var(wd_enabled) == 0)
-                return;
-        if (nmi_watchdog == NMI_LOCAL_APIC)
-                lapic_watchdog_stop();
-        else
-                __acpi_nmi_disable(NULL);
-        __get_cpu_var(wd_enabled) = 0;
-        atomic_dec(&nmi_active);
-}
-
-/*
- * the best way to detect whether a CPU has a 'hard lockup' problem
- * is to check it's local APIC timer IRQ counts. If they are not
- * changing then that CPU has some problem.
- *
- * as these watchdog NMI IRQs are generated on every CPU, we only
- * have to check the current processor.
- *
- * since NMIs don't listen to _any_ locks, we have to be extremely
- * careful not to rely on unsafe variables. The printk might lock
- * up though, so we have to break up any console locks first ...
- * [when there will be more tty-related locks, break them up here too!]
- */
-
-static DEFINE_PER_CPU(unsigned, last_irq_sum);
-static DEFINE_PER_CPU(long, alert_counter);
-static DEFINE_PER_CPU(int, nmi_touch);
-
-void touch_nmi_watchdog(void)
-{
-        if (nmi_watchdog_active()) {
-                unsigned cpu;
-
-                /*
-                 * Tell other CPUs to reset their alert counters. We cannot
-                 * do it ourselves because the alert count increase is not
-                 * atomic.
-                 */
-                for_each_present_cpu(cpu) {
-                        if (per_cpu(nmi_touch, cpu) != 1)
-                                per_cpu(nmi_touch, cpu) = 1;
-                }
-        }
-
-        /*
-         * Tickle the softlockup detector too:
-         */
-        touch_softlockup_watchdog();
-}
-EXPORT_SYMBOL(touch_nmi_watchdog);
-
-notrace __kprobes int
-nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
-{
-        /*
-         * Since current_thread_info()-> is always on the stack, and we
-         * always switch the stack NMI-atomically, it's safe to use
-         * smp_processor_id().
-         */
-        unsigned int sum;
-        int touched = 0;
-        int cpu = smp_processor_id();
-        int rc = 0;
-
-        sum = get_timer_irqs(cpu);
-
-        if (__get_cpu_var(nmi_touch)) {
-                __get_cpu_var(nmi_touch) = 0;
-                touched = 1;
-        }
-
-        /* We can be called before check_nmi_watchdog, hence NULL check. */
-        if (cpumask_test_cpu(cpu, to_cpumask(backtrace_mask))) {
-                static DEFINE_RAW_SPINLOCK(lock); /* Serialise the printks */
-
-                raw_spin_lock(&lock);
-                printk(KERN_WARNING "NMI backtrace for cpu %d\n", cpu);
-                show_regs(regs);
-                dump_stack();
-                raw_spin_unlock(&lock);
-                cpumask_clear_cpu(cpu, to_cpumask(backtrace_mask));
-
-                rc = 1;
-        }
-
-        /* Could check oops_in_progress here too, but it's safer not to */
-        if (mce_in_progress())
-                touched = 1;
-
-        /* if the none of the timers isn't firing, this cpu isn't doing much */
-        if (!touched && __get_cpu_var(last_irq_sum) == sum) {
-                /*
-                 * Ayiee, looks like this CPU is stuck ...
-                 * wait a few IRQs (5 seconds) before doing the oops ...
-                 */
-                __this_cpu_inc(alert_counter);
-                if (__this_cpu_read(alert_counter) == 5 * nmi_hz)
-                        /*
-                         * die_nmi will return ONLY if NOTIFY_STOP happens..
-                         */
-                        die_nmi("BUG: NMI Watchdog detected LOCKUP",
-                                regs, panic_on_timeout);
-        } else {
-                __get_cpu_var(last_irq_sum) = sum;
-                __this_cpu_write(alert_counter, 0);
-        }
-
-        /* see if the nmi watchdog went off */
-        if (!__get_cpu_var(wd_enabled))
-                return rc;
-        switch (nmi_watchdog) {
-        case NMI_LOCAL_APIC:
-                rc |= lapic_wd_event(nmi_hz);
-                break;
-        case NMI_IO_APIC:
-                /*
-                 * don't know how to accurately check for this.
-                 * just assume it was a watchdog timer interrupt
-                 * This matches the old behaviour.
-                 */
-                rc = 1;
-                break;
-        }
-        return rc;
-}
-
-#ifdef CONFIG_SYSCTL
-
-static void enable_ioapic_nmi_watchdog_single(void *unused)
-{
-        __get_cpu_var(wd_enabled) = 1;
-        atomic_inc(&nmi_active);
-        __acpi_nmi_enable(NULL);
-}
-
-static void enable_ioapic_nmi_watchdog(void)
-{
-        on_each_cpu(enable_ioapic_nmi_watchdog_single, NULL, 1);
-        touch_nmi_watchdog();
-}
-
-static void disable_ioapic_nmi_watchdog(void)
-{
-        on_each_cpu(stop_apic_nmi_watchdog, NULL, 1);
-}
-
-static int __init setup_unknown_nmi_panic(char *str)
-{
-        unknown_nmi_panic = 1;
-        return 1;
-}
-__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
-
-static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
-{
-        unsigned char reason = get_nmi_reason();
-        char buf[64];
-
-        sprintf(buf, "NMI received for unknown reason %02x\n", reason);
-        die_nmi(buf, regs, 1); /* Always panic here */
-        return 0;
-}
-
-/*
- * proc handler for /proc/sys/kernel/nmi
- */
-int proc_nmi_enabled(struct ctl_table *table, int write,
-                        void __user *buffer, size_t *length, loff_t *ppos)
-{
-        int old_state;
-
-        nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
-        old_state = nmi_watchdog_enabled;
-        proc_dointvec(table, write, buffer, length, ppos);
-        if (!!old_state == !!nmi_watchdog_enabled)
-                return 0;
-
-        if (atomic_read(&nmi_active) < 0 || !nmi_watchdog_active()) {
-                printk(KERN_WARNING
-                        "NMI watchdog is permanently disabled\n");
-                return -EIO;
-        }
-
-        if (nmi_watchdog == NMI_LOCAL_APIC) {
-                if (nmi_watchdog_enabled)
-                        enable_lapic_nmi_watchdog();
-                else
-                        disable_lapic_nmi_watchdog();
-        } else if (nmi_watchdog == NMI_IO_APIC) {
-                if (nmi_watchdog_enabled)
-                        enable_ioapic_nmi_watchdog();
-                else
-                        disable_ioapic_nmi_watchdog();
-        } else {
-                printk(KERN_WARNING
-                        "NMI watchdog doesn't know what hardware to touch\n");
-                return -EIO;
-        }
-        return 0;
-}
-
-#endif /* CONFIG_SYSCTL */
-
-int do_nmi_callback(struct pt_regs *regs, int cpu)
-{
-#ifdef CONFIG_SYSCTL
-        if (unknown_nmi_panic)
-                return unknown_nmi_panic_callback(regs, cpu);
-#endif
-        return 0;
-}
-
-void arch_trigger_all_cpu_backtrace(void)
-{
-        int i;
-
-        cpumask_copy(to_cpumask(backtrace_mask), cpu_online_mask);
-
-        printk(KERN_INFO "sending NMI to all CPUs:\n");
-        apic->send_IPI_all(NMI_VECTOR);
-
-        /* Wait for up to 10 seconds for all CPUs to do the backtrace */
-        for (i = 0; i < 10 * 1000; i++) {
-                if (cpumask_empty(to_cpumask(backtrace_mask)))
-                        break;
-                mdelay(1);
-        }
-}
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index c1c52c341f40..bd16b58b8850 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -48,6 +48,16 @@ unsigned int uv_apicid_hibits;
 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
 static DEFINE_SPINLOCK(uv_nmi_lock);
 
+static unsigned long __init uv_early_read_mmr(unsigned long addr)
+{
+        unsigned long val, *mmr;
+
+        mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
+        val = *mmr;
+        early_iounmap(mmr, sizeof(*mmr));
+        return val;
+}
+
 static inline bool is_GRU_range(u64 start, u64 end)
 {
         return start >= gru_start_paddr && end <= gru_end_paddr;
@@ -58,28 +68,24 @@ static bool uv_is_untracked_pat_range(u64 start, u64 end)
         return is_ISA_range(start, end) || is_GRU_range(start, end);
 }
 
-static int early_get_nodeid(void)
+static int __init early_get_pnodeid(void)
 {
         union uvh_node_id_u node_id;
-        unsigned long *mmr;
-
-        mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
-        node_id.v = *mmr;
-        early_iounmap(mmr, sizeof(*mmr));
+        union uvh_rh_gam_config_mmr_u  m_n_config;
+        int pnode;
 
         /* Currently, all blades have same revision number */
+        node_id.v = uv_early_read_mmr(UVH_NODE_ID);
+        m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
         uv_min_hub_revision_id = node_id.s.revision;
 
-        return node_id.s.node_id;
+        pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
+        return pnode;
 }
 
 static void __init early_get_apic_pnode_shift(void)
 {
-        unsigned long *mmr;
-
-        mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_APICID, sizeof(*mmr));
-        uvh_apicid.v = *mmr;
-        early_iounmap(mmr, sizeof(*mmr));
+        uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
         if (!uvh_apicid.v)
                 /*
                  * Old bios, use default value
@@ -95,21 +101,17 @@ static void __init early_get_apic_pnode_shift(void)
 static void __init uv_set_apicid_hibit(void)
 {
         union uvh_lb_target_physical_apic_id_mask_u apicid_mask;
-        unsigned long *mmr;
 
-        mmr = early_ioremap(UV_LOCAL_MMR_BASE |
-                UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK, sizeof(*mmr));
-        apicid_mask.v = *mmr;
-        early_iounmap(mmr, sizeof(*mmr));
+        apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK);
         uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;
 }
 
 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
-        int nodeid;
+        int pnodeid;
 
         if (!strcmp(oem_id, "SGI")) {
-                nodeid = early_get_nodeid();
+                pnodeid = early_get_pnodeid();
                 early_get_apic_pnode_shift();
                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
                 x86_platform.nmi_init = uv_nmi_init;
@@ -118,8 +120,8 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
                 else if (!strcmp(oem_table_id, "UVX"))
                         uv_system_type = UV_X2APIC;
                 else if (!strcmp(oem_table_id, "UVH")) {
-                        __get_cpu_var(x2apic_extra_bits) =
-                                nodeid << (uvh_apicid.s.pnode_shift - 1);
+                        __this_cpu_write(x2apic_extra_bits,
+                                pnodeid << uvh_apicid.s.pnode_shift);
                         uv_system_type = UV_NON_UNIQUE_APIC;
                         uv_set_apicid_hibit();
                         return 1;
@@ -284,7 +286,7 @@ static unsigned int x2apic_get_apic_id(unsigned long x)
         unsigned int id;
 
         WARN_ON(preemptible() && num_online_cpus() > 1);
-        id = x | __get_cpu_var(x2apic_extra_bits);
+        id = x | __this_cpu_read(x2apic_extra_bits);
 
         return id;
 }
@@ -376,7 +378,7 @@ struct apic __refdata apic_x2apic_uv_x = {
 
 static __cpuinit void set_x2apic_extra_bits(int pnode)
 {
-        __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
+        __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 }
 
 /*
@@ -639,7 +641,7 @@ void __cpuinit uv_cpu_init(void)
  */
 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
 {
-        if (reason != DIE_NMI_IPI)
+        if (reason != DIE_NMIUNKNOWN)
                 return NOTIFY_OK;
 
         if (in_crash_kexec)
@@ -682,27 +684,32 @@ void uv_nmi_init(void)
 void __init uv_system_init(void)
 {
         union uvh_rh_gam_config_mmr_u  m_n_config;
+        union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
         union uvh_node_id_u node_id;
         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
-        int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
+        int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
         int gnode_extra, max_pnode = 0;
         unsigned long mmr_base, present, paddr;
-        unsigned short pnode_mask;
+        unsigned short pnode_mask, pnode_io_mask;
 
         map_low_mmrs();
 
         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
         m_val = m_n_config.s.m_skt;
         n_val = m_n_config.s.n_skt;
+        mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
+        n_io = mmioh.s.n_io;
         mmr_base =
             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
             ~UV_MMR_ENABLE;
         pnode_mask = (1 << n_val) - 1;
+        pnode_io_mask = (1 << n_io) - 1;
+
         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
         gnode_upper = ((unsigned long)gnode_extra  << m_val);
-        printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
-                        n_val, m_val, gnode_upper, gnode_extra);
+        printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
+                        n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
 
         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 
@@ -735,7 +742,7 @@ void __init uv_system_init(void)
                 for (j = 0; j < 64; j++) {
                         if (!test_bit(j, &present))
                                 continue;
-                        pnode = (i * 64 + j);
+                        pnode = (i * 64 + j) & pnode_mask;
                         uv_blade_info[blade].pnode = pnode;
                         uv_blade_info[blade].nr_possible_cpus = 0;
                         uv_blade_info[blade].nr_online_cpus = 0;
@@ -756,6 +763,7 @@ void __init uv_system_init(void)
                 /*
                  * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
                  */
+                uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
                 pnode = uv_apicid_to_pnode(apicid);
                 blade = boot_pnode_to_blade(pnode);
@@ -772,7 +780,6 @@ void __init uv_system_init(void)
                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
                 uv_cpu_hub_info(cpu)->pnode = pnode;
-                uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
@@ -796,7 +803,7 @@ void __init uv_system_init(void)
 
         map_gru_high(max_pnode);
         map_mmr_high(max_pnode);
-        map_mmioh_high(max_pnode);
+        map_mmioh_high(max_pnode & pnode_io_mask);
 
         uv_cpu_init();
         uv_scir_register_cpu_notifier();
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 9e093f8fe78c..7c7bedb83c5a 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -668,7 +668,7 @@ EXPORT_SYMBOL_GPL(amd_erratum_383);
 
 bool cpu_has_amd_erratum(const int *erratum)
 {
-        struct cpuinfo_x86 *cpu = &current_cpu_data;
+        struct cpuinfo_x86 *cpu = __this_cpu_ptr(&cpu_info);
         int osvw_id = *erratum++;
         u32 range;
         u32 ms;
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 4b68bda30938..1d59834396bd 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -894,7 +894,6 @@ void __init identify_boot_cpu(void)
 #else
         vgetcpu_set_mode();
 #endif
-        init_hw_perf_events();
 }
 
 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 491977baf6c0..35c7e65e59be 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -521,7 +521,7 @@ static void check_supported_cpu(void *_rc)
 
         *rc = -ENODEV;
 
-        if (current_cpu_data.x86_vendor != X86_VENDOR_AMD)
+        if (__this_cpu_read(cpu_info.x86_vendor) != X86_VENDOR_AMD)
                 return;
 
         eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
@@ -1377,7 +1377,7 @@ static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol)
 static void query_values_on_cpu(void *_err)
 {
         int *err = _err;
-        struct powernow_k8_data *data = __get_cpu_var(powernow_data);
+        struct powernow_k8_data *data = __this_cpu_read(powernow_data);
 
         *err = query_current_values_with_pending_wait(data);
 }
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 17ad03366211..7283e98deaae 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -149,8 +149,7 @@ union _cpuid4_leaf_ecx {
 };
 
 struct amd_l3_cache {
-        struct   pci_dev *dev;
-        bool     can_disable;
+        struct   amd_northbridge *nb;
         unsigned indices;
         u8       subcaches[4];
 };
@@ -266,7 +265,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
                 line_size = l2.line_size;
                 lines_per_tag = l2.lines_per_tag;
                 /* cpu_data has errata corrections for K7 applied */
-                size_in_kb = current_cpu_data.x86_cache_size;
+                size_in_kb = __this_cpu_read(cpu_info.x86_cache_size);
                 break;
         case 3:
                 if (!l3.val)
@@ -288,7 +287,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
         eax->split.type = types[leaf];
         eax->split.level = levels[leaf];
         eax->split.num_threads_sharing = 0;
-        eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
+        eax->split.num_cores_on_die = __this_cpu_read(cpu_info.x86_max_cores) - 1;
 
 
         if (assoc == 0xffff)
@@ -311,14 +310,12 @@ struct _cache_attr {
 /*
  * L3 cache descriptors
  */
-static struct amd_l3_cache **__cpuinitdata l3_caches;
-
 static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3)
 {
         unsigned int sc0, sc1, sc2, sc3;
         u32 val = 0;
 
-        pci_read_config_dword(l3->dev, 0x1C4, &val);
+        pci_read_config_dword(l3->nb->misc, 0x1C4, &val);
 
         /* calculate subcache sizes */
         l3->subcaches[0] = sc0 = !(val & BIT(0));
@@ -330,47 +327,14 @@ static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3)
         l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
 }
 
-static struct amd_l3_cache * __cpuinit amd_init_l3_cache(int node)
-{
-        struct amd_l3_cache *l3;
-        struct pci_dev *dev = node_to_k8_nb_misc(node);
-
-        l3 = kzalloc(sizeof(struct amd_l3_cache), GFP_ATOMIC);
-        if (!l3) {
-                printk(KERN_WARNING "Error allocating L3 struct\n");
-                return NULL;
-        }
-
-        l3->dev = dev;
-
-        amd_calc_l3_indices(l3);
-
-        return l3;
-}
-
-static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf,
-                                           int index)
+static void __cpuinit amd_init_l3_cache(struct _cpuid4_info_regs *this_leaf,
+                                        int index)
 {
+        static struct amd_l3_cache *__cpuinitdata l3_caches;
         int node;
 
-        if (boot_cpu_data.x86 != 0x10)
-                return;
-
-        if (index < 3)
-                return;
-
-        /* see errata #382 and #388 */
-        if (boot_cpu_data.x86_model < 0x8)
-                return;
-
-        if ((boot_cpu_data.x86_model == 0x8 ||
-             boot_cpu_data.x86_model == 0x9)
-                &&
-             boot_cpu_data.x86_mask < 0x1)
-                        return;
-
-        /* not in virtualized environments */
-        if (k8_northbridges.num == 0)
+        /* only for L3, and not in virtualized environments */
+        if (index < 3 || amd_nb_num() == 0)
                 return;
 
         /*
@@ -378,7 +342,7 @@ static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf,
          * never freed but this is done only on shutdown so it doesn't matter.
          */
         if (!l3_caches) {
-                int size = k8_northbridges.num * sizeof(struct amd_l3_cache *);
+                int size = amd_nb_num() * sizeof(struct amd_l3_cache);
 
                 l3_caches = kzalloc(size, GFP_ATOMIC);
                 if (!l3_caches)
@@ -387,14 +351,12 @@ static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf,
 
         node = amd_get_nb_id(smp_processor_id());
 
-        if (!l3_caches[node]) {
-                l3_caches[node] = amd_init_l3_cache(node);
-                l3_caches[node]->can_disable = true;
+        if (!l3_caches[node].nb) {
+                l3_caches[node].nb = node_to_amd_nb(node);
+                amd_calc_l3_indices(&l3_caches[node]);
         }
 
-        WARN_ON(!l3_caches[node]);
-
-        this_leaf->l3 = l3_caches[node];
+        this_leaf->l3 = &l3_caches[node];
 }
 
 /*
@@ -408,7 +370,7 @@ int amd_get_l3_disable_slot(struct amd_l3_cache *l3, unsigned slot)
 {
         unsigned int reg = 0;
 
-        pci_read_config_dword(l3->dev, 0x1BC + slot * 4, &reg);
+        pci_read_config_dword(l3->nb->misc, 0x1BC + slot * 4, &reg);
 
         /* check whether this slot is activated already */
         if (reg & (3UL << 30))
@@ -422,7 +384,8 @@ static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
 {
         int index;
 
-        if (!this_leaf->l3 || !this_leaf->l3->can_disable)
+        if (!this_leaf->l3 ||
+            !amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
                 return -EINVAL;
 
         index = amd_get_l3_disable_slot(this_leaf->l3, slot);
@@ -457,7 +420,7 @@ static void amd_l3_disable_index(struct amd_l3_cache *l3, int cpu,
                 if (!l3->subcaches[i])
                         continue;
 
-                pci_write_config_dword(l3->dev, 0x1BC + slot * 4, reg);
+                pci_write_config_dword(l3->nb->misc, 0x1BC + slot * 4, reg);
 
                 /*
                  * We need to WBINVD on a core on the node containing the L3
@@ -467,7 +430,7 @@ static void amd_l3_disable_index(struct amd_l3_cache *l3, int cpu,
                 wbinvd_on_cpu(cpu);
 
                 reg |= BIT(31);
-                pci_write_config_dword(l3->dev, 0x1BC + slot * 4, reg);
+                pci_write_config_dword(l3->nb->misc, 0x1BC + slot * 4, reg);
         }
 }
 
@@ -524,7 +487,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
         if (!capable(CAP_SYS_ADMIN))
                 return -EPERM;
 
-        if (!this_leaf->l3 || !this_leaf->l3->can_disable)
+        if (!this_leaf->l3 ||
+            !amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
                 return -EINVAL;
 
         cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
@@ -545,7 +509,7 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
 #define STORE_CACHE_DISABLE(slot)                                       \
 static ssize_t                                                          \
 store_cache_disable_##slot(struct _cpuid4_info *this_leaf,              \
-                            const char *buf, size_t count)              \
+                           const char *buf, size_t count)               \
 {                                                                       \
         return store_cache_disable(this_leaf, buf, count, slot);        \
 }
@@ -558,10 +522,7 @@ static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
                 show_cache_disable_1, store_cache_disable_1);
 
 #else   /* CONFIG_AMD_NB */
-static void __cpuinit
-amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, int index)
-{
-};
+#define amd_init_l3_cache(x, y)
 #endif /* CONFIG_AMD_NB */
 
 static int
@@ -575,7 +536,7 @@ __cpuinit cpuid4_cache_lookup_regs(int index,
 
         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
                 amd_cpuid4(index, &eax, &ebx, &ecx);
-                amd_check_l3_disable(this_leaf, index);
+                amd_init_l3_cache(this_leaf, index);
         } else {
                 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
         }
@@ -983,30 +944,48 @@ define_one_ro(size);
 define_one_ro(shared_cpu_map);
 define_one_ro(shared_cpu_list);
 
-#define DEFAULT_SYSFS_CACHE_ATTRS       \
-        &type.attr,                     \
-        &level.attr,                    \
-        &coherency_line_size.attr,      \
-        &physical_line_partition.attr,  \
-        &ways_of_associativity.attr,    \
-        &number_of_sets.attr,           \
-        &size.attr,                     \
-        &shared_cpu_map.attr,           \
-        &shared_cpu_list.attr
-
 static struct attribute *default_attrs[] = {
-        DEFAULT_SYSFS_CACHE_ATTRS,
+        &type.attr,
+        &level.attr,
+        &coherency_line_size.attr,
+        &physical_line_partition.attr,
+        &ways_of_associativity.attr,
+        &number_of_sets.attr,
+        &size.attr,
+        &shared_cpu_map.attr,
+        &shared_cpu_list.attr,
         NULL
 };
 
-static struct attribute *default_l3_attrs[] = {
-        DEFAULT_SYSFS_CACHE_ATTRS,
 #ifdef CONFIG_AMD_NB
-        &cache_disable_0.attr,
-        &cache_disable_1.attr,
+static struct attribute ** __cpuinit amd_l3_attrs(void)
+{
+        static struct attribute **attrs;
+        int n;
+
+        if (attrs)
+                return attrs;
+
+        n = sizeof (default_attrs) / sizeof (struct attribute *);
+
+        if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE))
+                n += 2;
+
+        attrs = kzalloc(n * sizeof (struct attribute *), GFP_KERNEL);
+        if (attrs == NULL)
+                return attrs = default_attrs;
+
+        for (n = 0; default_attrs[n]; n++)
+                attrs[n] = default_attrs[n];
+
+        if (amd_nb_has_feature(AMD_NB_L3_INDEX_DISABLE)) {
+                attrs[n++] = &cache_disable_0.attr;
+                attrs[n++] = &cache_disable_1.attr;
+        }
+
+        return attrs;
+}
 #endif
-        NULL
-};
 
 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
 {
@@ -1117,11 +1096,11 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
 
                 this_leaf = CPUID4_INFO_IDX(cpu, i);
 
-                if (this_leaf->l3 && this_leaf->l3->can_disable)
-                        ktype_cache.default_attrs = default_l3_attrs;
-                else
-                        ktype_cache.default_attrs = default_attrs;
-
+                ktype_cache.default_attrs = default_attrs;
+#ifdef CONFIG_AMD_NB
+                if (this_leaf->l3)
+                        ktype_cache.default_attrs = amd_l3_attrs();
+#endif
                 retval = kobject_init_and_add(&(this_object->kobj),
                                               &ktype_cache,
                                               per_cpu(ici_cache_kobject, cpu),
diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index e7dbde7bfedb..a77971979564 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -25,6 +25,7 @@
 #include <linux/gfp.h>
 #include <asm/mce.h>
 #include <asm/apic.h>
+#include <asm/nmi.h>
 
 /* Update fake mce registers on current CPU. */
 static void inject_mce(struct mce *m)
@@ -83,7 +84,7 @@ static int mce_raise_notify(struct notifier_block *self,
         struct die_args *args = (struct die_args *)data;
         int cpu = smp_processor_id();
         struct mce *m = &__get_cpu_var(injectm);
-        if (val != DIE_NMI_IPI || !cpumask_test_cpu(cpu, mce_inject_cpumask))
+        if (val != DIE_NMI || !cpumask_test_cpu(cpu, mce_inject_cpumask))
                 return NOTIFY_DONE;
         cpumask_clear_cpu(cpu, mce_inject_cpumask);
         if (m->inject_flags & MCJ_EXCEPTION)
@@ -95,7 +96,7 @@ static int mce_raise_notify(struct notifier_block *self,
 
 static struct notifier_block mce_raise_nb = {
         .notifier_call = mce_raise_notify,
-        .priority = 1000,
+        .priority = NMI_LOCAL_NORMAL_PRIOR,
 };
 
 /* Inject mce on current CPU */
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 7a35b72d7c03..d916183b7f9c 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -326,7 +326,7 @@ static void mce_panic(char *msg, struct mce *final, char *exp)
 
 static int msr_to_offset(u32 msr)
 {
-        unsigned bank = __get_cpu_var(injectm.bank);
+        unsigned bank = __this_cpu_read(injectm.bank);
 
         if (msr == rip_msr)
                 return offsetof(struct mce, ip);
@@ -346,7 +346,7 @@ static u64 mce_rdmsrl(u32 msr)
 {
         u64 v;
 
-        if (__get_cpu_var(injectm).finished) {
+        if (__this_cpu_read(injectm.finished)) {
                 int offset = msr_to_offset(msr);
 
                 if (offset < 0)
@@ -369,7 +369,7 @@ static u64 mce_rdmsrl(u32 msr)
 
 static void mce_wrmsrl(u32 msr, u64 v)
 {
-        if (__get_cpu_var(injectm).finished) {
+        if (__this_cpu_read(injectm.finished)) {
                 int offset = msr_to_offset(msr);
 
                 if (offset >= 0)
@@ -1159,7 +1159,7 @@ static void mce_start_timer(unsigned long data)
 
         WARN_ON(smp_processor_id() != data);
 
-        if (mce_available(&current_cpu_data)) {
+        if (mce_available(__this_cpu_ptr(&cpu_info))) {
                 machine_check_poll(MCP_TIMESTAMP,
                                 &__get_cpu_var(mce_poll_banks));
         }
@@ -1767,7 +1767,7 @@ static int mce_shutdown(struct sys_device *dev)
 static int mce_resume(struct sys_device *dev)
 {
         __mcheck_cpu_init_generic();
-        __mcheck_cpu_init_vendor(&current_cpu_data);
+        __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
 
         return 0;
 }
@@ -1775,7 +1775,7 @@ static int mce_resume(struct sys_device *dev)
 static void mce_cpu_restart(void *data)
 {
         del_timer_sync(&__get_cpu_var(mce_timer));
-        if (!mce_available(&current_cpu_data))
+        if (!mce_available(__this_cpu_ptr(&cpu_info)))
                 return;
         __mcheck_cpu_init_generic();
         __mcheck_cpu_init_timer();
@@ -1790,7 +1790,7 @@ static void mce_restart(void)
 /* Toggle features for corrected errors */
 static void mce_disable_ce(void *all)
 {
-        if (!mce_available(&current_cpu_data))
+        if (!mce_available(__this_cpu_ptr(&cpu_info)))
                 return;
         if (all)
                 del_timer_sync(&__get_cpu_var(mce_timer));
@@ -1799,7 +1799,7 @@ static void mce_disable_ce(void *all)
 
 static void mce_enable_ce(void *all)
 {
-        if (!mce_available(&current_cpu_data))
+        if (!mce_available(__this_cpu_ptr(&cpu_info)))
                 return;
         cmci_reenable();
         cmci_recheck();
@@ -2022,7 +2022,7 @@ static void __cpuinit mce_disable_cpu(void *h)
         unsigned long action = *(unsigned long *)h;
         int i;
 
-        if (!mce_available(&current_cpu_data))
+        if (!mce_available(__this_cpu_ptr(&cpu_info)))
                 return;
 
         if (!(action & CPU_TASKS_FROZEN))
@@ -2040,7 +2040,7 @@ static void __cpuinit mce_reenable_cpu(void *h)
         unsigned long action = *(unsigned long *)h;
         int i;
 
-        if (!mce_available(&current_cpu_data))
+        if (!mce_available(__this_cpu_ptr(&cpu_info)))
                 return;
 
         if (!(action & CPU_TASKS_FROZEN))
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 80c482382d5c..5bf2fac52aca 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -31,8 +31,6 @@
 #include <asm/mce.h>
 #include <asm/msr.h>
 
-#define PFX               "mce_threshold: "
-#define VERSION           "version 1.1.1"
 #define NR_BANKS          6
 #define NR_BLOCKS         9
 #define THRESHOLD_MAX     0xFFF
@@ -59,12 +57,6 @@ struct threshold_block {
         struct list_head        miscj;
 };
 
-/* defaults used early on boot */
-static struct threshold_block threshold_defaults = {
-        .interrupt_enable       = 0,
-        .threshold_limit        = THRESHOLD_MAX,
-};
-
 struct threshold_bank {
         struct kobject          *kobj;
         struct threshold_block  *blocks;
@@ -89,50 +81,101 @@ static void amd_threshold_interrupt(void);
 struct thresh_restart {
         struct threshold_block  *b;
         int                     reset;
+        int                     set_lvt_off;
+        int                     lvt_off;
         u16                     old_limit;
 };
 
+static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
+{
+        int msr = (hi & MASK_LVTOFF_HI) >> 20;
+
+        if (apic < 0) {
+                pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
+                       "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
+                       b->bank, b->block, b->address, hi, lo);
+                return 0;
+        }
+
+        if (apic != msr) {
+                pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
+                       "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
+                       b->cpu, apic, b->bank, b->block, b->address, hi, lo);
+                return 0;
+        }
+
+        return 1;
+};
+
 /* must be called with correct cpu affinity */
 /* Called via smp_call_function_single() */
 static void threshold_restart_bank(void *_tr)
 {
         struct thresh_restart *tr = _tr;
-        u32 mci_misc_hi, mci_misc_lo;
+        u32 hi, lo;
 
-        rdmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
+        rdmsr(tr->b->address, lo, hi);
 
-        if (tr->b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
+        if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
                 tr->reset = 1;  /* limit cannot be lower than err count */
 
         if (tr->reset) {                /* reset err count and overflow bit */
-                mci_misc_hi =
-                    (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
+                hi =
+                    (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
                     (THRESHOLD_MAX - tr->b->threshold_limit);
         } else if (tr->old_limit) {     /* change limit w/o reset */
-                int new_count = (mci_misc_hi & THRESHOLD_MAX) +
+                int new_count = (hi & THRESHOLD_MAX) +
                     (tr->old_limit - tr->b->threshold_limit);
 
-                mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
+                hi = (hi & ~MASK_ERR_COUNT_HI) |
                     (new_count & THRESHOLD_MAX);
         }
 
+        if (tr->set_lvt_off) {
+                if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
+                        /* set new lvt offset */
+                        hi &= ~MASK_LVTOFF_HI;
+                        hi |= tr->lvt_off << 20;
+                }
+        }
+
         tr->b->interrupt_enable ?
-            (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
-            (mci_misc_hi &= ~MASK_INT_TYPE_HI);
+            (hi = (hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
+            (hi &= ~MASK_INT_TYPE_HI);
 
-        mci_misc_hi |= MASK_COUNT_EN_HI;
-        wrmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
+        hi |= MASK_COUNT_EN_HI;
+        wrmsr(tr->b->address, lo, hi);
+}
+
+static void mce_threshold_block_init(struct threshold_block *b, int offset)
+{
+        struct thresh_restart tr = {
+                .b                      = b,
+                .set_lvt_off            = 1,
+                .lvt_off                = offset,
+        };
+
+        b->threshold_limit              = THRESHOLD_MAX;
+        threshold_restart_bank(&tr);
+};
+
+static int setup_APIC_mce(int reserved, int new)
+{
+        if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
+                                              APIC_EILVT_MSG_FIX, 0))
+                return new;
+
+        return reserved;
 }
 
 /* cpu init entry point, called from mce.c with preempt off */
 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 {
+        struct threshold_block b;
         unsigned int cpu = smp_processor_id();
         u32 low = 0, high = 0, address = 0;
         unsigned int bank, block;
-        struct thresh_restart tr;
-        int lvt_off = -1;
-        u8 offset;
+        int offset = -1;
 
         for (bank = 0; bank < NR_BANKS; ++bank) {
                 for (block = 0; block < NR_BLOCKS; ++block) {
@@ -163,39 +206,16 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
                         if (shared_bank[bank] && c->cpu_core_id)
                                 break;
 #endif
-                        offset = (high & MASK_LVTOFF_HI) >> 20;
-                        if (lvt_off < 0) {
-                                if (setup_APIC_eilvt(offset,
-                                                     THRESHOLD_APIC_VECTOR,
-                                                     APIC_EILVT_MSG_FIX, 0)) {
-                                        pr_err(FW_BUG "cpu %d, failed to "
-                                               "setup threshold interrupt "
-                                               "for bank %d, block %d "
-                                               "(MSR%08X=0x%x%08x)",
-                                               smp_processor_id(), bank, block,
-                                               address, high, low);
-                                        continue;
-                                }
-                                lvt_off = offset;
-                        } else if (lvt_off != offset) {
-                                pr_err(FW_BUG "cpu %d, invalid threshold "
-                                       "interrupt offset %d for bank %d,"
-                                       "block %d (MSR%08X=0x%x%08x)",
-                                       smp_processor_id(), lvt_off, bank,
-                                       block, address, high, low);
-                                continue;
-                        }
-
-                        high &= ~MASK_LVTOFF_HI;
-                        high |= lvt_off << 20;
-                        wrmsr(address, low, high);
+                        offset = setup_APIC_mce(offset,
+                                                (high & MASK_LVTOFF_HI) >> 20);
 
-                        threshold_defaults.address = address;
-                        tr.b = &threshold_defaults;
-                        tr.reset = 0;
-                        tr.old_limit = 0;
-                        threshold_restart_bank(&tr);
+                        memset(&b, 0, sizeof(b));
+                        b.cpu           = cpu;
+                        b.bank          = bank;
+                        b.block         = block;
+                        b.address       = address;
 
+                        mce_threshold_block_init(&b, offset);
                         mce_threshold_vector = amd_threshold_interrupt;
                 }
         }
@@ -298,9 +318,8 @@ store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
 
         b->interrupt_enable = !!new;
 
+        memset(&tr, 0, sizeof(tr));
         tr.b            = b;
-        tr.reset        = 0;
-        tr.old_limit    = 0;
 
         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 
@@ -321,10 +340,10 @@ store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
         if (new < 1)
                 new = 1;
 
+        memset(&tr, 0, sizeof(tr));
         tr.old_limit = b->threshold_limit;
         b->threshold_limit = new;
         tr.b = b;
-        tr.reset = 0;
 
         smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
 
@@ -603,9 +622,9 @@ static __cpuinit int threshold_create_device(unsigned int cpu)
                         continue;
                 err = threshold_create_bank(cpu, bank);
                 if (err)
-                        goto out;
+                        return err;
         }
-out:
+
         return err;
 }
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 6fcd0936194f..8694ef56459d 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -130,7 +130,7 @@ void cmci_recheck(void)
         unsigned long flags;
         int banks;
 
-        if (!mce_available(&current_cpu_data) || !cmci_supported(&banks))
+        if (!mce_available(__this_cpu_ptr(&cpu_info)) || !cmci_supported(&banks))
                 return;
         local_irq_save(flags);
         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index 4b683267eca5..e12246ff5aa6 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -53,8 +53,13 @@ struct thermal_state {
         struct _thermal_state core_power_limit;
         struct _thermal_state package_throttle;
         struct _thermal_state package_power_limit;
+        struct _thermal_state core_thresh0;
+        struct _thermal_state core_thresh1;
 };
 
+/* Callback to handle core threshold interrupts */
+int (*platform_thermal_notify)(__u64 msr_val);
+
 static DEFINE_PER_CPU(struct thermal_state, thermal_state);
 
 static atomic_t therm_throt_en  = ATOMIC_INIT(0);
@@ -200,6 +205,22 @@ static int therm_throt_process(bool new_event, int event, int level)
         return 0;
 }
 
+static int thresh_event_valid(int event)
+{
+        struct _thermal_state *state;
+        unsigned int this_cpu = smp_processor_id();
+        struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
+        u64 now = get_jiffies_64();
+
+        state = (event == 0) ? &pstate->core_thresh0 : &pstate->core_thresh1;
+
+        if (time_before64(now, state->next_check))
+                return 0;
+
+        state->next_check = now + CHECK_INTERVAL;
+        return 1;
+}
+
 #ifdef CONFIG_SYSFS
 /* Add/Remove thermal_throttle interface for CPU device: */
 static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev,
@@ -313,6 +334,22 @@ device_initcall(thermal_throttle_init_device);
 #define PACKAGE_THROTTLED       ((__u64)2 << 62)
 #define PACKAGE_POWER_LIMIT     ((__u64)3 << 62)
 
+static void notify_thresholds(__u64 msr_val)
+{
+        /* check whether the interrupt handler is defined;
+         * otherwise simply return
+         */
+        if (!platform_thermal_notify)
+                return;
+
+        /* lower threshold reached */
+        if ((msr_val & THERM_LOG_THRESHOLD0) && thresh_event_valid(0))
+                platform_thermal_notify(msr_val);
+        /* higher threshold reached */
+        if ((msr_val & THERM_LOG_THRESHOLD1) && thresh_event_valid(1))
+                platform_thermal_notify(msr_val);
+}
+
 /* Thermal transition interrupt handler */
 static void intel_thermal_interrupt(void)
 {
@@ -321,6 +358,9 @@ static void intel_thermal_interrupt(void)
 
         rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
 
+        /* Check for violation of core thermal thresholds*/
+        notify_thresholds(msr_val);
+
         if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
                                 THERMAL_THROTTLING_EVENT,
                                 CORE_LEVEL) != 0)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 6d75b9145b13..9d977a2ea693 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -330,9 +330,6 @@ static bool reserve_pmc_hardware(void)
 {
         int i;
 
-        if (nmi_watchdog == NMI_LOCAL_APIC)
-                disable_lapic_nmi_watchdog();
-
         for (i = 0; i < x86_pmu.num_counters; i++) {
                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
                         goto perfctr_fail;
@@ -355,9 +352,6 @@ perfctr_fail:
         for (i--; i >= 0; i--)
                 release_perfctr_nmi(x86_pmu.perfctr + i);
 
-        if (nmi_watchdog == NMI_LOCAL_APIC)
-                enable_lapic_nmi_watchdog();
-
         return false;
 }
 
@@ -369,9 +363,6 @@ static void release_pmc_hardware(void)
                 release_perfctr_nmi(x86_pmu.perfctr + i);
                 release_evntsel_nmi(x86_pmu.eventsel + i);
         }
-
-        if (nmi_watchdog == NMI_LOCAL_APIC)
-                enable_lapic_nmi_watchdog();
 }
 
 #else
@@ -384,15 +375,53 @@ static void release_pmc_hardware(void) {}
 static bool check_hw_exists(void)
 {
         u64 val, val_new = 0;
-        int ret = 0;
+        int i, reg, ret = 0;
+
+        /*
+         * Check to see if the BIOS enabled any of the counters, if so
+         * complain and bail.
+         */
+        for (i = 0; i < x86_pmu.num_counters; i++) {
+                reg = x86_pmu.eventsel + i;
+                ret = rdmsrl_safe(reg, &val);
+                if (ret)
+                        goto msr_fail;
+                if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
+                        goto bios_fail;
+        }
 
+        if (x86_pmu.num_counters_fixed) {
+                reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
+                ret = rdmsrl_safe(reg, &val);
+                if (ret)
+                        goto msr_fail;
+                for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
+                        if (val & (0x03 << i*4))
+                                goto bios_fail;
+                }
+        }
+
+        /*
+         * Now write a value and read it back to see if it matches,
+         * this is needed to detect certain hardware emulators (qemu/kvm)
+         * that don't trap on the MSR access and always return 0s.
+         */
         val = 0xabcdUL;
-        ret |= checking_wrmsrl(x86_pmu.perfctr, val);
+        ret = checking_wrmsrl(x86_pmu.perfctr, val);
         ret |= rdmsrl_safe(x86_pmu.perfctr, &val_new);
         if (ret || val != val_new)
-                return false;
+                goto msr_fail;
 
         return true;
+
+bios_fail:
+        printk(KERN_CONT "Broken BIOS detected, using software events only.\n");
+        printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
+        return false;
+
+msr_fail:
+        printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
+        return false;
 }
 
 static void reserve_ds_buffers(void);
@@ -451,7 +480,7 @@ static int x86_setup_perfctr(struct perf_event *event)
         struct hw_perf_event *hwc = &event->hw;
         u64 config;
 
-        if (!hwc->sample_period) {
+        if (!is_sampling_event(event)) {
                 hwc->sample_period = x86_pmu.max_period;
                 hwc->last_period = hwc->sample_period;
                 local64_set(&hwc->period_left, hwc->sample_period);
@@ -968,8 +997,7 @@ x86_perf_event_set_period(struct perf_event *event)
 
 static void x86_pmu_enable_event(struct perf_event *event)
 {
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        if (cpuc->enabled)
+        if (__this_cpu_read(cpu_hw_events.enabled))
                 __x86_pmu_enable_event(&event->hw,
                                        ARCH_PERFMON_EVENTSEL_ENABLE);
 }
@@ -1239,11 +1267,10 @@ perf_event_nmi_handler(struct notifier_block *self,
 
         switch (cmd) {
         case DIE_NMI:
-        case DIE_NMI_IPI:
                 break;
         case DIE_NMIUNKNOWN:
                 this_nmi = percpu_read(irq_stat.__nmi_count);
-                if (this_nmi != __get_cpu_var(pmu_nmi).marked)
+                if (this_nmi != __this_cpu_read(pmu_nmi.marked))
                         /* let the kernel handle the unknown nmi */
                         return NOTIFY_DONE;
                 /*
@@ -1267,8 +1294,8 @@ perf_event_nmi_handler(struct notifier_block *self,
         this_nmi = percpu_read(irq_stat.__nmi_count);
         if ((handled > 1) ||
                 /* the next nmi could be a back-to-back nmi */
-            ((__get_cpu_var(pmu_nmi).marked == this_nmi) &&
-             (__get_cpu_var(pmu_nmi).handled > 1))) {
+            ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
+             (__this_cpu_read(pmu_nmi.handled) > 1))) {
                 /*
                  * We could have two subsequent back-to-back nmis: The
                  * first handles more than one counter, the 2nd
@@ -1279,8 +1306,8 @@ perf_event_nmi_handler(struct notifier_block *self,
                  * handling more than one counter. We will mark the
                  * next (3rd) and then drop it if unhandled.
                  */
-                __get_cpu_var(pmu_nmi).marked   = this_nmi + 1;
-                __get_cpu_var(pmu_nmi).handled  = handled;
+                __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
+                __this_cpu_write(pmu_nmi.handled, handled);
         }
 
         return NOTIFY_STOP;
@@ -1289,7 +1316,7 @@ perf_event_nmi_handler(struct notifier_block *self,
 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
         .notifier_call          = perf_event_nmi_handler,
         .next                   = NULL,
-        .priority               = 1
+        .priority               = NMI_LOCAL_LOW_PRIOR,
 };
 
 static struct event_constraint unconstrained;
@@ -1362,7 +1389,7 @@ static void __init pmu_check_apic(void)
         pr_info("no hardware sampling interrupt available.\n");
 }
 
-void __init init_hw_perf_events(void)
+int __init init_hw_perf_events(void)
 {
         struct event_constraint *c;
         int err;
@@ -1377,20 +1404,18 @@ void __init init_hw_perf_events(void)
                 err = amd_pmu_init();
                 break;
         default:
-                return;
+                return 0;
         }
         if (err != 0) {
                 pr_cont("no PMU driver, software events only.\n");
-                return;
+                return 0;
         }
 
         pmu_check_apic();
 
         /* sanity check that the hardware exists or is emulated */
-        if (!check_hw_exists()) {
-                pr_cont("Broken PMU hardware detected, software events only.\n");
-                return;
-        }
+        if (!check_hw_exists())
+                return 0;
 
         pr_cont("%s PMU driver.\n", x86_pmu.name);
 
@@ -1438,9 +1463,12 @@ void __init init_hw_perf_events(void)
         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
 
-        perf_pmu_register(&pmu);
+        perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
         perf_cpu_notifier(x86_pmu_notifier);
+
+        return 0;
 }
+early_initcall(init_hw_perf_events);
 
 static inline void x86_pmu_read(struct perf_event *event)
 {
@@ -1454,11 +1482,9 @@ static inline void x86_pmu_read(struct perf_event *event)
  */
 static void x86_pmu_start_txn(struct pmu *pmu)
 {
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-
         perf_pmu_disable(pmu);
-        cpuc->group_flag |= PERF_EVENT_TXN;
-        cpuc->n_txn = 0;
+        __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
+        __this_cpu_write(cpu_hw_events.n_txn, 0);
 }
 
 /*
@@ -1468,14 +1494,12 @@ static void x86_pmu_start_txn(struct pmu *pmu)
  */
 static void x86_pmu_cancel_txn(struct pmu *pmu)
 {
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-
-        cpuc->group_flag &= ~PERF_EVENT_TXN;
+        __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
         /*
          * Truncate the collected events.
          */
-        cpuc->n_added -= cpuc->n_txn;
-        cpuc->n_events -= cpuc->n_txn;
+        __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
+        __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
         perf_pmu_enable(pmu);
 }
 
@@ -1686,7 +1710,7 @@ perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 
         perf_callchain_store(entry, regs->ip);
 
-        dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
+        dump_trace(NULL, regs, NULL, &backtrace_ops, entry);
 }
 
 #ifdef CONFIG_COMPAT
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index e421b8cd6944..67e2202a6039 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -1,7 +1,5 @@
 #ifdef CONFIG_CPU_SUP_AMD
 
-static DEFINE_RAW_SPINLOCK(amd_nb_lock);
-
 static __initconst const u64 amd_hw_cache_event_ids
                                 [PERF_COUNT_HW_CACHE_MAX]
                                 [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -275,7 +273,7 @@ done:
         return &emptyconstraint;
 }
 
-static struct amd_nb *amd_alloc_nb(int cpu, int nb_id)
+static struct amd_nb *amd_alloc_nb(int cpu)
 {
         struct amd_nb *nb;
         int i;
@@ -285,7 +283,7 @@ static struct amd_nb *amd_alloc_nb(int cpu, int nb_id)
         if (!nb)
                 return NULL;
 
-        nb->nb_id = nb_id;
+        nb->nb_id = -1;
 
         /*
          * initialize all possible NB constraints
@@ -306,7 +304,7 @@ static int amd_pmu_cpu_prepare(int cpu)
         if (boot_cpu_data.x86_max_cores < 2)
                 return NOTIFY_OK;
 
-        cpuc->amd_nb = amd_alloc_nb(cpu, -1);
+        cpuc->amd_nb = amd_alloc_nb(cpu);
         if (!cpuc->amd_nb)
                 return NOTIFY_BAD;
 
@@ -325,8 +323,6 @@ static void amd_pmu_cpu_starting(int cpu)
         nb_id = amd_get_nb_id(cpu);
         WARN_ON_ONCE(nb_id == BAD_APICID);
 
-        raw_spin_lock(&amd_nb_lock);
-
         for_each_online_cpu(i) {
                 nb = per_cpu(cpu_hw_events, i).amd_nb;
                 if (WARN_ON_ONCE(!nb))
@@ -341,8 +337,6 @@ static void amd_pmu_cpu_starting(int cpu)
 
         cpuc->amd_nb->nb_id = nb_id;
         cpuc->amd_nb->refcnt++;
-
-        raw_spin_unlock(&amd_nb_lock);
 }
 
 static void amd_pmu_cpu_dead(int cpu)
@@ -354,8 +348,6 @@ static void amd_pmu_cpu_dead(int cpu)
 
         cpuhw = &per_cpu(cpu_hw_events, cpu);
 
-        raw_spin_lock(&amd_nb_lock);
-
         if (cpuhw->amd_nb) {
                 struct amd_nb *nb = cpuhw->amd_nb;
 
@@ -364,8 +356,6 @@ static void amd_pmu_cpu_dead(int cpu)
 
                 cpuhw->amd_nb = NULL;
         }
-
-        raw_spin_unlock(&amd_nb_lock);
 }
 
 static __initconst const struct x86_pmu amd_pmu = {
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index c8f5c088cad1..008835c1d79c 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -649,7 +649,7 @@ static void intel_pmu_enable_event(struct perf_event *event)
         struct hw_perf_event *hwc = &event->hw;
 
         if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
-                if (!__get_cpu_var(cpu_hw_events).enabled)
+                if (!__this_cpu_read(cpu_hw_events.enabled))
                         return;
 
                 intel_pmu_enable_bts(hwc->config);
@@ -679,7 +679,7 @@ static int intel_pmu_save_and_restart(struct perf_event *event)
 
 static void intel_pmu_reset(void)
 {
-        struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
+        struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
         unsigned long flags;
         int idx;
 
@@ -816,6 +816,32 @@ static int intel_pmu_hw_config(struct perf_event *event)
         if (ret)
                 return ret;
 
+        if (event->attr.precise_ip &&
+            (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
+                /*
+                 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
+                 * (0x003c) so that we can use it with PEBS.
+                 *
+                 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
+                 * PEBS capable. However we can use INST_RETIRED.ANY_P
+                 * (0x00c0), which is a PEBS capable event, to get the same
+                 * count.
+                 *
+                 * INST_RETIRED.ANY_P counts the number of cycles that retires
+                 * CNTMASK instructions. By setting CNTMASK to a value (16)
+                 * larger than the maximum number of instructions that can be
+                 * retired per cycle (4) and then inverting the condition, we
+                 * count all cycles that retire 16 or less instructions, which
+                 * is every cycle.
+                 *
+                 * Thereby we gain a PEBS capable cycle counter.
+                 */
+                u64 alt_config = 0x108000c0; /* INST_RETIRED.TOTAL_CYCLES */
+
+                alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
+                event->hw.config = alt_config;
+        }
+
         if (event->attr.type != PERF_TYPE_RAW)
                 return 0;
 
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index 81400b93e694..e56b9bfbabd1 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -753,19 +753,21 @@ out:
 
 static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
 {
-        int overflow = 0;
-        u32 low, high;
+        u64 v;
 
-        rdmsr(hwc->config_base + hwc->idx, low, high);
-
-        /* we need to check high bit for unflagged overflows */
-        if ((low & P4_CCCR_OVF) || !(high & (1 << 31))) {
-                overflow = 1;
-                (void)checking_wrmsrl(hwc->config_base + hwc->idx,
-                        ((u64)low) & ~P4_CCCR_OVF);
+        /* an official way for overflow indication */
+        rdmsrl(hwc->config_base + hwc->idx, v);
+        if (v & P4_CCCR_OVF) {
+                wrmsrl(hwc->config_base + hwc->idx, v & ~P4_CCCR_OVF);
+                return 1;
         }
 
-        return overflow;
+        /* it might be unflagged overflow */
+        rdmsrl(hwc->event_base + hwc->idx, v);
+        if (!(v & ARCH_P4_CNTRVAL_MASK))
+                return 1;
+
+        return 0;
 }
 
 static void p4_pmu_disable_pebs(void)
@@ -1152,9 +1154,9 @@ static __initconst const struct x86_pmu p4_pmu = {
          */
         .num_counters           = ARCH_P4_MAX_CCCR,
         .apic                   = 1,
-        .cntval_bits            = 40,
-        .cntval_mask            = (1ULL << 40) - 1,
-        .max_period             = (1ULL << 39) - 1,
+        .cntval_bits            = ARCH_P4_CNTRVAL_BITS,
+        .cntval_mask            = ARCH_P4_CNTRVAL_MASK,
+        .max_period             = (1ULL << (ARCH_P4_CNTRVAL_BITS - 1)) - 1,
         .hw_config              = p4_hw_config,
         .schedule_events        = p4_pmu_schedule_events,
         /*
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index d9f4ff8fcd69..d5a236615501 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -16,32 +16,12 @@
 #include <linux/kernel.h>
 #include <linux/bitops.h>
 #include <linux/smp.h>
-#include <linux/nmi.h>
+#include <asm/nmi.h>
 #include <linux/kprobes.h>
 
 #include <asm/apic.h>
 #include <asm/perf_event.h>
 
-struct nmi_watchdog_ctlblk {
-        unsigned int cccr_msr;
-        unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
-        unsigned int evntsel_msr;  /* the MSR to select the events to handle */
-};
-
-/* Interface defining a CPU specific perfctr watchdog */
-struct wd_ops {
-        int (*reserve)(void);
-        void (*unreserve)(void);
-        int (*setup)(unsigned nmi_hz);
-        void (*rearm)(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz);
-        void (*stop)(void);
-        unsigned perfctr;
-        unsigned evntsel;
-        u64 checkbit;
-};
-
-static const struct wd_ops *wd_ops;
-
 /*
  * this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  * offset from MSR_P4_BSU_ESCR0.
@@ -60,8 +40,6 @@ static const struct wd_ops *wd_ops;
 static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);
 static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);
 
-static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
-
 /* converts an msr to an appropriate reservation bit */
 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
 {
@@ -172,623 +150,3 @@ void release_evntsel_nmi(unsigned int msr)
         clear_bit(counter, evntsel_nmi_owner);
 }
 EXPORT_SYMBOL(release_evntsel_nmi);
-
-void disable_lapic_nmi_watchdog(void)
-{
-        BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
-
-        if (atomic_read(&nmi_active) <= 0)
-                return;
-
-        on_each_cpu(stop_apic_nmi_watchdog, NULL, 1);
-
-        if (wd_ops)
-                wd_ops->unreserve();
-
-        BUG_ON(atomic_read(&nmi_active) != 0);
-}
-
-void enable_lapic_nmi_watchdog(void)
-{
-        BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
-
-        /* are we already enabled */
-        if (atomic_read(&nmi_active) != 0)
-                return;
-
-        /* are we lapic aware */
-        if (!wd_ops)
-                return;
-        if (!wd_ops->reserve()) {
-                printk(KERN_ERR "NMI watchdog: cannot reserve perfctrs\n");
-                return;
-        }
-
-        on_each_cpu(setup_apic_nmi_watchdog, NULL, 1);
-        touch_nmi_watchdog();
-}
-
-/*
- * Activate the NMI watchdog via the local APIC.
- */
-
-static unsigned int adjust_for_32bit_ctr(unsigned int hz)
-{
-        u64 counter_val;
-        unsigned int retval = hz;
-
-        /*
-         * On Intel CPUs with P6/ARCH_PERFMON only 32 bits in the counter
-         * are writable, with higher bits sign extending from bit 31.
-         * So, we can only program the counter with 31 bit values and
-         * 32nd bit should be 1, for 33.. to be 1.
-         * Find the appropriate nmi_hz
-         */
-        counter_val = (u64)cpu_khz * 1000;
-        do_div(counter_val, retval);
-        if (counter_val > 0x7fffffffULL) {
-                u64 count = (u64)cpu_khz * 1000;
-                do_div(count, 0x7fffffffUL);
-                retval = count + 1;
-        }
-        return retval;
-}
-
-static void write_watchdog_counter(unsigned int perfctr_msr,
-                                const char *descr, unsigned nmi_hz)
-{
-        u64 count = (u64)cpu_khz * 1000;
-
-        do_div(count, nmi_hz);
-        if (descr)
-                pr_debug("setting %s to -0x%08Lx\n", descr, count);
-        wrmsrl(perfctr_msr, 0 - count);
-}
-
-static void write_watchdog_counter32(unsigned int perfctr_msr,
-                                const char *descr, unsigned nmi_hz)
-{
-        u64 count = (u64)cpu_khz * 1000;
-
-        do_div(count, nmi_hz);
-        if (descr)
-                pr_debug("setting %s to -0x%08Lx\n", descr, count);
-        wrmsr(perfctr_msr, (u32)(-count), 0);
-}
-
-/*
- * AMD K7/K8/Family10h/Family11h support.
- * AMD keeps this interface nicely stable so there is not much variety
- */
-#define K7_EVNTSEL_ENABLE       (1 << 22)
-#define K7_EVNTSEL_INT          (1 << 20)
-#define K7_EVNTSEL_OS           (1 << 17)
-#define K7_EVNTSEL_USR          (1 << 16)
-#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
-#define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
-
-static int setup_k7_watchdog(unsigned nmi_hz)
-{
-        unsigned int perfctr_msr, evntsel_msr;
-        unsigned int evntsel;
-        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
-
-        perfctr_msr = wd_ops->perfctr;
-        evntsel_msr = wd_ops->evntsel;
-
-        wrmsrl(perfctr_msr, 0UL);
-
-        evntsel = K7_EVNTSEL_INT
-                | K7_EVNTSEL_OS
-                | K7_EVNTSEL_USR
-                | K7_NMI_EVENT;
-
-        /* setup the timer */
-        wrmsr(evntsel_msr, evntsel, 0);
-        write_watchdog_counter(perfctr_msr, "K7_PERFCTR0", nmi_hz);
-
-        /* initialize the wd struct before enabling */
-        wd->perfctr_msr = perfctr_msr;
-        wd->evntsel_msr = evntsel_msr;
-        wd->cccr_msr = 0;  /* unused */
-
-        /* ok, everything is initialized, announce that we're set */
-        cpu_nmi_set_wd_enabled();
-
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-        evntsel |= K7_EVNTSEL_ENABLE;
-        wrmsr(evntsel_msr, evntsel, 0);
-
-        return 1;
-}
-
-static void single_msr_stop_watchdog(void)
-{
-        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
-
-        wrmsr(wd->evntsel_msr, 0, 0);
-}
-
-static int single_msr_reserve(void)
-{
-        if (!reserve_perfctr_nmi(wd_ops->perfctr))
-                return 0;
-
-        if (!reserve_evntsel_nmi(wd_ops->evntsel)) {
-                release_perfctr_nmi(wd_ops->perfctr);
-                return 0;
-        }
-        return 1;
-}
-
-static void single_msr_unreserve(void)
-{
-        release_evntsel_nmi(wd_ops->evntsel);
-        release_perfctr_nmi(wd_ops->perfctr);
-}
-
-static void __kprobes
-single_msr_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
-{
-        /* start the cycle over again */
-        write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz);
-}
-
-static const struct wd_ops k7_wd_ops = {
-        .reserve        = single_msr_reserve,
-        .unreserve      = single_msr_unreserve,
-        .setup          = setup_k7_watchdog,
-        .rearm          = single_msr_rearm,
-        .stop           = single_msr_stop_watchdog,
-        .perfctr        = MSR_K7_PERFCTR0,
-        .evntsel        = MSR_K7_EVNTSEL0,
-        .checkbit       = 1ULL << 47,
-};
-
-/*
- * Intel Model 6 (PPro+,P2,P3,P-M,Core1)
- */
-#define P6_EVNTSEL0_ENABLE      (1 << 22)
-#define P6_EVNTSEL_INT          (1 << 20)
-#define P6_EVNTSEL_OS           (1 << 17)
-#define P6_EVNTSEL_USR          (1 << 16)
-#define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
-#define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
-
-static int setup_p6_watchdog(unsigned nmi_hz)
-{
-        unsigned int perfctr_msr, evntsel_msr;
-        unsigned int evntsel;
-        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
-
-        perfctr_msr = wd_ops->perfctr;
-        evntsel_msr = wd_ops->evntsel;
-
-        /* KVM doesn't implement this MSR */
-        if (wrmsr_safe(perfctr_msr, 0, 0) < 0)
-                return 0;
-
-        evntsel = P6_EVNTSEL_INT
-                | P6_EVNTSEL_OS
-                | P6_EVNTSEL_USR
-                | P6_NMI_EVENT;
-
-        /* setup the timer */
-        wrmsr(evntsel_msr, evntsel, 0);
-        nmi_hz = adjust_for_32bit_ctr(nmi_hz);
-        write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0", nmi_hz);
-
-        /* initialize the wd struct before enabling */
-        wd->perfctr_msr = perfctr_msr;
-        wd->evntsel_msr = evntsel_msr;
-        wd->cccr_msr = 0;  /* unused */
-
-        /* ok, everything is initialized, announce that we're set */
-        cpu_nmi_set_wd_enabled();
-
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-        evntsel |= P6_EVNTSEL0_ENABLE;
-        wrmsr(evntsel_msr, evntsel, 0);
-
-        return 1;
-}
-
-static void __kprobes p6_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
-{
-        /*
-         * P6 based Pentium M need to re-unmask
-         * the apic vector but it doesn't hurt
-         * other P6 variant.
-         * ArchPerfom/Core Duo also needs this
-         */
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-
-        /* P6/ARCH_PERFMON has 32 bit counter write */
-        write_watchdog_counter32(wd->perfctr_msr, NULL, nmi_hz);
-}
-
-static const struct wd_ops p6_wd_ops = {
-        .reserve        = single_msr_reserve,
-        .unreserve      = single_msr_unreserve,
-        .setup          = setup_p6_watchdog,
-        .rearm          = p6_rearm,
-        .stop           = single_msr_stop_watchdog,
-        .perfctr        = MSR_P6_PERFCTR0,
-        .evntsel        = MSR_P6_EVNTSEL0,
-        .checkbit       = 1ULL << 39,
-};
-
-/*
- * Intel P4 performance counters.
- * By far the most complicated of all.
- */
-#define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1 << 7)
-#define P4_ESCR_EVENT_SELECT(N) ((N) << 25)
-#define P4_ESCR_OS              (1 << 3)
-#define P4_ESCR_USR             (1 << 2)
-#define P4_CCCR_OVF_PMI0        (1 << 26)
-#define P4_CCCR_OVF_PMI1        (1 << 27)
-#define P4_CCCR_THRESHOLD(N)    ((N) << 20)
-#define P4_CCCR_COMPLEMENT      (1 << 19)
-#define P4_CCCR_COMPARE         (1 << 18)
-#define P4_CCCR_REQUIRED        (3 << 16)
-#define P4_CCCR_ESCR_SELECT(N)  ((N) << 13)
-#define P4_CCCR_ENABLE          (1 << 12)
-#define P4_CCCR_OVF             (1 << 31)
-
-#define P4_CONTROLS 18
-static unsigned int p4_controls[18] = {
-        MSR_P4_BPU_CCCR0,
-        MSR_P4_BPU_CCCR1,
-        MSR_P4_BPU_CCCR2,
-        MSR_P4_BPU_CCCR3,
-        MSR_P4_MS_CCCR0,
-        MSR_P4_MS_CCCR1,
-        MSR_P4_MS_CCCR2,
-        MSR_P4_MS_CCCR3,
-        MSR_P4_FLAME_CCCR0,
-        MSR_P4_FLAME_CCCR1,
-        MSR_P4_FLAME_CCCR2,
-        MSR_P4_FLAME_CCCR3,
-        MSR_P4_IQ_CCCR0,
-        MSR_P4_IQ_CCCR1,
-        MSR_P4_IQ_CCCR2,
-        MSR_P4_IQ_CCCR3,
-        MSR_P4_IQ_CCCR4,
-        MSR_P4_IQ_CCCR5,
-};
-/*
- * Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
- * CRU_ESCR0 (with any non-null event selector) through a complemented
- * max threshold. [IA32-Vol3, Section 14.9.9]
- */
-static int setup_p4_watchdog(unsigned nmi_hz)
-{
-        unsigned int perfctr_msr, evntsel_msr, cccr_msr;
-        unsigned int evntsel, cccr_val;
-        unsigned int misc_enable, dummy;
-        unsigned int ht_num;
-        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
-
-        rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
-        if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
-                return 0;
-
-#ifdef CONFIG_SMP
-        /* detect which hyperthread we are on */
-        if (smp_num_siblings == 2) {
-                unsigned int ebx, apicid;
-
-                ebx = cpuid_ebx(1);
-                apicid = (ebx >> 24) & 0xff;
-                ht_num = apicid & 1;
-        } else
-#endif
-                ht_num = 0;
-
-        /*
-         * performance counters are shared resources
-         * assign each hyperthread its own set
-         * (re-use the ESCR0 register, seems safe
-         * and keeps the cccr_val the same)
-         */
-        if (!ht_num) {
-                /* logical cpu 0 */
-                perfctr_msr = MSR_P4_IQ_PERFCTR0;
-                evntsel_msr = MSR_P4_CRU_ESCR0;
-                cccr_msr = MSR_P4_IQ_CCCR0;
-                cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
-
-                /*
-                 * If we're on the kdump kernel or other situation, we may
-                 * still have other performance counter registers set to
-                 * interrupt and they'll keep interrupting forever because
-                 * of the P4_CCCR_OVF quirk. So we need to ACK all the
-                 * pending interrupts and disable all the registers here,
-                 * before reenabling the NMI delivery. Refer to p4_rearm()
-                 * about the P4_CCCR_OVF quirk.
-                 */
-                if (reset_devices) {
-                        unsigned int low, high;
-                        int i;
-
-                        for (i = 0; i < P4_CONTROLS; i++) {
-                                rdmsr(p4_controls[i], low, high);
-                                low &= ~(P4_CCCR_ENABLE | P4_CCCR_OVF);
-                                wrmsr(p4_controls[i], low, high);
-                        }
-                }
-        } else {
-                /* logical cpu 1 */
-                perfctr_msr = MSR_P4_IQ_PERFCTR1;
-                evntsel_msr = MSR_P4_CRU_ESCR0;
-                cccr_msr = MSR_P4_IQ_CCCR1;
-
-                /* Pentium 4 D processors don't support P4_CCCR_OVF_PMI1 */
-                if (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask == 4)
-                        cccr_val = P4_CCCR_OVF_PMI0;
-                else
-                        cccr_val = P4_CCCR_OVF_PMI1;
-                cccr_val |= P4_CCCR_ESCR_SELECT(4);
-        }
-
-        evntsel = P4_ESCR_EVENT_SELECT(0x3F)
-                | P4_ESCR_OS
-                | P4_ESCR_USR;
-
-        cccr_val |= P4_CCCR_THRESHOLD(15)
-                 | P4_CCCR_COMPLEMENT
-                 | P4_CCCR_COMPARE
-                 | P4_CCCR_REQUIRED;
-
-        wrmsr(evntsel_msr, evntsel, 0);
-        wrmsr(cccr_msr, cccr_val, 0);
-        write_watchdog_counter(perfctr_msr, "P4_IQ_COUNTER0", nmi_hz);
-
-        wd->perfctr_msr = perfctr_msr;
-        wd->evntsel_msr = evntsel_msr;
-        wd->cccr_msr = cccr_msr;
-
-        /* ok, everything is initialized, announce that we're set */
-        cpu_nmi_set_wd_enabled();
-
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-        cccr_val |= P4_CCCR_ENABLE;
-        wrmsr(cccr_msr, cccr_val, 0);
-        return 1;
-}
-
-static void stop_p4_watchdog(void)
-{
-        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
-        wrmsr(wd->cccr_msr, 0, 0);
-        wrmsr(wd->evntsel_msr, 0, 0);
-}
-
-static int p4_reserve(void)
-{
-        if (!reserve_perfctr_nmi(MSR_P4_IQ_PERFCTR0))
-                return 0;
-#ifdef CONFIG_SMP
-        if (smp_num_siblings > 1 && !reserve_perfctr_nmi(MSR_P4_IQ_PERFCTR1))
-                goto fail1;
-#endif
-        if (!reserve_evntsel_nmi(MSR_P4_CRU_ESCR0))
-                goto fail2;
-        /* RED-PEN why is ESCR1 not reserved here? */
-        return 1;
- fail2:
-#ifdef CONFIG_SMP
-        if (smp_num_siblings > 1)
-                release_perfctr_nmi(MSR_P4_IQ_PERFCTR1);
- fail1:
-#endif
-        release_perfctr_nmi(MSR_P4_IQ_PERFCTR0);
-        return 0;
-}
-
-static void p4_unreserve(void)
-{
-#ifdef CONFIG_SMP
-        if (smp_num_siblings > 1)
-                release_perfctr_nmi(MSR_P4_IQ_PERFCTR1);
-#endif
-        release_evntsel_nmi(MSR_P4_CRU_ESCR0);
-        release_perfctr_nmi(MSR_P4_IQ_PERFCTR0);
-}
-
-static void __kprobes p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
-{
-        unsigned dummy;
-        /*
-         * P4 quirks:
-         * - An overflown perfctr will assert its interrupt
-         *   until the OVF flag in its CCCR is cleared.
-         * - LVTPC is masked on interrupt and must be
-         *   unmasked by the LVTPC handler.
-         */
-        rdmsrl(wd->cccr_msr, dummy);
-        dummy &= ~P4_CCCR_OVF;
-        wrmsrl(wd->cccr_msr, dummy);
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-        /* start the cycle over again */
-        write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz);
-}
-
-static const struct wd_ops p4_wd_ops = {
-        .reserve        = p4_reserve,
-        .unreserve      = p4_unreserve,
-        .setup          = setup_p4_watchdog,
-        .rearm          = p4_rearm,
-        .stop           = stop_p4_watchdog,
-        /* RED-PEN this is wrong for the other sibling */
-        .perfctr        = MSR_P4_BPU_PERFCTR0,
-        .evntsel        = MSR_P4_BSU_ESCR0,
-        .checkbit       = 1ULL << 39,
-};
-
-/*
- * Watchdog using the Intel architected PerfMon.
- * Used for Core2 and hopefully all future Intel CPUs.
- */
-#define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
-#define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
-
-static struct wd_ops intel_arch_wd_ops;
-
-static int setup_intel_arch_watchdog(unsigned nmi_hz)
-{
-        unsigned int ebx;
-        union cpuid10_eax eax;
-        unsigned int unused;
-        unsigned int perfctr_msr, evntsel_msr;
-        unsigned int evntsel;
-        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
-
-        /*
-         * Check whether the Architectural PerfMon supports
-         * Unhalted Core Cycles Event or not.
-         * NOTE: Corresponding bit = 0 in ebx indicates event present.
-         */
-        cpuid(10, &(eax.full), &ebx, &unused, &unused);
-        if ((eax.split.mask_length <
-                        (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
-            (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
-                return 0;
-
-        perfctr_msr = wd_ops->perfctr;
-        evntsel_msr = wd_ops->evntsel;
-
-        wrmsrl(perfctr_msr, 0UL);
-
-        evntsel = ARCH_PERFMON_EVENTSEL_INT
-                | ARCH_PERFMON_EVENTSEL_OS
-                | ARCH_PERFMON_EVENTSEL_USR
-                | ARCH_PERFMON_NMI_EVENT_SEL
-                | ARCH_PERFMON_NMI_EVENT_UMASK;
-
-        /* setup the timer */
-        wrmsr(evntsel_msr, evntsel, 0);
-        nmi_hz = adjust_for_32bit_ctr(nmi_hz);
-        write_watchdog_counter32(perfctr_msr, "INTEL_ARCH_PERFCTR0", nmi_hz);
-
-        wd->perfctr_msr = perfctr_msr;
-        wd->evntsel_msr = evntsel_msr;
-        wd->cccr_msr = 0;  /* unused */
-
-        /* ok, everything is initialized, announce that we're set */
-        cpu_nmi_set_wd_enabled();
-
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-        evntsel |= ARCH_PERFMON_EVENTSEL_ENABLE;
-        wrmsr(evntsel_msr, evntsel, 0);
-        intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1);
-        return 1;
-}
-
-static struct wd_ops intel_arch_wd_ops __read_mostly = {
-        .reserve        = single_msr_reserve,
-        .unreserve      = single_msr_unreserve,
-        .setup          = setup_intel_arch_watchdog,
-        .rearm          = p6_rearm,
-        .stop           = single_msr_stop_watchdog,
-        .perfctr        = MSR_ARCH_PERFMON_PERFCTR1,
-        .evntsel        = MSR_ARCH_PERFMON_EVENTSEL1,
-};
-
-static void probe_nmi_watchdog(void)
-{
-        switch (boot_cpu_data.x86_vendor) {
-        case X86_VENDOR_AMD:
-                if (boot_cpu_data.x86 == 6 ||
-                    (boot_cpu_data.x86 >= 0xf && boot_cpu_data.x86 <= 0x15))
-                        wd_ops = &k7_wd_ops;
-                return;
-        case X86_VENDOR_INTEL:
-                /* Work around where perfctr1 doesn't have a working enable
-                 * bit as described in the following errata:
-                 * AE49 Core Duo and Intel Core Solo 65 nm
-                 * AN49 Intel Pentium Dual-Core
-                 * AF49 Dual-Core Intel Xeon Processor LV
-                 */
-                if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 14) ||
-                    ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 15 &&
-                     boot_cpu_data.x86_mask == 4))) {
-                        intel_arch_wd_ops.perfctr = MSR_ARCH_PERFMON_PERFCTR0;
-                        intel_arch_wd_ops.evntsel = MSR_ARCH_PERFMON_EVENTSEL0;
-                }
-                if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
-                        wd_ops = &intel_arch_wd_ops;
-                        break;
-                }
-                switch (boot_cpu_data.x86) {
-                case 6:
-                        if (boot_cpu_data.x86_model > 13)
-                                return;
-
-                        wd_ops = &p6_wd_ops;
-                        break;
-                case 15:
-                        wd_ops = &p4_wd_ops;
-                        break;
-                default:
-                        return;
-                }
-                break;
-        }
-}
-
-/* Interface to nmi.c */
-
-int lapic_watchdog_init(unsigned nmi_hz)
-{
-        if (!wd_ops) {
-                probe_nmi_watchdog();
-                if (!wd_ops) {
-                        printk(KERN_INFO "NMI watchdog: CPU not supported\n");
-                        return -1;
-                }
-
-                if (!wd_ops->reserve()) {
-                        printk(KERN_ERR
-                                "NMI watchdog: cannot reserve perfctrs\n");
-                        return -1;
-                }
-        }
-
-        if (!(wd_ops->setup(nmi_hz))) {
-                printk(KERN_ERR "Cannot setup NMI watchdog on CPU %d\n",
-                       raw_smp_processor_id());
-                return -1;
-        }
-
-        return 0;
-}
-
-void lapic_watchdog_stop(void)
-{
-        if (wd_ops)
-                wd_ops->stop();
-}
-
-unsigned lapic_adjust_nmi_hz(unsigned hz)
-{
-        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
-        if (wd->perfctr_msr == MSR_P6_PERFCTR0 ||
-            wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1)
-                hz = adjust_for_32bit_ctr(hz);
-        return hz;
-}
-
-int __kprobes lapic_wd_event(unsigned nmi_hz)
-{
-        struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
-        u64 ctr;
-
-        rdmsrl(wd->perfctr_msr, ctr);
-        if (ctr & wd_ops->checkbit) /* perfctr still running? */
-                return 0;
-
-        wd_ops->rearm(wd, nmi_hz);
-        return 1;
-}
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
index 6e8752c1bd52..d6fb146c0d8b 100644
--- a/arch/x86/kernel/dumpstack.c
+++ b/arch/x86/kernel/dumpstack.c
@@ -175,21 +175,21 @@ static const struct stacktrace_ops print_trace_ops = {
 
 void
 show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
-                unsigned long *stack, unsigned long bp, char *log_lvl)
+                unsigned long *stack, char *log_lvl)
 {
         printk("%sCall Trace:\n", log_lvl);
-        dump_trace(task, regs, stack, bp, &print_trace_ops, log_lvl);
+        dump_trace(task, regs, stack, &print_trace_ops, log_lvl);
 }
 
 void show_trace(struct task_struct *task, struct pt_regs *regs,
-                unsigned long *stack, unsigned long bp)
+                unsigned long *stack)
 {
-        show_trace_log_lvl(task, regs, stack, bp, "");
+        show_trace_log_lvl(task, regs, stack, "");
 }
 
 void show_stack(struct task_struct *task, unsigned long *sp)
 {
-        show_stack_log_lvl(task, NULL, sp, 0, "");
+        show_stack_log_lvl(task, NULL, sp, "");
 }
 
 /*
@@ -197,20 +197,14 @@ void show_stack(struct task_struct *task, unsigned long *sp)
  */
 void dump_stack(void)
 {
-        unsigned long bp = 0;
         unsigned long stack;
 
-#ifdef CONFIG_FRAME_POINTER
-        if (!bp)
-                get_bp(bp);
-#endif
-
         printk("Pid: %d, comm: %.20s %s %s %.*s\n",
                 current->pid, current->comm, print_tainted(),
                 init_utsname()->release,
                 (int)strcspn(init_utsname()->version, " "),
                 init_utsname()->version);
-        show_trace(NULL, NULL, &stack, bp);
+        show_trace(NULL, NULL, &stack);
 }
 EXPORT_SYMBOL(dump_stack);
 
diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c
index 1bc7f75a5bda..74cc1eda384b 100644
--- a/arch/x86/kernel/dumpstack_32.c
+++ b/arch/x86/kernel/dumpstack_32.c
@@ -17,11 +17,12 @@
 #include <asm/stacktrace.h>
 
 
-void dump_trace(struct task_struct *task, struct pt_regs *regs,
-                unsigned long *stack, unsigned long bp,
+void dump_trace(struct task_struct *task,
+                struct pt_regs *regs, unsigned long *stack,
                 const struct stacktrace_ops *ops, void *data)
 {
         int graph = 0;
+        unsigned long bp;
 
         if (!task)
                 task = current;
@@ -34,18 +35,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
                         stack = (unsigned long *)task->thread.sp;
         }
 
-#ifdef CONFIG_FRAME_POINTER
-        if (!bp) {
-                if (task == current) {
-                        /* Grab bp right from our regs */
-                        get_bp(bp);
-                } else {
-                        /* bp is the last reg pushed by switch_to */
-                        bp = *(unsigned long *) task->thread.sp;
-                }
-        }
-#endif
-
+        bp = stack_frame(task, regs);
         for (;;) {
                 struct thread_info *context;
 
@@ -65,7 +55,7 @@ EXPORT_SYMBOL(dump_trace);
 
 void
 show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
-                   unsigned long *sp, unsigned long bp, char *log_lvl)
+                   unsigned long *sp, char *log_lvl)
 {
         unsigned long *stack;
         int i;
@@ -87,7 +77,7 @@ show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
                 touch_nmi_watchdog();
         }
         printk(KERN_CONT "\n");
-        show_trace_log_lvl(task, regs, sp, bp, log_lvl);
+        show_trace_log_lvl(task, regs, sp, log_lvl);
 }
 
 
@@ -112,8 +102,7 @@ void show_registers(struct pt_regs *regs)
                 u8 *ip;
 
                 printk(KERN_EMERG "Stack:\n");
-                show_stack_log_lvl(NULL, regs, &regs->sp,
-                                0, KERN_EMERG);
+                show_stack_log_lvl(NULL, regs, &regs->sp, KERN_EMERG);
 
                 printk(KERN_EMERG "Code: ");
 
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index 6a340485249a..64101335de19 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -139,8 +139,8 @@ fixup_bp_irq_link(unsigned long bp, unsigned long *stack,
  * severe exception (double fault, nmi, stack fault, debug, mce) hardware stack
  */
 
-void dump_trace(struct task_struct *task, struct pt_regs *regs,
-                unsigned long *stack, unsigned long bp,
+void dump_trace(struct task_struct *task,
+                struct pt_regs *regs, unsigned long *stack,
                 const struct stacktrace_ops *ops, void *data)
 {
         const unsigned cpu = get_cpu();
@@ -149,6 +149,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
         unsigned used = 0;
         struct thread_info *tinfo;
         int graph = 0;
+        unsigned long bp;
 
         if (!task)
                 task = current;
@@ -160,18 +161,7 @@ void dump_trace(struct task_struct *task, struct pt_regs *regs,
                         stack = (unsigned long *)task->thread.sp;
         }
 
-#ifdef CONFIG_FRAME_POINTER
-        if (!bp) {
-                if (task == current) {
-                        /* Grab bp right from our regs */
-                        get_bp(bp);
-                } else {
-                        /* bp is the last reg pushed by switch_to */
-                        bp = *(unsigned long *) task->thread.sp;
-                }
-        }
-#endif
-
+        bp = stack_frame(task, regs);
         /*
          * Print function call entries in all stacks, starting at the
          * current stack address. If the stacks consist of nested
@@ -235,7 +225,7 @@ EXPORT_SYMBOL(dump_trace);
 
 void
 show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
-                   unsigned long *sp, unsigned long bp, char *log_lvl)
+                   unsigned long *sp, char *log_lvl)
 {
         unsigned long *irq_stack_end;
         unsigned long *irq_stack;
@@ -279,7 +269,7 @@ show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
         preempt_enable();
 
         printk(KERN_CONT "\n");
-        show_trace_log_lvl(task, regs, sp, bp, log_lvl);
+        show_trace_log_lvl(task, regs, sp, log_lvl);
 }
 
 void show_registers(struct pt_regs *regs)
@@ -308,7 +298,7 @@ void show_registers(struct pt_regs *regs)
 
                 printk(KERN_EMERG "Stack:\n");
                 show_stack_log_lvl(NULL, regs, (unsigned long *)sp,
-                                regs->bp, KERN_EMERG);
+                                   KERN_EMERG);
 
                 printk(KERN_EMERG "Code: ");
 
diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c
index 4572f25f9325..cd28a350f7f9 100644
--- a/arch/x86/kernel/early_printk.c
+++ b/arch/x86/kernel/early_printk.c
@@ -240,7 +240,7 @@ static int __init setup_early_printk(char *buf)
                 if (!strncmp(buf, "xen", 3))
                         early_console_register(&xenboot_console, keep);
 #endif
-#ifdef CONFIG_X86_MRST_EARLY_PRINTK
+#ifdef CONFIG_EARLY_PRINTK_MRST
                 if (!strncmp(buf, "mrst", 4)) {
                         mrst_early_console_init();
                         early_console_register(&early_mrst_console, keep);
@@ -250,7 +250,6 @@ static int __init setup_early_printk(char *buf)
                         hsu_early_console_init();
                         early_console_register(&early_hsu_console, keep);
                 }
-
 #endif
                 buf++;
         }
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index e3ba417e8697..d3b895f375d3 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -299,17 +299,21 @@ ENDPROC(native_usergs_sysret64)
 ENTRY(save_args)
         XCPT_FRAME
         cld
-        movq_cfi rdi, RDI+16-ARGOFFSET
-        movq_cfi rsi, RSI+16-ARGOFFSET
-        movq_cfi rdx, RDX+16-ARGOFFSET
-        movq_cfi rcx, RCX+16-ARGOFFSET
-        movq_cfi rax, RAX+16-ARGOFFSET
-        movq_cfi  r8,  R8+16-ARGOFFSET
-        movq_cfi  r9,  R9+16-ARGOFFSET
-        movq_cfi r10, R10+16-ARGOFFSET
-        movq_cfi r11, R11+16-ARGOFFSET
-
-        leaq -ARGOFFSET+16(%rsp),%rdi   /* arg1 for handler */
+        /*
+         * start from rbp in pt_regs and jump over
+         * return address.
+         */
+        movq_cfi rdi, RDI+8-RBP
+        movq_cfi rsi, RSI+8-RBP
+        movq_cfi rdx, RDX+8-RBP
+        movq_cfi rcx, RCX+8-RBP
+        movq_cfi rax, RAX+8-RBP
+        movq_cfi  r8,  R8+8-RBP
+        movq_cfi  r9,  R9+8-RBP
+        movq_cfi r10, R10+8-RBP
+        movq_cfi r11, R11+8-RBP
+
+        leaq -RBP+8(%rsp),%rdi  /* arg1 for handler */
         movq_cfi rbp, 8         /* push %rbp */
         leaq 8(%rsp), %rbp              /* mov %rsp, %ebp */
         testl $3, CS(%rdi)
@@ -782,8 +786,9 @@ END(interrupt)
 
 /* 0(%rsp): ~(interrupt number) */
         .macro interrupt func
-        subq $ORIG_RAX-ARGOFFSET+8, %rsp
-        CFI_ADJUST_CFA_OFFSET ORIG_RAX-ARGOFFSET+8
+        /* reserve pt_regs for scratch regs and rbp */
+        subq $ORIG_RAX-RBP, %rsp
+        CFI_ADJUST_CFA_OFFSET ORIG_RAX-RBP
         call save_args
         PARTIAL_FRAME 0
         call \func
@@ -808,9 +813,14 @@ ret_from_intr:
         TRACE_IRQS_OFF
         decl PER_CPU_VAR(irq_count)
         leaveq
+
         CFI_RESTORE             rbp
         CFI_DEF_CFA_REGISTER    rsp
         CFI_ADJUST_CFA_OFFSET   -8
+
+        /* we did not save rbx, restore only from ARGOFFSET */
+        addq $8, %rsp
+        CFI_ADJUST_CFA_OFFSET   -8
 exit_intr:
         GET_THREAD_INFO(%rcx)
         testl $3,CS-ARGOFFSET(%rsp)
diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c
index 3afb33f14d2d..382eb2936d4d 100644
--- a/arch/x86/kernel/ftrace.c
+++ b/arch/x86/kernel/ftrace.c
@@ -19,6 +19,7 @@
 #include <linux/sched.h>
 #include <linux/init.h>
 #include <linux/list.h>
+#include <linux/module.h>
 
 #include <trace/syscall.h>
 
@@ -49,6 +50,7 @@ static DEFINE_PER_CPU(int, save_modifying_code);
 int ftrace_arch_code_modify_prepare(void)
 {
         set_kernel_text_rw();
+        set_all_modules_text_rw();
         modifying_code = 1;
         return 0;
 }
@@ -56,6 +58,7 @@ int ftrace_arch_code_modify_prepare(void)
 int ftrace_arch_code_modify_post_process(void)
 {
         modifying_code = 0;
+        set_all_modules_text_ro();
         set_kernel_text_ro();
         return 0;
 }
@@ -167,9 +170,9 @@ static void ftrace_mod_code(void)
 
 void ftrace_nmi_enter(void)
 {
-        __get_cpu_var(save_modifying_code) = modifying_code;
+        __this_cpu_write(save_modifying_code, modifying_code);
 
-        if (!__get_cpu_var(save_modifying_code))
+        if (!__this_cpu_read(save_modifying_code))
                 return;
 
         if (atomic_inc_return(&nmi_running) & MOD_CODE_WRITE_FLAG) {
@@ -183,7 +186,7 @@ void ftrace_nmi_enter(void)
 
 void ftrace_nmi_exit(void)
 {
-        if (!__get_cpu_var(save_modifying_code))
+        if (!__this_cpu_read(save_modifying_code))
                 return;
 
         /* Finish all executions before clearing nmi_running */
diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c
index 763310165fa0..7f138b3c3c52 100644
--- a/arch/x86/kernel/head32.c
+++ b/arch/x86/kernel/head32.c
@@ -61,6 +61,9 @@ void __init i386_start_kernel(void)
         case X86_SUBARCH_MRST:
                 x86_mrst_early_setup();
                 break;
+        case X86_SUBARCH_CE4100:
+                x86_ce4100_early_setup();
+                break;
         default:
                 i386_default_early_setup();
                 break;
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index c0dbd9ac24f0..9f54b209c378 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -139,39 +139,6 @@ ENTRY(startup_32)
         movl %eax, pa(olpc_ofw_pgd)
 #endif
 
-#ifdef CONFIG_PARAVIRT
-        /* This is can only trip for a broken bootloader... */
-        cmpw $0x207, pa(boot_params + BP_version)
-        jb default_entry
-
-        /* Paravirt-compatible boot parameters.  Look to see what architecture
-                we're booting under. */
-        movl pa(boot_params + BP_hardware_subarch), %eax
-        cmpl $num_subarch_entries, %eax
-        jae bad_subarch
-
-        movl pa(subarch_entries)(,%eax,4), %eax
-        subl $__PAGE_OFFSET, %eax
-        jmp *%eax
-
-bad_subarch:
-WEAK(lguest_entry)
-WEAK(xen_entry)
-        /* Unknown implementation; there's really
-           nothing we can do at this point. */
-        ud2a
-
-        __INITDATA
-
-subarch_entries:
-        .long default_entry             /* normal x86/PC */
-        .long lguest_entry              /* lguest hypervisor */
-        .long xen_entry                 /* Xen hypervisor */
-        .long default_entry             /* Moorestown MID */
-num_subarch_entries = (. - subarch_entries) / 4
-.previous
-#endif /* CONFIG_PARAVIRT */
-
 /*
  * Initialize page tables.  This creates a PDE and a set of page
  * tables, which are located immediately beyond __brk_base.  The variable
@@ -181,7 +148,6 @@ num_subarch_entries = (. - subarch_entries) / 4
  *
  * Note that the stack is not yet set up!
  */
-default_entry:
 #ifdef CONFIG_X86_PAE
 
         /*
@@ -261,7 +227,42 @@ page_pde_offset = (__PAGE_OFFSET >> 20);
         movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax
         movl %eax,pa(initial_page_table+0xffc)
 #endif
-        jmp 3f
+
+#ifdef CONFIG_PARAVIRT
+        /* This is can only trip for a broken bootloader... */
+        cmpw $0x207, pa(boot_params + BP_version)
+        jb default_entry
+
+        /* Paravirt-compatible boot parameters.  Look to see what architecture
+                we're booting under. */
+        movl pa(boot_params + BP_hardware_subarch), %eax
+        cmpl $num_subarch_entries, %eax
+        jae bad_subarch
+
+        movl pa(subarch_entries)(,%eax,4), %eax
+        subl $__PAGE_OFFSET, %eax
+        jmp *%eax
+
+bad_subarch:
+WEAK(lguest_entry)
+WEAK(xen_entry)
+        /* Unknown implementation; there's really
+           nothing we can do at this point. */
+        ud2a
+
+        __INITDATA
+
+subarch_entries:
+        .long default_entry             /* normal x86/PC */
+        .long lguest_entry              /* lguest hypervisor */
+        .long xen_entry                 /* Xen hypervisor */
+        .long default_entry             /* Moorestown MID */
+num_subarch_entries = (. - subarch_entries) / 4
+.previous
+#else
+        jmp default_entry
+#endif /* CONFIG_PARAVIRT */
+
 /*
  * Non-boot CPU entry point; entered from trampoline.S
  * We can't lgdt here, because lgdt itself uses a data segment, but
@@ -282,7 +283,7 @@ ENTRY(startup_32_smp)
         movl %eax,%fs
         movl %eax,%gs
 #endif /* CONFIG_SMP */
-3:
+default_entry:
 
 /*
  *      New page tables may be in 4Mbyte page mode and may
@@ -316,6 +317,10 @@ ENTRY(startup_32_smp)
         subl $0x80000001, %eax
         cmpl $(0x8000ffff-0x80000001), %eax
         ja 6f
+
+        /* Clear bogus XD_DISABLE bits */
+        call verify_cpu
+
         mov $0x80000001, %eax
         cpuid
         /* Execute Disable bit supported? */
@@ -611,6 +616,8 @@ ignore_int:
 #endif
         iret
 
+#include "verify_cpu.S"
+
         __REFDATA
 .align 4
 ENTRY(initial_code)
@@ -622,13 +629,13 @@ ENTRY(initial_code)
 __PAGE_ALIGNED_BSS
         .align PAGE_SIZE_asm
 #ifdef CONFIG_X86_PAE
-ENTRY(initial_pg_pmd)
+initial_pg_pmd:
         .fill 1024*KPMDS,4,0
 #else
 ENTRY(initial_page_table)
         .fill 1024,4,0
 #endif
-ENTRY(initial_pg_fixmap)
+initial_pg_fixmap:
         .fill 1024,4,0
 ENTRY(empty_zero_page)
         .fill 4096,1,0
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index 42c594254507..02f07634d265 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -122,7 +122,7 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
                 return -EBUSY;
 
         set_debugreg(info->address, i);
-        __get_cpu_var(cpu_debugreg[i]) = info->address;
+        __this_cpu_write(cpu_debugreg[i], info->address);
 
         dr7 = &__get_cpu_var(cpu_dr7);
         *dr7 |= encode_dr7(i, info->len, info->type);
@@ -397,12 +397,12 @@ void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
 
 void hw_breakpoint_restore(void)
 {
-        set_debugreg(__get_cpu_var(cpu_debugreg[0]), 0);
-        set_debugreg(__get_cpu_var(cpu_debugreg[1]), 1);
-        set_debugreg(__get_cpu_var(cpu_debugreg[2]), 2);
-        set_debugreg(__get_cpu_var(cpu_debugreg[3]), 3);
+        set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
+        set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
+        set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
+        set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
         set_debugreg(current->thread.debugreg6, 6);
-        set_debugreg(__get_cpu_var(cpu_dr7), 7);
+        set_debugreg(__this_cpu_read(cpu_dr7), 7);
 }
 EXPORT_SYMBOL_GPL(hw_breakpoint_restore);
 
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 83ec0175f986..3a43caa3beb7 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -234,7 +234,7 @@ unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
         exit_idle();
         irq_enter();
 
-        irq = __get_cpu_var(vector_irq)[vector];
+        irq = __this_cpu_read(vector_irq[vector]);
 
         if (!handle_irq(irq, regs)) {
                 ack_APIC_irq();
@@ -350,12 +350,12 @@ void fixup_irqs(void)
         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
                 unsigned int irr;
 
-                if (__get_cpu_var(vector_irq)[vector] < 0)
+                if (__this_cpu_read(vector_irq[vector]) < 0)
                         continue;
 
                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
                 if (irr  & (1 << (vector % 32))) {
-                        irq = __get_cpu_var(vector_irq)[vector];
+                        irq = __this_cpu_read(vector_irq[vector]);
 
                         data = irq_get_irq_data(irq);
                         raw_spin_lock(&desc->lock);
diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c
index 96656f207751..48ff6dcffa02 100644
--- a/arch/x86/kernel/irq_32.c
+++ b/arch/x86/kernel/irq_32.c
@@ -79,7 +79,7 @@ execute_on_irq_stack(int overflow, struct irq_desc *desc, int irq)
         u32 *isp, arg1, arg2;
 
         curctx = (union irq_ctx *) current_thread_info();
-        irqctx = __get_cpu_var(hardirq_ctx);
+        irqctx = __this_cpu_read(hardirq_ctx);
 
         /*
          * this is where we switch to the IRQ stack. However, if we are
@@ -166,7 +166,7 @@ asmlinkage void do_softirq(void)
 
         if (local_softirq_pending()) {
                 curctx = current_thread_info();
-                irqctx = __get_cpu_var(softirq_ctx);
+                irqctx = __this_cpu_read(softirq_ctx);
                 irqctx->tinfo.task = curctx->task;
                 irqctx->tinfo.previous_esp = current_stack_pointer;
 
diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
index cd21b654dec6..a4130005028a 100644
--- a/arch/x86/kernel/kgdb.c
+++ b/arch/x86/kernel/kgdb.c
@@ -48,6 +48,7 @@
 #include <asm/apicdef.h>
 #include <asm/system.h>
 #include <asm/apic.h>
+#include <asm/nmi.h>
 
 struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] =
 {
@@ -525,10 +526,6 @@ static int __kgdb_notify(struct die_args *args, unsigned long cmd)
                 }
                 return NOTIFY_DONE;
 
-        case DIE_NMI_IPI:
-                /* Just ignore, we will handle the roundup on DIE_NMI. */
-                return NOTIFY_DONE;
-
         case DIE_NMIUNKNOWN:
                 if (was_in_debug_nmi[raw_smp_processor_id()]) {
                         was_in_debug_nmi[raw_smp_processor_id()] = 0;
@@ -606,7 +603,7 @@ static struct notifier_block kgdb_notifier = {
         /*
          * Lowest-prio notifier priority, we want to be notified last:
          */
-        .priority       = -INT_MAX,
+        .priority       = NMI_LOCAL_LOW_PRIOR,
 };
 
 /**
diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c
index 1cbd54c0df99..d91c477b3f62 100644
--- a/arch/x86/kernel/kprobes.c
+++ b/arch/x86/kernel/kprobes.c
@@ -403,7 +403,7 @@ static void __kprobes save_previous_kprobe(struct kprobe_ctlblk *kcb)
 
 static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb)
 {
-        __get_cpu_var(current_kprobe) = kcb->prev_kprobe.kp;
+        __this_cpu_write(current_kprobe, kcb->prev_kprobe.kp);
         kcb->kprobe_status = kcb->prev_kprobe.status;
         kcb->kprobe_old_flags = kcb->prev_kprobe.old_flags;
         kcb->kprobe_saved_flags = kcb->prev_kprobe.saved_flags;
@@ -412,7 +412,7 @@ static void __kprobes restore_previous_kprobe(struct kprobe_ctlblk *kcb)
 static void __kprobes set_current_kprobe(struct kprobe *p, struct pt_regs *regs,
                                 struct kprobe_ctlblk *kcb)
 {
-        __get_cpu_var(current_kprobe) = p;
+        __this_cpu_write(current_kprobe, p);
         kcb->kprobe_saved_flags = kcb->kprobe_old_flags
                 = (regs->flags & (X86_EFLAGS_TF | X86_EFLAGS_IF));
         if (is_IF_modifier(p->ainsn.insn))
@@ -586,7 +586,7 @@ static int __kprobes kprobe_handler(struct pt_regs *regs)
                 preempt_enable_no_resched();
                 return 1;
         } else if (kprobe_running()) {
-                p = __get_cpu_var(current_kprobe);
+                p = __this_cpu_read(current_kprobe);
                 if (p->break_handler && p->break_handler(p, regs)) {
                         setup_singlestep(p, regs, kcb, 0);
                         return 1;
@@ -759,11 +759,11 @@ static __used __kprobes void *trampoline_handler(struct pt_regs *regs)
 
                 orig_ret_address = (unsigned long)ri->ret_addr;
                 if (ri->rp && ri->rp->handler) {
-                        __get_cpu_var(current_kprobe) = &ri->rp->kp;
+                        __this_cpu_write(current_kprobe, &ri->rp->kp);
                         get_kprobe_ctlblk()->kprobe_status = KPROBE_HIT_ACTIVE;
                         ri->ret_addr = correct_ret_addr;
                         ri->rp->handler(ri, regs);
-                        __get_cpu_var(current_kprobe) = NULL;
+                        __this_cpu_write(current_kprobe, NULL);
                 }
 
                 recycle_rp_inst(ri, &empty_rp);
@@ -1184,6 +1184,10 @@ static void __kprobes optimized_callback(struct optimized_kprobe *op,
 {
         struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();
 
+        /* This is possible if op is under delayed unoptimizing */
+        if (kprobe_disabled(&op->kp))
+                return;
+
         preempt_disable();
         if (kprobe_running()) {
                 kprobes_inc_nmissed_count(&op->kp);
@@ -1198,10 +1202,10 @@ static void __kprobes optimized_callback(struct optimized_kprobe *op,
                 regs->ip = (unsigned long)op->kp.addr + INT3_SIZE;
                 regs->orig_ax = ~0UL;
 
-                __get_cpu_var(current_kprobe) = &op->kp;
+                __this_cpu_write(current_kprobe, &op->kp);
                 kcb->kprobe_status = KPROBE_HIT_ACTIVE;
                 opt_pre_handler(&op->kp, regs);
-                __get_cpu_var(current_kprobe) = NULL;
+                __this_cpu_write(current_kprobe, NULL);
         }
         preempt_enable_no_resched();
 }
@@ -1401,10 +1405,16 @@ int __kprobes arch_prepare_optimized_kprobe(struct optimized_kprobe *op)
         return 0;
 }
 
-/* Replace a breakpoint (int3) with a relative jump.  */
-int __kprobes arch_optimize_kprobe(struct optimized_kprobe *op)
+#define MAX_OPTIMIZE_PROBES 256
+static struct text_poke_param *jump_poke_params;
+static struct jump_poke_buffer {
+        u8 buf[RELATIVEJUMP_SIZE];
+} *jump_poke_bufs;
+
+static void __kprobes setup_optimize_kprobe(struct text_poke_param *tprm,
+                                            u8 *insn_buf,
+                                            struct optimized_kprobe *op)
 {
-        unsigned char jmp_code[RELATIVEJUMP_SIZE];
         s32 rel = (s32)((long)op->optinsn.insn -
                         ((long)op->kp.addr + RELATIVEJUMP_SIZE));
 
@@ -1412,16 +1422,79 @@ int __kprobes arch_optimize_kprobe(struct optimized_kprobe *op)
         memcpy(op->optinsn.copied_insn, op->kp.addr + INT3_SIZE,
                RELATIVE_ADDR_SIZE);
 
-        jmp_code[0] = RELATIVEJUMP_OPCODE;
-        *(s32 *)(&jmp_code[1]) = rel;
+        insn_buf[0] = RELATIVEJUMP_OPCODE;
+        *(s32 *)(&insn_buf[1]) = rel;
+
+        tprm->addr = op->kp.addr;
+        tprm->opcode = insn_buf;
+        tprm->len = RELATIVEJUMP_SIZE;
+}
+
+/*
+ * Replace breakpoints (int3) with relative jumps.
+ * Caller must call with locking kprobe_mutex and text_mutex.
+ */
+void __kprobes arch_optimize_kprobes(struct list_head *oplist)
+{
+        struct optimized_kprobe *op, *tmp;
+        int c = 0;
+
+        list_for_each_entry_safe(op, tmp, oplist, list) {
+                WARN_ON(kprobe_disabled(&op->kp));
+                /* Setup param */
+                setup_optimize_kprobe(&jump_poke_params[c],
+                                      jump_poke_bufs[c].buf, op);
+                list_del_init(&op->list);
+                if (++c >= MAX_OPTIMIZE_PROBES)
+                        break;
+        }
 
         /*
          * text_poke_smp doesn't support NMI/MCE code modifying.
          * However, since kprobes itself also doesn't support NMI/MCE
          * code probing, it's not a problem.
          */
-        text_poke_smp(op->kp.addr, jmp_code, RELATIVEJUMP_SIZE);
-        return 0;
+        text_poke_smp_batch(jump_poke_params, c);
+}
+
+static void __kprobes setup_unoptimize_kprobe(struct text_poke_param *tprm,
+                                              u8 *insn_buf,
+                                              struct optimized_kprobe *op)
+{
+        /* Set int3 to first byte for kprobes */
+        insn_buf[0] = BREAKPOINT_INSTRUCTION;
+        memcpy(insn_buf + 1, op->optinsn.copied_insn, RELATIVE_ADDR_SIZE);
+
+        tprm->addr = op->kp.addr;
+        tprm->opcode = insn_buf;
+        tprm->len = RELATIVEJUMP_SIZE;
+}
+
+/*
+ * Recover original instructions and breakpoints from relative jumps.
+ * Caller must call with locking kprobe_mutex.
+ */
+extern void arch_unoptimize_kprobes(struct list_head *oplist,
+                                    struct list_head *done_list)
+{
+        struct optimized_kprobe *op, *tmp;
+        int c = 0;
+
+        list_for_each_entry_safe(op, tmp, oplist, list) {
+                /* Setup param */
+                setup_unoptimize_kprobe(&jump_poke_params[c],
+                                        jump_poke_bufs[c].buf, op);
+                list_move(&op->list, done_list);
+                if (++c >= MAX_OPTIMIZE_PROBES)
+                        break;
+        }
+
+        /*
+         * text_poke_smp doesn't support NMI/MCE code modifying.
+         * However, since kprobes itself also doesn't support NMI/MCE
+         * code probing, it's not a problem.
+         */
+        text_poke_smp_batch(jump_poke_params, c);
 }
 
 /* Replace a relative jump with a breakpoint (int3).  */
@@ -1453,11 +1526,35 @@ static int  __kprobes setup_detour_execution(struct kprobe *p,
         }
         return 0;
 }
+
+static int __kprobes init_poke_params(void)
+{
+        /* Allocate code buffer and parameter array */
+        jump_poke_bufs = kmalloc(sizeof(struct jump_poke_buffer) *
+                                 MAX_OPTIMIZE_PROBES, GFP_KERNEL);
+        if (!jump_poke_bufs)
+                return -ENOMEM;
+
+        jump_poke_params = kmalloc(sizeof(struct text_poke_param) *
+                                   MAX_OPTIMIZE_PROBES, GFP_KERNEL);
+        if (!jump_poke_params) {
+                kfree(jump_poke_bufs);
+                jump_poke_bufs = NULL;
+                return -ENOMEM;
+        }
+
+        return 0;
+}
+#else   /* !CONFIG_OPTPROBES */
+static int __kprobes init_poke_params(void)
+{
+        return 0;
+}
 #endif
 
 int __init arch_init_kprobes(void)
 {
-        return 0;
+        return init_poke_params();
 }
 
 int __kprobes arch_trampoline_kprobe(struct kprobe *p)
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index ce0cb4721c9a..0fe6d1a66c38 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -155,12 +155,6 @@ static int apply_microcode_amd(int cpu)
         return 0;
 }
 
-static int get_ucode_data(void *to, const u8 *from, size_t n)
-{
-        memcpy(to, from, n);
-        return 0;
-}
-
 static void *
 get_next_ucode(const u8 *buf, unsigned int size, unsigned int *mc_size)
 {
@@ -168,8 +162,7 @@ get_next_ucode(const u8 *buf, unsigned int size, unsigned int *mc_size)
         u8 section_hdr[UCODE_CONTAINER_SECTION_HDR];
         void *mc;
 
-        if (get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR))
-                return NULL;
+        get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR);
 
         if (section_hdr[0] != UCODE_UCODE_TYPE) {
                 pr_err("error: invalid type field in container file section header\n");
@@ -183,16 +176,13 @@ get_next_ucode(const u8 *buf, unsigned int size, unsigned int *mc_size)
                 return NULL;
         }
 
-        mc = vmalloc(UCODE_MAX_SIZE);
-        if (mc) {
-                memset(mc, 0, UCODE_MAX_SIZE);
-                if (get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR,
-                                   total_size)) {
-                        vfree(mc);
-                        mc = NULL;
-                } else
-                        *mc_size = total_size + UCODE_CONTAINER_SECTION_HDR;
-        }
+        mc = vzalloc(UCODE_MAX_SIZE);
+        if (!mc)
+                return NULL;
+
+        get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, total_size);
+        *mc_size = total_size + UCODE_CONTAINER_SECTION_HDR;
+
         return mc;
 }
 
@@ -202,8 +192,7 @@ static int install_equiv_cpu_table(const u8 *buf)
         unsigned int *buf_pos = (unsigned int *)container_hdr;
         unsigned long size;
 
-        if (get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE))
-                return 0;
+        get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE);
 
         size = buf_pos[2];
 
@@ -219,10 +208,7 @@ static int install_equiv_cpu_table(const u8 *buf)
         }
 
         buf += UCODE_CONTAINER_HEADER_SIZE;
-        if (get_ucode_data(equiv_cpu_table, buf, size)) {
-                vfree(equiv_cpu_table);
-                return 0;
-        }
+        get_ucode_data(equiv_cpu_table, buf, size);
 
         return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */
 }
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 9af64d9c4b67..01b0f6d06451 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -118,21 +118,8 @@ static void __init MP_bus_info(struct mpc_bus *m)
 
 static void __init MP_ioapic_info(struct mpc_ioapic *m)
 {
-        if (!(m->flags & MPC_APIC_USABLE))
-                return;
-
-        printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
-               m->apicid, m->apicver, m->apicaddr);
-
-        mp_register_ioapic(m->apicid, m->apicaddr, gsi_top);
-}
-
-static void print_MP_intsrc_info(struct mpc_intsrc *m)
-{
-        apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
-                " IRQ %02x, APIC ID %x, APIC INT %02x\n",
-                m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
-                m->srcbusirq, m->dstapic, m->dstirq);
+        if (m->flags & MPC_APIC_USABLE)
+                mp_register_ioapic(m->apicid, m->apicaddr, gsi_top);
 }
 
 static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq)
@@ -144,73 +131,11 @@ static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq)
                 mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq);
 }
 
-static void __init assign_to_mp_irq(struct mpc_intsrc *m,
-                                    struct mpc_intsrc *mp_irq)
-{
-        mp_irq->dstapic = m->dstapic;
-        mp_irq->type = m->type;
-        mp_irq->irqtype = m->irqtype;
-        mp_irq->irqflag = m->irqflag;
-        mp_irq->srcbus = m->srcbus;
-        mp_irq->srcbusirq = m->srcbusirq;
-        mp_irq->dstirq = m->dstirq;
-}
-
-static void __init assign_to_mpc_intsrc(struct mpc_intsrc *mp_irq,
-                                        struct mpc_intsrc *m)
-{
-        m->dstapic = mp_irq->dstapic;
-        m->type = mp_irq->type;
-        m->irqtype = mp_irq->irqtype;
-        m->irqflag = mp_irq->irqflag;
-        m->srcbus = mp_irq->srcbus;
-        m->srcbusirq = mp_irq->srcbusirq;
-        m->dstirq = mp_irq->dstirq;
-}
-
-static int __init mp_irq_mpc_intsrc_cmp(struct mpc_intsrc *mp_irq,
-                                        struct mpc_intsrc *m)
-{
-        if (mp_irq->dstapic != m->dstapic)
-                return 1;
-        if (mp_irq->type != m->type)
-                return 2;
-        if (mp_irq->irqtype != m->irqtype)
-                return 3;
-        if (mp_irq->irqflag != m->irqflag)
-                return 4;
-        if (mp_irq->srcbus != m->srcbus)
-                return 5;
-        if (mp_irq->srcbusirq != m->srcbusirq)
-                return 6;
-        if (mp_irq->dstirq != m->dstirq)
-                return 7;
-
-        return 0;
-}
-
-static void __init MP_intsrc_info(struct mpc_intsrc *m)
-{
-        int i;
-
-        print_MP_intsrc_info(m);
-
-        for (i = 0; i < mp_irq_entries; i++) {
-                if (!mp_irq_mpc_intsrc_cmp(&mp_irqs[i], m))
-                        return;
-        }
-
-        assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
-        if (++mp_irq_entries == MAX_IRQ_SOURCES)
-                panic("Max # of irq sources exceeded!!\n");
-}
 #else /* CONFIG_X86_IO_APIC */
 static inline void __init MP_bus_info(struct mpc_bus *m) {}
 static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {}
-static inline void __init MP_intsrc_info(struct mpc_intsrc *m) {}
 #endif /* CONFIG_X86_IO_APIC */
 
-
 static void __init MP_lintsrc_info(struct mpc_lintsrc *m)
 {
         apic_printk(APIC_VERBOSE, "Lint: type %d, pol %d, trig %d, bus %02x,"
@@ -222,7 +147,6 @@ static void __init MP_lintsrc_info(struct mpc_lintsrc *m)
 /*
  * Read/parse the MPC
  */
-
 static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str)
 {
 
@@ -275,18 +199,6 @@ static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt)
 
 void __init default_smp_read_mpc_oem(struct mpc_table *mpc) { }
 
-static void __init smp_register_lapic_address(unsigned long address)
-{
-        mp_lapic_addr = address;
-
-        set_fixmap_nocache(FIX_APIC_BASE, address);
-        if (boot_cpu_physical_apicid == -1U) {
-                boot_cpu_physical_apicid  = read_apic_id();
-                apic_version[boot_cpu_physical_apicid] =
-                         GET_APIC_VERSION(apic_read(APIC_LVR));
-        }
-}
-
 static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
 {
         char str[16];
@@ -301,17 +213,13 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
 #ifdef CONFIG_X86_32
         generic_mps_oem_check(mpc, oem, str);
 #endif
-        /* save the local APIC address, it might be non-default */
+        /* Initialize the lapic mapping */
         if (!acpi_lapic)
-                mp_lapic_addr = mpc->lapic;
+                register_lapic_address(mpc->lapic);
 
         if (early)
                 return 1;
 
-        /* Initialize the lapic mapping */
-        if (!acpi_lapic)
-                smp_register_lapic_address(mpc->lapic);
-
         if (mpc->oemptr)
                 x86_init.mpparse.smp_read_mpc_oem(mpc);
 
@@ -337,7 +245,7 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
                         skip_entry(&mpt, &count, sizeof(struct mpc_ioapic));
                         break;
                 case MP_INTSRC:
-                        MP_intsrc_info((struct mpc_intsrc *)mpt);
+                        mp_save_irq((struct mpc_intsrc *)mpt);
                         skip_entry(&mpt, &count, sizeof(struct mpc_intsrc));
                         break;
                 case MP_LINTSRC:
@@ -429,13 +337,13 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
 
                 intsrc.srcbusirq = i;
                 intsrc.dstirq = i ? i : 2;      /* IRQ0 to INTIN2 */
-                MP_intsrc_info(&intsrc);
+                mp_save_irq(&intsrc);
         }
 
         intsrc.irqtype = mp_ExtINT;
         intsrc.srcbusirq = 0;
         intsrc.dstirq = 0;      /* 8259A to INTIN0 */
-        MP_intsrc_info(&intsrc);
+        mp_save_irq(&intsrc);
 }
 
 
@@ -784,11 +692,11 @@ static void __init check_irq_src(struct mpc_intsrc *m, int *nr_m_spare)
         int i;
 
         apic_printk(APIC_VERBOSE, "OLD ");
-        print_MP_intsrc_info(m);
+        print_mp_irq_info(m);
 
         i = get_MP_intsrc_index(m);
         if (i > 0) {
-                assign_to_mpc_intsrc(&mp_irqs[i], m);
+                memcpy(m, &mp_irqs[i], sizeof(*m));
                 apic_printk(APIC_VERBOSE, "NEW ");
                 print_mp_irq_info(&mp_irqs[i]);
                 return;
@@ -875,14 +783,14 @@ static int  __init replace_intsrc_all(struct mpc_table *mpc,
                 if (nr_m_spare > 0) {
                         apic_printk(APIC_VERBOSE, "*NEW* found\n");
                         nr_m_spare--;
-                        assign_to_mpc_intsrc(&mp_irqs[i], m_spare[nr_m_spare]);
+                        memcpy(m_spare[nr_m_spare], &mp_irqs[i], sizeof(mp_irqs[i]));
                         m_spare[nr_m_spare] = NULL;
                 } else {
                         struct mpc_intsrc *m = (struct mpc_intsrc *)mpt;
                         count += sizeof(struct mpc_intsrc);
                         if (check_slot(mpc_new_phys, mpc_new_length, count) < 0)
                                 goto out;
-                        assign_to_mpc_intsrc(&mp_irqs[i], m);
+                        memcpy(m, &mp_irqs[i], sizeof(*m));
                         mpc->length = count;
                         mpt += sizeof(struct mpc_intsrc);
                 }
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index ba0f0ca9f280..c01ffa5b9b87 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -143,7 +143,7 @@ static void flush_gart(void)
 
         spin_lock_irqsave(&iommu_bitmap_lock, flags);
         if (need_flush) {
-                k8_flush_garts();
+                amd_flush_garts();
                 need_flush = false;
         }
         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
@@ -561,17 +561,17 @@ static void enable_gart_translations(void)
 {
         int i;
 
-        if (!k8_northbridges.gart_supported)
+        if (!amd_nb_has_feature(AMD_NB_GART))
                 return;
 
-        for (i = 0; i < k8_northbridges.num; i++) {
-                struct pci_dev *dev = k8_northbridges.nb_misc[i];
+        for (i = 0; i < amd_nb_num(); i++) {
+                struct pci_dev *dev = node_to_amd_nb(i)->misc;
 
                 enable_gart_translation(dev, __pa(agp_gatt_table));
         }
 
         /* Flush the GART-TLB to remove stale entries */
-        k8_flush_garts();
+        amd_flush_garts();
 }
 
 /*
@@ -596,13 +596,13 @@ static void gart_fixup_northbridges(struct sys_device *dev)
         if (!fix_up_north_bridges)
                 return;
 
-        if (!k8_northbridges.gart_supported)
+        if (!amd_nb_has_feature(AMD_NB_GART))
                 return;
 
         pr_info("PCI-DMA: Restoring GART aperture settings\n");
 
-        for (i = 0; i < k8_northbridges.num; i++) {
-                struct pci_dev *dev = k8_northbridges.nb_misc[i];
+        for (i = 0; i < amd_nb_num(); i++) {
+                struct pci_dev *dev = node_to_amd_nb(i)->misc;
 
                 /*
                  * Don't enable translations just yet.  That is the next
@@ -644,7 +644,7 @@ static struct sys_device device_gart = {
  * Private Northbridge GATT initialization in case we cannot use the
  * AGP driver for some reason.
  */
-static __init int init_k8_gatt(struct agp_kern_info *info)
+static __init int init_amd_gatt(struct agp_kern_info *info)
 {
         unsigned aper_size, gatt_size, new_aper_size;
         unsigned aper_base, new_aper_base;
@@ -656,8 +656,8 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
 
         aper_size = aper_base = info->aper_size = 0;
         dev = NULL;
-        for (i = 0; i < k8_northbridges.num; i++) {
-                dev = k8_northbridges.nb_misc[i];
+        for (i = 0; i < amd_nb_num(); i++) {
+                dev = node_to_amd_nb(i)->misc;
                 new_aper_base = read_aperture(dev, &new_aper_size);
                 if (!new_aper_base)
                         goto nommu;
@@ -725,13 +725,13 @@ static void gart_iommu_shutdown(void)
         if (!no_agp)
                 return;
 
-        if (!k8_northbridges.gart_supported)
+        if (!amd_nb_has_feature(AMD_NB_GART))
                 return;
 
-        for (i = 0; i < k8_northbridges.num; i++) {
+        for (i = 0; i < amd_nb_num(); i++) {
                 u32 ctl;
 
-                dev = k8_northbridges.nb_misc[i];
+                dev = node_to_amd_nb(i)->misc;
                 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
 
                 ctl &= ~GARTEN;
@@ -749,14 +749,14 @@ int __init gart_iommu_init(void)
         unsigned long scratch;
         long i;
 
-        if (!k8_northbridges.gart_supported)
+        if (!amd_nb_has_feature(AMD_NB_GART))
                 return 0;
 
 #ifndef CONFIG_AGP_AMD64
         no_agp = 1;
 #else
         /* Makefile puts PCI initialization via subsys_initcall first. */
-        /* Add other K8 AGP bridge drivers here */
+        /* Add other AMD AGP bridge drivers here */
         no_agp = no_agp ||
                 (agp_amd64_init() < 0) ||
                 (agp_copy_info(agp_bridge, &info) < 0);
@@ -765,7 +765,7 @@ int __init gart_iommu_init(void)
         if (no_iommu ||
             (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
             !gart_iommu_aperture ||
-            (no_agp && init_k8_gatt(&info) < 0)) {
+            (no_agp && init_amd_gatt(&info) < 0)) {
                 if (max_pfn > MAX_DMA32_PFN) {
                         pr_warning("More than 4GB of memory but GART IOMMU not available.\n");
                         pr_warning("falling back to iommu=soft.\n");
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index b6472153e45b..7c23a0cd3eb9 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -86,8 +86,7 @@ void exit_thread(void)
 void show_regs(struct pt_regs *regs)
 {
         show_registers(regs);
-        show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs),
-                   regs->bp);
+        show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs));
 }
 
 void show_regs_common(void)
@@ -369,6 +368,7 @@ void default_idle(void)
 {
         if (hlt_use_halt()) {
                 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
+                trace_cpu_idle(1, smp_processor_id());
                 current_thread_info()->status &= ~TS_POLLING;
                 /*
                  * TS_POLLING-cleared state must be visible before we
@@ -439,8 +439,9 @@ EXPORT_SYMBOL_GPL(cpu_idle_wait);
 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
 {
         trace_power_start(POWER_CSTATE, (ax>>4)+1, smp_processor_id());
+        trace_cpu_idle((ax>>4)+1, smp_processor_id());
         if (!need_resched()) {
-                if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
+                if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLUSH_MONITOR))
                         clflush((void *)&current_thread_info()->flags);
 
                 __monitor((void *)&current_thread_info()->flags, 0, 0);
@@ -455,7 +456,8 @@ static void mwait_idle(void)
 {
         if (!need_resched()) {
                 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
-                if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
+                trace_cpu_idle(1, smp_processor_id());
+                if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLUSH_MONITOR))
                         clflush((void *)&current_thread_info()->flags);
 
                 __monitor((void *)&current_thread_info()->flags, 0, 0);
@@ -476,10 +478,12 @@ static void mwait_idle(void)
 static void poll_idle(void)
 {
         trace_power_start(POWER_CSTATE, 0, smp_processor_id());
+        trace_cpu_idle(0, smp_processor_id());
         local_irq_enable();
         while (!need_resched())
                 cpu_relax();
-        trace_power_end(0);
+        trace_power_end(smp_processor_id());
+        trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 }
 
 /*
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 96586c3cbbbf..4b9befa0e347 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -113,8 +113,8 @@ void cpu_idle(void)
                         stop_critical_timings();
                         pm_idle();
                         start_critical_timings();
-
                         trace_power_end(smp_processor_id());
+                        trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
                 }
                 tick_nohz_restart_sched_tick();
                 preempt_enable_no_resched();
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index b3d7a3a04f38..4c818a738396 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -142,6 +142,8 @@ void cpu_idle(void)
                         start_critical_timings();
 
                         trace_power_end(smp_processor_id());
+                        trace_cpu_idle(PWR_EVENT_EXIT,
+                                       smp_processor_id());
 
                         /* In many cases the interrupt that ended idle
                            has already called exit_idle. But some idle
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index c495aa8d4815..fc7aae1e2bc7 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -18,6 +18,7 @@
 #include <asm/pci_x86.h>
 #include <asm/virtext.h>
 #include <asm/cpu.h>
+#include <asm/nmi.h>
 
 #ifdef CONFIG_X86_32
 # include <linux/ctype.h>
@@ -747,7 +748,7 @@ static int crash_nmi_callback(struct notifier_block *self,
 {
         int cpu;
 
-        if (val != DIE_NMI_IPI)
+        if (val != DIE_NMI)
                 return NOTIFY_OK;
 
         cpu = raw_smp_processor_id();
@@ -778,6 +779,8 @@ static void smp_send_nmi_allbutself(void)
 
 static struct notifier_block crash_nmi_nb = {
         .notifier_call = crash_nmi_callback,
+        /* we want to be the first one called */
+        .priority = NMI_LOCAL_HIGH_PRIOR+1,
 };
 
 /* Halt all other CPUs, calling the specified function on each of them
diff --git a/arch/x86/kernel/reboot_fixups_32.c b/arch/x86/kernel/reboot_fixups_32.c
index fda313ebbb03..c8e41e90f59c 100644
--- a/arch/x86/kernel/reboot_fixups_32.c
+++ b/arch/x86/kernel/reboot_fixups_32.c
@@ -43,17 +43,33 @@ static void rdc321x_reset(struct pci_dev *dev)
         outb(1, 0x92);
 }
 
+static void ce4100_reset(struct pci_dev *dev)
+{
+        int i;
+
+        for (i = 0; i < 10; i++) {
+                outb(0x2, 0xcf9);
+                udelay(50);
+        }
+}
+
 struct device_fixup {
         unsigned int vendor;
         unsigned int device;
         void (*reboot_fixup)(struct pci_dev *);
 };
 
+/*
+ * PCI ids solely used for fixups_table go here
+ */
+#define PCI_DEVICE_ID_INTEL_CE4100      0x0708
+
 static const struct device_fixup fixups_table[] = {
 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, cs5530a_warm_reset },
 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, cs5536_warm_reset },
 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE, cs5530a_warm_reset },
 { PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6030, rdc321x_reset },
+{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100, ce4100_reset },
 };
 
 /*
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index a0f52af256a0..d3cfe26c0252 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -705,7 +705,7 @@ static u64 __init get_max_mapped(void)
 void __init setup_arch(char **cmdline_p)
 {
         int acpi = 0;
-        int k8 = 0;
+        int amd = 0;
         unsigned long flags;
 
 #ifdef CONFIG_X86_32
@@ -991,12 +991,12 @@ void __init setup_arch(char **cmdline_p)
         acpi = acpi_numa_init();
 #endif
 
-#ifdef CONFIG_K8_NUMA
+#ifdef CONFIG_AMD_NUMA
         if (!acpi)
-                k8 = !k8_numa_init(0, max_pfn);
+                amd = !amd_numa_init(0, max_pfn);
 #endif
 
-        initmem_init(0, max_pfn, acpi, k8);
+        initmem_init(0, max_pfn, acpi, amd);
         memblock_find_dma_reserve();
         dma32_reserve_bootmem();
 
@@ -1045,10 +1045,7 @@ void __init setup_arch(char **cmdline_p)
 #endif
 
         init_apic_mappings();
-        ioapic_init_mappings();
-
-        /* need to wait for io_apic is mapped */
-        probe_nr_irqs_gsi();
+        ioapic_and_gsi_init();
 
         kvm_guest_init();
 
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 083e99d1b7df..763df77343dd 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -97,12 +97,12 @@ static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
  */
 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
 
-void cpu_hotplug_driver_lock()
+void cpu_hotplug_driver_lock(void)
 {
         mutex_lock(&x86_cpu_hotplug_driver_mutex);
 }
 
-void cpu_hotplug_driver_unlock()
+void cpu_hotplug_driver_unlock(void)
 {
         mutex_unlock(&x86_cpu_hotplug_driver_mutex);
 }
@@ -281,6 +281,13 @@ static void __cpuinit smp_callin(void)
          */
         smp_store_cpu_info(cpuid);
 
+        /*
+         * This must be done before setting cpu_online_mask
+         * or calling notify_cpu_starting.
+         */
+        set_cpu_sibling_map(raw_smp_processor_id());
+        wmb();
+
         notify_cpu_starting(cpuid);
 
         /*
@@ -316,16 +323,6 @@ notrace static void __cpuinit start_secondary(void *unused)
          */
         check_tsc_sync_target();
 
-        if (nmi_watchdog == NMI_IO_APIC) {
-                legacy_pic->mask(0);
-                enable_NMI_through_LVT0();
-                legacy_pic->unmask(0);
-        }
-
-        /* This must be done before setting cpu_online_mask */
-        set_cpu_sibling_map(raw_smp_processor_id());
-        wmb();
-
         /*
          * We need to hold call_lock, so there is no inconsistency
          * between the time smp_call_function() determines number of
@@ -430,7 +427,7 @@ void __cpuinit set_cpu_sibling_map(int cpu)
 
         cpumask_set_cpu(cpu, c->llc_shared_map);
 
-        if (current_cpu_data.x86_max_cores == 1) {
+        if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
                 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
                 c->booted_cores = 1;
                 return;
@@ -1061,8 +1058,6 @@ static int __init smp_sanity_check(unsigned max_cpus)
                 printk(KERN_INFO "SMP mode deactivated.\n");
                 smpboot_clear_io_apic();
 
-                localise_nmi_watchdog();
-
                 connect_bsp_APIC();
                 setup_local_APIC();
                 end_local_APIC_setup();
@@ -1094,7 +1089,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
 
         preempt_disable();
         smp_cpu_index_default();
-        current_cpu_data = boot_cpu_data;
+        memcpy(__this_cpu_ptr(&cpu_info), &boot_cpu_data, sizeof(cpu_info));
         cpumask_copy(cpu_callin_mask, cpumask_of(0));
         mb();
         /*
@@ -1166,6 +1161,20 @@ out:
         preempt_enable();
 }
 
+void arch_disable_nonboot_cpus_begin(void)
+{
+        /*
+         * Avoid the smp alternatives switch during the disable_nonboot_cpus().
+         * In the suspend path, we will be back in the SMP mode shortly anyways.
+         */
+        skip_smp_alternatives = true;
+}
+
+void arch_disable_nonboot_cpus_end(void)
+{
+        skip_smp_alternatives = false;
+}
+
 void arch_enable_nonboot_cpus_begin(void)
 {
         set_mtrr_aps_delayed_init();
@@ -1196,7 +1205,6 @@ void __init native_smp_cpus_done(unsigned int max_cpus)
 #ifdef CONFIG_X86_IO_APIC
         setup_ioapic_dest();
 #endif
-        check_nmi_watchdog();
         mtrr_aps_init();
 }
 
@@ -1341,8 +1349,6 @@ int native_cpu_disable(void)
         if (cpu == 0)
                 return -EBUSY;
 
-        if (nmi_watchdog == NMI_LOCAL_APIC)
-                stop_apic_nmi_watchdog(NULL);
         clear_local_APIC();
 
         cpu_disable_common();
@@ -1377,7 +1383,7 @@ void play_dead_common(void)
 
         mb();
         /* Ack it */
-        __get_cpu_var(cpu_state) = CPU_DEAD;
+        __this_cpu_write(cpu_state, CPU_DEAD);
 
         /*
          * With physical CPU hotplug, we should halt the cpu
@@ -1397,11 +1403,11 @@ static inline void mwait_play_dead(void)
         int i;
         void *mwait_ptr;
 
-        if (!cpu_has(&current_cpu_data, X86_FEATURE_MWAIT))
+        if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_MWAIT))
                 return;
-        if (!cpu_has(&current_cpu_data, X86_FEATURE_CLFLSH))
+        if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLSH))
                 return;
-        if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
+        if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
                 return;
 
         eax = CPUID_MWAIT_LEAF;
@@ -1452,7 +1458,7 @@ static inline void mwait_play_dead(void)
 
 static inline void hlt_play_dead(void)
 {
-        if (current_cpu_data.x86 >= 4)
+        if (__this_cpu_read(cpu_info.x86) >= 4)
                 wbinvd();
 
         while (1) {
diff --git a/arch/x86/kernel/stacktrace.c b/arch/x86/kernel/stacktrace.c
index b53c525368a7..938c8e10a19a 100644
--- a/arch/x86/kernel/stacktrace.c
+++ b/arch/x86/kernel/stacktrace.c
@@ -73,22 +73,22 @@ static const struct stacktrace_ops save_stack_ops_nosched = {
  */
 void save_stack_trace(struct stack_trace *trace)
 {
-        dump_trace(current, NULL, NULL, 0, &save_stack_ops, trace);
+        dump_trace(current, NULL, NULL, &save_stack_ops, trace);
         if (trace->nr_entries < trace->max_entries)
                 trace->entries[trace->nr_entries++] = ULONG_MAX;
 }
 EXPORT_SYMBOL_GPL(save_stack_trace);
 
-void save_stack_trace_bp(struct stack_trace *trace, unsigned long bp)
+void save_stack_trace_regs(struct stack_trace *trace, struct pt_regs *regs)
 {
-        dump_trace(current, NULL, NULL, bp, &save_stack_ops, trace);
+        dump_trace(current, regs, NULL, &save_stack_ops, trace);
         if (trace->nr_entries < trace->max_entries)
                 trace->entries[trace->nr_entries++] = ULONG_MAX;
 }
 
 void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
 {
-        dump_trace(tsk, NULL, NULL, 0, &save_stack_ops_nosched, trace);
+        dump_trace(tsk, NULL, NULL, &save_stack_ops_nosched, trace);
         if (trace->nr_entries < trace->max_entries)
                 trace->entries[trace->nr_entries++] = ULONG_MAX;
 }
diff --git a/arch/x86/kernel/time.c b/arch/x86/kernel/time.c
index fb5cc5e14cfa..25a28a245937 100644
--- a/arch/x86/kernel/time.c
+++ b/arch/x86/kernel/time.c
@@ -22,10 +22,6 @@
 #include <asm/hpet.h>
 #include <asm/time.h>
 
-#if defined(CONFIG_X86_32) && defined(CONFIG_X86_IO_APIC)
-int timer_ack;
-#endif
-
 #ifdef CONFIG_X86_64
 volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES;
 #endif
@@ -63,20 +59,6 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
         /* Keep nmi watchdog up to date */
         inc_irq_stat(irq0_irqs);
 
-        /* Optimized out for !IO_APIC and x86_64 */
-        if (timer_ack) {
-                /*
-                 * Subtle, when I/O APICs are used we have to ack timer IRQ
-                 * manually to deassert NMI lines for the watchdog if run
-                 * on an 82489DX-based system.
-                 */
-                raw_spin_lock(&i8259A_lock);
-                outb(0x0c, PIC_MASTER_OCW3);
-                /* Ack the IRQ; AEOI will end it automatically. */
-                inb(PIC_MASTER_POLL);
-                raw_spin_unlock(&i8259A_lock);
-        }
-
         global_clock_event->event_handler(global_clock_event);
 
         /* MCA bus quirk: Acknowledge irq0 by setting bit 7 in port 0x61 */
diff --git a/arch/x86/kernel/trampoline_64.S b/arch/x86/kernel/trampoline_64.S
index 3af2dff58b21..075d130efcf9 100644
--- a/arch/x86/kernel/trampoline_64.S
+++ b/arch/x86/kernel/trampoline_64.S
@@ -127,7 +127,7 @@ startup_64:
 no_longmode:
         hlt
         jmp no_longmode
-#include "verify_cpu_64.S"
+#include "verify_cpu.S"
 
         # Careful these need to be in the same 64K segment as the above;
 tidt:
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index cb838ca42c96..b9b67166f9de 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -83,6 +83,13 @@ EXPORT_SYMBOL_GPL(used_vectors);
 
 static int ignore_nmis;
 
+int unknown_nmi_panic;
+/*
+ * Prevent NMI reason port (0x61) being accessed simultaneously, can
+ * only be used in NMI handler.
+ */
+static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
+
 static inline void conditional_sti(struct pt_regs *regs)
 {
         if (regs->flags & X86_EFLAGS_IF)
@@ -300,16 +307,23 @@ gp_in_kernel:
         die("general protection fault", regs, error_code);
 }
 
-static notrace __kprobes void
-mem_parity_error(unsigned char reason, struct pt_regs *regs)
+static int __init setup_unknown_nmi_panic(char *str)
 {
-        printk(KERN_EMERG
-                "Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
-                        reason, smp_processor_id());
+        unknown_nmi_panic = 1;
+        return 1;
+}
+__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
 
-        printk(KERN_EMERG
-                "You have some hardware problem, likely on the PCI bus.\n");
+static notrace __kprobes void
+pci_serr_error(unsigned char reason, struct pt_regs *regs)
+{
+        pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
+                 reason, smp_processor_id());
 
+        /*
+         * On some machines, PCI SERR line is used to report memory
+         * errors. EDAC makes use of it.
+         */
 #if defined(CONFIG_EDAC)
         if (edac_handler_set()) {
                 edac_atomic_assert_error();
@@ -320,11 +334,11 @@ mem_parity_error(unsigned char reason, struct pt_regs *regs)
         if (panic_on_unrecovered_nmi)
                 panic("NMI: Not continuing");
 
-        printk(KERN_EMERG "Dazed and confused, but trying to continue\n");
+        pr_emerg("Dazed and confused, but trying to continue\n");
 
-        /* Clear and disable the memory parity error line. */
-        reason = (reason & 0xf) | 4;
-        outb(reason, 0x61);
+        /* Clear and disable the PCI SERR error line. */
+        reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR;
+        outb(reason, NMI_REASON_PORT);
 }
 
 static notrace __kprobes void
@@ -332,22 +346,26 @@ io_check_error(unsigned char reason, struct pt_regs *regs)
 {
         unsigned long i;
 
-        printk(KERN_EMERG "NMI: IOCK error (debug interrupt?)\n");
+        pr_emerg(
+        "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
+                 reason, smp_processor_id());
         show_registers(regs);
 
         if (panic_on_io_nmi)
                 panic("NMI IOCK error: Not continuing");
 
         /* Re-enable the IOCK line, wait for a few seconds */
-        reason = (reason & 0xf) | 8;
-        outb(reason, 0x61);
+        reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK;
+        outb(reason, NMI_REASON_PORT);
 
-        i = 2000;
-        while (--i)
-                udelay(1000);
+        i = 20000;
+        while (--i) {
+                touch_nmi_watchdog();
+                udelay(100);
+        }
 
-        reason &= ~8;
-        outb(reason, 0x61);
+        reason &= ~NMI_REASON_CLEAR_IOCHK;
+        outb(reason, NMI_REASON_PORT);
 }
 
 static notrace __kprobes void
@@ -366,69 +384,50 @@ unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
                 return;
         }
 #endif
-        printk(KERN_EMERG
-                "Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
-                        reason, smp_processor_id());
+        pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
+                 reason, smp_processor_id());
 
-        printk(KERN_EMERG "Do you have a strange power saving mode enabled?\n");
-        if (panic_on_unrecovered_nmi)
+        pr_emerg("Do you have a strange power saving mode enabled?\n");
+        if (unknown_nmi_panic || panic_on_unrecovered_nmi)
                 panic("NMI: Not continuing");
 
-        printk(KERN_EMERG "Dazed and confused, but trying to continue\n");
+        pr_emerg("Dazed and confused, but trying to continue\n");
 }
 
 static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
 {
         unsigned char reason = 0;
-        int cpu;
 
-        cpu = smp_processor_id();
-
-        /* Only the BSP gets external NMIs from the system. */
-        if (!cpu)
-                reason = get_nmi_reason();
-
-        if (!(reason & 0xc0)) {
-                if (notify_die(DIE_NMI_IPI, "nmi_ipi", regs, reason, 2, SIGINT)
-                                                                == NOTIFY_STOP)
-                        return;
+        /*
+         * CPU-specific NMI must be processed before non-CPU-specific
+         * NMI, otherwise we may lose it, because the CPU-specific
+         * NMI can not be detected/processed on other CPUs.
+         */
+        if (notify_die(DIE_NMI, "nmi", regs, 0, 2, SIGINT) == NOTIFY_STOP)
+                return;
 
-#ifdef CONFIG_X86_LOCAL_APIC
-                if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
-                                                        == NOTIFY_STOP)
-                        return;
+        /* Non-CPU-specific NMI: NMI sources can be processed on any CPU */
+        raw_spin_lock(&nmi_reason_lock);
+        reason = get_nmi_reason();
 
-#ifndef CONFIG_LOCKUP_DETECTOR
+        if (reason & NMI_REASON_MASK) {
+                if (reason & NMI_REASON_SERR)
+                        pci_serr_error(reason, regs);
+                else if (reason & NMI_REASON_IOCHK)
+                        io_check_error(reason, regs);
+#ifdef CONFIG_X86_32
                 /*
-                 * Ok, so this is none of the documented NMI sources,
-                 * so it must be the NMI watchdog.
+                 * Reassert NMI in case it became active
+                 * meanwhile as it's edge-triggered:
                  */
-                if (nmi_watchdog_tick(regs, reason))
-                        return;
-                if (!do_nmi_callback(regs, cpu))
-#endif /* !CONFIG_LOCKUP_DETECTOR */
-                        unknown_nmi_error(reason, regs);
-#else
-                unknown_nmi_error(reason, regs);
+                reassert_nmi();
 #endif
-
+                raw_spin_unlock(&nmi_reason_lock);
                 return;
         }
-        if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP)
-                return;
+        raw_spin_unlock(&nmi_reason_lock);
 
-        /* AK: following checks seem to be broken on modern chipsets. FIXME */
-        if (reason & 0x80)
-                mem_parity_error(reason, regs);
-        if (reason & 0x40)
-                io_check_error(reason, regs);
-#ifdef CONFIG_X86_32
-        /*
-         * Reassert NMI in case it became active meanwhile
-         * as it's edge-triggered:
-         */
-        reassert_nmi();
-#endif
+        unknown_nmi_error(reason, regs);
 }
 
 dotraplinkage notrace __kprobes void
@@ -446,14 +445,12 @@ do_nmi(struct pt_regs *regs, long error_code)
 
 void stop_nmi(void)
 {
-        acpi_nmi_disable();
         ignore_nmis++;
 }
 
 void restart_nmi(void)
 {
         ignore_nmis--;
-        acpi_nmi_enable();
 }
 
 /* May run on IST stack. */
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 0c40d8b72416..823f79a17ad1 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -659,7 +659,7 @@ void restore_sched_clock_state(void)
 
         local_irq_save(flags);
 
-        __get_cpu_var(cyc2ns_offset) = 0;
+        __this_cpu_write(cyc2ns_offset, 0);
         offset = cyc2ns_suspend - sched_clock();
 
         for_each_possible_cpu(cpu)
@@ -872,6 +872,9 @@ __cpuinit int unsynchronized_tsc(void)
 
         if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
                 return 0;
+
+        if (tsc_clocksource_reliable)
+                return 0;
         /*
          * Intel systems are normally all synchronized.
          * Exceptions must mark TSC as unstable:
@@ -879,14 +882,92 @@ __cpuinit int unsynchronized_tsc(void)
         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
                 /* assume multi socket systems are not synchronized: */
                 if (num_possible_cpus() > 1)
-                        tsc_unstable = 1;
+                        return 1;
         }
 
-        return tsc_unstable;
+        return 0;
+}
+
+
+static void tsc_refine_calibration_work(struct work_struct *work);
+static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
+/**
+ * tsc_refine_calibration_work - Further refine tsc freq calibration
+ * @work - ignored.
+ *
+ * This functions uses delayed work over a period of a
+ * second to further refine the TSC freq value. Since this is
+ * timer based, instead of loop based, we don't block the boot
+ * process while this longer calibration is done.
+ *
+ * If there are any calibration anomolies (too many SMIs, etc),
+ * or the refined calibration is off by 1% of the fast early
+ * calibration, we throw out the new calibration and use the
+ * early calibration.
+ */
+static void tsc_refine_calibration_work(struct work_struct *work)
+{
+        static u64 tsc_start = -1, ref_start;
+        static int hpet;
+        u64 tsc_stop, ref_stop, delta;
+        unsigned long freq;
+
+        /* Don't bother refining TSC on unstable systems */
+        if (check_tsc_unstable())
+                goto out;
+
+        /*
+         * Since the work is started early in boot, we may be
+         * delayed the first time we expire. So set the workqueue
+         * again once we know timers are working.
+         */
+        if (tsc_start == -1) {
+                /*
+                 * Only set hpet once, to avoid mixing hardware
+                 * if the hpet becomes enabled later.
+                 */
+                hpet = is_hpet_enabled();
+                schedule_delayed_work(&tsc_irqwork, HZ);
+                tsc_start = tsc_read_refs(&ref_start, hpet);
+                return;
+        }
+
+        tsc_stop = tsc_read_refs(&ref_stop, hpet);
+
+        /* hpet or pmtimer available ? */
+        if (!hpet && !ref_start && !ref_stop)
+                goto out;
+
+        /* Check, whether the sampling was disturbed by an SMI */
+        if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
+                goto out;
+
+        delta = tsc_stop - tsc_start;
+        delta *= 1000000LL;
+        if (hpet)
+                freq = calc_hpet_ref(delta, ref_start, ref_stop);
+        else
+                freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
+
+        /* Make sure we're within 1% */
+        if (abs(tsc_khz - freq) > tsc_khz/100)
+                goto out;
+
+        tsc_khz = freq;
+        printk(KERN_INFO "Refined TSC clocksource calibration: "
+                "%lu.%03lu MHz.\n", (unsigned long)tsc_khz / 1000,
+                                        (unsigned long)tsc_khz % 1000);
+
+out:
+        clocksource_register_khz(&clocksource_tsc, tsc_khz);
 }
 
-static void __init init_tsc_clocksource(void)
+
+static int __init init_tsc_clocksource(void)
 {
+        if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
+                return 0;
+
         if (tsc_clocksource_reliable)
                 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
         /* lower the rating if we already know its unstable: */
@@ -894,8 +975,14 @@ static void __init init_tsc_clocksource(void)
                 clocksource_tsc.rating = 0;
                 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
         }
-        clocksource_register_khz(&clocksource_tsc, tsc_khz);
+        schedule_delayed_work(&tsc_irqwork, 0);
+        return 0;
 }
+/*
+ * We use device_initcall here, to ensure we run after the hpet
+ * is fully initialized, which may occur at fs_initcall time.
+ */
+device_initcall(init_tsc_clocksource);
 
 void __init tsc_init(void)
 {
@@ -949,6 +1036,5 @@ void __init tsc_init(void)
                 mark_tsc_unstable("TSCs unsynchronized");
 
         check_system_tsc_reliable();
-        init_tsc_clocksource();
 }
 
diff --git a/arch/x86/kernel/verify_cpu_64.S b/arch/x86/kernel/verify_cpu.S
index 56a8c2a867d9..0edefc19a113 100644
--- a/arch/x86/kernel/verify_cpu_64.S
+++ b/arch/x86/kernel/verify_cpu.S
@@ -7,6 +7,7 @@
  *      Copyright (c) 2007  Andi Kleen (ak@suse.de)
  *      Copyright (c) 2007  Eric Biederman (ebiederm@xmission.com)
  *      Copyright (c) 2007  Vivek Goyal (vgoyal@in.ibm.com)
+ *      Copyright (c) 2010  Kees Cook (kees.cook@canonical.com)
  *
  *      This source code is licensed under the GNU General Public License,
  *      Version 2.  See the file COPYING for more details.
@@ -14,18 +15,17 @@
  *      This is a common code for verification whether CPU supports
  *      long mode and SSE or not. It is not called directly instead this
  *      file is included at various places and compiled in that context.
- *      Following are the current usage.
+ *      This file is expected to run in 32bit code.  Currently:
  *
- *      This file is included by both 16bit and 32bit code.
+ *      arch/x86/boot/compressed/head_64.S: Boot cpu verification
+ *      arch/x86/kernel/trampoline_64.S: secondary processor verfication
+ *      arch/x86/kernel/head_32.S: processor startup
  *
- *      arch/x86_64/boot/setup.S : Boot cpu verification (16bit)
- *      arch/x86_64/boot/compressed/head.S: Boot cpu verification (32bit)
- *      arch/x86_64/kernel/trampoline.S: secondary processor verfication (16bit)
- *      arch/x86_64/kernel/acpi/wakeup.S:Verfication at resume (16bit)
- *
- *      verify_cpu, returns the status of cpu check in register %eax.
+ *      verify_cpu, returns the status of longmode and SSE in register %eax.
  *              0: Success    1: Failure
  *
+ *      On Intel, the XD_DISABLE flag will be cleared as a side-effect.
+ *
  *      The caller needs to check for the error code and take the action
  *      appropriately. Either display a message or halt.
  */
@@ -62,8 +62,41 @@ verify_cpu:
         cmpl    $0x444d4163,%ecx
         jnz     verify_cpu_noamd
         mov     $1,%di                  # cpu is from AMD
+        jmp     verify_cpu_check
 
 verify_cpu_noamd:
+        cmpl    $0x756e6547,%ebx        # GenuineIntel?
+        jnz     verify_cpu_check
+        cmpl    $0x49656e69,%edx
+        jnz     verify_cpu_check
+        cmpl    $0x6c65746e,%ecx
+        jnz     verify_cpu_check
+
+        # only call IA32_MISC_ENABLE when:
+        # family > 6 || (family == 6 && model >= 0xd)
+        movl    $0x1, %eax              # check CPU family and model
+        cpuid
+        movl    %eax, %ecx
+
+        andl    $0x0ff00f00, %eax       # mask family and extended family
+        shrl    $8, %eax
+        cmpl    $6, %eax
+        ja      verify_cpu_clear_xd     # family > 6, ok
+        jb      verify_cpu_check        # family < 6, skip
+
+        andl    $0x000f00f0, %ecx       # mask model and extended model
+        shrl    $4, %ecx
+        cmpl    $0xd, %ecx
+        jb      verify_cpu_check        # family == 6, model < 0xd, skip
+
+verify_cpu_clear_xd:
+        movl    $MSR_IA32_MISC_ENABLE, %ecx
+        rdmsr
+        btrl    $2, %edx                # clear MSR_IA32_MISC_ENABLE_XD_DISABLE
+        jnc     verify_cpu_check        # only write MSR if bit was changed
+        wrmsr
+
+verify_cpu_check:
         movl    $0x1,%eax               # Does the cpu have what it takes
         cpuid
         andl    $REQUIRED_MASK0,%edx
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index e03530aebfd0..bf4700755184 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -69,7 +69,7 @@ jiffies_64 = jiffies;
 
 PHDRS {
         text PT_LOAD FLAGS(5);          /* R_E */
-        data PT_LOAD FLAGS(7);          /* RWE */
+        data PT_LOAD FLAGS(6);          /* RW_ */
 #ifdef CONFIG_X86_64
         user PT_LOAD FLAGS(5);          /* R_E */
 #ifdef CONFIG_SMP
@@ -116,6 +116,10 @@ SECTIONS
 
         EXCEPTION_TABLE(16) :text = 0x9090
 
+#if defined(CONFIG_DEBUG_RODATA)
+        /* .text should occupy whole number of pages */
+        . = ALIGN(PAGE_SIZE);
+#endif
         X64_ALIGN_DEBUG_RODATA_BEGIN
         RO_DATA(PAGE_SIZE)
         X64_ALIGN_DEBUG_RODATA_END
@@ -335,7 +339,7 @@ SECTIONS
                 __bss_start = .;
                 *(.bss..page_aligned)
                 *(.bss)
-                . = ALIGN(4);
+                . = ALIGN(PAGE_SIZE);
                 __bss_stop = .;
         }
 
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index b989e1f1e5d3..46a368cb651e 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -976,7 +976,7 @@ static inline u64 nsec_to_cycles(u64 nsec)
         if (kvm_tsc_changes_freq())
                 printk_once(KERN_WARNING
                  "kvm: unreliable cycle conversion on adjustable rate TSC\n");
-        ret = nsec * __get_cpu_var(cpu_tsc_khz);
+        ret = nsec * __this_cpu_read(cpu_tsc_khz);
         do_div(ret, USEC_PER_SEC);
         return ret;
 }
@@ -1061,7 +1061,7 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
         local_irq_save(flags);
         kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
         kernel_ns = get_kernel_ns();
-        this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
+        this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
 
         if (unlikely(this_tsc_khz == 0)) {
                 local_irq_restore(flags);
@@ -4427,7 +4427,7 @@ EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
 
 static void tsc_bad(void *info)
 {
-        __get_cpu_var(cpu_tsc_khz) = 0;
+        __this_cpu_write(cpu_tsc_khz, 0);
 }
 
 static void tsc_khz_changed(void *data)
@@ -4441,7 +4441,7 @@ static void tsc_khz_changed(void *data)
                 khz = cpufreq_quick_get(raw_smp_processor_id());
         if (!khz)
                 khz = tsc_khz;
-        __get_cpu_var(cpu_tsc_khz) = khz;
+        __this_cpu_write(cpu_tsc_khz, khz);
 }
 
 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
diff --git a/arch/x86/lguest/i386_head.S b/arch/x86/lguest/i386_head.S
index e7d5382ef263..4f420c2f2d55 100644
--- a/arch/x86/lguest/i386_head.S
+++ b/arch/x86/lguest/i386_head.S
@@ -4,7 +4,6 @@
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
 #include <asm/processor-flags.h>
-#include <asm/pgtable.h>
 
 /*G:020
  * Our story starts with the kernel booting into startup_32 in
@@ -38,113 +37,9 @@ ENTRY(lguest_entry)
         /* Set up the initial stack so we can run C code. */
         movl $(init_thread_union+THREAD_SIZE),%esp
 
-        call init_pagetables
-
         /* Jumps are relative: we're running __PAGE_OFFSET too low. */
         jmp lguest_init+__PAGE_OFFSET
 
-/*
- * Initialize page tables.  This creates a PDE and a set of page
- * tables, which are located immediately beyond __brk_base.  The variable
- * _brk_end is set up to point to the first "safe" location.
- * Mappings are created both at virtual address 0 (identity mapping)
- * and PAGE_OFFSET for up to _end.
- *
- * FIXME: This code is taken verbatim from arch/x86/kernel/head_32.S: they
- * don't have a stack at this point, so we can't just use call and ret.
- */
-init_pagetables:
-#if PTRS_PER_PMD > 1
-#define PAGE_TABLE_SIZE(pages) (((pages) / PTRS_PER_PMD) + PTRS_PER_PGD)
-#else
-#define PAGE_TABLE_SIZE(pages) ((pages) / PTRS_PER_PGD)
-#endif
-#define pa(X) ((X) - __PAGE_OFFSET)
-
-/* Enough space to fit pagetables for the low memory linear map */
-MAPPING_BEYOND_END = \
-        PAGE_TABLE_SIZE(((1<<32) - __PAGE_OFFSET) >> PAGE_SHIFT) << PAGE_SHIFT
-#ifdef CONFIG_X86_PAE
-
-        /*
-         * In PAE mode initial_page_table is statically defined to contain
-         * enough entries to cover the VMSPLIT option (that is the top 1, 2 or 3
-         * entries). The identity mapping is handled by pointing two PGD entries
-         * to the first kernel PMD.
-         *
-         * Note the upper half of each PMD or PTE are always zero at this stage.
-         */
-
-#define KPMDS (((-__PAGE_OFFSET) >> 30) & 3) /* Number of kernel PMDs */
-
-        xorl %ebx,%ebx                          /* %ebx is kept at zero */
-
-        movl $pa(__brk_base), %edi
-        movl $pa(initial_pg_pmd), %edx
-        movl $PTE_IDENT_ATTR, %eax
-10:
-        leal PDE_IDENT_ATTR(%edi),%ecx          /* Create PMD entry */
-        movl %ecx,(%edx)                        /* Store PMD entry */
-                                                /* Upper half already zero */
-        addl $8,%edx
-        movl $512,%ecx
-11:
-        stosl
-        xchgl %eax,%ebx
-        stosl
-        xchgl %eax,%ebx
-        addl $0x1000,%eax
-        loop 11b
-
-        /*
-         * End condition: we must map up to the end + MAPPING_BEYOND_END.
-         */
-        movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp
-        cmpl %ebp,%eax
-        jb 10b
-1:
-        addl $__PAGE_OFFSET, %edi
-        movl %edi, pa(_brk_end)
-        shrl $12, %eax
-        movl %eax, pa(max_pfn_mapped)
-
-        /* Do early initialization of the fixmap area */
-        movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax
-        movl %eax,pa(initial_pg_pmd+0x1000*KPMDS-8)
-#else   /* Not PAE */
-
-page_pde_offset = (__PAGE_OFFSET >> 20);
-
-        movl $pa(__brk_base), %edi
-        movl $pa(initial_page_table), %edx
-        movl $PTE_IDENT_ATTR, %eax
-10:
-        leal PDE_IDENT_ATTR(%edi),%ecx          /* Create PDE entry */
-        movl %ecx,(%edx)                        /* Store identity PDE entry */
-        movl %ecx,page_pde_offset(%edx)         /* Store kernel PDE entry */
-        addl $4,%edx
-        movl $1024, %ecx
-11:
-        stosl
-        addl $0x1000,%eax
-        loop 11b
-        /*
-         * End condition: we must map up to the end + MAPPING_BEYOND_END.
-         */
-        movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp
-        cmpl %ebp,%eax
-        jb 10b
-        addl $__PAGE_OFFSET, %edi
-        movl %edi, pa(_brk_end)
-        shrl $12, %eax
-        movl %eax, pa(max_pfn_mapped)
-
-        /* Do early initialization of the fixmap area */
-        movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax
-        movl %eax,pa(initial_page_table+0xffc)
-#endif
-        ret
-
 /*G:055
  * We create a macro which puts the assembler code between lgstart_ and lgend_
  * markers.  These templates are put in the .text section: they can't be
diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c
index ff485d361182..fc45ba887d05 100644
--- a/arch/x86/lib/delay.c
+++ b/arch/x86/lib/delay.c
@@ -121,7 +121,7 @@ inline void __const_udelay(unsigned long xloops)
         asm("mull %%edx"
                 :"=d" (xloops), "=&a" (d0)
                 :"1" (xloops), "0"
-                (cpu_data(raw_smp_processor_id()).loops_per_jiffy * (HZ/4)));
+                (this_cpu_read(cpu_info.loops_per_jiffy) * (HZ/4)));
 
         __delay(++xloops);
 }
diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile
index 55543397a8a7..09df2f9a3d69 100644
--- a/arch/x86/mm/Makefile
+++ b/arch/x86/mm/Makefile
@@ -23,7 +23,7 @@ mmiotrace-y			:= kmmio.o pf_in.o mmio-mod.o
 obj-$(CONFIG_MMIOTRACE_TEST)    += testmmiotrace.o
 
 obj-$(CONFIG_NUMA)              += numa.o numa_$(BITS).o
-obj-$(CONFIG_K8_NUMA)           += k8topology_64.o
+obj-$(CONFIG_AMD_NUMA)          += amdtopology_64.o
 obj-$(CONFIG_ACPI_NUMA)         += srat_$(BITS).o
 
 obj-$(CONFIG_HAVE_MEMBLOCK)             += memblock.o
diff --git a/arch/x86/mm/k8topology_64.c b/arch/x86/mm/amdtopology_64.c
index 804a3b6c6e14..f21962c435ed 100644
--- a/arch/x86/mm/k8topology_64.c
+++ b/arch/x86/mm/amdtopology_64.c
@@ -1,8 +1,8 @@
 /*
- * AMD K8 NUMA support.
+ * AMD NUMA support.
  * Discover the memory map and associated nodes.
  *
- * This version reads it directly from the K8 northbridge.
+ * This version reads it directly from the AMD northbridge.
  *
  * Copyright 2002,2003 Andi Kleen, SuSE Labs.
  */
@@ -27,6 +27,7 @@
 #include <asm/amd_nb.h>
 
 static struct bootnode __initdata nodes[8];
+static unsigned char __initdata nodeids[8];
 static nodemask_t __initdata nodes_parsed = NODE_MASK_NONE;
 
 static __init int find_northbridge(void)
@@ -57,7 +58,7 @@ static __init void early_get_boot_cpu_id(void)
 {
         /*
          * need to get the APIC ID of the BSP so can use that to
-         * create apicid_to_node in k8_scan_nodes()
+         * create apicid_to_node in amd_scan_nodes()
          */
 #ifdef CONFIG_X86_MPPARSE
         /*
@@ -66,23 +67,9 @@ static __init void early_get_boot_cpu_id(void)
         if (smp_found_config)
                 early_get_smp_config();
 #endif
-        early_init_lapic_mapping();
 }
 
-int __init k8_get_nodes(struct bootnode *physnodes)
-{
-        int i;
-        int ret = 0;
-
-        for_each_node_mask(i, nodes_parsed) {
-                physnodes[ret].start = nodes[i].start;
-                physnodes[ret].end = nodes[i].end;
-                ret++;
-        }
-        return ret;
-}
-
-int __init k8_numa_init(unsigned long start_pfn, unsigned long end_pfn)
+int __init amd_numa_init(unsigned long start_pfn, unsigned long end_pfn)
 {
         unsigned long start = PFN_PHYS(start_pfn);
         unsigned long end = PFN_PHYS(end_pfn);
@@ -114,7 +101,7 @@ int __init k8_numa_init(unsigned long start_pfn, unsigned long end_pfn)
                 base = read_pci_config(0, nb, 1, 0x40 + i*8);
                 limit = read_pci_config(0, nb, 1, 0x44 + i*8);
 
-                nodeid = limit & 7;
+                nodeids[i] = nodeid = limit & 7;
                 if ((base & 3) == 0) {
                         if (i < numnodes)
                                 pr_info("Skipping disabled node %d\n", i);
@@ -194,7 +181,77 @@ int __init k8_numa_init(unsigned long start_pfn, unsigned long end_pfn)
         return 0;
 }
 
-int __init k8_scan_nodes(void)
+#ifdef CONFIG_NUMA_EMU
+static s16 fake_apicid_to_node[MAX_LOCAL_APIC] __initdata = {
+        [0 ... MAX_LOCAL_APIC-1] = NUMA_NO_NODE
+};
+
+void __init amd_get_nodes(struct bootnode *physnodes)
+{
+        int i;
+
+        for_each_node_mask(i, nodes_parsed) {
+                physnodes[i].start = nodes[i].start;
+                physnodes[i].end = nodes[i].end;
+        }
+}
+
+static int __init find_node_by_addr(unsigned long addr)
+{
+        int ret = NUMA_NO_NODE;
+        int i;
+
+        for (i = 0; i < 8; i++)
+                if (addr >= nodes[i].start && addr < nodes[i].end) {
+                        ret = i;
+                        break;
+                }
+        return ret;
+}
+
+/*
+ * For NUMA emulation, fake proximity domain (_PXM) to node id mappings must be
+ * setup to represent the physical topology but reflect the emulated
+ * environment.  For each emulated node, the real node which it appears on is
+ * found and a fake pxm to nid mapping is created which mirrors the actual
+ * locality.  node_distance() then represents the correct distances between
+ * emulated nodes by using the fake acpi mappings to pxms.
+ */
+void __init amd_fake_nodes(const struct bootnode *nodes, int nr_nodes)
+{
+        unsigned int bits;
+        unsigned int cores;
+        unsigned int apicid_base = 0;
+        int i;
+
+        bits = boot_cpu_data.x86_coreid_bits;
+        cores = 1 << bits;
+        early_get_boot_cpu_id();
+        if (boot_cpu_physical_apicid > 0)
+                apicid_base = boot_cpu_physical_apicid;
+
+        for (i = 0; i < nr_nodes; i++) {
+                int index;
+                int nid;
+                int j;
+
+                nid = find_node_by_addr(nodes[i].start);
+                if (nid == NUMA_NO_NODE)
+                        continue;
+
+                index = nodeids[nid] << bits;
+                if (fake_apicid_to_node[index + apicid_base] == NUMA_NO_NODE)
+                        for (j = apicid_base; j < cores + apicid_base; j++)
+                                fake_apicid_to_node[index + j] = i;
+#ifdef CONFIG_ACPI_NUMA
+                __acpi_map_pxm_to_node(nid, i);
+#endif
+        }
+        memcpy(apicid_to_node, fake_apicid_to_node, sizeof(apicid_to_node));
+}
+#endif /* CONFIG_NUMA_EMU */
+
+int __init amd_scan_nodes(void)
 {
         unsigned int bits;
         unsigned int cores;
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index c0e28a13de7d..947f42abe820 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -364,8 +364,9 @@ void free_init_pages(char *what, unsigned long begin, unsigned long end)
         /*
          * We just marked the kernel text read only above, now that
          * we are going to free part of that, we need to make that
-         * writeable first.
+         * writeable and non-executable first.
          */
+        set_memory_nx(begin, (end - begin) >> PAGE_SHIFT);
         set_memory_rw(begin, (end - begin) >> PAGE_SHIFT);
 
         printk(KERN_INFO "Freeing %s: %luk freed\n", what, (end - begin) >> 10);
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 0e969f9f401b..f89b5bb4e93f 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -226,7 +226,7 @@ page_table_range_init(unsigned long start, unsigned long end, pgd_t *pgd_base)
 
 static inline int is_kernel_text(unsigned long addr)
 {
-        if (addr >= PAGE_OFFSET && addr <= (unsigned long)__init_end)
+        if (addr >= (unsigned long)_text && addr <= (unsigned long)__init_end)
                 return 1;
         return 0;
 }
@@ -912,6 +912,23 @@ void set_kernel_text_ro(void)
         set_pages_ro(virt_to_page(start), size >> PAGE_SHIFT);
 }
 
+static void mark_nxdata_nx(void)
+{
+        /*
+         * When this called, init has already been executed and released,
+         * so everything past _etext sould be NX.
+         */
+        unsigned long start = PFN_ALIGN(_etext);
+        /*
+         * This comes from is_kernel_text upper limit. Also HPAGE where used:
+         */
+        unsigned long size = (((unsigned long)__init_end + HPAGE_SIZE) & HPAGE_MASK) - start;
+
+        if (__supported_pte_mask & _PAGE_NX)
+                printk(KERN_INFO "NX-protecting the kernel data: %luk\n", size >> 10);
+        set_pages_nx(virt_to_page(start), size >> PAGE_SHIFT);
+}
+
 void mark_rodata_ro(void)
 {
         unsigned long start = PFN_ALIGN(_text);
@@ -946,6 +963,7 @@ void mark_rodata_ro(void)
         printk(KERN_INFO "Testing CPA: write protecting again\n");
         set_pages_ro(virt_to_page(start), size >> PAGE_SHIFT);
 #endif
+        mark_nxdata_nx();
 }
 #endif
 
diff --git a/arch/x86/mm/kmemcheck/error.c b/arch/x86/mm/kmemcheck/error.c
index af3b6c8a436f..704a37cedddb 100644
--- a/arch/x86/mm/kmemcheck/error.c
+++ b/arch/x86/mm/kmemcheck/error.c
@@ -185,7 +185,7 @@ void kmemcheck_error_save(enum kmemcheck_shadow state,
         e->trace.entries = e->trace_entries;
         e->trace.max_entries = ARRAY_SIZE(e->trace_entries);
         e->trace.skip = 0;
-        save_stack_trace_bp(&e->trace, regs->bp);
+        save_stack_trace_regs(&e->trace, regs);
 
         /* Round address down to nearest 16 bytes */
         shadow_copy = kmemcheck_shadow_lookup(address
diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c
index 7ffc9b727efd..1e72102e80c9 100644
--- a/arch/x86/mm/numa_64.c
+++ b/arch/x86/mm/numa_64.c
@@ -260,30 +260,30 @@ void __init numa_init_array(void)
 #ifdef CONFIG_NUMA_EMU
 /* Numa emulation */
 static struct bootnode nodes[MAX_NUMNODES] __initdata;
-static struct bootnode physnodes[MAX_NUMNODES] __initdata;
+static struct bootnode physnodes[MAX_NUMNODES] __cpuinitdata;
 static char *cmdline __initdata;
 
 static int __init setup_physnodes(unsigned long start, unsigned long end,
-                                        int acpi, int k8)
+                                        int acpi, int amd)
 {
-        int nr_nodes = 0;
         int ret = 0;
         int i;
 
+        memset(physnodes, 0, sizeof(physnodes));
 #ifdef CONFIG_ACPI_NUMA
         if (acpi)
-                nr_nodes = acpi_get_nodes(physnodes);
+                acpi_get_nodes(physnodes, start, end);
 #endif
-#ifdef CONFIG_K8_NUMA
-        if (k8)
-                nr_nodes = k8_get_nodes(physnodes);
+#ifdef CONFIG_AMD_NUMA
+        if (amd)
+                amd_get_nodes(physnodes);
 #endif
         /*
          * Basic sanity checking on the physical node map: there may be errors
-         * if the SRAT or K8 incorrectly reported the topology or the mem=
+         * if the SRAT or AMD code incorrectly reported the topology or the mem=
          * kernel parameter is used.
          */
-        for (i = 0; i < nr_nodes; i++) {
+        for (i = 0; i < MAX_NUMNODES; i++) {
                 if (physnodes[i].start == physnodes[i].end)
                         continue;
                 if (physnodes[i].start > end) {
@@ -298,17 +298,6 @@ static int __init setup_physnodes(unsigned long start, unsigned long end,
                         physnodes[i].start = start;
                 if (physnodes[i].end > end)
                         physnodes[i].end = end;
-        }
-
-        /*
-         * Remove all nodes that have no memory or were truncated because of the
-         * limited address range.
-         */
-        for (i = 0; i < nr_nodes; i++) {
-                if (physnodes[i].start == physnodes[i].end)
-                        continue;
-                physnodes[ret].start = physnodes[i].start;
-                physnodes[ret].end = physnodes[i].end;
                 ret++;
         }
 
@@ -324,6 +313,24 @@ static int __init setup_physnodes(unsigned long start, unsigned long end,
         return ret;
 }
 
+static void __init fake_physnodes(int acpi, int amd, int nr_nodes)
+{
+        int i;
+
+        BUG_ON(acpi && amd);
+#ifdef CONFIG_ACPI_NUMA
+        if (acpi)
+                acpi_fake_nodes(nodes, nr_nodes);
+#endif
+#ifdef CONFIG_AMD_NUMA
+        if (amd)
+                amd_fake_nodes(nodes, nr_nodes);
+#endif
+        if (!acpi && !amd)
+                for (i = 0; i < nr_cpu_ids; i++)
+                        numa_set_node(i, 0);
+}
+
 /*
  * Setups up nid to range from addr to addr + size.  If the end
  * boundary is greater than max_addr, then max_addr is used instead.
@@ -352,8 +359,7 @@ static int __init setup_node_range(int nid, u64 *addr, u64 size, u64 max_addr)
  * Sets up nr_nodes fake nodes interleaved over physical nodes ranging from addr
  * to max_addr.  The return value is the number of nodes allocated.
  */
-static int __init split_nodes_interleave(u64 addr, u64 max_addr,
-                                                int nr_phys_nodes, int nr_nodes)
+static int __init split_nodes_interleave(u64 addr, u64 max_addr, int nr_nodes)
 {
         nodemask_t physnode_mask = NODE_MASK_NONE;
         u64 size;
@@ -384,7 +390,7 @@ static int __init split_nodes_interleave(u64 addr, u64 max_addr,
                 return -1;
         }
 
-        for (i = 0; i < nr_phys_nodes; i++)
+        for (i = 0; i < MAX_NUMNODES; i++)
                 if (physnodes[i].start != physnodes[i].end)
                         node_set(i, physnode_mask);
 
@@ -549,15 +555,13 @@ static int __init split_nodes_size_interleave(u64 addr, u64 max_addr, u64 size)
  * numa=fake command-line option.
  */
 static int __init numa_emulation(unsigned long start_pfn,
-                        unsigned long last_pfn, int acpi, int k8)
+                        unsigned long last_pfn, int acpi, int amd)
 {
         u64 addr = start_pfn << PAGE_SHIFT;
         u64 max_addr = last_pfn << PAGE_SHIFT;
-        int num_phys_nodes;
         int num_nodes;
         int i;
 
-        num_phys_nodes = setup_physnodes(addr, max_addr, acpi, k8);
         /*
          * If the numa=fake command-line contains a 'M' or 'G', it represents
          * the fixed node size.  Otherwise, if it is just a single number N,
@@ -572,7 +576,7 @@ static int __init numa_emulation(unsigned long start_pfn,
                 unsigned long n;
 
                 n = simple_strtoul(cmdline, NULL, 0);
-                num_nodes = split_nodes_interleave(addr, max_addr, num_phys_nodes, n);
+                num_nodes = split_nodes_interleave(addr, max_addr, n);
         }
 
         if (num_nodes < 0)
@@ -595,14 +599,15 @@ static int __init numa_emulation(unsigned long start_pfn,
                                                 nodes[i].end >> PAGE_SHIFT);
                 setup_node_bootmem(i, nodes[i].start, nodes[i].end);
         }
-        acpi_fake_nodes(nodes, num_nodes);
+        setup_physnodes(addr, max_addr, acpi, amd);
+        fake_physnodes(acpi, amd, num_nodes);
         numa_init_array();
         return 0;
 }
 #endif /* CONFIG_NUMA_EMU */
 
 void __init initmem_init(unsigned long start_pfn, unsigned long last_pfn,
-                                int acpi, int k8)
+                                int acpi, int amd)
 {
         int i;
 
@@ -610,8 +615,12 @@ void __init initmem_init(unsigned long start_pfn, unsigned long last_pfn,
         nodes_clear(node_online_map);
 
 #ifdef CONFIG_NUMA_EMU
-        if (cmdline && !numa_emulation(start_pfn, last_pfn, acpi, k8))
+        setup_physnodes(start_pfn << PAGE_SHIFT, last_pfn << PAGE_SHIFT,
+                        acpi, amd);
+        if (cmdline && !numa_emulation(start_pfn, last_pfn, acpi, amd))
                 return;
+        setup_physnodes(start_pfn << PAGE_SHIFT, last_pfn << PAGE_SHIFT,
+                        acpi, amd);
         nodes_clear(node_possible_map);
         nodes_clear(node_online_map);
 #endif
@@ -624,8 +633,8 @@ void __init initmem_init(unsigned long start_pfn, unsigned long last_pfn,
         nodes_clear(node_online_map);
 #endif
 
-#ifdef CONFIG_K8_NUMA
-        if (!numa_off && k8 && !k8_scan_nodes())
+#ifdef CONFIG_AMD_NUMA
+        if (!numa_off && amd && !amd_scan_nodes())
                 return;
         nodes_clear(node_possible_map);
         nodes_clear(node_online_map);
@@ -767,6 +776,7 @@ void __cpuinit numa_clear_node(int cpu)
 
 #ifndef CONFIG_DEBUG_PER_CPU_MAPS
 
+#ifndef CONFIG_NUMA_EMU
 void __cpuinit numa_add_cpu(int cpu)
 {
         cpumask_set_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]);
@@ -776,34 +786,115 @@ void __cpuinit numa_remove_cpu(int cpu)
 {
         cpumask_clear_cpu(cpu, node_to_cpumask_map[early_cpu_to_node(cpu)]);
 }
+#else
+void __cpuinit numa_add_cpu(int cpu)
+{
+        unsigned long addr;
+        u16 apicid;
+        int physnid;
+        int nid = NUMA_NO_NODE;
+
+        apicid = early_per_cpu(x86_cpu_to_apicid, cpu);
+        if (apicid != BAD_APICID)
+                nid = apicid_to_node[apicid];
+        if (nid == NUMA_NO_NODE)
+                nid = early_cpu_to_node(cpu);
+        BUG_ON(nid == NUMA_NO_NODE || !node_online(nid));
+
+        /*
+         * Use the starting address of the emulated node to find which physical
+         * node it is allocated on.
+         */
+        addr = node_start_pfn(nid) << PAGE_SHIFT;
+        for (physnid = 0; physnid < MAX_NUMNODES; physnid++)
+                if (addr >= physnodes[physnid].start &&
+                    addr < physnodes[physnid].end)
+                        break;
+
+        /*
+         * Map the cpu to each emulated node that is allocated on the physical
+         * node of the cpu's apic id.
+         */
+        for_each_online_node(nid) {
+                addr = node_start_pfn(nid) << PAGE_SHIFT;
+                if (addr >= physnodes[physnid].start &&
+                    addr < physnodes[physnid].end)
+                        cpumask_set_cpu(cpu, node_to_cpumask_map[nid]);
+        }
+}
+
+void __cpuinit numa_remove_cpu(int cpu)
+{
+        int i;
+
+        for_each_online_node(i)
+                cpumask_clear_cpu(cpu, node_to_cpumask_map[i]);
+}
+#endif /* !CONFIG_NUMA_EMU */
 
 #else /* CONFIG_DEBUG_PER_CPU_MAPS */
+static struct cpumask __cpuinit *debug_cpumask_set_cpu(int cpu, int enable)
+{
+        int node = early_cpu_to_node(cpu);
+        struct cpumask *mask;
+        char buf[64];
+
+        mask = node_to_cpumask_map[node];
+        if (!mask) {
+                pr_err("node_to_cpumask_map[%i] NULL\n", node);
+                dump_stack();
+                return NULL;
+        }
+
+        cpulist_scnprintf(buf, sizeof(buf), mask);
+        printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n",
+                enable ? "numa_add_cpu" : "numa_remove_cpu",
+                cpu, node, buf);
+        return mask;
+}
 
 /*
  * --------- debug versions of the numa functions ---------
  */
+#ifndef CONFIG_NUMA_EMU
 static void __cpuinit numa_set_cpumask(int cpu, int enable)
 {
-        int node = early_cpu_to_node(cpu);
         struct cpumask *mask;
-        char buf[64];
 
-        mask = node_to_cpumask_map[node];
-        if (mask == NULL) {
-                printk(KERN_ERR "node_to_cpumask_map[%i] NULL\n", node);
-                dump_stack();
+        mask = debug_cpumask_set_cpu(cpu, enable);
+        if (!mask)
                 return;
-        }
 
         if (enable)
                 cpumask_set_cpu(cpu, mask);
         else
                 cpumask_clear_cpu(cpu, mask);
+}
+#else
+static void __cpuinit numa_set_cpumask(int cpu, int enable)
+{
+        int node = early_cpu_to_node(cpu);
+        struct cpumask *mask;
+        int i;
 
-        cpulist_scnprintf(buf, sizeof(buf), mask);
-        printk(KERN_DEBUG "%s cpu %d node %d: mask now %s\n",
-                enable ? "numa_add_cpu" : "numa_remove_cpu", cpu, node, buf);
+        for_each_online_node(i) {
+                unsigned long addr;
+
+                addr = node_start_pfn(i) << PAGE_SHIFT;
+                if (addr < physnodes[node].start ||
+                                        addr >= physnodes[node].end)
+                        continue;
+                mask = debug_cpumask_set_cpu(cpu, enable);
+                if (!mask)
+                        return;
+
+                if (enable)
+                        cpumask_set_cpu(cpu, mask);
+                else
+                        cpumask_clear_cpu(cpu, mask);
+        }
 }
+#endif /* CONFIG_NUMA_EMU */
 
 void __cpuinit numa_add_cpu(int cpu)
 {
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 532e7933d606..8b830ca14ac4 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -13,6 +13,7 @@
 #include <linux/pfn.h>
 #include <linux/percpu.h>
 #include <linux/gfp.h>
+#include <linux/pci.h>
 
 #include <asm/e820.h>
 #include <asm/processor.h>
@@ -255,13 +256,16 @@ static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
                                    unsigned long pfn)
 {
         pgprot_t forbidden = __pgprot(0);
+        pgprot_t required = __pgprot(0);
 
         /*
          * The BIOS area between 640k and 1Mb needs to be executable for
          * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
          */
-        if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
+#ifdef CONFIG_PCI_BIOS
+        if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT))
                 pgprot_val(forbidden) |= _PAGE_NX;
+#endif
 
         /*
          * The kernel text needs to be executable for obvious reasons
@@ -278,6 +282,12 @@ static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
         if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT,
                    __pa((unsigned long)__end_rodata) >> PAGE_SHIFT))
                 pgprot_val(forbidden) |= _PAGE_RW;
+        /*
+         * .data and .bss should always be writable.
+         */
+        if (within(address, (unsigned long)_sdata, (unsigned long)_edata) ||
+            within(address, (unsigned long)__bss_start, (unsigned long)__bss_stop))
+                pgprot_val(required) |= _PAGE_RW;
 
 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
         /*
@@ -317,6 +327,7 @@ static inline pgprot_t static_protections(pgprot_t prot, unsigned long address,
 #endif
 
         prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
+        prot = __pgprot(pgprot_val(prot) | pgprot_val(required));
 
         return prot;
 }
@@ -393,7 +404,7 @@ try_preserve_large_page(pte_t *kpte, unsigned long address,
 {
         unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn;
         pte_t new_pte, old_pte, *tmp;
-        pgprot_t old_prot, new_prot;
+        pgprot_t old_prot, new_prot, req_prot;
         int i, do_split = 1;
         unsigned int level;
 
@@ -438,10 +449,10 @@ try_preserve_large_page(pte_t *kpte, unsigned long address,
          * We are safe now. Check whether the new pgprot is the same:
          */
         old_pte = *kpte;
-        old_prot = new_prot = pte_pgprot(old_pte);
+        old_prot = new_prot = req_prot = pte_pgprot(old_pte);
 
-        pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
-        pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
+        pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
+        pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
 
         /*
          * old_pte points to the large page base address. So we need
@@ -450,17 +461,17 @@ try_preserve_large_page(pte_t *kpte, unsigned long address,
         pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT);
         cpa->pfn = pfn;
 
-        new_prot = static_protections(new_prot, address, pfn);
+        new_prot = static_protections(req_prot, address, pfn);
 
         /*
          * We need to check the full range, whether
          * static_protection() requires a different pgprot for one of
          * the pages in the range we try to preserve:
          */
-        addr = address + PAGE_SIZE;
-        pfn++;
-        for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) {
-                pgprot_t chk_prot = static_protections(new_prot, addr, pfn);
+        addr = address & pmask;
+        pfn = pte_pfn(old_pte);
+        for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) {
+                pgprot_t chk_prot = static_protections(req_prot, addr, pfn);
 
                 if (pgprot_val(chk_prot) != pgprot_val(new_prot))
                         goto out_unlock;
@@ -483,7 +494,7 @@ try_preserve_large_page(pte_t *kpte, unsigned long address,
          * that we limited the number of possible pages already to
          * the number of pages in the large page.
          */
-        if (address == (nextpage_addr - psize) && cpa->numpages == numpages) {
+        if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) {
                 /*
                  * The address is aligned and the number of pages
                  * covers the full page.
diff --git a/arch/x86/mm/setup_nx.c b/arch/x86/mm/setup_nx.c
index a3250aa34086..410531d3c292 100644
--- a/arch/x86/mm/setup_nx.c
+++ b/arch/x86/mm/setup_nx.c
@@ -41,7 +41,7 @@ void __init x86_report_nx(void)
 {
         if (!cpu_has_nx) {
                 printk(KERN_NOTICE "Notice: NX (Execute Disable) protection "
-                       "missing in CPU or disabled in BIOS!\n");
+                       "missing in CPU!\n");
         } else {
 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
                 if (disable_nx) {
diff --git a/arch/x86/mm/srat_32.c b/arch/x86/mm/srat_32.c
index a17dffd136c1..f16434568a51 100644
--- a/arch/x86/mm/srat_32.c
+++ b/arch/x86/mm/srat_32.c
@@ -92,6 +92,7 @@ acpi_numa_processor_affinity_init(struct acpi_srat_cpu_affinity *cpu_affinity)
         /* mark this node as "seen" in node bitmap */
         BMAP_SET(pxm_bitmap, cpu_affinity->proximity_domain_lo);
 
+        /* don't need to check apic_id here, because it is always 8 bits */
         apicid_to_pxm[cpu_affinity->apic_id] = cpu_affinity->proximity_domain_lo;
 
         printk(KERN_DEBUG "CPU %02x in proximity domain %02x\n",
diff --git a/arch/x86/mm/srat_64.c b/arch/x86/mm/srat_64.c
index a35cb9d8b060..603d285d1daa 100644
--- a/arch/x86/mm/srat_64.c
+++ b/arch/x86/mm/srat_64.c
@@ -134,6 +134,10 @@ acpi_numa_x2apic_affinity_init(struct acpi_srat_x2apic_cpu_affinity *pa)
         }
 
         apic_id = pa->apic_id;
+        if (apic_id >= MAX_LOCAL_APIC) {
+                printk(KERN_INFO "SRAT: PXM %u -> APIC 0x%04x -> Node %u skipped apicid that is too big\n", pxm, apic_id, node);
+                return;
+        }
         apicid_to_node[apic_id] = node;
         node_set(node, cpu_nodes_parsed);
         acpi_numa = 1;
@@ -168,6 +172,12 @@ acpi_numa_processor_affinity_init(struct acpi_srat_cpu_affinity *pa)
                 apic_id = (pa->apic_id << 8) | pa->local_sapic_eid;
         else
                 apic_id = pa->apic_id;
+
+        if (apic_id >= MAX_LOCAL_APIC) {
+                printk(KERN_INFO "SRAT: PXM %u -> APIC 0x%02x -> Node %u skipped apicid that is too big\n", pxm, apic_id, node);
+                return;
+        }
+
         apicid_to_node[apic_id] = node;
         node_set(node, cpu_nodes_parsed);
         acpi_numa = 1;
@@ -339,18 +349,19 @@ static int __init nodes_cover_memory(const struct bootnode *nodes)
 
 void __init acpi_numa_arch_fixup(void) {}
 
-int __init acpi_get_nodes(struct bootnode *physnodes)
+#ifdef CONFIG_NUMA_EMU
+void __init acpi_get_nodes(struct bootnode *physnodes, unsigned long start,
+                                unsigned long end)
 {
         int i;
-        int ret = 0;
 
         for_each_node_mask(i, nodes_parsed) {
-                physnodes[ret].start = nodes[i].start;
-                physnodes[ret].end = nodes[i].end;
-                ret++;
+                cutoff_node(i, start, end);
+                physnodes[i].start = nodes[i].start;
+                physnodes[i].end = nodes[i].end;
         }
-        return ret;
 }
+#endif /* CONFIG_NUMA_EMU */
 
 /* Use the information discovered above to actually set up the nodes. */
 int __init acpi_scan_nodes(unsigned long start, unsigned long end)
@@ -495,8 +506,6 @@ void __init acpi_fake_nodes(const struct bootnode *fake_nodes, int num_nodes)
 {
         int i, j;
 
-        printk(KERN_INFO "Faking PXM affinity for fake nodes on real "
-                         "topology.\n");
         for (i = 0; i < num_nodes; i++) {
                 int nid, pxm;
 
@@ -516,6 +525,17 @@ void __init acpi_fake_nodes(const struct bootnode *fake_nodes, int num_nodes)
                             fake_apicid_to_node[j] == NUMA_NO_NODE)
                                 fake_apicid_to_node[j] = i;
         }
+
+        /*
+         * If there are apicid-to-node mappings for physical nodes that do not
+         * have a corresponding emulated node, it should default to a guaranteed
+         * value.
+         */
+        for (i = 0; i < MAX_LOCAL_APIC; i++)
+                if (apicid_to_node[i] != NUMA_NO_NODE &&
+                    fake_apicid_to_node[i] == NUMA_NO_NODE)
+                        fake_apicid_to_node[i] = 0;
+
         for (i = 0; i < num_nodes; i++)
                 __acpi_map_pxm_to_node(fake_node_to_pxm_map[i], i);
         memcpy(apicid_to_node, fake_apicid_to_node, sizeof(apicid_to_node));
diff --git a/arch/x86/oprofile/backtrace.c b/arch/x86/oprofile/backtrace.c
index 2d49d4e19a36..72cbec14d783 100644
--- a/arch/x86/oprofile/backtrace.c
+++ b/arch/x86/oprofile/backtrace.c
@@ -126,7 +126,7 @@ x86_backtrace(struct pt_regs * const regs, unsigned int depth)
         if (!user_mode_vm(regs)) {
                 unsigned long stack = kernel_stack_pointer(regs);
                 if (depth)
-                        dump_trace(NULL, regs, (unsigned long *)stack, 0,
+                        dump_trace(NULL, regs, (unsigned long *)stack,
                                    &backtrace_ops, &depth);
                 return;
         }
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 4e8baad36d37..e2b7b0c06cdf 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -65,7 +65,6 @@ static int profile_exceptions_notify(struct notifier_block *self,
 
         switch (val) {
         case DIE_NMI:
-        case DIE_NMI_IPI:
                 if (ctr_running)
                         model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs));
                 else if (!nmi_enabled)
@@ -143,7 +142,7 @@ static inline int has_mux(void)
 
 inline int op_x86_phys_to_virt(int phys)
 {
-        return __get_cpu_var(switch_index) + phys;
+        return __this_cpu_read(switch_index) + phys;
 }
 
 inline int op_x86_virt_to_phys(int virt)
@@ -361,7 +360,7 @@ static void nmi_cpu_setup(void *dummy)
 static struct notifier_block profile_exceptions_nb = {
         .notifier_call = profile_exceptions_notify,
         .next = NULL,
-        .priority = 2
+        .priority = NMI_LOCAL_LOW_PRIOR,
 };
 
 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
@@ -732,6 +731,9 @@ int __init op_nmi_init(struct oprofile_operations *ops)
                 case 0x14:
                         cpu_type = "x86-64/family14h";
                         break;
+                case 0x15:
+                        cpu_type = "x86-64/family15h";
+                        break;
                 default:
                         return -ENODEV;
                 }
diff --git a/arch/x86/oprofile/nmi_timer_int.c b/arch/x86/oprofile/nmi_timer_int.c
index e3ecb71b5790..720bf5a53c51 100644
--- a/arch/x86/oprofile/nmi_timer_int.c
+++ b/arch/x86/oprofile/nmi_timer_int.c
@@ -38,7 +38,7 @@ static int profile_timer_exceptions_notify(struct notifier_block *self,
 static struct notifier_block profile_timer_exceptions_nb = {
         .notifier_call = profile_timer_exceptions_notify,
         .next = NULL,
-        .priority = 0
+        .priority = NMI_LOW_PRIOR,
 };
 
 static int timer_start(void)
@@ -58,9 +58,6 @@ static void timer_stop(void)
 
 int __init op_nmi_timer_init(struct oprofile_operations *ops)
 {
-        if ((nmi_watchdog != NMI_IO_APIC) || (atomic_read(&nmi_active) <= 0))
-                return -ENODEV;
-
         ops->start = timer_start;
         ops->stop = timer_stop;
         ops->cpu_type = "timer";
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 7d90d47655ba..c3b8e24f2b16 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -29,11 +29,12 @@
 #include "op_x86_model.h"
 #include "op_counter.h"
 
-#define NUM_COUNTERS 4
+#define NUM_COUNTERS            4
+#define NUM_COUNTERS_F15H       6
 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
-#define NUM_VIRT_COUNTERS 32
+#define NUM_VIRT_COUNTERS       32
 #else
-#define NUM_VIRT_COUNTERS NUM_COUNTERS
+#define NUM_VIRT_COUNTERS       0
 #endif
 
 #define OP_EVENT_MASK                   0x0FFF
@@ -41,7 +42,8 @@
 
 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
 
-static unsigned long reset_value[NUM_VIRT_COUNTERS];
+static int num_counters;
+static unsigned long reset_value[OP_MAX_COUNTER];
 
 #define IBS_FETCH_SIZE                  6
 #define IBS_OP_SIZE                     12
@@ -387,7 +389,7 @@ static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
         int i;
 
         /* enable active counters */
-        for (i = 0; i < NUM_COUNTERS; ++i) {
+        for (i = 0; i < num_counters; ++i) {
                 int virt = op_x86_phys_to_virt(i);
                 if (!reset_value[virt])
                         continue;
@@ -406,7 +408,7 @@ static void op_amd_shutdown(struct op_msrs const * const msrs)
 {
         int i;
 
-        for (i = 0; i < NUM_COUNTERS; ++i) {
+        for (i = 0; i < num_counters; ++i) {
                 if (!msrs->counters[i].addr)
                         continue;
                 release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
@@ -418,7 +420,7 @@ static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
 {
         int i;
 
-        for (i = 0; i < NUM_COUNTERS; i++) {
+        for (i = 0; i < num_counters; i++) {
                 if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
                         goto fail;
                 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) {
@@ -426,8 +428,13 @@ static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
                         goto fail;
                 }
                 /* both registers must be reserved */
-                msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
-                msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
+                if (num_counters == NUM_COUNTERS_F15H) {
+                        msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1);
+                        msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);
+                } else {
+                        msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
+                        msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
+                }
                 continue;
         fail:
                 if (!counter_config[i].enabled)
@@ -447,7 +454,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
         int i;
 
         /* setup reset_value */
-        for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
+        for (i = 0; i < OP_MAX_COUNTER; ++i) {
                 if (counter_config[i].enabled
                     && msrs->counters[op_x86_virt_to_phys(i)].addr)
                         reset_value[i] = counter_config[i].count;
@@ -456,7 +463,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
         }
 
         /* clear all counters */
-        for (i = 0; i < NUM_COUNTERS; ++i) {
+        for (i = 0; i < num_counters; ++i) {
                 if (!msrs->controls[i].addr)
                         continue;
                 rdmsrl(msrs->controls[i].addr, val);
@@ -472,7 +479,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
         }
 
         /* enable active counters */
-        for (i = 0; i < NUM_COUNTERS; ++i) {
+        for (i = 0; i < num_counters; ++i) {
                 int virt = op_x86_phys_to_virt(i);
                 if (!reset_value[virt])
                         continue;
@@ -503,7 +510,7 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
         u64 val;
         int i;
 
-        for (i = 0; i < NUM_COUNTERS; ++i) {
+        for (i = 0; i < num_counters; ++i) {
                 int virt = op_x86_phys_to_virt(i);
                 if (!reset_value[virt])
                         continue;
@@ -526,7 +533,7 @@ static void op_amd_start(struct op_msrs const * const msrs)
         u64 val;
         int i;
 
-        for (i = 0; i < NUM_COUNTERS; ++i) {
+        for (i = 0; i < num_counters; ++i) {
                 if (!reset_value[op_x86_phys_to_virt(i)])
                         continue;
                 rdmsrl(msrs->controls[i].addr, val);
@@ -546,7 +553,7 @@ static void op_amd_stop(struct op_msrs const * const msrs)
          * Subtle: stop on all counters to avoid race with setting our
          * pm callback
          */
-        for (i = 0; i < NUM_COUNTERS; ++i) {
+        for (i = 0; i < num_counters; ++i) {
                 if (!reset_value[op_x86_phys_to_virt(i)])
                         continue;
                 rdmsrl(msrs->controls[i].addr, val);
@@ -603,6 +610,7 @@ static int force_ibs_eilvt_setup(void)
                 ret = setup_ibs_ctl(i);
                 if (ret)
                         return ret;
+                pr_err(FW_BUG "using offset %d for IBS interrupts\n", i);
                 return 0;
         }
 
@@ -706,18 +714,29 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
         return 0;
 }
 
+struct op_x86_model_spec op_amd_spec;
+
 static int op_amd_init(struct oprofile_operations *ops)
 {
         init_ibs();
         create_arch_files = ops->create_files;
         ops->create_files = setup_ibs_files;
+
+        if (boot_cpu_data.x86 == 0x15) {
+                num_counters = NUM_COUNTERS_F15H;
+        } else {
+                num_counters = NUM_COUNTERS;
+        }
+
+        op_amd_spec.num_counters = num_counters;
+        op_amd_spec.num_controls = num_counters;
+        op_amd_spec.num_virt_counters = max(num_counters, NUM_VIRT_COUNTERS);
+
         return 0;
 }
 
 struct op_x86_model_spec op_amd_spec = {
-        .num_counters           = NUM_COUNTERS,
-        .num_controls           = NUM_COUNTERS,
-        .num_virt_counters      = NUM_VIRT_COUNTERS,
+        /* num_counters/num_controls filled in at runtime */
         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
         .event_mask             = OP_EVENT_MASK,
         .init                   = op_amd_init,
diff --git a/arch/x86/oprofile/op_model_p4.c b/arch/x86/oprofile/op_model_p4.c
index 182558dd5515..9fadec074142 100644
--- a/arch/x86/oprofile/op_model_p4.c
+++ b/arch/x86/oprofile/op_model_p4.c
@@ -11,7 +11,7 @@
 #include <linux/oprofile.h>
 #include <linux/smp.h>
 #include <linux/ptrace.h>
-#include <linux/nmi.h>
+#include <asm/nmi.h>
 #include <asm/msr.h>
 #include <asm/fixmap.h>
 #include <asm/apic.h>
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index d769cda54082..94b745045e45 100644
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -95,8 +95,8 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
                  * counter width:
                  */
                 if (!(eax.split.version_id == 0 &&
-                        current_cpu_data.x86 == 6 &&
-                                current_cpu_data.x86_model == 15)) {
+                        __this_cpu_read(cpu_info.x86) == 6 &&
+                                __this_cpu_read(cpu_info.x86_model) == 15)) {
 
                         if (counter_width < eax.split.bit_width)
                                 counter_width = eax.split.bit_width;
@@ -235,8 +235,8 @@ static void arch_perfmon_setup_counters(void)
         eax.full = cpuid_eax(0xa);
 
         /* Workaround for BIOS bugs in 6/15. Taken from perfmon2 */
-        if (eax.split.version_id == 0 && current_cpu_data.x86 == 6 &&
-                current_cpu_data.x86_model == 15) {
+        if (eax.split.version_id == 0 && __this_cpu_read(cpu_info.x86) == 6 &&
+                __this_cpu_read(cpu_info.x86_model) == 15) {
                 eax.split.version_id = 2;
                 eax.split.num_counters = 2;
                 eax.split.bit_width = 40;
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index effd96e33f16..6b8759f7634e 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_OLPC)		+= olpc.o
 obj-$(CONFIG_PCI_XEN)           += xen.o
 
 obj-y                           += fixup.o
+obj-$(CONFIG_X86_INTEL_CE)      += ce4100.o
 obj-$(CONFIG_ACPI)              += acpi.o
 obj-y                           += legacy.o irq.o
 
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index fc1e8fe07e5c..e27dffbbb1a7 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -4,6 +4,7 @@
 #include <linux/cpu.h>
 #include <linux/range.h>
 
+#include <asm/amd_nb.h>
 #include <asm/pci_x86.h>
 
 #include <asm/pci-direct.h>
@@ -378,6 +379,34 @@ static struct notifier_block __cpuinitdata amd_cpu_notifier = {
         .notifier_call  = amd_cpu_notify,
 };
 
+static void __init pci_enable_pci_io_ecs(void)
+{
+#ifdef CONFIG_AMD_NB
+        unsigned int i, n;
+
+        for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
+                u8 bus = amd_nb_bus_dev_ranges[i].bus;
+                u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
+                u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;
+
+                for (; slot < limit; ++slot) {
+                        u32 val = read_pci_config(bus, slot, 3, 0);
+
+                        if (!early_is_amd_nb(val))
+                                continue;
+
+                        val = read_pci_config(bus, slot, 3, 0x8c);
+                        if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
+                                val |= ENABLE_CF8_EXT_CFG >> 32;
+                                write_pci_config(bus, slot, 3, 0x8c, val);
+                        }
+                        ++n;
+                }
+        }
+        pr_info("Extended Config Space enabled on %u nodes\n", n);
+#endif
+}
+
 static int __init pci_io_ecs_init(void)
 {
         int cpu;
@@ -386,6 +415,10 @@ static int __init pci_io_ecs_init(void)
         if (boot_cpu_data.x86 < 0x10)
                 return 0;
 
+        /* Try the PCI method first. */
+        if (early_pci_allowed())
+                pci_enable_pci_io_ecs();
+
         register_cpu_notifier(&amd_cpu_notifier);
         for_each_online_cpu(cpu)
                 amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
diff --git a/arch/x86/pci/ce4100.c b/arch/x86/pci/ce4100.c
new file mode 100644
index 000000000000..85b68ef5e809
--- /dev/null
+++ b/arch/x86/pci/ce4100.c
@@ -0,0 +1,315 @@
+/*
+ *  GPL LICENSE SUMMARY
+ *
+ *  Copyright(c) 2010 Intel Corporation. All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of version 2 of the GNU General Public License as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *  The full GNU General Public License is included in this distribution
+ *  in the file called LICENSE.GPL.
+ *
+ *  Contact Information:
+ *    Intel Corporation
+ *    2200 Mission College Blvd.
+ *    Santa Clara, CA  97052
+ *
+ * This provides access methods for PCI registers that mis-behave on
+ * the CE4100. Each register can be assigned a private init, read and
+ * write routine. The exception to this is the bridge device.  The
+ * bridge device is the only device on bus zero (0) that requires any
+ * fixup so it is a special case ATM
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+
+#include <asm/pci_x86.h>
+
+struct sim_reg {
+        u32 value;
+        u32 mask;
+};
+
+struct sim_dev_reg {
+        int dev_func;
+        int reg;
+        void (*init)(struct sim_dev_reg *reg);
+        void (*read)(struct sim_dev_reg *reg, u32 *value);
+        void (*write)(struct sim_dev_reg *reg, u32 value);
+        struct sim_reg sim_reg;
+};
+
+struct sim_reg_op {
+        void (*init)(struct sim_dev_reg *reg);
+        void (*read)(struct sim_dev_reg *reg, u32 value);
+        void (*write)(struct sim_dev_reg *reg, u32 value);
+};
+
+#define MB (1024 * 1024)
+#define KB (1024)
+#define SIZE_TO_MASK(size) (~(size - 1))
+
+#define DEFINE_REG(device, func, offset, size, init_op, read_op, write_op)\
+{ PCI_DEVFN(device, func), offset, init_op, read_op, write_op,\
+        {0, SIZE_TO_MASK(size)} },
+
+static void reg_init(struct sim_dev_reg *reg)
+{
+        pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4,
+                              &reg->sim_reg.value);
+}
+
+static void reg_read(struct sim_dev_reg *reg, u32 *value)
+{
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
+        *value = reg->sim_reg.value;
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+}
+
+static void reg_write(struct sim_dev_reg *reg, u32 value)
+{
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
+        reg->sim_reg.value = (value & reg->sim_reg.mask) |
+                (reg->sim_reg.value & ~reg->sim_reg.mask);
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+}
+
+static void sata_reg_init(struct sim_dev_reg *reg)
+{
+        pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4,
+                              &reg->sim_reg.value);
+        reg->sim_reg.value += 0x400;
+}
+
+static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value)
+{
+        reg_read(reg, value);
+        if (*value != reg->sim_reg.mask)
+                *value |= 0x100;
+}
+
+void sata_revid_init(struct sim_dev_reg *reg)
+{
+        reg->sim_reg.value = 0x01060100;
+        reg->sim_reg.mask = 0;
+}
+
+static void sata_revid_read(struct sim_dev_reg *reg, u32 *value)
+{
+        reg_read(reg, value);
+}
+
+static struct sim_dev_reg bus1_fixups[] = {
+        DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
+        DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write)
+        DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write)
+        DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write)
+        DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write)
+        DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
+        DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
+        DEFINE_REG(14, 0, 0x8,  0, sata_revid_init, sata_revid_read, 0)
+        DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write)
+        DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write)
+        DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write)
+        DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write)
+        DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write)
+        DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write)
+        DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write)
+        DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write)
+        DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
+        DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write)
+};
+
+static void __init init_sim_regs(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
+                if (bus1_fixups[i].init)
+                        bus1_fixups[i].init(&bus1_fixups[i]);
+        }
+}
+
+static inline void extract_bytes(u32 *value, int reg, int len)
+{
+        uint32_t mask;
+
+        *value >>= ((reg & 3) * 8);
+        mask = 0xFFFFFFFF >> ((4 - len) * 8);
+        *value &= mask;
+}
+
+int bridge_read(unsigned int devfn, int reg, int len, u32 *value)
+{
+        u32 av_bridge_base, av_bridge_limit;
+        int retval = 0;
+
+        switch (reg) {
+        /* Make BARs appear to not request any memory. */
+        case PCI_BASE_ADDRESS_0:
+        case PCI_BASE_ADDRESS_0 + 1:
+        case PCI_BASE_ADDRESS_0 + 2:
+        case PCI_BASE_ADDRESS_0 + 3:
+                *value = 0;
+                break;
+
+                /* Since subordinate bus number register is hardwired
+                 * to zero and read only, so do the simulation.
+                 */
+        case PCI_PRIMARY_BUS:
+                if (len == 4)
+                        *value = 0x00010100;
+                break;
+
+        case PCI_SUBORDINATE_BUS:
+                *value = 1;
+                break;
+
+        case PCI_MEMORY_BASE:
+        case PCI_MEMORY_LIMIT:
+                /* Get the A/V bridge base address. */
+                pci_direct_conf1.read(0, 0, devfn,
+                                PCI_BASE_ADDRESS_0, 4, &av_bridge_base);
+
+                av_bridge_limit = av_bridge_base + (512*MB - 1);
+                av_bridge_limit >>= 16;
+                av_bridge_limit &= 0xFFF0;
+
+                av_bridge_base >>= 16;
+                av_bridge_base &= 0xFFF0;
+
+                if (reg == PCI_MEMORY_LIMIT)
+                        *value = av_bridge_limit;
+                else if (len == 2)
+                        *value = av_bridge_base;
+                else
+                        *value = (av_bridge_limit << 16) | av_bridge_base;
+                break;
+                /* Make prefetchable memory limit smaller than prefetchable
+                 * memory base, so not claim prefetchable memory space.
+                 */
+        case PCI_PREF_MEMORY_BASE:
+                *value = 0xFFF0;
+                break;
+        case PCI_PREF_MEMORY_LIMIT:
+                *value = 0x0;
+                break;
+                /* Make IO limit smaller than IO base, so not claim IO space. */
+        case PCI_IO_BASE:
+                *value = 0xF0;
+                break;
+        case PCI_IO_LIMIT:
+                *value = 0;
+                break;
+        default:
+                retval = 1;
+        }
+        return retval;
+}
+
+static int ce4100_conf_read(unsigned int seg, unsigned int bus,
+                            unsigned int devfn, int reg, int len, u32 *value)
+{
+        int i, retval = 1;
+
+        if (bus == 1) {
+                for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
+                        if (bus1_fixups[i].dev_func == devfn &&
+                            bus1_fixups[i].reg == (reg & ~3) &&
+                            bus1_fixups[i].read) {
+                                bus1_fixups[i].read(&(bus1_fixups[i]),
+                                                    value);
+                                extract_bytes(value, reg, len);
+                                return 0;
+                        }
+                }
+        }
+
+        if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) &&
+            !bridge_read(devfn, reg, len, value))
+                return 0;
+
+        return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
+}
+
+static int ce4100_conf_write(unsigned int seg, unsigned int bus,
+                             unsigned int devfn, int reg, int len, u32 value)
+{
+        int i;
+
+        if (bus == 1) {
+                for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
+                        if (bus1_fixups[i].dev_func == devfn &&
+                            bus1_fixups[i].reg == (reg & ~3) &&
+                            bus1_fixups[i].write) {
+                                bus1_fixups[i].write(&(bus1_fixups[i]),
+                                                     value);
+                                return 0;
+                        }
+                }
+        }
+
+        /* Discard writes to A/V bridge BAR. */
+        if (bus == 0 && PCI_DEVFN(1, 0) == devfn &&
+            ((reg & ~3) == PCI_BASE_ADDRESS_0))
+                return 0;
+
+        return pci_direct_conf1.write(seg, bus, devfn, reg, len, value);
+}
+
+struct pci_raw_ops ce4100_pci_conf = {
+        .read = ce4100_conf_read,
+        .write = ce4100_conf_write,
+};
+
+static int __init ce4100_pci_init(void)
+{
+        init_sim_regs();
+        raw_pci_ops = &ce4100_pci_conf;
+        return 0;
+}
+subsys_initcall(ce4100_pci_init);
diff --git a/arch/x86/pci/pcbios.c b/arch/x86/pci/pcbios.c
index 2492d165096a..a5f7d0d63de0 100644
--- a/arch/x86/pci/pcbios.c
+++ b/arch/x86/pci/pcbios.c
@@ -9,6 +9,7 @@
 #include <linux/uaccess.h>
 #include <asm/pci_x86.h>
 #include <asm/pci-functions.h>
+#include <asm/cacheflush.h>
 
 /* BIOS32 signature: "_32_" */
 #define BIOS32_SIGNATURE        (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
@@ -25,6 +26,27 @@
 #define PCIBIOS_HW_TYPE1_SPEC           0x10
 #define PCIBIOS_HW_TYPE2_SPEC           0x20
 
+int pcibios_enabled;
+
+/* According to the BIOS specification at:
+ * http://members.datafast.net.au/dft0802/specs/bios21.pdf, we could
+ * restrict the x zone to some pages and make it ro. But this may be
+ * broken on some bios, complex to handle with static_protections.
+ * We could make the 0xe0000-0x100000 range rox, but this can break
+ * some ISA mapping.
+ *
+ * So we let's an rw and x hole when pcibios is used. This shouldn't
+ * happen for modern system with mmconfig, and if you don't want it
+ * you could disable pcibios...
+ */
+static inline void set_bios_x(void)
+{
+        pcibios_enabled = 1;
+        set_memory_x(PAGE_OFFSET + BIOS_BEGIN, (BIOS_END - BIOS_BEGIN) >> PAGE_SHIFT);
+        if (__supported_pte_mask & _PAGE_NX)
+                printk(KERN_INFO "PCI : PCI BIOS aera is rw and x. Use pci=nobios if you want it NX.\n");
+}
+
 /*
  * This is the standard structure used to identify the entry point
  * to the BIOS32 Service Directory, as documented in
@@ -332,6 +354,7 @@ static struct pci_raw_ops * __devinit pci_find_bios(void)
                         DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n",
                                         bios32_entry);
                         bios32_indirect.address = bios32_entry + PAGE_OFFSET;
+                        set_bios_x();
                         if (check_pcibios())
                                 return &pci_bios_access;
                 }
diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile
index 7bf70b812fa2..021eee91c056 100644
--- a/arch/x86/platform/Makefile
+++ b/arch/x86/platform/Makefile
@@ -1,5 +1,7 @@
 # Platform specific code goes here
+obj-y   += ce4100/
 obj-y   += efi/
+obj-y   += iris/
 obj-y   += mrst/
 obj-y   += olpc/
 obj-y   += scx200/
diff --git a/arch/x86/platform/ce4100/Makefile b/arch/x86/platform/ce4100/Makefile
new file mode 100644
index 000000000000..91fc92971d94
--- /dev/null
+++ b/arch/x86/platform/ce4100/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_X86_INTEL_CE)      += ce4100.o
diff --git a/arch/x86/platform/ce4100/ce4100.c b/arch/x86/platform/ce4100/ce4100.c
new file mode 100644
index 000000000000..d2c0d51a7178
--- /dev/null
+++ b/arch/x86/platform/ce4100/ce4100.c
@@ -0,0 +1,132 @@
+/*
+ * Intel CE4100  platform specific setup code
+ *
+ * (C) Copyright 2010 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
+
+#include <asm/setup.h>
+#include <asm/io.h>
+
+static int ce4100_i8042_detect(void)
+{
+        return 0;
+}
+
+static void __init sdv_find_smp_config(void)
+{
+}
+
+#ifdef CONFIG_SERIAL_8250
+
+
+static unsigned int mem_serial_in(struct uart_port *p, int offset)
+{
+        offset = offset << p->regshift;
+        return readl(p->membase + offset);
+}
+
+/*
+ * The UART Tx interrupts are not set under some conditions and therefore serial
+ * transmission hangs. This is a silicon issue and has not been root caused. The
+ * workaround for this silicon issue checks UART_LSR_THRE bit and UART_LSR_TEMT
+ * bit of LSR register in interrupt handler to see whether at least one of these
+ * two bits is set, if so then process the transmit request. If this workaround
+ * is not applied, then the serial transmission may hang. This workaround is for
+ * errata number 9 in Errata - B step.
+*/
+
+static unsigned int ce4100_mem_serial_in(struct uart_port *p, int offset)
+{
+        unsigned int ret, ier, lsr;
+
+        if (offset == UART_IIR) {
+                offset = offset << p->regshift;
+                ret = readl(p->membase + offset);
+                if (ret & UART_IIR_NO_INT) {
+                        /* see if the TX interrupt should have really set */
+                        ier = mem_serial_in(p, UART_IER);
+                        /* see if the UART's XMIT interrupt is enabled */
+                        if (ier & UART_IER_THRI) {
+                                lsr = mem_serial_in(p, UART_LSR);
+                                /* now check to see if the UART should be
+                                   generating an interrupt (but isn't) */
+                                if (lsr & (UART_LSR_THRE | UART_LSR_TEMT))
+                                        ret &= ~UART_IIR_NO_INT;
+                        }
+                }
+        } else
+                ret =  mem_serial_in(p, offset);
+        return ret;
+}
+
+static void ce4100_mem_serial_out(struct uart_port *p, int offset, int value)
+{
+        offset = offset << p->regshift;
+        writel(value, p->membase + offset);
+}
+
+static void ce4100_serial_fixup(int port, struct uart_port *up,
+        unsigned short *capabilites)
+{
+#ifdef CONFIG_EARLY_PRINTK
+        /*
+         * Over ride the legacy port configuration that comes from
+         * asm/serial.h. Using the ioport driver then switching to the
+         * PCI memmaped driver hangs the IOAPIC
+         */
+        if (up->iotype !=  UPIO_MEM32) {
+                up->uartclk  = 14745600;
+                up->mapbase = 0xdffe0200;
+                set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
+                                up->mapbase & PAGE_MASK);
+                up->membase =
+                        (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
+                up->membase += up->mapbase & ~PAGE_MASK;
+                up->iotype   = UPIO_MEM32;
+                up->regshift = 2;
+        }
+#endif
+        up->iobase = 0;
+        up->serial_in = ce4100_mem_serial_in;
+        up->serial_out = ce4100_mem_serial_out;
+
+        *capabilites |= (1 << 12);
+}
+
+static __init void sdv_serial_fixup(void)
+{
+        serial8250_set_isa_configurator(ce4100_serial_fixup);
+}
+
+#else
+static inline void sdv_serial_fixup(void);
+#endif
+
+static void __init sdv_arch_setup(void)
+{
+        sdv_serial_fixup();
+}
+
+/*
+ * CE4100 specific x86_init function overrides and early setup
+ * calls.
+ */
+void __init x86_ce4100_early_setup(void)
+{
+        x86_init.oem.arch_setup = sdv_arch_setup;
+        x86_platform.i8042_detect = ce4100_i8042_detect;
+        x86_init.resources.probe_roms = x86_init_noop;
+        x86_init.mpparse.get_smp_config = x86_init_uint_noop;
+        x86_init.mpparse.find_smp_config = sdv_find_smp_config;
+}
diff --git a/arch/x86/platform/iris/Makefile b/arch/x86/platform/iris/Makefile
new file mode 100644
index 000000000000..db921983a102
--- /dev/null
+++ b/arch/x86/platform/iris/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_X86_32_IRIS)               += iris.o
diff --git a/arch/x86/platform/iris/iris.c b/arch/x86/platform/iris/iris.c
new file mode 100644
index 000000000000..1ba7f5ed8c9b
--- /dev/null
+++ b/arch/x86/platform/iris/iris.c
@@ -0,0 +1,91 @@
+/*
+ * Eurobraille/Iris power off support.
+ *
+ * Eurobraille's Iris machine is a PC with no APM or ACPI support.
+ * It is shutdown by a special I/O sequence which this module provides.
+ *
+ *  Copyright (C) Shérab <Sebastien.Hinderer@ens-lyon.org>
+ *
+ * This program is free software ; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation ; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY ; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with the program ; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/moduleparam.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <asm/io.h>
+
+#define IRIS_GIO_BASE           0x340
+#define IRIS_GIO_INPUT          IRIS_GIO_BASE
+#define IRIS_GIO_OUTPUT         (IRIS_GIO_BASE + 1)
+#define IRIS_GIO_PULSE          0x80 /* First byte to send */
+#define IRIS_GIO_REST           0x00 /* Second byte to send */
+#define IRIS_GIO_NODEV          0xff /* Likely not an Iris */
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Sébastien Hinderer <Sebastien.Hinderer@ens-lyon.org>");
+MODULE_DESCRIPTION("A power_off handler for Iris devices from EuroBraille");
+MODULE_SUPPORTED_DEVICE("Eurobraille/Iris");
+
+static int force;
+
+module_param(force, bool, 0);
+MODULE_PARM_DESC(force, "Set to one to force poweroff handler installation.");
+
+static void (*old_pm_power_off)(void);
+
+static void iris_power_off(void)
+{
+        outb(IRIS_GIO_PULSE, IRIS_GIO_OUTPUT);
+        msleep(850);
+        outb(IRIS_GIO_REST, IRIS_GIO_OUTPUT);
+}
+
+/*
+ * Before installing the power_off handler, try to make sure the OS is
+ * running on an Iris.  Since Iris does not support DMI, this is done
+ * by reading its input port and seeing whether the read value is
+ * meaningful.
+ */
+static int iris_init(void)
+{
+        unsigned char status;
+        if (force != 1) {
+                printk(KERN_ERR "The force parameter has not been set to 1 so the Iris poweroff handler will not be installed.\n");
+                return -ENODEV;
+        }
+        status = inb(IRIS_GIO_INPUT);
+        if (status == IRIS_GIO_NODEV) {
+                printk(KERN_ERR "This machine does not seem to be an Iris. Power_off handler not installed.\n");
+                return -ENODEV;
+        }
+        old_pm_power_off = pm_power_off;
+        pm_power_off = &iris_power_off;
+        printk(KERN_INFO "Iris power_off handler installed.\n");
+
+        return 0;
+}
+
+static void iris_exit(void)
+{
+        pm_power_off = old_pm_power_off;
+        printk(KERN_INFO "Iris power_off handler uninstalled.\n");
+}
+
+module_init(iris_init);
+module_exit(iris_exit);
diff --git a/arch/x86/platform/mrst/Makefile b/arch/x86/platform/mrst/Makefile
index efbbc552fa95..f61ccdd49341 100644
--- a/arch/x86/platform/mrst/Makefile
+++ b/arch/x86/platform/mrst/Makefile
@@ -1 +1,3 @@
 obj-$(CONFIG_X86_MRST)          += mrst.o
+obj-$(CONFIG_X86_MRST)          += vrtc.o
+obj-$(CONFIG_EARLY_PRINTK_MRST) += early_printk_mrst.o
diff --git a/arch/x86/kernel/early_printk_mrst.c b/arch/x86/platform/mrst/early_printk_mrst.c
index 65df603622b2..65df603622b2 100644
--- a/arch/x86/kernel/early_printk_mrst.c
+++ b/arch/x86/platform/mrst/early_printk_mrst.c
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index 79ae68154e87..ea6529e93c6f 100644
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -9,9 +9,19 @@
  * as published by the Free Software Foundation; version 2
  * of the License.
  */
+
+#define pr_fmt(fmt) "mrst: " fmt
+
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/sfi.h>
+#include <linux/intel_pmic_gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <linux/module.h>
 
@@ -23,7 +33,9 @@
 #include <asm/mrst.h>
 #include <asm/io.h>
 #include <asm/i8259.h>
+#include <asm/intel_scu_ipc.h>
 #include <asm/apb_timer.h>
+#include <asm/reboot.h>
 
 /*
  * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
@@ -59,32 +71,6 @@ struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
 EXPORT_SYMBOL_GPL(sfi_mrtc_array);
 int sfi_mrtc_num;
 
-static inline void assign_to_mp_irq(struct mpc_intsrc *m,
-                                    struct mpc_intsrc *mp_irq)
-{
-        memcpy(mp_irq, m, sizeof(struct mpc_intsrc));
-}
-
-static inline int mp_irq_cmp(struct mpc_intsrc *mp_irq,
-                                struct mpc_intsrc *m)
-{
-        return memcmp(mp_irq, m, sizeof(struct mpc_intsrc));
-}
-
-static void save_mp_irq(struct mpc_intsrc *m)
-{
-        int i;
-
-        for (i = 0; i < mp_irq_entries; i++) {
-                if (!mp_irq_cmp(&mp_irqs[i], m))
-                        return;
-        }
-
-        assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
-        if (++mp_irq_entries == MAX_IRQ_SOURCES)
-                panic("Max # of irq sources exceeded!!\n");
-}
-
 /* parse all the mtimer info to a static mtimer array */
 static int __init sfi_parse_mtmr(struct sfi_table_header *table)
 {
@@ -102,10 +88,10 @@ static int __init sfi_parse_mtmr(struct sfi_table_header *table)
                 memcpy(sfi_mtimer_array, pentry, totallen);
         }
 
-        printk(KERN_INFO "SFI: MTIMER info (num = %d):\n", sfi_mtimer_num);
+        pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
         pentry = sfi_mtimer_array;
         for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
-                printk(KERN_INFO "timer[%d]: paddr = 0x%08x, freq = %dHz,"
+                pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz,"
                         " irq = %d\n", totallen, (u32)pentry->phys_addr,
                         pentry->freq_hz, pentry->irq);
                         if (!pentry->irq)
@@ -118,7 +104,7 @@ static int __init sfi_parse_mtmr(struct sfi_table_header *table)
                         mp_irq.srcbusirq = pentry->irq; /* IRQ */
                         mp_irq.dstapic = MP_APIC_ALL;
                         mp_irq.dstirq = pentry->irq;
-                        save_mp_irq(&mp_irq);
+                        mp_save_irq(&mp_irq);
         }
 
         return 0;
@@ -176,19 +162,19 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
                 memcpy(sfi_mrtc_array, pentry, totallen);
         }
 
-        printk(KERN_INFO "SFI: RTC info (num = %d):\n", sfi_mrtc_num);
+        pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
         pentry = sfi_mrtc_array;
         for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
-                printk(KERN_INFO "RTC[%d]: paddr = 0x%08x, irq = %d\n",
+                pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
                         totallen, (u32)pentry->phys_addr, pentry->irq);
                 mp_irq.type = MP_IOAPIC;
                 mp_irq.irqtype = mp_INT;
-                mp_irq.irqflag = 0;
+                mp_irq.irqflag = 0xf;   /* level trigger and active low */
                 mp_irq.srcbus = 0;
                 mp_irq.srcbusirq = pentry->irq; /* IRQ */
                 mp_irq.dstapic = MP_APIC_ALL;
                 mp_irq.dstirq = pentry->irq;
-                save_mp_irq(&mp_irq);
+                mp_save_irq(&mp_irq);
         }
         return 0;
 }
@@ -209,6 +195,7 @@ static unsigned long __init mrst_calibrate_tsc(void)
 
 void __init mrst_time_init(void)
 {
+        sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
         switch (mrst_timer_options) {
         case MRST_TIMER_APBT_ONLY:
                 break;
@@ -224,16 +211,10 @@ void __init mrst_time_init(void)
                 return;
         }
         /* we need at least one APB timer */
-        sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
         pre_init_apic_IRQ0();
         apbt_time_init();
 }
 
-void __init mrst_rtc_init(void)
-{
-        sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
-}
-
 void __cpuinit mrst_arch_setup(void)
 {
         if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
@@ -256,6 +237,17 @@ static int mrst_i8042_detect(void)
         return 0;
 }
 
+/* Reboot and power off are handled by the SCU on a MID device */
+static void mrst_power_off(void)
+{
+        intel_scu_ipc_simple_command(0xf1, 1);
+}
+
+static void mrst_reboot(void)
+{
+        intel_scu_ipc_simple_command(0xf1, 0);
+}
+
 /*
  * Moorestown specific x86_init function overrides and early setup
  * calls.
@@ -281,6 +273,10 @@ void __init x86_mrst_early_setup(void)
 
         legacy_pic = &null_legacy_pic;
 
+        /* Moorestown specific power_off/restart method */
+        pm_power_off = mrst_power_off;
+        machine_ops.emergency_restart  = mrst_reboot;
+
         /* Avoid searching for BIOS MP tables */
         x86_init.mpparse.find_smp_config = x86_init_noop;
         x86_init.mpparse.get_smp_config = x86_init_uint_noop;
@@ -309,3 +305,505 @@ static inline int __init setup_x86_mrst_timer(char *arg)
         return 0;
 }
 __setup("x86_mrst_timer=", setup_x86_mrst_timer);
+
+/*
+ * Parsing GPIO table first, since the DEVS table will need this table
+ * to map the pin name to the actual pin.
+ */
+static struct sfi_gpio_table_entry *gpio_table;
+static int gpio_num_entry;
+
+static int __init sfi_parse_gpio(struct sfi_table_header *table)
+{
+        struct sfi_table_simple *sb;
+        struct sfi_gpio_table_entry *pentry;
+        int num, i;
+
+        if (gpio_table)
+                return 0;
+        sb = (struct sfi_table_simple *)table;
+        num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
+        pentry = (struct sfi_gpio_table_entry *)sb->pentry;
+
+        gpio_table = (struct sfi_gpio_table_entry *)
+                                kmalloc(num * sizeof(*pentry), GFP_KERNEL);
+        if (!gpio_table)
+                return -1;
+        memcpy(gpio_table, pentry, num * sizeof(*pentry));
+        gpio_num_entry = num;
+
+        pr_debug("GPIO pin info:\n");
+        for (i = 0; i < num; i++, pentry++)
+                pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
+                " pin = %d\n", i,
+                        pentry->controller_name,
+                        pentry->pin_name,
+                        pentry->pin_no);
+        return 0;
+}
+
+static int get_gpio_by_name(const char *name)
+{
+        struct sfi_gpio_table_entry *pentry = gpio_table;
+        int i;
+
+        if (!pentry)
+                return -1;
+        for (i = 0; i < gpio_num_entry; i++, pentry++) {
+                if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
+                        return pentry->pin_no;
+        }
+        return -1;
+}
+
+/*
+ * Here defines the array of devices platform data that IAFW would export
+ * through SFI "DEVS" table, we use name and type to match the device and
+ * its platform data.
+ */
+struct devs_id {
+        char name[SFI_NAME_LEN + 1];
+        u8 type;
+        u8 delay;
+        void *(*get_platform_data)(void *info);
+};
+
+/* the offset for the mapping of global gpio pin to irq */
+#define MRST_IRQ_OFFSET 0x100
+
+static void __init *pmic_gpio_platform_data(void *info)
+{
+        static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
+        int gpio_base = get_gpio_by_name("pmic_gpio_base");
+
+        if (gpio_base == -1)
+                gpio_base = 64;
+        pmic_gpio_pdata.gpio_base = gpio_base;
+        pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET;
+        pmic_gpio_pdata.gpiointr = 0xffffeff8;
+
+        return &pmic_gpio_pdata;
+}
+
+static void __init *max3111_platform_data(void *info)
+{
+        struct spi_board_info *spi_info = info;
+        int intr = get_gpio_by_name("max3111_int");
+
+        if (intr == -1)
+                return NULL;
+        spi_info->irq = intr + MRST_IRQ_OFFSET;
+        return NULL;
+}
+
+/* we have multiple max7315 on the board ... */
+#define MAX7315_NUM 2
+static void __init *max7315_platform_data(void *info)
+{
+        static struct pca953x_platform_data max7315_pdata[MAX7315_NUM];
+        static int nr;
+        struct pca953x_platform_data *max7315 = &max7315_pdata[nr];
+        struct i2c_board_info *i2c_info = info;
+        int gpio_base, intr;
+        char base_pin_name[SFI_NAME_LEN + 1];
+        char intr_pin_name[SFI_NAME_LEN + 1];
+
+        if (nr == MAX7315_NUM) {
+                pr_err("too many max7315s, we only support %d\n",
+                                MAX7315_NUM);
+                return NULL;
+        }
+        /* we have several max7315 on the board, we only need load several
+         * instances of the same pca953x driver to cover them
+         */
+        strcpy(i2c_info->type, "max7315");
+        if (nr++) {
+                sprintf(base_pin_name, "max7315_%d_base", nr);
+                sprintf(intr_pin_name, "max7315_%d_int", nr);
+        } else {
+                strcpy(base_pin_name, "max7315_base");
+                strcpy(intr_pin_name, "max7315_int");
+        }
+
+        gpio_base = get_gpio_by_name(base_pin_name);
+        intr = get_gpio_by_name(intr_pin_name);
+
+        if (gpio_base == -1)
+                return NULL;
+        max7315->gpio_base = gpio_base;
+        if (intr != -1) {
+                i2c_info->irq = intr + MRST_IRQ_OFFSET;
+                max7315->irq_base = gpio_base + MRST_IRQ_OFFSET;
+        } else {
+                i2c_info->irq = -1;
+                max7315->irq_base = -1;
+        }
+        return max7315;
+}
+
+static void __init *emc1403_platform_data(void *info)
+{
+        static short intr2nd_pdata;
+        struct i2c_board_info *i2c_info = info;
+        int intr = get_gpio_by_name("thermal_int");
+        int intr2nd = get_gpio_by_name("thermal_alert");
+
+        if (intr == -1 || intr2nd == -1)
+                return NULL;
+
+        i2c_info->irq = intr + MRST_IRQ_OFFSET;
+        intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
+
+        return &intr2nd_pdata;
+}
+
+static void __init *lis331dl_platform_data(void *info)
+{
+        static short intr2nd_pdata;
+        struct i2c_board_info *i2c_info = info;
+        int intr = get_gpio_by_name("accel_int");
+        int intr2nd = get_gpio_by_name("accel_2");
+
+        if (intr == -1 || intr2nd == -1)
+                return NULL;
+
+        i2c_info->irq = intr + MRST_IRQ_OFFSET;
+        intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
+
+        return &intr2nd_pdata;
+}
+
+static void __init *no_platform_data(void *info)
+{
+        return NULL;
+}
+
+static const struct devs_id __initconst device_ids[] = {
+        {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
+        {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
+        {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
+        {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
+        {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
+        {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
+        {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
+        {"msic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
+        {},
+};
+
+#define MAX_IPCDEVS     24
+static struct platform_device *ipc_devs[MAX_IPCDEVS];
+static int ipc_next_dev;
+
+#define MAX_SCU_SPI     24
+static struct spi_board_info *spi_devs[MAX_SCU_SPI];
+static int spi_next_dev;
+
+#define MAX_SCU_I2C     24
+static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
+static int i2c_bus[MAX_SCU_I2C];
+static int i2c_next_dev;
+
+static void __init intel_scu_device_register(struct platform_device *pdev)
+{
+        if(ipc_next_dev == MAX_IPCDEVS)
+                pr_err("too many SCU IPC devices");
+        else
+                ipc_devs[ipc_next_dev++] = pdev;
+}
+
+static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
+{
+        struct spi_board_info *new_dev;
+
+        if (spi_next_dev == MAX_SCU_SPI) {
+                pr_err("too many SCU SPI devices");
+                return;
+        }
+
+        new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
+        if (!new_dev) {
+                pr_err("failed to alloc mem for delayed spi dev %s\n",
+                        sdev->modalias);
+                return;
+        }
+        memcpy(new_dev, sdev, sizeof(*sdev));
+
+        spi_devs[spi_next_dev++] = new_dev;
+}
+
+static void __init intel_scu_i2c_device_register(int bus,
+                                                struct i2c_board_info *idev)
+{
+        struct i2c_board_info *new_dev;
+
+        if (i2c_next_dev == MAX_SCU_I2C) {
+                pr_err("too many SCU I2C devices");
+                return;
+        }
+
+        new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
+        if (!new_dev) {
+                pr_err("failed to alloc mem for delayed i2c dev %s\n",
+                        idev->type);
+                return;
+        }
+        memcpy(new_dev, idev, sizeof(*idev));
+
+        i2c_bus[i2c_next_dev] = bus;
+        i2c_devs[i2c_next_dev++] = new_dev;
+}
+
+/* Called by IPC driver */
+void intel_scu_devices_create(void)
+{
+        int i;
+
+        for (i = 0; i < ipc_next_dev; i++)
+                platform_device_add(ipc_devs[i]);
+
+        for (i = 0; i < spi_next_dev; i++)
+                spi_register_board_info(spi_devs[i], 1);
+
+        for (i = 0; i < i2c_next_dev; i++) {
+                struct i2c_adapter *adapter;
+                struct i2c_client *client;
+
+                adapter = i2c_get_adapter(i2c_bus[i]);
+                if (adapter) {
+                        client = i2c_new_device(adapter, i2c_devs[i]);
+                        if (!client)
+                                pr_err("can't create i2c device %s\n",
+                                        i2c_devs[i]->type);
+                } else
+                        i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
+        }
+}
+EXPORT_SYMBOL_GPL(intel_scu_devices_create);
+
+/* Called by IPC driver */
+void intel_scu_devices_destroy(void)
+{
+        int i;
+
+        for (i = 0; i < ipc_next_dev; i++)
+                platform_device_del(ipc_devs[i]);
+}
+EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
+
+static void __init install_irq_resource(struct platform_device *pdev, int irq)
+{
+        /* Single threaded */
+        static struct resource __initdata res = {
+                .name = "IRQ",
+                .flags = IORESOURCE_IRQ,
+        };
+        res.start = irq;
+        platform_device_add_resources(pdev, &res, 1);
+}
+
+static void __init sfi_handle_ipc_dev(struct platform_device *pdev)
+{
+        const struct devs_id *dev = device_ids;
+        void *pdata = NULL;
+
+        while (dev->name[0]) {
+                if (dev->type == SFI_DEV_TYPE_IPC &&
+                        !strncmp(dev->name, pdev->name, SFI_NAME_LEN)) {
+                        pdata = dev->get_platform_data(pdev);
+                        break;
+                }
+                dev++;
+        }
+        pdev->dev.platform_data = pdata;
+        intel_scu_device_register(pdev);
+}
+
+static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info)
+{
+        const struct devs_id *dev = device_ids;
+        void *pdata = NULL;
+
+        while (dev->name[0]) {
+                if (dev->type == SFI_DEV_TYPE_SPI &&
+                                !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) {
+                        pdata = dev->get_platform_data(spi_info);
+                        break;
+                }
+                dev++;
+        }
+        spi_info->platform_data = pdata;
+        if (dev->delay)
+                intel_scu_spi_device_register(spi_info);
+        else
+                spi_register_board_info(spi_info, 1);
+}
+
+static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info)
+{
+        const struct devs_id *dev = device_ids;
+        void *pdata = NULL;
+
+        while (dev->name[0]) {
+                if (dev->type == SFI_DEV_TYPE_I2C &&
+                        !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) {
+                        pdata = dev->get_platform_data(i2c_info);
+                        break;
+                }
+                dev++;
+        }
+        i2c_info->platform_data = pdata;
+
+        if (dev->delay)
+                intel_scu_i2c_device_register(bus, i2c_info);
+        else
+                i2c_register_board_info(bus, i2c_info, 1);
+ }
+
+
+static int __init sfi_parse_devs(struct sfi_table_header *table)
+{
+        struct sfi_table_simple *sb;
+        struct sfi_device_table_entry *pentry;
+        struct spi_board_info spi_info;
+        struct i2c_board_info i2c_info;
+        struct platform_device *pdev;
+        int num, i, bus;
+        int ioapic;
+        struct io_apic_irq_attr irq_attr;
+
+        sb = (struct sfi_table_simple *)table;
+        num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
+        pentry = (struct sfi_device_table_entry *)sb->pentry;
+
+        for (i = 0; i < num; i++, pentry++) {
+                if (pentry->irq != (u8)0xff) { /* native RTE case */
+                        /* these SPI2 devices are not exposed to system as PCI
+                         * devices, but they have separate RTE entry in IOAPIC
+                         * so we have to enable them one by one here
+                         */
+                        ioapic = mp_find_ioapic(pentry->irq);
+                        irq_attr.ioapic = ioapic;
+                        irq_attr.ioapic_pin = pentry->irq;
+                        irq_attr.trigger = 1;
+                        irq_attr.polarity = 1;
+                        io_apic_set_pci_routing(NULL, pentry->irq, &irq_attr);
+                }
+                switch (pentry->type) {
+                case SFI_DEV_TYPE_IPC:
+                        /* ID as IRQ is a hack that will go away */
+                        pdev = platform_device_alloc(pentry->name, pentry->irq);
+                        if (pdev == NULL) {
+                                pr_err("out of memory for SFI platform device '%s'.\n",
+                                                        pentry->name);
+                                continue;
+                        }
+                        install_irq_resource(pdev, pentry->irq);
+                        pr_debug("info[%2d]: IPC bus, name = %16.16s, "
+                                "irq = 0x%2x\n", i, pentry->name, pentry->irq);
+                        sfi_handle_ipc_dev(pdev);
+                        break;
+                case SFI_DEV_TYPE_SPI:
+                        memset(&spi_info, 0, sizeof(spi_info));
+                        strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
+                        spi_info.irq = pentry->irq;
+                        spi_info.bus_num = pentry->host_num;
+                        spi_info.chip_select = pentry->addr;
+                        spi_info.max_speed_hz = pentry->max_freq;
+                        pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, "
+                                "irq = 0x%2x, max_freq = %d, cs = %d\n", i,
+                                spi_info.bus_num,
+                                spi_info.modalias,
+                                spi_info.irq,
+                                spi_info.max_speed_hz,
+                                spi_info.chip_select);
+                        sfi_handle_spi_dev(&spi_info);
+                        break;
+                case SFI_DEV_TYPE_I2C:
+                        memset(&i2c_info, 0, sizeof(i2c_info));
+                        bus = pentry->host_num;
+                        strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
+                        i2c_info.irq = pentry->irq;
+                        i2c_info.addr = pentry->addr;
+                        pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
+                                "irq = 0x%2x, addr = 0x%x\n", i, bus,
+                                i2c_info.type,
+                                i2c_info.irq,
+                                i2c_info.addr);
+                        sfi_handle_i2c_dev(bus, &i2c_info);
+                        break;
+                case SFI_DEV_TYPE_UART:
+                case SFI_DEV_TYPE_HSI:
+                default:
+                        ;
+                }
+        }
+        return 0;
+}
+
+static int __init mrst_platform_init(void)
+{
+        sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
+        sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
+        return 0;
+}
+arch_initcall(mrst_platform_init);
+
+/*
+ * we will search these buttons in SFI GPIO table (by name)
+ * and register them dynamically. Please add all possible
+ * buttons here, we will shrink them if no GPIO found.
+ */
+static struct gpio_keys_button gpio_button[] = {
+        {KEY_POWER,             -1, 1, "power_btn",     EV_KEY, 0, 3000},
+        {KEY_PROG1,             -1, 1, "prog_btn1",     EV_KEY, 0, 20},
+        {KEY_PROG2,             -1, 1, "prog_btn2",     EV_KEY, 0, 20},
+        {SW_LID,                -1, 1, "lid_switch",    EV_SW,  0, 20},
+        {KEY_VOLUMEUP,          -1, 1, "vol_up",        EV_KEY, 0, 20},
+        {KEY_VOLUMEDOWN,        -1, 1, "vol_down",      EV_KEY, 0, 20},
+        {KEY_CAMERA,            -1, 1, "camera_full",   EV_KEY, 0, 20},
+        {KEY_CAMERA_FOCUS,      -1, 1, "camera_half",   EV_KEY, 0, 20},
+        {SW_KEYPAD_SLIDE,       -1, 1, "MagSw1",        EV_SW,  0, 20},
+        {SW_KEYPAD_SLIDE,       -1, 1, "MagSw2",        EV_SW,  0, 20},
+};
+
+static struct gpio_keys_platform_data mrst_gpio_keys = {
+        .buttons        = gpio_button,
+        .rep            = 1,
+        .nbuttons       = -1, /* will fill it after search */
+};
+
+static struct platform_device pb_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &mrst_gpio_keys,
+        },
+};
+
+/*
+ * Shrink the non-existent buttons, register the gpio button
+ * device if there is some
+ */
+static int __init pb_keys_init(void)
+{
+        struct gpio_keys_button *gb = gpio_button;
+        int i, num, good = 0;
+
+        num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
+        for (i = 0; i < num; i++) {
+                gb[i].gpio = get_gpio_by_name(gb[i].desc);
+                if (gb[i].gpio == -1)
+                        continue;
+
+                if (i != good)
+                        gb[good] = gb[i];
+                good++;
+        }
+
+        if (good) {
+                mrst_gpio_keys.nbuttons = good;
+                return platform_device_register(&pb_device);
+        }
+        return 0;
+}
+late_initcall(pb_keys_init);
diff --git a/arch/x86/platform/mrst/vrtc.c b/arch/x86/platform/mrst/vrtc.c
new file mode 100644
index 000000000000..32cd7edd71a0
--- /dev/null
+++ b/arch/x86/platform/mrst/vrtc.c
@@ -0,0 +1,165 @@
+/*
+ * vrtc.c: Driver for virtual RTC device on Intel MID platform
+ *
+ * (C) Copyright 2009 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ *
+ * Note:
+ * VRTC is emulated by system controller firmware, the real HW
+ * RTC is located in the PMIC device. SCU FW shadows PMIC RTC
+ * in a memory mapped IO space that is visible to the host IA
+ * processor.
+ *
+ * This driver is based on RTC CMOS driver.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sfi.h>
+#include <linux/platform_device.h>
+
+#include <asm/mrst.h>
+#include <asm/mrst-vrtc.h>
+#include <asm/time.h>
+#include <asm/fixmap.h>
+
+static unsigned char __iomem *vrtc_virt_base;
+
+unsigned char vrtc_cmos_read(unsigned char reg)
+{
+        unsigned char retval;
+
+        /* vRTC's registers range from 0x0 to 0xD */
+        if (reg > 0xd || !vrtc_virt_base)
+                return 0xff;
+
+        lock_cmos_prefix(reg);
+        retval = __raw_readb(vrtc_virt_base + (reg << 2));
+        lock_cmos_suffix(reg);
+        return retval;
+}
+EXPORT_SYMBOL_GPL(vrtc_cmos_read);
+
+void vrtc_cmos_write(unsigned char val, unsigned char reg)
+{
+        if (reg > 0xd || !vrtc_virt_base)
+                return;
+
+        lock_cmos_prefix(reg);
+        __raw_writeb(val, vrtc_virt_base + (reg << 2));
+        lock_cmos_suffix(reg);
+}
+EXPORT_SYMBOL_GPL(vrtc_cmos_write);
+
+unsigned long vrtc_get_time(void)
+{
+        u8 sec, min, hour, mday, mon;
+        u32 year;
+
+        while ((vrtc_cmos_read(RTC_FREQ_SELECT) & RTC_UIP))
+                cpu_relax();
+
+        sec = vrtc_cmos_read(RTC_SECONDS);
+        min = vrtc_cmos_read(RTC_MINUTES);
+        hour = vrtc_cmos_read(RTC_HOURS);
+        mday = vrtc_cmos_read(RTC_DAY_OF_MONTH);
+        mon = vrtc_cmos_read(RTC_MONTH);
+        year = vrtc_cmos_read(RTC_YEAR);
+
+        /* vRTC YEAR reg contains the offset to 1960 */
+        year += 1960;
+
+        printk(KERN_INFO "vRTC: sec: %d min: %d hour: %d day: %d "
+                "mon: %d year: %d\n", sec, min, hour, mday, mon, year);
+
+        return mktime(year, mon, mday, hour, min, sec);
+}
+
+/* Only care about the minutes and seconds */
+int vrtc_set_mmss(unsigned long nowtime)
+{
+        int real_sec, real_min;
+        int vrtc_min;
+
+        vrtc_min = vrtc_cmos_read(RTC_MINUTES);
+
+        real_sec = nowtime % 60;
+        real_min = nowtime / 60;
+        if (((abs(real_min - vrtc_min) + 15)/30) & 1)
+                real_min += 30;
+        real_min %= 60;
+
+        vrtc_cmos_write(real_sec, RTC_SECONDS);
+        vrtc_cmos_write(real_min, RTC_MINUTES);
+        return 0;
+}
+
+void __init mrst_rtc_init(void)
+{
+        unsigned long rtc_paddr;
+        void __iomem *virt_base;
+
+        sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
+        if (!sfi_mrtc_num)
+                return;
+
+        rtc_paddr = sfi_mrtc_array[0].phys_addr;
+
+        /* vRTC's register address may not be page aligned */
+        set_fixmap_nocache(FIX_LNW_VRTC, rtc_paddr);
+
+        virt_base = (void __iomem *)__fix_to_virt(FIX_LNW_VRTC);
+        virt_base += rtc_paddr & ~PAGE_MASK;
+        vrtc_virt_base = virt_base;
+
+        x86_platform.get_wallclock = vrtc_get_time;
+        x86_platform.set_wallclock = vrtc_set_mmss;
+}
+
+/*
+ * The Moorestown platform has a memory mapped virtual RTC device that emulates
+ * the programming interface of the RTC.
+ */
+
+static struct resource vrtc_resources[] = {
+        [0] = {
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device vrtc_device = {
+        .name           = "rtc_mrst",
+        .id             = -1,
+        .resource       = vrtc_resources,
+        .num_resources  = ARRAY_SIZE(vrtc_resources),
+};
+
+/* Register the RTC device if appropriate */
+static int __init mrst_device_create(void)
+{
+        /* No Moorestown, no device */
+        if (!mrst_identify_cpu())
+                return -ENODEV;
+        /* No timer, no device */
+        if (!sfi_mrtc_num)
+                return -ENODEV;
+
+        /* iomem resource */
+        vrtc_resources[0].start = sfi_mrtc_array[0].phys_addr;
+        vrtc_resources[0].end = sfi_mrtc_array[0].phys_addr +
+                                MRST_VRTC_MAP_SZ;
+        /* irq resource */
+        vrtc_resources[1].start = sfi_mrtc_array[0].irq;
+        vrtc_resources[1].end = sfi_mrtc_array[0].irq;
+
+        return platform_device_register(&vrtc_device);
+}
+
+module_init(mrst_device_create);
diff --git a/arch/x86/platform/sfi/sfi.c b/arch/x86/platform/sfi/sfi.c
index dd4c281ffe57..7785b72ecc3a 100644
--- a/arch/x86/platform/sfi/sfi.c
+++ b/arch/x86/platform/sfi/sfi.c
@@ -34,23 +34,12 @@
 #ifdef CONFIG_X86_LOCAL_APIC
 static unsigned long sfi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
 
-static void __init mp_sfi_register_lapic_address(unsigned long address)
-{
-        mp_lapic_addr = address;
-
-        set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
-        if (boot_cpu_physical_apicid == -1U)
-                boot_cpu_physical_apicid = read_apic_id();
-
-        pr_info("Boot CPU = %d\n", boot_cpu_physical_apicid);
-}
-
 /* All CPUs enumerated by SFI must be present and enabled */
 static void __cpuinit mp_sfi_register_lapic(u8 id)
 {
-        if (MAX_APICS - id <= 0) {
+        if (MAX_LOCAL_APIC - id <= 0) {
                 pr_warning("Processor #%d invalid (max %d)\n",
-                        id, MAX_APICS);
+                        id, MAX_LOCAL_APIC);
                 return;
         }
 
@@ -110,7 +99,7 @@ static int __init sfi_parse_ioapic(struct sfi_table_header *table)
 int __init sfi_platform_init(void)
 {
 #ifdef CONFIG_X86_LOCAL_APIC
-        mp_sfi_register_lapic_address(sfi_lapic_addr);
+        register_lapic_address(sfi_lapic_addr);
         sfi_table_parse(SFI_SIG_CPUS, NULL, NULL, sfi_parse_cpus);
 #endif
 #ifdef CONFIG_X86_IO_APIC
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index ba9caa808a9c..df58e9cad96a 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -1341,7 +1341,7 @@ uv_activation_descriptor_init(int node, int pnode)
 
         /*
          * each bau_desc is 64 bytes; there are 8 (UV_ITEMS_PER_DESCRIPTOR)
-         * per cpu; and up to 32 (UV_ADP_SIZE) cpu's per uvhub
+         * per cpu; and one per cpu on the uvhub (UV_ADP_SIZE)
          */
         bau_desc = kmalloc_node(sizeof(struct bau_desc) * UV_ADP_SIZE
                                 * UV_ITEMS_PER_DESCRIPTOR, GFP_KERNEL, node);
@@ -1490,7 +1490,7 @@ calculate_destination_timeout(void)
 /*
  * initialize the bau_control structure for each cpu
  */
-static void __init uv_init_per_cpu(int nuvhubs)
+static int __init uv_init_per_cpu(int nuvhubs)
 {
         int i;
         int cpu;
@@ -1507,7 +1507,7 @@ static void __init uv_init_per_cpu(int nuvhubs)
         struct bau_control *smaster = NULL;
         struct socket_desc {
                 short num_cpus;
-                short cpu_number[16];
+                short cpu_number[MAX_CPUS_PER_SOCKET];
         };
         struct uvhub_desc {
                 unsigned short socket_mask;
@@ -1540,6 +1540,10 @@ static void __init uv_init_per_cpu(int nuvhubs)
                 sdp = &bdp->socket[socket];
                 sdp->cpu_number[sdp->num_cpus] = cpu;
                 sdp->num_cpus++;
+                if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
+                        printk(KERN_EMERG "%d cpus per socket invalid\n", sdp->num_cpus);
+                        return 1;
+                }
         }
         for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
                 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
@@ -1570,6 +1574,12 @@ static void __init uv_init_per_cpu(int nuvhubs)
                                 bcp->uvhub_master = hmaster;
                                 bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->
                                                 blade_processor_id;
+                                if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
+                                        printk(KERN_EMERG
+                                                "%d cpus per uvhub invalid\n",
+                                                bcp->uvhub_cpu);
+                                        return 1;
+                                }
                         }
 nextsocket:
                         socket++;
@@ -1595,6 +1605,7 @@ nextsocket:
                 bcp->congested_reps = congested_reps;
                 bcp->congested_period = congested_period;
         }
+        return 0;
 }
 
 /*
@@ -1625,7 +1636,10 @@ static int __init uv_bau_init(void)
         spin_lock_init(&disable_lock);
         congested_cycles = microsec_2_cycles(congested_response_us);
 
-        uv_init_per_cpu(nuvhubs);
+        if (uv_init_per_cpu(nuvhubs)) {
+                nobau = 1;
+                return 0;
+        }
 
         uv_partition_base_pnode = 0x7fffffff;
         for (uvhub = 0; uvhub < nuvhubs; uvhub++)
diff --git a/arch/x86/platform/visws/visws_quirks.c b/arch/x86/platform/visws/visws_quirks.c
index 3371bd053b89..632037671746 100644
--- a/arch/x86/platform/visws/visws_quirks.c
+++ b/arch/x86/platform/visws/visws_quirks.c
@@ -171,7 +171,7 @@ static void __init MP_processor_info(struct mpc_cpu *m)
         ver = m->apicver;
         if ((ver >= 0x14 && m->apicid >= 0xff) || m->apicid >= 0xf) {
                 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
-                        m->apicid, MAX_APICS);
+                        m->apicid, MAX_LOCAL_APIC);
                 return;
         }
 
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 44dcad43989d..7e8d3bc80af6 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -574,8 +574,8 @@ static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g)
 
         preempt_disable();
 
-        start = __get_cpu_var(idt_desc).address;
-        end = start + __get_cpu_var(idt_desc).size + 1;
+        start = __this_cpu_read(idt_desc.address);
+        end = start + __this_cpu_read(idt_desc.size) + 1;
 
         xen_mc_flush();
 
@@ -1174,6 +1174,15 @@ asmlinkage void __init xen_start_kernel(void)
 
         xen_smp_init();
 
+#ifdef CONFIG_ACPI_NUMA
+        /*
+         * The pages we from Xen are not related to machine pages, so
+         * any NUMA information the kernel tries to get from ACPI will
+         * be meaningless.  Prevent it from trying.
+         */
+        acpi_numa = -1;
+#endif
+
         pgd = (pgd_t *)xen_start_info->pt_base;
 
         if (!xen_initial_domain())
@@ -1256,25 +1265,6 @@ asmlinkage void __init xen_start_kernel(void)
 #endif
 }
 
-static uint32_t xen_cpuid_base(void)
-{
-        uint32_t base, eax, ebx, ecx, edx;
-        char signature[13];
-
-        for (base = 0x40000000; base < 0x40010000; base += 0x100) {
-                cpuid(base, &eax, &ebx, &ecx, &edx);
-                *(uint32_t *)(signature + 0) = ebx;
-                *(uint32_t *)(signature + 4) = ecx;
-                *(uint32_t *)(signature + 8) = edx;
-                signature[12] = 0;
-
-                if (!strcmp("XenVMMXenVMM", signature) && ((eax - base) >= 2))
-                        return base;
-        }
-
-        return 0;
-}
-
 static int init_hvm_pv_info(int *major, int *minor)
 {
         uint32_t eax, ebx, ecx, edx, pages, msr, base;
@@ -1384,6 +1374,18 @@ static bool __init xen_hvm_platform(void)
         return true;
 }
 
+bool xen_hvm_need_lapic(void)
+{
+        if (xen_pv_domain())
+                return false;
+        if (!xen_hvm_domain())
+                return false;
+        if (xen_feature(XENFEAT_hvm_pirqs) && xen_have_vector_callback)
+                return false;
+        return true;
+}
+EXPORT_SYMBOL_GPL(xen_hvm_need_lapic);
+
 const __refconst struct hypervisor_x86 x86_hyper_xen_hvm = {
         .name                   = "Xen HVM",
         .detect                 = xen_hvm_platform,
diff --git a/arch/x86/xen/multicalls.h b/arch/x86/xen/multicalls.h
index 9e565da5d1f7..4ec8035e3216 100644
--- a/arch/x86/xen/multicalls.h
+++ b/arch/x86/xen/multicalls.h
@@ -22,7 +22,7 @@ static inline void xen_mc_batch(void)
         unsigned long flags;
         /* need to disable interrupts until this entry is complete */
         local_irq_save(flags);
-        __get_cpu_var(xen_mc_irq_flags) = flags;
+        __this_cpu_write(xen_mc_irq_flags, flags);
 }
 
 static inline struct multicall_space xen_mc_entry(size_t args)
diff --git a/arch/x86/xen/spinlock.c b/arch/x86/xen/spinlock.c
index 23e061b9327b..cc9b1e182fcf 100644
--- a/arch/x86/xen/spinlock.c
+++ b/arch/x86/xen/spinlock.c
@@ -159,8 +159,8 @@ static inline struct xen_spinlock *spinning_lock(struct xen_spinlock *xl)
 {
         struct xen_spinlock *prev;
 
-        prev = __get_cpu_var(lock_spinners);
-        __get_cpu_var(lock_spinners) = xl;
+        prev = __this_cpu_read(lock_spinners);
+        __this_cpu_write(lock_spinners, xl);
 
         wmb();                  /* set lock of interest before count */
 
@@ -179,14 +179,14 @@ static inline void unspinning_lock(struct xen_spinlock *xl, struct xen_spinlock
         asm(LOCK_PREFIX " decw %0"
             : "+m" (xl->spinners) : : "memory");
         wmb();                  /* decrement count before restoring lock */
-        __get_cpu_var(lock_spinners) = prev;
+        __this_cpu_write(lock_spinners, prev);
 }
 
 static noinline int xen_spin_lock_slow(struct arch_spinlock *lock, bool irq_enable)
 {
         struct xen_spinlock *xl = (struct xen_spinlock *)lock;
         struct xen_spinlock *prev;
-        int irq = __get_cpu_var(lock_kicker_irq);
+        int irq = __this_cpu_read(lock_kicker_irq);
         int ret;
         u64 start;
 
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 5da5e53fb94c..067759e3d6a5 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -135,24 +135,24 @@ static void do_stolen_accounting(void)
 
         /* Add the appropriate number of ticks of stolen time,
            including any left-overs from last time. */
-        stolen = runnable + offline + __get_cpu_var(xen_residual_stolen);
+        stolen = runnable + offline + __this_cpu_read(xen_residual_stolen);
 
         if (stolen < 0)
                 stolen = 0;
 
         ticks = iter_div_u64_rem(stolen, NS_PER_TICK, &stolen);
-        __get_cpu_var(xen_residual_stolen) = stolen;
+        __this_cpu_write(xen_residual_stolen, stolen);
         account_steal_ticks(ticks);
 
         /* Add the appropriate number of ticks of blocked time,
            including any left-overs from last time. */
-        blocked += __get_cpu_var(xen_residual_blocked);
+        blocked += __this_cpu_read(xen_residual_blocked);
 
         if (blocked < 0)
                 blocked = 0;
 
         ticks = iter_div_u64_rem(blocked, NS_PER_TICK, &blocked);
-        __get_cpu_var(xen_residual_blocked) = blocked;
+        __this_cpu_write(xen_residual_blocked, blocked);
         account_idle_ticks(ticks);
 }
 
diff --git a/arch/xtensa/include/asm/ioctls.h b/arch/xtensa/include/asm/ioctls.h
index ab1800012ed9..ccf1800f0b0c 100644
--- a/arch/xtensa/include/asm/ioctls.h
+++ b/arch/xtensa/include/asm/ioctls.h
@@ -98,6 +98,7 @@
 #define TCSETSF2        _IOW('T', 45, struct termios2)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+#define TIOCGDEV        _IOR('T',0x32, unsigned int) /* Get primary device node of /dev/console */
 #define TIOCSIG         _IOW('T',0x36, int)  /* Generate signal on Pty slave */
 
 #define TIOCSERCONFIG   _IO('T', 83)