ENGR00275213-1 arm: pcie: enable pcie on imx6 platforms

Add PCIe related clocks definitions and select pci on imx6
platforms

toggle bit18 of grp1 fix pcie pm issue:
Set bit18 of gpr1 before enter into supend, and clean it
after resume, can fix the following errata.
Errata ERR005723_PCIe PCIe does not support L2 Power Down.

Signed-off-by: Richard Zhu <r65037@freescale.com>

3 files changed, 45 insertions, 1 deletions

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0633cf9cc01f..c26aac0a203d 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -809,6 +809,8 @@ config SOC_IMX6Q
         select HAVE_IMX_SRC
         select HAVE_SMP
         select MFD_SYSCON
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
         select PINCTRL
         select PINCTRL_IMX6Q
         select PL310_ERRATA_588369 if CACHE_PL310
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index f39e7706c5c5..e9f068c646a1 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -58,6 +58,8 @@ static const char *vpu_axi_sels[]	= { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m",
 static const char *cko1_sels[]  = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
                                     "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
                                     "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_aduio_div", };
+static const char *lvds_sels[]  = { "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
+                                    "dummy", "dummy", "pcie_ref", "sata_ref", "usbphy1", "usbphy2", };
 static const char *cko2_sels[] = {
         "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
         "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
@@ -105,7 +107,7 @@ enum mx6q_clks {
         usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
         spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, gpt_3m, video_27m,
         ldb_di0_div_7, ldb_di1_div_7, ldb_di0_div_sel, ldb_di1_div_sel,
-        pll4_audio_div, clk_max
+        pll4_audio_div, lvds1_sel, lvds1_in, lvds1_out, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -170,6 +172,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
         clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
 
+        /*                              name            reg       shift width parent_names     num_parents */
+        clk[lvds1_sel]    = imx_clk_mux("lvds1_sel",    base + 0x160, 0,  5,  lvds_sels,       ARRAY_SIZE(lvds_sels));
+
         /*
          * Bit 20 is the reserved and read-only bit, we do this only for:
          * - Do nothing for usbphy clk_enable/disable
@@ -188,6 +193,9 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 
         clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
         clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
+        /* NOTICE: The gate of the lvds1 in/out is used to select the clk direction */
+        clk[lvds1_in] = imx_clk_gate("lvds1_in", NULL, base + 0x160, 12);
+        clk[lvds1_out] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10);
 
         clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
         clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
@@ -448,6 +456,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
          */
         clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
 
+        /* Set the parent clks of PCIe lvds1 and pcie_axi to be sata ref, axi */
+        if (clk_set_parent(clk[lvds1_sel], clk[sata_ref]))
+                pr_err("Failed to set PCIe bus parent clk.\n");
+        if (clk_set_parent(clk[pcie_axi_sel], clk[axi]))
+                pr_err("Failed to set PCIe parent clk.\n");
+
         /* gpu clock initilazation */
         clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]);
         clk_set_rate(clk[gpu3d_shader], 594000000);
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 1f75d059a887..acb32940b39b 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -18,6 +18,9 @@
 #include <linux/of_irq.h>
 #include <linux/suspend.h>
 #include <linux/genalloc.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
 #include <asm/cacheflush.h>
 #include <asm/fncpy.h>
 #include <asm/proc-fns.h>
@@ -229,6 +232,22 @@ static int imx6_suspend_finish(unsigned long val)
 
 static int imx6_pm_enter(suspend_state_t state)
 {
+        struct regmap *gpr;
+
+        /*
+         * L2 can exit by 'reset' or Inband beacon (from remote EP)
+         * toggling phy_powerdown has same effect as 'inband beacon'
+         * So, toggle bit18 of GPR1, to fix errata
+         * "PCIe PCIe does not support L2 Power Down"
+         */
+        gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+        if (IS_ERR(gpr)) {
+                pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
+                return PTR_ERR(gpr);
+        }
+        regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD,
+                        IMX6Q_GPR1_PCIE_TEST_PD);
+
         switch (state) {
         case PM_SUSPEND_STANDBY:
                 imx6_set_lpm(STOP_POWER_ON);
@@ -258,6 +277,15 @@ static int imx6_pm_enter(suspend_state_t state)
                 return -EINVAL;
         }
 
+        /*
+         * L2 can exit by 'reset' or Inband beacon (from remote EP)
+         * toggling phy_powerdown has same effect as 'inband beacon'
+         * So, toggle bit18 of GPR1, to fix errata
+         * "PCIe PCIe does not support L2 Power Down"
+         */
+        regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD,
+                        !IMX6Q_GPR1_PCIE_TEST_PD);
+
         return 0;
 }