PCI: exynos: Split into Synopsys part and Exynos part

Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys Designware part;
other parts are Exynos specific.

Also, the Synopsys Designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
Designware part and Exynos specific part.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index b7ffc4dfe219..b035e463492e 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -234,6 +234,7 @@
                 #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0x0 0 &gic 53>;
+                num-lanes = <4>;
         };
 
         pcie@2a0000 {
@@ -253,5 +254,6 @@
                 #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0x0 0 &gic 56>;
+                num-lanes = <4>;
         };
 };