Merge ../linux-2.6

16 files changed, 856 insertions, 134 deletions

diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index 76f4476cab44..d8837911bbc6 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -82,6 +82,12 @@ config LUAN
         help
           This option enables support for the IBM PPC440SP evaluation board.
 
+config YUCCA
+        bool "Yucca"
+        select WANT_EARLY_SERIAL
+        help
+          This option enables support for the AMCC PPC440SPe evaluation board.
+
 config OCOTEA
         bool "Ocotea"
         select WANT_EARLY_SERIAL
@@ -124,9 +130,14 @@ config 440SP
         depends on LUAN
         default y
 
+config 440SPE
+        bool
+        depends on YUCCA
+        default y
+
 config 440
         bool
-        depends on 440GP || 440SP || 440EP
+        depends on 440GP || 440SP || 440SPE || 440EP
         default y
 
 config 440A
@@ -158,7 +169,7 @@ config BOOKE
 
 config IBM_OCP
         bool
-        depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
+        depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
         default y
 
 config XILINX_OCP
@@ -168,7 +179,7 @@ config XILINX_OCP
 
 config IBM_EMAC4
         bool
-        depends on 440GX || 440SP
+        depends on 440GX || 440SP || 440SPE
         default y
 
 config BIOS_FIXUP
@@ -214,7 +225,7 @@ config EMBEDDEDBOOT
 
 config IBM_OPENBIOS
         bool
-        depends on ASH || BUBINGA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
+        depends on ASH || REDWOOD_5 || REDWOOD_6
         default y
 
 config PPC4xx_DMA
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index 1dd6d7fd6a9a..c9bb61170954 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_EBONY)		+= ebony.o
 obj-$(CONFIG_EP405)             += ep405.o
 obj-$(CONFIG_BUBINGA)           += bubinga.o
 obj-$(CONFIG_LUAN)              += luan.o
+obj-$(CONFIG_YUCCA)             += yucca.o
 obj-$(CONFIG_OCOTEA)            += ocotea.o
 obj-$(CONFIG_REDWOOD_5)         += redwood5.o
 obj-$(CONFIG_REDWOOD_6)         += redwood6.o
@@ -22,6 +23,7 @@ obj-$(CONFIG_440EP)		+= ibm440ep.o
 obj-$(CONFIG_440GP)             += ibm440gp.o
 obj-$(CONFIG_440GX)             += ibm440gx.o
 obj-$(CONFIG_440SP)             += ibm440sp.o
+obj-$(CONFIG_440SPE)            += ppc440spe.o
 obj-$(CONFIG_405EP)             += ibm405ep.o
 obj-$(CONFIG_405GPR)            += ibm405gpr.o
 obj-$(CONFIG_VIRTEX_II_PRO)     += virtex-ii_pro.o
diff --git a/arch/ppc/platforms/4xx/bubinga.c b/arch/ppc/platforms/4xx/bubinga.c
index 3678abf86313..8110f55668c5 100644
--- a/arch/ppc/platforms/4xx/bubinga.c
+++ b/arch/ppc/platforms/4xx/bubinga.c
@@ -89,7 +89,7 @@ bubinga_early_serial_map(void)
           * by 16.
           */
         uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
-        uart_clock = __res.bi_pllouta_freq / uart_div;
+        uart_clock = __res.bi_procfreq / uart_div;
 
         /* Setup serial port access */
         memset(&port, 0, sizeof(port));
diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h
index b1df856f8e22..b5380cfaf5c0 100644
--- a/arch/ppc/platforms/4xx/bubinga.h
+++ b/arch/ppc/platforms/4xx/bubinga.h
@@ -1,52 +1,34 @@
 /*
- * Support for IBM PPC 405EP evaluation board (Bubinga).
+ * arch/ppc/platforms/4xx/bubinga.h
  *
- * Author: SAW (IBM), derived from walnut.h.
- *         Maintained by MontaVista Software <source@mvista.com>
+ * Bubinga board definitions
+ *
+ * Copyright (c) 2005 DENX Software Engineering
+ * Stefan Roese <sr@denx.de>
+ *
+ * Based on original work by
+ *      SAW (IBM)
+ *      2003 (c) MontaVista Softare Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  *
- * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
  */
 
 #ifdef __KERNEL__
 #ifndef __BUBINGA_H__
 #define __BUBINGA_H__
 
-/* 405EP */
+#include <linux/config.h>
 #include <platforms/4xx/ibm405ep.h>
-
-#ifndef __ASSEMBLY__
-/*
- * Data structure defining board information maintained by the boot
- * ROM on IBM's evaluation board. An effort has been made to
- * keep the field names consistent with the 8xx 'bd_t' board info
- * structures.
- */
-
-typedef struct board_info {
-        unsigned char    bi_s_version[4];       /* Version of this structure */
-        unsigned char    bi_r_version[30];      /* Version of the IBM ROM */
-        unsigned int     bi_memsize;            /* DRAM installed, in bytes */
-        unsigned char    bi_enetaddr[2][6];     /* Local Ethernet MAC address */        unsigned char    bi_pci_enetaddr[6];    /* PCI Ethernet MAC address */
-        unsigned int     bi_intfreq;            /* Processor speed, in Hz */
-        unsigned int     bi_busfreq;            /* PLB Bus speed, in Hz */
-        unsigned int     bi_pci_busfreq;        /* PCI Bus speed, in Hz */
-        unsigned int     bi_opb_busfreq;        /* OPB Bus speed, in Hz */
-        unsigned int     bi_pllouta_freq;       /* PLL OUTA speed, in Hz */
-} bd_t;
-
-/* Some 4xx parts use a different timebase frequency from the internal clock.
-*/
-#define bi_tbfreq bi_intfreq
-
+#include <asm/ppcboot.h>
 
 /* Memory map for the Bubinga board.
  * Generic 4xx plus RTC.
  */
 
-extern void *bubinga_rtc_base;
 #define BUBINGA_RTC_PADDR       ((uint)0xf0000000)
 #define BUBINGA_RTC_VADDR       BUBINGA_RTC_PADDR
 #define BUBINGA_RTC_SIZE        ((uint)8*1024)
@@ -58,12 +40,18 @@ extern void *bubinga_rtc_base;
  * for typical configurations at various CPU speeds.
  * The base baud is calculated as (FWDA / EXT UART DIV / 16)
  */
-#define BASE_BAUD       0
+#define BASE_BAUD               0
 
-#define BUBINGA_FPGA_BASE      0xF0300000
+/* Flash */
+#define PPC40x_FPGA_BASE        0xF0300000
+#define PPC40x_FPGA_REG_OFFS    1       /* offset to flash map reg */
+#define PPC40x_FLASH_ONBD_N(x)  (x & 0x02)
+#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
+#define PPC40x_FLASH_LOW        0xFFF00000
+#define PPC40x_FLASH_HIGH       0xFFF80000
+#define PPC40x_FLASH_SIZE       0x80000
 
-#define PPC4xx_MACHINE_NAME     "IBM Bubinga"
+#define PPC4xx_MACHINE_NAME     "IBM Bubinga"
 
-#endif /* !__ASSEMBLY__ */
 #endif /* __BUBINGA_H__ */
 #endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
index d08faa46a0ae..b91ad4272dfe 100644
--- a/arch/ppc/platforms/4xx/ebony.h
+++ b/arch/ppc/platforms/4xx/ebony.h
@@ -24,8 +24,8 @@
 #define PPC44x_EMAC0_MR0        0xE0000800
 
 /* Where to find the MAC info */
-#define EBONY_OPENBIOS_MAC_BASE   0xfffffe0c
-#define EBONY_OPENBIOS_MAC_OFFSET 0x0c
+#define OPENBIOS_MAC_BASE       0xfffffe0c
+#define OPENBIOS_MAC_OFFSET     0x0c
 
 /* Default clock rates for Rev. B and Rev. C silicon */
 #define EBONY_440GP_RB_SYSCLK   33000000
diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c
new file mode 100644
index 000000000000..6139a0b3393e
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ppc440spe.c
@@ -0,0 +1,148 @@
+/*
+ * arch/ppc/platforms/4xx/ppc440spe.c
+ *
+ * PPC440SPe I/O descriptions
+ *
+ * Roland Dreier <rolandd@cisco.com>
+ * Copyright (c) 2005 Cisco Systems.  All rights reserved.
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2002-2005 MontaVista Software Inc.
+ *
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003, 2004 Zultys Technologies
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <platforms/4xx/ppc440spe.h>
+#include <asm/ocp.h>
+#include <asm/ppc4xx_pic.h>
+
+static struct ocp_func_emac_data ppc440spe_emac0_def = {
+        .rgmii_idx      = -1,           /* No RGMII */
+        .rgmii_mux      = -1,           /* No RGMII */
+        .zmii_idx       = -1,           /* No ZMII */
+        .zmii_mux       = -1,           /* No ZMII */
+        .mal_idx        = 0,            /* MAL device index */
+        .mal_rx_chan    = 0,            /* MAL rx channel number */
+        .mal_tx_chan    = 0,            /* MAL tx channel number */
+        .wol_irq        = 61,           /* WOL interrupt number */
+        .mdio_idx       = -1,           /* No shared MDIO */
+        .tah_idx        = -1,           /* No TAH */
+};
+OCP_SYSFS_EMAC_DATA()
+
+static struct ocp_func_mal_data ppc440spe_mal0_def = {
+        .num_tx_chans   = 1,            /* Number of TX channels */
+        .num_rx_chans   = 1,            /* Number of RX channels */
+        .txeob_irq      = 38,           /* TX End Of Buffer IRQ  */
+        .rxeob_irq      = 39,           /* RX End Of Buffer IRQ  */
+        .txde_irq       = 34,           /* TX Descriptor Error IRQ */
+        .rxde_irq       = 35,           /* RX Descriptor Error IRQ */
+        .serr_irq       = 33,           /* MAL System Error IRQ    */
+        .dcr_base       = DCRN_MAL_BASE /* MAL0_CFG DCR number */
+};
+OCP_SYSFS_MAL_DATA()
+
+static struct ocp_func_iic_data ppc440spe_iic0_def = {
+        .fast_mode      = 0,            /* Use standad mode (100Khz) */
+};
+
+static struct ocp_func_iic_data ppc440spe_iic1_def = {
+        .fast_mode      = 0,            /* Use standad mode (100Khz) */
+};
+OCP_SYSFS_IIC_DATA()
+
+struct ocp_def core_ocp[] = {
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_16550,
+          .index        = 0,
+          .paddr        = PPC440SPE_UART0_ADDR,
+          .irq          = UART0_INT,
+          .pm           = IBM_CPM_UART0,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_16550,
+          .index        = 1,
+          .paddr        = PPC440SPE_UART1_ADDR,
+          .irq          = UART1_INT,
+          .pm           = IBM_CPM_UART1,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_16550,
+          .index        = 2,
+          .paddr        = PPC440SPE_UART2_ADDR,
+          .irq          = UART2_INT,
+          .pm           = IBM_CPM_UART2,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_IIC,
+          .index        = 0,
+          .paddr        = 0x00000004f0000400ULL,
+          .irq          = 2,
+          .pm           = IBM_CPM_IIC0,
+          .additions    = &ppc440spe_iic0_def,
+          .show         = &ocp_show_iic_data
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_IIC,
+          .index        = 1,
+          .paddr        = 0x00000004f0000500ULL,
+          .irq          = 3,
+          .pm           = IBM_CPM_IIC1,
+          .additions    = &ppc440spe_iic1_def,
+          .show         = &ocp_show_iic_data
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_GPIO,
+          .index        = 0,
+          .paddr        = 0x00000004f0000700ULL,
+          .irq          = OCP_IRQ_NA,
+          .pm           = IBM_CPM_GPIO0,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_MAL,
+          .paddr        = OCP_PADDR_NA,
+          .irq          = OCP_IRQ_NA,
+          .pm           = OCP_CPM_NA,
+          .additions    = &ppc440spe_mal0_def,
+          .show         = &ocp_show_mal_data,
+        },
+        { .vendor       = OCP_VENDOR_IBM,
+          .function     = OCP_FUNC_EMAC,
+          .index        = 0,
+          .paddr        = 0x00000004f0000800ULL,
+          .irq          = 60,
+          .pm           = OCP_CPM_NA,
+          .additions    = &ppc440spe_emac0_def,
+          .show         = &ocp_show_emac_data,
+        },
+        { .vendor       = OCP_VENDOR_INVALID
+        }
+};
+
+/* Polarity and triggering settings for internal interrupt sources */
+struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
+        { .polarity     = 0xffffffff,
+          .triggering   = 0x010f0004,
+          .ext_irq_mask = 0x00000000,
+        },
+        { .polarity     = 0xffffffff,
+          .triggering   = 0x001f8040,
+          .ext_irq_mask = 0x00007c30,   /* IRQ6 - IRQ7, IRQ8 - IRQ12 */
+        },
+        { .polarity     = 0xffffffff,
+          .triggering   = 0x00000000,
+          .ext_irq_mask = 0x000000fc,   /* IRQ0 - IRQ5 */
+        },
+        { .polarity     = 0xffffffff,
+          .triggering   = 0x00000000,
+          .ext_irq_mask = 0x00000000,
+        },
+};
diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h
new file mode 100644
index 000000000000..2216846973b8
--- /dev/null
+++ b/arch/ppc/platforms/4xx/ppc440spe.h
@@ -0,0 +1,66 @@
+/*
+ * arch/ppc/platforms/4xx/ibm440spe.h
+ *
+ * PPC440SPe definitions
+ *
+ * Roland Dreier <rolandd@cisco.com>
+ * Copyright (c) 2005 Cisco Systems.  All rights reserved.
+ *
+ * Matt Porter <mporter@kernel.crashing.org>
+ * Copyright 2004-2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __PPC_PLATFORMS_PPC440SPE_H
+#define __PPC_PLATFORMS_PPC440SPE_H
+
+#include <linux/config.h>
+
+#include <asm/ibm44x.h>
+
+/* UART */
+#define PPC440SPE_UART0_ADDR    0x00000004f0000200ULL
+#define PPC440SPE_UART1_ADDR    0x00000004f0000300ULL
+#define PPC440SPE_UART2_ADDR    0x00000004f0000600ULL
+#define UART0_INT               0
+#define UART1_INT               1
+#define UART2_INT               37
+
+/* Clock and Power Management */
+#define IBM_CPM_IIC0            0x80000000      /* IIC interface */
+#define IBM_CPM_IIC1            0x40000000      /* IIC interface */
+#define IBM_CPM_PCI             0x20000000      /* PCI bridge */
+#define IBM_CPM_CPU                 0x02000000  /* processor core */
+#define IBM_CPM_DMA                 0x01000000  /* DMA controller */
+#define IBM_CPM_BGO                 0x00800000  /* PLB to OPB bus arbiter */
+#define IBM_CPM_BGI                 0x00400000  /* OPB to PLB bridge */
+#define IBM_CPM_EBC                 0x00200000  /* External Bux Controller */
+#define IBM_CPM_EBM                 0x00100000  /* Ext Bus Master Interface */
+#define IBM_CPM_DMC                 0x00080000  /* SDRAM peripheral controller */
+#define IBM_CPM_PLB                 0x00040000  /* PLB bus arbiter */
+#define IBM_CPM_SRAM            0x00020000      /* SRAM memory controller */
+#define IBM_CPM_PPM                 0x00002000  /* PLB Performance Monitor */
+#define IBM_CPM_UIC1            0x00001000      /* Universal Interrupt Controller */
+#define IBM_CPM_GPIO0           0x00000800      /* General Purpose IO (??) */
+#define IBM_CPM_GPT                 0x00000400  /* General Purpose Timers  */
+#define IBM_CPM_UART0           0x00000200      /* serial port 0 */
+#define IBM_CPM_UART1           0x00000100      /* serial port 1 */
+#define IBM_CPM_UART2           0x00000100      /* serial port 1 */
+#define IBM_CPM_UIC0            0x00000080      /* Universal Interrupt Controller */
+#define IBM_CPM_TMRCLK          0x00000040      /* CPU timers */
+#define IBM_CPM_EMAC0           0x00000020      /* EMAC 0     */
+
+#define DFLT_IBM4xx_PM          ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
+                                | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
+                                | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
+                                | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
+                                | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
+                                | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
+                                | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
+#endif /* __PPC_PLATFORMS_PPC440SP_H */
+#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c
index d8019eec4704..281b4a2ffb96 100644
--- a/arch/ppc/platforms/4xx/sycamore.c
+++ b/arch/ppc/platforms/4xx/sycamore.c
@@ -88,9 +88,6 @@ ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 void __init
 sycamore_setup_arch(void)
 {
-#define SYCAMORE_PS2_BASE       0xF0100000
-#define SYCAMORE_FPGA_BASE      0xF0300000
-
         void *fpga_brdc;
         unsigned char fpga_brdc_data;
         void *fpga_enable;
@@ -100,7 +97,7 @@ sycamore_setup_arch(void)
 
         ppc4xx_setup_arch();
 
-        ibm_ocp_set_emac(0, 1);
+        ibm_ocp_set_emac(0, 0);
 
         kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
         if (!kb_data) {
@@ -111,7 +108,7 @@ sycamore_setup_arch(void)
 
         kb_cs = kb_data + 1;
 
-        fpga_status = ioremap(SYCAMORE_FPGA_BASE, 8);
+        fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
         if (!fpga_status) {
                 printk(KERN_CRIT
                        "sycamore_setup_arch() fpga_status ioremap failed\n");
diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h
index 3e7b4e2c8c57..1cd6c824fd62 100644
--- a/arch/ppc/platforms/4xx/sycamore.h
+++ b/arch/ppc/platforms/4xx/sycamore.h
@@ -1,67 +1,52 @@
 /*
  * arch/ppc/platforms/4xx/sycamore.h
  *
- * Macros, definitions, and data structures specific to the IBM PowerPC
- * 405GPr "Sycamore" evaluation board.
+ * Sycamore board definitions
  *
- * Author: Armin Kuster <akuster@mvista.com>
+ * Copyright (c) 2005 DENX Software Engineering
+ * Stefan Roese <sr@denx.de>
+ *
+ * Based on original work by
+ *      Armin Kuster <akuster@mvista.com>
+ *      2000 (c) MontaVista, Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  *
- * 2000 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
  */
 
 #ifdef __KERNEL__
 #ifndef __ASM_SYCAMORE_H__
 #define __ASM_SYCAMORE_H__
 
+#include <linux/config.h>
 #include <platforms/4xx/ibm405gpr.h>
+#include <asm/ppcboot.h>
 
-#ifndef __ASSEMBLY__
-/*
- * Data structure defining board information maintained by the boot
- * ROM on IBM's "Sycamore" evaluation board. An effort has been made to
- * keep the field names consistent with the 8xx 'bd_t' board info
- * structures.
- */
-
-typedef struct board_info {
-        unsigned char    bi_s_version[4];       /* Version of this structure */
-        unsigned char    bi_r_version[30];      /* Version of the IBM ROM */
-        unsigned int     bi_memsize;            /* DRAM installed, in bytes */
-        unsigned char    bi_enetaddr[6];        /* Local Ethernet MAC address */
-        unsigned char    bi_pci_enetaddr[6];    /* PCI Ethernet MAC address */
-        unsigned int     bi_intfreq;            /* Processor speed, in Hz */
-        unsigned int     bi_busfreq;            /* PLB Bus speed, in Hz */
-        unsigned int     bi_pci_busfreq;        /* PCI Bus speed, in Hz */
-} bd_t;
-
-/* Some 4xx parts use a different timebase frequency from the internal clock.
-*/
-#define bi_tbfreq bi_intfreq
-
-
-/* Memory map for the IBM "Sycamore" 405GP evaluation board.
+/* Memory map for the IBM "Sycamore" 405GPr evaluation board.
  * Generic 4xx plus RTC.
  */
 
-extern void *sycamore_rtc_base;
 #define SYCAMORE_RTC_PADDR      ((uint)0xf0000000)
 #define SYCAMORE_RTC_VADDR      SYCAMORE_RTC_PADDR
-#define SYCAMORE_RTC_SIZE               ((uint)8*1024)
+#define SYCAMORE_RTC_SIZE       ((uint)8*1024)
 
-#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
-#define BASE_BAUD               201600
-#else
 #define BASE_BAUD               691200
-#endif
 
-#define SYCAMORE_PS2_BASE               0xF0100000
-#define SYCAMORE_FPGA_BASE      0xF0300000
+#define SYCAMORE_PS2_BASE       0xF0100000
+
+/* Flash */
+#define PPC40x_FPGA_BASE        0xF0300000
+#define PPC40x_FPGA_REG_OFFS    5       /* offset to flash map reg */
+#define PPC40x_FLASH_ONBD_N(x)  (x & 0x02)
+#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
+#define PPC40x_FLASH_LOW        0xFFF00000
+#define PPC40x_FLASH_HIGH       0xFFF80000
+#define PPC40x_FLASH_SIZE       0x80000
 
 #define PPC4xx_MACHINE_NAME     "IBM Sycamore"
 
-#endif /* !__ASSEMBLY__ */
 #endif /* __ASM_SYCAMORE_H__ */
 #endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c
index a33eda4b7489..74cb33182d9f 100644
--- a/arch/ppc/platforms/4xx/walnut.c
+++ b/arch/ppc/platforms/4xx/walnut.c
@@ -90,7 +90,7 @@ walnut_setup_arch(void)
 
         kb_cs = kb_data + 1;
 
-        fpga_status = ioremap(WALNUT_FPGA_BASE, 8);
+        fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
         if (!fpga_status) {
                 printk(KERN_CRIT
                        "walnut_setup_arch() fpga_status ioremap failed\n");
diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h
index 04cfbf3696b9..dcf2691698c0 100644
--- a/arch/ppc/platforms/4xx/walnut.h
+++ b/arch/ppc/platforms/4xx/walnut.h
@@ -1,72 +1,55 @@
 /*
  * arch/ppc/platforms/4xx/walnut.h
  *
- * Macros, definitions, and data structures specific to the IBM PowerPC
- * 405GP "Walnut" evaluation board.
+ * Walnut board definitions
  *
- * Authors: Grant Erickson <grant@lcse.umn.edu>, Frank Rowand
- * <frank_rowand@mvista.com>, Debbie Chu <debbie_chu@mvista.com> or
- * source@mvista.com
+ * Copyright (c) 2005 DENX Software Engineering
+ * Stefan Roese <sr@denx.de>
  *
- * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
+ * Based on original work by
+ *      Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
+ *      Frank Rowand <frank_rowand@mvista.com>
+ *      Debbie Chu <debbie_chu@mvista.com>
+ *      2000 (c) MontaVista, Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  *
- * 2000 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
  */
 
 #ifdef __KERNEL__
 #ifndef __ASM_WALNUT_H__
 #define __ASM_WALNUT_H__
 
-/* We have a 405GP core */
+#include <linux/config.h>
 #include <platforms/4xx/ibm405gp.h>
-
-#ifndef __ASSEMBLY__
-/*
- * Data structure defining board information maintained by the boot
- * ROM on IBM's "Walnut" evaluation board. An effort has been made to
- * keep the field names consistent with the 8xx 'bd_t' board info
- * structures.
- */
-
-typedef struct board_info {
-        unsigned char    bi_s_version[4];       /* Version of this structure */
-        unsigned char    bi_r_version[30];      /* Version of the IBM ROM */
-        unsigned int     bi_memsize;            /* DRAM installed, in bytes */
-        unsigned char    bi_enetaddr[6];        /* Local Ethernet MAC address */
-        unsigned char    bi_pci_enetaddr[6];    /* PCI Ethernet MAC address */
-        unsigned int     bi_intfreq;            /* Processor speed, in Hz */
-        unsigned int     bi_busfreq;            /* PLB Bus speed, in Hz */
-        unsigned int     bi_pci_busfreq;        /* PCI Bus speed, in Hz */
-} bd_t;
-
-/* Some 4xx parts use a different timebase frequency from the internal clock.
-*/
-#define bi_tbfreq bi_intfreq
-
+#include <asm/ppcboot.h>
 
 /* Memory map for the IBM "Walnut" 405GP evaluation board.
  * Generic 4xx plus RTC.
  */
 
-extern void *walnut_rtc_base;
 #define WALNUT_RTC_PADDR        ((uint)0xf0000000)
 #define WALNUT_RTC_VADDR        WALNUT_RTC_PADDR
 #define WALNUT_RTC_SIZE         ((uint)8*1024)
 
-#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK
-#define BASE_BAUD               201600
-#else
 #define BASE_BAUD               691200
-#endif
 
 #define WALNUT_PS2_BASE         0xF0100000
-#define WALNUT_FPGA_BASE        0xF0300000
+
+/* Flash */
+#define PPC40x_FPGA_BASE        0xF0300000
+#define PPC40x_FPGA_REG_OFFS    5       /* offset to flash map reg */
+#define PPC40x_FLASH_ONBD_N(x)  (x & 0x02)
+#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
+#define PPC40x_FLASH_LOW        0xFFF00000
+#define PPC40x_FLASH_HIGH       0xFFF80000
+#define PPC40x_FLASH_SIZE       0x80000
+#define WALNUT_FPGA_BASE        PPC40x_FPGA_BASE
 
 #define PPC4xx_MACHINE_NAME     "IBM Walnut"
 
-#endif /* !__ASSEMBLY__ */
 #endif /* __ASM_WALNUT_H__ */
 #endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c
new file mode 100644
index 000000000000..e60f4bd437ec
--- /dev/null
+++ b/arch/ppc/platforms/4xx/yucca.c
@@ -0,0 +1,395 @@
+/*
+ * arch/ppc/platforms/4xx/yucca.c
+ *
+ * Yucca board specific routines
+ *
+ * Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter)
+ *
+ * Copyright 2004-2005 MontaVista Software Inc.
+ * Copyright (c) 2005 Cisco Systems.  All rights reserved.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/types.h>
+#include <linux/major.h>
+#include <linux/blkdev.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/ide.h>
+#include <linux/initrd.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ocp.h>
+#include <asm/pci-bridge.h>
+#include <asm/time.h>
+#include <asm/todc.h>
+#include <asm/bootinfo.h>
+#include <asm/ppc4xx_pic.h>
+#include <asm/ppcboot.h>
+
+#include <syslib/ibm44x_common.h>
+#include <syslib/ibm440gx_common.h>
+#include <syslib/ibm440sp_common.h>
+#include <syslib/ppc440spe_pcie.h>
+
+extern bd_t __res;
+
+static struct ibm44x_clocks clocks __initdata;
+
+static void __init
+yucca_calibrate_decr(void)
+{
+        unsigned int freq;
+
+        if (mfspr(SPRN_CCR1) & CCR1_TCS)
+                freq = YUCCA_TMR_CLK;
+        else
+                freq = clocks.cpu;
+
+        ibm44x_calibrate_decr(freq);
+}
+
+static int
+yucca_show_cpuinfo(struct seq_file *m)
+{
+        seq_printf(m, "vendor\t\t: AMCC\n");
+        seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n");
+
+        return 0;
+}
+
+static enum {
+        HOSE_UNKNOWN,
+        HOSE_PCIX,
+        HOSE_PCIE0,
+        HOSE_PCIE1,
+        HOSE_PCIE2
+} hose_type[4];
+
+static inline int
+yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+        struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
+
+        if (hose_type[hose->index] == HOSE_PCIX) {
+                static char pci_irq_table[][4] =
+                /*
+                 *      PCI IDSEL/INTPIN->INTLINE
+                 *        A   B   C   D
+                 */
+                {
+                        { 81, -1, -1, -1 },     /* IDSEL 1 - PCIX0 Slot 0 */
+                };
+                const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
+                return PCI_IRQ_TABLE_LOOKUP;
+        } else if (hose_type[hose->index] == HOSE_PCIE0) {
+                static char pci_irq_table[][4] =
+                /*
+                 *      PCI IDSEL/INTPIN->INTLINE
+                 *        A   B   C   D
+                 */
+                {
+                        { 96, 97, 98, 99 },
+                };
+                const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
+                return PCI_IRQ_TABLE_LOOKUP;
+        } else if (hose_type[hose->index] == HOSE_PCIE1) {
+                static char pci_irq_table[][4] =
+                /*
+                 *      PCI IDSEL/INTPIN->INTLINE
+                 *        A   B   C   D
+                 */
+                {
+                        { 100, 101, 102, 103 },
+                };
+                const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
+                return PCI_IRQ_TABLE_LOOKUP;
+        } else if (hose_type[hose->index] == HOSE_PCIE2) {
+                static char pci_irq_table[][4] =
+                /*
+                 *      PCI IDSEL/INTPIN->INTLINE
+                 *        A   B   C   D
+                 */
+                {
+                        { 104, 105, 106, 107 },
+                };
+                const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
+                return PCI_IRQ_TABLE_LOOKUP;
+        }
+        return -1;
+}
+
+static void __init yucca_set_emacdata(void)
+{
+        struct ocp_def *def;
+        struct ocp_func_emac_data *emacdata;
+
+        /* Set phy_map, phy_mode, and mac_addr for the EMAC */
+        def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
+        emacdata = def->additions;
+        emacdata->phy_map = 0x00000001; /* Skip 0x00 */
+        emacdata->phy_mode = PHY_MODE_GMII;
+        memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
+}
+
+static int __init yucca_pcie_card_present(int port)
+{
+   void __iomem *pcie_fpga_base;
+   u16 reg;
+
+   pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
+   reg = in_be16(pcie_fpga_base + FPGA_REG1C);
+   iounmap(pcie_fpga_base);
+
+   switch(port) {
+   case 0: return !(reg & FPGA_REG1C_PE0_PRSNT);
+   case 1: return !(reg & FPGA_REG1C_PE1_PRSNT);
+   case 2: return !(reg & FPGA_REG1C_PE2_PRSNT);
+   default: return 0;
+   }
+}
+
+/*
+ * For the given slot, set rootpoint mode, send power to the slot,
+ * turn on the green LED and turn off the yellow LED, enable the clock
+ * and turn off reset.
+ */
+static void __init yucca_setup_pcie_fpga_rootpoint(int port)
+{
+        void __iomem *pcie_reg_fpga_base;
+        u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
+
+        pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
+
+        switch(port) {
+        case 0:
+                rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
+                endpoint    = 0;
+                power       = FPGA_REG1A_PE0_PWRON;
+                green_led   = FPGA_REG1A_PE0_GLED;
+                clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
+                yellow_led  = FPGA_REG1A_PE0_YLED;
+                reset_off   = FPGA_REG1C_PE0_PERST;
+                break;
+        case 1:
+                rootpoint   = 0;
+                endpoint    = FPGA_REG1C_PE1_ENDPOINT;
+                power       = FPGA_REG1A_PE1_PWRON;
+                green_led   = FPGA_REG1A_PE1_GLED;
+                clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
+                yellow_led  = FPGA_REG1A_PE1_YLED;
+                reset_off   = FPGA_REG1C_PE1_PERST;
+                break;
+        case 2:
+                rootpoint   = 0;
+                endpoint    = FPGA_REG1C_PE2_ENDPOINT;
+                power       = FPGA_REG1A_PE2_PWRON;
+                green_led   = FPGA_REG1A_PE2_GLED;
+                clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
+                yellow_led  = FPGA_REG1A_PE2_YLED;
+                reset_off   = FPGA_REG1C_PE2_PERST;
+                break;
+
+        default:
+                return;
+        }
+
+        out_be16(pcie_reg_fpga_base + FPGA_REG1A,
+                 ~(power | clock | green_led) &
+                 (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A)));
+        out_be16(pcie_reg_fpga_base + FPGA_REG1C,
+                 ~(endpoint | reset_off) &
+                 (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C)));
+
+        /*
+         * Leave device in reset for a while after powering on the
+         * slot to give it a chance to initialize.
+         */
+        mdelay(250);
+
+        out_be16(pcie_reg_fpga_base + FPGA_REG1C,
+                 reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C));
+
+        iounmap(pcie_reg_fpga_base);
+}
+
+static void __init
+yucca_setup_hoses(void)
+{
+        struct pci_controller *hose;
+        char name[20];
+        int i;
+
+        if (0 && ppc440spe_init_pcie()) {
+                printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
+                return;
+        }
+
+        for (i = 0; i <= 2; ++i) {
+                if (!yucca_pcie_card_present(i))
+                        continue;
+
+                printk(KERN_INFO "PCIE%d: card present\n", i);
+                yucca_setup_pcie_fpga_rootpoint(i);
+                if (ppc440spe_init_pcie_rootport(i)) {
+                        printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
+                        continue;
+                }
+
+                hose = pcibios_alloc_controller();
+                if (!hose)
+                        return;
+
+                sprintf(name, "PCIE%d host bridge", i);
+                pci_init_resource(&hose->io_resource,
+                                  YUCCA_PCIX_LOWER_IO,
+                                  YUCCA_PCIX_UPPER_IO,
+                                  IORESOURCE_IO,
+                                  name);
+
+                hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
+                        i * YUCCA_PCIE_MEM_SIZE;
+                hose->mem_space.end   = hose->mem_space.start +
+                        YUCCA_PCIE_MEM_SIZE - 1;
+
+                pci_init_resource(&hose->mem_resources[0],
+                                  hose->mem_space.start,
+                                  hose->mem_space.end,
+                                  IORESOURCE_MEM,
+                                  name);
+
+                hose->first_busno = 0;
+                hose->last_busno  = 15;
+                hose_type[hose->index] = HOSE_PCIE0 + i;
+
+                ppc440spe_setup_pcie(hose, i);
+                hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+        }
+
+        ppc_md.pci_swizzle = common_swizzle;
+        ppc_md.pci_map_irq = yucca_map_irq;
+}
+
+TODC_ALLOC();
+
+static void __init
+yucca_early_serial_map(void)
+{
+        struct uart_port port;
+
+        /* Setup ioremapped serial port access */
+        memset(&port, 0, sizeof(port));
+        port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8);
+        port.irq = UART0_INT;
+        port.uartclk = clocks.uart0;
+        port.regshift = 0;
+        port.iotype = SERIAL_IO_MEM;
+        port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+        port.line = 0;
+
+        if (early_serial_setup(&port) != 0) {
+                printk("Early serial init of port 0 failed\n");
+        }
+
+        port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8);
+        port.irq = UART1_INT;
+        port.uartclk = clocks.uart1;
+        port.line = 1;
+
+        if (early_serial_setup(&port) != 0) {
+                printk("Early serial init of port 1 failed\n");
+        }
+
+        port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8);
+        port.irq = UART2_INT;
+        port.uartclk = BASE_BAUD;
+        port.line = 2;
+
+        if (early_serial_setup(&port) != 0) {
+                printk("Early serial init of port 2 failed\n");
+        }
+}
+
+static void __init
+yucca_setup_arch(void)
+{
+        yucca_set_emacdata();
+
+#if !defined(CONFIG_BDI_SWITCH)
+        /*
+         * The Abatron BDI JTAG debugger does not tolerate others
+         * mucking with the debug registers.
+         */
+        mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
+#endif
+
+        /*
+         * Determine various clocks.
+         * To be completely correct we should get SysClk
+         * from FPGA, because it can be changed by on-board switches
+         * --ebs
+         */
+        /* 440GX and 440SPe clocking is the same - rd */
+        ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
+        ocp_sys_info.opb_bus_freq = clocks.opb;
+
+        /* init to some ~sane value until calibrate_delay() runs */
+        loops_per_jiffy = 50000000/HZ;
+
+        /* Setup PCIXn host bridges */
+        yucca_setup_hoses();
+
+#ifdef CONFIG_BLK_DEV_INITRD
+        if (initrd_start)
+                ROOT_DEV = Root_RAM0;
+        else
+#endif
+#ifdef CONFIG_ROOT_NFS
+                ROOT_DEV = Root_NFS;
+#else
+                ROOT_DEV = Root_HDA1;
+#endif
+
+        yucca_early_serial_map();
+
+        /* Identify the system */
+        printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n");
+}
+
+void __init platform_init(unsigned long r3, unsigned long r4,
+                unsigned long r5, unsigned long r6, unsigned long r7)
+{
+        ibm44x_platform_init(r3, r4, r5, r6, r7);
+
+        ppc_md.setup_arch = yucca_setup_arch;
+        ppc_md.show_cpuinfo = yucca_show_cpuinfo;
+        ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
+        ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
+
+        ppc_md.calibrate_decr = yucca_calibrate_decr;
+#ifdef CONFIG_KGDB
+        ppc_md.early_serial_map = yucca_early_serial_map;
+#endif
+}
diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h
new file mode 100644
index 000000000000..01a4afea1514
--- /dev/null
+++ b/arch/ppc/platforms/4xx/yucca.h
@@ -0,0 +1,111 @@
+/*
+ * arch/ppc/platforms/4xx/yucca.h
+ *
+ * Yucca board definitions
+ *
+ * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter)
+ *
+ * Copyright 2004-2005 MontaVista Software Inc.
+ * Copyright (c) 2005 Cisco Systems.  All rights reserved.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_YUCCA_H__
+#define __ASM_YUCCA_H__
+
+#include <linux/config.h>
+#include <platforms/4xx/ppc440spe.h>
+
+/* F/W TLB mapping used in bootloader glue to reset EMAC */
+#define PPC44x_EMAC0_MR0        0xa0000800
+
+/* Location of MAC addresses in PIBS image */
+#define PIBS_FLASH_BASE         0xffe00000
+#define PIBS_MAC_BASE           (PIBS_FLASH_BASE+0x1b0400)
+
+/* External timer clock frequency */
+#define YUCCA_TMR_CLK           25000000
+
+/*
+ * FPGA registers
+ */
+#define YUCCA_FPGA_REG_BASE                     0x00000004e2000000ULL
+#define YUCCA_FPGA_REG_SIZE                     0x24
+
+#define FPGA_REG1A                              0x1a
+
+#define FPGA_REG1A_PE0_GLED                     0x8000
+#define FPGA_REG1A_PE1_GLED                     0x4000
+#define FPGA_REG1A_PE2_GLED                     0x2000
+#define FPGA_REG1A_PE0_YLED                     0x1000
+#define FPGA_REG1A_PE1_YLED                     0x0800
+#define FPGA_REG1A_PE2_YLED                     0x0400
+#define FPGA_REG1A_PE0_PWRON                    0x0200
+#define FPGA_REG1A_PE1_PWRON                    0x0100
+#define FPGA_REG1A_PE2_PWRON                    0x0080
+#define FPGA_REG1A_PE0_REFCLK_ENABLE            0x0040
+#define FPGA_REG1A_PE1_REFCLK_ENABLE            0x0020
+#define FPGA_REG1A_PE2_REFCLK_ENABLE            0x0010
+#define FPGA_REG1A_PE_SPREAD0                   0x0008
+#define FPGA_REG1A_PE_SPREAD1                   0x0004
+#define FPGA_REG1A_PE_SELSOURCE_0               0x0002
+#define FPGA_REG1A_PE_SELSOURCE_1               0x0001
+
+#define FPGA_REG1C                              0x1c
+
+#define FPGA_REG1C_PE0_ROOTPOINT                0x8000
+#define FPGA_REG1C_PE1_ENDPOINT                 0x4000
+#define FPGA_REG1C_PE2_ENDPOINT                 0x2000
+#define FPGA_REG1C_PE0_PRSNT                    0x1000
+#define FPGA_REG1C_PE1_PRSNT                    0x0800
+#define FPGA_REG1C_PE2_PRSNT                    0x0400
+#define FPGA_REG1C_PE0_WAKE                     0x0080
+#define FPGA_REG1C_PE1_WAKE                     0x0040
+#define FPGA_REG1C_PE2_WAKE                     0x0020
+#define FPGA_REG1C_PE0_PERST                    0x0010
+#define FPGA_REG1C_PE1_PERST                    0x0008
+#define FPGA_REG1C_PE2_PERST                    0x0004
+
+/*
+ * Serial port defines
+ */
+#define RS_TABLE_SIZE   3
+
+/* PIBS defined UART mappings, used before early_serial_setup */
+#define UART0_IO_BASE   0xa0000200
+#define UART1_IO_BASE   0xa0000300
+#define UART2_IO_BASE   0xa0000600
+
+#define BASE_BAUD       11059200
+#define STD_UART_OP(num)                                        \
+        { 0, BASE_BAUD, 0, UART##num##_INT,                     \
+                (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),        \
+                iomem_base: (void*)UART##num##_IO_BASE,         \
+                io_type: SERIAL_IO_MEM},
+
+#define SERIAL_PORT_DFNS        \
+        STD_UART_OP(0)          \
+        STD_UART_OP(1)          \
+        STD_UART_OP(2)
+
+/* PCI support */
+#define YUCCA_PCIX_LOWER_IO     0x00000000
+#define YUCCA_PCIX_UPPER_IO     0x0000ffff
+#define YUCCA_PCIX_LOWER_MEM    0x80000000
+#define YUCCA_PCIX_UPPER_MEM    0x8fffffff
+#define YUCCA_PCIE_LOWER_MEM    0x90000000
+#define YUCCA_PCIE_MEM_SIZE     0x10000000
+
+#define YUCCA_PCIX_MEM_SIZE     0x10000000
+#define YUCCA_PCIX_MEM_OFFSET   0x00000000
+#define YUCCA_PCIE_MEM_SIZE     0x10000000
+#define YUCCA_PCIE_MEM_OFFSET   0x00000000
+
+#endif                          /* __ASM_YUCCA_H__ */
+#endif                          /* __KERNEL__ */
diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
index bd3ac0136756..16ad092d8a06 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
@@ -45,6 +45,8 @@
 
 #include <mm/mmu_decl.h>
 
+#include <syslib/ppc85xx_rio.h>
+
 #include <platforms/85xx/mpc85xx_ads_common.h>
 
 #ifndef CONFIG_PCI
@@ -189,3 +191,11 @@ mpc85xx_exclude_device(u_char bus, u_char devfn)
 }
 
 #endif /* CONFIG_PCI */
+
+#ifdef CONFIG_RAPIDIO
+void platform_rio_init(void)
+{
+        /* 512MB RIO LAW at 0xc0000000 */
+        mpc85xx_rio_setup(0xc0000000, 0x20000000);
+}
+#endif /* CONFIG_RAPIDIO */
diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
index 1e1b85f8193a..15ce9d070634 100644
--- a/arch/ppc/platforms/85xx/stx_gp3.c
+++ b/arch/ppc/platforms/85xx/stx_gp3.c
@@ -37,6 +37,7 @@
 #include <linux/module.h>
 #include <linux/fsl_devices.h>
 #include <linux/interrupt.h>
+#include <linux/rio.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -57,6 +58,7 @@
 
 #include <syslib/cpm2_pic.h>
 #include <syslib/ppc85xx_common.h>
+#include <syslib/ppc85xx_rio.h>
 
 
 unsigned char __res[sizeof(bd_t)];
@@ -273,6 +275,18 @@ int mpc85xx_exclude_device(u_char bus, u_char devfn)
 }
 #endif /* CONFIG_PCI */
 
+#ifdef CONFIG_RAPIDIO
+void
+platform_rio_init(void)
+{
+        /*
+         * The STx firmware configures the RapidIO Local Access Window
+         * at 0xc0000000 with a size of 512MB.
+         */
+        mpc85xx_rio_setup(0xc0000000, 0x20000000);
+}
+#endif /* CONFIG_RAPIDIO */
+
 void __init
 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
               unsigned long r6, unsigned long r7)
diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c
index b1324564456e..b9d844f88c2b 100644
--- a/arch/ppc/platforms/ev64360.c
+++ b/arch/ppc/platforms/ev64360.c
@@ -52,6 +52,8 @@ static u32		ev64360_bus_frequency;
 
 unsigned char   __res[sizeof(bd_t)];
 
+TODC_ALLOC();
+
 static int __init
 ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
@@ -182,6 +184,9 @@ ev64360_setup_peripherals(void)
                  EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 
+        TODC_INIT(TODC_TYPE_DS1501, 0, 0,
+                ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8);
+
         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
                  EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
@@ -496,6 +501,13 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
         ppc_md.power_off = ev64360_power_off;
         ppc_md.halt = ev64360_halt;
         ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
+        ppc_md.init = NULL;
+
+        ppc_md.time_init = todc_time_init;
+        ppc_md.set_rtc_time = todc_set_rtc_time;
+        ppc_md.get_rtc_time = todc_get_rtc_time;
+        ppc_md.nvram_read_val = todc_direct_read_val;
+        ppc_md.nvram_write_val = todc_direct_write_val;
         ppc_md.calibrate_decr = ev64360_calibrate_decr;
 
 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)