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authorHuang Shijie <b32955@freescale.com>2014-03-17 03:01:11 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:58:12 -0400
commit4cc306e55c1077e119aa025737b9747fa4ce3dc8 (patch)
treeff63feaf47a7ff7ccd74aa257b23e0f9658360a9 /arch/arm/boot
parentc9121897d7588a0dcdca56f9aa6771274862f51d (diff)
ENGR00303701-2 ARM: dts: imx6sx-19x19-arm2: enable the WEIM
enable the 32MB parallel NOR flash. Signed-off-by: Huang Shijie <b32955@freescale.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/imx6sx-19x19-arm2.dts19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
index f0cbe3c6ffbe..505bcbfbc07c 100644
--- a/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
+++ b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
@@ -478,3 +478,22 @@
478 no-1-8-v; 478 no-1-8-v;
479 status = "okay"; 479 status = "okay";
480}; 480};
481
482&weim {
483 pinctrl-names = "default";
484 pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
485 #address-cells = <2>;
486 #size-cells = <1>;
487 ranges = <0 0 0x50000000 0x08000000>;
488 status = "disabled"; /* pin conflict with qspi, nand and lcd1 */
489
490 nor@0,0 {
491 compatible = "cfi-flash";
492 reg = <0 0 0x02000000>;
493 #address-cells = <1>;
494 #size-cells = <1>;
495 bank-width = <2>;
496 fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000
497 0x0000c000 0x1404a38e 0x00000000>;
498 };
499};