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authorHuang Shijie <b32955@freescale.com>2014-03-17 01:36:23 -0400
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:58:12 -0400
commitc9121897d7588a0dcdca56f9aa6771274862f51d (patch)
tree1396afad69b858dbc3714112b8064f71745d7529 /arch/arm/boot
parent252b52411bc919f3fc13d3fb8dd267f57ae7feaf (diff)
ENGR00303701-1 ARM: dts: imx6sx: add WEIM support
Add the WEIM node and the pinctrl. Signed-off-by: Huang Shijie <b32955@freescale.com>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi67
1 files changed, 67 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 218c289a2f55..d218bf756951 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -759,6 +759,13 @@
759 status = "disabled"; 759 status = "disabled";
760 }; 760 };
761 761
762 weim: weim@021b8000 {
763 compatible = "fsl,imx6q-weim";
764 reg = <0x021b8000 0x4000>;
765 interrupts = <0 14 0x04>;
766 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
767 };
768
762 i2c1: i2c@021a0000 { 769 i2c1: i2c@021a0000 {
763 #address-cells = <1>; 770 #address-cells = <1>;
764 #size-cells = <0>; 771 #size-cells = <0>;
@@ -1637,4 +1644,64 @@
1637 }; 1644 };
1638 1645
1639 }; 1646 };
1647
1648 weim {
1649 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1650 fsl,pins = <
1651 MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1
1652 >;
1653 };
1654
1655 pinctrl_weim_nor_1: weim_norgrp-1 {
1656 fsl,pins = <
1657 MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1
1658 MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1
1659 MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060
1660 /* data */
1661 MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0
1662 MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0
1663 MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0
1664 MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0
1665 MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0
1666 MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0
1667 MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0
1668 MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0
1669 MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0
1670 MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0
1671 MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0
1672 MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0
1673 MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0
1674 MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0
1675 MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0
1676 MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0
1677 /* address */
1678 MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1
1679 MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1
1680 MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1
1681 MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1
1682 MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1
1683 MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1
1684 MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1
1685 MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1
1686 MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1
1687 MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1
1688 MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1
1689 MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1
1690 MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1
1691 MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1
1692 MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1
1693 MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1
1694 MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1
1695 MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1
1696 MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1
1697 MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1
1698 MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1
1699 MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1
1700 MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1
1701 MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1
1702 MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1
1703 MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1
1704 >;
1705 };
1706 };
1640}; 1707};