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authorDave Airlie <airlied@redhat.com>2011-01-09 18:27:06 -0500
committerDave Airlie <airlied@redhat.com>2011-01-09 18:27:06 -0500
commitc3307cd6a7ca91c257795c5275e887a3eafb6880 (patch)
treee4ddaa114644f16ef44026c3f4e5376e90e9c25c
parent0ba41e449fd0f45f5b29c1009020ab1b298bedda (diff)
parent187f3da3d98a1740d71e1f5d4fb3c68df09ecca8 (diff)
Merge branch 'drm-radeon-ni' of ../drm-radeon-next into drm-core-next
* 'drm-radeon-ni' of ../drm-radeon-next: (30 commits) radeon: consolidate asic-specific function decls for pre-r600 drm/radeon/kms: add NI pci ids drm/radeon/kms: don't enable pcie gen2 on NI yet drm/radeon/kms: add radeon_asic struct for NI asics drm/radeon/kms/ni: load default sclk/mclk/vddc at pm init drm/radeon/kms: add ucode loader for NI drm/radeon/kms: add support for DCE5 display LUTs drm/radeon/kms: add ni_reg.h drm/radeon/kms: add bo blit support for NI drm/radeon/kms: always use writeback/events for fences on NI drm/radeon/kms: adjust default clock/vddc tracking for pm on DCE5 drm/radeon/kms: add backend map workaround for barts drm/radeon/kms: fill gpu init for NI asics drm/radeon/kms: add disabled vbios accessor for NI asics drm/radeon/kms: handle NI thermal controller drm/radeon/kms: parse DCE5 encoder caps when setting up encoders drm/radeon/kms: dvo dpms updates for DCE5 drm/radeon/kms: dac dpms updates for DCE5 drm/radeon/kms: DCE5 atom dig encoder updates drm/radeon/kms: DCE5 atom transmitter control updates ...
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/Makefile2
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c57
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c169
-rw-r--r--drivers/gpu/drm/radeon/evergreen_blit_kms.c69
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h44
-rw-r--r--drivers/gpu/drm/radeon/ni.c316
-rw-r--r--drivers/gpu/drm/radeon/ni_reg.h86
-rw-r--r--drivers/gpu/drm/radeon/nid.h41
-rw-r--r--drivers/gpu/drm/radeon/r300.c5
-rw-r--r--drivers/gpu/drm/radeon/r600.c220
-rw-r--r--drivers/gpu/drm/radeon/r600d.h39
-rw-r--r--drivers/gpu/drm/radeon/radeon.h81
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c65
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h55
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c100
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c41
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c73
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c106
-rw-r--r--drivers/gpu/drm/radeon/radeon_family.h3
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c37
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h10
-rw-r--r--drivers/gpu/drm/radeon/rv770.c76
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h38
-rw-r--r--include/drm/drm_pciids.h36
26 files changed, 1629 insertions, 149 deletions
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index e97e6f842699..e47eecfc2df4 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -66,7 +66,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
66 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ 66 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
67 r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ 67 r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
68 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \ 68 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
69 radeon_trace_points.o 69 radeon_trace_points.o ni.o
70 70
71radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 71radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
72radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o 72radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 9fbabaa6ee44..b0ab185b86f6 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -403,6 +403,7 @@ union atom_enable_ss {
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
406}; 407};
407 408
408static void atombios_crtc_program_ss(struct drm_crtc *crtc, 409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
@@ -417,7 +418,30 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
417 418
418 memset(&args, 0, sizeof(args)); 419 memset(&args, 0, sizeof(args));
419 420
420 if (ASIC_IS_DCE4(rdev)) { 421 if (ASIC_IS_DCE5(rdev)) {
422 args.v3.usSpreadSpectrumAmountFrac = 0;
423 args.v3.ucSpreadSpectrumType = ss->type;
424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
427 args.v3.usSpreadSpectrumAmount = ss->amount;
428 args.v3.usSpreadSpectrumStep = ss->step;
429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
432 args.v3.usSpreadSpectrumAmount = ss->amount;
433 args.v3.usSpreadSpectrumStep = ss->step;
434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
437 args.v3.usSpreadSpectrumAmount = 0;
438 args.v3.usSpreadSpectrumStep = 0;
439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
443 args.v2.ucEnable = enable;
444 } else if (ASIC_IS_DCE4(rdev)) {
421 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 445 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
422 args.v2.ucSpreadSpectrumType = ss->type; 446 args.v2.ucSpreadSpectrumType = ss->type;
423 switch (pll_id) { 447 switch (pll_id) {
@@ -673,9 +697,14 @@ union set_pixel_clock {
673 PIXEL_CLOCK_PARAMETERS_V2 v2; 697 PIXEL_CLOCK_PARAMETERS_V2 v2;
674 PIXEL_CLOCK_PARAMETERS_V3 v3; 698 PIXEL_CLOCK_PARAMETERS_V3 v3;
675 PIXEL_CLOCK_PARAMETERS_V5 v5; 699 PIXEL_CLOCK_PARAMETERS_V5 v5;
700 PIXEL_CLOCK_PARAMETERS_V6 v6;
676}; 701};
677 702
678static void atombios_crtc_set_dcpll(struct drm_crtc *crtc) 703/* on DCE5, make sure the voltage is high enough to support the
704 * required disp clk.
705 */
706static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
707 u32 dispclk)
679{ 708{
680 struct drm_device *dev = crtc->dev; 709 struct drm_device *dev = crtc->dev;
681 struct radeon_device *rdev = dev->dev_private; 710 struct radeon_device *rdev = dev->dev_private;
@@ -698,9 +727,16 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
698 * SetPixelClock provides the dividers 727 * SetPixelClock provides the dividers
699 */ 728 */
700 args.v5.ucCRTC = ATOM_CRTC_INVALID; 729 args.v5.ucCRTC = ATOM_CRTC_INVALID;
701 args.v5.usPixelClock = rdev->clock.default_dispclk; 730 args.v5.usPixelClock = dispclk;
702 args.v5.ucPpll = ATOM_DCPLL; 731 args.v5.ucPpll = ATOM_DCPLL;
703 break; 732 break;
733 case 6:
734 /* if the default dcpll clock is specified,
735 * SetPixelClock provides the dividers
736 */
737 args.v6.ulDispEngClkFreq = dispclk;
738 args.v6.ucPpll = ATOM_DCPLL;
739 break;
704 default: 740 default:
705 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 741 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
706 return; 742 return;
@@ -784,6 +820,18 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
784 args.v5.ucEncoderMode = encoder_mode; 820 args.v5.ucEncoderMode = encoder_mode;
785 args.v5.ucPpll = pll_id; 821 args.v5.ucPpll = pll_id;
786 break; 822 break;
823 case 6:
824 args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
825 args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);
826 args.v6.ucRefDiv = ref_div;
827 args.v6.usFbDiv = cpu_to_le16(fb_div);
828 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
829 args.v6.ucPostDiv = post_div;
830 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
831 args.v6.ucTransmitterID = encoder_id;
832 args.v6.ucEncoderMode = encoder_mode;
833 args.v6.ucPpll = pll_id;
834 break;
787 default: 835 default:
788 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 836 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
789 return; 837 return;
@@ -1377,7 +1425,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
1377 rdev->clock.default_dispclk); 1425 rdev->clock.default_dispclk);
1378 if (ss_enabled) 1426 if (ss_enabled)
1379 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss); 1427 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1380 atombios_crtc_set_dcpll(crtc); 1428 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1429 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
1381 if (ss_enabled) 1430 if (ss_enabled)
1382 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss); 1431 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1383 } 1432 }
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index eaf4fba90b72..7fe8ebdcdc0e 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -39,6 +39,7 @@
39 39
40static void evergreen_gpu_init(struct radeon_device *rdev); 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev); 41void evergreen_fini(struct radeon_device *rdev);
42static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
42 43
43void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) 44void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
44{ 45{
@@ -400,16 +401,28 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
400 case 0: 401 case 0:
401 case 4: 402 case 4:
402 default: 403 default:
403 return 3840 * 2; 404 if (ASIC_IS_DCE5(rdev))
405 return 4096 * 2;
406 else
407 return 3840 * 2;
404 case 1: 408 case 1:
405 case 5: 409 case 5:
406 return 5760 * 2; 410 if (ASIC_IS_DCE5(rdev))
411 return 6144 * 2;
412 else
413 return 5760 * 2;
407 case 2: 414 case 2:
408 case 6: 415 case 6:
409 return 7680 * 2; 416 if (ASIC_IS_DCE5(rdev))
417 return 8192 * 2;
418 else
419 return 7680 * 2;
410 case 3: 420 case 3:
411 case 7: 421 case 7:
412 return 1920 * 2; 422 if (ASIC_IS_DCE5(rdev))
423 return 2048 * 2;
424 else
425 return 1920 * 2;
413 } 426 }
414} 427}
415 428
@@ -1146,7 +1159,7 @@ static void evergreen_mc_program(struct radeon_device *rdev)
1146 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1159 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1147 WREG32(MC_VM_FB_LOCATION, tmp); 1160 WREG32(MC_VM_FB_LOCATION, tmp);
1148 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1161 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1149 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1162 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1150 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1163 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1151 if (rdev->flags & RADEON_IS_AGP) { 1164 if (rdev->flags & RADEON_IS_AGP) {
1152 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 1165 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
@@ -1371,11 +1384,14 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1371 case CHIP_CEDAR: 1384 case CHIP_CEDAR:
1372 case CHIP_REDWOOD: 1385 case CHIP_REDWOOD:
1373 case CHIP_PALM: 1386 case CHIP_PALM:
1387 case CHIP_TURKS:
1388 case CHIP_CAICOS:
1374 force_no_swizzle = false; 1389 force_no_swizzle = false;
1375 break; 1390 break;
1376 case CHIP_CYPRESS: 1391 case CHIP_CYPRESS:
1377 case CHIP_HEMLOCK: 1392 case CHIP_HEMLOCK:
1378 case CHIP_JUNIPER: 1393 case CHIP_JUNIPER:
1394 case CHIP_BARTS:
1379 default: 1395 default:
1380 force_no_swizzle = true; 1396 force_no_swizzle = true;
1381 break; 1397 break;
@@ -1489,6 +1505,7 @@ static void evergreen_program_channel_remap(struct radeon_device *rdev)
1489 switch (rdev->family) { 1505 switch (rdev->family) {
1490 case CHIP_HEMLOCK: 1506 case CHIP_HEMLOCK:
1491 case CHIP_CYPRESS: 1507 case CHIP_CYPRESS:
1508 case CHIP_BARTS:
1492 tcp_chan_steer_lo = 0x54763210; 1509 tcp_chan_steer_lo = 0x54763210;
1493 tcp_chan_steer_hi = 0x0000ba98; 1510 tcp_chan_steer_hi = 0x0000ba98;
1494 break; 1511 break;
@@ -1496,6 +1513,8 @@ static void evergreen_program_channel_remap(struct radeon_device *rdev)
1496 case CHIP_REDWOOD: 1513 case CHIP_REDWOOD:
1497 case CHIP_CEDAR: 1514 case CHIP_CEDAR:
1498 case CHIP_PALM: 1515 case CHIP_PALM:
1516 case CHIP_TURKS:
1517 case CHIP_CAICOS:
1499 default: 1518 default:
1500 tcp_chan_steer_lo = 0x76543210; 1519 tcp_chan_steer_lo = 0x76543210;
1501 tcp_chan_steer_hi = 0x0000ba98; 1520 tcp_chan_steer_hi = 0x0000ba98;
@@ -1639,6 +1658,69 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1639 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1658 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1640 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1659 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1641 break; 1660 break;
1661 case CHIP_BARTS:
1662 rdev->config.evergreen.num_ses = 2;
1663 rdev->config.evergreen.max_pipes = 4;
1664 rdev->config.evergreen.max_tile_pipes = 8;
1665 rdev->config.evergreen.max_simds = 7;
1666 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1667 rdev->config.evergreen.max_gprs = 256;
1668 rdev->config.evergreen.max_threads = 248;
1669 rdev->config.evergreen.max_gs_threads = 32;
1670 rdev->config.evergreen.max_stack_entries = 512;
1671 rdev->config.evergreen.sx_num_of_sets = 4;
1672 rdev->config.evergreen.sx_max_export_size = 256;
1673 rdev->config.evergreen.sx_max_export_pos_size = 64;
1674 rdev->config.evergreen.sx_max_export_smx_size = 192;
1675 rdev->config.evergreen.max_hw_contexts = 8;
1676 rdev->config.evergreen.sq_num_cf_insts = 2;
1677
1678 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1679 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1680 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1681 break;
1682 case CHIP_TURKS:
1683 rdev->config.evergreen.num_ses = 1;
1684 rdev->config.evergreen.max_pipes = 4;
1685 rdev->config.evergreen.max_tile_pipes = 4;
1686 rdev->config.evergreen.max_simds = 6;
1687 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1688 rdev->config.evergreen.max_gprs = 256;
1689 rdev->config.evergreen.max_threads = 248;
1690 rdev->config.evergreen.max_gs_threads = 32;
1691 rdev->config.evergreen.max_stack_entries = 256;
1692 rdev->config.evergreen.sx_num_of_sets = 4;
1693 rdev->config.evergreen.sx_max_export_size = 256;
1694 rdev->config.evergreen.sx_max_export_pos_size = 64;
1695 rdev->config.evergreen.sx_max_export_smx_size = 192;
1696 rdev->config.evergreen.max_hw_contexts = 8;
1697 rdev->config.evergreen.sq_num_cf_insts = 2;
1698
1699 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1700 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1701 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1702 break;
1703 case CHIP_CAICOS:
1704 rdev->config.evergreen.num_ses = 1;
1705 rdev->config.evergreen.max_pipes = 4;
1706 rdev->config.evergreen.max_tile_pipes = 2;
1707 rdev->config.evergreen.max_simds = 2;
1708 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1709 rdev->config.evergreen.max_gprs = 256;
1710 rdev->config.evergreen.max_threads = 192;
1711 rdev->config.evergreen.max_gs_threads = 16;
1712 rdev->config.evergreen.max_stack_entries = 256;
1713 rdev->config.evergreen.sx_num_of_sets = 4;
1714 rdev->config.evergreen.sx_max_export_size = 128;
1715 rdev->config.evergreen.sx_max_export_pos_size = 32;
1716 rdev->config.evergreen.sx_max_export_smx_size = 96;
1717 rdev->config.evergreen.max_hw_contexts = 4;
1718 rdev->config.evergreen.sq_num_cf_insts = 1;
1719
1720 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1721 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1722 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1723 break;
1642 } 1724 }
1643 1725
1644 /* Initialize HDP */ 1726 /* Initialize HDP */
@@ -1780,6 +1862,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1780 switch (rdev->family) { 1862 switch (rdev->family) {
1781 case CHIP_CYPRESS: 1863 case CHIP_CYPRESS:
1782 case CHIP_HEMLOCK: 1864 case CHIP_HEMLOCK:
1865 case CHIP_BARTS:
1783 gb_backend_map = 0x66442200; 1866 gb_backend_map = 0x66442200;
1784 break; 1867 break;
1785 case CHIP_JUNIPER: 1868 case CHIP_JUNIPER:
@@ -1918,6 +2001,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1918 switch (rdev->family) { 2001 switch (rdev->family) {
1919 case CHIP_CEDAR: 2002 case CHIP_CEDAR:
1920 case CHIP_PALM: 2003 case CHIP_PALM:
2004 case CHIP_CAICOS:
1921 /* no vertex cache */ 2005 /* no vertex cache */
1922 sq_config &= ~VC_ENABLE; 2006 sq_config &= ~VC_ENABLE;
1923 break; 2007 break;
@@ -1977,6 +2061,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1977 switch (rdev->family) { 2061 switch (rdev->family) {
1978 case CHIP_CEDAR: 2062 case CHIP_CEDAR:
1979 case CHIP_PALM: 2063 case CHIP_PALM:
2064 case CHIP_CAICOS:
1980 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); 2065 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1981 break; 2066 break;
1982 default: 2067 default:
@@ -2767,12 +2852,31 @@ static int evergreen_startup(struct radeon_device *rdev)
2767{ 2852{
2768 int r; 2853 int r;
2769 2854
2770 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2855 /* enable pcie gen2 link */
2771 r = r600_init_microcode(rdev); 2856 if (!ASIC_IS_DCE5(rdev))
2857 evergreen_pcie_gen2_enable(rdev);
2858
2859 if (ASIC_IS_DCE5(rdev)) {
2860 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2861 r = ni_init_microcode(rdev);
2862 if (r) {
2863 DRM_ERROR("Failed to load firmware!\n");
2864 return r;
2865 }
2866 }
2867 r = btc_mc_load_microcode(rdev);
2772 if (r) { 2868 if (r) {
2773 DRM_ERROR("Failed to load firmware!\n"); 2869 DRM_ERROR("Failed to load MC firmware!\n");
2774 return r; 2870 return r;
2775 } 2871 }
2872 } else {
2873 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2874 r = r600_init_microcode(rdev);
2875 if (r) {
2876 DRM_ERROR("Failed to load firmware!\n");
2877 return r;
2878 }
2879 }
2776 } 2880 }
2777 2881
2778 evergreen_mc_program(rdev); 2882 evergreen_mc_program(rdev);
@@ -3049,3 +3153,52 @@ void evergreen_fini(struct radeon_device *rdev)
3049 rdev->bios = NULL; 3153 rdev->bios = NULL;
3050 radeon_dummy_page_fini(rdev); 3154 radeon_dummy_page_fini(rdev);
3051} 3155}
3156
3157static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3158{
3159 u32 link_width_cntl, speed_cntl;
3160
3161 if (rdev->flags & RADEON_IS_IGP)
3162 return;
3163
3164 if (!(rdev->flags & RADEON_IS_PCIE))
3165 return;
3166
3167 /* x2 cards have a special sequence */
3168 if (ASIC_IS_X2(rdev))
3169 return;
3170
3171 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3172 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3173 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3174
3175 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3176 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3177 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3178
3179 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3180 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3181 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3182
3183 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3184 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3185 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3186
3187 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3188 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3189 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3190
3191 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3192 speed_cntl |= LC_GEN2_EN_STRAP;
3193 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3194
3195 } else {
3196 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3197 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3198 if (1)
3199 link_width_cntl |= LC_UPCONFIGURE_DIS;
3200 else
3201 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3202 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3203 }
3204}
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index 2ccd1f0545fe..b758dc7f2f2c 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -148,7 +148,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
148 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); 148 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
149 149
150 if ((rdev->family == CHIP_CEDAR) || 150 if ((rdev->family == CHIP_CEDAR) ||
151 (rdev->family == CHIP_PALM)) 151 (rdev->family == CHIP_PALM) ||
152 (rdev->family == CHIP_CAICOS))
152 cp_set_surface_sync(rdev, 153 cp_set_surface_sync(rdev,
153 PACKET3_TC_ACTION_ENA, 48, gpu_addr); 154 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
154 else 155 else
@@ -353,10 +354,74 @@ set_default_state(struct radeon_device *rdev)
353 num_hs_stack_entries = 42; 354 num_hs_stack_entries = 42;
354 num_ls_stack_entries = 42; 355 num_ls_stack_entries = 42;
355 break; 356 break;
357 case CHIP_BARTS:
358 num_ps_gprs = 93;
359 num_vs_gprs = 46;
360 num_temp_gprs = 4;
361 num_gs_gprs = 31;
362 num_es_gprs = 31;
363 num_hs_gprs = 23;
364 num_ls_gprs = 23;
365 num_ps_threads = 128;
366 num_vs_threads = 20;
367 num_gs_threads = 20;
368 num_es_threads = 20;
369 num_hs_threads = 20;
370 num_ls_threads = 20;
371 num_ps_stack_entries = 85;
372 num_vs_stack_entries = 85;
373 num_gs_stack_entries = 85;
374 num_es_stack_entries = 85;
375 num_hs_stack_entries = 85;
376 num_ls_stack_entries = 85;
377 break;
378 case CHIP_TURKS:
379 num_ps_gprs = 93;
380 num_vs_gprs = 46;
381 num_temp_gprs = 4;
382 num_gs_gprs = 31;
383 num_es_gprs = 31;
384 num_hs_gprs = 23;
385 num_ls_gprs = 23;
386 num_ps_threads = 128;
387 num_vs_threads = 20;
388 num_gs_threads = 20;
389 num_es_threads = 20;
390 num_hs_threads = 20;
391 num_ls_threads = 20;
392 num_ps_stack_entries = 42;
393 num_vs_stack_entries = 42;
394 num_gs_stack_entries = 42;
395 num_es_stack_entries = 42;
396 num_hs_stack_entries = 42;
397 num_ls_stack_entries = 42;
398 break;
399 case CHIP_CAICOS:
400 num_ps_gprs = 93;
401 num_vs_gprs = 46;
402 num_temp_gprs = 4;
403 num_gs_gprs = 31;
404 num_es_gprs = 31;
405 num_hs_gprs = 23;
406 num_ls_gprs = 23;
407 num_ps_threads = 128;
408 num_vs_threads = 10;
409 num_gs_threads = 10;
410 num_es_threads = 10;
411 num_hs_threads = 10;
412 num_ls_threads = 10;
413 num_ps_stack_entries = 42;
414 num_vs_stack_entries = 42;
415 num_gs_stack_entries = 42;
416 num_es_stack_entries = 42;
417 num_hs_stack_entries = 42;
418 num_ls_stack_entries = 42;
419 break;
356 } 420 }
357 421
358 if ((rdev->family == CHIP_CEDAR) || 422 if ((rdev->family == CHIP_CEDAR) ||
359 (rdev->family == CHIP_PALM)) 423 (rdev->family == CHIP_PALM) ||
424 (rdev->family == CHIP_CAICOS))
360 sq_config = 0; 425 sq_config = 0;
361 else 426 else
362 sq_config = VC_ENABLE; 427 sq_config = VC_ENABLE;
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 94140e142abb..36d32d83d866 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -581,6 +581,44 @@
581# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 581# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
582# define DC_HPDx_EN (1 << 28) 582# define DC_HPDx_EN (1 << 28)
583 583
584/* PCIE link stuff */
585#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
586#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
587# define LC_LINK_WIDTH_SHIFT 0
588# define LC_LINK_WIDTH_MASK 0x7
589# define LC_LINK_WIDTH_X0 0
590# define LC_LINK_WIDTH_X1 1
591# define LC_LINK_WIDTH_X2 2
592# define LC_LINK_WIDTH_X4 3
593# define LC_LINK_WIDTH_X8 4
594# define LC_LINK_WIDTH_X16 6
595# define LC_LINK_WIDTH_RD_SHIFT 4
596# define LC_LINK_WIDTH_RD_MASK 0x70
597# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
598# define LC_RECONFIG_NOW (1 << 8)
599# define LC_RENEGOTIATION_SUPPORT (1 << 9)
600# define LC_RENEGOTIATE_EN (1 << 10)
601# define LC_SHORT_RECONFIG_EN (1 << 11)
602# define LC_UPCONFIGURE_SUPPORT (1 << 12)
603# define LC_UPCONFIGURE_DIS (1 << 13)
604#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
605# define LC_GEN2_EN_STRAP (1 << 0)
606# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
607# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
608# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
609# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
610# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
611# define LC_CURRENT_DATA_RATE (1 << 11)
612# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
613# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
614# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
615# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
616#define MM_CFGREGS_CNTL 0x544c
617# define MM_WR_TO_CFG_EN (1 << 3)
618#define LINK_CNTL2 0x88 /* F0 */
619# define TARGET_LINK_SPEED_MASK (0xf << 0)
620# define SELECTABLE_DEEMPHASIS (1 << 6)
621
584/* 622/*
585 * PM4 623 * PM4
586 */ 624 */
@@ -610,7 +648,7 @@
610#define PACKET3_NOP 0x10 648#define PACKET3_NOP 0x10
611#define PACKET3_SET_BASE 0x11 649#define PACKET3_SET_BASE 0x11
612#define PACKET3_CLEAR_STATE 0x12 650#define PACKET3_CLEAR_STATE 0x12
613#define PACKET3_INDIRECT_BUFFER_SIZE 0x13 651#define PACKET3_INDEX_BUFFER_SIZE 0x13
614#define PACKET3_DISPATCH_DIRECT 0x15 652#define PACKET3_DISPATCH_DIRECT 0x15
615#define PACKET3_DISPATCH_INDIRECT 0x16 653#define PACKET3_DISPATCH_INDIRECT 0x16
616#define PACKET3_INDIRECT_BUFFER_END 0x17 654#define PACKET3_INDIRECT_BUFFER_END 0x17
@@ -651,14 +689,14 @@
651# define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 689# define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
652# define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 690# define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
653# define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 691# define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
654# define PACKET3_CB11_DEST_BASE_ENA (1 << 17) 692# define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
655# define PACKET3_FULL_CACHE_ENA (1 << 20) 693# define PACKET3_FULL_CACHE_ENA (1 << 20)
656# define PACKET3_TC_ACTION_ENA (1 << 23) 694# define PACKET3_TC_ACTION_ENA (1 << 23)
657# define PACKET3_VC_ACTION_ENA (1 << 24) 695# define PACKET3_VC_ACTION_ENA (1 << 24)
658# define PACKET3_CB_ACTION_ENA (1 << 25) 696# define PACKET3_CB_ACTION_ENA (1 << 25)
659# define PACKET3_DB_ACTION_ENA (1 << 26) 697# define PACKET3_DB_ACTION_ENA (1 << 26)
660# define PACKET3_SH_ACTION_ENA (1 << 27) 698# define PACKET3_SH_ACTION_ENA (1 << 27)
661# define PACKET3_SMX_ACTION_ENA (1 << 28) 699# define PACKET3_SX_ACTION_ENA (1 << 28)
662#define PACKET3_ME_INITIALIZE 0x44 700#define PACKET3_ME_INITIALIZE 0x44
663#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 701#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
664#define PACKET3_COND_WRITE 0x45 702#define PACKET3_COND_WRITE 0x45
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
new file mode 100644
index 000000000000..5e0bef80ad7f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -0,0 +1,316 @@
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include "drmP.h"
28#include "radeon.h"
29#include "radeon_asic.h"
30#include "radeon_drm.h"
31#include "nid.h"
32#include "atom.h"
33#include "ni_reg.h"
34
35#define EVERGREEN_PFP_UCODE_SIZE 1120
36#define EVERGREEN_PM4_UCODE_SIZE 1376
37#define EVERGREEN_RLC_UCODE_SIZE 768
38#define BTC_MC_UCODE_SIZE 6024
39
40/* Firmware Names */
41MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
42MODULE_FIRMWARE("radeon/BARTS_me.bin");
43MODULE_FIRMWARE("radeon/BARTS_mc.bin");
44MODULE_FIRMWARE("radeon/BTC_rlc.bin");
45MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
46MODULE_FIRMWARE("radeon/TURKS_me.bin");
47MODULE_FIRMWARE("radeon/TURKS_mc.bin");
48MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
49MODULE_FIRMWARE("radeon/CAICOS_me.bin");
50MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
51
52#define BTC_IO_MC_REGS_SIZE 29
53
54static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
55 {0x00000077, 0xff010100},
56 {0x00000078, 0x00000000},
57 {0x00000079, 0x00001434},
58 {0x0000007a, 0xcc08ec08},
59 {0x0000007b, 0x00040000},
60 {0x0000007c, 0x000080c0},
61 {0x0000007d, 0x09000000},
62 {0x0000007e, 0x00210404},
63 {0x00000081, 0x08a8e800},
64 {0x00000082, 0x00030444},
65 {0x00000083, 0x00000000},
66 {0x00000085, 0x00000001},
67 {0x00000086, 0x00000002},
68 {0x00000087, 0x48490000},
69 {0x00000088, 0x20244647},
70 {0x00000089, 0x00000005},
71 {0x0000008b, 0x66030000},
72 {0x0000008c, 0x00006603},
73 {0x0000008d, 0x00000100},
74 {0x0000008f, 0x00001c0a},
75 {0x00000090, 0xff000001},
76 {0x00000094, 0x00101101},
77 {0x00000095, 0x00000fff},
78 {0x00000096, 0x00116fff},
79 {0x00000097, 0x60010000},
80 {0x00000098, 0x10010000},
81 {0x00000099, 0x00006000},
82 {0x0000009a, 0x00001000},
83 {0x0000009f, 0x00946a00}
84};
85
86static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
87 {0x00000077, 0xff010100},
88 {0x00000078, 0x00000000},
89 {0x00000079, 0x00001434},
90 {0x0000007a, 0xcc08ec08},
91 {0x0000007b, 0x00040000},
92 {0x0000007c, 0x000080c0},
93 {0x0000007d, 0x09000000},
94 {0x0000007e, 0x00210404},
95 {0x00000081, 0x08a8e800},
96 {0x00000082, 0x00030444},
97 {0x00000083, 0x00000000},
98 {0x00000085, 0x00000001},
99 {0x00000086, 0x00000002},
100 {0x00000087, 0x48490000},
101 {0x00000088, 0x20244647},
102 {0x00000089, 0x00000005},
103 {0x0000008b, 0x66030000},
104 {0x0000008c, 0x00006603},
105 {0x0000008d, 0x00000100},
106 {0x0000008f, 0x00001c0a},
107 {0x00000090, 0xff000001},
108 {0x00000094, 0x00101101},
109 {0x00000095, 0x00000fff},
110 {0x00000096, 0x00116fff},
111 {0x00000097, 0x60010000},
112 {0x00000098, 0x10010000},
113 {0x00000099, 0x00006000},
114 {0x0000009a, 0x00001000},
115 {0x0000009f, 0x00936a00}
116};
117
118static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
119 {0x00000077, 0xff010100},
120 {0x00000078, 0x00000000},
121 {0x00000079, 0x00001434},
122 {0x0000007a, 0xcc08ec08},
123 {0x0000007b, 0x00040000},
124 {0x0000007c, 0x000080c0},
125 {0x0000007d, 0x09000000},
126 {0x0000007e, 0x00210404},
127 {0x00000081, 0x08a8e800},
128 {0x00000082, 0x00030444},
129 {0x00000083, 0x00000000},
130 {0x00000085, 0x00000001},
131 {0x00000086, 0x00000002},
132 {0x00000087, 0x48490000},
133 {0x00000088, 0x20244647},
134 {0x00000089, 0x00000005},
135 {0x0000008b, 0x66030000},
136 {0x0000008c, 0x00006603},
137 {0x0000008d, 0x00000100},
138 {0x0000008f, 0x00001c0a},
139 {0x00000090, 0xff000001},
140 {0x00000094, 0x00101101},
141 {0x00000095, 0x00000fff},
142 {0x00000096, 0x00116fff},
143 {0x00000097, 0x60010000},
144 {0x00000098, 0x10010000},
145 {0x00000099, 0x00006000},
146 {0x0000009a, 0x00001000},
147 {0x0000009f, 0x00916a00}
148};
149
150int btc_mc_load_microcode(struct radeon_device *rdev)
151{
152 const __be32 *fw_data;
153 u32 mem_type, running, blackout = 0;
154 u32 *io_mc_regs;
155 int i;
156
157 if (!rdev->mc_fw)
158 return -EINVAL;
159
160 switch (rdev->family) {
161 case CHIP_BARTS:
162 io_mc_regs = (u32 *)&barts_io_mc_regs;
163 break;
164 case CHIP_TURKS:
165 io_mc_regs = (u32 *)&turks_io_mc_regs;
166 break;
167 case CHIP_CAICOS:
168 default:
169 io_mc_regs = (u32 *)&caicos_io_mc_regs;
170 break;
171 }
172
173 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
174 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
175
176 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
177 if (running) {
178 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
179 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
180 }
181
182 /* reset the engine and set to writable */
183 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
184 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
185
186 /* load mc io regs */
187 for (i = 0; i < BTC_IO_MC_REGS_SIZE; i++) {
188 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
189 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
190 }
191 /* load the MC ucode */
192 fw_data = (const __be32 *)rdev->mc_fw->data;
193 for (i = 0; i < BTC_MC_UCODE_SIZE; i++)
194 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
195
196 /* put the engine back into the active state */
197 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
198 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
199 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
200
201 /* wait for training to complete */
202 while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD))
203 udelay(10);
204
205 if (running)
206 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
207 }
208
209 return 0;
210}
211
212int ni_init_microcode(struct radeon_device *rdev)
213{
214 struct platform_device *pdev;
215 const char *chip_name;
216 const char *rlc_chip_name;
217 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
218 char fw_name[30];
219 int err;
220
221 DRM_DEBUG("\n");
222
223 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
224 err = IS_ERR(pdev);
225 if (err) {
226 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
227 return -EINVAL;
228 }
229
230 switch (rdev->family) {
231 case CHIP_BARTS:
232 chip_name = "BARTS";
233 rlc_chip_name = "BTC";
234 break;
235 case CHIP_TURKS:
236 chip_name = "TURKS";
237 rlc_chip_name = "BTC";
238 break;
239 case CHIP_CAICOS:
240 chip_name = "CAICOS";
241 rlc_chip_name = "BTC";
242 break;
243 default: BUG();
244 }
245
246 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
247 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
248 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
249 mc_req_size = BTC_MC_UCODE_SIZE * 4;
250
251 DRM_INFO("Loading %s Microcode\n", chip_name);
252
253 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
254 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
255 if (err)
256 goto out;
257 if (rdev->pfp_fw->size != pfp_req_size) {
258 printk(KERN_ERR
259 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
260 rdev->pfp_fw->size, fw_name);
261 err = -EINVAL;
262 goto out;
263 }
264
265 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
266 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
267 if (err)
268 goto out;
269 if (rdev->me_fw->size != me_req_size) {
270 printk(KERN_ERR
271 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
272 rdev->me_fw->size, fw_name);
273 err = -EINVAL;
274 }
275
276 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
277 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
278 if (err)
279 goto out;
280 if (rdev->rlc_fw->size != rlc_req_size) {
281 printk(KERN_ERR
282 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
283 rdev->rlc_fw->size, fw_name);
284 err = -EINVAL;
285 }
286
287 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
288 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
289 if (err)
290 goto out;
291 if (rdev->mc_fw->size != mc_req_size) {
292 printk(KERN_ERR
293 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
294 rdev->mc_fw->size, fw_name);
295 err = -EINVAL;
296 }
297out:
298 platform_device_unregister(pdev);
299
300 if (err) {
301 if (err != -EINVAL)
302 printk(KERN_ERR
303 "ni_cp: Failed to load firmware \"%s\"\n",
304 fw_name);
305 release_firmware(rdev->pfp_fw);
306 rdev->pfp_fw = NULL;
307 release_firmware(rdev->me_fw);
308 rdev->me_fw = NULL;
309 release_firmware(rdev->rlc_fw);
310 rdev->rlc_fw = NULL;
311 release_firmware(rdev->mc_fw);
312 rdev->mc_fw = NULL;
313 }
314 return err;
315}
316
diff --git a/drivers/gpu/drm/radeon/ni_reg.h b/drivers/gpu/drm/radeon/ni_reg.h
new file mode 100644
index 000000000000..5db7b7d6feb0
--- /dev/null
+++ b/drivers/gpu/drm/radeon/ni_reg.h
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef __NI_REG_H__
25#define __NI_REG_H__
26
27/* northern islands - DCE5 */
28
29#define NI_INPUT_GAMMA_CONTROL 0x6840
30# define NI_GRPH_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 0)
31# define NI_INPUT_GAMMA_USE_LUT 0
32# define NI_INPUT_GAMMA_BYPASS 1
33# define NI_INPUT_GAMMA_SRGB_24 2
34# define NI_INPUT_GAMMA_XVYCC_222 3
35# define NI_OVL_INPUT_GAMMA_MODE(x) (((x) & 0x3) << 4)
36
37#define NI_PRESCALE_GRPH_CONTROL 0x68b4
38# define NI_GRPH_PRESCALE_BYPASS (1 << 4)
39
40#define NI_PRESCALE_OVL_CONTROL 0x68c4
41# define NI_OVL_PRESCALE_BYPASS (1 << 4)
42
43#define NI_INPUT_CSC_CONTROL 0x68d4
44# define NI_INPUT_CSC_GRPH_MODE(x) (((x) & 0x3) << 0)
45# define NI_INPUT_CSC_BYPASS 0
46# define NI_INPUT_CSC_PROG_COEFF 1
47# define NI_INPUT_CSC_PROG_SHARED_MATRIXA 2
48# define NI_INPUT_CSC_OVL_MODE(x) (((x) & 0x3) << 4)
49
50#define NI_OUTPUT_CSC_CONTROL 0x68f0
51# define NI_OUTPUT_CSC_GRPH_MODE(x) (((x) & 0x7) << 0)
52# define NI_OUTPUT_CSC_BYPASS 0
53# define NI_OUTPUT_CSC_TV_RGB 1
54# define NI_OUTPUT_CSC_YCBCR_601 2
55# define NI_OUTPUT_CSC_YCBCR_709 3
56# define NI_OUTPUT_CSC_PROG_COEFF 4
57# define NI_OUTPUT_CSC_PROG_SHARED_MATRIXB 5
58# define NI_OUTPUT_CSC_OVL_MODE(x) (((x) & 0x7) << 4)
59
60#define NI_DEGAMMA_CONTROL 0x6960
61# define NI_GRPH_DEGAMMA_MODE(x) (((x) & 0x3) << 0)
62# define NI_DEGAMMA_BYPASS 0
63# define NI_DEGAMMA_SRGB_24 1
64# define NI_DEGAMMA_XVYCC_222 2
65# define NI_OVL_DEGAMMA_MODE(x) (((x) & 0x3) << 4)
66# define NI_ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
67# define NI_CURSOR_DEGAMMA_MODE(x) (((x) & 0x3) << 12)
68
69#define NI_GAMUT_REMAP_CONTROL 0x6964
70# define NI_GRPH_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 0)
71# define NI_GAMUT_REMAP_BYPASS 0
72# define NI_GAMUT_REMAP_PROG_COEFF 1
73# define NI_GAMUT_REMAP_PROG_SHARED_MATRIXA 2
74# define NI_GAMUT_REMAP_PROG_SHARED_MATRIXB 3
75# define NI_OVL_GAMUT_REMAP_MODE(x) (((x) & 0x3) << 4)
76
77#define NI_REGAMMA_CONTROL 0x6a80
78# define NI_GRPH_REGAMMA_MODE(x) (((x) & 0x7) << 0)
79# define NI_REGAMMA_BYPASS 0
80# define NI_REGAMMA_SRGB_24 1
81# define NI_REGAMMA_XVYCC_222 2
82# define NI_REGAMMA_PROG_A 3
83# define NI_REGAMMA_PROG_B 4
84# define NI_OVL_REGAMMA_MODE(x) (((x) & 0x7) << 4)
85
86#endif
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
new file mode 100644
index 000000000000..f7b445390e02
--- /dev/null
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef NI_H
25#define NI_H
26
27#define MC_SHARED_BLACKOUT_CNTL 0x20ac
28#define MC_SEQ_SUP_CNTL 0x28c8
29#define RUN_MASK (1 << 0)
30#define MC_SEQ_SUP_PGM 0x28cc
31#define MC_IO_PAD_CNTL_D0 0x29d0
32#define MEM_FALL_OUT_CMD (1 << 8)
33#define MC_SEQ_MISC0 0x2a00
34#define MC_SEQ_MISC0_GDDR5_SHIFT 28
35#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
36#define MC_SEQ_MISC0_GDDR5_VALUE 5
37#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
38#define MC_SEQ_IO_DEBUG_DATA 0x2a48
39
40#endif
41
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 23fee54c3b75..fae5e709f270 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -558,10 +558,7 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev)
558 558
559 /* FIXME wait for idle */ 559 /* FIXME wait for idle */
560 560
561 if (rdev->family < CHIP_R600) 561 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
562 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
563 else
564 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
565 562
566 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 563 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
567 case RADEON_PCIE_LC_LINK_WIDTH_X0: 564 case RADEON_PCIE_LC_LINK_WIDTH_X0:
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 279794c391e9..6b50716267c0 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -94,6 +94,7 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
94void r600_gpu_init(struct radeon_device *rdev); 94void r600_gpu_init(struct radeon_device *rdev);
95void r600_fini(struct radeon_device *rdev); 95void r600_fini(struct radeon_device *rdev);
96void r600_irq_disable(struct radeon_device *rdev); 96void r600_irq_disable(struct radeon_device *rdev);
97static void r600_pcie_gen2_enable(struct radeon_device *rdev);
97 98
98/* get temperature in millidegrees */ 99/* get temperature in millidegrees */
99u32 rv6xx_get_temp(struct radeon_device *rdev) 100u32 rv6xx_get_temp(struct radeon_device *rdev)
@@ -2379,6 +2380,9 @@ int r600_startup(struct radeon_device *rdev)
2379{ 2380{
2380 int r; 2381 int r;
2381 2382
2383 /* enable pcie gen2 link */
2384 r600_pcie_gen2_enable(rdev);
2385
2382 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2386 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2383 r = r600_init_microcode(rdev); 2387 r = r600_init_microcode(rdev);
2384 if (r) { 2388 if (r) {
@@ -3531,3 +3535,219 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3531 } else 3535 } else
3532 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 3536 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3533} 3537}
3538
3539void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3540{
3541 u32 link_width_cntl, mask, target_reg;
3542
3543 if (rdev->flags & RADEON_IS_IGP)
3544 return;
3545
3546 if (!(rdev->flags & RADEON_IS_PCIE))
3547 return;
3548
3549 /* x2 cards have a special sequence */
3550 if (ASIC_IS_X2(rdev))
3551 return;
3552
3553 /* FIXME wait for idle */
3554
3555 switch (lanes) {
3556 case 0:
3557 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3558 break;
3559 case 1:
3560 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3561 break;
3562 case 2:
3563 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3564 break;
3565 case 4:
3566 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3567 break;
3568 case 8:
3569 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3570 break;
3571 case 12:
3572 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3573 break;
3574 case 16:
3575 default:
3576 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3577 break;
3578 }
3579
3580 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3581
3582 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3583 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3584 return;
3585
3586 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3587 return;
3588
3589 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3590 RADEON_PCIE_LC_RECONFIG_NOW |
3591 R600_PCIE_LC_RENEGOTIATE_EN |
3592 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3593 link_width_cntl |= mask;
3594
3595 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3596
3597 /* some northbridges can renegotiate the link rather than requiring
3598 * a complete re-config.
3599 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3600 */
3601 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3602 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3603 else
3604 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3605
3606 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3607 RADEON_PCIE_LC_RECONFIG_NOW));
3608
3609 if (rdev->family >= CHIP_RV770)
3610 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3611 else
3612 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3613
3614 /* wait for lane set to complete */
3615 link_width_cntl = RREG32(target_reg);
3616 while (link_width_cntl == 0xffffffff)
3617 link_width_cntl = RREG32(target_reg);
3618
3619}
3620
3621int r600_get_pcie_lanes(struct radeon_device *rdev)
3622{
3623 u32 link_width_cntl;
3624
3625 if (rdev->flags & RADEON_IS_IGP)
3626 return 0;
3627
3628 if (!(rdev->flags & RADEON_IS_PCIE))
3629 return 0;
3630
3631 /* x2 cards have a special sequence */
3632 if (ASIC_IS_X2(rdev))
3633 return 0;
3634
3635 /* FIXME wait for idle */
3636
3637 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3638
3639 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3640 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3641 return 0;
3642 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3643 return 1;
3644 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3645 return 2;
3646 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3647 return 4;
3648 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3649 return 8;
3650 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3651 default:
3652 return 16;
3653 }
3654}
3655
3656static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3657{
3658 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3659 u16 link_cntl2;
3660
3661 if (rdev->flags & RADEON_IS_IGP)
3662 return;
3663
3664 if (!(rdev->flags & RADEON_IS_PCIE))
3665 return;
3666
3667 /* x2 cards have a special sequence */
3668 if (ASIC_IS_X2(rdev))
3669 return;
3670
3671 /* only RV6xx+ chips are supported */
3672 if (rdev->family <= CHIP_R600)
3673 return;
3674
3675 /* 55 nm r6xx asics */
3676 if ((rdev->family == CHIP_RV670) ||
3677 (rdev->family == CHIP_RV620) ||
3678 (rdev->family == CHIP_RV635)) {
3679 /* advertise upconfig capability */
3680 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3681 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3682 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3683 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3684 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3685 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3686 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3687 LC_RECONFIG_ARC_MISSING_ESCAPE);
3688 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3689 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3690 } else {
3691 link_width_cntl |= LC_UPCONFIGURE_DIS;
3692 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3693 }
3694 }
3695
3696 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3697 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3698 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3699
3700 /* 55 nm r6xx asics */
3701 if ((rdev->family == CHIP_RV670) ||
3702 (rdev->family == CHIP_RV620) ||
3703 (rdev->family == CHIP_RV635)) {
3704 WREG32(MM_CFGREGS_CNTL, 0x8);
3705 link_cntl2 = RREG32(0x4088);
3706 WREG32(MM_CFGREGS_CNTL, 0);
3707 /* not supported yet */
3708 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3709 return;
3710 }
3711
3712 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3713 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3714 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3715 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3716 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3717 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3718
3719 tmp = RREG32(0x541c);
3720 WREG32(0x541c, tmp | 0x8);
3721 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3722 link_cntl2 = RREG16(0x4088);
3723 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3724 link_cntl2 |= 0x2;
3725 WREG16(0x4088, link_cntl2);
3726 WREG32(MM_CFGREGS_CNTL, 0);
3727
3728 if ((rdev->family == CHIP_RV670) ||
3729 (rdev->family == CHIP_RV620) ||
3730 (rdev->family == CHIP_RV635)) {
3731 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3732 training_cntl &= ~LC_POINT_7_PLUS_EN;
3733 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3734 } else {
3735 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3736 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3737 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3738 }
3739
3740 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3741 speed_cntl |= LC_GEN2_EN_STRAP;
3742 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3743
3744 } else {
3745 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3746 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3747 if (1)
3748 link_width_cntl |= LC_UPCONFIGURE_DIS;
3749 else
3750 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3751 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3752 }
3753}
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index c89cfa8e0c05..a5d898b4bad2 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -737,6 +737,45 @@
737# define DxGRPH_PFLIP_INT_MASK (1 << 0) 737# define DxGRPH_PFLIP_INT_MASK (1 << 0)
738# define DxGRPH_PFLIP_INT_TYPE (1 << 8) 738# define DxGRPH_PFLIP_INT_TYPE (1 << 8)
739 739
740/* PCIE link stuff */
741#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
742# define LC_POINT_7_PLUS_EN (1 << 6)
743#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
744# define LC_LINK_WIDTH_SHIFT 0
745# define LC_LINK_WIDTH_MASK 0x7
746# define LC_LINK_WIDTH_X0 0
747# define LC_LINK_WIDTH_X1 1
748# define LC_LINK_WIDTH_X2 2
749# define LC_LINK_WIDTH_X4 3
750# define LC_LINK_WIDTH_X8 4
751# define LC_LINK_WIDTH_X16 6
752# define LC_LINK_WIDTH_RD_SHIFT 4
753# define LC_LINK_WIDTH_RD_MASK 0x70
754# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
755# define LC_RECONFIG_NOW (1 << 8)
756# define LC_RENEGOTIATION_SUPPORT (1 << 9)
757# define LC_RENEGOTIATE_EN (1 << 10)
758# define LC_SHORT_RECONFIG_EN (1 << 11)
759# define LC_UPCONFIGURE_SUPPORT (1 << 12)
760# define LC_UPCONFIGURE_DIS (1 << 13)
761#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
762# define LC_GEN2_EN_STRAP (1 << 0)
763# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
764# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
765# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
766# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
767# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
768# define LC_CURRENT_DATA_RATE (1 << 11)
769# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
770# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
771# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
772# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
773#define MM_CFGREGS_CNTL 0x544c
774# define MM_WR_TO_CFG_EN (1 << 3)
775#define LINK_CNTL2 0x88 /* F0 */
776# define TARGET_LINK_SPEED_MASK (0xf << 0)
777# define SELECTABLE_DEEMPHASIS (1 << 6)
778
740/* 779/*
741 * PM4 780 * PM4
742 */ 781 */
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index aff8080026a1..e9486630a467 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -739,6 +739,7 @@ enum radeon_int_thermal_type {
739 THERMAL_TYPE_RV770, 739 THERMAL_TYPE_RV770,
740 THERMAL_TYPE_EVERGREEN, 740 THERMAL_TYPE_EVERGREEN,
741 THERMAL_TYPE_SUMO, 741 THERMAL_TYPE_SUMO,
742 THERMAL_TYPE_NI,
742}; 743};
743 744
744struct radeon_voltage { 745struct radeon_voltage {
@@ -822,6 +823,9 @@ struct radeon_pm {
822 u32 current_sclk; 823 u32 current_sclk;
823 u32 current_mclk; 824 u32 current_mclk;
824 u32 current_vddc; 825 u32 current_vddc;
826 u32 default_sclk;
827 u32 default_mclk;
828 u32 default_vddc;
825 struct radeon_i2c_chan *i2c_bus; 829 struct radeon_i2c_chan *i2c_bus;
826 /* selected pm method */ 830 /* selected pm method */
827 enum radeon_pm_method pm_method; 831 enum radeon_pm_method pm_method;
@@ -1148,6 +1152,7 @@ struct radeon_device {
1148 const struct firmware *me_fw; /* all family ME firmware */ 1152 const struct firmware *me_fw; /* all family ME firmware */
1149 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 1153 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1150 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 1154 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1155 const struct firmware *mc_fw; /* NI MC firmware */
1151 struct r600_blit r600_blit; 1156 struct r600_blit r600_blit;
1152 struct r700_vram_scratch vram_scratch; 1157 struct r700_vram_scratch vram_scratch;
1153 int msi_enabled; /* msi enabled */ 1158 int msi_enabled; /* msi enabled */
@@ -1244,6 +1249,8 @@ static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1244 */ 1249 */
1245#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 1250#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1246#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 1251#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1252#define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
1253#define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
1247#define RREG32(reg) r100_mm_rreg(rdev, (reg)) 1254#define RREG32(reg) r100_mm_rreg(rdev, (reg))
1248#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) 1255#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1249#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) 1256#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
@@ -1317,6 +1324,14 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
1317 (rdev->family == CHIP_RV410) || \ 1324 (rdev->family == CHIP_RV410) || \
1318 (rdev->family == CHIP_RS400) || \ 1325 (rdev->family == CHIP_RS400) || \
1319 (rdev->family == CHIP_RS480)) 1326 (rdev->family == CHIP_RS480))
1327#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1328 (rdev->ddev->pdev->device == 0x9443) || \
1329 (rdev->ddev->pdev->device == 0x944B) || \
1330 (rdev->ddev->pdev->device == 0x9506) || \
1331 (rdev->ddev->pdev->device == 0x9509) || \
1332 (rdev->ddev->pdev->device == 0x950F) || \
1333 (rdev->ddev->pdev->device == 0x689C) || \
1334 (rdev->ddev->pdev->device == 0x689D))
1320#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1335#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1321#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 1336#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1322 (rdev->family == CHIP_RS690) || \ 1337 (rdev->family == CHIP_RS690) || \
@@ -1325,7 +1340,9 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
1325#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1340#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1326#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1341#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1327#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1342#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1328#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM)) 1343#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1344 (rdev->flags & RADEON_IS_IGP))
1345#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1329 1346
1330/* 1347/*
1331 * BIOS helpers. 1348 * BIOS helpers.
@@ -1432,65 +1449,6 @@ extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc
1432extern int radeon_resume_kms(struct drm_device *dev); 1449extern int radeon_resume_kms(struct drm_device *dev);
1433extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 1450extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1434 1451
1435/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1436extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1437extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1438
1439/* rv200,rv250,rv280 */
1440extern void r200_set_safe_registers(struct radeon_device *rdev);
1441
1442/* r300,r350,rv350,rv370,rv380 */
1443extern void r300_set_reg_safe(struct radeon_device *rdev);
1444extern void r300_mc_program(struct radeon_device *rdev);
1445extern void r300_mc_init(struct radeon_device *rdev);
1446extern void r300_clock_startup(struct radeon_device *rdev);
1447extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1448extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1449extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1450extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1451extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1452
1453/* r420,r423,rv410 */
1454extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1455extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1456extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1457extern void r420_pipes_init(struct radeon_device *rdev);
1458
1459/* rv515 */
1460struct rv515_mc_save {
1461 u32 d1vga_control;
1462 u32 d2vga_control;
1463 u32 vga_render_control;
1464 u32 vga_hdp_control;
1465 u32 d1crtc_control;
1466 u32 d2crtc_control;
1467};
1468extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1469extern void rv515_vga_render_disable(struct radeon_device *rdev);
1470extern void rv515_set_safe_registers(struct radeon_device *rdev);
1471extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1472extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1473extern void rv515_clock_startup(struct radeon_device *rdev);
1474extern void rv515_debugfs(struct radeon_device *rdev);
1475extern int rv515_suspend(struct radeon_device *rdev);
1476
1477/* rs400 */
1478extern int rs400_gart_init(struct radeon_device *rdev);
1479extern int rs400_gart_enable(struct radeon_device *rdev);
1480extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1481extern void rs400_gart_disable(struct radeon_device *rdev);
1482extern void rs400_gart_fini(struct radeon_device *rdev);
1483
1484/* rs600 */
1485extern void rs600_set_safe_registers(struct radeon_device *rdev);
1486extern int rs600_irq_set(struct radeon_device *rdev);
1487extern void rs600_irq_disable(struct radeon_device *rdev);
1488
1489/* rs690, rs740 */
1490extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1491 struct drm_display_mode *mode1,
1492 struct drm_display_mode *mode2);
1493
1494/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */ 1452/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1495extern bool r600_card_posted(struct radeon_device *rdev); 1453extern bool r600_card_posted(struct radeon_device *rdev);
1496extern void r600_cp_stop(struct radeon_device *rdev); 1454extern void r600_cp_stop(struct radeon_device *rdev);
@@ -1545,6 +1503,9 @@ extern int evergreen_irq_set(struct radeon_device *rdev);
1545extern int evergreen_blit_init(struct radeon_device *rdev); 1503extern int evergreen_blit_init(struct radeon_device *rdev);
1546extern void evergreen_blit_fini(struct radeon_device *rdev); 1504extern void evergreen_blit_fini(struct radeon_device *rdev);
1547 1505
1506extern int ni_init_microcode(struct radeon_device *rdev);
1507extern int btc_mc_load_microcode(struct radeon_device *rdev);
1508
1548/* radeon_acpi.c */ 1509/* radeon_acpi.c */
1549#if defined(CONFIG_ACPI) 1510#if defined(CONFIG_ACPI)
1550extern int radeon_acpi_init(struct radeon_device *rdev); 1511extern int radeon_acpi_init(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 3d73fe484f42..3a1b16186224 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -94,7 +94,7 @@ static void radeon_register_accessor_init(struct radeon_device *rdev)
94 rdev->mc_rreg = &rs600_mc_rreg; 94 rdev->mc_rreg = &rs600_mc_rreg;
95 rdev->mc_wreg = &rs600_mc_wreg; 95 rdev->mc_wreg = &rs600_mc_wreg;
96 } 96 }
97 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_RV740)) { 97 if ((rdev->family >= CHIP_R600) && (rdev->family <= CHIP_HEMLOCK)) {
98 rdev->pciep_rreg = &r600_pciep_rreg; 98 rdev->pciep_rreg = &r600_pciep_rreg;
99 rdev->pciep_wreg = &r600_pciep_wreg; 99 rdev->pciep_wreg = &r600_pciep_wreg;
100 } 100 }
@@ -631,8 +631,8 @@ static struct radeon_asic r600_asic = {
631 .set_engine_clock = &radeon_atom_set_engine_clock, 631 .set_engine_clock = &radeon_atom_set_engine_clock,
632 .get_memory_clock = &radeon_atom_get_memory_clock, 632 .get_memory_clock = &radeon_atom_get_memory_clock,
633 .set_memory_clock = &radeon_atom_set_memory_clock, 633 .set_memory_clock = &radeon_atom_set_memory_clock,
634 .get_pcie_lanes = &rv370_get_pcie_lanes, 634 .get_pcie_lanes = &r600_get_pcie_lanes,
635 .set_pcie_lanes = NULL, 635 .set_pcie_lanes = &r600_set_pcie_lanes,
636 .set_clock_gating = NULL, 636 .set_clock_gating = NULL,
637 .set_surface_reg = r600_set_surface_reg, 637 .set_surface_reg = r600_set_surface_reg,
638 .clear_surface_reg = r600_clear_surface_reg, 638 .clear_surface_reg = r600_clear_surface_reg,
@@ -725,8 +725,8 @@ static struct radeon_asic rv770_asic = {
725 .set_engine_clock = &radeon_atom_set_engine_clock, 725 .set_engine_clock = &radeon_atom_set_engine_clock,
726 .get_memory_clock = &radeon_atom_get_memory_clock, 726 .get_memory_clock = &radeon_atom_get_memory_clock,
727 .set_memory_clock = &radeon_atom_set_memory_clock, 727 .set_memory_clock = &radeon_atom_set_memory_clock,
728 .get_pcie_lanes = &rv370_get_pcie_lanes, 728 .get_pcie_lanes = &r600_get_pcie_lanes,
729 .set_pcie_lanes = NULL, 729 .set_pcie_lanes = &r600_set_pcie_lanes,
730 .set_clock_gating = &radeon_atom_set_clock_gating, 730 .set_clock_gating = &radeon_atom_set_clock_gating,
731 .set_surface_reg = r600_set_surface_reg, 731 .set_surface_reg = r600_set_surface_reg,
732 .clear_surface_reg = r600_clear_surface_reg, 732 .clear_surface_reg = r600_clear_surface_reg,
@@ -772,8 +772,8 @@ static struct radeon_asic evergreen_asic = {
772 .set_engine_clock = &radeon_atom_set_engine_clock, 772 .set_engine_clock = &radeon_atom_set_engine_clock,
773 .get_memory_clock = &radeon_atom_get_memory_clock, 773 .get_memory_clock = &radeon_atom_get_memory_clock,
774 .set_memory_clock = &radeon_atom_set_memory_clock, 774 .set_memory_clock = &radeon_atom_set_memory_clock,
775 .get_pcie_lanes = NULL, 775 .get_pcie_lanes = &r600_get_pcie_lanes,
776 .set_pcie_lanes = NULL, 776 .set_pcie_lanes = &r600_set_pcie_lanes,
777 .set_clock_gating = NULL, 777 .set_clock_gating = NULL,
778 .set_surface_reg = r600_set_surface_reg, 778 .set_surface_reg = r600_set_surface_reg,
779 .clear_surface_reg = r600_clear_surface_reg, 779 .clear_surface_reg = r600_clear_surface_reg,
@@ -836,6 +836,52 @@ static struct radeon_asic sumo_asic = {
836 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 836 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
837}; 837};
838 838
839static struct radeon_asic btc_asic = {
840 .init = &evergreen_init,
841 .fini = &evergreen_fini,
842 .suspend = &evergreen_suspend,
843 .resume = &evergreen_resume,
844 .cp_commit = &r600_cp_commit,
845 .gpu_is_lockup = &evergreen_gpu_is_lockup,
846 .asic_reset = &evergreen_asic_reset,
847 .vga_set_state = &r600_vga_set_state,
848 .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
849 .gart_set_page = &rs600_gart_set_page,
850 .ring_test = &r600_ring_test,
851 .ring_ib_execute = &r600_ring_ib_execute,
852 .irq_set = &evergreen_irq_set,
853 .irq_process = &evergreen_irq_process,
854 .get_vblank_counter = &evergreen_get_vblank_counter,
855 .fence_ring_emit = &r600_fence_ring_emit,
856 .cs_parse = &evergreen_cs_parse,
857 .copy_blit = &evergreen_copy_blit,
858 .copy_dma = &evergreen_copy_blit,
859 .copy = &evergreen_copy_blit,
860 .get_engine_clock = &radeon_atom_get_engine_clock,
861 .set_engine_clock = &radeon_atom_set_engine_clock,
862 .get_memory_clock = &radeon_atom_get_memory_clock,
863 .set_memory_clock = &radeon_atom_set_memory_clock,
864 .get_pcie_lanes = NULL,
865 .set_pcie_lanes = NULL,
866 .set_clock_gating = NULL,
867 .set_surface_reg = r600_set_surface_reg,
868 .clear_surface_reg = r600_clear_surface_reg,
869 .bandwidth_update = &evergreen_bandwidth_update,
870 .hpd_init = &evergreen_hpd_init,
871 .hpd_fini = &evergreen_hpd_fini,
872 .hpd_sense = &evergreen_hpd_sense,
873 .hpd_set_polarity = &evergreen_hpd_set_polarity,
874 .gui_idle = &r600_gui_idle,
875 .pm_misc = &evergreen_pm_misc,
876 .pm_prepare = &evergreen_pm_prepare,
877 .pm_finish = &evergreen_pm_finish,
878 .pm_init_profile = &r600_pm_init_profile,
879 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
880 .pre_page_flip = &evergreen_pre_page_flip,
881 .page_flip = &evergreen_page_flip,
882 .post_page_flip = &evergreen_post_page_flip,
883};
884
839int radeon_asic_init(struct radeon_device *rdev) 885int radeon_asic_init(struct radeon_device *rdev)
840{ 886{
841 radeon_register_accessor_init(rdev); 887 radeon_register_accessor_init(rdev);
@@ -923,6 +969,11 @@ int radeon_asic_init(struct radeon_device *rdev)
923 case CHIP_PALM: 969 case CHIP_PALM:
924 rdev->asic = &sumo_asic; 970 rdev->asic = &sumo_asic;
925 break; 971 break;
972 case CHIP_BARTS:
973 case CHIP_TURKS:
974 case CHIP_CAICOS:
975 rdev->asic = &btc_asic;
976 break;
926 default: 977 default:
927 /* FIXME: not supported yet */ 978 /* FIXME: not supported yet */
928 return -EINVAL; 979 return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 4970eda1bd41..e01f07718539 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -102,6 +102,11 @@ int r100_pci_gart_enable(struct radeon_device *rdev);
102void r100_pci_gart_disable(struct radeon_device *rdev); 102void r100_pci_gart_disable(struct radeon_device *rdev);
103int r100_debugfs_mc_info_init(struct radeon_device *rdev); 103int r100_debugfs_mc_info_init(struct radeon_device *rdev);
104int r100_gui_wait_for_idle(struct radeon_device *rdev); 104int r100_gui_wait_for_idle(struct radeon_device *rdev);
105void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup,
106 struct radeon_cp *cp);
107bool r100_gpu_cp_is_lockup(struct radeon_device *rdev,
108 struct r100_gpu_lockup *lockup,
109 struct radeon_cp *cp);
105void r100_ib_fini(struct radeon_device *rdev); 110void r100_ib_fini(struct radeon_device *rdev);
106int r100_ib_init(struct radeon_device *rdev); 111int r100_ib_init(struct radeon_device *rdev);
107void r100_irq_disable(struct radeon_device *rdev); 112void r100_irq_disable(struct radeon_device *rdev);
@@ -138,10 +143,11 @@ extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
138 * r200,rv250,rs300,rv280 143 * r200,rv250,rs300,rv280
139 */ 144 */
140extern int r200_copy_dma(struct radeon_device *rdev, 145extern int r200_copy_dma(struct radeon_device *rdev,
141 uint64_t src_offset, 146 uint64_t src_offset,
142 uint64_t dst_offset, 147 uint64_t dst_offset,
143 unsigned num_pages, 148 unsigned num_pages,
144 struct radeon_fence *fence); 149 struct radeon_fence *fence);
150void r200_set_safe_registers(struct radeon_device *rdev);
145 151
146/* 152/*
147 * r300,r350,rv350,rv380 153 * r300,r350,rv350,rv380
@@ -162,6 +168,15 @@ extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
162extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 168extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
163extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 169extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
164extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 170extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
171extern void r300_set_reg_safe(struct radeon_device *rdev);
172extern void r300_mc_program(struct radeon_device *rdev);
173extern void r300_mc_init(struct radeon_device *rdev);
174extern void r300_clock_startup(struct radeon_device *rdev);
175extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
176extern int rv370_pcie_gart_init(struct radeon_device *rdev);
177extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
178extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
179extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
165 180
166/* 181/*
167 * r420,r423,rv410 182 * r420,r423,rv410
@@ -171,6 +186,10 @@ extern void r420_fini(struct radeon_device *rdev);
171extern int r420_suspend(struct radeon_device *rdev); 186extern int r420_suspend(struct radeon_device *rdev);
172extern int r420_resume(struct radeon_device *rdev); 187extern int r420_resume(struct radeon_device *rdev);
173extern void r420_pm_init_profile(struct radeon_device *rdev); 188extern void r420_pm_init_profile(struct radeon_device *rdev);
189extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
190extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
191extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
192extern void r420_pipes_init(struct radeon_device *rdev);
174 193
175/* 194/*
176 * rs400,rs480 195 * rs400,rs480
@@ -183,6 +202,12 @@ void rs400_gart_tlb_flush(struct radeon_device *rdev);
183int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 202int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
184uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 203uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
185void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 204void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
205int rs400_gart_init(struct radeon_device *rdev);
206int rs400_gart_enable(struct radeon_device *rdev);
207void rs400_gart_adjust_size(struct radeon_device *rdev);
208void rs400_gart_disable(struct radeon_device *rdev);
209void rs400_gart_fini(struct radeon_device *rdev);
210
186 211
187/* 212/*
188 * rs600. 213 * rs600.
@@ -194,6 +219,7 @@ extern int rs600_suspend(struct radeon_device *rdev);
194extern int rs600_resume(struct radeon_device *rdev); 219extern int rs600_resume(struct radeon_device *rdev);
195int rs600_irq_set(struct radeon_device *rdev); 220int rs600_irq_set(struct radeon_device *rdev);
196int rs600_irq_process(struct radeon_device *rdev); 221int rs600_irq_process(struct radeon_device *rdev);
222void rs600_irq_disable(struct radeon_device *rdev);
197u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 223u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
198void rs600_gart_tlb_flush(struct radeon_device *rdev); 224void rs600_gart_tlb_flush(struct radeon_device *rdev);
199int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 225int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
@@ -211,6 +237,8 @@ extern void rs600_pm_finish(struct radeon_device *rdev);
211extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 237extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
212extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 238extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
213extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 239extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
240void rs600_set_safe_registers(struct radeon_device *rdev);
241
214 242
215/* 243/*
216 * rs690,rs740 244 * rs690,rs740
@@ -222,10 +250,21 @@ int rs690_suspend(struct radeon_device *rdev);
222uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 250uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
223void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 251void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
224void rs690_bandwidth_update(struct radeon_device *rdev); 252void rs690_bandwidth_update(struct radeon_device *rdev);
253void rs690_line_buffer_adjust(struct radeon_device *rdev,
254 struct drm_display_mode *mode1,
255 struct drm_display_mode *mode2);
225 256
226/* 257/*
227 * rv515 258 * rv515
228 */ 259 */
260struct rv515_mc_save {
261 u32 d1vga_control;
262 u32 d2vga_control;
263 u32 vga_render_control;
264 u32 vga_hdp_control;
265 u32 d1crtc_control;
266 u32 d2crtc_control;
267};
229int rv515_init(struct radeon_device *rdev); 268int rv515_init(struct radeon_device *rdev);
230void rv515_fini(struct radeon_device *rdev); 269void rv515_fini(struct radeon_device *rdev);
231uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 270uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
@@ -236,6 +275,14 @@ void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
236void rv515_bandwidth_update(struct radeon_device *rdev); 275void rv515_bandwidth_update(struct radeon_device *rdev);
237int rv515_resume(struct radeon_device *rdev); 276int rv515_resume(struct radeon_device *rdev);
238int rv515_suspend(struct radeon_device *rdev); 277int rv515_suspend(struct radeon_device *rdev);
278void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
279void rv515_vga_render_disable(struct radeon_device *rdev);
280void rv515_set_safe_registers(struct radeon_device *rdev);
281void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
282void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
283void rv515_clock_startup(struct radeon_device *rdev);
284void rv515_debugfs(struct radeon_device *rdev);
285
239 286
240/* 287/*
241 * r520,rv530,rv560,rv570,r580 288 * r520,rv530,rv560,rv570,r580
@@ -284,6 +331,8 @@ extern void r600_pm_misc(struct radeon_device *rdev);
284extern void r600_pm_init_profile(struct radeon_device *rdev); 331extern void r600_pm_init_profile(struct radeon_device *rdev);
285extern void rs780_pm_init_profile(struct radeon_device *rdev); 332extern void rs780_pm_init_profile(struct radeon_device *rdev);
286extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 333extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
334extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
335extern int r600_get_pcie_lanes(struct radeon_device *rdev);
287 336
288/* 337/*
289 * rv770,rv730,rv710,rv740 338 * rv770,rv730,rv710,rv740
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index e4f7e3e82a50..1573202a6418 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -37,7 +37,7 @@ radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
37extern void radeon_link_encoder_connector(struct drm_device *dev); 37extern void radeon_link_encoder_connector(struct drm_device *dev);
38extern void 38extern void
39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 39radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
40 uint32_t supported_device); 40 uint32_t supported_device, u16 caps);
41 41
42/* from radeon_connector.c */ 42/* from radeon_connector.c */
43extern void 43extern void
@@ -537,6 +537,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
537 u16 size, data_offset; 537 u16 size, data_offset;
538 u8 frev, crev; 538 u8 frev, crev;
539 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 539 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
540 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
540 ATOM_OBJECT_TABLE *router_obj; 541 ATOM_OBJECT_TABLE *router_obj;
541 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 542 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
542 ATOM_OBJECT_HEADER *obj_header; 543 ATOM_OBJECT_HEADER *obj_header;
@@ -561,6 +562,9 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
561 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 562 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
562 (ctx->bios + data_offset + 563 (ctx->bios + data_offset +
563 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 564 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
565 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
566 (ctx->bios + data_offset +
567 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
564 router_obj = (ATOM_OBJECT_TABLE *) 568 router_obj = (ATOM_OBJECT_TABLE *)
565 (ctx->bios + data_offset + 569 (ctx->bios + data_offset +
566 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 570 le16_to_cpu(obj_header->usRouterObjectTableOffset));
@@ -666,14 +670,35 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
666 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 670 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
667 671
668 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 672 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
669 u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]); 673 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
670 674 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
671 radeon_add_atom_encoder(dev, 675 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
672 encoder_obj, 676 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
673 le16_to_cpu 677 (ctx->bios + data_offset +
674 (path-> 678 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
675 usDeviceTag)); 679 ATOM_ENCODER_CAP_RECORD *cap_record;
680 u16 caps = 0;
676 681
682 while (record->ucRecordType > 0 &&
683 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
684 switch (record->ucRecordType) {
685 case ATOM_ENCODER_CAP_RECORD_TYPE:
686 cap_record =(ATOM_ENCODER_CAP_RECORD *)
687 record;
688 caps = le16_to_cpu(cap_record->usEncoderCap);
689 break;
690 }
691 record = (ATOM_COMMON_RECORD_HEADER *)
692 ((char *)record + record->ucRecordSize);
693 }
694 radeon_add_atom_encoder(dev,
695 encoder_obj,
696 le16_to_cpu
697 (path->
698 usDeviceTag),
699 caps);
700 }
701 }
677 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 702 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
678 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 703 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
679 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 704 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
@@ -1007,7 +1032,8 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
1007 radeon_get_encoder_enum(dev, 1032 radeon_get_encoder_enum(dev,
1008 (1 << i), 1033 (1 << i),
1009 dac), 1034 dac),
1010 (1 << i)); 1035 (1 << i),
1036 0);
1011 else 1037 else
1012 radeon_add_legacy_encoder(dev, 1038 radeon_add_legacy_encoder(dev,
1013 radeon_get_encoder_enum(dev, 1039 radeon_get_encoder_enum(dev,
@@ -1086,6 +1112,7 @@ union firmware_info {
1086 ATOM_FIRMWARE_INFO_V1_3 info_13; 1112 ATOM_FIRMWARE_INFO_V1_3 info_13;
1087 ATOM_FIRMWARE_INFO_V1_4 info_14; 1113 ATOM_FIRMWARE_INFO_V1_4 info_14;
1088 ATOM_FIRMWARE_INFO_V2_1 info_21; 1114 ATOM_FIRMWARE_INFO_V2_1 info_21;
1115 ATOM_FIRMWARE_INFO_V2_2 info_22;
1089}; 1116};
1090 1117
1091bool radeon_atom_get_clock_info(struct drm_device *dev) 1118bool radeon_atom_get_clock_info(struct drm_device *dev)
@@ -1160,8 +1187,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
1160 *p2pll = *p1pll; 1187 *p2pll = *p1pll;
1161 1188
1162 /* system clock */ 1189 /* system clock */
1163 spll->reference_freq = 1190 if (ASIC_IS_DCE4(rdev))
1164 le16_to_cpu(firmware_info->info.usReferenceClock); 1191 spll->reference_freq =
1192 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1193 else
1194 spll->reference_freq =
1195 le16_to_cpu(firmware_info->info.usReferenceClock);
1165 spll->reference_div = 0; 1196 spll->reference_div = 0;
1166 1197
1167 spll->pll_out_min = 1198 spll->pll_out_min =
@@ -1183,8 +1214,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
1183 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1214 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1184 1215
1185 /* memory clock */ 1216 /* memory clock */
1186 mpll->reference_freq = 1217 if (ASIC_IS_DCE4(rdev))
1187 le16_to_cpu(firmware_info->info.usReferenceClock); 1218 mpll->reference_freq =
1219 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1220 else
1221 mpll->reference_freq =
1222 le16_to_cpu(firmware_info->info.usReferenceClock);
1188 mpll->reference_div = 0; 1223 mpll->reference_div = 0;
1189 1224
1190 mpll->pll_out_min = 1225 mpll->pll_out_min =
@@ -1213,8 +1248,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
1213 if (ASIC_IS_DCE4(rdev)) { 1248 if (ASIC_IS_DCE4(rdev)) {
1214 rdev->clock.default_dispclk = 1249 rdev->clock.default_dispclk =
1215 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1250 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1216 if (rdev->clock.default_dispclk == 0) 1251 if (rdev->clock.default_dispclk == 0) {
1217 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1252 if (ASIC_IS_DCE5(rdev))
1253 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1254 else
1255 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1256 }
1218 rdev->clock.dp_extclk = 1257 rdev->clock.dp_extclk =
1219 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1258 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1220 } 1259 }
@@ -1852,6 +1891,7 @@ static const char *pp_lib_thermal_controller_names[] = {
1852 "Evergreen", 1891 "Evergreen",
1853 "emc2103", 1892 "emc2103",
1854 "Sumo", 1893 "Sumo",
1894 "Northern Islands",
1855}; 1895};
1856 1896
1857union power_info { 1897union power_info {
@@ -2115,6 +2155,11 @@ static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
2115 (controller->ucFanParameters & 2155 (controller->ucFanParameters &
2116 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2156 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2117 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2157 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2158 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2159 DRM_INFO("Internal thermal controller %s fan control\n",
2160 (controller->ucFanParameters &
2161 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2162 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2118 } else if ((controller->ucType == 2163 } else if ((controller->ucType ==
2119 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || 2164 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2120 (controller->ucType == 2165 (controller->ucType ==
@@ -2204,15 +2249,22 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde
2204 rdev->pm.default_power_state_index = state_index; 2249 rdev->pm.default_power_state_index = state_index;
2205 rdev->pm.power_state[state_index].default_clock_mode = 2250 rdev->pm.power_state[state_index].default_clock_mode =
2206 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2251 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2207 /* patch the table values with the default slck/mclk from firmware info */ 2252 if (ASIC_IS_DCE5(rdev)) {
2208 for (j = 0; j < mode_index; j++) { 2253 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2209 rdev->pm.power_state[state_index].clock_info[j].mclk = 2254 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2210 rdev->clock.default_mclk; 2255 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2211 rdev->pm.power_state[state_index].clock_info[j].sclk = 2256 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2212 rdev->clock.default_sclk; 2257 } else {
2213 if (vddc) 2258 /* patch the table values with the default slck/mclk from firmware info */
2214 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2259 for (j = 0; j < mode_index; j++) {
2215 vddc; 2260 rdev->pm.power_state[state_index].clock_info[j].mclk =
2261 rdev->clock.default_mclk;
2262 rdev->pm.power_state[state_index].clock_info[j].sclk =
2263 rdev->clock.default_sclk;
2264 if (vddc)
2265 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2266 vddc;
2267 }
2216 } 2268 }
2217 } 2269 }
2218} 2270}
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 8f2c7b50dcf5..1aba85cad1a8 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -131,6 +131,45 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
131 return true; 131 return true;
132} 132}
133 133
134static bool ni_read_disabled_bios(struct radeon_device *rdev)
135{
136 u32 bus_cntl;
137 u32 d1vga_control;
138 u32 d2vga_control;
139 u32 vga_render_control;
140 u32 rom_cntl;
141 bool r;
142
143 bus_cntl = RREG32(R600_BUS_CNTL);
144 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
145 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
146 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
147 rom_cntl = RREG32(R600_ROM_CNTL);
148
149 /* enable the rom */
150 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
151 /* Disable VGA mode */
152 WREG32(AVIVO_D1VGA_CONTROL,
153 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
154 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
155 WREG32(AVIVO_D2VGA_CONTROL,
156 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
157 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
158 WREG32(AVIVO_VGA_RENDER_CONTROL,
159 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
160 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
161
162 r = radeon_read_bios(rdev);
163
164 /* restore regs */
165 WREG32(R600_BUS_CNTL, bus_cntl);
166 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
167 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
168 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
169 WREG32(R600_ROM_CNTL, rom_cntl);
170 return r;
171}
172
134static bool r700_read_disabled_bios(struct radeon_device *rdev) 173static bool r700_read_disabled_bios(struct radeon_device *rdev)
135{ 174{
136 uint32_t viph_control; 175 uint32_t viph_control;
@@ -416,6 +455,8 @@ static bool radeon_read_disabled_bios(struct radeon_device *rdev)
416{ 455{
417 if (rdev->flags & RADEON_IS_IGP) 456 if (rdev->flags & RADEON_IS_IGP)
418 return igp_read_bios_from_vram(rdev); 457 return igp_read_bios_from_vram(rdev);
458 else if (rdev->family >= CHIP_BARTS)
459 return ni_read_disabled_bios(rdev);
419 else if (rdev->family >= CHIP_RV770) 460 else if (rdev->family >= CHIP_RV770)
420 return r700_read_disabled_bios(rdev); 461 return r700_read_disabled_bios(rdev);
421 else if (rdev->family >= CHIP_R600) 462 else if (rdev->family >= CHIP_R600)
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 44cf0d707006..26091d602b84 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -82,6 +82,9 @@ static const char radeon_family_name[][16] = {
82 "CYPRESS", 82 "CYPRESS",
83 "HEMLOCK", 83 "HEMLOCK",
84 "PALM", 84 "PALM",
85 "BARTS",
86 "TURKS",
87 "CAICOS",
85 "LAST", 88 "LAST",
86}; 89};
87 90
@@ -225,6 +228,11 @@ int radeon_wb_init(struct radeon_device *rdev)
225 rdev->wb.use_event = true; 228 rdev->wb.use_event = true;
226 } 229 }
227 } 230 }
231 /* always use writeback/events on NI */
232 if (ASIC_IS_DCE5(rdev)) {
233 rdev->wb.enabled = true;
234 rdev->wb.use_event = true;
235 }
228 236
229 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 237 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
230 238
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index acebbc76c2f9..d26dabf878d9 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -68,7 +68,7 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id); 68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69} 69}
70 70
71static void evergreen_crtc_load_lut(struct drm_crtc *crtc) 71static void dce4_crtc_load_lut(struct drm_crtc *crtc)
72{ 72{
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev; 74 struct drm_device *dev = crtc->dev;
@@ -98,6 +98,66 @@ static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
98 } 98 }
99} 99}
100 100
101static void dce5_crtc_load_lut(struct drm_crtc *crtc)
102{
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
106 int i;
107
108 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
109
110 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
111 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
112 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
113 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
114 NI_GRPH_PRESCALE_BYPASS);
115 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
116 NI_OVL_PRESCALE_BYPASS);
117 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
118 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
119 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
120
121 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
122
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
124 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
125 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
126
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
128 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
129 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
130
131 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
132 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
133
134 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
135 for (i = 0; i < 256; i++) {
136 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
137 (radeon_crtc->lut_r[i] << 20) |
138 (radeon_crtc->lut_g[i] << 10) |
139 (radeon_crtc->lut_b[i] << 0));
140 }
141
142 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
143 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
147 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
148 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
149 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
150 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
151 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
152 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
153 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
154 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
155 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
156 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
157 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
158
159}
160
101static void legacy_crtc_load_lut(struct drm_crtc *crtc) 161static void legacy_crtc_load_lut(struct drm_crtc *crtc)
102{ 162{
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 163 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
@@ -130,8 +190,10 @@ void radeon_crtc_load_lut(struct drm_crtc *crtc)
130 if (!crtc->enabled) 190 if (!crtc->enabled)
131 return; 191 return;
132 192
133 if (ASIC_IS_DCE4(rdev)) 193 if (ASIC_IS_DCE5(rdev))
134 evergreen_crtc_load_lut(crtc); 194 dce5_crtc_load_lut(crtc);
195 else if (ASIC_IS_DCE4(rdev))
196 dce4_crtc_load_lut(crtc);
135 else if (ASIC_IS_AVIVO(rdev)) 197 else if (ASIC_IS_AVIVO(rdev))
136 avivo_crtc_load_lut(crtc); 198 avivo_crtc_load_lut(crtc);
137 else 199 else
@@ -1119,7 +1181,10 @@ int radeon_modeset_init(struct radeon_device *rdev)
1119 1181
1120 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs; 1182 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1121 1183
1122 if (ASIC_IS_AVIVO(rdev)) { 1184 if (ASIC_IS_DCE5(rdev)) {
1185 rdev->ddev->mode_config.max_width = 16384;
1186 rdev->ddev->mode_config.max_height = 16384;
1187 } else if (ASIC_IS_AVIVO(rdev)) {
1123 rdev->ddev->mode_config.max_width = 8192; 1188 rdev->ddev->mode_config.max_width = 8192;
1124 rdev->ddev->mode_config.max_height = 8192; 1189 rdev->ddev->mode_config.max_height = 8192;
1125 } else { 1190 } else {
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 55b84b8e6b29..e7a948f60587 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -712,7 +712,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
712 * - 2 DIG encoder blocks. 712 * - 2 DIG encoder blocks.
713 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 713 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
714 * 714 *
715 * DCE 4.0 715 * DCE 4.0/5.0
716 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 716 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
717 * Supports up to 6 digital outputs 717 * Supports up to 6 digital outputs
718 * - 6 DIG encoder blocks. 718 * - 6 DIG encoder blocks.
@@ -743,6 +743,7 @@ union dig_encoder_control {
743 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 743 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
744 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 744 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
745 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 745 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
746 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
746}; 747};
747 748
748void 749void
@@ -758,6 +759,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
758 uint8_t frev, crev; 759 uint8_t frev, crev;
759 int dp_clock = 0; 760 int dp_clock = 0;
760 int dp_lane_count = 0; 761 int dp_lane_count = 0;
762 int hpd_id = RADEON_HPD_NONE;
761 763
762 if (connector) { 764 if (connector) {
763 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 765 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -766,6 +768,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
766 768
767 dp_clock = dig_connector->dp_clock; 769 dp_clock = dig_connector->dp_clock;
768 dp_lane_count = dig_connector->dp_lane_count; 770 dp_lane_count = dig_connector->dp_lane_count;
771 hpd_id = radeon_connector->hpd.hpd;
769 } 772 }
770 773
771 /* no dig encoder assigned */ 774 /* no dig encoder assigned */
@@ -790,19 +793,36 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
790 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 793 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
791 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 794 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
792 795
793 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) { 796 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
794 if (dp_clock == 270000) 797 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
795 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
796 args.v1.ucLaneNum = dp_lane_count; 798 args.v1.ucLaneNum = dp_lane_count;
797 } else if (radeon_encoder->pixel_clock > 165000) 799 else if (radeon_encoder->pixel_clock > 165000)
798 args.v1.ucLaneNum = 8; 800 args.v1.ucLaneNum = 8;
799 else 801 else
800 args.v1.ucLaneNum = 4; 802 args.v1.ucLaneNum = 4;
801 803
802 if (ASIC_IS_DCE4(rdev)) { 804 if (ASIC_IS_DCE5(rdev)) {
805 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
806 (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST)) {
807 if (dp_clock == 270000)
808 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
809 else if (dp_clock == 540000)
810 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
811 }
812 args.v4.acConfig.ucDigSel = dig->dig_encoder;
813 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
814 if (hpd_id == RADEON_HPD_NONE)
815 args.v4.ucHPD_ID = 0;
816 else
817 args.v4.ucHPD_ID = hpd_id + 1;
818 } else if (ASIC_IS_DCE4(rdev)) {
819 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
820 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
803 args.v3.acConfig.ucDigSel = dig->dig_encoder; 821 args.v3.acConfig.ucDigSel = dig->dig_encoder;
804 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; 822 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
805 } else { 823 } else {
824 if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
825 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
806 switch (radeon_encoder->encoder_id) { 826 switch (radeon_encoder->encoder_id) {
807 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 827 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
808 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 828 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
@@ -829,6 +849,7 @@ union dig_transmitter_control {
829 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 849 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
830 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 850 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
831 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 851 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
852 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
832}; 853};
833 854
834void 855void
@@ -923,10 +944,18 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
923 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 944 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
924 pll_id = radeon_crtc->pll_id; 945 pll_id = radeon_crtc->pll_id;
925 } 946 }
926 if (is_dp && rdev->clock.dp_extclk) 947
927 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 948 if (ASIC_IS_DCE5(rdev)) {
928 else 949 if (is_dp && rdev->clock.dp_extclk)
929 args.v3.acConfig.ucRefClkSource = pll_id; 950 args.v4.acConfig.ucRefClkSource = 3; /* external src */
951 else
952 args.v4.acConfig.ucRefClkSource = pll_id;
953 } else {
954 if (is_dp && rdev->clock.dp_extclk)
955 args.v3.acConfig.ucRefClkSource = 2; /* external src */
956 else
957 args.v3.acConfig.ucRefClkSource = pll_id;
958 }
930 959
931 switch (radeon_encoder->encoder_id) { 960 switch (radeon_encoder->encoder_id) {
932 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 961 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
@@ -1198,6 +1227,8 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1198 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1227 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1199 int index = 0; 1228 int index = 0;
1200 bool is_dig = false; 1229 bool is_dig = false;
1230 bool is_dce5_dac = false;
1231 bool is_dce5_dvo = false;
1201 1232
1202 memset(&args, 0, sizeof(args)); 1233 memset(&args, 0, sizeof(args));
1203 1234
@@ -1220,7 +1251,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1220 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1251 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1221 break; 1252 break;
1222 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1253 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1223 if (ASIC_IS_DCE3(rdev)) 1254 if (ASIC_IS_DCE5(rdev))
1255 is_dce5_dvo = true;
1256 else if (ASIC_IS_DCE3(rdev))
1224 is_dig = true; 1257 is_dig = true;
1225 else 1258 else
1226 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1259 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
@@ -1236,12 +1269,16 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1236 break; 1269 break;
1237 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1270 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1238 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1271 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1239 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1272 if (ASIC_IS_DCE5(rdev))
1240 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1273 is_dce5_dac = true;
1241 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1274 else {
1242 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1275 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1243 else 1276 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1244 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1277 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1278 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1279 else
1280 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1281 }
1245 break; 1282 break;
1246 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1283 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1247 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1284 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
@@ -1300,6 +1337,28 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1300 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1337 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1301 break; 1338 break;
1302 } 1339 }
1340 } else if (is_dce5_dac) {
1341 switch (mode) {
1342 case DRM_MODE_DPMS_ON:
1343 atombios_dac_setup(encoder, ATOM_ENABLE);
1344 break;
1345 case DRM_MODE_DPMS_STANDBY:
1346 case DRM_MODE_DPMS_SUSPEND:
1347 case DRM_MODE_DPMS_OFF:
1348 atombios_dac_setup(encoder, ATOM_DISABLE);
1349 break;
1350 }
1351 } else if (is_dce5_dvo) {
1352 switch (mode) {
1353 case DRM_MODE_DPMS_ON:
1354 atombios_dvo_setup(encoder, ATOM_ENABLE);
1355 break;
1356 case DRM_MODE_DPMS_STANDBY:
1357 case DRM_MODE_DPMS_SUSPEND:
1358 case DRM_MODE_DPMS_OFF:
1359 atombios_dvo_setup(encoder, ATOM_DISABLE);
1360 break;
1361 }
1303 } else { 1362 } else {
1304 switch (mode) { 1363 switch (mode) {
1305 case DRM_MODE_DPMS_ON: 1364 case DRM_MODE_DPMS_ON:
@@ -1329,7 +1388,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1329 switch (mode) { 1388 switch (mode) {
1330 case DRM_MODE_DPMS_ON: 1389 case DRM_MODE_DPMS_ON:
1331 default: 1390 default:
1332 if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP)) 1391 if (ASIC_IS_DCE41(rdev))
1333 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT; 1392 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1334 else 1393 else
1335 action = ATOM_ENABLE; 1394 action = ATOM_ENABLE;
@@ -1337,7 +1396,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1337 case DRM_MODE_DPMS_STANDBY: 1396 case DRM_MODE_DPMS_STANDBY:
1338 case DRM_MODE_DPMS_SUSPEND: 1397 case DRM_MODE_DPMS_SUSPEND:
1339 case DRM_MODE_DPMS_OFF: 1398 case DRM_MODE_DPMS_OFF:
1340 if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP)) 1399 if (ASIC_IS_DCE41(rdev))
1341 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT; 1400 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1342 else 1401 else
1343 action = ATOM_DISABLE; 1402 action = ATOM_DISABLE;
@@ -1529,6 +1588,7 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1529 struct radeon_encoder_atom_dig *dig; 1588 struct radeon_encoder_atom_dig *dig;
1530 uint32_t dig_enc_in_use = 0; 1589 uint32_t dig_enc_in_use = 0;
1531 1590
1591 /* DCE4/5 */
1532 if (ASIC_IS_DCE4(rdev)) { 1592 if (ASIC_IS_DCE4(rdev)) {
1533 dig = radeon_encoder->enc_priv; 1593 dig = radeon_encoder->enc_priv;
1534 if (ASIC_IS_DCE41(rdev)) { 1594 if (ASIC_IS_DCE41(rdev)) {
@@ -1663,7 +1723,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1663 } 1723 }
1664 1724
1665 if (ext_encoder) { 1725 if (ext_encoder) {
1666 if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP)) { 1726 if (ASIC_IS_DCE41(rdev)) {
1667 atombios_external_encoder_setup(encoder, ext_encoder, 1727 atombios_external_encoder_setup(encoder, ext_encoder,
1668 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 1728 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1669 atombios_external_encoder_setup(encoder, ext_encoder, 1729 atombios_external_encoder_setup(encoder, ext_encoder,
@@ -1986,7 +2046,10 @@ radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1986} 2046}
1987 2047
1988void 2048void
1989radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) 2049radeon_add_atom_encoder(struct drm_device *dev,
2050 uint32_t encoder_enum,
2051 uint32_t supported_device,
2052 u16 caps)
1990{ 2053{
1991 struct radeon_device *rdev = dev->dev_private; 2054 struct radeon_device *rdev = dev->dev_private;
1992 struct drm_encoder *encoder; 2055 struct drm_encoder *encoder;
@@ -2029,6 +2092,7 @@ radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t
2029 radeon_encoder->rmx_type = RMX_OFF; 2092 radeon_encoder->rmx_type = RMX_OFF;
2030 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2093 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2031 radeon_encoder->is_ext_encoder = false; 2094 radeon_encoder->is_ext_encoder = false;
2095 radeon_encoder->caps = caps;
2032 2096
2033 switch (radeon_encoder->encoder_id) { 2097 switch (radeon_encoder->encoder_id) {
2034 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2098 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index 4c222d5437d1..1ca55eb09ad3 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -81,6 +81,9 @@ enum radeon_family {
81 CHIP_CYPRESS, 81 CHIP_CYPRESS,
82 CHIP_HEMLOCK, 82 CHIP_HEMLOCK,
83 CHIP_PALM, 83 CHIP_PALM,
84 CHIP_BARTS,
85 CHIP_TURKS,
86 CHIP_CAICOS,
84 CHIP_LAST, 87 CHIP_LAST,
85}; 88};
86 89
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index fd185f783a31..12bdeab91c86 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -379,6 +379,7 @@ struct radeon_encoder {
379 int hdmi_audio_workaround; 379 int hdmi_audio_workaround;
380 int hdmi_buffer_status; 380 int hdmi_buffer_status;
381 bool is_ext_encoder; 381 bool is_ext_encoder;
382 u16 caps;
382}; 383};
383 384
384struct radeon_connector_atom_dig { 385struct radeon_connector_atom_dig {
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 0afd26ccccfa..3b1b2bf9cdd5 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -167,13 +167,13 @@ static void radeon_set_power_state(struct radeon_device *rdev)
167 if (radeon_gui_idle(rdev)) { 167 if (radeon_gui_idle(rdev)) {
168 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 168 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
169 clock_info[rdev->pm.requested_clock_mode_index].sclk; 169 clock_info[rdev->pm.requested_clock_mode_index].sclk;
170 if (sclk > rdev->clock.default_sclk) 170 if (sclk > rdev->pm.default_sclk)
171 sclk = rdev->clock.default_sclk; 171 sclk = rdev->pm.default_sclk;
172 172
173 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 173 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
174 clock_info[rdev->pm.requested_clock_mode_index].mclk; 174 clock_info[rdev->pm.requested_clock_mode_index].mclk;
175 if (mclk > rdev->clock.default_mclk) 175 if (mclk > rdev->pm.default_mclk)
176 mclk = rdev->clock.default_mclk; 176 mclk = rdev->pm.default_mclk;
177 177
178 /* upvolt before raising clocks, downvolt after lowering clocks */ 178 /* upvolt before raising clocks, downvolt after lowering clocks */
179 if (sclk < rdev->pm.current_sclk) 179 if (sclk < rdev->pm.current_sclk)
@@ -440,6 +440,7 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev,
440 temp = rv770_get_temp(rdev); 440 temp = rv770_get_temp(rdev);
441 break; 441 break;
442 case THERMAL_TYPE_EVERGREEN: 442 case THERMAL_TYPE_EVERGREEN:
443 case THERMAL_TYPE_NI:
443 temp = evergreen_get_temp(rdev); 444 temp = evergreen_get_temp(rdev);
444 break; 445 break;
445 case THERMAL_TYPE_SUMO: 446 case THERMAL_TYPE_SUMO:
@@ -529,12 +530,21 @@ void radeon_pm_suspend(struct radeon_device *rdev)
529 530
530void radeon_pm_resume(struct radeon_device *rdev) 531void radeon_pm_resume(struct radeon_device *rdev)
531{ 532{
533 /* set up the default clocks if the MC ucode is loaded */
534 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
535 if (rdev->pm.default_vddc)
536 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc);
537 if (rdev->pm.default_sclk)
538 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
539 if (rdev->pm.default_mclk)
540 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
541 }
532 /* asic init will reset the default power state */ 542 /* asic init will reset the default power state */
533 mutex_lock(&rdev->pm.mutex); 543 mutex_lock(&rdev->pm.mutex);
534 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 544 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
535 rdev->pm.current_clock_mode_index = 0; 545 rdev->pm.current_clock_mode_index = 0;
536 rdev->pm.current_sclk = rdev->clock.default_sclk; 546 rdev->pm.current_sclk = rdev->pm.default_sclk;
537 rdev->pm.current_mclk = rdev->clock.default_mclk; 547 rdev->pm.current_mclk = rdev->pm.default_mclk;
538 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 548 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
539 if (rdev->pm.pm_method == PM_METHOD_DYNPM 549 if (rdev->pm.pm_method == PM_METHOD_DYNPM
540 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 550 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
@@ -557,6 +567,8 @@ int radeon_pm_init(struct radeon_device *rdev)
557 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 567 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
558 rdev->pm.dynpm_can_upclock = true; 568 rdev->pm.dynpm_can_upclock = true;
559 rdev->pm.dynpm_can_downclock = true; 569 rdev->pm.dynpm_can_downclock = true;
570 rdev->pm.default_sclk = rdev->clock.default_sclk;
571 rdev->pm.default_mclk = rdev->clock.default_mclk;
560 rdev->pm.current_sclk = rdev->clock.default_sclk; 572 rdev->pm.current_sclk = rdev->clock.default_sclk;
561 rdev->pm.current_mclk = rdev->clock.default_mclk; 573 rdev->pm.current_mclk = rdev->clock.default_mclk;
562 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 574 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
@@ -568,6 +580,15 @@ int radeon_pm_init(struct radeon_device *rdev)
568 radeon_combios_get_power_modes(rdev); 580 radeon_combios_get_power_modes(rdev);
569 radeon_pm_print_states(rdev); 581 radeon_pm_print_states(rdev);
570 radeon_pm_init_profile(rdev); 582 radeon_pm_init_profile(rdev);
583 /* set up the default clocks if the MC ucode is loaded */
584 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
585 if (rdev->pm.default_vddc)
586 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc);
587 if (rdev->pm.default_sclk)
588 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
589 if (rdev->pm.default_mclk)
590 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
591 }
571 } 592 }
572 593
573 /* set up the internal thermal sensor if applicable */ 594 /* set up the internal thermal sensor if applicable */
@@ -803,9 +824,9 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
803 struct drm_device *dev = node->minor->dev; 824 struct drm_device *dev = node->minor->dev;
804 struct radeon_device *rdev = dev->dev_private; 825 struct radeon_device *rdev = dev->dev_private;
805 826
806 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk); 827 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
807 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 828 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
808 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk); 829 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
809 if (rdev->asic->get_memory_clock) 830 if (rdev->asic->get_memory_clock)
810 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 831 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
811 if (rdev->pm.current_vddc) 832 if (rdev->pm.current_vddc)
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 0a310b7f71c3..3cd4dace57c7 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -55,6 +55,7 @@
55#include "r500_reg.h" 55#include "r500_reg.h"
56#include "r600_reg.h" 56#include "r600_reg.h"
57#include "evergreen_reg.h" 57#include "evergreen_reg.h"
58#include "ni_reg.h"
58 59
59#define RADEON_MC_AGP_LOCATION 0x014c 60#define RADEON_MC_AGP_LOCATION 0x014c
60#define RADEON_MC_AGP_START_MASK 0x0000FFFF 61#define RADEON_MC_AGP_START_MASK 0x0000FFFF
@@ -320,6 +321,15 @@
320# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8) 321# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
321# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9) 322# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
322# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10) 323# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
324# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
325# define R600_PCIE_LC_RENEGOTIATION_SUPPORT (1 << 9)
326# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)
327# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)
328# define R600_PCIE_LC_UPCONFIGURE_SUPPORT (1 << 12)
329# define R600_PCIE_LC_UPCONFIGURE_DIS (1 << 13)
330
331#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c
332#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
323 333
324#define RADEON_CACHE_CNTL 0x1724 334#define RADEON_CACHE_CNTL 0x1724
325#define RADEON_CACHE_LINE 0x0f0c /* PCI */ 335#define RADEON_CACHE_LINE 0x0f0c /* PCI */
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 645aa1fd7611..3a264aa3a79a 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -41,6 +41,7 @@
41 41
42static void rv770_gpu_init(struct radeon_device *rdev); 42static void rv770_gpu_init(struct radeon_device *rdev);
43void rv770_fini(struct radeon_device *rdev); 43void rv770_fini(struct radeon_device *rdev);
44static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
44 45
45u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 46u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
46{ 47{
@@ -1124,6 +1125,9 @@ static int rv770_startup(struct radeon_device *rdev)
1124{ 1125{
1125 int r; 1126 int r;
1126 1127
1128 /* enable pcie gen2 link */
1129 rv770_pcie_gen2_enable(rdev);
1130
1127 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1131 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1128 r = r600_init_microcode(rdev); 1132 r = r600_init_microcode(rdev);
1129 if (r) { 1133 if (r) {
@@ -1362,3 +1366,75 @@ void rv770_fini(struct radeon_device *rdev)
1362 rdev->bios = NULL; 1366 rdev->bios = NULL;
1363 radeon_dummy_page_fini(rdev); 1367 radeon_dummy_page_fini(rdev);
1364} 1368}
1369
1370static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
1371{
1372 u32 link_width_cntl, lanes, speed_cntl, tmp;
1373 u16 link_cntl2;
1374
1375 if (rdev->flags & RADEON_IS_IGP)
1376 return;
1377
1378 if (!(rdev->flags & RADEON_IS_PCIE))
1379 return;
1380
1381 /* x2 cards have a special sequence */
1382 if (ASIC_IS_X2(rdev))
1383 return;
1384
1385 /* advertise upconfig capability */
1386 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1387 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1388 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1389 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1390 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
1391 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
1392 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
1393 LC_RECONFIG_ARC_MISSING_ESCAPE);
1394 link_width_cntl |= lanes | LC_RECONFIG_NOW |
1395 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
1396 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1397 } else {
1398 link_width_cntl |= LC_UPCONFIGURE_DIS;
1399 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1400 }
1401
1402 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1403 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
1404 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
1405
1406 tmp = RREG32(0x541c);
1407 WREG32(0x541c, tmp | 0x8);
1408 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
1409 link_cntl2 = RREG16(0x4088);
1410 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
1411 link_cntl2 |= 0x2;
1412 WREG16(0x4088, link_cntl2);
1413 WREG32(MM_CFGREGS_CNTL, 0);
1414
1415 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1416 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
1417 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1418
1419 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1420 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
1421 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1422
1423 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1424 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
1425 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1426
1427 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
1428 speed_cntl |= LC_GEN2_EN_STRAP;
1429 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
1430
1431 } else {
1432 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
1433 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
1434 if (1)
1435 link_width_cntl |= LC_UPCONFIGURE_DIS;
1436 else
1437 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
1438 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
1439 }
1440}
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index fc77e1e1a179..abc8cf5a3672 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -360,4 +360,42 @@
360#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 360#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
361#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 361#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
362 362
363/* PCIE link stuff */
364#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
365#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
366# define LC_LINK_WIDTH_SHIFT 0
367# define LC_LINK_WIDTH_MASK 0x7
368# define LC_LINK_WIDTH_X0 0
369# define LC_LINK_WIDTH_X1 1
370# define LC_LINK_WIDTH_X2 2
371# define LC_LINK_WIDTH_X4 3
372# define LC_LINK_WIDTH_X8 4
373# define LC_LINK_WIDTH_X16 6
374# define LC_LINK_WIDTH_RD_SHIFT 4
375# define LC_LINK_WIDTH_RD_MASK 0x70
376# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
377# define LC_RECONFIG_NOW (1 << 8)
378# define LC_RENEGOTIATION_SUPPORT (1 << 9)
379# define LC_RENEGOTIATE_EN (1 << 10)
380# define LC_SHORT_RECONFIG_EN (1 << 11)
381# define LC_UPCONFIGURE_SUPPORT (1 << 12)
382# define LC_UPCONFIGURE_DIS (1 << 13)
383#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
384# define LC_GEN2_EN_STRAP (1 << 0)
385# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
386# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
387# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
388# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
389# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
390# define LC_CURRENT_DATA_RATE (1 << 11)
391# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
392# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
393# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
394# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
395#define MM_CFGREGS_CNTL 0x544c
396# define MM_WR_TO_CFG_EN (1 << 3)
397#define LINK_CNTL2 0x88 /* F0 */
398# define TARGET_LINK_SPEED_MASK (0xf << 0)
399# define SELECTABLE_DEEMPHASIS (1 << 6)
400
363#endif 401#endif
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index e6b28a39942f..fe29ae328bd9 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -142,6 +142,42 @@
142 {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 142 {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
143 {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 143 {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
144 {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 144 {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
145 {0x1002, 0x6720, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
146 {0x1002, 0x6721, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
147 {0x1002, 0x6722, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
148 {0x1002, 0x6723, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
149 {0x1002, 0x6724, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
150 {0x1002, 0x6725, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
151 {0x1002, 0x6726, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
152 {0x1002, 0x6727, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
153 {0x1002, 0x6728, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
154 {0x1002, 0x6729, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
155 {0x1002, 0x6738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
156 {0x1002, 0x6739, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
157 {0x1002, 0x6740, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
158 {0x1002, 0x6741, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
159 {0x1002, 0x6742, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
160 {0x1002, 0x6743, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
161 {0x1002, 0x6744, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
162 {0x1002, 0x6745, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
163 {0x1002, 0x6746, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
164 {0x1002, 0x6747, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
165 {0x1002, 0x6748, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
166 {0x1002, 0x6749, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
167 {0x1002, 0x6750, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
168 {0x1002, 0x6758, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
169 {0x1002, 0x6759, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
170 {0x1002, 0x6760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
171 {0x1002, 0x6761, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
172 {0x1002, 0x6762, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
173 {0x1002, 0x6763, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
174 {0x1002, 0x6764, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
175 {0x1002, 0x6765, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
176 {0x1002, 0x6766, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
177 {0x1002, 0x6767, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
178 {0x1002, 0x6768, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
179 {0x1002, 0x6770, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
180 {0x1002, 0x6779, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
145 {0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 181 {0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
146 {0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ 182 {0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
147 {0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ 183 {0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 12:39:37 -0500