ARM: i.MX6: clk: add different DualLite MLB clock config

Commit fbcb441217dd2bce00e892fd5b2a481c2249f1a4 upstream.

The CCM_CBCMR register (address 0x02C4018) has different meaning
between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite.

Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the
i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock
configuration.

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

1 files changed, 8 insertions, 1 deletions

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 369100ddaaf7..79a118a2925d 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -495,7 +495,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
         clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
         clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
-        clk[mlb]          = imx_clk_gate2("mlb",           "axi",               base + 0x74, 18);
+        if (cpu_is_imx6dl())
+                /*
+                 * The multiplexer and divider of the imx6q clock gpu2d get
+                 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
+                 */
+                clk[mlb] = imx_clk_gate2("mlb",            "gpu2d_core_podf",   base + 0x74, 18);
+        else
+                clk[mlb] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);
         clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
         clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
         clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);