ARM: imx: disable pll8_mlb in mx6q_clks

Commit 7f96d2d4d86377df04c8856b8fd47b0ad58c98aa upstream.

The MLB PLL clock's operation doesn't fit for clock framework and
it should be handled internally in MLB driver.
Remove initialization of pll8_mlb clock device but leave its
declaration in mx6q_clks to avoid affecting imx6q clock numbering.

[ shawn.guo: The MLB PLL is currently implemented as an imx pllv3
  clock.  But it does not really make too much sense, because the PLL
  does not have ENABLE, POWERDOWN and DIV_SELECT bits.

  Also commit 0e57446 (ARM i.MX6: correct MLB clock configuration)
  already removes the incorrect parenting on MLB PLL, now it's safe
  and reasonable to remove the PLL completely from clock framework,
  and let MLB driver handle the PLL per its particular need. ]

Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

1 files changed, 0 insertions, 1 deletions

diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index e6cdd6c19253..369100ddaaf7 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -302,7 +302,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
         clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f);
         clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
         clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
-        clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll8_mlb",     "osc", base + 0xd0, 0x0);
 
         /*
          * Bit 20 is the reserved and read-only bit, we do this only for: