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authorGrant Likely <grant.likely@secretlab.ca>2008-01-25 00:25:31 -0500
committerGrant Likely <grant.likely@secretlab.ca>2008-01-26 17:32:11 -0500
commit24ce6bc4a2b75509b29372f1e5e7e0fe51d98e66 (patch)
treea0dae7f428373307312d2bccac59ec5dc35f4af7
parent66ffbe490b6156898364b3f20a571a78f8d77bc8 (diff)
[POWERPC] mpc5200: make dts files conform to generic names recommended practice
Modify mpc5200 dts files to match Open Firmware's Generic Names recommended practice. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts58
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts94
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts91
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts66
-rw-r--r--arch/powerpc/boot/dts/tqm5200.dts43
-rw-r--r--arch/powerpc/boot/serial.c2
6 files changed, 150 insertions, 204 deletions
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 2b88a58791ac..30737eafe68e 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -47,17 +47,14 @@
47 soc5200@f0000000 { 47 soc5200@f0000000 {
48 #address-cells = <1>; 48 #address-cells = <1>;
49 #size-cells = <1>; 49 #size-cells = <1>;
50 model = "fsl,mpc5200b"; 50 compatible = "fsl,mpc5200b-immr";
51 compatible = "fsl,mpc5200b";
52 revision = ""; // from bootloader
53 device_type = "soc";
54 ranges = <0 f0000000 0000c000>; 51 ranges = <0 f0000000 0000c000>;
55 reg = <f0000000 00000100>; 52 reg = <f0000000 00000100>;
56 bus-frequency = <0>; // from bootloader 53 bus-frequency = <0>; // from bootloader
57 system-frequency = <0>; // from bootloader 54 system-frequency = <0>; // from bootloader
58 55
59 cdm@200 { 56 cdm@200 {
60 compatible = "mpc5200b-cdm","mpc5200-cdm"; 57 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
61 reg = <200 38>; 58 reg = <200 38>;
62 }; 59 };
63 60
@@ -65,11 +62,11 @@
65 // 5200 interrupts are encoded into two levels; 62 // 5200 interrupts are encoded into two levels;
66 interrupt-controller; 63 interrupt-controller;
67 #interrupt-cells = <3>; 64 #interrupt-cells = <3>;
68 compatible = "mpc5200b-pic","mpc5200-pic"; 65 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
69 reg = <500 80>; 66 reg = <500 80>;
70 }; 67 };
71 68
72 gpt@600 { // General Purpose Timer 69 timer@600 { // General Purpose Timer
73 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 70 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
74 reg = <600 10>; 71 reg = <600 10>;
75 interrupts = <1 9 0>; 72 interrupts = <1 9 0>;
@@ -77,49 +74,49 @@
77 fsl,has-wdt; 74 fsl,has-wdt;
78 }; 75 };
79 76
80 gpt@610 { // General Purpose Timer 77 timer@610 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 78 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <610 10>; 79 reg = <610 10>;
83 interrupts = <1 a 0>; 80 interrupts = <1 a 0>;
84 interrupt-parent = <&mpc5200_pic>; 81 interrupt-parent = <&mpc5200_pic>;
85 }; 82 };
86 83
87 gpt@620 { // General Purpose Timer 84 timer@620 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 85 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 reg = <620 10>; 86 reg = <620 10>;
90 interrupts = <1 b 0>; 87 interrupts = <1 b 0>;
91 interrupt-parent = <&mpc5200_pic>; 88 interrupt-parent = <&mpc5200_pic>;
92 }; 89 };
93 90
94 gpt@630 { // General Purpose Timer 91 timer@630 { // General Purpose Timer
95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
96 reg = <630 10>; 93 reg = <630 10>;
97 interrupts = <1 c 0>; 94 interrupts = <1 c 0>;
98 interrupt-parent = <&mpc5200_pic>; 95 interrupt-parent = <&mpc5200_pic>;
99 }; 96 };
100 97
101 gpt@640 { // General Purpose Timer 98 timer@640 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 99 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <640 10>; 100 reg = <640 10>;
104 interrupts = <1 d 0>; 101 interrupts = <1 d 0>;
105 interrupt-parent = <&mpc5200_pic>; 102 interrupt-parent = <&mpc5200_pic>;
106 }; 103 };
107 104
108 gpt@650 { // General Purpose Timer 105 timer@650 { // General Purpose Timer
109 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 106 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
110 reg = <650 10>; 107 reg = <650 10>;
111 interrupts = <1 e 0>; 108 interrupts = <1 e 0>;
112 interrupt-parent = <&mpc5200_pic>; 109 interrupt-parent = <&mpc5200_pic>;
113 }; 110 };
114 111
115 gpt@660 { // General Purpose Timer 112 timer@660 { // General Purpose Timer
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 113 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 reg = <660 10>; 114 reg = <660 10>;
118 interrupts = <1 f 0>; 115 interrupts = <1 f 0>;
119 interrupt-parent = <&mpc5200_pic>; 116 interrupt-parent = <&mpc5200_pic>;
120 }; 117 };
121 118
122 gpt@670 { // General Purpose Timer 119 timer@670 { // General Purpose Timer
123 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
124 reg = <670 10>; 121 reg = <670 10>;
125 interrupts = <1 10 0>; 122 interrupts = <1 10 0>;
@@ -127,43 +124,42 @@
127 }; 124 };
128 125
129 rtc@800 { // Real time clock 126 rtc@800 { // Real time clock
130 compatible = "mpc5200b-rtc","mpc5200-rtc"; 127 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
131 reg = <800 100>; 128 reg = <800 100>;
132 interrupts = <1 5 0 1 6 0>; 129 interrupts = <1 5 0 1 6 0>;
133 interrupt-parent = <&mpc5200_pic>; 130 interrupt-parent = <&mpc5200_pic>;
134 }; 131 };
135 132
136 gpio@b00 { 133 gpio@b00 {
137 compatible = "mpc5200b-gpio","mpc5200-gpio"; 134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
138 reg = <b00 40>; 135 reg = <b00 40>;
139 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
140 interrupt-parent = <&mpc5200_pic>; 137 interrupt-parent = <&mpc5200_pic>;
141 }; 138 };
142 139
143 gpio-wkup@c00 { 140 gpio@c00 {
144 compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup"; 141 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
145 reg = <c00 40>; 142 reg = <c00 40>;
146 interrupts = <1 8 0 0 3 0>; 143 interrupts = <1 8 0 0 3 0>;
147 interrupt-parent = <&mpc5200_pic>; 144 interrupt-parent = <&mpc5200_pic>;
148 }; 145 };
149 146
150 spi@f00 { 147 spi@f00 {
151 compatible = "mpc5200b-spi","mpc5200-spi"; 148 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
152 reg = <f00 20>; 149 reg = <f00 20>;
153 interrupts = <2 d 0 2 e 0>; 150 interrupts = <2 d 0 2 e 0>;
154 interrupt-parent = <&mpc5200_pic>; 151 interrupt-parent = <&mpc5200_pic>;
155 }; 152 };
156 153
157 usb@1000 { 154 usb@1000 {
158 device_type = "usb-ohci-be"; 155 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
159 compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
160 reg = <1000 ff>; 156 reg = <1000 ff>;
161 interrupts = <2 6 0>; 157 interrupts = <2 6 0>;
162 interrupt-parent = <&mpc5200_pic>; 158 interrupt-parent = <&mpc5200_pic>;
163 }; 159 };
164 160
165 dma-controller@1200 { 161 dma-controller@1200 {
166 compatible = "mpc5200b-bestcomm","mpc5200-bestcomm"; 162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
167 reg = <1200 80>; 163 reg = <1200 80>;
168 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
169 3 4 0 3 5 0 3 6 0 3 7 0 165 3 4 0 3 5 0 3 6 0 3 7 0
@@ -173,13 +169,13 @@
173 }; 169 };
174 170
175 xlb@1f00 { 171 xlb@1f00 {
176 compatible = "mpc5200b-xlb","mpc5200-xlb"; 172 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
177 reg = <1f00 100>; 173 reg = <1f00 100>;
178 }; 174 };
179 175
180 serial@2000 { // PSC1 176 serial@2000 { // PSC1
181 device_type = "serial"; 177 device_type = "serial";
182 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 178 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
183 port-number = <0>; // Logical port assignment 179 port-number = <0>; // Logical port assignment
184 reg = <2000 100>; 180 reg = <2000 100>;
185 interrupts = <2 1 0>; 181 interrupts = <2 1 0>;
@@ -188,7 +184,7 @@
188 184
189 serial@2200 { // PSC2 185 serial@2200 { // PSC2
190 device_type = "serial"; 186 device_type = "serial";
191 compatible = "mpc5200-psc-uart"; 187 compatible = "fsl,mpc5200-psc-uart";
192 port-number = <1>; // Logical port assignment 188 port-number = <1>; // Logical port assignment
193 reg = <2200 100>; 189 reg = <2200 100>;
194 interrupts = <2 2 0>; 190 interrupts = <2 2 0>;
@@ -197,7 +193,7 @@
197 193
198 serial@2400 { // PSC3 194 serial@2400 { // PSC3
199 device_type = "serial"; 195 device_type = "serial";
200 compatible = "mpc5200-psc-uart"; 196 compatible = "fsl,mpc5200-psc-uart";
201 port-number = <2>; // Logical port assignment 197 port-number = <2>; // Logical port assignment
202 reg = <2400 100>; 198 reg = <2400 100>;
203 interrupts = <2 3 0>; 199 interrupts = <2 3 0>;
@@ -206,7 +202,7 @@
206 202
207 serial@2c00 { // PSC6 203 serial@2c00 { // PSC6
208 device_type = "serial"; 204 device_type = "serial";
209 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 205 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
210 port-number = <5>; // Logical port assignment 206 port-number = <5>; // Logical port assignment
211 reg = <2c00 100>; 207 reg = <2c00 100>;
212 interrupts = <2 4 0>; 208 interrupts = <2 4 0>;
@@ -215,15 +211,15 @@
215 211
216 ethernet@3000 { 212 ethernet@3000 {
217 device_type = "network"; 213 device_type = "network";
218 compatible = "mpc5200b-fec","mpc5200-fec"; 214 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
219 reg = <3000 800>; 215 reg = <3000 800>;
220 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ 216 local-mac-address = [ 00 00 00 00 00 00 ];
221 interrupts = <2 5 0>; 217 interrupts = <2 5 0>;
222 interrupt-parent = <&mpc5200_pic>; 218 interrupt-parent = <&mpc5200_pic>;
223 }; 219 };
224 220
225 i2c@3d40 { 221 i2c@3d40 {
226 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; 222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
227 reg = <3d40 40>; 223 reg = <3d40 40>;
228 interrupts = <2 10 0>; 224 interrupts = <2 10 0>;
229 interrupt-parent = <&mpc5200_pic>; 225 interrupt-parent = <&mpc5200_pic>;
@@ -231,7 +227,7 @@
231 }; 227 };
232 228
233 sram@8000 { 229 sram@8000 {
234 compatible = "mpc5200b-sram","mpc5200-sram"; 230 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
235 reg = <8000 4000>; 231 reg = <8000 4000>;
236 }; 232 };
237 }; 233 };
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 7de3d2133d7c..0d701c1bf539 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -10,15 +10,8 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/*
14 * WARNING: Do not depend on this tree layout remaining static just yet.
15 * The MPC5200 device tree conventions are still in flux
16 * Keep an eye on the linuxppc-dev mailing list for more details
17 */
18
19/ { 13/ {
20 model = "fsl,lite5200"; 14 model = "fsl,lite5200";
21 // revision = "1.0";
22 compatible = "fsl,lite5200"; 15 compatible = "fsl,lite5200";
23 #address-cells = <1>; 16 #address-cells = <1>;
24 #size-cells = <1>; 17 #size-cells = <1>;
@@ -48,30 +41,27 @@
48 soc5200@f0000000 { 41 soc5200@f0000000 {
49 #address-cells = <1>; 42 #address-cells = <1>;
50 #size-cells = <1>; 43 #size-cells = <1>;
51 model = "fsl,mpc5200"; 44 compatible = "fsl,mpc5200-immr";
52 compatible = "mpc5200";
53 revision = ""; // from bootloader
54 device_type = "soc";
55 ranges = <0 f0000000 0000c000>; 45 ranges = <0 f0000000 0000c000>;
56 reg = <f0000000 00000100>; 46 reg = <f0000000 00000100>;
57 bus-frequency = <0>; // from bootloader 47 bus-frequency = <0>; // from bootloader
58 system-frequency = <0>; // from bootloader 48 system-frequency = <0>; // from bootloader
59 49
60 cdm@200 { 50 cdm@200 {
61 compatible = "mpc5200-cdm"; 51 compatible = "fsl,mpc5200-cdm";
62 reg = <200 38>; 52 reg = <200 38>;
63 }; 53 };
64 54
65 mpc5200_pic: pic@500 { 55 mpc5200_pic: interrupt-controller@500 {
66 // 5200 interrupts are encoded into two levels; 56 // 5200 interrupts are encoded into two levels;
67 interrupt-controller; 57 interrupt-controller;
68 #interrupt-cells = <3>; 58 #interrupt-cells = <3>;
69 device_type = "interrupt-controller"; 59 device_type = "interrupt-controller";
70 compatible = "mpc5200-pic"; 60 compatible = "fsl,mpc5200-pic";
71 reg = <500 80>; 61 reg = <500 80>;
72 }; 62 };
73 63
74 gpt@600 { // General Purpose Timer 64 timer@600 { // General Purpose Timer
75 compatible = "fsl,mpc5200-gpt"; 65 compatible = "fsl,mpc5200-gpt";
76 cell-index = <0>; 66 cell-index = <0>;
77 reg = <600 10>; 67 reg = <600 10>;
@@ -80,7 +70,7 @@
80 fsl,has-wdt; 70 fsl,has-wdt;
81 }; 71 };
82 72
83 gpt@610 { // General Purpose Timer 73 timer@610 { // General Purpose Timer
84 compatible = "fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200-gpt";
85 cell-index = <1>; 75 cell-index = <1>;
86 reg = <610 10>; 76 reg = <610 10>;
@@ -88,7 +78,7 @@
88 interrupt-parent = <&mpc5200_pic>; 78 interrupt-parent = <&mpc5200_pic>;
89 }; 79 };
90 80
91 gpt@620 { // General Purpose Timer 81 timer@620 { // General Purpose Timer
92 compatible = "fsl,mpc5200-gpt"; 82 compatible = "fsl,mpc5200-gpt";
93 cell-index = <2>; 83 cell-index = <2>;
94 reg = <620 10>; 84 reg = <620 10>;
@@ -96,7 +86,7 @@
96 interrupt-parent = <&mpc5200_pic>; 86 interrupt-parent = <&mpc5200_pic>;
97 }; 87 };
98 88
99 gpt@630 { // General Purpose Timer 89 timer@630 { // General Purpose Timer
100 compatible = "fsl,mpc5200-gpt"; 90 compatible = "fsl,mpc5200-gpt";
101 cell-index = <3>; 91 cell-index = <3>;
102 reg = <630 10>; 92 reg = <630 10>;
@@ -104,7 +94,7 @@
104 interrupt-parent = <&mpc5200_pic>; 94 interrupt-parent = <&mpc5200_pic>;
105 }; 95 };
106 96
107 gpt@640 { // General Purpose Timer 97 timer@640 { // General Purpose Timer
108 compatible = "fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200-gpt";
109 cell-index = <4>; 99 cell-index = <4>;
110 reg = <640 10>; 100 reg = <640 10>;
@@ -112,7 +102,7 @@
112 interrupt-parent = <&mpc5200_pic>; 102 interrupt-parent = <&mpc5200_pic>;
113 }; 103 };
114 104
115 gpt@650 { // General Purpose Timer 105 timer@650 { // General Purpose Timer
116 compatible = "fsl,mpc5200-gpt"; 106 compatible = "fsl,mpc5200-gpt";
117 cell-index = <5>; 107 cell-index = <5>;
118 reg = <650 10>; 108 reg = <650 10>;
@@ -120,7 +110,7 @@
120 interrupt-parent = <&mpc5200_pic>; 110 interrupt-parent = <&mpc5200_pic>;
121 }; 111 };
122 112
123 gpt@660 { // General Purpose Timer 113 timer@660 { // General Purpose Timer
124 compatible = "fsl,mpc5200-gpt"; 114 compatible = "fsl,mpc5200-gpt";
125 cell-index = <6>; 115 cell-index = <6>;
126 reg = <660 10>; 116 reg = <660 10>;
@@ -128,7 +118,7 @@
128 interrupt-parent = <&mpc5200_pic>; 118 interrupt-parent = <&mpc5200_pic>;
129 }; 119 };
130 120
131 gpt@670 { // General Purpose Timer 121 timer@670 { // General Purpose Timer
132 compatible = "fsl,mpc5200-gpt"; 122 compatible = "fsl,mpc5200-gpt";
133 cell-index = <7>; 123 cell-index = <7>;
134 reg = <670 10>; 124 reg = <670 10>;
@@ -137,25 +127,23 @@
137 }; 127 };
138 128
139 rtc@800 { // Real time clock 129 rtc@800 { // Real time clock
140 compatible = "mpc5200-rtc"; 130 compatible = "fsl,mpc5200-rtc";
141 device_type = "rtc"; 131 device_type = "rtc";
142 reg = <800 100>; 132 reg = <800 100>;
143 interrupts = <1 5 0 1 6 0>; 133 interrupts = <1 5 0 1 6 0>;
144 interrupt-parent = <&mpc5200_pic>; 134 interrupt-parent = <&mpc5200_pic>;
145 }; 135 };
146 136
147 mscan@900 { 137 can@900 {
148 device_type = "mscan"; 138 compatible = "fsl,mpc5200-mscan";
149 compatible = "mpc5200-mscan";
150 cell-index = <0>; 139 cell-index = <0>;
151 interrupts = <2 11 0>; 140 interrupts = <2 11 0>;
152 interrupt-parent = <&mpc5200_pic>; 141 interrupt-parent = <&mpc5200_pic>;
153 reg = <900 80>; 142 reg = <900 80>;
154 }; 143 };
155 144
156 mscan@980 { 145 can@980 {
157 device_type = "mscan"; 146 compatible = "fsl,mpc5200-mscan";
158 compatible = "mpc5200-mscan";
159 cell-index = <1>; 147 cell-index = <1>;
160 interrupts = <2 12 0>; 148 interrupts = <2 12 0>;
161 interrupt-parent = <&mpc5200_pic>; 149 interrupt-parent = <&mpc5200_pic>;
@@ -163,38 +151,36 @@
163 }; 151 };
164 152
165 gpio@b00 { 153 gpio@b00 {
166 compatible = "mpc5200-gpio"; 154 compatible = "fsl,mpc5200-gpio";
167 reg = <b00 40>; 155 reg = <b00 40>;
168 interrupts = <1 7 0>; 156 interrupts = <1 7 0>;
169 interrupt-parent = <&mpc5200_pic>; 157 interrupt-parent = <&mpc5200_pic>;
170 }; 158 };
171 159
172 gpio-wkup@c00 { 160 gpio@c00 {
173 compatible = "mpc5200-gpio-wkup"; 161 compatible = "fsl,mpc5200-gpio-wkup";
174 reg = <c00 40>; 162 reg = <c00 40>;
175 interrupts = <1 8 0 0 3 0>; 163 interrupts = <1 8 0 0 3 0>;
176 interrupt-parent = <&mpc5200_pic>; 164 interrupt-parent = <&mpc5200_pic>;
177 }; 165 };
178 166
179 spi@f00 { 167 spi@f00 {
180 device_type = "spi"; 168 compatible = "fsl,mpc5200-spi";
181 compatible = "mpc5200-spi";
182 reg = <f00 20>; 169 reg = <f00 20>;
183 interrupts = <2 d 0 2 e 0>; 170 interrupts = <2 d 0 2 e 0>;
184 interrupt-parent = <&mpc5200_pic>; 171 interrupt-parent = <&mpc5200_pic>;
185 }; 172 };
186 173
187 usb@1000 { 174 usb@1000 {
188 device_type = "usb-ohci-be"; 175 compatible = "fsl,mpc5200-ohci","ohci-be";
189 compatible = "mpc5200-ohci","ohci-be";
190 reg = <1000 ff>; 176 reg = <1000 ff>;
191 interrupts = <2 6 0>; 177 interrupts = <2 6 0>;
192 interrupt-parent = <&mpc5200_pic>; 178 interrupt-parent = <&mpc5200_pic>;
193 }; 179 };
194 180
195 bestcomm@1200 { 181 dma-controller@1200 {
196 device_type = "dma-controller"; 182 device_type = "dma-controller";
197 compatible = "mpc5200-bestcomm"; 183 compatible = "fsl,mpc5200-bestcomm";
198 reg = <1200 80>; 184 reg = <1200 80>;
199 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 185 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
200 3 4 0 3 5 0 3 6 0 3 7 0 186 3 4 0 3 5 0 3 6 0 3 7 0
@@ -204,13 +190,13 @@
204 }; 190 };
205 191
206 xlb@1f00 { 192 xlb@1f00 {
207 compatible = "mpc5200-xlb"; 193 compatible = "fsl,mpc5200-xlb";
208 reg = <1f00 100>; 194 reg = <1f00 100>;
209 }; 195 };
210 196
211 serial@2000 { // PSC1 197 serial@2000 { // PSC1
212 device_type = "serial"; 198 device_type = "serial";
213 compatible = "mpc5200-psc-uart"; 199 compatible = "fsl,mpc5200-psc-uart";
214 port-number = <0>; // Logical port assignment 200 port-number = <0>; // Logical port assignment
215 cell-index = <0>; 201 cell-index = <0>;
216 reg = <2000 100>; 202 reg = <2000 100>;
@@ -220,8 +206,7 @@
220 206
221 // PSC2 in ac97 mode example 207 // PSC2 in ac97 mode example
222 //ac97@2200 { // PSC2 208 //ac97@2200 { // PSC2
223 // device_type = "sound"; 209 // compatible = "fsl,mpc5200-psc-ac97";
224 // compatible = "mpc5200-psc-ac97";
225 // cell-index = <1>; 210 // cell-index = <1>;
226 // reg = <2200 100>; 211 // reg = <2200 100>;
227 // interrupts = <2 2 0>; 212 // interrupts = <2 2 0>;
@@ -230,8 +215,7 @@
230 215
231 // PSC3 in CODEC mode example 216 // PSC3 in CODEC mode example
232 //i2s@2400 { // PSC3 217 //i2s@2400 { // PSC3
233 // device_type = "sound"; 218 // compatible = "fsl,mpc5200-psc-i2s";
234 // compatible = "mpc5200-psc-i2s";
235 // cell-index = <2>; 219 // cell-index = <2>;
236 // reg = <2400 100>; 220 // reg = <2400 100>;
237 // interrupts = <2 3 0>; 221 // interrupts = <2 3 0>;
@@ -241,7 +225,7 @@
241 // PSC4 in uart mode example 225 // PSC4 in uart mode example
242 //serial@2600 { // PSC4 226 //serial@2600 { // PSC4
243 // device_type = "serial"; 227 // device_type = "serial";
244 // compatible = "mpc5200-psc-uart"; 228 // compatible = "fsl,mpc5200-psc-uart";
245 // cell-index = <3>; 229 // cell-index = <3>;
246 // reg = <2600 100>; 230 // reg = <2600 100>;
247 // interrupts = <2 b 0>; 231 // interrupts = <2 b 0>;
@@ -251,7 +235,7 @@
251 // PSC5 in uart mode example 235 // PSC5 in uart mode example
252 //serial@2800 { // PSC5 236 //serial@2800 { // PSC5
253 // device_type = "serial"; 237 // device_type = "serial";
254 // compatible = "mpc5200-psc-uart"; 238 // compatible = "fsl,mpc5200-psc-uart";
255 // cell-index = <4>; 239 // cell-index = <4>;
256 // reg = <2800 100>; 240 // reg = <2800 100>;
257 // interrupts = <2 c 0>; 241 // interrupts = <2 c 0>;
@@ -260,8 +244,7 @@
260 244
261 // PSC6 in spi mode example 245 // PSC6 in spi mode example
262 //spi@2c00 { // PSC6 246 //spi@2c00 { // PSC6
263 // device_type = "spi"; 247 // compatible = "fsl,mpc5200-psc-spi";
264 // compatible = "mpc5200-psc-spi";
265 // cell-index = <5>; 248 // cell-index = <5>;
266 // reg = <2c00 100>; 249 // reg = <2c00 100>;
267 // interrupts = <2 4 0>; 250 // interrupts = <2 4 0>;
@@ -270,16 +253,16 @@
270 253
271 ethernet@3000 { 254 ethernet@3000 {
272 device_type = "network"; 255 device_type = "network";
273 compatible = "mpc5200-fec"; 256 compatible = "fsl,mpc5200-fec";
274 reg = <3000 800>; 257 reg = <3000 800>;
275 mac-address = [ 02 03 04 05 06 07 ]; // Bad! 258 local-mac-address = [ 00 00 00 00 00 00 ];
276 interrupts = <2 5 0>; 259 interrupts = <2 5 0>;
277 interrupt-parent = <&mpc5200_pic>; 260 interrupt-parent = <&mpc5200_pic>;
278 }; 261 };
279 262
280 ata@3a00 { 263 ata@3a00 {
281 device_type = "ata"; 264 device_type = "ata";
282 compatible = "mpc5200-ata"; 265 compatible = "fsl,mpc5200-ata";
283 reg = <3a00 100>; 266 reg = <3a00 100>;
284 interrupts = <2 7 0>; 267 interrupts = <2 7 0>;
285 interrupt-parent = <&mpc5200_pic>; 268 interrupt-parent = <&mpc5200_pic>;
@@ -288,7 +271,7 @@
288 i2c@3d00 { 271 i2c@3d00 {
289 #address-cells = <1>; 272 #address-cells = <1>;
290 #size-cells = <0>; 273 #size-cells = <0>;
291 compatible = "mpc5200-i2c","fsl-i2c"; 274 compatible = "fsl,mpc5200-i2c","fsl-i2c";
292 cell-index = <0>; 275 cell-index = <0>;
293 reg = <3d00 40>; 276 reg = <3d00 40>;
294 interrupts = <2 f 0>; 277 interrupts = <2 f 0>;
@@ -299,7 +282,7 @@
299 i2c@3d40 { 282 i2c@3d40 {
300 #address-cells = <1>; 283 #address-cells = <1>;
301 #size-cells = <0>; 284 #size-cells = <0>;
302 compatible = "mpc5200-i2c","fsl-i2c"; 285 compatible = "fsl,mpc5200-i2c","fsl-i2c";
303 cell-index = <1>; 286 cell-index = <1>;
304 reg = <3d40 40>; 287 reg = <3d40 40>;
305 interrupts = <2 10 0>; 288 interrupts = <2 10 0>;
@@ -307,8 +290,7 @@
307 fsl5200-clocking; 290 fsl5200-clocking;
308 }; 291 };
309 sram@8000 { 292 sram@8000 {
310 device_type = "sram"; 293 compatible = "fsl,mpc5200-sram","sram";
311 compatible = "mpc5200-sram","sram";
312 reg = <8000 4000>; 294 reg = <8000 4000>;
313 }; 295 };
314 }; 296 };
@@ -318,7 +300,7 @@
318 #size-cells = <2>; 300 #size-cells = <2>;
319 #address-cells = <3>; 301 #address-cells = <3>;
320 device_type = "pci"; 302 device_type = "pci";
321 compatible = "mpc5200-pci"; 303 compatible = "fsl,mpc5200-pci";
322 reg = <f0000d00 100>; 304 reg = <f0000d00 100>;
323 interrupt-map-mask = <f800 0 0 7>; 305 interrupt-map-mask = <f800 0 0 7>;
324 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 306 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index dd2c4fd3d098..571ba02accac 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -18,7 +18,6 @@
18 18
19/ { 19/ {
20 model = "fsl,lite5200b"; 20 model = "fsl,lite5200b";
21 // revision = "1.0";
22 compatible = "fsl,lite5200b"; 21 compatible = "fsl,lite5200b";
23 #address-cells = <1>; 22 #address-cells = <1>;
24 #size-cells = <1>; 23 #size-cells = <1>;
@@ -48,30 +47,27 @@
48 soc5200@f0000000 { 47 soc5200@f0000000 {
49 #address-cells = <1>; 48 #address-cells = <1>;
50 #size-cells = <1>; 49 #size-cells = <1>;
51 model = "fsl,mpc5200b"; 50 compatible = "fsl,mpc5200b-immr";
52 compatible = "mpc5200";
53 revision = ""; // from bootloader
54 device_type = "soc";
55 ranges = <0 f0000000 0000c000>; 51 ranges = <0 f0000000 0000c000>;
56 reg = <f0000000 00000100>; 52 reg = <f0000000 00000100>;
57 bus-frequency = <0>; // from bootloader 53 bus-frequency = <0>; // from bootloader
58 system-frequency = <0>; // from bootloader 54 system-frequency = <0>; // from bootloader
59 55
60 cdm@200 { 56 cdm@200 {
61 compatible = "mpc5200b-cdm","mpc5200-cdm"; 57 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
62 reg = <200 38>; 58 reg = <200 38>;
63 }; 59 };
64 60
65 mpc5200_pic: pic@500 { 61 mpc5200_pic: interrupt-controller@500 {
66 // 5200 interrupts are encoded into two levels; 62 // 5200 interrupts are encoded into two levels;
67 interrupt-controller; 63 interrupt-controller;
68 #interrupt-cells = <3>; 64 #interrupt-cells = <3>;
69 device_type = "interrupt-controller"; 65 device_type = "interrupt-controller";
70 compatible = "mpc5200b-pic","mpc5200-pic"; 66 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
71 reg = <500 80>; 67 reg = <500 80>;
72 }; 68 };
73 69
74 gpt@600 { // General Purpose Timer 70 timer@600 { // General Purpose Timer
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 71 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
76 cell-index = <0>; 72 cell-index = <0>;
77 reg = <600 10>; 73 reg = <600 10>;
@@ -80,7 +76,7 @@
80 fsl,has-wdt; 76 fsl,has-wdt;
81 }; 77 };
82 78
83 gpt@610 { // General Purpose Timer 79 timer@610 { // General Purpose Timer
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 cell-index = <1>; 81 cell-index = <1>;
86 reg = <610 10>; 82 reg = <610 10>;
@@ -88,7 +84,7 @@
88 interrupt-parent = <&mpc5200_pic>; 84 interrupt-parent = <&mpc5200_pic>;
89 }; 85 };
90 86
91 gpt@620 { // General Purpose Timer 87 timer@620 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 cell-index = <2>; 89 cell-index = <2>;
94 reg = <620 10>; 90 reg = <620 10>;
@@ -96,7 +92,7 @@
96 interrupt-parent = <&mpc5200_pic>; 92 interrupt-parent = <&mpc5200_pic>;
97 }; 93 };
98 94
99 gpt@630 { // General Purpose Timer 95 timer@630 { // General Purpose Timer
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 96 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 cell-index = <3>; 97 cell-index = <3>;
102 reg = <630 10>; 98 reg = <630 10>;
@@ -104,7 +100,7 @@
104 interrupt-parent = <&mpc5200_pic>; 100 interrupt-parent = <&mpc5200_pic>;
105 }; 101 };
106 102
107 gpt@640 { // General Purpose Timer 103 timer@640 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 cell-index = <4>; 105 cell-index = <4>;
110 reg = <640 10>; 106 reg = <640 10>;
@@ -112,7 +108,7 @@
112 interrupt-parent = <&mpc5200_pic>; 108 interrupt-parent = <&mpc5200_pic>;
113 }; 109 };
114 110
115 gpt@650 { // General Purpose Timer 111 timer@650 { // General Purpose Timer
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 112 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 cell-index = <5>; 113 cell-index = <5>;
118 reg = <650 10>; 114 reg = <650 10>;
@@ -120,7 +116,7 @@
120 interrupt-parent = <&mpc5200_pic>; 116 interrupt-parent = <&mpc5200_pic>;
121 }; 117 };
122 118
123 gpt@660 { // General Purpose Timer 119 timer@660 { // General Purpose Timer
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
125 cell-index = <6>; 121 cell-index = <6>;
126 reg = <660 10>; 122 reg = <660 10>;
@@ -128,7 +124,7 @@
128 interrupt-parent = <&mpc5200_pic>; 124 interrupt-parent = <&mpc5200_pic>;
129 }; 125 };
130 126
131 gpt@670 { // General Purpose Timer 127 timer@670 { // General Purpose Timer
132 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 128 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
133 cell-index = <7>; 129 cell-index = <7>;
134 reg = <670 10>; 130 reg = <670 10>;
@@ -137,25 +133,23 @@
137 }; 133 };
138 134
139 rtc@800 { // Real time clock 135 rtc@800 { // Real time clock
140 compatible = "mpc5200b-rtc","mpc5200-rtc"; 136 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
141 device_type = "rtc"; 137 device_type = "rtc";
142 reg = <800 100>; 138 reg = <800 100>;
143 interrupts = <1 5 0 1 6 0>; 139 interrupts = <1 5 0 1 6 0>;
144 interrupt-parent = <&mpc5200_pic>; 140 interrupt-parent = <&mpc5200_pic>;
145 }; 141 };
146 142
147 mscan@900 { 143 can@900 {
148 device_type = "mscan"; 144 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
149 compatible = "mpc5200b-mscan","mpc5200-mscan";
150 cell-index = <0>; 145 cell-index = <0>;
151 interrupts = <2 11 0>; 146 interrupts = <2 11 0>;
152 interrupt-parent = <&mpc5200_pic>; 147 interrupt-parent = <&mpc5200_pic>;
153 reg = <900 80>; 148 reg = <900 80>;
154 }; 149 };
155 150
156 mscan@980 { 151 can@980 {
157 device_type = "mscan"; 152 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
158 compatible = "mpc5200b-mscan","mpc5200-mscan";
159 cell-index = <1>; 153 cell-index = <1>;
160 interrupts = <2 12 0>; 154 interrupts = <2 12 0>;
161 interrupt-parent = <&mpc5200_pic>; 155 interrupt-parent = <&mpc5200_pic>;
@@ -163,38 +157,36 @@
163 }; 157 };
164 158
165 gpio@b00 { 159 gpio@b00 {
166 compatible = "mpc5200b-gpio","mpc5200-gpio"; 160 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
167 reg = <b00 40>; 161 reg = <b00 40>;
168 interrupts = <1 7 0>; 162 interrupts = <1 7 0>;
169 interrupt-parent = <&mpc5200_pic>; 163 interrupt-parent = <&mpc5200_pic>;
170 }; 164 };
171 165
172 gpio-wkup@c00 { 166 gpio@c00 {
173 compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup"; 167 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
174 reg = <c00 40>; 168 reg = <c00 40>;
175 interrupts = <1 8 0 0 3 0>; 169 interrupts = <1 8 0 0 3 0>;
176 interrupt-parent = <&mpc5200_pic>; 170 interrupt-parent = <&mpc5200_pic>;
177 }; 171 };
178 172
179 spi@f00 { 173 spi@f00 {
180 device_type = "spi"; 174 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
181 compatible = "mpc5200b-spi","mpc5200-spi";
182 reg = <f00 20>; 175 reg = <f00 20>;
183 interrupts = <2 d 0 2 e 0>; 176 interrupts = <2 d 0 2 e 0>;
184 interrupt-parent = <&mpc5200_pic>; 177 interrupt-parent = <&mpc5200_pic>;
185 }; 178 };
186 179
187 usb@1000 { 180 usb@1000 {
188 device_type = "usb-ohci-be"; 181 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
189 compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
190 reg = <1000 ff>; 182 reg = <1000 ff>;
191 interrupts = <2 6 0>; 183 interrupts = <2 6 0>;
192 interrupt-parent = <&mpc5200_pic>; 184 interrupt-parent = <&mpc5200_pic>;
193 }; 185 };
194 186
195 bestcomm@1200 { 187 dma-controller@1200 {
196 device_type = "dma-controller"; 188 device_type = "dma-controller";
197 compatible = "mpc5200b-bestcomm","mpc5200-bestcomm"; 189 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
198 reg = <1200 80>; 190 reg = <1200 80>;
199 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 191 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
200 3 4 0 3 5 0 3 6 0 3 7 0 192 3 4 0 3 5 0 3 6 0 3 7 0
@@ -204,13 +196,13 @@
204 }; 196 };
205 197
206 xlb@1f00 { 198 xlb@1f00 {
207 compatible = "mpc5200b-xlb","mpc5200-xlb"; 199 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
208 reg = <1f00 100>; 200 reg = <1f00 100>;
209 }; 201 };
210 202
211 serial@2000 { // PSC1 203 serial@2000 { // PSC1
212 device_type = "serial"; 204 device_type = "serial";
213 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 205 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
214 port-number = <0>; // Logical port assignment 206 port-number = <0>; // Logical port assignment
215 cell-index = <0>; 207 cell-index = <0>;
216 reg = <2000 100>; 208 reg = <2000 100>;
@@ -220,8 +212,7 @@
220 212
221 // PSC2 in ac97 mode example 213 // PSC2 in ac97 mode example
222 //ac97@2200 { // PSC2 214 //ac97@2200 { // PSC2
223 // device_type = "sound"; 215 // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
224 // compatible = "mpc5200b-psc-ac97","mpc5200-psc-ac97";
225 // cell-index = <1>; 216 // cell-index = <1>;
226 // reg = <2200 100>; 217 // reg = <2200 100>;
227 // interrupts = <2 2 0>; 218 // interrupts = <2 2 0>;
@@ -230,8 +221,7 @@
230 221
231 // PSC3 in CODEC mode example 222 // PSC3 in CODEC mode example
232 //i2s@2400 { // PSC3 223 //i2s@2400 { // PSC3
233 // device_type = "sound"; 224 // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
234 // compatible = "mpc5200b-psc-i2s"; //not 5200 compatible
235 // cell-index = <2>; 225 // cell-index = <2>;
236 // reg = <2400 100>; 226 // reg = <2400 100>;
237 // interrupts = <2 3 0>; 227 // interrupts = <2 3 0>;
@@ -241,7 +231,7 @@
241 // PSC4 in uart mode example 231 // PSC4 in uart mode example
242 //serial@2600 { // PSC4 232 //serial@2600 { // PSC4
243 // device_type = "serial"; 233 // device_type = "serial";
244 // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 234 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
245 // cell-index = <3>; 235 // cell-index = <3>;
246 // reg = <2600 100>; 236 // reg = <2600 100>;
247 // interrupts = <2 b 0>; 237 // interrupts = <2 b 0>;
@@ -251,7 +241,7 @@
251 // PSC5 in uart mode example 241 // PSC5 in uart mode example
252 //serial@2800 { // PSC5 242 //serial@2800 { // PSC5
253 // device_type = "serial"; 243 // device_type = "serial";
254 // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 244 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
255 // cell-index = <4>; 245 // cell-index = <4>;
256 // reg = <2800 100>; 246 // reg = <2800 100>;
257 // interrupts = <2 c 0>; 247 // interrupts = <2 c 0>;
@@ -260,8 +250,7 @@
260 250
261 // PSC6 in spi mode example 251 // PSC6 in spi mode example
262 //spi@2c00 { // PSC6 252 //spi@2c00 { // PSC6
263 // device_type = "spi"; 253 // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
264 // compatible = "mpc5200b-psc-spi","mpc5200-psc-spi";
265 // cell-index = <5>; 254 // cell-index = <5>;
266 // reg = <2c00 100>; 255 // reg = <2c00 100>;
267 // interrupts = <2 4 0>; 256 // interrupts = <2 4 0>;
@@ -270,9 +259,9 @@
270 259
271 ethernet@3000 { 260 ethernet@3000 {
272 device_type = "network"; 261 device_type = "network";
273 compatible = "mpc5200b-fec","mpc5200-fec"; 262 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
274 reg = <3000 400>; 263 reg = <3000 400>;
275 mac-address = [ 02 03 04 05 06 07 ]; // Bad! 264 local-mac-address = [ 00 00 00 00 00 00 ];
276 interrupts = <2 5 0>; 265 interrupts = <2 5 0>;
277 interrupt-parent = <&mpc5200_pic>; 266 interrupt-parent = <&mpc5200_pic>;
278 phy-handle = <&phy0>; 267 phy-handle = <&phy0>;
@@ -281,8 +270,7 @@
281 mdio@3000 { 270 mdio@3000 {
282 #address-cells = <1>; 271 #address-cells = <1>;
283 #size-cells = <0>; 272 #size-cells = <0>;
284 device_type = "mdio"; 273 compatible = "fsl,mpc5200b-mdio";
285 compatible = "mpc5200b-fec-phy";
286 reg = <3000 400>; // fec range, since we need to setup fec interrupts 274 reg = <3000 400>; // fec range, since we need to setup fec interrupts
287 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 275 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
288 interrupt-parent = <&mpc5200_pic>; 276 interrupt-parent = <&mpc5200_pic>;
@@ -295,7 +283,7 @@
295 283
296 ata@3a00 { 284 ata@3a00 {
297 device_type = "ata"; 285 device_type = "ata";
298 compatible = "mpc5200b-ata","mpc5200-ata"; 286 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
299 reg = <3a00 100>; 287 reg = <3a00 100>;
300 interrupts = <2 7 0>; 288 interrupts = <2 7 0>;
301 interrupt-parent = <&mpc5200_pic>; 289 interrupt-parent = <&mpc5200_pic>;
@@ -304,7 +292,7 @@
304 i2c@3d00 { 292 i2c@3d00 {
305 #address-cells = <1>; 293 #address-cells = <1>;
306 #size-cells = <0>; 294 #size-cells = <0>;
307 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; 295 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
308 cell-index = <0>; 296 cell-index = <0>;
309 reg = <3d00 40>; 297 reg = <3d00 40>;
310 interrupts = <2 f 0>; 298 interrupts = <2 f 0>;
@@ -315,7 +303,7 @@
315 i2c@3d40 { 303 i2c@3d40 {
316 #address-cells = <1>; 304 #address-cells = <1>;
317 #size-cells = <0>; 305 #size-cells = <0>;
318 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; 306 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
319 cell-index = <1>; 307 cell-index = <1>;
320 reg = <3d40 40>; 308 reg = <3d40 40>;
321 interrupts = <2 10 0>; 309 interrupts = <2 10 0>;
@@ -323,8 +311,7 @@
323 fsl5200-clocking; 311 fsl5200-clocking;
324 }; 312 };
325 sram@8000 { 313 sram@8000 {
326 device_type = "sram"; 314 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
327 compatible = "mpc5200b-sram","mpc5200-sram","sram";
328 reg = <8000 4000>; 315 reg = <8000 4000>;
329 }; 316 };
330 }; 317 };
@@ -334,7 +321,7 @@
334 #size-cells = <2>; 321 #size-cells = <2>;
335 #address-cells = <3>; 322 #address-cells = <3>;
336 device_type = "pci"; 323 device_type = "pci";
337 compatible = "mpc5200b-pci","mpc5200-pci"; 324 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
338 reg = <f0000d00 100>; 325 reg = <f0000d00 100>;
339 interrupt-map-mask = <f800 0 0 7>; 326 interrupt-map-mask = <f800 0 0 7>;
340 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 327 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index ee30805e35cd..76951ab038ee 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -10,12 +10,6 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/*
14 * WARNING: Do not depend on this tree layout remaining static just yet.
15 * The MPC5200 device tree conventions are still in flux
16 * Keep an eye on the linuxppc-dev mailing list for more details
17 */
18
19/ { 13/ {
20 model = "promess,motionpro"; 14 model = "promess,motionpro";
21 compatible = "promess,motionpro"; 15 compatible = "promess,motionpro";
@@ -47,29 +41,26 @@
47 soc5200@f0000000 { 41 soc5200@f0000000 {
48 #address-cells = <1>; 42 #address-cells = <1>;
49 #size-cells = <1>; 43 #size-cells = <1>;
50 model = "fsl,mpc5200b"; 44 compatible = "fsl,mpc5200b-immr";
51 compatible = "fsl,mpc5200b";
52 revision = ""; // from bootloader
53 device_type = "soc";
54 ranges = <0 f0000000 0000c000>; 45 ranges = <0 f0000000 0000c000>;
55 reg = <f0000000 00000100>; 46 reg = <f0000000 00000100>;
56 bus-frequency = <0>; // from bootloader 47 bus-frequency = <0>; // from bootloader
57 system-frequency = <0>; // from bootloader 48 system-frequency = <0>; // from bootloader
58 49
59 cdm@200 { 50 cdm@200 {
60 compatible = "mpc5200b-cdm","mpc5200-cdm"; 51 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
61 reg = <200 38>; 52 reg = <200 38>;
62 }; 53 };
63 54
64 mpc5200_pic: pic@500 { 55 mpc5200_pic: interrupt-controller@500 {
65 // 5200 interrupts are encoded into two levels; 56 // 5200 interrupts are encoded into two levels;
66 interrupt-controller; 57 interrupt-controller;
67 #interrupt-cells = <3>; 58 #interrupt-cells = <3>;
68 compatible = "mpc5200b-pic","mpc5200-pic"; 59 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
69 reg = <500 80>; 60 reg = <500 80>;
70 }; 61 };
71 62
72 gpt@600 { // General Purpose Timer 63 timer@600 { // General Purpose Timer
73 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 64 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
74 reg = <600 10>; 65 reg = <600 10>;
75 interrupts = <1 9 0>; 66 interrupts = <1 9 0>;
@@ -77,35 +68,35 @@
77 fsl,has-wdt; 68 fsl,has-wdt;
78 }; 69 };
79 70
80 gpt@610 { // General Purpose Timer 71 timer@610 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 72 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <610 10>; 73 reg = <610 10>;
83 interrupts = <1 a 0>; 74 interrupts = <1 a 0>;
84 interrupt-parent = <&mpc5200_pic>; 75 interrupt-parent = <&mpc5200_pic>;
85 }; 76 };
86 77
87 gpt@620 { // General Purpose Timer 78 timer@620 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 79 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 reg = <620 10>; 80 reg = <620 10>;
90 interrupts = <1 b 0>; 81 interrupts = <1 b 0>;
91 interrupt-parent = <&mpc5200_pic>; 82 interrupt-parent = <&mpc5200_pic>;
92 }; 83 };
93 84
94 gpt@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
96 reg = <630 10>; 87 reg = <630 10>;
97 interrupts = <1 c 0>; 88 interrupts = <1 c 0>;
98 interrupt-parent = <&mpc5200_pic>; 89 interrupt-parent = <&mpc5200_pic>;
99 }; 90 };
100 91
101 gpt@640 { // General Purpose Timer 92 timer@640 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <640 10>; 94 reg = <640 10>;
104 interrupts = <1 d 0>; 95 interrupts = <1 d 0>;
105 interrupt-parent = <&mpc5200_pic>; 96 interrupt-parent = <&mpc5200_pic>;
106 }; 97 };
107 98
108 gpt@650 { // General Purpose Timer 99 timer@650 { // General Purpose Timer
109 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
110 reg = <650 10>; 101 reg = <650 10>;
111 interrupts = <1 e 0>; 102 interrupts = <1 e 0>;
@@ -130,28 +121,28 @@
130 }; 121 };
131 122
132 rtc@800 { // Real time clock 123 rtc@800 { // Real time clock
133 compatible = "mpc5200b-rtc","mpc5200-rtc"; 124 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
134 reg = <800 100>; 125 reg = <800 100>;
135 interrupts = <1 5 0 1 6 0>; 126 interrupts = <1 5 0 1 6 0>;
136 interrupt-parent = <&mpc5200_pic>; 127 interrupt-parent = <&mpc5200_pic>;
137 }; 128 };
138 129
139 mscan@980 { 130 mscan@980 {
140 compatible = "mpc5200b-mscan","mpc5200-mscan"; 131 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
141 interrupts = <2 12 0>; 132 interrupts = <2 12 0>;
142 interrupt-parent = <&mpc5200_pic>; 133 interrupt-parent = <&mpc5200_pic>;
143 reg = <980 80>; 134 reg = <980 80>;
144 }; 135 };
145 136
146 gpio@b00 { 137 gpio@b00 {
147 compatible = "mpc5200b-gpio","mpc5200-gpio"; 138 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
148 reg = <b00 40>; 139 reg = <b00 40>;
149 interrupts = <1 7 0>; 140 interrupts = <1 7 0>;
150 interrupt-parent = <&mpc5200_pic>; 141 interrupt-parent = <&mpc5200_pic>;
151 }; 142 };
152 143
153 gpio-wkup@c00 { 144 gpio@c00 {
154 compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup"; 145 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
155 reg = <c00 40>; 146 reg = <c00 40>;
156 interrupts = <1 8 0 0 3 0>; 147 interrupts = <1 8 0 0 3 0>;
157 interrupt-parent = <&mpc5200_pic>; 148 interrupt-parent = <&mpc5200_pic>;
@@ -159,21 +150,21 @@
159 150
160 151
161 spi@f00 { 152 spi@f00 {
162 compatible = "mpc5200b-spi","mpc5200-spi"; 153 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
163 reg = <f00 20>; 154 reg = <f00 20>;
164 interrupts = <2 d 0 2 e 0>; 155 interrupts = <2 d 0 2 e 0>;
165 interrupt-parent = <&mpc5200_pic>; 156 interrupt-parent = <&mpc5200_pic>;
166 }; 157 };
167 158
168 usb@1000 { 159 usb@1000 {
169 compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be"; 160 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
170 reg = <1000 ff>; 161 reg = <1000 ff>;
171 interrupts = <2 6 0>; 162 interrupts = <2 6 0>;
172 interrupt-parent = <&mpc5200_pic>; 163 interrupt-parent = <&mpc5200_pic>;
173 }; 164 };
174 165
175 dma-controller@1200 { 166 dma-controller@1200 {
176 compatible = "mpc5200b-bestcomm","mpc5200-bestcomm"; 167 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
177 reg = <1200 80>; 168 reg = <1200 80>;
178 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 169 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
179 3 4 0 3 5 0 3 6 0 3 7 0 170 3 4 0 3 5 0 3 6 0 3 7 0
@@ -183,13 +174,13 @@
183 }; 174 };
184 175
185 xlb@1f00 { 176 xlb@1f00 {
186 compatible = "mpc5200b-xlb","mpc5200-xlb"; 177 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
187 reg = <1f00 100>; 178 reg = <1f00 100>;
188 }; 179 };
189 180
190 serial@2000 { // PSC1 181 serial@2000 { // PSC1
191 device_type = "serial"; 182 device_type = "serial";
192 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 183 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
193 port-number = <0>; // Logical port assignment 184 port-number = <0>; // Logical port assignment
194 reg = <2000 100>; 185 reg = <2000 100>;
195 interrupts = <2 1 0>; 186 interrupts = <2 1 0>;
@@ -198,7 +189,7 @@
198 189
199 // PSC2 in spi master mode 190 // PSC2 in spi master mode
200 spi@2200 { // PSC2 191 spi@2200 { // PSC2
201 compatible = "mpc5200b-psc-spi","mpc5200-psc-spi"; 192 compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
202 cell-index = <1>; 193 cell-index = <1>;
203 reg = <2200 100>; 194 reg = <2200 100>;
204 interrupts = <2 2 0>; 195 interrupts = <2 2 0>;
@@ -208,7 +199,7 @@
208 // PSC5 in uart mode 199 // PSC5 in uart mode
209 serial@2800 { // PSC5 200 serial@2800 { // PSC5
210 device_type = "serial"; 201 device_type = "serial";
211 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart"; 202 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
212 port-number = <4>; // Logical port assignment 203 port-number = <4>; // Logical port assignment
213 reg = <2800 100>; 204 reg = <2800 100>;
214 interrupts = <2 c 0>; 205 interrupts = <2 c 0>;
@@ -217,22 +208,22 @@
217 208
218 ethernet@3000 { 209 ethernet@3000 {
219 device_type = "network"; 210 device_type = "network";
220 compatible = "mpc5200b-fec","mpc5200-fec"; 211 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
221 reg = <3000 800>; 212 reg = <3000 800>;
222 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ 213 local-mac-address = [ 00 00 00 00 00 00 ];
223 interrupts = <2 5 0>; 214 interrupts = <2 5 0>;
224 interrupt-parent = <&mpc5200_pic>; 215 interrupt-parent = <&mpc5200_pic>;
225 }; 216 };
226 217
227 ata@3a00 { 218 ata@3a00 {
228 compatible = "mpc5200b-ata","mpc5200-ata"; 219 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
229 reg = <3a00 100>; 220 reg = <3a00 100>;
230 interrupts = <2 7 0>; 221 interrupts = <2 7 0>;
231 interrupt-parent = <&mpc5200_pic>; 222 interrupt-parent = <&mpc5200_pic>;
232 }; 223 };
233 224
234 i2c@3d40 { 225 i2c@3d40 {
235 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c"; 226 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
236 reg = <3d40 40>; 227 reg = <3d40 40>;
237 interrupts = <2 10 0>; 228 interrupts = <2 10 0>;
238 interrupt-parent = <&mpc5200_pic>; 229 interrupt-parent = <&mpc5200_pic>;
@@ -240,13 +231,12 @@
240 }; 231 };
241 232
242 sram@8000 { 233 sram@8000 {
243 compatible = "mpc5200b-sram","mpc5200-sram"; 234 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
244 reg = <8000 4000>; 235 reg = <8000 4000>;
245 }; 236 };
246 }; 237 };
247 238
248 lpb { 239 lpb {
249 model = "fsl,lpb";
250 compatible = "fsl,lpb"; 240 compatible = "fsl,lpb";
251 #address-cells = <2>; 241 #address-cells = <2>;
252 #size-cells = <1>; 242 #size-cells = <1>;
@@ -288,7 +278,7 @@
288 #size-cells = <2>; 278 #size-cells = <2>;
289 #address-cells = <3>; 279 #address-cells = <3>;
290 device_type = "pci"; 280 device_type = "pci";
291 compatible = "mpc5200b-pci","mpc5200-pci"; 281 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
292 reg = <f0000d00 100>; 282 reg = <f0000d00 100>;
293 interrupt-map-mask = <f800 0 0 7>; 283 interrupt-map-mask = <f800 0 0 7>;
294 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot 284 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index 58c9799caf16..c86464f007da 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -10,12 +10,6 @@
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12 12
13/*
14 * WARNING: Do not depend on this tree layout remaining static just yet.
15 * The MPC5200 device tree conventions are still in flux
16 * Keep an eye on the linuxppc-dev mailing list for more details
17 */
18
19/ { 13/ {
20 model = "tqc,tqm5200"; 14 model = "tqc,tqm5200";
21 compatible = "tqc,tqm5200"; 15 compatible = "tqc,tqm5200";
@@ -47,29 +41,26 @@
47 soc5200@f0000000 { 41 soc5200@f0000000 {
48 #address-cells = <1>; 42 #address-cells = <1>;
49 #size-cells = <1>; 43 #size-cells = <1>;
50 model = "fsl,mpc5200"; 44 compatible = "fsl,mpc5200-immr";
51 compatible = "fsl,mpc5200";
52 revision = ""; // from bootloader
53 device_type = "soc";
54 ranges = <0 f0000000 0000c000>; 45 ranges = <0 f0000000 0000c000>;
55 reg = <f0000000 00000100>; 46 reg = <f0000000 00000100>;
56 bus-frequency = <0>; // from bootloader 47 bus-frequency = <0>; // from bootloader
57 system-frequency = <0>; // from bootloader 48 system-frequency = <0>; // from bootloader
58 49
59 cdm@200 { 50 cdm@200 {
60 compatible = "mpc5200-cdm"; 51 compatible = "fsl,mpc5200-cdm";
61 reg = <200 38>; 52 reg = <200 38>;
62 }; 53 };
63 54
64 mpc5200_pic: pic@500 { 55 mpc5200_pic: interrupt-controller@500 {
65 // 5200 interrupts are encoded into two levels; 56 // 5200 interrupts are encoded into two levels;
66 interrupt-controller; 57 interrupt-controller;
67 #interrupt-cells = <3>; 58 #interrupt-cells = <3>;
68 compatible = "mpc5200-pic"; 59 compatible = "fsl,mpc5200-pic";
69 reg = <500 80>; 60 reg = <500 80>;
70 }; 61 };
71 62
72 gpt@600 { // General Purpose Timer 63 timer@600 { // General Purpose Timer
73 compatible = "fsl,mpc5200-gpt"; 64 compatible = "fsl,mpc5200-gpt";
74 reg = <600 10>; 65 reg = <600 10>;
75 interrupts = <1 9 0>; 66 interrupts = <1 9 0>;
@@ -78,21 +69,21 @@
78 }; 69 };
79 70
80 gpio@b00 { 71 gpio@b00 {
81 compatible = "mpc5200-gpio"; 72 compatible = "fsl,mpc5200-gpio";
82 reg = <b00 40>; 73 reg = <b00 40>;
83 interrupts = <1 7 0>; 74 interrupts = <1 7 0>;
84 interrupt-parent = <&mpc5200_pic>; 75 interrupt-parent = <&mpc5200_pic>;
85 }; 76 };
86 77
87 usb@1000 { 78 usb@1000 {
88 compatible = "mpc5200-ohci","ohci-be"; 79 compatible = "fsl,mpc5200-ohci","ohci-be";
89 reg = <1000 ff>; 80 reg = <1000 ff>;
90 interrupts = <2 6 0>; 81 interrupts = <2 6 0>;
91 interrupt-parent = <&mpc5200_pic>; 82 interrupt-parent = <&mpc5200_pic>;
92 }; 83 };
93 84
94 dma-controller@1200 { 85 dma-controller@1200 {
95 compatible = "mpc5200-bestcomm"; 86 compatible = "fsl,mpc5200-bestcomm";
96 reg = <1200 80>; 87 reg = <1200 80>;
97 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 88 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
98 3 4 0 3 5 0 3 6 0 3 7 0 89 3 4 0 3 5 0 3 6 0 3 7 0
@@ -102,13 +93,13 @@
102 }; 93 };
103 94
104 xlb@1f00 { 95 xlb@1f00 {
105 compatible = "mpc5200-xlb"; 96 compatible = "fsl,mpc5200-xlb";
106 reg = <1f00 100>; 97 reg = <1f00 100>;
107 }; 98 };
108 99
109 serial@2000 { // PSC1 100 serial@2000 { // PSC1
110 device_type = "serial"; 101 device_type = "serial";
111 compatible = "mpc5200-psc-uart"; 102 compatible = "fsl,mpc5200-psc-uart";
112 port-number = <0>; // Logical port assignment 103 port-number = <0>; // Logical port assignment
113 reg = <2000 100>; 104 reg = <2000 100>;
114 interrupts = <2 1 0>; 105 interrupts = <2 1 0>;
@@ -117,7 +108,7 @@
117 108
118 serial@2200 { // PSC2 109 serial@2200 { // PSC2
119 device_type = "serial"; 110 device_type = "serial";
120 compatible = "mpc5200-psc-uart"; 111 compatible = "fsl,mpc5200-psc-uart";
121 port-number = <1>; // Logical port assignment 112 port-number = <1>; // Logical port assignment
122 reg = <2200 100>; 113 reg = <2200 100>;
123 interrupts = <2 2 0>; 114 interrupts = <2 2 0>;
@@ -126,7 +117,7 @@
126 117
127 serial@2400 { // PSC3 118 serial@2400 { // PSC3
128 device_type = "serial"; 119 device_type = "serial";
129 compatible = "mpc5200-psc-uart"; 120 compatible = "fsl,mpc5200-psc-uart";
130 port-number = <2>; // Logical port assignment 121 port-number = <2>; // Logical port assignment
131 reg = <2400 100>; 122 reg = <2400 100>;
132 interrupts = <2 3 0>; 123 interrupts = <2 3 0>;
@@ -135,22 +126,22 @@
135 126
136 ethernet@3000 { 127 ethernet@3000 {
137 device_type = "network"; 128 device_type = "network";
138 compatible = "mpc5200-fec"; 129 compatible = "fsl,mpc5200-fec";
139 reg = <3000 800>; 130 reg = <3000 800>;
140 local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ 131 local-mac-address = [ 00 00 00 00 00 00 ];
141 interrupts = <2 5 0>; 132 interrupts = <2 5 0>;
142 interrupt-parent = <&mpc5200_pic>; 133 interrupt-parent = <&mpc5200_pic>;
143 }; 134 };
144 135
145 ata@3a00 { 136 ata@3a00 {
146 compatible = "mpc5200-ata"; 137 compatible = "fsl,mpc5200-ata";
147 reg = <3a00 100>; 138 reg = <3a00 100>;
148 interrupts = <2 7 0>; 139 interrupts = <2 7 0>;
149 interrupt-parent = <&mpc5200_pic>; 140 interrupt-parent = <&mpc5200_pic>;
150 }; 141 };
151 142
152 i2c@3d40 { 143 i2c@3d40 {
153 compatible = "mpc5200-i2c","fsl-i2c"; 144 compatible = "fsl,mpc5200-i2c","fsl-i2c";
154 reg = <3d40 40>; 145 reg = <3d40 40>;
155 interrupts = <2 10 0>; 146 interrupts = <2 10 0>;
156 interrupt-parent = <&mpc5200_pic>; 147 interrupt-parent = <&mpc5200_pic>;
@@ -158,7 +149,7 @@
158 }; 149 };
159 150
160 sram@8000 { 151 sram@8000 {
161 compatible = "mpc5200-sram"; 152 compatible = "fsl,mpc5200-sram";
162 reg = <8000 4000>; 153 reg = <8000 4000>;
163 }; 154 };
164 }; 155 };
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index b6c68ef46809..9960421eb6b9 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -126,7 +126,7 @@ int serial_console_init(void)
126 dt_is_compatible(devp, "fsl,cpm2-scc-uart") || 126 dt_is_compatible(devp, "fsl,cpm2-scc-uart") ||
127 dt_is_compatible(devp, "fsl,cpm2-smc-uart")) 127 dt_is_compatible(devp, "fsl,cpm2-smc-uart"))
128 rc = cpm_console_init(devp, &serial_cd); 128 rc = cpm_console_init(devp, &serial_cd);
129 else if (dt_is_compatible(devp, "mpc5200-psc-uart")) 129 else if (dt_is_compatible(devp, "fsl,mpc5200-psc-uart"))
130 rc = mpc5200_psc_console_init(devp, &serial_cd); 130 rc = mpc5200_psc_console_init(devp, &serial_cd);
131 else if (dt_is_compatible(devp, "xlnx,opb-uartlite-1.00.b") || 131 else if (dt_is_compatible(devp, "xlnx,opb-uartlite-1.00.b") ||
132 dt_is_compatible(devp, "xlnx,xps-uartlite-1.00.a")) 132 dt_is_compatible(devp, "xlnx,xps-uartlite-1.00.a"))
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 04:50:20 -0500