e1000e: cosmetic move of #defines and prototypes to the new ich8lan.h

Move #defines and function prototypes specific to the ICH/PCH family of
devices (ICH8/82562, ICH8/82566, ICH8/82567, ICH9/82562, ICH9/82566,
ICH9/82567, ICH10/82567, 82577, 82578, 82579, I217, I218) to the new
ich8lan.h header file (the convention for Intel wired ethernet drivers is
to use the name of the first device in the family for related file and
function names).  These defines and function prototypes can be used by
other files in the driver and moving them to the ICH/PCH-family-specific
file makes it clearer to which devices they are applicable.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

6 files changed, 270 insertions, 230 deletions

diff --git a/drivers/net/ethernet/intel/e1000e/defines.h b/drivers/net/ethernet/intel/e1000e/defines.h
index b425544144ec..fc3a4fe1ac71 100644
--- a/drivers/net/ethernet/intel/e1000e/defines.h
+++ b/drivers/net/ethernet/intel/e1000e/defines.h
@@ -749,38 +749,6 @@
 /* BME1000 PHY Specific Control Register */
 #define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */
 
-/* PHY Low Power Idle Control */
-#define I82579_LPI_CTRL                         PHY_REG(772, 20)
-#define I82579_LPI_CTRL_100_ENABLE              0x2000
-#define I82579_LPI_CTRL_1000_ENABLE             0x4000
-#define I82579_LPI_CTRL_ENABLE_MASK             0x6000
-#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT    0x80
-
-/* Extended Management Interface (EMI) Registers */
-#define I82579_EMI_ADDR         0x10
-#define I82579_EMI_DATA         0x11
-#define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
-#define I82579_MSE_THRESHOLD    0x084F  /* 82579 Mean Square Error Threshold */
-#define I82577_MSE_THRESHOLD    0x0887  /* 82577 Mean Square Error Threshold */
-#define I82579_MSE_LINK_DOWN    0x2411  /* MSE count before dropping link */
-#define I82579_EEE_PCS_STATUS   0x182D  /* IEEE MMD Register 3.1 >> 8 */
-#define I82579_EEE_CAPABILITY   0x0410  /* IEEE MMD Register 3.20 */
-#define I82579_EEE_ADVERTISEMENT        0x040E  /* IEEE MMD Register 7.60 */
-#define I82579_EEE_LP_ABILITY           0x040F  /* IEEE MMD Register 7.61 */
-#define I82579_EEE_100_SUPPORTED        (1 << 1) /* 100BaseTx EEE supported */
-#define I82579_EEE_1000_SUPPORTED       (1 << 2) /* 1000BaseTx EEE supported */
-#define I217_EEE_PCS_STATUS     0x9401  /* IEEE MMD Register 3.1 */
-#define I217_EEE_CAPABILITY     0x8000  /* IEEE MMD Register 3.20 */
-#define I217_EEE_ADVERTISEMENT  0x8001  /* IEEE MMD Register 7.60 */
-#define I217_EEE_LP_ABILITY     0x8002  /* IEEE MMD Register 7.61 */
-
-#define E1000_EEE_RX_LPI_RCVD   0x0400  /* Tx LP idle received */
-#define E1000_EEE_TX_LPI_RCVD   0x0800  /* Rx LP idle received */
-
-#define PHY_PAGE_SHIFT 5
-#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
-                           ((reg) & MAX_PHY_REG_ADDRESS))
-
 /* Bits...
  * 15-5: page
  * 4-0: register offset
@@ -827,8 +795,4 @@
 /* SerDes Control */
 #define E1000_GEN_POLL_TIMEOUT          640
 
-/* FW Semaphore */
-#define E1000_FWSM_WLOCK_MAC_MASK       0x0380
-#define E1000_FWSM_WLOCK_MAC_SHIFT      7
-
 #endif /* _E1000_DEFINES_H_ */
diff --git a/drivers/net/ethernet/intel/e1000e/e1000.h b/drivers/net/ethernet/intel/e1000e/e1000.h
index 12c5d4043505..7a383cd715d6 100644
--- a/drivers/net/ethernet/intel/e1000e/e1000.h
+++ b/drivers/net/ethernet/intel/e1000e/e1000.h
@@ -104,44 +104,6 @@ struct e1000_info;
          (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
          (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
 
-/* PHY Wakeup Registers and defines */
-#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
-#define BM_RCTL         PHY_REG(BM_WUC_PAGE, 0)
-#define BM_WUC          PHY_REG(BM_WUC_PAGE, 1)
-#define BM_WUFC         PHY_REG(BM_WUC_PAGE, 2)
-#define BM_WUS          PHY_REG(BM_WUC_PAGE, 3)
-#define BM_RAR_L(_i)    (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
-#define BM_RAR_M(_i)    (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
-#define BM_RAR_H(_i)    (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
-#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
-#define BM_MTA(_i)      (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
-
-#define BM_RCTL_UPE           0x0001          /* Unicast Promiscuous Mode */
-#define BM_RCTL_MPE           0x0002          /* Multicast Promiscuous Mode */
-#define BM_RCTL_MO_SHIFT      3               /* Multicast Offset Shift */
-#define BM_RCTL_MO_MASK       (3 << 3)        /* Multicast Offset Mask */
-#define BM_RCTL_BAM           0x0020          /* Broadcast Accept Mode */
-#define BM_RCTL_PMCF          0x0040          /* Pass MAC Control Frames */
-#define BM_RCTL_RFCE          0x0080          /* Rx Flow Control Enable */
-
-#define HV_STATS_PAGE   778
-#define HV_SCC_UPPER    PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
-#define HV_SCC_LOWER    PHY_REG(HV_STATS_PAGE, 17)
-#define HV_ECOL_UPPER   PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
-#define HV_ECOL_LOWER   PHY_REG(HV_STATS_PAGE, 19)
-#define HV_MCC_UPPER    PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
-#define HV_MCC_LOWER    PHY_REG(HV_STATS_PAGE, 21)
-#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
-#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
-#define HV_COLC_UPPER   PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
-#define HV_COLC_LOWER   PHY_REG(HV_STATS_PAGE, 26)
-#define HV_DC_UPPER     PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
-#define HV_DC_LOWER     PHY_REG(HV_STATS_PAGE, 28)
-#define HV_TNCRS_UPPER  PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
-#define HV_TNCRS_LOWER  PHY_REG(HV_STATS_PAGE, 30)
-
-#define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */
-
 /* BM PHY Copper Specific Status */
 #define BM_CS_STATUS                      17
 #define BM_CS_STATUS_LINK_UP              0x0400
@@ -156,9 +118,6 @@ struct e1000_info;
 #define HV_M_STATUS_SPEED_1000            0x0200
 #define HV_M_STATUS_LINK_UP               0x0040
 
-#define E1000_ICH_FWSM_PCIM2PCI         0x01000000 /* ME PCIm-to-PCI active */
-#define E1000_ICH_FWSM_PCIM2PCI_COUNT   2000
-
 /* Time to wait before putting the device into D3 if there's no link (in ms). */
 #define LINK_TIMEOUT            100
 
@@ -579,17 +538,6 @@ extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
 
 extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
 
-extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
-extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
-                                                 bool state);
-extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
-extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
-extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
-extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
-extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
-extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
-extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
-
 extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
 extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
 extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
@@ -700,7 +648,6 @@ extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
 extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
 extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
 extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
-extern s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
 extern void e1000e_ptp_init(struct e1000_adapter *adapter);
 extern void e1000e_ptp_remove(struct e1000_adapter *adapter);
 
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index 8a145f468721..21a9cc36e467 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -200,10 +200,6 @@ enum e1e_registers {
 #define E1000_RA        (E1000_RAL(0))
         E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
 #define E1000_RAH(_n)   (E1000_RAH_BASE + ((_n) * 8))
-        E1000_SHRAL_PCH_LPT_BASE = 0x05408,
-#define E1000_SHRAL_PCH_LPT(_n)   (E1000_SHRAL_PCH_LPT_BASE + ((_n) * 8))
-        E1000_SHRAH_PCH_LTP_BASE = 0x0540C,
-#define E1000_SHRAH_PCH_LPT(_n)   (E1000_SHRAH_PCH_LTP_BASE + ((_n) * 8))
         E1000_SHRAL_BASE = 0x05438, /* Shared Receive Address Low - RW */
 #define E1000_SHRAL(_n)   (E1000_SHRAL_BASE + ((_n) * 8))
         E1000_SHRAH_BASE = 0x0543C, /* Shared Receive Address High - RW */
@@ -215,6 +211,7 @@ enum e1e_registers {
         E1000_MRQC     = 0x05818, /* Multiple Receive Control - RW */
         E1000_MANC     = 0x05820, /* Management Control - RW */
         E1000_FFLT     = 0x05F00, /* Flexible Filter Length Table - RW Array */
+        E1000_CRC_OFFSET = 0x05F50, /* CRC Offset register */
         E1000_HOST_IF  = 0x08800, /* Host Interface */
 
         E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
@@ -233,9 +230,6 @@ enum e1e_registers {
         E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
 #define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4))
         E1000_FFLT_DBG  = 0x05F04, /* Debug Register */
-        E1000_PCH_RAICC_BASE = 0x05F50, /* Receive Address Initial CRC */
-#define E1000_PCH_RAICC(_n)     (E1000_PCH_RAICC_BASE + ((_n) * 4))
-#define E1000_CRC_OFFSET        E1000_PCH_RAICC_BASE
         E1000_HICR      = 0x08F00, /* Host Interface Control */
         E1000_SYSTIML   = 0x0B600, /* System time register Low - RO */
         E1000_SYSTIMH   = 0x0B604, /* System time register High - RO */
@@ -272,10 +266,6 @@ enum e1e_registers {
 #define BM_WUC_HOST_WU_BIT              (1 << 4)
 #define BM_WUC_ME_WU_BIT                (1 << 5)
 
-#define BM_WUC  PHY_REG(BM_WUC_PAGE, 1)
-#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
-#define BM_WUS  PHY_REG(BM_WUC_PAGE, 3)
-
 #define IGP01E1000_PHY_PCS_INIT_REG     0x00B4
 #define IGP01E1000_PHY_POLARITY_MASK    0x0078
 
@@ -1004,5 +994,6 @@ struct e1000_hw {
 
 #include "82571.h"
 #include "80003es2lan.h"
+#include "ich8lan.h"
 
 #endif
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index a019b46f30e2..1e838b235e8a 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -57,132 +57,6 @@
 
 #include "e1000.h"
 
-#define ICH_FLASH_GFPREG                0x0000
-#define ICH_FLASH_HSFSTS                0x0004
-#define ICH_FLASH_HSFCTL                0x0006
-#define ICH_FLASH_FADDR                 0x0008
-#define ICH_FLASH_FDATA0                0x0010
-#define ICH_FLASH_PR0                   0x0074
-
-#define ICH_FLASH_READ_COMMAND_TIMEOUT  500
-#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
-#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
-#define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
-#define ICH_FLASH_CYCLE_REPEAT_COUNT    10
-
-#define ICH_CYCLE_READ                  0
-#define ICH_CYCLE_WRITE                 2
-#define ICH_CYCLE_ERASE                 3
-
-#define FLASH_GFPREG_BASE_MASK          0x1FFF
-#define FLASH_SECTOR_ADDR_SHIFT         12
-
-#define ICH_FLASH_SEG_SIZE_256          256
-#define ICH_FLASH_SEG_SIZE_4K           4096
-#define ICH_FLASH_SEG_SIZE_8K           8192
-#define ICH_FLASH_SEG_SIZE_64K          65536
-
-
-#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
-/* FW established a valid mode */
-#define E1000_ICH_FWSM_FW_VALID         0x00008000
-
-#define E1000_ICH_MNG_IAMT_MODE         0x2
-
-#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
-                                 (ID_LED_DEF1_OFF2 <<  8) | \
-                                 (ID_LED_DEF1_ON2  <<  4) | \
-                                 (ID_LED_DEF1_DEF2))
-
-#define E1000_ICH_NVM_SIG_WORD          0x13
-#define E1000_ICH_NVM_SIG_MASK          0xC000
-#define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
-#define E1000_ICH_NVM_SIG_VALUE         0x80
-
-#define E1000_ICH8_LAN_INIT_TIMEOUT     1500
-
-#define E1000_FEXTNVM_SW_CONFIG         1
-#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
-
-#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK    0x0C000000
-#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC  0x08000000
-
-#define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
-#define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
-#define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
-
-#define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
-
-#define E1000_ICH_RAR_ENTRIES           7
-#define E1000_PCH2_RAR_ENTRIES          5 /* RAR[0], SHRA[0-3] */
-#define E1000_PCH_LPT_RAR_ENTRIES       12 /* RAR[0], SHRA[0-10] */
-
-#define PHY_PAGE_SHIFT 5
-#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
-                           ((reg) & MAX_PHY_REG_ADDRESS))
-#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
-#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
-
-#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
-#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
-#define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
-
-#define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
-
-#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
-
-/* SMBus Control Phy Register */
-#define CV_SMB_CTRL             PHY_REG(769, 23)
-#define CV_SMB_CTRL_FORCE_SMBUS 0x0001
-
-/* SMBus Address Phy Register */
-#define HV_SMB_ADDR            PHY_REG(768, 26)
-#define HV_SMB_ADDR_MASK       0x007F
-#define HV_SMB_ADDR_PEC_EN     0x0200
-#define HV_SMB_ADDR_VALID      0x0080
-#define HV_SMB_ADDR_FREQ_MASK           0x1100
-#define HV_SMB_ADDR_FREQ_LOW_SHIFT      8
-#define HV_SMB_ADDR_FREQ_HIGH_SHIFT     12
-
-/* PHY Power Management Control */
-#define HV_PM_CTRL              PHY_REG(770, 17)
-#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA  0x100
-
-/* Intel Rapid Start Technology Support */
-#define I217_PROXY_CTRL                 BM_PHY_REG(BM_WUC_PAGE, 70)
-#define I217_PROXY_CTRL_AUTO_DISABLE    0x0080
-#define I217_SxCTRL                     PHY_REG(BM_PORT_CTRL_PAGE, 28)
-#define I217_SxCTRL_ENABLE_LPI_RESET    0x1000
-#define I217_CGFREG                     PHY_REG(772, 29)
-#define I217_CGFREG_ENABLE_MTA_RESET    0x0002
-#define I217_MEMPWR                     PHY_REG(772, 26)
-#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
-
-/* Strapping Option Register - RO */
-#define E1000_STRAP                     0x0000C
-#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
-#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
-#define E1000_STRAP_SMT_FREQ_MASK       0x00003000
-#define E1000_STRAP_SMT_FREQ_SHIFT      12
-
-/* OEM Bits Phy Register */
-#define HV_OEM_BITS            PHY_REG(768, 25)
-#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
-#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
-#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
-
-#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
-#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
-
-/* KMRN Mode Control */
-#define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
-#define HV_KMRN_MDIO_SLOW      0x0400
-
-/* KMRN FIFO Control and Status */
-#define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)
-#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000
-#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12
-
 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 /* Offset 04h HSFSTS */
 union ich8_hws_flash_status {
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h
new file mode 100644
index 000000000000..b6d3174d7d2d
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h
@@ -0,0 +1,268 @@
+/*******************************************************************************
+
+  Intel PRO/1000 Linux driver
+  Copyright(c) 1999 - 2013 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  Linux NICS <linux.nics@intel.com>
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#ifndef _E1000E_ICH8LAN_H_
+#define _E1000E_ICH8LAN_H_
+
+#define ICH_FLASH_GFPREG                0x0000
+#define ICH_FLASH_HSFSTS                0x0004
+#define ICH_FLASH_HSFCTL                0x0006
+#define ICH_FLASH_FADDR                 0x0008
+#define ICH_FLASH_FDATA0                0x0010
+#define ICH_FLASH_PR0                   0x0074
+
+/* Requires up to 10 seconds when MNG might be accessing part. */
+#define ICH_FLASH_READ_COMMAND_TIMEOUT  10000000
+#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
+#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
+#define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
+#define ICH_FLASH_CYCLE_REPEAT_COUNT    10
+
+#define ICH_CYCLE_READ                  0
+#define ICH_CYCLE_WRITE                 2
+#define ICH_CYCLE_ERASE                 3
+
+#define FLASH_GFPREG_BASE_MASK          0x1FFF
+#define FLASH_SECTOR_ADDR_SHIFT         12
+
+#define ICH_FLASH_SEG_SIZE_256          256
+#define ICH_FLASH_SEG_SIZE_4K           4096
+#define ICH_FLASH_SEG_SIZE_8K           8192
+#define ICH_FLASH_SEG_SIZE_64K          65536
+
+#define E1000_ICH_FWSM_RSPCIPHY 0x00000040      /* Reset PHY on PCI Reset */
+/* FW established a valid mode */
+#define E1000_ICH_FWSM_FW_VALID 0x00008000
+#define E1000_ICH_FWSM_PCIM2PCI 0x01000000      /* ME PCIm-to-PCI active */
+#define E1000_ICH_FWSM_PCIM2PCI_COUNT   2000
+
+#define E1000_ICH_MNG_IAMT_MODE         0x2
+
+#define E1000_FWSM_WLOCK_MAC_MASK       0x0380
+#define E1000_FWSM_WLOCK_MAC_SHIFT      7
+
+/* Shared Receive Address Registers */
+#define E1000_SHRAL_PCH_LPT(_i)         (0x05408 + ((_i) * 8))
+#define E1000_SHRAH_PCH_LPT(_i)         (0x0540C + ((_i) * 8))
+
+#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
+                                 (ID_LED_OFF1_OFF2 <<  8) | \
+                                 (ID_LED_OFF1_ON2  <<  4) | \
+                                 (ID_LED_DEF1_DEF2))
+
+#define E1000_ICH_NVM_SIG_WORD          0x13
+#define E1000_ICH_NVM_SIG_MASK          0xC000
+#define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
+#define E1000_ICH_NVM_SIG_VALUE         0x80
+
+#define E1000_ICH8_LAN_INIT_TIMEOUT     1500
+
+#define E1000_FEXTNVM_SW_CONFIG         1
+#define E1000_FEXTNVM_SW_CONFIG_ICH8M   (1 << 27)       /* different on ICH8M */
+
+#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK     0x0C000000
+#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC   0x08000000
+
+#define E1000_FEXTNVM4_BEACON_DURATION_MASK     0x7
+#define E1000_FEXTNVM4_BEACON_DURATION_8USEC    0x7
+#define E1000_FEXTNVM4_BEACON_DURATION_16USEC   0x3
+
+#define PCIE_ICH8_SNOOP_ALL     PCIE_NO_SNOOP_ALL
+
+#define E1000_ICH_RAR_ENTRIES   7
+#define E1000_PCH2_RAR_ENTRIES  5       /* RAR[0], SHRA[0-3] */
+#define E1000_PCH_LPT_RAR_ENTRIES       12      /* RAR[0], SHRA[0-10] */
+
+#define PHY_PAGE_SHIFT          5
+#define PHY_REG(page, reg)      (((page) << PHY_PAGE_SHIFT) | \
+                                 ((reg) & MAX_PHY_REG_ADDRESS))
+#define IGP3_KMRN_DIAG  PHY_REG(770, 19)        /* KMRN Diagnostic */
+#define IGP3_VR_CTRL    PHY_REG(776, 18)        /* Voltage Regulator Control */
+
+#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS            0x0002
+#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK    0x0300
+#define IGP3_VR_CTRL_MODE_SHUTDOWN              0x0200
+
+/* PHY Wakeup Registers and defines */
+#define BM_PORT_GEN_CFG         PHY_REG(BM_PORT_CTRL_PAGE, 17)
+#define BM_RCTL                 PHY_REG(BM_WUC_PAGE, 0)
+#define BM_WUC                  PHY_REG(BM_WUC_PAGE, 1)
+#define BM_WUFC                 PHY_REG(BM_WUC_PAGE, 2)
+#define BM_WUS                  PHY_REG(BM_WUC_PAGE, 3)
+#define BM_RAR_L(_i)            (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
+#define BM_RAR_M(_i)            (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
+#define BM_RAR_H(_i)            (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
+#define BM_RAR_CTRL(_i)         (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
+#define BM_MTA(_i)              (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
+
+#define BM_RCTL_UPE             0x0001  /* Unicast Promiscuous Mode */
+#define BM_RCTL_MPE             0x0002  /* Multicast Promiscuous Mode */
+#define BM_RCTL_MO_SHIFT        3       /* Multicast Offset Shift */
+#define BM_RCTL_MO_MASK         (3 << 3)        /* Multicast Offset Mask */
+#define BM_RCTL_BAM             0x0020  /* Broadcast Accept Mode */
+#define BM_RCTL_PMCF            0x0040  /* Pass MAC Control Frames */
+#define BM_RCTL_RFCE            0x0080  /* Rx Flow Control Enable */
+
+#define HV_LED_CONFIG           PHY_REG(768, 30)        /* LED Configuration */
+#define HV_MUX_DATA_CTRL        PHY_REG(776, 16)
+#define HV_MUX_DATA_CTRL_GEN_TO_MAC     0x0400
+#define HV_MUX_DATA_CTRL_FORCE_SPEED    0x0004
+#define HV_STATS_PAGE   778
+/* Half-duplex collision counts */
+#define HV_SCC_UPPER    PHY_REG(HV_STATS_PAGE, 16)      /* Single Collision */
+#define HV_SCC_LOWER    PHY_REG(HV_STATS_PAGE, 17)
+#define HV_ECOL_UPPER   PHY_REG(HV_STATS_PAGE, 18)      /* Excessive Coll. */
+#define HV_ECOL_LOWER   PHY_REG(HV_STATS_PAGE, 19)
+#define HV_MCC_UPPER    PHY_REG(HV_STATS_PAGE, 20)      /* Multiple Collision */
+#define HV_MCC_LOWER    PHY_REG(HV_STATS_PAGE, 21)
+#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23)     /* Late Collision */
+#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
+#define HV_COLC_UPPER   PHY_REG(HV_STATS_PAGE, 25)      /* Collision */
+#define HV_COLC_LOWER   PHY_REG(HV_STATS_PAGE, 26)
+#define HV_DC_UPPER     PHY_REG(HV_STATS_PAGE, 27)      /* Defer Count */
+#define HV_DC_LOWER     PHY_REG(HV_STATS_PAGE, 28)
+#define HV_TNCRS_UPPER  PHY_REG(HV_STATS_PAGE, 29)      /* Tx with no CRS */
+#define HV_TNCRS_LOWER  PHY_REG(HV_STATS_PAGE, 30)
+
+#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
+
+#define E1000_NVM_K1_CONFIG     0x1B    /* NVM K1 Config Word */
+#define E1000_NVM_K1_ENABLE     0x1     /* NVM Enable K1 bit */
+
+/* SMBus Control Phy Register */
+#define CV_SMB_CTRL             PHY_REG(769, 23)
+#define CV_SMB_CTRL_FORCE_SMBUS 0x0001
+
+/* SMBus Address Phy Register */
+#define HV_SMB_ADDR             PHY_REG(768, 26)
+#define HV_SMB_ADDR_MASK        0x007F
+#define HV_SMB_ADDR_PEC_EN      0x0200
+#define HV_SMB_ADDR_VALID       0x0080
+#define HV_SMB_ADDR_FREQ_MASK           0x1100
+#define HV_SMB_ADDR_FREQ_LOW_SHIFT      8
+#define HV_SMB_ADDR_FREQ_HIGH_SHIFT     12
+
+/* Strapping Option Register - RO */
+#define E1000_STRAP                     0x0000C
+#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
+#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
+#define E1000_STRAP_SMT_FREQ_MASK       0x00003000
+#define E1000_STRAP_SMT_FREQ_SHIFT      12
+
+/* OEM Bits Phy Register */
+#define HV_OEM_BITS             PHY_REG(768, 25)
+#define HV_OEM_BITS_LPLU        0x0004  /* Low Power Link Up */
+#define HV_OEM_BITS_GBE_DIS     0x0040  /* Gigabit Disable */
+#define HV_OEM_BITS_RESTART_AN  0x0400  /* Restart Auto-negotiation */
+
+/* KMRN Mode Control */
+#define HV_KMRN_MODE_CTRL       PHY_REG(769, 16)
+#define HV_KMRN_MDIO_SLOW       0x0400
+
+/* KMRN FIFO Control and Status */
+#define HV_KMRN_FIFO_CTRLSTA                    PHY_REG(770, 16)
+#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK      0x7000
+#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT     12
+
+/* PHY Power Management Control */
+#define HV_PM_CTRL              PHY_REG(770, 17)
+#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA  0x100
+
+#define SW_FLAG_TIMEOUT         1000    /* SW Semaphore flag timeout in ms */
+
+/* PHY Low Power Idle Control */
+#define I82579_LPI_CTRL                         PHY_REG(772, 20)
+#define I82579_LPI_CTRL_100_ENABLE              0x2000
+#define I82579_LPI_CTRL_1000_ENABLE             0x4000
+#define I82579_LPI_CTRL_ENABLE_MASK             0x6000
+#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT    0x80
+
+/* Extended Management Interface (EMI) Registers */
+#define I82579_EMI_ADDR         0x10
+#define I82579_EMI_DATA         0x11
+#define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
+#define I82579_MSE_THRESHOLD    0x084F  /* 82579 Mean Square Error Threshold */
+#define I82577_MSE_THRESHOLD    0x0887  /* 82577 Mean Square Error Threshold */
+#define I82579_MSE_LINK_DOWN    0x2411  /* MSE count before dropping link */
+#define I82579_EEE_PCS_STATUS           0x182D  /* IEEE MMD Register 3.1 >> 8 */
+#define I82579_EEE_CAPABILITY           0x0410  /* IEEE MMD Register 3.20 */
+#define I82579_EEE_ADVERTISEMENT        0x040E  /* IEEE MMD Register 7.60 */
+#define I82579_EEE_LP_ABILITY           0x040F  /* IEEE MMD Register 7.61 */
+#define I82579_EEE_100_SUPPORTED        (1 << 1)        /* 100BaseTx EEE */
+#define I82579_EEE_1000_SUPPORTED       (1 << 2)        /* 1000BaseTx EEE */
+#define I217_EEE_PCS_STATUS     0x9401  /* IEEE MMD Register 3.1 */
+#define I217_EEE_CAPABILITY     0x8000  /* IEEE MMD Register 3.20 */
+#define I217_EEE_ADVERTISEMENT  0x8001  /* IEEE MMD Register 7.60 */
+#define I217_EEE_LP_ABILITY     0x8002  /* IEEE MMD Register 7.61 */
+
+#define E1000_EEE_RX_LPI_RCVD   0x0400  /* Tx LP idle received */
+#define E1000_EEE_TX_LPI_RCVD   0x0800  /* Rx LP idle received */
+
+/* Intel Rapid Start Technology Support */
+#define I217_PROXY_CTRL         BM_PHY_REG(BM_WUC_PAGE, 70)
+#define I217_PROXY_CTRL_AUTO_DISABLE    0x0080
+#define I217_SxCTRL                     PHY_REG(BM_PORT_CTRL_PAGE, 28)
+#define I217_SxCTRL_ENABLE_LPI_RESET    0x1000
+#define I217_CGFREG                     PHY_REG(772, 29)
+#define I217_CGFREG_ENABLE_MTA_RESET    0x0002
+#define I217_MEMPWR                     PHY_REG(772, 26)
+#define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
+
+/* Receive Address Initial CRC Calculation */
+#define E1000_PCH_RAICC(_n)     (0x05F50 + ((_n) * 4))
+
+/* Latency Tolerance Reporting */
+#define E1000_LTRV                      0x000F8
+#define E1000_LTRV_SCALE_MAX            5
+#define E1000_LTRV_SCALE_FACTOR         5
+#define E1000_LTRV_REQ_SHIFT            15
+#define E1000_LTRV_NOSNOOP_SHIFT        16
+#define E1000_LTRV_SEND                 (1 << 30)
+
+/* Proprietary Latency Tolerance Reporting PCI Capability */
+#define E1000_PCI_LTR_CAP_LPT           0xA8
+
+/* OBFF Control & Threshold Defines */
+#define E1000_SVCR_OFF_EN               0x00000001
+#define E1000_SVCR_OFF_MASKINT          0x00001000
+#define E1000_SVCR_OFF_TIMER_MASK       0xFFFF0000
+#define E1000_SVCR_OFF_TIMER_SHIFT      16
+#define E1000_SVT_OFF_HWM_MASK          0x0000001F
+
+void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
+void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
+                                                  bool state);
+void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
+void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
+void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
+void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
+s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
+void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
+s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
+s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
+#endif /* _E1000E_ICH8LAN_H_ */
diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c
index ae656f16c9fd..851685dd00d4 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.c
+++ b/drivers/net/ethernet/intel/e1000e/phy.c
@@ -91,10 +91,6 @@ static const u16 e1000_igp_2_cable_length_table[] = {
 /* BM PHY Copper Specific Control 1 */
 #define BM_CS_CTRL1                       16
 
-#define HV_MUX_DATA_CTRL               PHY_REG(776, 16)
-#define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400
-#define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004
-
 /**
  *  e1000e_check_reset_block_generic - Check if PHY reset is blocked
  *  @hw: pointer to the HW structure