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authorBruce Allan <bruce.w.allan@intel.com>2013-01-22 03:44:09 -0500
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2013-02-05 02:32:20 -0500
commit21b5a6f8ff3cbcd7623187628320a4e7125120fb (patch)
tree5bb69e7dd2057fc29491653a606339f6ba228ff0
parentf25701df2ef171894730534e5b557186d2bacf17 (diff)
e1000e: cosmetic move of #defines to the new 80003es2lan.h
Move #defines specific to the ESB2/82563 family of devices to the new 80003es2lan.h header file. These defines can be used by other files in the driver and moving them to the 80003es2lan-family-specific file makes it clearer to which devices they are applicable. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat
-rw-r--r--drivers/net/ethernet/intel/e1000e/80003es2lan.c63
-rw-r--r--drivers/net/ethernet/intel/e1000e/80003es2lan.h95
-rw-r--r--drivers/net/ethernet/intel/e1000e/hw.h1
3 files changed, 96 insertions, 63 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.c b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
index a00457abce69..e0991388664c 100644
--- a/drivers/net/ethernet/intel/e1000e/80003es2lan.c
+++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
@@ -32,69 +32,6 @@
32 32
33#include "e1000.h" 33#include "e1000.h"
34 34
35#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
36#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
37#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
38#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
39
40#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
41#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
42#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
43
44#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
45#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
46#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
47
48#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
49#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
50
51#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
52#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
53
54#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
55#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
56
57/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
58#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
59#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
60#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
61#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
62#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
63
64/* PHY Specific Control Register 2 (Page 0, Register 26) */
65#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
66 /* 1=Reverse Auto-Negotiation */
67
68/* MAC Specific Control Register (Page 2, Register 21) */
69/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
70#define GG82563_MSCR_TX_CLK_MASK 0x0007
71#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
72#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
73#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
74
75#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
76
77/* DSP Distance Register (Page 5, Register 26) */
78#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
79 1 = 50-80M
80 2 = 80-110M
81 3 = 110-140M
82 4 = >140M
83 */
84
85/* Kumeran Mode Control Register (Page 193, Register 16) */
86#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
87
88/* Max number of times Kumeran read/write should be validated */
89#define GG82563_MAX_KMRN_RETRY 0x5
90
91/* Power Management Control Register (Page 193, Register 20) */
92#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
93 /* 1=Enable SERDES Electrical Idle */
94
95/* In-Band Control Register (Page 194, Register 18) */
96#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
97
98/* A table for the GG82563 cable length where the range is defined 35/* A table for the GG82563 cable length where the range is defined
99 * with a lower bound at "index" and the upper bound at 36 * with a lower bound at "index" and the upper bound at
100 * "index + 5". 37 * "index + 5".
diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.h b/drivers/net/ethernet/intel/e1000e/80003es2lan.h
new file mode 100644
index 000000000000..90d363b2d280
--- /dev/null
+++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.h
@@ -0,0 +1,95 @@
1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000E_80003ES2LAN_H_
30#define _E1000E_80003ES2LAN_H_
31
32#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
33#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
34#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
35#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
36
37#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
38#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
39#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
40
41#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
42#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
43#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
44
45#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
46#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
47
48#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */
49#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
50
51#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
52#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
53
54/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
55#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */
56#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
57#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
58#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
59#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
60
61/* PHY Specific Control Register 2 (Page 0, Register 26) */
62#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */
63
64/* MAC Specific Control Register (Page 2, Register 21) */
65/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
66#define GG82563_MSCR_TX_CLK_MASK 0x0007
67#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
68#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
69#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
70
71#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
72
73/* DSP Distance Register (Page 5, Register 26)
74 * 0 = <50M
75 * 1 = 50-80M
76 * 2 = 80-100M
77 * 3 = 110-140M
78 * 4 = >140M
79 */
80#define GG82563_DSPD_CABLE_LENGTH 0x0007
81
82/* Kumeran Mode Control Register (Page 193, Register 16) */
83#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
84
85/* Max number of times Kumeran read/write should be validated */
86#define GG82563_MAX_KMRN_RETRY 0x5
87
88/* Power Management Control Register (Page 193, Register 20) */
89/* 1=Enable SERDES Electrical Idle */
90#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
91
92/* In-Band Control Register (Page 194, Register 18) */
93#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
94
95#endif
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index 6f94437d8c0e..8a145f468721 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -1003,5 +1003,6 @@ struct e1000_hw {
1003}; 1003};
1004 1004
1005#include "82571.h" 1005#include "82571.h"
1006#include "80003es2lan.h"
1006 1007
1007#endif 1008#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 16:16:09 -0400