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path: root/arch/mips/include/uapi/asm/inst.h
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* MIPS: inst.h: Rename cbcond{0,1}_op to pop{1,3}0_opPaul Burton2016-07-05
| | | | | | | | | | | | | The opcodes currently defined in inst.h as cbcond0_op & cbcond1_op are actually defined in the MIPS base instruction set manuals as pop10 & pop30 respectively. Rename them as such, for consistency with the documentation. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* MIPS: inst.h: Rename b{eq,ne}zcji[al]c_op to pop{6,7}6_opPaul Burton2016-07-05
| | | | | | | | | | | | | The opcodes currently defined in inst.h as beqzcjic_op & bnezcjialc_op are actually defined in the MIPS base instruction set manuals as pop66 & pop76 respectively. Rename them as such, for consistency with the documentation. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* MIPS: uasm: Add r6 MUL encodingJames Hogan2016-07-05
| | | | | | | | | | | Add the R6 MUL instruction encoding for 3 operand signed multiply to uasm so that KVM can use uasm for generating its entry point code at runtime on R6. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* MIPS: uasm: Add MTHI/MTLO instructionsJames Hogan2016-07-05
| | | | | | | | | | Add MTHI/MTLO instructions for writing to the hi & lo registers to uasm so that KVM can use uasm for generating its entry point code at runtime. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* MIPS: uasm: Add DI instructionJames Hogan2016-07-05
| | | | | | | | | | Add DI instruction for disabling interrupts to uasm so that KVM can use uasm for generating its entry point code at runtime. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* MIPS: uasm: Add CFCMSA/CTCMSA instructionsJames Hogan2016-07-05
| | | | | | | | | | | Add CFCMSA/CTCMSA instructions for accessing MSA control registers to uasm so that KVM can use uasm for generating its entry point code at runtime. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* MIPS: KVM: Convert emulation to use asm/inst.hJames Hogan2016-06-15
| | | | | | | | | | | | | | | Convert various MIPS KVM guest instruction emulation functions to decode instructions (and encode translations) using the union mips_instruction and related enumerations in asm/inst.h rather than #defines and hardcoded values. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* MIPS: inst: Declare fsel_op for sel.fmt instructionPaul Burton2016-05-13
| | | | | | | | | | | | | | Declare the opcode for the MIPSr6 sel.fmt instruction, as fsel_op in order to match other FP op names. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13152/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson-3: Fast TLB refill handlerHuacai Chen2016-05-13
| | | | | | | | | | | | | | | | | Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which can be used for fast TLB refill. [ralf@linux-mips.org: Resolve conflict.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move KVM specific opcodes into asm/inst.hJames Hogan2016-01-23
| | | | | | | | | | | | | | | | | | | The header arch/mips/kvm/opcode.h defines a few extra opcodes which aren't in arch/mips/include/uapi/asm/inst.h. There's nothing KVM specific about them, so lets move them into inst.h where they belong and delete the header. Note that mfmcz_op is renamed to mfmc0_op to match the instruction set manual, and wait_op was already added to inst.h in commit b0a3eae2b943 ("MIPS: inst.h: define COP0 wait op"), merged in v3.16-rc1. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11895/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: inst.h: Fix some instruction descriptionsMaciej W. Rozycki2016-01-23
| | | | | | | | | | | | | | | Fix the description of the microMIPS NOP16 encoding or MM_NOP16, which is not equivalent to the MIPS16 NOP instruction. This is 0x0c00 and represents the microMIPS `MOVE16 $0, $0' operation, whereas MIPS16 NOP is encoded as 0x6500, representing `MOVE $0, $16'. Also fix a typo in `mm_fp0_format' description. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12177/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Correct the emulation of microMIPS ADDIUPC instructionMaciej W. Rozycki2016-01-23
| | | | | | | | | | | | | | | Emulate the microMIPS ADDIUPC instruction directly in `mips_dsemul'. If executed in the emulation frame, this instruction produces an incorrect result, because the value of the PC there is not the same as where the instruction originated. Reshape code so as to handle all microMIPS cases together. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12175/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: inst.h: Add new MIPS R6 FPU opcodesMarkos Chandras2015-09-03
| | | | | | | | | Add opcodes for the new MIPS R6 FPU instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10952/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Declare MSA MI10 instruction formatsLeonid Yegoshin2015-09-03
| | | | | | | | | | | | | | Declare a struct describing the MSA MI10 instruction format used for ld & st instructions, for use by subsequent patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-kernel@vger.kernel.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10571/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructionsMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BEQZC and JIC instructionsMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BALC instructionMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructionsMarkos Chandras2015-02-17
| | | | | | | MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and BNEZLAC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructionsMarkos Chandras2015-02-17
| | | | | | | MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and BEQZALC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 branch compact (BC) instructionMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the BC1{EQ,NE}Z FPU instructionsMarkos Chandras2015-02-17
| | | | | | | | | MIPS R6 introduced the following two branch instructions for COP1: BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: mm: Add MIPS R6 instruction encodingsLeonid Yegoshin2015-02-16
| | | | | | | | MIPS R6 defines new opcodes for ll, sc, cache and pref instructions so we need to take these into consideration in the micro-assembler. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Add MFHC0 and MTHC0 instructions to uasm.Steven J. Hill2014-11-24
| | | | | | | | | New instructions for Extended Physical Addressing (XPA) functionality. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8453/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add SLT uasm instructionMarkos Chandras2014-06-26
| | | | | | | | | | It will be used later on by bpf-jit Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/7120/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add mflo uasm instructionMarkos Chandras2014-05-30
| | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: uasm: Add mul uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6736/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add wsbh uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6732/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add sltu uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6731/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add mfhi uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add divu uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Resolved conflict.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add srlv uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict due to other preceeding conflicts.] Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6726/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: uasm: Add sllv uasm instructionMarkos Chandras2014-05-30
| | | | | | | | | | | | It will be used later on by bpf-jit [ralf@linux-mips.org: Fixed conflict with 49e9529b9d43773307b8c73bd251b71784830c3d [MIPS: uasm: add jalr instruction]. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6725/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'wip-mips-pm' of https://github.com/paulburton/linux into ↵Ralf Baechle2014-05-29
|\ | | | | | | mips-for-linux-next
| * MIPS: inst.h: define microMIPS wait opPaul Burton2014-05-28
| | | | | | | | | | | | | | The opcode for the wait instruction within POOL32AXf was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: inst.h: define microMIPS sync opPaul Burton2014-05-28
| | | | | | | | | | | | | | The opcode for the sync instruction within POOL32AXf was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: inst.h: define MT yield opPaul Burton2014-05-28
| | | | | | | | | | | | | | The opcode for the MT ASE yield instruction within the spec3 group was missing. This patch adds it for use by a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: inst.h: define COP0 wait opPaul Burton2014-05-28
| | | | | | | | | | | | | | The func field for the wait instruction was missing from inst.h - this patch adds it. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | MIPS: Move definition of __BITFIELD_FIELD to sharable header.Ralf Baechle2014-05-21
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: inst.h: Rename BITFIELD_FIELD to __BITFIELD_FIELD.Ralf Baechle2014-05-12
|/ | | | | | | <uapi/asm/inst.h> is exported to userland so the macro name BITFIELD_FIELD pollutes the namespace. Prefix the name with __ fixes this. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch '3.14-fixes' into mips-for-linux-nextRalf Baechle2014-03-31
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| * MIPS: math-emu: Fix prefx detection and COP1X function field definitionDeng-Cheng Zhu2014-03-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running applications which contain the instruction "prefx" on FPU-less CPUs, a message "Illegal instruction" will be seen. This instruction is supposed to be ignored by the FPU emulator. However, its current detection and function field encoding are incorrect. This patch fix the issue. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Patchwork: https://patchwork.linux-mips.org/patch/6608/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: uapi: inst: Add instruction format for SPECIAL3 instructionsLeonid Yegoshin2014-03-26
| | | | | | | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* | MIPS: uapi: inst: Add new EVA opcodesLeonid Yegoshin2014-03-26
|/ | | | | Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: microMIPS: mfhc1 & mthc1 support for the FPU emulatorSteven J. Hill2014-01-13
| | | | | | | | | | | | | This patch adds support for microMIPS encodings of the mfhc1 & mthc1 instructions introduced in release 2 of the mips32 & mips64 architectures, converting them to their mips32 equivalents for the FPU emulator. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6110/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Add mfhc1 & mthc1 support.Leonid Yegoshin2014-01-13
| | | | | | | | | | | | | | | | This patch adds support for the mfhc1 & mthc1 instructions to the FPU emulator. These instructions were introduced in release 2 of the MIPS32 & MIPS64 architectures and allow access to the most significant 32 bits of a 64-bit FP register. [ralf@linux-mips.org: Fix ifdef hell added by original patch.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6112/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: microMIPS: Fix POOL16C minor opcode enumTony Wu2013-06-21
| | | | | | | | | | | | | As pointed out by Maciej, POOL16C minor opcodes were mostly shifted by one bit. Correct those opcodes, and also add jraddiusp to the enum. Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Acked-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: david.daney@cavium.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5527/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MIPS16e: Add instruction formats.Steven J. Hill2013-05-09
| | | | | | | Add structures for all the MIPS16e instructions. Also add the enumerations for all the bit fields for opcodes, functions, etc. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
* MIPS: microMIPS: Floating point support.Leonid Yegoshin2013-05-09
| | | | | | | Add logic needed to do floating point emulation in microMIPS mode. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Steven J. Hill <Steven. Hill@imgtec.com>
* MIPS: microMIPS: Add instruction formats.Steven J. Hill2013-05-01
| | | | | | | | | | | | | | Add structures for all the microMIPS instructions. Also add the enumerations for all the bit fields for opcodes, functions, etc. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Cc: kevink@paralogos.com Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/4921/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit d7f19e43a4337d4d40ff5e241172912130d06a4c)
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-01
| | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>