aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/marvell
Commit message (Collapse)AuthorAge
* arm64: dts: marvell: add unique identifiers for Armada A8k SPI controllersMarcin Wojtas2016-11-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling SPI controllers, which are attached to different busses inside an SoC, may result in overlapping enumeration and cause sysfs registration failure. Example log after enabling two controllers on Armada 8040 SoC with same identifiers: [ 3.740415] sysfs: cannot create duplicate filename '/class/spi_master/spi0' [ 3.747510] ------------[ cut here ]------------ [ 3.752145] WARNING: at fs/sysfs/dir.c:31 [...] [ 4.002299] orion_spi: probe of f4700600.spi failed with error -17 spi-orion driver offers dedicated DT property ('cell-index'), that allow setting unique identifiers. Recently added support for CP110-slave HW block introduced two new SPI controllers' nodes with same ID as ones from CP110-master. This commit fixes the issue by assigning different 'cell-index' values for CP110-slave SPI controllers. Fixes: 4eef78a0091b ("arm64: dts: marvell: add description for the slave CP110 in Armada 8K") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: fix clocksource for CP110 slave SPI0Marcin Wojtas2016-11-09
| | | | | | | | | | I2C and SPI interfaces share common clock trees within the CP110 HW block. It occurred that SPI0 interface has wrong clock assignment in the device tree, which is fixed in this commit to a proper value. Fixes: c749b8d9de32 ("arm64: dts: marvell: add description for the ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: Fix typo in label name on Armada 37xxGregory CLEMENT2016-11-09
| | | | | | | | The label names of the peripheral clocks have a typo. Fix it before it is more widely used. Reported-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* Merge tag 'mvebu-fixes-4.8-3' of git://git.infradead.org/linux-mvebu into fixesOlof Johansson2016-10-17
|\ | | | | | | | | | | | | | | | | | | | | | | | | mvebu fixes for 4.8 (part 3) - Select corediv clk for all mvebu v7 SoC - Fix clocksource for CP110 master SPI0 for Armada 7K/8K * tag 'mvebu-fixes-4.8-3' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: fix clocksource for CP110 master SPI0 ARM: mvebu: Select corediv clk for all mvebu v7 SoC Signed-off-by: Olof Johansson <olof@lixom.net>
| * arm64: dts: marvell: fix clocksource for CP110 master SPI0Marcin Wojtas2016-09-20
| | | | | | | | | | | | | | | | | | | | | | I2C and SPI interfaces share common clock trees within the CP110 HW block. It occurred that SPI0 interface has wrong clock assignment in the device tree, which is fixed in this commit to a proper value. Fixes: 728dacc7f4dd ("arm64: dts: marvell: initial DT description of ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> CC: <stable@vger.kernel.org> v4.7+ Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | Merge tag 'berlin64-dt-for-v4.9-1' of ↵Olof Johansson2016-10-03
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.infradead.org/users/hesselba/linux-berlin into next/dt64 Berlin64 DT changes for v4.9 - enable dw wdt nodes unconditionally, driver supports multiple instances now - switch to Cortex-A53 pmu compatible - add L2 cache topology * tag 'berlin64-dt-for-v4.9-1' of git://git.infradead.org/users/hesselba/linux-berlin: arm64: dts: berlin4ct: Add L2 cache topology arm64: dts: berlin4ct: enable all wdt nodes unconditionally arm64: dts: berlin4ct: switch to Cortex-A53 specific pmu nodes Signed-off-by: Olof Johansson <olof@lixom.net>
| * | arm64: dts: berlin4ct: Add L2 cache topologyJisheng Zhang2016-09-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the L2 cache topology for berlin4ct which has 1MB L2 cache. [Sebastian: rename cache node from "l2-cache" to "cache"] Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
| * | arm64: dts: berlin4ct: enable all wdt nodes unconditionallyJisheng Zhang2016-09-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | After commit f29a72c24ad4 ("watchdog: dw_wdt: Convert to use watchdog infrastructure"), the dw_wdt driver can support multiple variants, so unconditionally enable all dw_wdt nodes now. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
| * | arm64: dts: berlin4ct: switch to Cortex-A53 specific pmu nodesJisheng Zhang2016-09-28
| |/ | | | | | | | | | | | | | | | | Commit ac82d1277215 ("arm64: perf: add Cortex-A53 support") adds the cortex A53 PMU support, thus instead of using the generic armv8-pmuv3 compatibility use the more specific Cortex A53 compatibility. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* | Merge tag 'mvebu-dt64-4.9-2' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann2016-09-19
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/dt64 Pull "mvebu dt64 for 4.9 (part 2)" from Gregory CLEMENT: - enable MSI for PCIe on Armada 7K/8K * tag 'mvebu-dt64-4.9-2' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: enable MSI for PCIe on Armada 7K/8K
| * | arm64: dts: marvell: enable MSI for PCIe on Armada 7K/8KThomas Petazzoni2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a reference to the appropriate MSI controller in the description of the PCIe controllers on Marvel Armada 7K and 8K platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | | Merge branch 'dt/irq-fix' into next/dt64Arnd Bergmann2016-09-14
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | * dt/irq-fix: arm64: dts: Fix broken architected timer interrupt trigger This resolves a non-obvious conflict between a bugfix from v4.8 and a cleanup for the exynos7 platform.
| * | arm64: dts: Fix broken architected timer interrupt triggerMarc Zyngier2016-09-14
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | arm64: dts: marvell: describe the PIC and PMU on Armada 7K/8KThomas Petazzoni2016-08-26
| | | | | | | | | | | | | | | | | | This commit adds the necessary Device Tree description for the PIC interrupt controller and the PMU available in the Marvell Armada 7K and Armada 8K SoCs. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: add description for the Armada 8040 dev boardThomas Petazzoni2016-08-08
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a Device Tree description for the Marvell Armada 8040 Development Board. It features a quad-core Cortex A72 Armada 8040 SoC, with a large number of peripherals: dual Gigabit, dual 10 GBit, 6 PCIe interfaces, 6 SATA ports, 4 USB 3.0 ports, and more. Only a subset of the functionalities are supported so far, and additional features will be progressively enabled in the future. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: add description for the slave CP110 in Armada 8KThomas Petazzoni2016-08-08
|/ | | | | | | | | | | | | | The Armada 8K platforms (8020 and 8040) have two CP110 HW blocks: one master, one slave. So far, only the master CP110 was described. This commit adds the Device Tree description for the slave CP110, and hooks it up in the DT description of the Armada 8020 and Armada 8040 SoCs. The slave CP110 description is somewhat similar to the master CP110 description except for a number of things like register offsets, interrupt numbers, references to clocks, etc. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* Merge tag 'pci-v4.8-changes' of ↵Linus Torvalds2016-08-02
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Highlights: - ARM64 support for ACPI host bridges - new drivers for Axis ARTPEC-6 and Marvell Aardvark - new pci_alloc_irq_vectors() interface for MSI-X, MSI, legacy INTx - pci_resource_to_user() cleanup (more to come) Detailed summary: Enumeration: - Move ecam.h to linux/include/pci-ecam.h (Jayachandran C) - Add parent device field to ECAM struct pci_config_window (Jayachandran C) - Add generic MCFG table handling (Tomasz Nowicki) - Refactor pci_bus_assign_domain_nr() for CONFIG_PCI_DOMAINS_GENERIC (Tomasz Nowicki) - Factor DT-specific pci_bus_find_domain_nr() code out (Tomasz Nowicki) Resource management: - Add devm_request_pci_bus_resources() (Bjorn Helgaas) - Unify pci_resource_to_user() declarations (Bjorn Helgaas) - Implement pci_resource_to_user() with pcibios_resource_to_bus() (microblaze, powerpc, sparc) (Bjorn Helgaas) - Request host bridge window resources (designware, iproc, rcar, xgene, xilinx, xilinx-nwl) (Bjorn Helgaas) - Make PCI I/O space optional on ARM32 (Bjorn Helgaas) - Ignore write combining when mapping I/O port space (Bjorn Helgaas) - Claim bus resources on MIPS PCI_PROBE_ONLY set-ups (Bjorn Helgaas) - Remove unicore32 pci=firmware command line parameter handling (Bjorn Helgaas) - Support I/O resources when parsing host bridge resources (Jayachandran C) - Add helpers to request/release memory and I/O regions (Johannes Thumshirn) - Use pci_(request|release)_mem_regions (NVMe, lpfc, GenWQE, ethernet/intel, alx) (Johannes Thumshirn) - Extend pci=resource_alignment to specify device/vendor IDs (Koehrer Mathias (ETAS/ESW5)) - Add generic pci_bus_claim_resources() (Lorenzo Pieralisi) - Claim bus resources on ARM32 PCI_PROBE_ONLY set-ups (Lorenzo Pieralisi) - Remove ARM32 and ARM64 arch-specific pcibios_enable_device() (Lorenzo Pieralisi) - Add pci_unmap_iospace() to unmap I/O resources (Sinan Kaya) - Remove powerpc __pci_mmap_set_pgprot() (Yinghai Lu) PCI device hotplug: - Allow additional bus numbers for hotplug bridges (Keith Busch) - Ignore interrupts during D3cold (Lukas Wunner) Power management: - Enforce type casting for pci_power_t (Andy Shevchenko) - Don't clear d3cold_allowed for PCIe ports (Mika Westerberg) - Put PCIe ports into D3 during suspend (Mika Westerberg) - Power on bridges before scanning new devices (Mika Westerberg) - Runtime resume bridge before rescan (Mika Westerberg) - Add runtime PM support for PCIe ports (Mika Westerberg) - Remove redundant check of pcie_set_clkpm (Shawn Lin) Virtualization: - Add function 1 DMA alias quirk for Marvell 88SE9182 (Aaron Sierra) - Add DMA alias quirk for Adaptec 3805 (Alex Williamson) - Mark Atheros AR9485 and QCA9882 to avoid bus reset (Chris Blake) - Add ACS quirk for Solarflare SFC9220 (Edward Cree) MSI: - Fix PCI_MSI dependencies (Arnd Bergmann) - Add pci_msix_desc_addr() helper (Christoph Hellwig) - Switch msix_program_entries() to use pci_msix_desc_addr() (Christoph Hellwig) - Make the "entries" argument to pci_enable_msix() optional (Christoph Hellwig) - Provide sensible IRQ vector alloc/free routines (Christoph Hellwig) - Spread interrupt vectors in pci_alloc_irq_vectors() (Christoph Hellwig) Error Handling: - Bind DPC to Root Ports as well as Downstream Ports (Keith Busch) - Remove DPC tristate module option (Keith Busch) - Convert Downstream Port Containment driver to use devm_* functions (Mika Westerberg) Generic host bridge driver: - Select IRQ_DOMAIN (Arnd Bergmann) - Claim bus resources on PCI_PROBE_ONLY set-ups (Lorenzo Pieralisi) ACPI host bridge driver: - Add ARM64 acpi_pci_bus_find_domain_nr() (Tomasz Nowicki) - Add ARM64 ACPI support for legacy IRQs parsing and consolidation with DT code (Tomasz Nowicki) - Implement ARM64 AML accessors for PCI_Config region (Tomasz Nowicki) - Support ARM64 ACPI-based PCI host controller (Tomasz Nowicki) Altera host bridge driver: - Check link status before retrain link (Ley Foon Tan) - Poll for link up status after retraining the link (Ley Foon Tan) Axis ARTPEC-6 host bridge driver: - Add PCI_MSI_IRQ_DOMAIN dependency (Arnd Bergmann) - Add DT binding for Axis ARTPEC-6 PCIe controller (Niklas Cassel) - Add Axis ARTPEC-6 PCIe controller driver (Niklas Cassel) Intel VMD host bridge driver: - Use lock save/restore in interrupt enable path (Jon Derrick) - Select device dma ops to override (Keith Busch) - Initialize list item in IRQ disable (Keith Busch) - Use x86_vector_domain as parent domain (Keith Busch) - Separate MSI and MSI-X vector sharing (Keith Busch) Marvell Aardvark host bridge driver: - Add DT binding for the Aardvark PCIe controller (Thomas Petazzoni) - Add Aardvark PCI host controller driver (Thomas Petazzoni) - Add Aardvark PCIe support for Armada 3700 (Thomas Petazzoni) Microsoft Hyper-V host bridge driver: - Fix interrupt cleanup path (Cathy Avery) - Don't leak buffer in hv_pci_onchannelcallback() (Vitaly Kuznetsov) - Handle all pending messages in hv_pci_onchannelcallback() (Vitaly Kuznetsov) NVIDIA Tegra host bridge driver: - Program PADS_REFCLK_CFG* always, not just on legacy SoCs (Stephen Warren) - Program PADS_REFCLK_CFG* registers with per-SoC values (Stephen Warren) - Use lower-case hex consistently for register definitions (Thierry Reding) - Use generic pci_remap_iospace() rather than ARM32-specific one (Thierry Reding) - Stop setting pcibios_min_mem (Thierry Reding) Renesas R-Car host bridge driver: - Drop gen2 dummy I/O port region (Bjorn Helgaas) TI DRA7xx host bridge driver: - Fix return value in case of error (Christophe JAILLET) Xilinx AXI host bridge driver: - Fix return value in case of error (Christophe JAILLET) Miscellaneous: - Make bus_attr_resource_alignment static (Ben Dooks) - Include <asm/dma.h> for isa_dma_bridge_buggy (Ben Dooks) - MAINTAINERS: Add file patterns for PCI device tree bindings (Geert Uytterhoeven) - Make host bridge drivers explicitly non-modular (Paul Gortmaker)" * tag 'pci-v4.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (125 commits) PCI: xgene: Make explicitly non-modular PCI: thunder-pem: Make explicitly non-modular PCI: thunder-ecam: Make explicitly non-modular PCI: tegra: Make explicitly non-modular PCI: rcar-gen2: Make explicitly non-modular PCI: rcar: Make explicitly non-modular PCI: mvebu: Make explicitly non-modular PCI: layerscape: Make explicitly non-modular PCI: keystone: Make explicitly non-modular PCI: hisi: Make explicitly non-modular PCI: generic: Make explicitly non-modular PCI: designware-plat: Make it explicitly non-modular PCI: artpec6: Make explicitly non-modular PCI: armada8k: Make explicitly non-modular PCI: artpec: Add PCI_MSI_IRQ_DOMAIN dependency PCI: Add ACS quirk for Solarflare SFC9220 arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700 PCI: aardvark: Add Aardvark PCI host controller driver dt-bindings: add DT binding for the Aardvark PCIe controller PCI: tegra: Program PADS_REFCLK_CFG* registers with per-SoC values ...
| * arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700Thomas Petazzoni2016-07-26
| | | | | | | | | | | | | | | | Add the SoC-level description of the PCIe controller found on the Marvell Armada 3700 and enable this PCIe controller on the development board for this SoC. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | arm64: dts: marvell: add peripherals clocks for Armada 37xxGregory CLEMENT2016-07-04
| | | | | | | | | | | | | | Add two new blocks of clocks. The peripheral clocks are the source clocks of the peripheral of the Armada 3700 SoC. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: add tbg clocks for Armada 37xxGregory CLEMENT2016-07-04
| | | | | | | | | | | | | | Add a new block of clocks. The Time Base Generators clocks can be the parent of the peripheral clocks. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: Add xtal clock support for Armada 3700Gregory CLEMENT2016-07-04
| | | | | | | | | | | | | | | | The configuration of the clock depend of the gpio latch. This information is stored in the gpio block registers. That's why the block is shared using a syscon node. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: add XOR engine description for Armada 7K/8K CPThomas Petazzoni2016-06-30
| | | | | | | | | | | | | | | | This commit adds the Device Tree description for the two XOR engines found in the CP part of the Armada 7K/8K SoC. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | arm64: dts: marvell: adjust to the latest mv-xor-v2 DT bindingThomas Petazzoni2016-06-30
|/ | | | | | | | | | | | | | | | As suggested by Rob Herring, we should: 1/ Use a SoC-specific compatible string in addition to the more generic one. 2/ The generic compatible string has been changed from "marvell,mv-xor-v2" to "marvell,xor-v2". We simply reflect the changes made to the Device Tree bindings to the relevant Marvell 7K/8K Device Tree files. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: add XOR node for Armada 3700 SoCGregory CLEMENT2016-04-29
| | | | | | | | Armada 3700 SoC comprise one dual-channel XOR engine and this patch adds its according representation. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: Use a SoC-specific compatible for xHCI on Armada37xxGregory CLEMENT2016-04-27
| | | | | | | | | | | Even if the Armada 37xx does not any specific setup, the device tree binding documentation requires to use a SoC-specific version corresponding to the platform first followed by the generic version. This patch introduce this new compatible string and updates the documentation accordingly. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: Rename armada-37xx USB nodeAndreas Färber2016-04-27
| | | | | | | | | No need to reflect the USB version in the node name. Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> [gregory.clement@free-electrons.com: drop Fixes tag as it is not a bug fix.]
* arm64: dts: marvell: Clean up armada-3720-dbAndreas Färber2016-04-27
| | | | | | | | | | | | Instead of duplicating the SoC's node hierarchy, including a bus node named "internal-regs", reference the actually desired nodes by label, like Berlin already does. Add labels where necessary. Drop an inconsistent white line while at it. Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> [gregory.clement@free-electrons.com: drop Fixes tag as it is not a bug fix.]
* arm64: dts: marvell: enable several CP interfaces on Armada 7040-DBThomas Petazzoni2016-04-26
| | | | | | | | | | | | | | This commit enables several interfaces of the CP side of the Armada 7040 for the Armada 7040 DB board: - one PCIe interface - one SPI controller with an attached SPI flash - one I2C controller - one SATA controller - two USB3 controllers Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: initial DT description of Armada 7K/8K CP110 masterThomas Petazzoni2016-04-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds an initial Device Tree description for the CP110 master that is found in the Armada 7K and 8K SoCs. This initial description describes: - the system controller (to provide clocks) - three PCIe interfaces - the SATA interface - the I2C controllers - the SPI controllers For the record, the organization of the SoCs is as follows: - 7020: dual-core AP, one CP110 (master) - 7040: quad-core AP, one CP110 (master) - 8020: dual-core AP, two CP110s (master and slave) - 8040: quad-core AP, two CP110s (master and slave) For this reason, all of the 7020, 7040, 8020 and 8040 include armada-cp110-master.dtsi. When support for the second CP110 (slave) used in 8020 and 8040 will be added, the .dtsi files for those SoCs will in addition include armada-cp110-slave.dtsi. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: use the proper I2C controller compatible string for 7K/8KThomas Petazzoni2016-04-26
| | | | | | | | | The I2C controller found in the Marvell Armada 7K/8K provides the bridge/offloading features, so the Device Tree should use the marvell,mv78230-i2c compatible string instead of marvell,mv64xxx-i2c. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: improve SPI flash description on Armada 7040-DBThomas Petazzoni2016-04-26
| | | | | | | | | | | | | | | | | This commit slightly improves the description of the SPI flash connected to the SPI controller of the Armada 7040, by: - Using the more generic "jedec,spi-nor" compatible string, which lets the driver auto-detect the exact SPI flash type. - Removing the silly comment about the Chip Select, since reg = <0> is explicit enough. - Switching to the new Device Tree binding to describe flash partitions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: use new clock binding on Armada AP806Thomas Petazzoni2016-04-26
| | | | | | | | This commit updates the Marvell AP806 Device Tree description to make use of the accepted clock Device Tree binding. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: add UART aliases and define stdout-pathThomas Petazzoni2016-04-26
| | | | | | | | | | This commit adds the necessary UART aliases to the main Armada 7K/8K .dtsi file, and uses them to define the /chosen/stdout-path property on the Armada 7040 DB board. Suggested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: rename armada-ap806 XOR nodesAndreas Färber2016-04-26
| | | | | | | | | | | | | | | Node names should not contain an instance number, the unit address serves to distinguish nodes of the same name. So rename the XOR nodes to just xor@<address>. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andreas Färber <afaerber@suse.de> [Thomas: - remove labels, they are really not needed for XOR engines. - remove the Fixes: tag, as this is not a fix.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: clean up armada-7040-dbAndreas Färber2016-04-26
| | | | | | | | | | | | | | Instead of duplicating the node hierarchy, reference the nodes by label, adding labels where necessary. Drop some trailing or inconsistent white lines while at it. Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Andreas Färber <afaerber@suse.de> [Thomas: drop Fixes tag as it is not a bug fix.] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: re-order Device Tree nodes for Armada AP806Thomas Petazzoni2016-02-26
| | | | | | | | | | The DT nodes representing the XOR engines were not placed at the proper location to comply with the requirement of ordering DT nodes by their unit address. This commit fixes this mistake. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: update Armada AP806 clock descriptionThomas Petazzoni2016-02-26
| | | | | | | | | | | | Following the review from the DT maintainers, the DT binding for the clocks has changed, and we now use a DFX server node exposing a syscon, with the clock nodes being subnodes of the DFX server node. This commit therefore updates the AP806 Device Tree file to use this new DT binding. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: marvell: add Device Tree files for Armada 7K/8KThomas Petazzoni2016-02-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds the base Device Tree files for the Armada 7K and 8K SoCs, as well as the Armada 8040 DB board. The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are composed of: - An AP806 block that contains the CPU core and a few basic peripherals. The AP806 is available in dual core configurations (used in 7020 and 8020) and quad core configurations (used in 8020 and 8040). - One or two CP110 blocks that contain all the high-speed interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110, and the 8K family chips have two CP110, giving them twice the number of HW interfaces. In order to represent this from a Device Tree point of view, this commit creates the following hierarchy: * armada-ap806.dtsi - definitions common to dual/quad ap806 * armada-ap806-dual.dtsi - description of the two CPUs * armada-7020.dtsi - description of the 7020 SoC * armada-8020.dtsi - description of the 8020 SoC * armada-ap806-quad.dtsi - description of the four CPUs * armada-7040.dtsi - description of the 7040 SoC * armada-7040-db.dts - description of the 7040 board * armada-8040.dtsi - description of the 8040 SoC The CP110 blocks are not described yet, and will be part of future patch series. [gregory.clement@free-electrons.com: Fix commit title by adding ' dts:'] Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: add the Marvell Armada 3700 family and a development boardGregory CLEMENT2016-02-17
| | | | | | | | | | Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53 CPUs. There are two members in this family: the Armada 3710 (Single CPU) and the Armada 3720 (Dual CPUs). It also adds a dts file for the Marvell Armada 3720 DB board. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* arm64: dts: berlin4ct: support cpuidle-dtJisheng Zhang2015-12-06
| | | | | | | | | | This patch adds an idle-states node to describe the berlin4ct idle states and also adds references to the idle-states node in all CPU nodes. After this patch cpuidle is enabled. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* arm64: dts: berlin: PSCI-1.0 supportJisheng Zhang2015-11-28
| | | | | | | | The firmware can support PSCI-1.0 in fact. This change also enables suspend to ram on Marvell berlin arm64 SoC. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* arm64: dts: berlin4ct: add watchdog nodesJisheng Zhang2015-11-28
| | | | | | | | | The Marvell Berlin BG4CT has 3 watchdogs which are compatible with the snps,dw-wdt driver sit in the sysmgr domain. This patch adds the corresponding device tree nodes. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* arm64: dts: berlin4ct: add default pinmux for uart0Jisheng Zhang2015-11-19
| | | | | | | | | | | Add urt0 txd and rxd muxing setup in the dtsi because uart0 always uses them to work, no other possibilities. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* arm64: dts: berlin4ct: add the pinctrl nodeJisheng Zhang2015-11-19
| | | | | | | | | | Add the avio, soc, sm pinctrl nodes for Marvell berlin4ct SoC. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* arm64: dts: add dts file for Marvell Berlin4CT STB boardJisheng Zhang2015-09-20
| | | | | | | | | This patch adds dts for the Berlin4CT STB reference board which is also based on the Berlin4CT SoC. The Berlin4CT DMP board will be deprecated as time goes. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* arm64: dts: berlin4ct: add GPIO nodesJisheng Zhang2015-09-20
| | | | | | | | Marvell berlin4ct SoC has 6 GPIO ports powered by snps,dw-apb-gpio. This patch adds the corresponding device tree nodes. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* arm64: dts: Add dts files for Marvell Berlin4CT SoCJisheng Zhang2015-08-03
Add initial dtsi file to support Marvell Berlin4CT SoC with quad Cortex-A53 CPUs. It also adds dts file for Marvell Berlin4CT DMP board which is based on Berlin4CT SoC. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-14 19:31:47 -0400