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* arm64: dts: hi6220: Reset the mmc hostsDaniel Lezcano2017-05-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 0fbdf9953b41c28845fe8d05007ff09634ee3000 upstream. The MMC hosts could be left in an unconsistent or uninitialized state from the firmware. Instead of assuming, the firmware did the right things, let's reset the host controllers. This change fixes a bug when the mmc2/sdio is initialized leading to a hung task: [ 242.704294] INFO: task kworker/7:1:675 blocked for more than 120 seconds. [ 242.711129] Not tainted 4.9.0-rc8-00017-gcf0251f #3 [ 242.716571] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 242.724435] kworker/7:1 D 0 675 2 0x00000000 [ 242.729973] Workqueue: events_freezable mmc_rescan [ 242.734796] Call trace: [ 242.737269] [<ffff00000808611c>] __switch_to+0xa8/0xb4 [ 242.742437] [<ffff000008d07c04>] __schedule+0x1c0/0x67c [ 242.747689] [<ffff000008d08254>] schedule+0x40/0xa0 [ 242.752594] [<ffff000008d0b284>] schedule_timeout+0x1c4/0x35c [ 242.758366] [<ffff000008d08e38>] wait_for_common+0xd0/0x15c [ 242.763964] [<ffff000008d09008>] wait_for_completion+0x28/0x34 [ 242.769825] [<ffff000008a1a9f4>] mmc_wait_for_req_done+0x40/0x124 [ 242.775949] [<ffff000008a1ab98>] mmc_wait_for_req+0xc0/0xf8 [ 242.781549] [<ffff000008a1ac3c>] mmc_wait_for_cmd+0x6c/0x84 [ 242.787149] [<ffff000008a26610>] mmc_io_rw_direct_host+0x9c/0x114 [ 242.793270] [<ffff000008a26aa0>] sdio_reset+0x34/0x7c [ 242.798347] [<ffff000008a1d46c>] mmc_rescan+0x2fc/0x360 [ ... ] Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* arm64: dts: r8a7795: Mark EthernetAVB device node disabledGeert Uytterhoeven2017-05-14
| | | | | | | | | | | | | commit 0d1390ff283f6c38595288e7f74da6829896b8b7 upstream. Device nodes representing I/O devices should be marked disabled in the SoC-specific DTS, and overridden by board-specific DTSes where needed. Fixes: a92843c8a6f8c039 ("arm64: dts: r8a7795: add EthernetAVB device node") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* arm64: dts: hisi: fix hip06 sas am-max-trans quirkJohn Garry2017-04-12
| | | | | | | | | | | | | [ Upstream commit f65e786604b34d0b599b8c01ecca28be2d746290 ] The string for the am max transmissions quirk property is not correct -> fix it. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Sasha Levin <alexander.levin@verizon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM64: dts: bcm2835: Fix bcm2837 compatible stringAndreas Färber2017-01-15
| | | | | | | | | | | | | | commit 4f24450c6e580ac8591942c8bf65355a06b44635 upstream. bcm2837-rpi-3-b.dts, its only in-tree user, was overriding it as "brcm,bcm2837" already. Fixes: 9d56c22a7861 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.") Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LEDAndrea Merello2017-01-15
| | | | | | | | | | | | | | | | | commit a44e87b47148c6ee6b78509f47e6a15c0fae890a upstream. We are incorrectly defining the pwr LED, attaching it to a gpio line that is wired to the Wi-Fi SDIO module (which fails due to this). The actual power LED is connected to the GPIO expander, which we don't expose currently. Fixes: 9d56c22a7861 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.") Thanks-to: Eric Anholt <eric@anholt.net> [for clarifying we can't control the LED] Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* arm64: dts: mt8173: Fix auxadc nodeMatthias Brugger2017-01-15
| | | | | | | | | | | | | | | | | | commit a3207d644fb89e5d7d5e01f00c04dcfc6d2d44d5 upstream. The devicetree node for mt8173-auxadc lacks the clock and io-channel-cells property. This leads to a non-working driver. mt6577-auxadc 11001000.auxadc: failed to get auxadc clock mt6577-auxadc: probe of 11001000.auxadc failed with error -2 Fix these fields to get the device up and running. Fixes: 748c7d4de46a ("ARM64: dts: mt8173: Add thermal/auxadc device nodes") Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* arm64: dts: hip06: Correct hardware pin number of usb nodeKefeng Wang2017-01-12
| | | | | | | | | | | | commit 4d75a171b67ffc3f4dadbd654c9d281091300eb2 upstream. The ohci/ehci hardware pin number should be 640/641, correct them. Fixes: commit aa8d3e74f54d ("arm64: dts: Add initial dts for Hisilicon Hip06 D03 board") Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* arm64: tegra: Add VDD_GPU regulator to Jetson TX1Alexandre Courbot2017-01-09
| | | | | | | | | | | | | | | | | | commit 5e6b9a89afceadb1ee45472098f7d20af260335c upstream. Add the VDD_GPU regulator (a GPIO-enabled PWM regulator) to the Jetson TX1 board. This addition allows the GPU to be used provided the bootloader properly enabled the GPU node. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [as pointed out by Thierry on IRC, nobody has reported a bug in the field, but using a new bootloader with a .dtb that has the incorrect data, it will crash on boot] Fixes: 336f79c7b6d7 ("arm64: tegra: Add NVIDIA Jetson TX1 Developer Kit support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* arm64: dts: juno: fix cluster sleep state entry latency on all SoC versionsSudeep Holla2016-12-02
| | | | | | | | | | | | | | | | | The core and the cluster sleep state entry latencies can't be same as cluster sleep involves more work compared to core level e.g. shared cache maintenance. Experiments have shown on an average about 100us more latency for the cluster sleep state compared to the core level sleep. This patch fixes the entry latency for the cluster sleep state. Fixes: 28e10a8f3a03 ("arm64: dts: juno: Add idle-states to device tree") Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: "Jon Medhurst (Tixy)" <tixy@linaro.org> Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: dts: juno: Correct PCI IO windowJeremy Linton2016-11-30
| | | | | | | | | | The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'mvebu-fixes-4.9-1' of git://git.infradead.org/linux-mvebu into fixesOlof Johansson2016-11-17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mvebu fixes for 4.9 (part 1) All of them are fixes for arm64 device tree - 2 for the SPI node on the Armada 7K/8K - 1 for the clock node on the Armada 37xx * tag 'mvebu-fixes-4.9-1' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: add unique identifiers for Armada A8k SPI controllers arm64: dts: marvell: fix clocksource for CP110 slave SPI0 arm64: dts: marvell: Fix typo in label name on Armada 37xx Signed-off-by: Olof Johansson <olof@lixom.net>
| * arm64: dts: marvell: add unique identifiers for Armada A8k SPI controllersMarcin Wojtas2016-11-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling SPI controllers, which are attached to different busses inside an SoC, may result in overlapping enumeration and cause sysfs registration failure. Example log after enabling two controllers on Armada 8040 SoC with same identifiers: [ 3.740415] sysfs: cannot create duplicate filename '/class/spi_master/spi0' [ 3.747510] ------------[ cut here ]------------ [ 3.752145] WARNING: at fs/sysfs/dir.c:31 [...] [ 4.002299] orion_spi: probe of f4700600.spi failed with error -17 spi-orion driver offers dedicated DT property ('cell-index'), that allow setting unique identifiers. Recently added support for CP110-slave HW block introduced two new SPI controllers' nodes with same ID as ones from CP110-master. This commit fixes the issue by assigning different 'cell-index' values for CP110-slave SPI controllers. Fixes: 4eef78a0091b ("arm64: dts: marvell: add description for the slave CP110 in Armada 8K") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: fix clocksource for CP110 slave SPI0Marcin Wojtas2016-11-09
| | | | | | | | | | | | | | | | | | | | I2C and SPI interfaces share common clock trees within the CP110 HW block. It occurred that SPI0 interface has wrong clock assignment in the device tree, which is fixed in this commit to a proper value. Fixes: c749b8d9de32 ("arm64: dts: marvell: add description for the ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: Fix typo in label name on Armada 37xxGregory CLEMENT2016-11-09
| | | | | | | | | | | | | | | | The label names of the peripheral clocks have a typo. Fix it before it is more widely used. Reported-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | Merge tag 'pci-v4.9-fixes-3' of ↵Linus Torvalds2016-11-11
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: - Update MAINTAINERS for Intel VMD driver filename - Update Rockchip rk3399 host bridge driver DTS and resets - Fix ROM shadow problem that made some video device initialization fail * tag 'pci-v4.9-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: VMD: Update filename to reflect move arm64: dts: rockchip: add three new resets for rk3399 PCIe controller PCI: rockchip: Add three new resets as required properties PCI: Don't attempt to claim shadow copies of ROM
| * arm64: dts: rockchip: add three new resets for rk3399 PCIe controllerShawn Lin2016-11-10
| | | | | | | | | | | | | | | | | | pm_rst, aclk_rst and pclk_rst should be controlled by driver, so we need to add these three resets for PCIe controller. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'v4.9-rockchip-dts64-fixes1' of ↵Olof Johansson2016-10-29
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into fixes Correct regulator handling on Rockchip arm64 boards to make bind/unbind calls work correctly and remove a sdio-only property from non-sdio mmc hosts, that accidentially was added there. * tag 'v4.9-rockchip-dts64-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: remove the abuse of keep-power-in-suspend arm64: dts: rockchip: remove always-on and boot-on from vcc_sd Signed-off-by: Olof Johansson <olof@lixom.net>
| * | arm64: dts: rockchip: remove the abuse of keep-power-in-suspendShawn Lin2016-10-18
| | | | | | | | | | | | | | | | | | | | | | | | It was invented for sdio only, and should not be used for sdmmc or emmc. Remove it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | arm64: dts: rockchip: remove always-on and boot-on from vcc_sdShawn Lin2016-10-15
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Please don't add these for vcc_sd, and mmc-core/driver will control it. Otherwise, it will waste energy even without sdmmc in slot. Moreover, it will causes a bug: If we insert/remove sd card, we could see [9.337271] mmc0: new ultra high speed SDR25 SDHC card at address 0007 [9.345144] mmcblk0: mmc0:0007 SD32G 29.3 GiB This is okay for normal sd insert/remove test, but when I debug some issues for sdmmc, I did unbind/bind test. And there is a interesting phenomenon when we bind the driver again: [58.314069] mmc0: new high speed SDHC card at address 0007 [58.320282] mmcblk0: mmc0:0007 SD32G 29.3 GiB So the sd card could just support high speed without power cycle since the vcc_sd is always on, which makes the sd card fail to reinit its internal ocr mask. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'arm-soc/for-4.9/devicetree-arm64-fixes' of ↵Olof Johansson2016-10-29
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://github.com/Broadcom/stblinux into fixes This pull request contains a single fix for Broadcom ARM64-based SoCs: - Ray adds the required bus width and OOB sector size properties to the Northstar 2 SVK reference board in order for the NAND controller to work properly * tag 'arm-soc/for-4.9/devicetree-arm64-fixes' of http://github.com/Broadcom/stblinux: arm64: dts: Updated NAND DT properties for NS2 SVK Signed-off-by: Olof Johansson <olof@lixom.net>
| * | arm64: dts: Updated NAND DT properties for NS2 SVKRay Jui2016-10-23
| |/ | | | | | | | | | | | | | | | | This patch adds NAND DT properties for NS2 SVK to configure the bus width width and OOB sector size Signed-off-by: Prafulla Kota <prafulla.kota@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | Merge tag 'imx-fixes-4.9' of ↵Olof Johansson2016-10-29
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes The i.MX fixes for 4.9: - A couple of patches from Fabio to fix the GPC power domain regression which is caused by PM Domain core change 0159ec670763dd ("PM / Domains: Verify the PM domain is present when adding a provider"), and a related kernel crash seen with multi_v7_defconfig build. - Correct the PHY ID mask for AR8031 to match phy driver code. - Apply new added timer erratum A008585 for LS1043A and LS2080A SoC. - Correct vf610 global timer IRQ flag to avoid warning from gic driver after commit 992345a58e0c ("irqchip/gic: WARN if setting the interrupt type for a PPI fails"). * tag 'imx-fixes-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: mach-imx6q: Fix the PHY ID mask for AR8031 ARM: dts: vf610: fix IRQ flag of global timer ARM: imx: gpc: Fix the imx_gpc_genpd_init() error path ARM: imx: gpc: Initialize all power domains arm64: dts: Add timer erratum property for LS2080A and LS1043A Signed-off-by: Olof Johansson <olof@lixom.net>
| * | arm64: dts: Add timer erratum property for LS2080A and LS1043AScott Wood2016-10-21
| |/ | | | | | | | | | | | | | | | | Both the LS1043A and LS2080A platforms are affected by the Freescale A008585 erratum. Advertise it in their respective device trees. Signed-off-by: Scott Wood <oss@buserror.net> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | Merge tag 'uniphier-fixes-v4.9' of ↵Olof Johansson2016-10-29
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into fixes UniPhier ARM SoC fixes for v4.9 - Add "select ARCH_HAS_RESET_CONTROLLER" in Kconfig - Rename wrongly-named mioctrl to sdctrl * tag 'uniphier-fixes-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: change MIO node to SD control node ARM: dts: uniphier: change MIO node to SD control node reset: uniphier: rename MIO reset to SD reset for Pro5, PXs2, LD20 SoCs arm64: uniphier: select ARCH_HAS_RESET_CONTROLLER ARM: uniphier: select ARCH_HAS_RESET_CONTROLLER Signed-off-by: Olof Johansson <olof@lixom.net>
| * | arm64: dts: uniphier: change MIO node to SD control nodeMasahiro Yamada2016-10-22
| |/ | | | | | | | | | | | | I made a mistake bacuse the Media I/O block is not implemented in this SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge tag 'mvebu-fixes-4.8-3' of git://git.infradead.org/linux-mvebu into fixesOlof Johansson2016-10-17
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | mvebu fixes for 4.8 (part 3) - Select corediv clk for all mvebu v7 SoC - Fix clocksource for CP110 master SPI0 for Armada 7K/8K * tag 'mvebu-fixes-4.8-3' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: fix clocksource for CP110 master SPI0 ARM: mvebu: Select corediv clk for all mvebu v7 SoC Signed-off-by: Olof Johansson <olof@lixom.net>
| * arm64: dts: marvell: fix clocksource for CP110 master SPI0Marcin Wojtas2016-09-20
| | | | | | | | | | | | | | | | | | | | | | I2C and SPI interfaces share common clock trees within the CP110 HW block. It occurred that SPI0 interface has wrong clock assignment in the device tree, which is fixed in this commit to a proper value. Fixes: 728dacc7f4dd ("arm64: dts: marvell: initial DT description of ...") Signed-off-by: Marcin Wojtas <mw@semihalf.com> CC: <stable@vger.kernel.org> v4.7+ Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | Merge branch 'for-4.9' of ↵Linus Torvalds2016-10-14
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata Pull libata updates from Tejun Heo: - Write same support added - Minor ahci MSIX irq handling updates - Non-critical SCSI command translation fixes - Controller specific changes * 'for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: ahci: qoriq: Revert "ahci: qoriq: Disable NCQ on ls2080a SoC" libata: remove <asm-generic/libata-portmap.h> libata: remove unused definitions from <asm/libata-portmap.h> pata_at91: Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR ata: Replace BUG() with BUG_ON(). ata: sata_mv: Replacing dma_pool_alloc and memset with a single call dma_pool_zalloc. libata: Some drives failing on SCT Write Same ahci: use pci_alloc_irq_vectors libata: SCT Write Same handle ATA_DFLAG_PIO libata: SCT Write Same / DSM Trim libata: Add support for SCT Write Same libata: Safely overwrite attached page in WRITE SAME xlat ahci: also use a per-port lock for the multi-MSIX case ARM: dts: STiH407-family: Add ports-implemented property in sata nodes ahci: st: Add ports-implemented property in support ahci: qoriq: enable snoopable sata read and write ahci: qoriq: adjust sata parameter libata-scsi: fix MODE SELECT translation for Control mode page libata-scsi: use u8 array to store mode page copy
| * \ Merge branch 'master' into for-4.9Tejun Heo2016-09-06
| |\ \
| * | | ahci: qoriq: enable snoopable sata read and writeTang Yuantian2016-08-10
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | By default the SATA IP on the qoriq SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
* | | Merge branch 'next' of ↵Linus Torvalds2016-10-12
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux Pull thermal managament updates from Zhang Rui: - Enhance thermal "userspace" governor to export the reason when a thermal event is triggered and delivered to user space. From Srinivas Pandruvada - Introduce a single TSENS thermal driver for the different versions of the TSENS IP that exist, on different qcom msm/apq SoCs'. Support for msm8916, msm8960, msm8974 and msm8996 families is also added. From Rajendra Nayak - Introduce hardware-tracked trip points support to the device tree thermal sensor framework. The framework supports an arbitrary number of trip points. Whenever the current temperature is changed, the trip points immediately below and above the current temperature are found, driver callback is invoked to program the hardware to get notified when either of the two trip points are triggered. Hardware-tracked trip points support for rockchip thermal driver is also added at the same time. From Sascha Hauer, Caesar Wang - Introduce a new thermal driver, which enables TMU (Thermal Monitor Unit) on QorIQ platform. From Jia Hongtao - Introduce a new thermal driver for Maxim MAX77620. From Laxman Dewangan - Introduce a new thermal driver for Intel platforms using WhiskeyCove PMIC. From Bin Gao - Add mt2701 chip support to MTK thermal driver. From Dawei Chien - Enhance Tegra thermal driver to enable soctherm node and set "critical", "hot" trips, for Tegra124, Tegra132, Tegra210. From Wei Ni - Add resume support for tango thermal driver. From Marc Gonzalez - several small fixes and improvements for rockchip, qcom, imx, rcar, mtk thermal drivers and thermal core code. From Caesar Wang, Keerthy, Rocky Hao, Wei Yongjun, Peter Robinson, Bui Duc Phuc, Axel Lin, Hugh Kang * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: (48 commits) thermal: int3403: Process trip change notification thermal: int340x: New Interface to read trip and notify thermal: user_space gov: Add additional information in uevent thermal: Enhance thermal_zone_device_update for events arm64: tegra: set hot trips for Tegra210 arm64: tegra: set critical trips for Tegra210 arm64: tegra: add soctherm node for Tegra210 arm64: tegra: set hot trips for Tegra132 arm64: tegra: set critical trips for Tegra132 arm64: tegra: use tegra132-soctherm for Tegra132 arm: tegra: set hot trips for Tegra124 arm: tegra: set critical trips for Tegra124 thermal: tegra: add hw-throttle for Tegra132 thermal: tegra: add hw-throttle function of: Add bindings of hw throttle for Tegra soctherm thermal: mtk_thermal: Check return value of devm_thermal_zone_of_sensor_register thermal: Add Mediatek thermal driver for mt2701. dt-bindings: thermal: Add binding document for Mediatek thermal controller thermal: max77620: Add thermal driver for reporting junction temp thermal: max77620: Add DT binding doc for thermal driver ...
| * | | arm64: tegra: set hot trips for Tegra210Wei Ni2016-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
| * | | arm64: tegra: set critical trips for Tegra210Wei Ni2016-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra210, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
| * | | arm64: tegra: add soctherm node for Tegra210Wei Ni2016-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds soctherm node for Tegra210, and add cpu, gpu, mem, pllx as thermal-zones. Set critical trip temperatures for them. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
| * | | arm64: tegra: set hot trips for Tegra132Wei Ni2016-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable throttle function for SOC_THERM. Set "hot" trips for cpu and gpu thermal zones, which can trigger the SOC_THERM hardware throttle. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
| * | | arm64: tegra: set critical trips for Tegra132Wei Ni2016-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set general "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones on Tegra132, these trips can trigger shut down or reset. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
| * | | arm64: tegra: use tegra132-soctherm for Tegra132Wei Ni2016-09-27
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | The Tegra132 has the specific settings for soctherm, so change to use campatible "nvidia,tegra132-soctherm" for it. And adds cpu, gpu, mem and pllx thermal zones. Signed-off-by: Wei Ni <wni@nvidia.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
* | | Merge tag 'armsoc-late' of ↵Linus Torvalds2016-10-08
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "These updates have been kept in a separate branch mostly because they rely on updates to the respective clk drivers to keep the shared header files in sync. - The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an automotive SoC similar to the ⅹ8a7795 chip we already support, but the dts changes rely on a clock driver change that has been merged for v4.9 through the clk tree. - The Amlogic meson-gxbb (S905) platform gains support for a few drivers merged through our tree, in particular the network and usb driver changes are required and included here, and also the clk tree changes. - The Allwinner platforms have seen a large-scale change to their clk drivers and the dts file updates must come after that. This includes the newly added Nextthing GR8 platform, which is derived from sun5i/A13. - Some integrator (arm32) changes rely on clk driver changes. - A single patch for lpc32xx has no such dependency but wasn't added until just before the merge window" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) ARM: dts: lpc32xx: add device node for IRAM on-chip memory ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03 ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board ARM: dts: sun8i: add pinmux for UART1 at PG dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC dts: sun8i-h3: add pinmux definitions for I2C0-2 dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux dts: sun8i-h3: add pinmux definitions for UART2-3 ARM: dts: sun9i: a80-optimus: Disable EHCI1 ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04 ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03 ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes ...
| * \ \ Merge tag 'amlogic-dt64-2' of ↵Arnd Bergmann2016-09-19
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/late Pull "Amlogic 64-bit DT changes for v4.9, round 2" from Kevin Hilman: Primarily adding support for newly added drivers - USB host - I2C - SPI flash controller - PWM - mailbox, MHU - pinctrl: add pins for SPI, I2C, SDIO and then enabling these drivers on various boards. * tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes ARM64: dts: meson-gxbb-p20x: Enable USB Nodes ARM64: dts: meson-gxbb: add USB Nodes ARM64: dts: gxbb: add i2c bus ARM64: dts: meson-gxbb: add I2C nodes ARM64: dts: meson-gxbb: add pins for I2C ARM64: dts: meson-gxbb: Add SPIFC node ARM64: dts: meson-gxbb: add the SDIO pins ARM64: dts: amlogic: add spi nor pins ARM64: dts: meson-gxbb: use the new GXBB DWMAC glue driver ARM64: dts: meson-gxbb: Add Meson GXBB PWM Controller nodes ARM64: dts: meson-gxbb: Add Meson MHU Node ARM64: dts: amlogic: enable ethernet on all Tronsmart Vega S95 devices
| | * | | ARM64: dts: meson-gxbb-vega-s95: Enable USB NodesMartin Blumenstingl2016-09-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable both gxbb USB controller and add a 5V regulator for the OTG port VBUS Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb-p20x: Enable USB NodesJerome Brunet2016-09-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable both gxbb USB controller and add a 5V regulator for the OTG port VBUS Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [khilman: rename vbus node to match P200 schematics] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: add USB NodesMartin Blumenstingl2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the nodes for the dwc2 USB controller and the related USB PHYs. Currently we force usb0 to host mode because OTG is currently not working in our PHY driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: gxbb: add i2c busJerome Brunet2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add nodes for i2c bus on gxbb based platforms. On the OdroidC2 (I2C A) and P200 (I2C B), the pull-up resistor are present directly on the board. This indicates that these pins are dedicated to i2c. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: add I2C nodesNeil Armstrong2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: add pins for I2CJerome Brunet2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: Add SPIFC nodeNeil Armstrong2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: add the SDIO pinsNeil Armstrong2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is used to configure the pins of the sd_emmc_a controller to which an SDIO module is connected (when available). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: amlogic: add spi nor pinsJerome Brunet2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: use the new GXBB DWMAC glue driverMartin Blumenstingl2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Amlogic reference driver uses the "mc_val" devicetree property to configure the PRG_ETHERNET_ADDR0 register. Unfortunately it uses magic values for this configuration. According to the datasheet the PRG_ETHERNET_ADDR0 register is at address 0xc8834108. However, the reference driver uses 0xc8834540 instead. According to my tests, the value from the reference driver is correct. No changes are required to the board dts files because the only required configuration option is the phy-mode, which had to be configured correctly before as well. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
| | * | | ARM64: dts: meson-gxbb: Add Meson GXBB PWM Controller nodesNeil Armstrong2016-09-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jérôme Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-08 10:02:56 -0400