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* arm64: dts: Add timer erratum property for LS2080A and LS1043AScott Wood2016-10-21
| | | | | | | | | Both the LS1043A and LS2080A platforms are affected by the Freescale A008585 erratum. Advertise it in their respective device trees. Signed-off-by: Scott Wood <oss@buserror.net> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge branch 'for-4.9' of ↵Linus Torvalds2016-10-14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata Pull libata updates from Tejun Heo: - Write same support added - Minor ahci MSIX irq handling updates - Non-critical SCSI command translation fixes - Controller specific changes * 'for-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: ahci: qoriq: Revert "ahci: qoriq: Disable NCQ on ls2080a SoC" libata: remove <asm-generic/libata-portmap.h> libata: remove unused definitions from <asm/libata-portmap.h> pata_at91: Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR ata: Replace BUG() with BUG_ON(). ata: sata_mv: Replacing dma_pool_alloc and memset with a single call dma_pool_zalloc. libata: Some drives failing on SCT Write Same ahci: use pci_alloc_irq_vectors libata: SCT Write Same handle ATA_DFLAG_PIO libata: SCT Write Same / DSM Trim libata: Add support for SCT Write Same libata: Safely overwrite attached page in WRITE SAME xlat ahci: also use a per-port lock for the multi-MSIX case ARM: dts: STiH407-family: Add ports-implemented property in sata nodes ahci: st: Add ports-implemented property in support ahci: qoriq: enable snoopable sata read and write ahci: qoriq: adjust sata parameter libata-scsi: fix MODE SELECT translation for Control mode page libata-scsi: use u8 array to store mode page copy
| * ahci: qoriq: enable snoopable sata read and writeTang Yuantian2016-08-10
| | | | | | | | | | | | | | | | | | | | | | By default the SATA IP on the qoriq SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
* | Merge branch 'dt/irq-fix' into next/dt64Arnd Bergmann2016-09-14
|\ \ | | | | | | | | | | | | | | | | | | | | | * dt/irq-fix: arm64: dts: Fix broken architected timer interrupt trigger This resolves a non-obvious conflict between a bugfix from v4.8 and a cleanup for the exynos7 platform.
| * | arm64: dts: Fix broken architected timer interrupt triggerMarc Zyngier2016-09-14
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | arm64: dts: ls2080a: Add 'dma-coherent' for ls2080a PCI nodesLiu Gang2016-09-09
| | | | | | | | | | | | | | | | | | | | | | | | | | The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls2080a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | arm64: dts: add stdout-path to chosen node for ls2080a/ls1043a boardsStuart Yoder2016-08-30
| | | | | | | | | | | | | | | | Add a default stdout-path to chosen node for ls2080a/ls1043a boards to allow booting kernels without specifying console info in bootargs. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | arm64: dts: updates serial aliases for ls1043a rdb and qds boardsStuart Yoder2016-08-30
| | | | | | | | | | | | | | | | | | -add missing serial aliases to ls1043a-rdb -update ls1043a-qds boards serial aliases to use the standard duarts instead of low power uarts Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | arm64: dts: Add DDR memory controller for Layerscape SoCsYork Sun2016-08-30
|/ | | | | | | Add DDR memory controller nodes to enable EDAC driver. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge tag 'armsoc-dt64' of ↵Linus Torvalds2016-08-01
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull 64-bit ARM DT updates from Olof Johansson: "Just as the 32-bit contents, the 64-bit device tree branch also contains a number of additions this release cycle. New platforms: - LG LG1313 - Mediatek MT6755 - Renesas r8a7796 - Broadcom 2837 Other platforms with larger updates are: - Nvidia X1 platforms (USB 3.0, regulators, display subsystem) - Mediatek MT8173 (display subsystem added) - Rockchip RK3399 (a lot of new peripherals) - ARM Juno reference implementation (SCPI power domains, coresight, thermal)" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (118 commits) arm64: tegra: Enable HDMI on Jetson TX1 arm64: tegra: Add sor1_src clock arm64: tegra: Add XUSB powergates on Tegra210 arm64: tegra: Add DPAUX pinctrl bindings arm64: tegra: Add ACONNECT bus node for Tegra210 arm64: tegra: Add audio powergate node for Tegra210 arm64: tegra: Add regulators for Tegra210 Smaug arm64: tegra: Correct Tegra210 XUSB mailbox interrupt arm64: tegra: Enable XUSB controller on Jetson TX1 arm64: tegra: Enable debug serial on Jetson TX1 arm64: tegra: Add Tegra210 XUSB controller arm64: tegra: Add Tegra210 XUSB pad controller arm64: tegra: Add DSI panel on Jetson TX1 arm64: tegra: p2597: Add SDMMC power supplies arm64: tegra: Add PMIC support on Jetson TX1 Revert "ARM64: DTS: meson-gxbb: switch ethernet to real clock" arm64: dts: hi6220: Add pl031 RTC support arm64: dts: r8a7796/salvator-x: Enable watchdog timer arm64: dts: r8a7796: Add RWDT node arm64: dts: r8a7796: Use SYSC "always-on" PM Domain ...
| * arm64: dts: ls2080a: Add cache nodes for cacheinfo supportLi Yang2016-06-21
| | | | | | | | | | | | | | | | Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * arm64: dts: ls1043a: Add cache nodes for cacheinfo supportLi Yang2016-06-21
| | | | | | | | | | | | | | | | Adds the cache nodes and next-level-cache property for the cacheinfo to work. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodesLiu Gang2016-06-15
| | | | | | | | | | | | | | | | | | | | | | | | | | The 'dma-coherent' indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. The PCI IP block of ls1043a has this capability, so adding this feature to improve the PCI performance. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 nodeRajesh Bhagat2016-06-11
| | | | | | | | | | | | | | | | Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 nodeRajesh Bhagat2016-06-11
| | | | | | | | | | | | | | | | Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property is used to disable rx detection in P3 PHY mode. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * arm64: dts: fsl: Update address-cells and reg properties of cpu nodesAlison Wang2016-06-08
| | | | | | | | | | | | | | | | | | | | MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1, since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update the #address-cells and reg properties accordingly. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | arm64: dts: ls1043a: add crypto nodeHoria Geantă2016-06-07
|/ | | | | | | | | LS1043A has a SEC v5.4 security engine. For now don't add rtic or sec_mon subnodes, since these features haven't been tested yet. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* arm64: dts: ls2080a: fsl-mc dt node updatesStuart Yoder2016-04-25
| | | | | | | | | | updates to the fsl-mc node for full functionality: -msi-parent is needed for interrupt support -ranges is needed to enable the bus driver to translate bus addresses -dpmac nodes provide a basis for relating dpmac objects to PHYs Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: ls1043a: add the DTS node for QSPI supportYuan Yao2016-04-17
| | | | | Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: ls2080a: Add compatible "fsl,ls2080a-gpio" for ls2080a gpio nodesLiu Gang2016-04-13
| | | | | | | | | | | | | The compatible "fsl,qoriq-gpio" is used by gpio driver: drivers/gpio/gpio-mpc8xxx.c to implement general gpio functionalities. The chip-specific compatible "fsl,ls2080a-gpio" may be used to fix potential gpio IP block errata or other chip-specific gpio issues. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: ls1043a: Add compatible "fsl,qoriq-gpio" for ls1043a gpio nodesLiu Gang2016-04-13
| | | | | | | | | | | | | The compatible "fsl,qoriq-gpio" is used by gpio driver: drivers/gpio/gpio-mpc8xxx.c to implement general gpio functionalities. The chip-specific compatible "fsl,ls1043a-gpio" may be used to fix potential gpio IP block errata or other chip-specific gpio issues. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: ls2080a: update the DTS for QSPI and DSPI supportYuan Yao2016-04-12
| | | | | | Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: ls1043a-rdb: add the DTS for DSPI supportYunhui Cui2016-04-12
| | | | | | | | This patch adds dts nodes for DSPI on LS1043A-RDB. Signed-off-by: Yunhui Cui <B56489@freescale.com> Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* arm64: dts: add LS1043a-QDS board supportShaohui Xie2016-03-30
| | | | | | | | | | | | The LS1043a-QDS board is a high-performance computing, evaluation, development, and test platform supporting the LS1043a SoC. shawn.guo: sort the entries in Makefile alphabetcially Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* Merge tag 'armsoc-dt64' of ↵Linus Torvalds2016-03-20
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Arnd Bergmann: "The arm64 device tree changes make up an increasing portion of the overall changes, so they are kept separate from the 32-bit devicetree changes and from the other arm64 updates. Newly added SoCs and boards are: - 96Boards Husky board - AMD Overdrive board - Amlogic S905 SoC and related Tronsmart boxes - Annapurna Labs Alpine family and development board - Broadcom Vulcan servers - Broadcom Northstar 2 SoC - Marvell Armada 3700 family and development board - Qualcomm MSM8996 SoC Additional devices are enabled for existing platforms from Applied Micro, Hisilicon, Mediatek, Qualcomm, and Renesas and there are a couple of other updates for Rockchip, Xilinx and NXP/Freescale" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (102 commits) ARM64: dts: amlogic: Add Tronsmart Vega S95 configs Documentation: devicetree: amlogic: Document Tronsmart Vega S95 boards ARM64: dts: Prepare configs for Amlogic Meson GXBaby Documentation: devicetree: amlogic: Document Meson GXBaby devicetree: bindings: Add vendor prefix for Tronsmart arm64: dts: qcom: Fix MPP's function used for LED control arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi arm64: dts: add the Alpine v2 EVP arm64: dts: marvell: re-order Device Tree nodes for Armada AP806 arm64: dts: marvell: update Armada AP806 clock description arm64: dts: marvell: add Device Tree files for Armada 7K/8K arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform. arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver arm64: dts: apm: mailbox device tree node for APM X-Gene platform. arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2 arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2 ...
| * arm64: dts: ls1043a: Add quirk for Erratum A009116Rajesh Bhagat2016-02-14
| | | | | | | | | | | | | | | | | | Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum A009116. This property provides value of GFLADJ_30MHZ for post silicon frame length adjustment. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * arm64: dts: ls2080a: Add quirk for Erratum A009116Lijun Pan2016-02-14
| | | | | | | | | | | | | | | | | | | | Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum A009116. This property provides value of GFLADJ_30MHZ for post silicon frame length adjustment. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | dts/ls2080a: Update PCIe compatibleMinghuan Lian2016-02-24
|/ | | | | | | | | | The patch adds LS2085a to PCIe compatible to fix the compatibility issue when using firmware with LS2085a compatible property. Signed-off-by: Minghuan Lian <minghuan.lian@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* Merge tag 'armsoc-dt64' of ↵Linus Torvalds2016-01-20
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 64-bit DT updates from Olof Johansson: "This is the first release where we split up the 64-bit contributions a bit more, and in particular we are having a separate DT branch for them. Contents: - New devices added to Broadcom NorthStar2 - Misc fixes for Exynos7 boards - QCOM updates for MSM8916 - Rockchip tweaks for rk3368 SoC and eval board - A series of fixes for APM X-Gene v1 and v2 - Renesas R8A7795 CPU/PSCI additions - Marvell Berlin4CT PSCI, cpuidle, watchdog portions - Freescale LS1043a SoC and dev board support + some treewide or other misc changes" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits) dts/ls2080a: Update DTSI to add support of SP805 WDT Documentation: DT: Add entry for ARM SP805-WDT arm64: dts: X-Gene v2: I2C1 clock is always on arm64: dts: X-Gene v1: I2C0 clock is always on arm64: dts: Fix to use standard DT node names for X-Gene 1 and X-Gene 2 platforms arm64: dts: hikey: add label properties to UARTs arm64: dts: apq8016-sbc: add label properties for UART, I2C, and SPI arm64: dts: apq8016-sbc: enable UART0 on LS connector arm64: dts: juno: Add idle-states to device tree arm64: dts: Added syscon-reboot node for FSL's LS2080A SoC arm64: dts: add LS1043a-RDB board support arm64: dts: add Freescale LS1043a SoC support Documentation: DT: Add entry for Freescale LS1043a-RDB board arm64: dts: uniphier: add PH1-LD10 SoC/board support arm64: renesas: r8a7795: fix SATA clock assignment arm64: dts: salvator-x: Enable SATA controller arm64: dts: r8a7795: Add SATA controller node arm64: renesas: r8a7795: add internal delay for i2c IPs arm64: renesas: salvator-x: Add board part number to DT bindings arm64: dts: r8a7795: Add pmu device nodes ...
| * dts/ls2080a: Update DTSI to add support of SP805 WDTBhupesh Sharma2015-12-31
| | | | | | | | | | | | | | | | | | This patch updates the LS2080a DTSI (DTS Include) file to add support for eight SP805 Watchdog units which can be used to reset the eight Cortex-A57 cores available on LS2080A. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * arm64: dts: Added syscon-reboot node for FSL's LS2080A SoCJ. German Rivera2015-12-22
| | | | | | | | | | | | | | | | | | | | Added sys-reboot node to the FSL's LS2080A SoC DT to leverage the ARM-generic reboot mechanism for this SoC. This mechanism is enabled through CONFIG_POWER_RESET_SYSCON. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * arm64: dts: add LS1043a-RDB board supportShaohui Xie2015-12-22
| | | | | | | | | | | | | | | | | | Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * arm64: dts: add Freescale LS1043a SoC supportMingkai Hu2015-12-22
| | | | | | | | | | | | | | | | | | | | | | | | | | LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks are similar to LS1021a which also complies to Freescale Chassis 2.1 spec. Created LS1043a SoC DTSI file to be included by board level DTS files. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* | ls2080a/dts: Add little endian property for GPIO IP blockLiu Gang2015-12-11
| | | | | | | | | | | | | | | | | | | | The GPIO block for ls2080a platform has little endian registers, the GPIO driver needs this property to read/write registers by right interface. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
* | ARM64: dts: ls2080a: fix eSDHC endiannessyangbo lu2015-12-11
|/ | | | | | | | | | | Add the "little-endian" property to fix the issue that eSDHC is not working and dumping out "mmc0: Controller never released inhibit bit(s)." error messages constantly. Fixes: 5461597f6ce0 ("dts/ls2080a: Update DTSI to add support of various peripherals") Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
* dts/Makefile: Add build support for LS2080a QDS & RDB board DTSBhupesh Sharma2015-10-23
| | | | | | | | This patch adds build support for LS2080a QDS & RDB board DTS files in the arm64 DTS Makefile. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* dts/ls2080a: Add DTS support for LS2080a QDS & RDB boardsBhupesh Sharma2015-10-23
| | | | | | | | | This patch adds the LS2080a DTS files for QDS and RDB boards which support the LS2080a SoC. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* dts/ls2080a: Update Simulator DTS to add support of various peripheralsBhupesh Sharma2015-10-23
| | | | | | | | | | This patch updates the LS2080a simulator DTS to add support of various peripherals which are supported on the simulator platform and explicitly disables those which are yet not supported on the platform. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* dts/ls2080a: Remove text about writing to Free Software FoundationBhupesh Sharma2015-10-23
| | | | | | | | | | Checkpatch complains about the text suggesting writing to Free Software Foundation for GPLv2 license copy. This patch removes the same from the .dtsi and .dts Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* dts/ls2080a: Update DTSI to add support of various peripheralsBhupesh Sharma2015-10-23
| | | | | | | | | | | | | | | | | | | | | This patch updates the LS2080a DTSI (DTS Include) file to add support for the following peripherals: - USB 3.0 Host - PMU - CCN-504 - SATA - SPI - PCIe Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: Rename FSL LS2085A SoC support code to LS2080ABhupesh Sharma2015-10-23
| | | | | | | | Freescale is renaming the LS2085A SoC to LS2080A. This patch addresses the same. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: Use generic Layerscape SoC family namingBhupesh Sharma2015-10-23
| | | | | | | | | | | | Freescale will be a spinning-out a set of ARMv8 based SoCs which will be based on a similar overall SoC architecture. So, this patch converts the existing infrastructure in the arm64/dts, arm64/Kconfig and arm64/configs to use the generic convention ARCH_LAYERSCAPE in place of the more specific FSL_LS2085A, to save code duplication later-on. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* arm64: Add DTS support for FSL's LS2085A SoCBhupesh Sharma2015-01-27
This patch adds the device tree support for FSL LS2085A SoC based on ARMv8 architecture. Following levels of DTSI/DTS files have been created for the LS2085A SoC family: - fsl-ls2085a.dtsi: DTS-Include file for FSL LS2085A SoC. - fsl-ls2085a-simu.dts: DTS file for FSL LS2085a software simulator model. In addition, this patch adds build support for FSL's LS2085A simulator model in arm64 dts Makefile. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Arnab Basu <arnab_basu@rocketmail.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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