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path: root/drivers/pwm/pwm-tegra.c
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Diffstat (limited to 'drivers/pwm/pwm-tegra.c')
-rw-r--r--drivers/pwm/pwm-tegra.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 0a688dabd670..21518bea00c6 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -76,6 +76,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
76 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); 76 struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
77 unsigned long long c = duty_ns; 77 unsigned long long c = duty_ns;
78 unsigned long rate, hz; 78 unsigned long rate, hz;
79 unsigned long long ns100 = NSEC_PER_SEC;
79 u32 val = 0; 80 u32 val = 0;
80 int err; 81 int err;
81 82
@@ -94,9 +95,11 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
94 * cycles at the PWM clock rate will take period_ns nanoseconds. 95 * cycles at the PWM clock rate will take period_ns nanoseconds.
95 */ 96 */
96 rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH; 97 rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
97 hz = NSEC_PER_SEC / period_ns;
98 98
99 rate = (rate + (hz / 2)) / hz; 99 /* Consider precision in PWM_SCALE_WIDTH rate calculation */
100 ns100 *= 100;
101 hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
102 rate = DIV_ROUND_CLOSEST(rate * 100, hz);
100 103
101 /* 104 /*
102 * Since the actual PWM divider is the register's frequency divider 105 * Since the actual PWM divider is the register's frequency divider